id	author	title	date	pages	extension	mime	words	sentences	flesch	summary	cache	txt
29461	Digital Equipment Corporation	Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960			.txt	text/plain	10483	1015	71	single address, single instruction machine operating in parallel on 36 The address portion of the Memory Buffer Register communicates with the Index Adder, the Memory Address Register, and the Program instruction, thus, the address portion of the Memory Buffer is connected The Program Counter holds the memory location of the next instruction to The Instruction Register receives the first six bits of the Memory The six Sense Switches allow the operator to manually select program Buffer Register, the Arithmetic Element, and the Memory Addressing Operating times of PDP-3 instructions are normally multiples of the address an index register for memory-type instructions. is in the shift and rotate instructions in which the memory address the memory register containing the indirect address also has a 1 in bit Program Counter is indexed one extra position and the next instruction For each In-Out Transfer instruction, six lines of paper tape are read	./cache/29461.txt	./txt/29461.txt