id	author	title	date	pages	extension	mime	words	sentences	flesch	summary	cache	txt
en-wikipedia-org-2372		MIPS architecture - Wikipedia			.html	text/html	8775	1004	63	MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks,[6] MDMX (MaDMaX) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room,[7] and MIPS MT, which adds multithreading capability.[8] This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit (FPU) in a MIPS Iand II-compatible mode. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions' and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture.[24] It is supported by hardware and software development tools from MIPS Technologies and other providers. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor cores.	./cache/en-wikipedia-org-2372.html	./txt/en-wikipedia-org-2372.txt