DIGITAL SIGNAL PROCESSOR CONTROL ALGORITHM FOR PWM INVERTER A. A. Heggo ABSTRACT Recent developments in power electronic device technology promises faster switching capability at high power. The hybrid pulse width modulation method which requires two of the four switches in a full bridge inverter are used, and enable pulse pattern operation at high frequency. The use of two level switching instead of three level switching enables the use of higher frequency for given computation time delay. The proposed control scheme is implemented using bi-polar junction transistors (BJT) controlling an inverter t o produce a very low frequency (THD) sinusoidal output voltage. Simulation and experimental results are presented to verify the performance. 1 INTRODUCTION The 111 bridge inverter in Fig. (1) is widely employed in various applications such as motor drives and active filter [1][2]. The inverter comprises switching poles S1, S2, S3, S4, S5 and S6. The switching poles are commonly controlled by a variety of PWM techniques 131, and by pulse- shified square-wave drives [4]. Application of switching devices such as IGBT achieve very high switching frequency PWM inverters with improved performance [5]. With the availability of high frequency switching devices the instantaneous feedback control (IFC) was presented [6]. The advantages of this technique are high transient response and the disadvantage is that relatively large harmonic amplitudes occur for frequencies near the average switching frequency. By using a microprocessor, a digital feedback approach such as' a microprocessor deadbeat control was proposed [7][8]. The PWM inverter system is converted into a discrete time system and a state feedback output deadbeat control is applied. Manuscript received from Dr; A. A. Heggo on : 1111 111998 Accepted on: 13/6/1999 Engineering Research Bulletin, Vol 22,No 3, 1999 Minufiya University, Faculty of Engineering, Shebin El-Kom , Egypt, ISSN 11 10-1 180 Digital signal processor @SPs) are now applied for the control of power electionics and drive systems. DSPs are much faster (ten or one hundred times) than a microprocessor [9]. Simplification of control hardware and corresponding reduction of cost are the principal advantages ofDSP control [lo]. A digital controller was used to implement the control algorithm and provide switching signal t o the power circuit. The proposed control model is implemented using DSPs controlling an inverter to produce a very low'total harmonic distortion (THD) in sinusoidal output voltage. Fig. 1 - System description 2 CONTROL ALGORITHM A modified algorithm of the deadbeat controlled PWM inverter is suitable for stabilised power supply systems. Two levels are used in the pulse pattern. Given a computation time delay, twice the switching fi-equency can be adapted resulting in lower THD sinusoidal output. This work presents the deduction of a new discrete time state equation and the proposed deadbeat control algorithm for PWM inverters. Simulation results are obtained and presented. , 2.1 Deadbeat Control This technique depends upon the digital feedback closed loop. This means measuring of output, and controls the inverter switches to generate the required PWM pattern to produce a low THD sinusoidal output voltage. The digital control algorithm is designed to control pulse width such that the output voltage equals the sinusoidal reference at every sampling instant, Fig. (2). So the output voltage will be in phase and very close to sinusoidal reference. Any deviation of the output voltage from the reference due to a load disturbance or non- linear circuits is controlled within one sampling interval Ts. (a) Sampling Instant 1 2 3 4 5 Fig. 2 - Sampling Time The PWM pattern is determined at every sampling instant digitally by DSPs based on the output measurements and the references. 2.2 State Model Reference I error Vin Vout + Inverter Filter Load Digital AID Controller Converter Fig. 3 - Block Diagram of Digital Control Inverter As shown in Fig. (3) the deadbeat controller for PWM inverter is considered. The inverter, L C filter and resistive load represent the plant of closed loop digital feedback system. L '~ Load R v o u t Fig. 4 - State Model The circuit shown in Fig. (4) is modelled as a second-order system with state vector fli], where Vis load voltage and i is capacitor current. The state equation becomes: where: 2.3 Two Level scheme The basic circuit for the deadbeat controlled PWM inverter with a two level switching pattern is shown in Fig. (5). Positive half cycle Negative half cycle Fig. 5 - Two Level Deadbeat Controlled PWM Inverter Pattern The continuous time domain state ( I ) can be written as: i= A X + B U where: x = state vector u = scalar input A = non-singular matrix Then the closed form circuit is: where x(fJ is the initial state vector at t = to ifthe input u is constant for f , i t i t 1 then Eq.(4) becomes: using Eq.(5), the discrete-time system equation with the input is derived as follows: and by expansion the terms: AAT/2 AAT A ~ ( A T / ~ ) ~ e x ] + - + 2 2 e A T ~ l + A T + (AT )2 2 then Eq.(8) becomes: X/(K + I ) TI = eAT X(KI] - 2eATI2 BEAT + ( + A'z + (I I ) 2 6 where (K + I ) = t;, and KT = 1, this is a discrete-time system of Eq.(3) Rewriting Eq.(l 1) gives: where: f, is corresponding to element of eAT gi is corresponding to element of 2 e A T n ~ ~ hi is corresponding to element of (T + A f / 2 + A ~ / ~ ) B E V(K), i(X) and AT@) represent the values of voltage, the current and the sampling time: t = K T Therefore, by analysis of Eq.(l2) gives: 3 COMPUTER SIMULATION The following circuit parameters were used in computing the pulse width AT(K), and to obtain waveforms of voltage and current. Line Load Two level scheme THDIfimdamental 0.889l15.6 The simulation results are shown in Figs. (6), (7) and (8) 4 CONCLUSION A two deadbeat controller is used to minimise the total harmonic distribution of the digital inverter. This scheme will lead to the following advantages: - provide more computation time for the same interval switching number - provide a maximum voltage equal to the dc busbar voltage during each switching interval, Ei + E The obtained results show the waveforms of output voltages during various types of modulation. REFERENCES Hue, C., Two-Level Switching Pattern In Deadbeat DSP Controlled PWM Inverter, IEEE Translation of Power Electronic, Vol. 10, No. 3, May 1995. Goodnough, F., Mos Controlled thyristor turns off IMW in 2ms, Electron Design, November 1988. Gokhale, K. P., Kawamers, A,, and HoR, R. G., Deadbeat Microprocessor Control Of PWM For Sinusoidal Output Waveform Systems, IEEE Trans. Ind. Appliket, Vol. 1A23, No. 5, pp 901-909, September/October 1987. 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Heumann, K., Rapp, G. and Jung, M., Comparative Study Of New Power Transistor With Respect To High Frequency Inverter Application, EPE 89, 1989, pp 99-104. 6 NOMENCLATURE AT sampling time A, B matrix of state variable equation AID analogue / digital converter C filter capacitance DSP digital signal processor f output frequency I capacitor current K integer, positive number 0, 1,2,3 L filter inductive N no. of sampling PWM pulse width modulation R load resistance T interval time V load output voltage V;, input voltage (5- b) CURRENT WAVICI;ORhl Fig.6 The voltage and current waverorms under the "15 Pulse Modulation Mode" - Pul :e acSc Fig.7 The voltage and current waveforms under the "9 Pulse Modulation Mode" , , , . (8 - b ' C U R I < E N T \VAVI3FOllh] Fig.8 The voltage and current waveforms under the "5 Pulse Modulation Mode"