id	author	title	date	pages	extension	mime	words	sentences	flesch	summary	cache	txt
work_5mrw3qouhrez7dsxvmhhninjiy	Varsha Kakkara	A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study	2020	21	.pdf	application/pdf	6853	867	59	Integrated circuits may be vulnerable to hardware Trojan attacks during its design or Design of a Viterbi decoder and possible hardware Trojan models Keywords Coded communication system, Hardware Trojan, Viterbi decoder, Bit error rate and its hardware Trojan models: an FPGA-based implementation study. The work is concentrated toward RTL design of a Viterbi decoder and possible Trojans concept to a RTL level circuit design of the decoder and the Trojan activities. implementation of the Viterbi decoder is achieved and the Trojan effects on the system decoder performance, the decoder was fed with noisy data of different SNRs. Figure 14 shows the BERs obtained for the MATLAB behavioral model, the RTL design Effect of hardware trojans on the performance of a coded communication system. A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study	./cache/work_5mrw3qouhrez7dsxvmhhninjiy.pdf	./txt/work_5mrw3qouhrez7dsxvmhhninjiy.txt