ANALYSIS OF TRANSISTOR CLASS A OSCILLATOR 
 
 by 
 
 DAVID 
 
 -1 
 
 J. COMERJ 
 
 Technical Report 
 
 Submitted in partial satisfaction of the requirements for the degree of 
 
 MASTER OF SCIENCE 
 
 i n 
 Electrical Engineering 
 
 i n the 
 GRADUATE DIVISION 
 
 of the 
 UNIVERSITY OF CALIFORNIA 
 
 U. C. BERKOEY 
 UG LIBRARY 
 
 Approved: 
 
 ComnriTi ftee i n Charge 
 
 Degree conferred 
 
SUMMARY 
 
 A simple design procedure tor Class A small signal 
 
 123 
 oscillation has been outlined in the literature. 
 
 The procedure was verified by constructing a circuit 
 based on this theory and comparing actual results with 
 calculated results* An extension to large signal opera- 
 tion for maximum output power also appears in the same 
 literature* This theory was checked to see if modifica- 
 tion was necessary* It was found that a simple piece- 
 wise linear approximation to the emitter diode character- 
 istic, based on the small signal value of emitter diode 
 resistance, improves the design procedure and allows 
 efficient Class A operation to be realized* Maximum 
 available Class A output power was closely approached, 
 but not fully attained with the methods reported in 
 this paper* 
 
INTRODUCTION 
 
 Of the different methods of oscillator analysis and 
 design, one of the simplest and most general is that 
 
 based upon a study of the dynamic admittance appearing 
 
 1 2 
 at the output terminals of a two-port network* 
 
 The basic oscillator circuit is shown in Pig* 1 with 
 a transistor as the active device* 
 
 FEEDBACK 
 NETWORK 
 
 TRAN- 
 SISTOR 
 
 Fig* 1* Basic Oscillator Circuit 
 
 The output admittance that the network presents to 
 the load can be expressed as a function of the transistor 
 parameters and the feedback network parameters. This 
 admittance for sinusoidal oscillation can be expressed as 
 
 YG+jB . (1) 
 
 o o o 
 
 In order for oscillations to exist at a particular 
 frequency the output susceptance must be approximately zero 
 at that frequency, and the sum of the output conductance 
 
and the load conductance must be negative, i.e. 
 
 B O (2) 
 
 o 
 
 G_ + G ^ o ^ (3) 
 
 These conditions can be examined for any transistor 
 configuration v using the network parameters for that 
 particular configuration. Thus, this method of analysis 
 is quite general with respect to configuration. In this 
 paper, a common base configuration is examined using y- 
 parameters to define the network. 
 
 This method of analysis utilizes small signal para- 
 meters of the two-port network, to specify conditions for 
 1) marginal stability; 2) oscillation to the maximum pos- 
 sible frequency with a given load conductance; 3) maximum 
 loading at a given frequency* 
 
 The analysis can be extended to the design of large- 
 signal class A operation using small-signal linear theory 
 along with the assumption of idealized non-linearity of 
 emitter diode resistance, i.e. emitter resistance constant 
 for forward bias, and infinite for zero or reverse bias. 
 
 Research for this paper was done with the following 
 objectives: 1) to verify the design procedure for the 
 small signal case; 2) to examine the theory for extension 
 to large signal oscillation and, if necessary, to base a 
 modification of design procedure on experimental results. 
 
 SMALL SIGNAL THEORY 
 
 Since the y-parameters of a given transistor configu- 
 ration are specified at a given frequency and bias point, 
 the output admittance of the circuit of Fig. 2 is a function 
 of load susceptance and the feedback network parameters. 
 
Fig. 2. Oscillator Circuit 
 
 with Transformer Feedback 
 
 An ideal transformer is assumed as the feedback 
 element with a susceptance Z p in series with the input 
 terminal* This feedback network is a very basic form, 
 from which other feedback networks such as the tee or 
 pi can be derived. The output admittance presented to 
 the load can be expressed in terms of the transformer 
 
 turns ratio T, the susceptance B.,. and the y or h para- 
 
 r 
 
 meters* This output admittance (see Fig* 2) is 
 
 T) 
 
 (T - h !2> (h 21 
 
 22 
 
 or in terms of y parameters 
 
 l! <y 
 
 (y 21 - T/Z p ) 
 
 (5) 
 
 If the output admittance is expressed in terms of its real 
 and imaginary parts, it becomes 
 
 JB 
 
 n 
 
 (6) 
 
The real part of Y Q is differentiated with respect 
 to T and equated to zero, i,e. 
 
 x G 
 
 n * .......... (7) 
 
 ax 
 
 Solving Eq. 7 .for T gives the optimum turns ratio T . 
 
 o 
 
 2 2 
 
 T O ni + n * * . . (8) 
 
 2m 
 
 where m is the real part and n is the negative of the 
 imaginary part of the short circuit current gain* Sub- 
 stituting T into the equation for G , differentiating 
 with respect to the feedback susceptance, and equating 
 
 this derivative to zero gives the optimum value of & 
 
 r 
 
 Bp m * . . . ( 9 ) 
 nR 1 + 'mX-' 
 
 where H is the real and X? is the imaginary part of 
 h 1 _ and h.. = 1/y-,-.* Yp'^p^JBpt * he feedback admittance* 
 The optimum value of G is found from the above 
 
 values of B and T 
 r , o 
 
 21 * 12 )2 * (b 21 
 where g is the real part and b is the imaginary part 
 
 of " " 
 
 Eq* 1O gives the maximum load that can be ap- 
 plied to the oscillator at the design frequency* 
 
 The same theory can be used to specify T and B for 
 oscillation to the maximum frequency for a given load or 
 to design for marginal stability* 
 
 MAXIMUM OUTPUT POWER 
 
 After having designed the circuit for maximum load- 
 ing and applying the calculated maximum load, it is found 
 
that the output voltage and power in this load are 
 quite small since the load impedance is small. Therefore, 
 the assumption of small signal parameters is quite rea- 
 sonable. Experimentally, it is found that increasing 
 the load resistance increases the output power, but there 
 is no sudden build up of oscillations and the output power 
 is still very small* 
 
 In order to extend this design to large signal 
 operation, approaching maximum efficiency, the collector 
 voltage must saturate at the peak of one-half cycle and 
 the emitter current must cut off at the peak of the other 
 one-half cycle. It is assumed that the emitter diode 
 resistance is equal to its small signal value until the 
 current cuts off, at which point the resistance is 
 assumed infinite* The current passing through the load 
 conductance must cause a peak voltage equal to the col* 
 
 lector supply voltage V . Since the mean bias current 
 
 c 
 
 specifies the maximum collector current, the load con- 
 ductance must be adjusted to give the desired voltage 
 
 3 
 swing. With this value of G , the power dissipated is 
 
 P T "MVp - ffi* ...... (ID 
 
 ~2~~ 2 
 
 where (a) is the magnitude of alpha at design frequency; 
 
 R 1 is the real part of h _ , I is the emitter current. 
 
 JL x . e 
 
 The first term of Eq. 11 is the available A-C power 
 
 as the collector voltage swings over a range of O to V 
 
 c 
 
 and the collector current varies from to la I I The 
 
 I * C 
 
 second term is the power dissipated in the part of GL 
 which cancels the negative output conductance of the cir- 
 cuit, i.e. the power fed back to the input of the tran- 
 sistor* 
 
The ratio of these powers can be considered in order 
 
 to solve for the adjusted value of G T in terms of G to 
 
 JL 
 
 (12) 
 
 Since the output voltage is greatly increased, the 
 current that is fed back must be reduced to its original 
 value; therefore the turns ratio must be reduced* 
 
 value the turns ratio must be 
 
 T A 21 R T (13) 
 
 A O 
 
 FTT 
 
 where T is the turns ratio for maximum load conditions 
 o 
 
 and T. is the adjusted turns ratio* 
 
 Under the assumptions made in arriving at Eqs. (12) 
 and (13)* these adjusted values should give maximum power 
 output; but since large signal operation is now in effect, 
 rather than the assumed small signal operation, some 
 modification in parameters might give more accurate results* 
 It seems reasonable that the assumption of the emitter 
 diode exhibiting extreme non-linearities is unrealistic 
 and could be modified by using a more representative 
 piece-wise linear approximation, so allowing a more ac- 
 curate design procedure* 
 
 MEASUREMENT OF TRANSISTOR PARAMETERS 
 
 Since the parameters of the transistor play an im- 
 portant part in the analysis of the oscillator, accuracy 
 in measuring these parameters is essential* For this 
 reason, the parameters were measured by two different 
 methods and compared to check the accuracy of the mea- 
 surements* 
 
The first method of obtaining the transistor para- 
 meters utilized a Wayne Kerr admittance bridge* This 
 bridge was used to measure the y parameters at the design 
 frequency directly. 
 
 The second method was aimed at obtaining the equi- 
 valent circuit of the transistor by measurement of single 
 element values. The circuit of Pig. 3 shows the equi- 
 valent circuit of the uniform base transistor* 
 
 <X m - jn 
 
 e o 
 
 
 Fig. 3 Equivalent Circuit Representation 
 of Uniform Base Transistor. 
 
 c a is the diffusion capacitance. 
 
 r , is the diode resistance. 
 
 e 
 
 r, 4 is the extrinsic base resistance. 
 
 C is the collector depletion region capacitance, 
 
 c 
 
 a is the short circuit current gain from emitter 
 to collector. 
 
 The current gain as a function of frequency was 
 measured and in this way the magnitude and phase of a 
 at the design frequency was obtained* 
 
In order to obtain C. and r. , the common emitter 
 
 d b ' 
 
 configuration was used. The output was short circuited* 
 The input admittance was measured as the frequency was 
 varied from about f_ to f_. A low emitter current was 
 used in order to obtain a high resistance in shunt with 
 the diffusion capacitance* By neglecting this high 
 resistance (compared to the impedance of the diffusion 
 capacitance) the input admittance presented by the equi- 
 valent circuit of Fig* k can be expressed as 
 
 Y n = G + jB 
 
 o) 
 
 where C,_ C, + C ^ C_ , the base charging capacitance; 
 r , is the extrinsic base resistance; Cx) is the radian 
 frequency. 
 
 bb f b 
 
 'bte 
 
 Fig. 4 High Frequency Equivalent Circuit of 
 Transistor in Common Emitter Configuration for Low Emitter 
 
 Control 
 
Prom Eq. 14 the measured input capacitance is given 
 
 by 
 
 B 
 
 
 
 . (15) 
 
 and 
 
 . (16) 
 
 1 2 
 
 If - is plotted as a function of (J , a straight line 
 
 will result as in Fig. 5* 
 
 n :Tr 
 
 
 TO ft 
 
 Radian Frequency Squared - X 10 2 
 
 1000 
 
 Fig. 5. l/C vs 
 
 At the point where U) * 0, the value of l/ c in is 
 equal to 1/C... The slope of the line is equal to r ^t c ^ 
 Thus, this method gives both r fel and C^. The input capac- 
 itance was measured on the Wayne Kerr bridge. The emitter 
 
 diffusion capacitance C . in the common base configuration 
 
 4 d 
 
 is found from 
 
 ~ 2 C 
 
 - 5 c i 
 
 . (17) 
 
10 
 The only element of the equivalent circuit remain- 
 
 capacitance. This can be measured by the Wayne Kerr 
 bridge with the transistor in the common base configu- 
 ration* 
 
 Since r , is determined by the bias current, all 
 
 e 
 
 element values of the equivalent circuit of Fig. 3 have 
 now been determined. The equivalent circuit values can 
 also be derived from the y parameters. 
 
 Alpha is found from the following equation: 
 
 a = - y 21 . . . ...... /* (18) 
 
 The phase of a is considered in order to 
 
 Since r ,is known for the particular bias current C 
 
 e ' e 
 
 can be found from Eq. 19 
 
 CO /p B _ (19) 
 
 r e' C d M Jrt 
 
 The extrinsic base resistance r, . is found from 
 
 D ' 
 
 Eq. 20 
 
 r , Z e y 12 ..... . . (20) 
 
 b 
 
 y 22 * y !2 
 
 where Z is the parallel combination of r and C ,. 
 e e * d 
 
 The collector capacitance C is found from Eq. 21 
 
 c 
 
 C c = j y !2 (21) 
 
 CO^.YH 
 
 which holds for 1 
 
 (Sc 
 
 If the measured element values compare closely 
 with those values derived from the y parameters, the y 
 parameters can be assumed to have been measured accu- 
 rately. 
 
11 
 
 The equivalent circuit of the particular transistor 
 used in this experiment was obtained from the two dif- 
 ferent methods reported above. The agreement was close 
 enough to verify the accuracy of the measured values of 
 the y parameters which are reported below, along with other 
 pertinent data* 
 
 Transistor type IBM 075 
 Emitter current = 0.5ma 
 
 y = I.l4xl0~ 2 -j 
 
 -4 4 
 
 y 12 =-2. 04x10 -j 4.40x10" 
 
 2i' 
 
 y 22' 
 
 k 
 
 Element Values 
 
 Calculated 
 (from y parameters) 
 575pf 
 
 52 A 
 59^ 
 
 4. 35xlO~% j 6.28x10 
 Measured 
 
 4 
 " 
 
 VERIFICATION OF MAXIMUM INSTABILITY CASE 
 
 An oscillator was constructed based on the theory 
 for the case of maximum load at a given frequency. The 
 circuit is shown in Pig. 6 using the pi feedback network. 
 The equations used in obtaining the pi or tee network 
 from the transformer network are given in Sec. 1 of the 
 appendix. 
 
 Fig. 6 Oscillator Designed for Maximum Loading 
 l?6pf L = 5p,h-9vLh adjustable 
 
 a 246pf R b = 10,000 ohms 
 
12 
 
 The oscillator was designed to operate at 5MC/S. 
 The minimum load resistance was calculated to be 513 ohms 
 at this frequency. With an infinite JL or an open circuit 
 output, the circuit oscillated at 5.2 MC/S. The output 
 voltage was 1.3 volts peak to peak. As the circuit was 
 loaded the frequency approached 5 MC/S. Using a load 
 resistance of 510 ohms, the circuit oscillated at exactly 
 5 MC/S. Any increase of load conductance stopped the 
 oscillation completely. This value of conductance then 
 gives the maximum load that can be applied to the output 
 terminals without stopping the oscillations* 
 
 The power delivered to the load under these condi- 
 tions was quite small; the output voltage was only .05 
 volts peak to peak. 
 
 In order to increase the output power, the small 
 signal theory was extended to calculate new values for 
 the feedback network and the load conductance (Eqs. 12 
 and 13)* These calculations are found in Sec. 2 of the 
 appendix. 
 
 The revised values in the feedback network are as 
 follows: C. - 420pf, C- - 2.l6pf and L 3 20uh. The opti- 
 mum load resistance for maximum power output was calculated 
 to be 21,OOO ohms. 
 
 With these values in the circuit, the output voltage 
 was increased to a peak to peak value of 2 volts. Accord- 
 ing to the theory, this value should be the maximum output 
 voltage and thus deliver the maximum power to the load. 
 That this is not the case is seen in the graph of Fig. 7 
 where output power is plotted as a function of load re- 
 sistance* 
 
1 .040 
 
 o 
 
 0. 
 
 01 
 p 
 
 .020 
 
 Frequency constant at 5 MC/S 
 
 100 
 
 20 4O 60 80 
 Load Resistance - Kilohms 
 
 .' 
 
 Fig, ? Output Power vs Load Resistance for 
 Circuit Based on Small Signal Parameters 
 
 The power reaches a peak of .042 mw. when the load 
 resistance is approximately 36,OOO ohms* This peak power 
 is still far short of the .856 mw. that the oscillator is 
 capable of developing* 
 
 These results demonstrate that the theory used does 
 not predict the correct values to be used in the feedback 
 network* 
 
 The next step is to determine the procedure to be 
 used in order to make the peak of the power curve occur at 
 the calculated value of load resistance, i.e. 21,OOO ohms* 
 
 MODIFICATION OF DESIGN PROCEDURE TO OBTAIN MAXIMUM POWER OUTPUT 
 
 As the emitter current swings from its maximum value 
 to zero value, the emitter diode resistance increases from 
 a small value to a very large value* Since the current 
 that is fed back depends on the turns ratio which was cal- 
 culated on the basis of a constant, relatively small emitter 
 resistance, it could be expected that this current is not 
 
14 
 
 enough to achieve full output. Therefore, the turns ratio 
 should be increased in order to increase the feedback 
 current. 
 
 The turns ratio was increased experimentally by in- 
 creasing C 2 in the circuit of Pig. 6 , since for the small 
 turns ratio used, C is proportional to this ratio. The 
 load resistance used was that calculated to give maximum 
 output or 21,000 ohms. As C was increased, the tuning 
 inductance was decreased so that the oscillation fre- 
 quency remained constant at 5MC/S. The output voltage 
 increased with C_ until C- reached a certain value. As 
 C was increased further, the output voltage remained 
 
 jft 
 
 constant. That value of C which just gave maximum out* 
 put was chosen as the proper value. 
 
 The graph of Fig. 8 shows a plot of output voltage 
 vs turns ratio. 
 
 H 
 
 
 
 8.0 
 
 fl) p< 
 
 bO 
 
 03 O 
 
 ** v 4 o 
 
 H ** U 
 
 O 
 
 -P &4 
 
 I 
 
 O.O 
 
 . 4 '-L-UL ' I !_l_Uh -I- 
 r ! t i ! I 1 i ' 
 
 IT 
 
 2T, 
 
 3T, 
 
 A 
 -3 
 
 4x 5T 6T 
 
 A A ''A A A A 
 
 Turns Ratio - Calculated Value of T. 5.l4xlO~ 
 
 jriiciiLi iJ !-*ILJ 
 
 i Jx ill". LI D i T . m 
 Fig. 8. Output Voltage vs Turns Ratio. 
 
 In order to verify that the correct turns ratio had 
 now been obtained, the load resistance was then varied 
 and readings of output power taken. The results of this 
 
15 
 
 data are shown in the graph of Pig. 9. 
 .30 
 
 .20 
 
 .10 
 
 
 
 
 04 
 
 
 
 
 
 
 
 
 
 
 
 
 o 
 
 10 
 
 20 
 
 30 
 
 40 
 
 
 
 Load 
 
 Resistance 
 
 .! _i -. ' _j. .! -1- 1 j - 
 
 - Kilohms 
 
 _r i ! ,j u-j-H- 
 
 nitn 
 
 . _ -> 
 
 Fig. 9. Output Power vs Load Resistance for 
 Modified Turns Ratio. 
 
 The peak of the output power plotted against load 
 resistance now occurs at 21,000 ohms which was the cal- 
 culated optimum value. The new value of turns ratio 
 giving these conditions was found to be k times the value 
 calculated from eq. 13. 
 
 It should be noted that the output power is .2^4mw. 
 whereas the predicted value was . 856mw. This discrepancy 
 came about because the output voltage achieved only a 
 little over one-half of its maximum possible swing. 
 Changing the turns ratio appears to have improved two 
 aspects of circuit performance. First, the power output 
 is much greater than the value achieved before the turns 
 ratio was changed. Second, the power output, which varies 
 
17 
 
 The graph of Fig. 10 shows the emitter diode 
 characteristic of the transistor. A straight line is 
 drawn tangent to the curve at 0.5ma. The reciprocal 
 of the slope of this line gives the small signal value 
 of the diode resistance for a bias of 0.5ma. Also 
 drawn through the O.^ma point is the line whose slope 
 gives the piece-wise linear approximation of diode 
 conductance over the full current swing from to 
 1 ma. The slope of this line is equal to one fourth of 
 the slope of the first line, reflecting the fact that the 
 large signal value of r e iis approximately four times the 
 small signal value. 
 
 CQ 
 
 s 
 
 H 
 r-H 
 rH 
 H 
 
 E 
 I 
 
 p 
 
 o 
 
 O 
 
 -p 
 
 H 
 
 6 
 w 
 
 
 1.2 
 
 ! I .!.:!! : ! I i ' > *LJ_i ' ' ! i 
 
 0.8 
 
 0.4 
 
 0.0 
 
 ' 
 Slopes 1/r e 
 
 small signal 
 
 - 
 
 tfctfc 
 
 \^ 
 
 ^ 
 
 
 Slope= l/r e , 
 piece-wise linear 
 approximation over 
 full current swing 
 
 120 
 
 160 
 
 20O 
 
 Base-Emitter Voltage - millivolts 
 
 
 
 Fig. 1O. Emitter Diode Characteristic 
 
IS 
 ADJUSTING THE PHASE OF THE FEEDBACK CURRENT 
 
 Since the large signal value of r .has increased 
 
 e f 
 over the small signal value* the phase of the feedback 
 
 current will be different than in the small signal de- 
 sign case. In the circuit of Pig. 2, the phase of the 
 feedback current is adjusted by the susceptance B_. 
 This susceptance can be calculated from Eq. 23 
 
 B, 
 
 F nR ' + mX ' * * 
 
 where a * m - j n and h.- R 1 + jX 
 
 It is seen that B p depends on R 1 f which is also equal 
 R e {j\]Jt and hence the large signal value of B p will differ 
 from the small signal value. Therefore, the extension 
 of theory from the small signal to the large signal 
 case is not complete until B_ is readjusted for max- 
 
 IT 
 
 iraum output. With the circuit operating under the 
 conditions which gave the maximum output as shown in 
 Fig. 9 i.e. a load resistance of 21,OOO ohms and an 
 adjusted turns ratio equal to four times the calculated 
 
 value, the feedback susceptance B_ was varied* The power 
 
 r 
 
 output varied as B^ was changed, a relationship that 
 
 r 
 
 could be reflected in a plot of B F vs power output. A 
 more informative graph, however, is that of Pig. 11. 
 
 As B_ was adjusted to a certain value, the output power 
 r 
 
 reading was taken. In Pig. 11, this power reading is 
 plotted against the value of R 1 which when substituted 
 into Eq. 23 1 will give the value of B p corresponding 
 to that particular output power. All other terms in Eq. 
 23 remain equal to their small signal value. In effect 
 Eq. 23 was solved to find R 1 in terms of B p and the 
 
 remaining terms. 
 
 m/B - mX 
 
 R m (24) 
 
 n 
 
19 
 
 The power output for a given fiL can then be 
 plotted against R 1 as in Fig. 11. IB this way, the 
 role of R 1 in optimizing the phase of the f wit back cur- 
 rent for maximum power output can be seen. 
 
 *> 
 3 
 C 
 
 t, 
 0) 
 
 * 
 o 
 
 do! 
 
 60 
 
 20 
 
 00 
 
 1R 
 
 3R' 
 
 4R 1 
 
 Resistance Used In Calculating B_ from jq 
 
 r 
 
 .v 1 s small signal value of Re 
 
 > -i R 
 
 Fig. 11. Power Output 
 
 Fig. 11 shows that the proper phase for maximum out- 
 is obtained when B- is calculated on the basis of 
 
 r 
 
 I eing about 4.4 times the small signal value. 
 
20 
 
 The above result tends to substantiate the result 
 of the last section; i.e. the large signal value of 
 R 1 is approximately four times the small signal value. 
 
 It is seen that correcting the turns ratio makes 
 the peak power output occur at the proper value of load 
 resistance. However, in order to increase the power 
 output such that it approaches the maximum theoretical 
 value, the phase of the feedback current must be cor- 
 rected* Therefore, the design of an oscillator for 
 maximum output power can be based upon the small signal 
 parameters using a simple modification of the emitter 
 diode resistance. This modification can then be used 
 in calculating the turns ratio and the feedback sus- 
 ceptance. 
 
 The analysis of the oscillator has been carried to 
 the point where nearly optimum results are obtained* 
 More important, element values of the oscillator to 
 obtain these results can be predicted by small signal 
 parameter values and a simple approximation to the diode 
 resistance. 
 
 CONCLUSIONS 
 
 The design procedure outlined in the three refer- 
 ences has been verified for small signal operation. The 
 extension to large signal operation gives results which 
 are not optimum. An important reason for these non- 
 optimum conditions is the fact that the emitter diode 
 resistance varies appreciably over the oscillation 
 cycle. A piece-wise linear approximation of this re- 
 sistance, which is more representative of the large 
 signal value, was obtained. This value was found to be 
 about four times the small signal value. Using this 
 modification of diode resistance, the output power was 
 
21 
 
 82% of the maximum theoretical output* It should be 
 profitable to continue this research with the objective 
 of obtaining the maximum available output power* 
 
APPENDIX 
 
 Section 1* Equations for obtaining equivalent 
 feedback circuits from basic transformer feedback* 
 
 a) Transformer - coupled form 
 
 b) Pi impedance - coupled form c) Tee impedance - coupled for 
 
 Y p (l - T) 
 
 - T) 
 
 - TY p (l.- T) 
 
 Z L (1 - T) 
 
 Y 3 - TY F 
 
 Z C TZ L 
 
 Section 2. Calculations of element values for 
 maximum output 
 
 I. / e? /N"" 2 \ I e o e \ 
 
 1.95 x 10" 3 4.4? x 10' 
 
 41 R 
 e 
 
 10" 3 )(52.5) 
 
 la IV ~LO .715 (6) 
 c 
 
 = 21,000 ohms 
 
 . 2 (.5 x 10- 5 )(52.5) <42 . 5<14 x 10 -3 
 
 a IV. w .715 
 
 T A " 21 e R< T 
 
Section 3* 
 
 Changing T. with 
 
 Experimental Data 
 K 
 
 21 J 
 
 A 
 
 10 , 
 
 20 
 
 1 T 
 
 1 7 
 
 1 & 
 
 
 27 , 
 
 5. 2 
 
 3m 
 
 5 6 
 
 
 6 4 
 
 6-O - 
 
 6.4 
 
 Volt* (p-p) 
 
 Changing 
 
 R (kilohms) 
 
 10 
 
 16 
 
 18 
 
 21 
 
 24 
 
 30 
 
 36 
 
 with T 
 
 Volts (p-p) 
 4.4 
 5.3 
 5.7 
 6.4 
 6.4 
 6.6 
 7.0 
 
 Emitter Diode Characteristic 
 
 I., ma. V, volts 
 c oe 
 
 .012 .034 
 
 .038 .060 
 
 .215 .100 
 
 .400 .116 
 
 .500- .122 
 
 .600 .130 
 
 .780 . .135 
 
 .900 .140 
 
 Power Output vs Feedback 
 Susceptance 
 
 P R 
 
 out F.B. 
 raw. (in terms of 
 Bp original) 
 
 .27 
 33 
 .3 
 
 . Tt J 
 
 .56 
 .60 
 .70 
 .70 
 .64 
 
 R' 
 
 F 
 
 4. 
 
 11 
 
 * R 1 is found from eq. 23. 
 It is the value which when 
 substituted into eq. 23 
 will give the correspond- 
 ing value of B., _ . 
 r o. 
 
REFERENCES 
 
 1* D.F. Page and A.R. Boothroyd, "Instability in 
 Two-Port Active Networks," IRE Trans . on Circuit Theory, 
 vol. CT-5, No. 3; June 1958. 
 
 2. D.P. Page, "A Design Basis for Junction Tran- 
 sistor Oscillator Circuits," Proc. IRE, vol. 46, pp 
 1271-1280, June 1958. 
 
 3 A.R. Boothroyd, "The Transistor as an Active 
 Two-Port Network," Scientia Electrica Band' VII, Heft 1; 
 pp 3-15 t March 1961. 
 
 4. A.R. Boothroyd, Lecture Notes from EE 298 Class, 
 University of California, Berkeley Campus, Spring 19&1. 
 
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