ll B RAHY OF THE UNIVERSITY OF ILLINOIS 510.84 It6r no. 237-242 cop. 2 The person charging this material is re- sponsible for its return on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. University of Illinois Library MSI IB ,! 871 DEC . "i L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/artrixfinalrepor238univ .'^Report Wo. 238 JVUlJCt; 000-11+69-0067 ARTRIX FINAL REPORT by J. W. Esch, A. F. Irwin, W. J. Kubitz, P. E. Oberbeck, W. J. Poppelbaum, and D. C. Rollenhagen June 20, 1967 THE UBJMRY OF Itf£ AUG I 10c > D or , ' v <- J UNIVERSITY OF ILLINOIS Report No. 238 COO-1^69-0067 ARTRIX FBIAL REPORT J. ¥. Esch, A. F. Irwin, ¥. J. Kubitz, P. E. Oberbeck, W. J. Poppelbaum, and D. C. Rollenhagen June 20 , 1967 Report lo, 238 ARTRIX FINAL REPORT by J. W. Esch, A, F. Irwin, ¥. J. Kubitz^ P. E, Oberbeck, W. J. Poppelbaum, and D, C. Rollenhagen June 20, 1967 Department of Computer Science University of Illinois Urbana, Illinois 6l801 ARTRIX FINAL REPORT CONTENTS 1.0 General Description j_ lol Purpose • -I 1.2 Physical Description and Definition of Subsystems 1 1-3 Description of Operation 3 1.3-1 The WRITE Modes g 1.3.2 The CONSTRUCT Mode 9 1.3-3 The ERASE Modes -^ 2,0 Subsystem Interaction 13 17 17 17 3.0 Subsystem Operation -in 3 = 1 DISPLAY 3-1.1 MONITOR 3.1.2 LIGHT PEN 3=1-3 CONTROL SWITCHES and INDICATORS 20 3.2 Memory 2^ 3.2.1 Memotron-Vidicon Storage Cell 2k 3-2.1.1 Memotron Storage Units 2h 3.2.1.2 Vidicon Cameras 26 3-2.2 MEMORY CONTROL UNIT 28 3-2. 2.1.: Synchronization, Blanking, and Deflection Circuits 2Q 3-2.2.1.1 Synchronization Circuits 29 3-2.2.1.2 Deflection Circuits 29 3.2.2.1.3 Blanking and Gating Circuits 31 3-2.2.2 Logic and Video Circuits 32 3.2.2.2.1 ERASE Modes 32 3.2.2.2.1.1 TOTAL ERASE Functions 32 3-2.2.2.1,2 ERASE POINT Pen Mode 36 3.2.2.2.1.3 ERASE DISPLAY Pen Mode 39 3-2.2.2.1.4 EXECUTE ERASE Sequence 39 11 3.2.2.2.2 Writing Modes 1^ 5-2.2.2.2.1 WRITE POINT Mode 1^ 3.2.2.2.2.2 WRITE DISPLAY Mode 1^ 3.2.2.2.3 CONSTRUCTION Mode ^ 3. 2. 2. 2 A Video Output Circuit 3-3 PROCESSOR 3-3-1 Digital Section of the PROCESSOR 3- 3-1-1 Synchronizing Signals 3.3-1.2 Control Flip-Plop 3-3»l-3 Counter Operation c--, 3-3.1.^ Slope Control Circuits 3-3-1-5 Miscellaneous Circuits 4 .0 Conclusions 47 47 48 48 50 53 5^ 3-3-2 Hybrid Section of the PROCESSOR 55 3-3-2.1 Circle Operation 3.3-2.2 Line Operation 55 58 61 4.1 Summary ^ 4.2 Recommendations g. Ill 66 66 66 78 APPENDIX A1.0 Power Distribution System Al.l AC Power Distribution A1.2 DC Power Distribution Alo3 VOLTAGE MONITOR 6 g A2.0 Description of Circuits 7 ^ A2.1 DIAMOND GATE, 1469-14A ^ A2.2 DCVGLA, 1469-102B ^ A2.3 Integrated Circuits, 1469-103B-00 1J+69-103B-01 1469-103B-02 1469-103B-03 l469-i03B-o4 A2.4 D/A converter, i469-io4b A2.5 DC and AC MIXER and AMPLIFIER, 1469-105A A2.6 DPDT RELAY, l469-106 A2o7 DELAY MULTIVIBRATOR, 1469-107 A2.8 CONSTANT VOLTAGE SOURCE, 1469-10 8 84 A2»9 8,064 MHz CLOCK, 1469-109A 84 A2.10 SYNCHRONIZATION SEPARATOR/GATE DRIVER/VERTICAL BLANKING LOGIC DRIVER, I469-110A 84 -A2ol0,l SYNCHRONIZATION SEPARATOR 84 A2.10.2 GATE DRIVER 85 A2 o i0„3 VERTICAL BLANKING LOGIC DRIVER 85 A2.ll HORIZONTAL and VERTICAL Sweep Generators 1469-11LA-00 and 01 A2.12 ONE SHOT BUFFER, 1469-112 A2.13 VIDEO to LOGIC CONVERTER, 1469-113A A2„l4 Z-AXIS DRIVER, l469-ll4A A2„15 INDICATOR, 1469-1153-03 and 04 A2 l6 VIDEO ADDER and SYNCHRONIZATION INSERTER, l469-ll6A 87 79 79 83 84 85 86 86 86 87 IV A2.22.1 PHASE SHIFTER and EMITTER FOLLOWER, 1^69-152-00 87 A2.17 COMPARATOR, 1469-117 A2.18 PEW PULSE SHAPING CIRCUIT AM) MULTIVIBRATOR GATE 1^69-ll8A ' 88 A2.19 DISCRIMINATOR and SHAPER, 1469-119 A2.20 PEN PREAMPLIFIER, 1469-121 A2,21 DC ADDER and AMPLIFIER, 1469-123 A2.22 General Circuit Cards 88 88 89 89 89 90 90 90 92 92 A2 22 e 2 AMPLIFIER and EMITTER FOLLOWER, 1^69-152-01 A2.22.3 10kHz SQUARE WAVE GENERATOR, 1469-152-02 89 A2«22 9 4 +1„7 VOLT POWER SUPPLY, 1469-152-03 89 A2.22c5 EMITTER FOLLOWER, 1469-152-04 A2.22.6 EMITTER FOLLOWERS, 1469-152-05 A2.22.7 PEN GATE, 1469-152-06 A2.23 PLUS and MINUS SINE and COSINE GENERATOR, 1469-153-00 90 A2.24. VOLTAGE MONITOR, 1469-15 7 92 A2.25 H g RELAY, l469~i64B A2.26 FILTER, 1469-173 A2.27 PEN EMITTER -FOLLOWER and ENABLE FILTER 92 A3.0 Complete ARTRIX Drawings o^ A3.1 System Drawings o^ A3olol Panel Layout o^ A3. 1.2 System Block Diagram 05 A3 .1-3 Control Panel 05 A3. 1.4 LIGHT PEN ^ A3. 1.5 DISPLAY CONSOLE JUNCTION BOX 98 A3.I06 AC PANEL and AC ON-OFF PANEL 99 A3. 1.7 MAIN CONSOLE JUNCTION BOX 100 A3.I08 VOLTAGE MONITOR 10 1 A3- 1.9 ARTRIX Pen Cable Diagram 102 109 110 A3« 2 Memory Drawings 103 A3. 2.1 MEMORY CONTROL Card Rack List 10 4 A3. 2.2 MEMORY CONTROL UNIT 10? A3- 2. 3 PARTIAL SCHEMATIC of CAMERA CONTROL UNIT 108 A3. 3 PROCESSOR Drawings A3 .3.1 PROCESSOR Card Rack List A3 -3.2 Digital Section ., , , 113 A3. 3*2.1 PROCESSOR Control Circuits 114 A3. 3.2.2 HORIZONTAL MASTER SYNCHRONOUS COUNTER 115 A3. 3- 2. 3 VERTICAL MASTER RIPPLE COUNTER 116 A3 o 3. 2 .k HORIZONTAL POINT 1 SYNCHRONOUS COUNTER 11? A3. 3. 2. 5 VERTICAL POINT 1 RIPPLE COUNTER 118 A3. 3 * 2. 6 HORIZONTAL POINT 2 SYNCHRONOUS COUNTER i:L q A3- 3. 2. 7 VERTICAL POINT 2 RIPPLE COUNTER 120 A3. 3 «2. 8 EXPANDING RADIUS RIPPLE COUNTER 121 A3«3,2o9 SWITCHING CIRCUIT 122 A3- 3- 3 Hybrid Section 1C , 123 A3. 3»3.1 PROCESSOR - Hybrid 12 1+ A3^ Circuit Card Schematics , oc 12> The circuit cards are listed in order of their card number. lk-69-lkA DIAMOND GATE 12 £ 11+69-102B DOVGLA 1^69-103B-00 2 -INPUT NAND 1U69-1033-01 J-K FLIP-ELOP 1^69-1033-02 3-INPUT NAND 1^69-103B-03 1+- and 8-INPUT NAND 1^69-103B-0^ MONOSTABLE MULTIVIBRATOR 1^69 -104B 9 BIT D/A CONVERTER ^k 1^69-105A DC AMPLIFIER and MIXER I35 lJ+69-106 DPDT RELAY 137 li+69-107 DELAY MULTIVIBRATOR 139 128 129 130 131 132 133 VI 158 159 1^69-108 CONSTANT VOLTAGE SOURCE ^.kl 1469-109A 8,064 Miz CLOCK lh2 1^69-llOA SYNCHRONIZATION SEPARATOR/GATE driver/vertical blanking logic DRIVER 1 i l3 1^69-lllA-OO VERTICAL SWEEP GENERATOR jltf 1^69-lllA-Ol HORIZONTAL SWEEP GENERATOR ±1+7 1^69-112 ONE SHOT BUFFER ± kQ lk69- 113A VIDEO to LOGIC CONVERTER 150 l469-Il4A Zf-AXIS DRIVER 152 1469-115B INDICATOR 15 4 1^69 -116a VIDEO ADDER and SYNCHRONIZATION INSERTER 1^69-117 COMPARATOR 1^69 -118A PEN PULSE SHAPING CIRCUIT and MULTIVIBRATOR -GATE l6o 1469-119 DISCRIMINATOR and SHAPER 162 1^69-121 PEN PREAMPLIFIER 164 1469-123 DC and AC MEXER and AMPLIFIER 165 1^69-152-00 PHASE SHIFTER and EMITTER FOLLOWER 167 1^69-152-01 AMPLIFER and EMITTER FOLLOWER 168 1469-152-02 lOKHz SQUARE WAVE GENERATOR 170 1469-152-05 +1.7 VOLT POWER SUPPLY 171 l46c*- 152 -04 AMPLIFIER and EMITTER FOLLOWER 172 1469-152-05 EMITTER FOLLOWER yjk 1469-152-06 PEN GATE MULTIVIBRATOR I76 1469-152-07 DISPLAY GATE DRIVER I77 1469-153-00 lOKHz OSCILLATOR and AMPLIFIER 178 1469-157 VOLTAGE MONITOR 179 1469- 164B Hfe RELAY !8o 1469-173 FILTER l82 LIGHT PEN CABLE DRIVER and ENABLE FILTER ^ Vll A^.O Physical Description 2.85 A^.l Complete ARTRIX System !86 A^.2 ARTRIX Printed Circuit Boards 187 A^.3 PROCESSOR Rack and CAMERA CONTROL UNIT Rack 189 A5-0 Definition of PROCESSOR Logic Symbols 191 A6.0 Alignment Procedure ]_oc A6.1 Memory Alignment ^95 A6.I0I Cameras 195 i . . A6.1.2 Memb-Corders 195 A6.I.3 Horizontal and Vertical Gain and Position (Pen Alignment) 196 A6.2 PROCESSOR Alignment 197 A6.2.1 Tracking of POINT 1 I97 A6.2.2 Length and Position Lines 197 A6.2.3 Dummy Offset for Circles 198 A6.2.^ Shape and Size of Circles 199 A6.3 Memory Control Adjustment 199 A6.3.I 150 MILLISECOND MULTIVIBRATOR, Card Bll 199 A6.3.2 Pen Threshold Adjustment, Card Ai 200 A.6.3.3 Video Adders, Cards A7 and A8 200 A6.3A Discriminator Adjustment 200 A6.3.5 Erase Level Adjustment 201 Vlll LIST OF ILLUSTRATIONS - BODY 1.1 The ARTRIX System 2 1=2 MAIN CONSOLE , 3 1.3 a DISPLAY CONSOLE, Front ^ 1.3 b DISPLAY CONSOLE, Rear 5 lA LIGHT PEN g 1-5 Block Diagram of ARTRIX 7 1.6 CONTROLS of ARTRIX DISPLAY CONSOLE' 10 2.1 Subsystem Interaction , ^ 3.1 DISPLAY CONSOLE lg 3.2 Basic ARTRIX Writing Scheme 19 3.3 Simplified Schematic of DISPLAY CONSOLE JUNCTION BOX 23 3A Typical Memotron-Vidicon Combination 2 5 3-5 Partial Schematic of CAMERA CONTROL UMTS 27 3.6 MEMORY CONTROL UMT 30 3.7 Simplified Diagram of DISPLAY CONSOLE JUNCTION BOX 33 3.8 Simplified Diagram of MAIN JUNCTION BOX 34 3.9 Schematic of MEMORY CONTROL UNIT 3.10 a The ERASE Operation 3° 10 b The EXECUTE ERASE Counter Sequence ^ 3.H The ARTRIX PROCESSOR 3.12 Hybrid PROCESSOR 35 h 9 3.13 Generation of a Circle with Sine and Cosine Functions 57 3-14 Generation of a Line with a Positive and Negative Sine Function 59 IX LIST OF ILLUSTRATIONS - APPENDIX Al.l AO Panel and AC On-Off Panel 6y A1.2 MAIN CONSOLE and DISPLAY CONSOLE Interconnection Drawing 68 A1.3 Simplified Diagram of Main JUNCTION BOX 69 Al.U Simplified Diagram of DISPLAY CONSOLE JUNCTION BOX 70 A 1.5 VOLTAGE MONITOR Chassis 72 A2.1 Basic Scheme of DCVG.LA 76 A2.2 Schematic Diagram of the DCVGLA 77 A2„3 9 Bit D/A Converter A2.4 Basic Scheme of DC and AC Mixer and Amplifier A2.5 Schematic Diagram of DC and AC Mixer and Amplifier A2.6 Schematic of PLUS and MENUS SINE and COSINE, GENERATOR 91 80 81 82 A3. 1.1 Panel Layout A3 . 1.2 System Block Diagram A3. 1-3 Control Panel A3.1« i + LIGHT PEN A3. 1.5 DISPLAY CONSOLE JUNCTION BOX A3 ° 1.6 AC PANEL and AC ON-OFF PANEL A3°lo7 MAIN CONSOLE JUNCTION BOX A3 .1.8 VOLTAGE MONITOR A3. 1.9 ARTRIX PEN CABLE DIAGRAM A3. 2. 2 MEMORY CONTROL UNIT 107 A3°2„3 PARTIAL SCHEMATIC of CAMERA CONTROL UNIT 108 A3 *3*2.1 PROCESSOR Control Circuits 12 h A3-3-2.2 HORIZONTAL MASTER SYNCHRONOUS COUNTER 115 A3 . 3 . 2 . 3 VERTI CAL MASTER RI PPLE COUNTER 1X 6 A3. 3. 2. k HORIZONTAL POINT 1 SYNCHRONOUS COUNTER U7 A3. 3. 2,5 VERTICAL POINT 1 RIPPLE COUNTER, ll8 A3. 3 =2. 6 HORIZONTAL POINT 2 SYNCHRONOUS COUNTER H9 A3 .3.2.7 VERTICAL POINT 2 RIPPLE COUNTER !2 9^ 95 96 97 98 99 100 101 102 121 122 123 A3. 3- 2. 8 EXPANDING RADIUS RIPPLE COUNTER A3. 3- 2. 9 SWITCHING CIRCUIT A3.3-3 Hybrid Section A3> CO X I (1) ,c Eh H o H 0) u hO •H P>4 -> W^mmmmmamsmmMmmmmmMmtm mm Figure 1.2 MAIN CONSOLE -k- Figure l.J a DISPLAY CONSOLE, Front -5- Figure 1.5 b DISPLAY CONSOLE, Rear -6- Figure l.k LIGHT PEN -7- x H K I O S a) CO •H o o pq LT\ o H -8- The PROCESSOR and MEMORY are contained in the MAIN CONSOLE (Figure 1.2) . The PROCESSOR is a hybrid subsystem, containing all the digital logic and hybrid circuitry necessary for the graphical constructions. The MEMORY contains four analog storage units necessary for storing construction points, for storing line drawings on the DISPLAY and for use during the ERASE mode of operation. These four units are called the TEMPORARY, ERASE, POINT and DISPLAY memories. The DISPLAY, which is contained in the DISPLAY CONSOLE, is a television monitor which serves as the "writing pad" for the operator (Figure 1.3) . On it, he draws all his line drawings, performs graphical constructions, and erases when he so desires. In addition to the three basic subsystems, the LIGHT PEN and CONTROLS are integral parts of the system, though they are not classified as subsystems. The LIGHT PEN (Figure lA) plugs into the DISPLAY CONSOLE:, and in the WRITE mode of operation it is used as an ordinary pencil except that an actuating button called the ENABLE button must be depressed. In the ERASE mode of operation the LI PEN is used as an eraser in a similar manner. The CONTROLS consist of rows of buttons on the DISPLAY CONSOLE which switch the system between the various modes of operation. Above each button is an indicator which lights when the system switches to the chosen mode of operation or when the indicated function has been performed. 1*3 Description of Operation r Jrie three basic modes of operation of ARTRIX are WRITE, CONSTRUCT and ERASE. The following paragraphs describe the sequences of operation in each of these three modes. It is assumed that the system has beer- switched on and that sufficient warm-up time has been allowed. 1.3.1 The WRITE Modes r 2'ae operator may write in either the WRITE DISPLAY mode or the WRITE POINT mode. The former is for simple line drawings while -9- the latter is for -writing construction points. Both the points written in the WRITE POINT mode and the line drawings written in the WRITE DISPLAY mode appear simultaneously on the DISPLAY as well as any constructions which have been performed . Depressing the appropriate button will switch ARTRIX to the chosen mode of operation,, Refer to Figure 1.6. The writing of either points or line drawings is then accomplished by depressing the ENABLE button on the LIGHT PEN and writing with the LIGHT PEN on the DISPLAY as one would write with a pen on paper. 1.3.2 The CONSTRUCT Mode Assuming that several points have been written in the WRITE POINT mode, the operator may wish to proceed with a construction. Depressing the button labelled CONSTRUCT places the system in the CONSTRUCT mode of operation. The operator must then select the desired mode of construction, circle or line, and depress the appropriate button. Two points are required for the construction of a line or circle. For a line the two points are its end points and for a circle the two points are, in sequence, the center of the circle and a point on its circumference. Of the points which have been written in the WRITE POINT mode, the two which are to be used for the construction must be indicated with the LIGHT PEN. When the LIGHT PEN is directed to the first point, and the ENABLE button depressed, the POINT 1 STORED indicator will light. Similarly, when the second point is selected with the LIGHT PEN, the POINT 2 STORED indicator will light. If ARTRIX is in the CIRCLE mode of operation, the RADIUS STORED indicator will light soon after the two points have been selected. The construction is executed upon depressing the EXECUTE CONSTRUCT button. A straight line will then appear between the two points in the LINE mode of operation, or a CIRCLE will appear centered at the first point with the second point on its circumference in the CIRCLE mode of operation. ■ a. a a. in o o < UJ Sir IE O S Q- UJ Q- H En O H O -p C O o H CD g v\ -11- In addition to the basic operations described above, ARTRIX is capable of translating circles and lines as well as constructing concentric circles. These operations are accomplished, basically, by indicating a new point to replace one of the two used previously in a construction. Translation of circles is accomplished by depressing the POINT 1 RESET button and indicating a new POINT 1 with the LIGHT PEN. The POINT 1 STORED indicator will light again indicating that a circle is to be constructed about the new center point with: the same radius as that of the previous circle. Upon depressing the EXECUTE CONSTRUCT button, a new circle will appear in addition to the one previously constructed, but which has been translated to the new center. A line which has been constructed in the LINE mode of operation may be translated parallel to itself by depressing the POINT 1 RESET button and indicating a new POINT 1 with the LIGHT PEN. When the EXECUTE CONSTRUCT button is depressed, a line will appear on the DISPLAY parallel to the first line, terminating at the new POINT 1. Its length will be the same as that of the first line. Concentric circles are constructed by changing POINT 2 and the radius of the first circle. The POINT 2 RESET button and the RADIUS RESET button must be depressed and a new POINT 2 indicated with the LIGHT PEN. The distance between this and POINT 1 will, of course, be the new radius. When POINT 2 is indicated, the POINT 2 STORED indicator and RADIUS STORED indicators will light. Upon depressing the EXECUTE CONSTRUCT button, a new circle will appear concentrically about or within the first circle. If an entirely different construction is to be performed, depressing the PROCESSOR RESET button will clear the PROCESSOR of points used previously in constructions. The PROCESSOR RESET indicator will light when the PROCESSOR has been reset. The PROCESSOR may be reset even though ARTRIX is not in the CONSTRUCT mode. However, no new points may be indicated and stored until the system is returned to the CONSTRUCT mode. In addition, the PROCESSOR preserves all stored information when ARTRIX is switched in and out of the CONSTRUCT mode. -12- 1.3.3 The ERASE Modes ARTRIX is equipped with facilities for erasing partially, for example, erasing sections of a line drawing; or erasing totally, that is, erasing the entire contents of one or all of the four storage units of the MEMORY. Buttons designating erasure of each of the four units, TEMPORARY, ERASE POINT, and DISPLAY, are located on the CONTROL switch panel. Depressing any one of these will erase the entire contents of the corresponding storage unit. Depressing the button labelled TOTAL vill erase the contents of all of the four storage units, thus clearing the entire MEMORY of previously stored information. Either the POINT memory or the DISPLAY memory may be erased selectively by depressing the button labelled ERASE POINT or ERASE DISPLAY, respectively. The portions of the line drawing or the points to be erased must be indicated with the LIGHT PEN. The LIGHT PEN is used as if it were an eraser, with the ENABLE button depressed. When all points or lines to be erased have been so indicated, these points and lines will vanish from the DISPLAY upon depressing the button labelled EXECUTE ERASE. -13- 2.0 Subsystem Interaction Figure 2.1 shows the basic interconnections between the PROCESSOR, MEMORY, and DISPLAY subsystems of ARTRIX. The PROCESSOR is shown in two separate blocks, one representing the digital section, the other representing the hybrid section. The TEMPORARY memory has been deleted from the MEMORY block since it operates in conjunction with the ERASE and DISPLAY memories only, and does not interact with the other subsystems. Also shown in Figure 2.1 is the LIC-HT PEN as well as those switches relevant to the subsystem interaction. Included in this section of the report are brief discussions of the MEMORY and PROCESSOR to facilitate an understanding of the subsystem interaction. Detailed discussions of these subsystems follow in Sections 3.2 and 3.3. Each of the four storage units of the MEMORY, namely DISPLAY, POINT, ERASE and TEMPORARY (the natter having been deleted) consists of a storage tube for storage of information, and a Vidicon camera for reading the stored information. A deflection signal is necessary for controlling the WRITE beam of the storage tube. Each memory is also equipped with an erase input for erasing its entire contents. Thus there are three inputs and one input from each unit; the inputs are the write, deflection and erase signals, and the output is the read signal. These signals are labelled W, D, E, R, respectively, on Figure 2.1. Only those inputs and outputs relative to the discussion, are shown in Figure 2.1, In the WRITE DISPLAY mode of operation switch S is set at position 1, and the signal from the LIGHT PEN is directed to the WRITE input of the DISPLAY memory. Thus the sketch is stored in the DISPLAY memory as it is being drawn. S^ is normally switched to the position labelled NORMAL DEFLECTION, ganged with S ± which is normally open. Similarly, with S 2 in position 2, and the system in the WRITE POINT mode, points are drawn with the LIGHT PEN and stored in the POINT MEMORY. With S^ in position 3, and ARTRIX in the ERASE mode, all points or portions of a drawing indicated for erasure with the LIGHT PEN are stored in the ERASE MEMORY. When points are to be erased from the ■1k- -»2_i Z li. CO ui Q -15- POINT MEMORY, S^ will be in the upper position; when portions of a sketch are to be erased from the DISPLAY MEMORY, S, "will be in the lower position. The DISPLAY consists of a cathode ray tube whose beam sweeps out the stored information on the MONITOR. The LIGHT PEN contains a photosensitive device which detects the light of the beam as it sweeps in front of the pen. The time which elapses between the beginning of the sweep and the instant when the beam position and pen position are coincident is a measure of the coordinate position of the LIGHT PEN on the DISPLAY. Coincidence is detected by the AND gate when S 2 is in position k, as shown in Figure 2.1. When signals appear at the input of the gate simultaneously, a signal will appear at the output. The digital section of the PROCESSOR contains binary counters whose contents correspond to vertical and horizontal coordinates of ' the position on the DISPLAY. These counters run continuously in synchronization with the motion of the electron beam in the DISPLAY until a point is indicated. That is, each binary count in the vertical counter corresponds to one of 500 horizontal lines on the DISPLAY, and each binary count in the horizontal counter corresponds to one of 500 segments of each horizontal line. In the CONSTRUCT mode of operation with S 2 in position k, the position counters of the PROCESSOR count continuously commencing at the beginning of each sweep of the DISPLAY until a point is indicated by the LIGHT PEN. When a signal is received from the output of the AND gate, the horizontal and vertical position counters of the PROCESSOR stop, the contents therein representing the horizontal and vertical of the LIGHT PEN. A POINT STORED indicator then lights indicating that a point has been stored. The PROCESSOR contains two horizontal and two vertical counters, one pair being used to store the coordinates of POINT 1, the other pair being used to store the coordinates of POINT 2 in the same manner described above. In the LINE mode of operation the digital signals from the horizontal and vertical counters are converted to analog voltages in the -16- hybrid section of the PROCESSOR. These voltages are used to determine the length, slope and position of the line on the DISPLAY. The line is generated as a Lissajous pattern in the 111 SPLAY MEMORY with sinusoidal deflection signals. The 10 KHz sinusoidal oscillator which generates these signals is shown in Figure 2.1. When the EXECUTE CONSTRUCT button is depressed, S switches from the normal deflection signal to the deflection signal arriving from the hybrid section of the PROCESSOR. S 1 is closed at the same time which allows the line to be written in the DISPLAY MEMORY, and subsequently the line appears on the DISPLAY. The same basic sequence of events occurs in the CIRCLE mode of operation as in the LINE mode except that a radius counter is employed. This counter stores the magnitude of the radius in bit form which is then coverted to an analog voltage in the hybrid section of the PROCESSOR. Translation of lines and circles and the construction of concentric circles is accomplished by resetting the appropriate counter (s), thus changing the corresponding analog voltages in the PROCESSOR. In the case of translating a line, for example, this amounts to shifting the DC levels of the Lissajous pattern in the DISPLAY MEMORY. -17- 3*0 Subsystem Operation 3.1 DISPLAY 3.1.1 MONITOR The ARTRIX DISPLAY system consists of a standard 23 M black and white television MONITOR, a LIGHT PEN and a set of CONTROL SWITCHES. These are all located in the DISPLAY CONSOLE as shown in Figure 3.1. The MONITOR displays the video output of the MEMORY CONTROL UNIT. This video output consists of the contents of both the DISPLAY MEMORY and the POINT MEMORY as explained in Section 3.2.2.2.4. Thus the operator is presented with a continuous view of the contents of the two memories with which he works. 3.1.2 LIGHT PEN The LIGHT PEN detects the light produced by the scanning of the electron beam in the MONITOR (See Figure 3.2). Because the LIGHT PEN cannot detect light where none is present, the use of this type of light pen necessitates a gray background level on the MONITOR. Thus the MONITOR picture consists of white writing on a gray background. The LIGHT PEN contains an ENABLE button as well as the photo diode light detector and amplifier. The output of the LIGHT PEN amplifier is sent to a line driver in the PEN EMITTER FOLLOWER chassis located in the DISPLAY CONSOLE (Figure 3.2). The ENABLE button controls the output of the LIGHT PEN in such a way that the LIGHT PEN output pulse is ineffective except when the ENABLE button is depressed. This control takes place in the MEMORY CONTROL UNIT. The LIGHT PEN mode switches determine the function of the LIGHT PEN pulse when the ENABLE button is depressed. This control takes place in the MEMORY CONTROL UNIT. The LIGHT PEN mode switches determine the function of the LIGHT PEN pulse when the ENABLE button is depressed (Figure 3.1) . ■18- Figure 5.1 DISPLAY CONSOLE ■19- 1 1 DISPLAY SCAN STORAGE TUBE LIGHT PEN VIDICON SWEEP GENERATOR Figure 3„2 Basic ARTRIX: Writing Scheme -20- 3.1.3 Control Switches and Indicators The LIGHT PEN mode section of the CONTROL SWITCHES allows operation of the LIGHT PEN in one of five different mutually exclusive modes: WRITE POINT, WRITE DISPLAY, CONSTRUCT, ERASE DISPLAY, and ERASE POINT. In the WRITE POINT mode, the LIGHT PEN can write one point per television frame into the POINT MEMORY. The WRITE POINT mode switch also causes the WRITE POINT INDICATOR to light. In the WRITE DISPLAY mode the LIGHT PEN can write one point per television frame into the DISPLAY MEMORY. The WRITE DISPLAY mode switch causes the WRITE DISPLAY INDICATOR to light . In either the ERASE POINT or ERASE DISPLAY mode, the LIGHT PEN can write one point per television frame into the ERASE MEMORY. The ERASE POINT and ERASE DISPLAY mode switches cause their respective indicators to light. Information written into the ERASE MEMORY shows up on the MONITOR as a dark shade of gray. This occurs because the output of the ERASE MEMORY is used to delete information from either the POINT MEMORY or the DISPLAY MEMORY video signal depending on whether the ERASE POINT or ERASE DISPLAY mode has been chosen. This is accomplished by blacking the appropriate video signal (POINT or DISPLAY) at points corresponding to those written in the ERASE MEMORY. A description of this operation is given in Section 3.2.2.2.1.2. In the remaining mode, CONSTRUCT, the LIGHT PEN is used to locate points on the MONITOR which are stored in the POINT MEMORY. The actual processing of the LIGHT PEN pulse is accomplished in the MEMORY CONTROL UNIT and a description of these operations is contained in Section 3.2.2.2.3. The CONSTRUCT INDICATOR lights either yellow (LINE) or blue (ARC -CIRCLE) depending on the PROCESSOR mode switches. The remaining CONTROL SWITCHES can be divided into two groups: the MEMORY erase control switches and the PROCESSOR control switches. There are six switches which control the erase functions of the system: TOTAL, TEMPORARY, POINT, DISPLAY, ERASE, and EXECUTE ERASE (See Figure 3-l)« Five of these six switches have no associated indicators. Depressing the TOTAL button erases all information on all four memories. -21- Depressing the ERASE, DISPLAY, POINT, or TEMPORARY buttons causes all information in the ERASE MEMORY, DISPLAY MEMORY, POINT MEMORY, or TEMPORARY MEMORY, respectively, to be erased. The EXECUTE ERASE button functions only in either the ERASE POINT mode or ERASE DISPLAY mode. When this button is depressed a sequential process takes place in the MEMORY CONTROL UNIT which accomplishes the following: 1) The contents of the memory (either POINT MEMORY or DISPLAY MEMORY depending on whether the mode is ERASE POINT or ERASE DISPLAY) has its contents blacked out at points corresponding to the contents of the ERASE MEMORY while it is written into the TEMPORARY MEMORY . 2) The original memory (POINT or DISPLAY) and the ERASE MEMORY are completely erased. 3) The information in the TEMPORARY MEMORY is written back into the original memory (POINT or DISPLAY) . 4) The TEMPORARY MEMORY is completely erased. Thus at the end of this process the original memory contains the information that it originally possessed less that information which had appeared in the ERASE MEMORY. During this sequential operation, the EXECUTE ERASE indicator lights. The remaining set of switches, the PROCESSOR CONTROL switches, control the mode of operation of the PROCESSOR and the contents of the PROCESSOR POINT REGISTERS, There are three mutually exclusive mode switches: LINE, CIRCLE, and ARC. These switches determine whether the PROCESSOR will calculate a circle, a line, or an arc . In each case the appropriate PROCESSOR MODE INDICATOR lights . In order for the PROCESSOR to generate any of these, the LIGHT PEN must be in the CONSTRUCT mode. With the LIGHT PEN in the CONSTRUCT mode, it can be used to designate points on the MONITOR. The first point designated is known as POINT 1 and the second point designated is known as POINT 2. When a point is stored in the PROCESSOR, the appropiate POINT STORED indicator lights. In the CIRCLE mode, POINT 1 is interpreted by the PROCESSOR as the center of the desired circle and POINT 2 is interpreted -22- as a point defining the circumference of the circle. The radius of the circle is calculated from these two points. When the radius is stored the RADIUS STORED INDICATOR lights. Similarly in the LINE mode, POINT 1 and POINT 2 define the ends of the line for the PROCESSOR. In the CIRCLE mode either POINT 1 or POINT 2 (center or radius) may he changed independently by operating the appropriate reset button (POINT 1 RESET or POINT 2 RESET) and then indicating the new point. When it desired to change the radius of the circle, the RADIUS RESET button must also be depressed. In the LINE mode, a line may be translated by changing POINT las above . Changing POINT 2 in the line mode has no useful significance. The ARC mode has not been implemented in the current system. There are two buttons remaining: PROCESSOR RESET and EXECUTE CONSTRUCTION. The PROCESSOR RESET button causes the POINT 1, POINT 2, and RADIUS REGISTERS all to be reset simultaneously. With all registers reset, the PROCESSOR RESET INDICATOR lights. The EXECUTE CONSTRUCTION button causes the MEMORY CONTROL unit to write the construction (line or circle) into the DISPLAY MEMORY. The EXECUTE CONSTRUCTION READY INDICATOR lights when the PROCESSOR is in a state such that a construction has been generated and can be written into the DISPLAY MEMORY at the option of the operator. The CONTROL SWITCHES and INDICATORS are connected to the MAIN CONSOLE through the DISPLAY CONSOLE JUNCTION BOX, Figure 3-3). This junction box serves as a distribution point for power and control signals in the DISPLAY CONSOLE. It contains two printed circuit cards, a LAMP DRIVER card and a SWITCH FILTER card. The LAMP DRIVER card drives the CONTROL SWITCH INDICATORS which operate from logic level signals generated in the PROCESSOR and MEMORY CONTROL UNIT. Other indicators are operated directly by the CONTROL SWITCHES. The FILTER card in conjunction with the clamping diodes which are mounted externally to the card serves to generate low impedence logic signals from the CONTROL SWITCHES in order to drive the logic circuits in the MAIN CONSOLE -23- x o t cog -I I- o < or o II CD ~3 r snvNois aoivoiaNi U3M0d oa > siioa s- o or co K LJ z X O O m O J— 5 S ~3 o w DC li- J CO _J o > o f-H + u — CO X < 2^ o O 5 5P o H o o Eh or 2 a. id "3 r ~3 u Ld O LU CO CO CO < X o —, LJ Ld o< LU _J CO < UJ o _J _J o snvNois noaiNoo X o CD ~3 8 B o I H o o •H -P 0) o CO a) •H li) J "la h n u i . t- tf> N -1 vb o 2 u O ui o ui z © CO — O " '© 25 e O Z3 -P ■H o o o s O o °H -P .3 o CO H CO •ri -P u ai P-i ir\ g •H P4 -28- Section 3. 3. 1.1. The horizontal drive pulses originate in the MASTER UNIT and are fed to Slaves #2 and #3 through CABLE 52. Likewise, the vertical drive pulses are sent through CABLE 51. Composite blanking originates at connector J609 of the MASTER UNIT and goes to connector J609 of the Slave units on CABLE 73- Since connectors J609 and j6l0 of the slave UNIT are common terminals, blanking appears at J6l0 -where it is fed to the MEMORY CONTROL UNIT on CABLE U8. Composite synchronization appears at connector J6ll of the MASTER UNIT, and goes to the MEMORY CONTROL UNIT on CABLE 50. The synchronization pulses from the PROCESSOR are fed to the CAMERA CONTROL UNIT OSCILLATOR at connector J6l0 of the MASTER UNIT. Connectors J603 and j6oi+ of the MASTER UNIT are the video outputs of the TEMPORARY MEMORY. Connectors J653 and J6$h of the SLAVE #1 UNIT are the video outputs of the ERASE MEMORY. Similarly, connectors J603 and j60^ of SLAVE #2 unit correspond to the POINT MEMORY video and connectors J653 and j6$h of SLAVE #3 unit correspond to DISPLAY MEMORY video. There is no connection to connectors J606 and J608 of the SLAVE #2 UNIT, since these are drive pulse outputs and are not used. The remaining four connectors are synchronization input connectors. No synchronization is added to the video signal in the CAMERA CONTROL UNITS, thus the TEMPORARY synchronization (MASTER) and ERASE synchronization (SLAVE #l) inputs are not used. The POINT (SLAVE #2) and DISPLAY (SLAVE #3) synchronization inputs are used, however, but not for synchronization. These inputs are used in the ERASE mode. In this mode a signal is applied to the synchronization input which causes the video level to be reduced to the black level, thus "erasing" a portion of the video signal. By adjusting the synchronization level potentiometer in the control units, the input signal reduces the video level only to the black level rather than to some negative level. 3.2.2 MEMORY CONTROL UNIT -29- 3 * 2 ' 2 ' 1 Synchroniza tion, Blanking and Deflection Circuits 3.2.2.1.1 Synchronization Circuits A standard composite EIA synchronization signal is supplied to the MEMORY CONTROL UNIT from the CAMERA CONTROL UNIT at connector J50 (see Figure 3.6) . The CAMERA CONTROL also supplies this synchronization signal to the PROCESSOR (see Section 3.3.1.1). This signal is fed to the VIDEO ADDER on card A8 and to the SYNCHRONIZATION SEPARATOR circuit on card CI. At the VIDEO ADDER card, the composite synchronization signal is added to the output video signal being sent to the DISPLAY CONSOLE. At the SYNCHRONIZATION SEPARATOR, the synchronization signal is separated into horizontal and vertical synchronization pulses. The horizontal synchronization pulses are then passed to the HORIZONTAL RAMP GENERATOR circuit on card C3, where they are used to synchronize the horizontal sawtooth deflection voltage. The vertical synchronization pulses are fed to the VERTICAL RAMP GENERATOR on card C2, where they are used to synchronize the vertical deflection voltage. The vertical " synchronization pulses are also sent to the VERTICAL SYNCHRONIZATION LOGIC DRIVER (also on Cl) , where the synchronization pulses are converted to logical signal levels compatible with the logic circuits. The use of these VERTICAL SYNCHRONIZATION LOGIC PULSES will be described later when the erase operation is discussed. 3-2.2.1.2 Deflection Circuits The horizontal and vertical deflection signals generated by the circuits on cards C2 and C3 are sent directly to the POINT, ERASE and TEMPORARY MEMORIES at connectors J62 and j6h . These ramps also pass through the DEFLECTION CONTROL RELAY (on card C4) and to the DISPLAY MEMORY at connectors J38 and J39 except when the LIGHT PEN is in the CONSTRUCT mode and the PROCESSOR is in the EXECUTE CONSTRUCTION READY state. The logical AND of these two conditions is accomplished on card B5 . If the LIGHT PEN is in the CONSTRUCT mode and the PROCESSOR ■50- W* \v H- iiiiiii Uiiiiiiiiiii.fi ill -31- is in the EXECUTE CONSTRUCTION READY state the DEFLECTION CONTROL RELAY is energized and the DISPLAY MEMORY deflection inputs at connectors J38 and J39 are connected to the PROCESSOR deflection outputs (connectors J 7 and j6 9 ) . Under these circumstances, the deflection of the write beam in the DISPLAY MEMORY is controlled by the PROCESSOR. Note that C3, the HORIZONTAL RAMP GENERATOR card has one other input (see Figure 3-6). This input is used w hen the LIGHT PEN is in a WRITE or ERASE mode. It causes the horizontal deflection voltage to pause for the duration of the LIGHT PEN pulse, thus producing no motion of the writing beam at this time. An explanation of this operation is discussed in Section 3.2.2.1.3. 3.2.2.1.3 Blanking and Gating Circuits Composite EIA blanking is supplied to the MEMORY CONTROL UNIT at connector JU8. This signal is applied to the BLAMING AMPLIFIER and BUFFER circuit on card CI. This circuit changes the level of the BLANKING signal to the level required by the GATE input of the MEMO-CORDER storage units. The GATE input of the storage units is used to unblank the writing beam during each horizontai trace ^ ^ unblanking signal appears at connector jUl and drives the POINT, ERASE and TEMPORARY MEMORY gaxe inputs. The gate input of the DISPLAY MEMORY normally receives its unblanking signal through the DISPLAY GATE CONTROL RELAY oncard Ck. This is the same gate signal as that supplied to the other memories. However, when the LIGHT PEN is In the CONSTRUCT mode and the processor is in the EXECUTE CONSTRUCT READY state, the GATE CONTROL RELAY is energized and the gating signal for the DISPLAY MEMORY is obtained from the DISPLAY GATE GENERATOR circuit on card r 5 T he DISPLAY GATE GENERATOR circuit develops an unblanking voltage output .hich depends on the magnitude of the deflection signals from the PROCESSOR. In this vay, the writing beam intensity in the DISPLAY MEMORY Is reduced as the magnitude of the deflection signal from the PROCESSOR decreases. The reduction of the beam velocity vhich accompanies a decrease in pattern -32- size at fixed frequency necessitates this lover beam intensity. If the beam intensity is not reduced, small patterns will be smeared. A vertical blanking pulse is supplied to the MEMORY CONTROL UNIT from the CAMERA CONTROL UNIT at connector 1^9 • This signal is applied to the VERTICAL BLANKING LOGIC DRIVER circuit (also on card Cl) . . Here it is changed to system logic levels and sent to connector J66 to supply the PROCESSOR with pulses at television field rates. See Section 3. 3. 1.1 for an explanation of the use of this signal. 3.2.2.2 Logic and Video Circuits 3.2.2.2.1 ERASE Modes 3.2.2.2.1.1 TOTAL ERASE Functions Complete erasure of any one or all of the four memory storage units is accomplished through operation of the appropriate button on the DISPLAY CONSOLE. Selective erasure of the POINT and DISPLAY MEMORIES is possible and is described in Sections 3=2.2.2.1.2, 3.2.2.2.1.3 and 3.2.2.2. l.U. For complete erasure of the POINT, DISPLAY, ERASE or TEMPORARY MEMORY, the operator depresses the POINT, DISPLAY, ERASE or TEMPORARY erase button on the DISPLAY CONSOLE. This generates a logic signal in the DISPLAY CONSOLE JUNCTION BOX (Figure 3-7) vhich is sent to the MAIN CONSOLE and the MEMORY CONTROL UNIT through the interconnecting cables and the MAIN CONSOLE JUNCTION BOX (Figure 3-8). These signals appear at connector J2 5 of the MEMORY CONTROL UNIT on pins C, D, E, and F. Complete erasure of the POINT MEMORY vill be described as typical of the four memories. In the following discussion, refer to Figure 3.9. The logic signal generated at the DISPLAY CONSOLE JUNCTION BOX appears at connector J25, Pin E. This logic signal is sent to a NAND circuit on card BIO vhich is used as an OR circuit. Thus a logical zero at either pin 9 or pin 10 of card BIO causes the 150 millisecond RELAY GATE circuit on card Bll to be triggered. This -33- o t $ co _J t- o < or o I- o n "3 n i> _i S110A 9- UJ o a. T CO l- _i o > o 1-1 + ~3 X — OQ < o o or z JONTROL CHES P uj FROM C swn swn FILT -3 UJ H t ° — uj uj _J o u. sivnois noaiNOo OQ < Z UJ ~3 X o CQ o pq o p. o CQ o o Si <2 3 o S CO Jh «J0 ca •H Q ■H t) + 2 (Y 2" Y 1 ) Y l + Y o Y -_ sin(cot) + ■ 2 - ! 5 -1+8- The means for generating these equations is illustrated in Figure 3-H« The Appendix contains a list of all logic signals used in the PROCESSOR and a brief explanation of each. Here the internal operation of the PROCESSOR control circuits will he explained in terms of these logic signals. Operations within the PROCESSOR will be described in detail for each mode of ARTRIX. 3.3.I The Digital Section of the PROCESSOR 3.3.I.I Synchronizing Signals When the operator turns the system on, the PROCESSOR begins several continuous operations. These are: providing a digital count corresponding to the horizontal and the vertical position of the electron beam in the DISPLAY, and providing synchronization for the entire ARTRIX system. Synchronizing signals are supplied to the CAMERA CONTROL UNIT, the PROCESSOR contains an 8.O6U MHz oscillator, designated TM, which goes through a phase adjusting circuit to form the HORIZONTAL TRIGGER clocking pulse, designated TH. (TH^A^gHM-CS-tA^gHM)™) . Phase adjustment is necessary because the synchronizing frequence required by the television CAMERA CONTROL UNIT is twice the television line frequency. If the phase were not monitored and corrected automatically, the CAMERA CONTROL UNIT could be synchronized in error by one half a television line. The TH clocking pulses are counted down by the HORIZONTAL MASTER COUNTER (HM) which has 9 bits. The output of its last state corresponds to the television line frequency. The vertical count corresponding to the vertical deflection of the television system is contained in the VERTICAL MASTER COUNTER ( VM) . Because of interlacing, there are even and odd fields. Consequently, the VM COUNTER counts by twos and the least significant bit corresponds to an even or odd field. There is one other condition to be satisfied. The VM COUNTER must overflow during vertical blanking (VB) and wait until -k 9 - ij > X < ^ i? Q < 2 < 3 3 2 in ill +i -d +- m z 5,5 +',? _«1 «> 2 1 u la s si > 2 8 _l < Z < J 5 D + M t O ra 2 CO »n pq O Ji N o K X EH S ID EH H H HI K m 3 < bD 0! °H ^ d N out n ul i hi (V Jo. ->7 i £ »< y < *s h 7 a! I- o r^ ti) ii "/ u a ^ V) j i J h u s< 5 D a oo Q < in ill «* vn j < vl > VJ u U Q -50- the end of the VB before continuing. This is necessary since the VM COUNTER has 9 stages (512 counts, one count per line) whereas there are 525 television lines including VB. Overflow is accomplished by forming the VERTICAL TRIGGER clocking pulse, TV = ^HM(A i _ g VM+A) where QoHM is the line frequency, A- gVM is the VM overflow signal, and A is the output of a flip-flop. This flip-flop is reset by A-_gVM and set by the trailing edge of the VB signal. To get the VM COUNTER to count by twos, the TV clocking pulses are fed to the second stage (from the low order end) . To get the least significant stage to correspond to the proper field, the signal E=QqHM-QHM and E are formed. These signals drive the J and K sides of a J-K flip-flop which is triggered by the VB signal. Due to delays inherent in the CAMERA CONTROL UNIT, the television synchronization pulse generated therein lags the synchronization pulse from the PROCESSOR. The synchronization signal from the PROCESSOR is generated as QgHM-Q HM to compensate for these delays. 3.3.1.2 Control Flip-Flops Depressing the CONSTRUCT button has no direct effect on the PROCESSOR. The operator selects a PROCESSOR mode by depressing the CIRCLE or LINE mode button. These two buttons set opposite sides of an R-S flip-flop whose outputs are CR (for circle) and CR (for line). These are two primary logic signals which, in addition to performing control functions, light the CIRCLE or LINE indicator on the PROCESSOR rack. In either the CIRCLE or LINE mode, when the RESET PROCESSOR button is depressed, the logic signal OP-RP resets five R-S flip-flops. In addition, this signal serves other logical functions, for example, resetting the ER COUNTER. Two of the flip-flops are the overflow flip-flops (0F1 and 0F2) . The outputs of these flip-flops are used to reset the HP , VP , HP 2 , and VP g COUNTERS. These outputs are also used to generate control signals for these counters. 0F1 and 0F2 are set -51- * o™ , m ( , e . when the ^ Md ^ cQm overf ^ simuitane , ^ De f nning " ^^ ^' The other three fli p - flops are used -hen points are indicated by the operator. After the PROCESSOR has been reset +h* n. + . CIJ reset ; the operator may ideate construction points. Points are indicated by directing the LIGHT PEN to a point on the DISPLAY, whlch ls stored ^ 8 POINT MEMORY, and pushing the ENABLE button on the LIGHT PEN One " UlSS " S6nt t0 thS PR ° CESS0R eaCh tiMe the E » M b "«°" is depressed us the LIGHT PEN "sees" a point. In the PROCESSOR the first of T three flip-flops mentioned above is set by the leading edge of the first pulse, the second flip-f lop ls set by ^ ^^ ^ ^ ^ *»* pulse, and the third fli-n-f-irm ■?.-, *. t_ ,, flip flop ls set by the leading edge of the second pulse. Thus, the first of these flip-flops (P ) inrlT, + ^^ ii-ops [f ) indicates when POINT 1 nas been indicated and the fhiwi f-p \ ■ ,. e thlrd (P 2 } lndl cates when POINT 2 has been greeted. All five flip . flops „ ^ ^ ^ ^ r e are other condition, under which they can be reset. The 0E1 and flap-flops are reset by the operator whenever the PROCESSOR or POINT 1 ' ZZT' FliP " fl ° PS ° P1 and P 2 are «» t whenever the PROCESSOR or -rU-LiMi d is reset. 3-3-1-3 Counter Operation . ln „ In ^ follo ™8 Paragraphs the operation of each counter will be explained for the LINE and CIRCLE modes. The HORIZONTAL POINT 1 COUNTER (HP) contains a binary number corresponding to the horizontal position of POINT 1. When the operator resets either POINT 1 or the PROCESSOR, 0? becomes a logical one until the beginning of a frame. This signal is used to reset I 1 : Z 1 c + omts the sisnai ™ ; ih = v° p i is the ° m s ^- mas, HP starts counting from zero (having been reset) at tv. >, ■ • ~p „ * & leseu; at tne beginning of a frame and stops when P ± is indicated. The VERTICAL POINT 1 COUNTER (VP ) contains a binary number corresponding to the vertical position of Point 1. vp counts slgnal Ty -52- and is controlled by SV«|H'(3F) + A^gVP.^ When (^ is a logical "zero", VP will count until the output of its eight most significant stages are all zero. At the beginning of the next frame, it counts until POINT 1 has been indicated. The (OF^) signal insures that VP ] _ has been completely reset before it begins counting. The least significant bit is clocked by the VB signal and controlled by a signal E which indicates the even and odd fields of a frame. The HORIZONTAL POINT 2 COUNTER (RPg) contains a binary number uhich corresponds to the horizontal position of POINT 2 in the CIRCLE mode. In the LINE mode, the binary number corresponds to the magnitude of the difference in the horizontal positions of POINT 2 and POINT 1. Similarly, HP g is reset by OT gJ counts TH, and is controlled by t)H=OF -P (CR+P ) . When POINT 2 or the PROCESSOR is reset in the CIRCLE mode, HP is reset and starts counting at the beginning of a frame and stops counting uhen POINT 2 is indicated. When POINT 1 and POINT 2 or the PROCESSOR are reset in the LINE mode, HPg is reset and starts counting when POINT 1 is indicated and stops counting when POINT 2 is indicated. If Pg is reset and P 1 is not, HP 2 starts counting at the beginning of a frame. Note that if the horizontal deflection of POINT 1 is larger than that of POINT 2, HP 2 is the complement of the difference in deflections. The VERTICAL POINT 2 COUNTER (VPJ contains a binary number corresponding to the vertical position of POINT 2 in the CIRCLE mode. In the LINE mode, this number corresponds to the magnitude of the difference between vertical deflections of POINT 1 and POINT 2. Similarly, VP counts signal TV and is controlled by T|V=r|H° (OF ) + A-_gVP 2 . Thus uhen OF becomes a logical "zero", VP 2 counts until the outputs of its eight most significant stages are all zero. It then stops counting until the beginning of the next frame when it starts counting according to tjH . The (OF ) term insures that VP g starts counting only after it has been reset to zero (i.e. completely reset). Since the VP g control signal contains a term tjH, it counts as explained above for HP 2 . Like VP^ the -53- least significant stage of VP., is clocked by the VB signal and is controlled by $ , CR E + CR ^ and „ CR-E + CRT, Ron even and odd frames respectively. In the OTPrT"F mnHo iro j j-xj une oxkujH mode, YP^ operates like VP . In the LINE mode, POINT 1 and POINT 2 are separated by an even number of -ines for an even number of fields and an odd number of lines for an odd nUmheT ° f fields > ^dependent of the field (even or odd) in which POINT 1 -was indicated. The ER COUNTER contains a binary number corresponding to the radius of the circle_to be constructed. It counts signal EF and is controlled by CR-P^RS. RS is the output of an R-S flip-flop which ls reS et by PROCESSOR RESET or RADIUS RESET button and is set by coinc ' coinc *' P l ' P 2 ( 1,e -> when a circle of expanding radius cen- tered at POINT 1 goes through POINT 2) . The ER COUNTER will begin counting again when the RADIUS RESET button is depressed. 3.3.1.** Slope Control Circuits Other PROCESSOR control circuits determine the sign of the difference between the deflections of POINT 1 and POINT 2 in the LINE mode of operation. In the horizontal case, for example, it is necessary to determine whether HP^ is positive or negative. An R-S flip-flop is reset by A^h^ (i.e., HP 2 ls reset, implying that the horizontal deflection of the system corresponds to the contents of HP r ) and set by A^HM^ (i.e., when HM is set to zero, implying zero horizontal deflection) . Thus the output of the flip-flop is a logical "zero" when HP^ is positive and is a logical "one" when HP 2 -H Pl is negative. The output of the flip-flop is ANDed with CR to ensure that it is a "one" only in the LINE mode. The results are CH and CH. Similarly, in the vertical case, it is necessary to determine whether VP^ is positive or negative. This is accomplished in the same manner as for the horizontal case. An R-S flip-flop is reset by '- -5h- (A- nVP ) °MMr . MMr is the output of a monostable multivibrator which is triggered by the one to zero transition of Qg HM. The output duration is apprximately 125 nanoseconds. This is necessary to eliminat erroneous pulses in A- gVPg which arise because YP^ is a ripple counter. The R-S flip-flop is reset when the outputs of VP are all zero (except for the least significant bit) and the vertical deflection corresponds to the contents of VP . The flip-flop is set by (A-_g VM) (MMV) (P 2 ) , that is, when VM is set to zero, implying no vertical deflection. Thus the output of the flip-flop is a logical "zero" when HT^-fO^ is positive and is a logical "one" when HP -HP is negative. The output of the flip-flop is ANDed with CR to ensure that it is a "one" only in the LINE mode. The results are CV and CV . 3.3.1.5 Miscellaneous Circuits The signal CHG = A HM + A VM may be used to present a grid raster on the MONITOR. The switching network of the PROCESSOR provides the signals for the DCVGLA. The i th input to the HORIZONTAL DCVGLA is given by H.=CH°Q..HP + CH'Q. "HP + CR-Q. 'ER. The i th input to the VERTICAL DCVGLA is given by V.=CV-Qj_-VP 2 + CV-Q 1 -VP 2 + CR-Q^ER. The digital signals for the D/A converters are taken directly from the appropriate counters. The remaining circuits in the PROCESSOR deal with the interaction between the PROCESSOR and other parts of the system. When the EXECUTE CONSTRUCT button is depressed by the operator, the construction being : generated is written into the MEMORY by the PROCESSOR WRITE GATE signal (PWG) . This happens only when the PROCESSOR is ready to execute the construction. The EXECUTE READY signal is given by XR=CR«P *RS + CR-P T . The PWG signal is the output of an R-S flip-flop which is set by (OP-XC) -XR and reset by ^OP-XC) . Using an R-S flip-flop eliminates the contact bounce of the manual push button switch. -55- The PR signal indicates uhen the PROCESSOR has been reset and is given by PR = p .p .p 1 2 s 3-3.2 Hybrid Section of the Processor The hybrid section of the PROCESSOR is shovn in Figure 3 12 All control inputs are from the digital section of the PROCESSOR and are m the digital form. All outputs (except those from the comparators) are analog, and go to the DISPLAY MEMORY via the DEFLECTION CONTROL RELAY in the MEMORY CONTROL UNIT. Solid arrows represent analog signals and open arrows represent digital signals. In the following discussion, ARTRIX is assumed to be in the CONSTRUCT mode of operation. 3-3.2.1 Circle Operation When the PROCESSOR is in the CIRCLE mode, sine and cosine waveforms are selected by means of relays and the logic signals CR, CV, and CH. Flgure ,.„ sh0 . JS thg comWnatlon Qf these ^^ ^ form a circle in the MEMORY. The cosine wave is applied to the vertical channel and the sine.ave is applied to the horizontal channel. Waveform manipulations are performed in each channel using horizontal and vertical digital inputs. The gain of the vertical channel is only 3 /l» that of the horizontal channel. This preserves the 3:1 aspect ratio of the television MONITOR. The analog signal necessary for circle generation are: X = R sin(wt) + X Y = R cos(-wt) + Y X x and Y 2 are voltages corresponding to the position of the center of the circle. The digital signals H^ and V^ corresponding to these voltages are generated as described in section 3. 3. 1.3. HP and VP 1 are now applied to the number 2 HORIZONTAL and VERTIAL D/A CONVERTERS. The output of these D/A converters are two DC voltages corresponding to HP., and VP r The radius of the circle is determined by coincidence. The sine and cosine voltages are applied to an amplifier ■ 5 6- 2 z o M o X >- UJ < _l CO Q -H 0. X oo o o^ z OO £o~< o°4 s« or ^ O Q X < § tr < y Q U. "urn 8^1 lo K O CO CO w o o •H ft 3 CD d •H CC Ld UJ o CD CO < T Q- X CO ■57- OSCI LLOSCOPE VERTICAL INPUT Rcos(u>t) + HP Figure 3.13 Generation of a Circle with Sine and Cosine Functions -58- whose gain is proportional to a given digital input. This is the Digitally Controlled Variable Gain Linear Amplifier, designated as DCVGLA. The digital inputs to the horizontal and vertical DCVGLAs are identical and are stepped from to 5U when the center of the circle and POINT 2 have been indicated. The outputs of the DCVGLAs are then sinusoids whose amplitudes increase with time. These outputs are mixed in the DC and AC MIXER and AMPLIFIER with signals X ± and X g in the horizontal and vertical channels, respectively. The number 1 VERTICAL and HORIZONTAL D/A CONVERTERS are disabled by CR and CR in the circle mode. The output of the MIXER is a sinusoid, whose amplitude increases, with a DC offset. The indicated point on the circumference of the circle is similarly converted by a D/A converter (0) to a DC level corresponding to the coordinates of that point. These two DC levels are then compared with the sinsoids whose amplitudes are increasing. The desired radius is reached when the amplitudes of both sinusoids equal the DC levels (or coordinates of POINT 2) simultaneously When this coincidence occurs, a logic signal causes the RADIUS COUNTER to stop. In other words, the circle expands about its center until the indicated size (designated by the HP 2 and VP 2 ) has been reached. 3.3.2.2 Line Operation As in the CIRCLE mode, logic signals CR, CV and CH select sine or minus sine functions for line generation. (Actually, the selection of sine or minus sine, depending on the slope of the line, is not determined until POINT 2 is indicated). Figure 3-1^ shows the combination of these signals to form a line. The CR and CR signals enable both the #1 and #2 D/A CONVERTERS whose outputs go to the DC and AC MIXER and AMPLIFIER. When POINT 1 is indicated, signals VP 1 and HP are available and are applied to the D/A CONVERTERS. The outputs c/the D/A CONVERTERS are fed to the MIXER. The output of the MIXER then corresponds to the coordinates of the first endpoint of the line (POINT l) . a o •H -P O a B QJ G •H CO H 13 CO > H Eh M CO o Ph -P »H 1-3 O o ■H -P CO 0) a OJ C5 -=t- H M s -60- Recall the equations of a line from section 3-3.0: ( X 2- X l } ,. , X l +X 2 X = ^ x sin(wt) + —3 — (VV , , Y l +Y 2 Y = ■ 2 X sin(wt) + — g— It is evident that "POINT 2 must now be indicated to give the digital signals (H^-HP^ and (VP^vT^) . These signals are applied to the DCVGLA to give the proper sine-wave amplitude, and to the #1 D/A CONVERTERS to give the proper DC offset. This keeps the line from extending through POINT 1. All three output signals are then of the form required for line generation, and are applied to the deflection plates of the DISPLAY MEMORY. No use is made of HPg and VP D/A CONVERTERS in the LINE mode, and comparison methods are not required. ■61- u . Conclusions u .1 Summary The fundamental objective of the ARTRIX project ,as to Prove the feasibility of a self-contained hybrid graphical processing system. The project ,as carried out on a relatively low cost scale since a separate digital computer was not required for information processing. One of the difficulties encountered with ARTRIX was that of resolution. The upper limit on the resolution of ARTRIX vas poorer than had been anticipated. The minimum achievable line *idth was 3 television lines for free hand drawings, and 2 television imes for constructions. The principal factor limiting the system resolution was the Memotron storage tube In the Memotron-Vidicon memory device. Under optimum conditions, the best posible resolution of the Memotron storage tube is 5 lines per inch, which when displayed on a television screen having a y.k aspect ratio, corresponds to about 280 total television lines. Under actual operating conditions however, this figure was more realistically about 200 lines. Had another method of storage been used, the resolution might have approached that of digital systems. It is significant, however, that in spite of the poor resolution, the cost and bulk of a core memory and its associated input and output equipment, or the cost and bulk of other means of storage for that matter, would far exceed that of the Memotron-Vidicon storage technique. The Memotron and its required circuitry were readily available as a packaged unit, the MEM0-C0RDER and in combination with the Vidicon camera unit, provided obvious advantages as a small, self-contained, ready-built storage unit. The most frustrating, though by no means insurmountable problem was misregistration of points, drawings and constructions due to drift in DC levels within the system. . It was found that this drift problem was minimal when sufficient warm up time was allowed. -62- The time required however, vas about 1.5 hours. The most probable sources of drift error within the system were the camera control units and the DC hybrid circuits. Improved temperature stabilization of the camera circuitry would probaly improve the system performance considerably. The hybrid approach to the design of ARTRIX vas highly successful. Aside from occasional misregistration, the CIRCLE and LINE modes of ARTRIX functioned admirably. The method of digitizing the television raster into X and Y coordinates and digitally controlling analog signal generators to produce lines and circles resulted in far more accuracy than the corresponding system resolution. The entire PROCESSOR was based on 500 television line resolution when, as stated above, the maximum system resolution was 280 lines. The most significant advantages of the hybrid design over an all-digital design are low cost and relatively few components. Clearly, circle and line generation using Lissajous patterns is a trivial exercise compared to circle and line generation by digital means. Higher order curves would, of course, require more complex Lissajous patterns. The control of video information between the memories and the DISPLAY, and the processing of the LIGHT PEN pulses presented no major problems, contrary to original anticipations. Delays between the video signals were insignificant and required no compensation Writing points in the memories within the capabilities of the Memotron tubes was accomplished using the beam-hold technique described in section 3.2.2.2.2.1. The ERASE mode of operation functioned somewhat less than satisfactorily for reasons not clearly understood at this time. It vas throught that much information was being lost during the transfer process since the beam-holding technique could not be employed in transferring information between Memo-Corders during the erase cycle. It was found, however, that this was not the significant problem. It -6 3 - has been determined that information is transferred to the TEMPORARY MEMORY successfully, but fails to be rewritten into POINT or DISPLAY MEMORY. In spite of the most degrading aspect of ARTRIX that of resolution, the ARTRIX project was generally very successful. I„ its final form, ARTRIX produced lines, circles and on some occasions erasures, with precision and regularity surpassing the expectations of its designers . ^2 ^Recommendations An interesting project would be the design of an all-analog system using capacltive storage techniques in place of binary counters to store coordinates of lines and points. With high input impedance devices such as operational amplifiers and field effect transistors it is felt sufficiently long storage times, with readout, would easily be obtained. In such a system, the linear ramp deflection voltages might serve as coordinate references. In contrast, an all digital system, while easily constructed due to the high degree of development in digital design, provides unnecessary accuracy at a premi™ cost. As in digital systems, the greatest need in ARTRIX is an improved storage mediur, for pictorial information . Several semi -analog devices which might be considered as alternatives to the Memotron-Vidicon combination are the scan-converter tube, the tape recorder or the disc recorder. Although the scan-converter is unsurpassed with respect to resolution, its usefulness is limited by its relatively short storage time. Typical storage times are from three to five minutes. Furthermore, poor registration between the read and «rite modes is a limiting factor for accurate local erasure. A video tape recorder with sufficiently high resolution vould be an alternative were it not for its lack of any selective erase capability. Its storage time is, of course, virtually unlimited. -61*- The video disc recorder is the most promising alternative, providing its resolution is sufficiently high. Multi-track disc recorders are available with selective erase facilities. The multi- track feature would be extremely advantageous in a system such as ARTRIX, where more than one memory unit is required. Also additional tracks can be added to the disc recorder at a nominal cost. -6 5 - APPENDIX -66- A1.0 Power Distribution System Al.l AC Power Distribution Figure Al.l shows the AC PANEL and the AC ON-OFF PANEL. All AC power supplied to ARTRIX is controlled by the relay located in the AC PANEL-. This relay will operate if the AC ON-OFF switch is in the ON position and the VOLTAGE MONITOR (located in the MAIN JUNCTION BOX) senses no irregularities in the DC supply voltages. (For turn-on the VOLTAGE MONITOR is bypassed. See Section Al.j) . If these two conditions are met, the relay in the AC PANEL energizes. This applies AC power to the three AC strips in the MAIN CONSOLE and to the AC strip in the DISPLAY CONSOLE (see Figure A1.2) . The transformer in the AC PANEL supplies the AC ON-OFF indicator light with power. The ON-OFF indicator is controlled by the ON-OFF switch. The VOLTAGE MONITOR (see Section A1.3), in addition to monitoring the D.C. power supplies, also monitors the supplies in the CAMERA CONTROL UNITS and the MEMO-CORDERS . The sensing lines for this operation are on connector P80 as shown in Figure Al.l. A1.2 DC Power Distribution The DC power supplies all operate when the AC power is applied. The outputs of the supplies go to the MAIN JUNCTION BOX (Figure Al-3), where the voltages are distributed to the MEMORY CONTROL UNIT, the PROCESSOR and the DISPLAY CONSOLE. These voltages are monitored at the MAIN JUNCTION BOX. The DC power is distributed in the DISPLAY CONSOLE by the DISPLAY CONSOLE JUNCTION BOX (Figure AX.k) . The ARTRIX system uses six DC power supplies to supply the following voltages: -5, +10, -15 and +25 volts . A1.3 The VOLTAGE MONITOR The ARTRIX VOLTAGE MONITOR was designed to provide the system with a self-contained safety device for the protection of the -68- , H Ii»s ,„, | lU'JIIII ' »u»fllA ■■WWII II W>>WI\ m..-\ I xiaiav 30K3DS eJinanoo i° iNMiumjo M' : \ TJ^J —Li i o o o o o o ■6 9 - x a o H B H O 6 g (0 •H P 13 0) ■H ■H H CO H < P"h -70- S1VN9IS HOIVOIONI U3M0d oa T -3 CO H _J O > o r-» + X ><; z° _ CD o < a s § o H EH 2h oo cc z Lj_ 3 "3 w 1-3 U a o a ~3 CO CO z , cc CO UJ UJ UJ _J CD < Z UJ < — HI Ht ° — UJ LU o^ o H> -J _l o u_ ONTROL CHES in ~3 SWITCH FILTER ROM C SWIT sivnois iohinoo ~3 X o CO ~3 Jx •71- equipment within the system. Although it does not have a 100 per cent fault detection capability, it does give a high degree of protection to the more critical sections of the system, such as the storage tubes, cameras and the circuitry of the PROCESSOR and MEMORY CONTROL UHIT, The VOLTAGE MONITOR circuit (Figures A1. 5 and A1.6) consists of three basic sections: a VOLTAGE SUMMING CIRCUIT, a DIFFERENTIAL AMPLIFIER, and a LOCK-OUT RELAY. Some additional features will be described below. The SUMMING CIRCUIT is a resistive adder containing a precision resistor for each sense line connected to the VOLTAGE MONITOR. The sense lines are attached to the selected monitor points, such as the logic power supplies, camera power supplies and MEMO-CORDER power supplies. The resistors are selected to provide a 1 milliampere load for each monitored voltage (for example, monitoring 5 volts requires a 50 k resistor, 2 5 k resistor, etc.). These resistors are connected to a common point. When all the input voltages are present and adjusted, the currents at the common point sum to produce about volts. The change of, or the lack of any of the sensed voltages will cause a change in the voltage level at the common point. The common point of the SUMMING CIRCUIT provides one of the two inputs to a DIFFERENTIAL AMPLIFIER. The otner input is an adjustable DC voltage. After the system is turned on and adjusted, this DC voltage is adjusted to the same voltage level as that of the common point of the SUMMING CIRCUIT. This will balance the DIFFERENTIAL AMPLIFIER, resulting in zero ouput . The output of the DIFFERENTIAL AMPLIFIER drives a relay. The relay is connected such that it latches on its own contacts once closed, hence the term "lock-out". Any detected change of the sensed voltage levels will energize the LOCK-OUT RELAY. One set of contacts on the LOCK-OUT RELAY is in series with the AC ON-OFF SWITCH. Therefore, any detected change in the monitored voltage will shut down the system. -72- \l il SiJ -v^-@- -w^ ■^A@-@- POT -^-i-@- lift < £ 8 Q. §«! 30 iD t a" — , , W n.d U[ ^ s ?!< zX M« J. — v_^v — ■ li H a> S> H s l n si s'. 9 9 9 9 9 9 Y Y a 46466666 I i< si si «i «'. 9 9 9 9 9 9 If s-s £ 5 1 „• Tza w •H W W o <& o EH H g < P o > < V h p IJ 1 l| J J *r -73- An alarm horn is connected to the VOLTAGE MONITOR such that a detected malfunction vill provide an audible tone, alerting the operator. A MUTE button is provided to silence the alarm once the operator has become avare of a malfunction. A MUTE INDICATOR uarns of the muted condition. Since protection is not provided in the muted condition, the VOLTAGE MONITOR must be reset after the malfunction is corrected. The system .as found to be more stable if it operates continuously and is not shut dovn overnight (see Section A^.l). It is conceivable that a fault could occur uhile the system is unattended. A 60-second time delay relay .as installed .hich mutes the horn after the elapsed time. Should a lock-out condition occur vhile the system is unattended, the possibility of the horn sounding for hours at a time is thus eliminated. The VOLTAGE MONITOR has a self-contained peer supply uhich is n ot disabled by an automatic shut doun of the rest of the system. It should be noted that a manual shut dovn appears as a fault to the VOLTAGE MONITOR, causing a lock-out condition. It is necessary, therefore, to have a VOLTAGE MONITOR BYPASS SWITCH on the VOLTAGE MONITOR panel. This s.itch must be set in the BYPASS position in order to pouer up the system. The suitch may then be returned to the NORMAL position. A2.0 Description of Circuits A2.1 DIAMOND GATE, l^-l^A The DIAMOND GATE circuit is an analog gating circuit •which uses a conventional diode bridge configuration. It differs from conventional analog gates, however, in that the bridge is biased on by a current source and sink. Turning off the DIAMOND GATE is accomplished by shunting the bias current around the bridge . This circuit is topologically the same as the diamond gate employed in the PARAMATRIX system. For more details see "Hybrid Circuits for the Paramatrix System" by Edward F. Prozeller, Report No. 188, Department of Computer Science, University of Illinois, Urbana, Illinois, September 1, 19^5 • A2.2 DCVGLA (Digitally Controlled Variable Gain Linear Amplifier) 1^69-102 The DCVGLA controls the amplitude of a sine-wave by means of a digital input. There are 512 increments corresponding to 9 digital bits. A mathematical transfer function for this device ■would be as follows: X = Ksin r o i 2 8] (art) A d 2 U + A x 2 + A 2 2 + . . . + Ag2 ] where a Q ao are the binary inputs, K is an arbitrary gain constant and X is the output. The output has a peak to peak variation from zero to + 10 volts. A gain constant of K ~ 1.5 is used which requires a 6.67 volt peak input sinewave . Currents are summed through resistors to obtain the above function. The resistor values are in the ratio of 2 : 2 : 2 : . .»t2 Transistors switch these resistors in and out of the circuit. The scheme is similar to that in a D/A converter, except that an AC voltage is converted instead of a DC voltage. The digital control of the -75- voltage is independent of the phase and amplitude of the AC voltage. A basic diagram of the scheme used is shown in Figure A2.1 and the actual circuit used is shown in Figure A2.2. The constant controlled voltage source in the circuit is an emitter follower whose emitter resistances are the digitally selected resistors. A Darlington configuration of the transistors was chosen to make the impedence of the source as low as possible. This gives the circuit a curren gain of about 0^ whfire p and P 2 are the respective betas of the 2N2102 and 2N3054 transistors. This proved to be adequate for variations in the emitter resistance from R Q /2 to open circuit. A DC bias current is used to keep the transistors in the active region. The 8 Hy coil in series with the bias resistor appears as an AC open circuit at 10 KHz. Current is sensed at the collector of the Darlington pair. A transformer is the current detection device. It provides complete DC isolation from the rest of the circuit, gives large voltage gain, and provides the required impedence match. The AC resistance in the collector is small compared with the minimum AC resistance in the emitter. The load on the secondary of the transformer is 10K ohms. The turns ratio of the transformer is such as to present 3 ohms in the primary; 3 ohms in the collector is small compared with a minimum of 100 ohms in the emitter. Using this value as a reference, the R Q in the digital emitter chain was chosen close to 200 ohms. Since it is difficult to procure precision resistors such that R Q is 200 ohms + 0.1$, and since the saturation resistance of the transistor switch would add an even greater error, it was decided to use adjustable resistors in the first six most significant bits of the chain. For the lasyhree bits 1# resistors were found adequate, and at this value (2 R Q ) the saturation resistance of the transistors is also negligible. The resistance chain is adjusted such that any two adjacent bits provide an output voltage in the ratio of 2:1. The switching in -76- < 3 o o i o CO CJ •H CO — H < M •H — (/) CO ■77- — ^w\, 1 G5u sc 2 W S H to fO < I ; T I 1 CD a C5 -78- and out of a given resistor is accomplished by a two-stage switching circuit. Two stages must be compatible with the logic levels of the digital system, and must provide the high gain needed to drive the first two most significant bits. Peak currents of the order of 200 ma flow through the transistor when switching the most significant bit. The accuracy of the system is one part in 512, or about 0.2?*. A limiting condition in adding more bits is that the resistance of the least significant bit be less than the total parallel resistance of the backbiased collectors of all the other legs. In other words, the current flowing in the least significant leg must be greater than the total leadage currents in all the other legs. Another requirement is that the AC impedance in the bias drive under open circuit conditions must be large compared with the resistance of the least significant bit. The latter requirement limits the accuracy of the circuit. An inductance of 8 Hy provides an impedence of about 500K ohms compared to about 50K ohms in the path of the least significant bit. A2.3 Integrated Circuits , l469~103B-00, 01, 02, 03, 04 . Twelve 2-input NAND gates are mounted on the 1469-10 3B-00 card. These gates are contained in three Texas Instruments SN7400 integrated circuit packages, each of which Is a Quad 2-input NAND gate. Three single-phase J-K flip-flops are mounted on the 1469-103B-01 card, each of which is a Texas Instruments SNT^TO. Nine 3-input HAND gates are mounted on the 1469-10 3B-02 card, each of which is a Texas Instruments SNT^IO triple 3-input NAND gate. Two 4 -input NAM) gates and two 8-input NAND gates are mounted on the 1469-103B-03 card. Component A is a Texas Instruments SNT440 or SN7420 dual 4-input NAND gate, and components B and C are Texas Instruments SN7430 8-input NAND gates. Three monostable multivibrators are mounted on the 1469-103B-04 card, each of which is a Texas Instruments SNT380 monostable multivibrator. ■79- A2. 1 * D/A CONVERTER lk69-10kB The D/A CONVERTER provides a fixed DO output voltage for a given digital input. The circuit consist, of a binary chain of resistors. Each digital input switches a resistor into or out of the circuit. The currents through these resistors are then summed and a m plif led . The ^^ CQnverslon rate Qf ^ ^^ ^ ^ 2.5 MHz. A schematic of the D/A OOWTTRrmrw 4 r. 1 . ~ oiic u/r uuwvii,KihK is shown in Figure A2.5. A2-5 PC and AC MIXER and AMPT.TFTER lit69-105A The DC and AC MIXER and AMPLIFIER is a digitally controlled analog circuit. The circuit performs three functions: First, it is a precision adding or subtracting circuit of DC voltages. Second, it is a compensated differential DC amplifier. Third, it is mixer which combines the DC output voltage (DC offset) of a D/A converter with a sinusoidal voltage. It can be digitally controlled to ^rform addition of two variable voltages, or one variable and one fixed voltage. The circuit also provides a buffered output for the hybrid PROCESSOR F lgure A2.4 shows a basic diagram of the circuit, and Figure A2. 5 gives a complete schematic of the circuit rw«» *• „ ^, me circuit. Operation of the circuit is as follows In the digitally controlled DC adder and subtracter, the digital control signal corresponds to either LINE or CIRCLE operation For LINE operation, a DC voltage of the same magnitude as that of the sinusoid is added to prevent extension of the line through POINT ] Another DC offset translates POINT 1 to the proper location on The digital signal for m operatlon selects current ^^ y ^ ^ mode. Both current source^ and i 2 are controlled sources. I 1. controlled by the D/A converter which determines translation, and I is controlled by the D/A converter which determines the additional DC * offset required to prevent extension of the line through POINT 1. These two currents are then summed through R s . The voltage across R is Proportional to the sum of the currents. If one of the currents is negative with respect to a new reference, subtraction takes place -80- rli- H ^ — &■ zQ^' (i pvy>— I 1 l 1 V I s K |i- " — w— |i |i- ■■ — oHi 1 M O o < -p ■H pq OJ < 03 > + > + r-i CM O o" 1- z. Z 0. a. Z _J - 1- C_> o CO o ~ Q Q Q u When the system is in the CIRCLE mode of operation, the additional DC offset due to source I g ls not used. The digital control then selects I y which is a fixed current source equal to the quiescent value of ^ . Since this corresponds to the zero reference, it does not cause translation of the circle. It is necessary, however, since the zero reference differs from ground or zero current at this point. This fixed current reference can be adjusted to the correct value by means of a potentiometer . The controlled current sources are essentially emitter followers, whose collector currents are summed through a 2.2K ohm resistor (R ) The output of the adder is then applied to a compensated DC amplifier Vhose gain is such that a + 10 volt variation i S possible at its output. The compensation circuit ,as designed to prevent drift due to supply variations. The reference for the differential amplifier is essentially of the same configuration as the DC equivalent of the signal source. Hence, through common mode rejection, the supply variations are eliminated at the output. The sinusoids are mixed with the DC voltage levels by applying the DC to an emitter follower whose output is in series with the output transformer of the DCVGLA . The AC voltage is developed by the DCVGLA across the 10K ohm resistor and is added to the DC voltage across the emitter resistor of the emitter follower The output of this series circuit is then tied to another emitter follower, which provides a high input impedance to the mxxer and a low output impedance to the rest of the system. A2.6 DPDT RELAY, l469~106 The DPDT RELAY circuit consists of a DPDT relay and a relay driver transistor. A grounded input causes the relay to turn on. An input of -5 volts keeps the relay off. -8fc- A2.7 DELAY MULTIVIBRATOR , li+69-lOT The DELAY MULTIVIBRATOR circuit is an emitter coupled monostable multivibrator. It produces a 500 millisecond output pulse for a positive trigger input. A2.8 CONSTANT VOLTAGE SOURCE , LU69-IO8 The CONSTANT VOLTAGE SOURCE circuit is part of the DCVGLA circuit and is described in section A2.2. A2.9 Q.06k MHz CLOCK 1U69-IO9A The &.06h MHz CLOCK is a crystal controlled Colpitts oscillator with a two stage shaping circuit. The rise and fall times of the output pulses are less than 20 nanoseconds. A2.10 SYNCHRONIZATION SEPARATOR, GATE DRIVER and VERTICAL BL ANKING DRIVER ll+69-HOA A2.10.1 SYNCHRONIZATION SEPARATOR The SYNCHRONIZATION SEPARATOR accepts standard EIA negative composite synchronization at pin S and separates it into horizontal and vertical synchronization pulses. It also generates a logic level pulse corresponding to vertical synchronization. The input to the SYNCHRONIZATION SEPARATOR goes through an emitter follower which drives both the horizontal and the vertical synchronization circuits. The horizontal synchronization is obtained by differentiating the output of the emitter follower. The vertical synchronization is obtained by integrating the output of the emitter follower. Both of these signals then pass to emitter followers. The outputs are at pins P and M, respectively. The output of the vertical emitter follower is integrated again in order to remove all traces of horizontal synchronization. It is then amplified and sent to an emitter follower whose output appears at pin K. -35- A2.10.2 GATE DRIVER The GATE DRIVER accepts composite EIA blanking at pin D. This signal is amplified twice to raise it to the twenty volt level required by the MEMO-CORDER. Output at pin E is supplied by an emitter follower. The output signal is clipped and clamped to limit the overshoot and undershoot due to an unterminated cable. A2.10.3 VERTICAL BLANKING LOGIC DRIVER The VERTICAL BLAMING LOGIC DRIVER accepts the vertical blanking signal at pin F. This signal is amplified and clipped at the - 5 volt level. The output at pin H is supplied by an emitter follower. A2 ' 1:L HORIZONTA L and VERTICAL SWEEP GENERATORS . 1469-111-00 and 01 The HORIZONTAL and VERTICAL SWEEP GENERATORS supply the deflection voltages for the storage units, and are nearly identical in operation. Each consists of a synchronizing gate circuit and a linear ramp generator. Synchronization pulses are supplied to the first stage, vhich gates an asymmetric astable multivibrator. The output from the multivibrator is taken at the emitter of the transistor which is cut off for the longest duration of each cycle. During this period the ramp generator supplies a linear ramp voltage wnose maximum amplitude is variable from 8 to 2 5 volts. During the short duration of each cycle the linear sweep is discontinued by gating the ramp gener- ator off. This produces a sawtooth voltage wnose abrupt trailing edge corresponds to the retrace of the electron beams in the storage units. An astable, rather than monostable, multivibrator is employed as a safeguard in the event that the synchronization signal is lost. The beams will continue sweeping in the storage units, and not remain in a fixed position. The ramp generator consists of an adjustable constant- current source which charges a oanapirnr rr.v Q „ I6et) d capacitor. Ine generator is gated -86- off by discharging this capacitor at the end of each sweep. The deflection voltage is held constant while writing in the storage units by cutting off the transistor constant-current source. The emitter of the PNP transistor is held at a negative voltage with respect to the base for a period of 2 microseconds. The charging current ceases, and the voltage across the capacitor remains nearly constant during the cut-off period. The output stage is a highly linear emitter follower which presents a relatively high impedance to the constant current source . A2 . 12 ONE SHOT BUTTER, 1^69-112 The ONE SHOT BUFFER circuit is an emitter coupled monostable multivibrator which generates a 2 millisecond output pulse for a positive trigger input. The 330 ohm resistor and the 0.1+7 uf capacitor provides filtering, if a mechanical switch is used at the input. The output of the multivibrator is amplified and clamped. Final output is supplied by emitter followers. A2.13 VIDEO TO LOGIC CONVERTER , 1U69-113 The VIDEO TO LOGIC CONVERTER is a two stage wideband amplifier with emitter follower input and output stages. It provides a -5 volt to 0-volt transition for an input between 0.5 to 2.0 volts. A2.1U Z-AXIS DRIVER , l^-ll^A The Z-AXIS DRIVER supplies the WRITE pulses to the storage units. It supplies a negative 10-volt output pulse for any positive input pulse which exceeds 0.5 volts in amplitude. The circuit consists of an input and output emitter follower and a direct-coupled complementary NPN-PNP amplifier. The complementarity eliminates the collector delay which normally exists in the case of a -87- single transistor amplifier. The result is an output pulse whose rise and fall times are about 20 nanoseconds. The Z-AXIS DRIVER is regulated to accommodate 2-volt fluctuations in supply voltages . A2.15 INDICATORS , 1^69-115-03 and Oh Eight transistor drivers and eight bulbs are mounted on each INDICATOR card. The bulbs are mounted such that they are visible vhen the card is inserted in a card rack. The 115-03 card uses 2N130 9 transistors and a IX input resistor. The 115-04 card uses a 2N2665 transistor with a direct input. A2 * 16 VIDEO ADDER and SYNCHRONIZATION INSERTER . lk69-ll6A The sources of the video signals to be added may be considered as voltage sources due to the 75-ohm termination uhich precedes the VIDEO ADDER and SYNCHRONIZATION INSERTER circuit. The input impedance of the circuit is high relative to 75 ohms, hence there is no interaction between the video sources. The currents due to these video sources are added linearly by a resistive network, ^hich is equipped with individual video gain controls as veil as a gain control of the video sum signal. The su*> is amplified by two direct-coupled amplifier stages, and the signal then proceeds to an emitter follower. Synchronization pulses which arrive at pin 17 are amplified and pull the video signal negative at the output of the emitter follower. A potentiometer adjusts the bias of the synchronization pulse amplifier, thus providing a synchronization level adjustment. The final stage of the VIDEO ADDER and SYNCHRONIZATION INSERTER circuit is a second emitter follower. A2.17 COMPARATOR, 1^69-117 The COMPARATOR compares an increasing sinusoidal voltage With a DC voltage level. The output is a 0.2 microsecond pulse which occurs vhen the two input voltage are within 3 millivolts of each other . -88- A2.18 PEN PULSE SHAPER and MULTIVIBRATOR GATE , IU69-H8 The PEN PULSE SHAPER consists of a threshold amplifier followed by a second stage of amplification , and an emitter follower output stage. A tunnel diode is used at the input of the threshold amplifier and a series potentiometer selects the threshold level. The threshold amplifier acts as a discriminating circuit, adjusted to select those pulses -whose amplitudes exceed the threshold. The two amplifier stages are ac -coupled using a small differentiating capacitor to shape the incoming pulses. The output pulse width is between 50 and 100 nanoseconds. The pulses from the PEN PULSE SHAPER trigger the MULTI- VIBRATOR GATE, a monostable multivibrator followed by two current amplifiers. The outputs from these amplifiers are the SWEEP GATE pulse and the WRITE pulse, respectively. A2.19 DISCRIMINATOR and SHAPER , 1U69-119 The DISCRIMINATOR and SHAPER circuit is designed to provide shaped output voltage pulses at a fixed amplitude for any input signal which exceeds an adjustable threshold level. The first stage is an emitter follower which buffers the input signal. The second stage amplifies this signal after which it is applied to the discrimination stage. The discrimination level is controlled by adjusting the emitter bias of this stage. The discrimination stage provides additional gain, and the output level is controlled by adjusting the amount of base drive to the final stage, the output emitter follower. A2.20 PEN PREAMPLIFIER , 1^69-121 The PEN PREAMPLIFIER circuit is designed to amplify the pulse produced by the photodiode in the LIGHT PEN. The current from the photodiode produces a voltage across its 10K load resistor. This voltage pulse is capacitively coupled into the first amplifier stage ■89- This stage is direct coupled to another amplifier stage which is, in turn, direct coupled to the emitter follower output stage. The switch in the circuit produces the ENABLE signal when it is closed. This switch grounds the enable line going to the pen. A2.21 DC ADDER and AMPLIFIER The function of this circuit is similar to that of the DC and AC MIXER and AMPLIFIER except that there is no digital control. The circuit amplifies the DC output of the 9-Bit D/A CONVERTER and mixes it with one of the sinusoidal voltages. A2.22 General Circuit Cards . 1469-152 A2 ' 22 ' 1 PHASE SHIFTER and EMITTER FOLLOWER . 1469-152-00 This circuit is described in Section A2.23, 10 KHz OSCILLATOR and AMPLIFIER. It is used at the output of the oscillator to generate the sine, minus sine, and cosine voltage waveforms. A2,22 ' 2 AMPLIFIER and EMITTER FOLLOWER , 1469-152-01 The AMPLIFIER and EMITTER FOLLOWER circuit amplifies the incoming signal, clamps it to a -5 volts, and provides a buffered output. It is designed to restore a signal to logic levels. A2 - 22 '3 10 KHz SQUARE WAVE GENERATOR . 1469-152-02 This circuit provides a 10 KHz square wave at its output, Pin 19, when a lOKHz sine wave is applied to the input, pin C. A2.22.4 +1.7 VOLT POWER SUPPLY . 1469-152-03 The +1.7 VOLT POWER SUPPLY generates +1.7 volts from a +10 volt input level. -90- A2.22.5 EMITTER FOLLOWER , 1^69-152-OU The EMITTER FOLLOWER circuit amplifies the input, clamps it at -5 volts, and provides a buffered output. A2.22.6 EMITTER FOLLOWERS , 1U69-152-05 Emitter Followers A and B on card 152-05 are coaxial cable drivers which buffer the integrated circuits. Circuit C is designed to drive the display monitor directly. Its input is the cross-hatch grid generated by the processor intregrated circuits. Circuit D is used to shift the level of the composite synchronization signal, generated by the CAMERA CONTROL UNIT, to that of the integrated circuits in the PROCESSOR . A2.22.T PEN GATE , 1^69-152-06 The PEN GATE circuit is a collector coupled monostable multivibrator which generates a 200 u second output pulse for a positive trigger pulse input. The output is buffered by an emitter follower. A2.23 PLUS and MINUS SINE and COSINE GENERATOR , 1469-153-00 The circuit consists of four sections: a sinusoisal oscillator, an amplifier, a phase -shifting network, and an output buffer network vith amplitude control of each sinusoid. A schematic diagram of the circuit is given in Figure A2.6. The oscillator is a Colpitts configuration with emitter feedback. Since frequency stability is of no consequence, a free-running LC tuned configuration proved adequate. The loop-gain is adjusted as close as possible to unity to provide the greatest linearity. A frequency of lOKHz is used so as not to exceed the response time of the ARTRIX COMPARATOR circuit. Also, at this frequency any third harmonic distortion does not pass through transformer used in the phase-shifting network and the DCVGLA. The amplfier is a single ended class A configuration with a transformer output. The only caution to be observed is that of not saturating the transformer. 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UJ EL -103- A3-2.0 Memory Drawings -10>+- A3-2.1 MEMORY CONTROL Card Rack List RACK A SPACE 1 IMUlvLDrJA 1U69-118A-00 2 1U69- iUa-oo 3 1U69- iUa-oo 1+ 1H69-113A-00 5 11+69-11^-00 6 1U69-11UA-00 7 1U69-116A-00 8 1U69-118A -00 9 1U69-152 -Oh 10 11+69-152 -03 11 11+69-1^2 -06 12 1U69-119 -00 13 1U69-119 -00 lU 11+69-119 -00 15 11+69-119 -00 NAME PEN PULSE SHAPING CIRCUIT and MULTIVIBRATOR GATE DIAMOND GATE DIAMOND GATE VIDEO to LOGIC CONVERTER Z-AXIS DRIVER Z-AXIS DRIVER VIDEO ADDER/SYNCHRONIZATION INSERTER VIDEO ADDER/SYNCHRONIZATION INSERTER EMITTER FOLLOWER +1.7 VOLT POWER SUPPLY PEN GATE MULTIVIBRATOR DISCRIMINATOR and SHAPER DISCRIMINATOR and SHAPER DISCRIMINATOR and SHAPER DISCRIMINATOR and SHAPER -105- RACK B SPACE NUMBER NAME 1 1U69-115 -03 INDICATOR 1U69-112 -00 ONE SHOT BUFFER 3 lh6 9 -W3B-00 2 _ Input mm 1^6 9 -103B-00 2-Input NAND 5 1U69-103B-00 2 . Input mm 1^6 9 -103B-01 j. K F i ip . Flop 1469-103B-01 j. K Flip _ Flop 8 1U69-103B-02 >Input NMD 1^69-115B-03 INDICATOR 10 1469-103B-00 2-Xnput NAND 11 1^69-107 -00 RELAY GATE 22 1^69-103B-00 2-Input NAND 13 1^69-l6UB-00 mercury relay lb 15 1U69-173 -00 KELTER 16 1^69-152 -01 Emitter Follower -io6- RACK C NUMBER NAME ll+69-HOA-OO SYNCHRONIZATION SEPARATOR/GATE DRXVT2R/VERTI CAL BLANKING LOGIC DRIVER 2 ll+69-lllA-OO VERTICAL SWEEP GENERATOR 3 1U69-111A-01 HORIZONTAL SWEEP GENERATOR 1+ 1)469-106 -00 DPDT RELAY 6 1U69-152 -07 DISPLAY GATE GENERATOR -107- ""■" 1 3M3IK MlfMK» |1 J03BUIW30 Mlfl IS' Eh hH 1 o o o s OJ OJ e bo •H .; (8- ■109- A3-3.0 PROCESSOR Drawings -110- A3oj3°l PROCESSOR Card Rack List RACK A VARIATION 00 00 00 00 00 02 01 03 01 01 03 01 03 01 01 01 03 01 01 01 01 01 01 01 01 01 01 01 FUNCTION 2 -Input NAND 2 -Input NAND 2-Input NAND 2 -Input NAND 2 -Input NAND 3-Input NAND J-K Flip-Flop h and 8-Input NAND J-K Flip-Flop J-K Flip-Flop k and 8-Input NAND J-K Flip-Flop h and 8-Input NAND J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop h and 8-Input NAND J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop -111- RACK B — VARIATION FUNCTION 1. 103B 01 2. 103B 01 3- 103B 01 k. 103B 5. 103B 6. 103B 7. 103B 8. 103B 9. 103B 10. 10 3B 11. 115B 12. 115B 13. 115B lh. lO^B 15- 115B 16. H5B 17. 115B 18. 103B 19. 115B 20. 115 B 21. 115B 22. 103B 23. 115B 2k. 10 3B 25. 10 3B J-K Flip-Flop J-K Flip-Flop J-K Flip-Flop 00 2 -Input NAND 00 2 -Input NAND 00 2 -Input NAND 02 3-Input NAND 00 2 -Input NAND 02 3 -Input NAND 00 2 -Input NAND °3 INDICATOR °3 INDICATOR °3 INDICATOR 00 2 -Input NAND °3 INDICATOR °3 INDICATOR °3 INDICATOR 00 2 -Input NAND °3 INDICATOR °3 INDICATOR °3 INDICATOR 02 3 -Input NAND °3 INDICATOR 01 J-K Flip-Flop °3 U and 8 -Input NAND 26. 10 3B rsU U4 MONOSTABLE MULTIVIBRATOR 27. 104B 28. 152 00 9 BIT D/A CONVERTER. 05 EMITTER FOLLOWER -112- RACK C TYPE VARIATION 1. 153 00 2. Blank -- 3o Blank -- k. 152 __ 5. 106 00 6. Blank -- 7. 108 00 8. Blank -- 9„ Blank -- 10. Blank — lie 102B 00 12. 108 00 15. Blank — Ik. Blank — 15. Blank — 16. 102B 00 17. 123 00 18. 101+B 00 19. 104B 00 20. 152 02 21. IOUB 00 22. IOUB 00 23 - 105A 00 2k. 117 00 25 117 00 26. 109A 00 27. ioUb 00 28. lO^B 00 FUNCTION 10 KHz OSCILLATOR and AMPLIFIER PHASE SHIFTER and EMITTER FOLLOWER DPDT RELAY CONSTANT VOLTAGE SOURCE DCVGLA CONSTANT VOLTAGE SOURCE DCVGLA DC and AC ADDER and AMPLIFIER 9 BIT D/A CONVERTER 9 BIT D/A CONVERTER IOKHz SQUARE WAVE GENERATOR 9 BIT D/A CONVERTER 9 BIT D/A CONVERTER D.C. AMPLIFIER and MIXER COMPARATOR COMPARATOR Q.06k MHz CLOCK 9 BIT D/A CONVERTER 9 BIT D/A CONVERTER -113- A3- 3. 2 Digital Section ■yjji- 4 si ii 1 ii »» l| 1 5 5 K i iaisi -l\}* V* 8 5 J 3 J *«' l T ... S' »» xi 1 1 his ii !§&!< P * i ii *__ < ijjlhil * — YvM - 1 1 1 ' si i ,r: " a- ir J ?T ff 7 17 " f i -— HIS a jlii ! 5 jfe |_ i L_ » , J*f ti fiH li'cf jlrri |ii! |l«| M l " N . 1 ■- I I ii 1 i I i I ? ! » - s5 H * 5S" | j 1 i — t™t-^ l tr uT L L ± !T X r 1 - » L -l 1 ■ IL 1 T"V ""' ^]j ! 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Vio t3 O o fe 1-3 < o H En > i*> < a O £E • m < x 2 C\J u m » < I rA Nl < b liJ rA < •H -117- o 2 1 IP o 7 o £ J io 2( IH Z2 2. tf i-i- • M - ° 2 llo X4 ° 2 I io IO o IO o o o o £5 o o s o OJ I •H ■118- I B o H O PM Hi H > (A < H •H to -119- n 8 o o CVJ H O ft h3 § g Q 7T io at o r- r> id m u> 'W 3 i( IH a 2 % 8 o I PM H K OJ H O H Ei b- K ■ x 2 u o CM < CD ■ UJ I ro ,_ < - >- i>o OJ o < < m -1 CM a> a 0. ** JH p M •H h4 ■121- ■122- r ^__ i». EH g K H O o EH ON CM MA ■ KA < B M •H -123- A3-3.3 PROCESSOR - Hybrid Section ■12k> Htititi am T3 •H U >> H iA IA < 5 60 •H -125- A3^ Circuit Card Schemati cs •126- 1469 -14A DIAMOND (ANALOG) GATE +25v GATE o- INPUT 13 v 1N964B 680X1 5%,1/2W 68 K 6 -25v NOTES 1 ALL RESISTORS 5% , 1/4W EXCEPT AS NOTED 2. SEE NEXT PAGE FOR PIN AND VOLTAGE CONNECTIONS -1p r 1469 -14A DIAMOND (ANALOG) GATE U o-GAIL IN 16 o- S o- 14 o- P o- 12 o- M o- 10 o- K o- 8 o- H o- 6 o- E o- 4 o- C o- 2 o- A o- 1 o- GND Z o- 22 o- Y o- X o- 21 o- +10 -10 +25 20 o- A B D H .47 25 v 10 WS, i 10 — w\— 1.0 ^AAr- "> + 10 OUT .47 25 v 17 — o 15 13 11 -o 7 — o 5 -o 3 .47 25v ->-10 -t> GND .47 25 v -25 L P ->+25 •I ->-25 -128- ■129- 1469-103B-00 TWO INPUT NAND INTEGRATED CIRCUITS h r J4 .13 12 FLAT PACK A 10 11 FLAT PACK B FLAT PACK C GND SUPPLY VOLTAGE 10 (-5v) 21 ° W" ■> GND FILTERED VOLTAGE OUT Y o- 2 O- -t>-5v B O- NOTES © JUMPERS ALLOW POSITIVE OR NEGATIVE OPERATION 2. ALL CIRCUITS TEXAS INSTRUMENTS SN7400 -130- 1469-103B-01 J-K FLIP-FLOP INTEGRATED CIRCUIT r M 1 Q 1 E ' CLEAR t o c ' i o p ' n A \-.*» j c K 1 - - Z* ' zSo/^ H ' 0^ ' o L ' ft A 1 ft o K ' 3JV * o F ' k o N PRESET o— Q -1 u o "! l n CLEAR [ o x o w a A i to J C K 1 - - [ 9 9^ * S 13 IS o 1A T f7 A 1 to s 9A> * o 12 1 o v PRESET o L Q J n 17 r q "1 5 1 CLEAF t S 3 \ O 19 ' a A l b J C K 1 ■ o 20 I 3^J t °7 ' t^ S 15 o 16 ' a A i e 8 I %*J * 6 i f ■ r> PRESE o ! Q FLAT PACK A FLAT PACK B FLAT PACK C GND< A O Z O- SUPPLYWLTAGE „ ^1°^ FILTERED VOLTAGE OUT Y O- 2 O- B O- -O O- LJ .47 25v -C> GND .47 25 v -C>-5v NOTES ® JUMPERS ALLOW POSITIVE OR NEGATIVE OPERATION 2. ALL CIRCUITS TEXAS INSTRUMENTS SN7470 -131* 1469-103B-02 3 INPUT NAND INTEGRATED CIRCUIT FLAT PACK A FLAT PACK B FLAT PACK C GNO - O- t_i ® SUPPLY VOLTAGE „ 10 ( . 5v) 21 O WV^ .47 25v © n -o o- FILTERED VOLTAGE OUT NOTES Y O- 2 O- B O- -O GND .47 25 v ->-5v © JUMPERS ALLOW POSITIVE OR NEGATIVE OPERATION 2. ALL CIRCUITS TEXAS INSTRUMENTS SN7410 ■152- 1469-103B-03 4 AND 8 INPUT NAND INTEGRATED CIRCUIT n 8 r ^V Szl ' / t^ 1 A >] s^ Si Z±: ^V £n ^ 10 Sm Sn o n 13 i - x~-^ S^ s^ $^^x ^ f - \ £E 1 S Ll> Sx Sx 2x Si o n H F~ V-^ Tr SX 5^x JH I *" 7 - A o c C> IV Sn £z 0^ % , o J FLAT PACK A FLAT PACK B FLAT PACK C J r a o- GND - Z O 1 O- L 22 O SUPPLY VOLTAGE ^ Cr _J^ r (-5v) FILTERED VOLTAGE OUT r Y O- 2 O- -O O- © .47 25v I B O- © -o o- -l> GND .47 25v ->-5v NOTES (T) JUMPERS ALLOW POSITIVE OR NEGATIVE OPERATION 2 ALL CIRCUITS TEXAS INSTRUMENTS SN7440 FOR THE " 4 INPUT HANDS AND SN7430 FOR THE 8 INPUT HANDS -133- 1469-103B-04 MONOSTABLE MULTIVIBRATOR INTEGRATED CIRCUIT FLAT PACK A FLAT PACK B FLAT PACK C GND f A O- Z O- 1 o- L 22 O- SUPPLY VOLTAGE 10 (-5v) 21 ° W^ FILTERED VOLTAGE OUT Y O- 2 O- 1- B O- — O O f © .47 25v © n — o o — -H> GND .47 25 v -O -5v NOTES © JUMPERS ALLOW POSITIVE OR NEGATIVE OPERATION 2. ALL CIRCUITS TEXAS INSTRUMENTS SN7380 -13^- 1469-104B 9 BIT D/A CONVERTER PIN N SIGNAL /4 o- OUT PIN V OUT PIN R SIGNAL o- OUT PIN 21 + 10v 500 a ;2.2K i6.8K 150*1 :iok ison N — -to mic /in oM-ic/in — IK :iok SM1530 & 'T N 25v i-lOv T1N751 ^ -57 25v 2N3640 2N3640 1N751 1N751 -*f •*- .47 25v r -o PIN 22 10 K REFERENCE OUT PIN D ion NOTES -25v PIN 20 1 ALL RESISTORS 1/4 W, 5% UNLESS SPECIFIED 2 ALL TRANSISTORS 2N964 UNLESS SPECIFIED 3 ALL DIODES 1N995 UNLESS SPECIFIED -135- 1469-105A DC AMPLIFIER AND MIXER O > lO OJ OJ o •—I OJ 2 OJ > i CO O- < 5* i-H ^ X Q UJ Ul 2 u. o UJ Ul UJ 0. en (/) Q cn 0T (A) < UJ o _l 2 55 Eg IO tzuj 32 OJ 02 \ ceo I-l o° or 0J2 O Cl l- UJ (/) £* CO GND -L.47 '■^25v -1 >-25v .47 25v 210 + 25 H>+25v -137' 1469-106 DPDT RELAY IN O 820 1/4 W, 5% 1N995 — VW C0M-1 1N482 2N1613 C0M-2 -O N.0.-1 -O N.C.-l -O N.0.-2 -O N.C.-2 NOTES 1. SEE NEXT PAGE FOR PIN CONNECTIONS. L38- 1469-106 DPDT RELAY N.0.-1 n COM-1 N.C.-l \J A O - n IN N.0.-2 — o 5 O — COM-2 r\ N.C.-2 \J o V-* B '"» r\ ^\ — o 9 O *-» /^ w n VJ C « T "3 r\ — o 13 O <"» o n VJ D ^ — o 17 O \J — O 2 B 3 D 4 C 6 F 7 J 8 H 10 L 11 N 12 M 14 R 15 T 16 S A O- 1 O- Z O GND 22 O -5v 10 19 O — ^^— VW- .47 25v -> GND ->-5v 21 O + 25v 10 .47 25 v -l>+25v -139- 1469-107 10-500 ms DELAY MULTIVIBRATOR TRIG O 50 K WIDTH?* — O OUT 2N706A O-lOv NOTES 1-ALL RESISTORS 1/4W,5% UNLESS SPECIFIED 2. SEE NEXT PAGE FOR PIN CONNECTIONS. -1^0- 1469-107 10-500 ms DELAY MULTIVIBRATOR IN OUT K A OUT < 4 O — 9 O- 14 O 19 O B O 3 O 2 -O 8 ■O 7 O 13 O 12 O 18 O 17 A O GND GND 1 O- Z O- .47 25 v 22 O- 21 O- -lOv 10 -V\Ar -> -lOv ■141. 00 CO en en o i- o LU I- UJ Q «» W\ WV»- in ID - / V\Ar 4. > O O cm in H« + 6 o -I CVJ CO o o c\j in m 6^6 C\J CVJ O in CM CM o i 6 CD fs. ^H" Q UJ U UJ 0. 00 00 00 UJ _l z 3 in 00 or o i- 00 00 UJ or oo UJ -14-2- 1469-109 8.064 MC CLOCK -1J4.3- 1469-110 SYNC SEPARATOR , GATE DRIVER BLANKING LOGIC DRIVER VERT Ld 6 tz CO - to O CO u ■3M- 1469-110 SYNC SEPARATOR , GATE DRIVER , VERT. BLANKING LOGIC DRIVER GATE DRIVER COMPOSITE BLANK IN PIN D 1N914B GATE O OUT PIN E -lOv VERT. BLANKING LOGIC DRIVER SPACE PROVIDED FOR TERMINATING RESISTOR -> i i VERTICAL BLANK c IN PIN F T IK 2N967 \CVZN1305 VERTICAL BLANK , LOGIC ' PULSE OUT PIN H 1N995 2.2K -5v 1 -lOv ■1^5- 1469-110 SYNC SEPARATOR , GATE DRIVER VERT BLANKING LOGIC DRIVER vtK ' VLKf A o 1 o GND 22 o .47 25v 21 o +25 19 o- 2.7 ■AAA W O -5 18 o- V 17 U -10 2.7 AAA^ O O- -15 2.7 AAAr -L- 10 M f ^ 20 v -t>+25 I ->-5 10/xf 20 v -> GND ->-10 .47 25v -15 NOTES l.ALL RESISTORS 1/4 W , 5% UNLESS SPECIFIED, ■ lK6- 1469-111-00 VERTICAL SWEEP GENERATOR -147- 1469-111-01 HORIZONTAL SWEEP GENERATOR CO n -Z > + ycvj UJ 1-00 < Si a: UJ co < o CD u. o UJ 0. CO CO co LU _l 2 co or p CO co UJ or N-CVJ x >o_ co -lU8- 1469-112 ONE SHOT BUFFER (2ms) i — vw — |h -WV |l> Q UJ If) _J 6^ en a: o h- (f) (f) (f) UJ -149- 1469-112 ONE SHOT BUFFER (2 ms) 1 o TRIG. IN — I OUT ■o D OUT 6 o B ■o K ■o j 11 o C -O R — O P 16 o — ■ D -o w -o v Z o 22 o 1 — > GND -5 10 20 o 2 vy^ .47 '25v ■* >-5 .47 25v 21o-^l -10 -150- UJ cr UJ > O o o o o o Q > 0> Q UJ U. o UJ CL 10 GND 20^^25 10^ .47 25v * > + 25 .47 25 v pi ~ -io 1Q 21 O- VW- * > -10 -15k- cr LU > LT Q 5 z IT) Q_ 5 cr i—i o Li_ (/) LU cr O o < CL C/) CO X LU LU (T Z _l LU _l LU < CO C\J -155- 1469-115-03 INDICATOR DRIVER 2 o- IN A OUT -o 3 4 o — o 5 6 o -o 7 8 o- D — o 9 10 o- 11 12 o -o 13 14 G -o 15 16 o H -o 17 18 o GND 1-0 19 o- -^w\, f >GND 1.0 — V\A ^-U O vw- — > + 25 1 o- -5 — O -5 22 o- -156- LU > IT Q DC O \- < o i LO I CD CD \A > J -> li") J 1 _J LU ■z. o Q_ > LU _l CO Z in i CD Z h- _l LU < 3 X 00 £ CO Q LU Lu O . W CO ^ 2 CO o co H co o LU LU -J ^ Z 2 => 9 o ^2 "It S. K 5 o CO LU cr o £2 co , — 1— W LU c z -I LU CO -1 LU LU < CO I- • o .-i C\J -157- 1469-115-04 INDICATOR DRIVER 2 o— A 4 o- B -o 5 6 o- C 7 8 o D -o 9 10 o- 12 14 o 16 o , -o 11 -o 13 -o 15 ■o 17 lft n GND L0 lc> O— ■ VW- f >GND 19 o- 1.0 20 o- ±2527 + 25 1 o- -5 -5 22 o- -158- 1469-116 VIDEO ADDER AND SYNC INSERTER C\J i — *sAA — ||i ill — v*< — I 0) Z If) 0> Q UJ o UJ 0- (/) CM zo? 0- o -159- 1469-117 COMPARATOR O) = + a. m in O m to 9H» o in o ' — ' III o n E to r-H co 1- CO hi 2 3 Q CO ^S UJ X CJ> in o h- UJ •i < 2 2 o i-i UJ ^ m CO rr ac i- n to c !> z S5 m CO cr o g CO UJ tr •l6l- 1469-118 PEN PULSE SHAPING CIRCUIT AND MULTIVIBRATOR GATE -162- 1469-119 DISCRIMINATOR AND SHAPER co UJ I- o z Q UJ U. o • UJ UJ Q. o CO < 0. CO CO H UJ X _J Ul z z Z> 85 Ul UJ (O CO at $ CO z S o i-i H o co UJ GND 19 o >+10 21 o -25 -25 -167- 1469-152-00 PHASE SHIFTER AND EMITTER FOLLOWER -168- 1469-152-01 EMITTER FOLLOWER IN o C IN o oout 2N1305,7,9 NOTES 1. ALL RESISTORS 1/4 W, 5% UNLESS SPECIFIED 2. SEE NEXT PAGE FOR PIN CONNECTIONS. ■169= 1469-152-01 EMITTER FOLLOWER 2 o- IN 3 o CIN 1 OUT 5 O- 6 O B 8 o 9 o 7 11 o 12 o ■ D 10 22 o- GND -5 1-0 19 O - WV .47 25v *— >-5 GND .47 T 25 20 0-^2 J£ -> -10 -170- 1469-152-02 10 Kc SQUAREWAVE GENERATOR & in : i CM C\J Q l|| wv o Ld o UJ o. CO CO CO UJ 55 if) CO tr o h- co CO UJ or CO UJ o-o -171- 1469-152-03 +1.7 VOLT POWER SUPPLY PIN 21 + 10 PIN 22 GND PIN 6 OUT -172- 1469-152-04 EMITTER FOLLOWER IN lo 1.1K -W\/ < IN 2o -10 -5 A -10 A 1.1 K * 1N914B 2N967 -H^J2N2906A o OUT 1.1K NOTES 1. ALL RESISTORS 1/4 W , 5 % . 2. SEE NEXT PAGE FOR PIN CONNECTIONS -1Y> 1469-152-04 EMITTER FOLLOWER 2 o- IN 1 3 oJ^ I OUT 5 o- 6 o . B — o 4 22 o- GND 20 o-' 10 .JL .47 25v O-10 — ->GND ^25 19 o -5 12 -t> -5 -17^- 1469-152-05 EMITTER FOLLOWER CIRCUITS A&B IN o- -5 A €) 2N967 r -o OUT CIRCUIT C IN o- -5 a ■K> 2N967 ^ IK 2.7/xf K 35v ^51il, -O OUT •OPTIONAL LOAD CIRCUIT D IN O- 4.3 -vw -10 -5 -10 A A IK 1N482 ■-o €> 2N1305 2N1305 -o OUT r NOTES 1. ALL RESISTORS 1/4 W, 5%. 2. SEE NEXT PAGE FOR PIN CONNECTIONS. •175- 1469-152-05 EMITTER FOLLOWER 2 o- -o 3 5 o B 15 o- -o 12 18 o — D o 16 A o 22 o- GND -O GND 20 O^ 1 ^ AAAr 1 o 4 o- -.47 s 25v -o-io .47 25v 12 -5 10 o -5 19 o- -176- 1469-152-06 PEN GATE 50 pf PIN 3 IN PIN 20 -5 PIN 21 -10 1N914B !! 2.2 K 500 pf 1N914B -^1 ' N I 1M ioon — vw— 100/xf 15 v ■= PIN 22 io a -Wv — -f .47 25v -± PIN 22 OUT PIN ' NOTES l.ALL RESISTORS 1/4 W , 5 % . -177- 1469-152-07 DISPLAY GATE DRIVER o CO CD -178- 1469-153-00 10 Kc OSCILLATOR AND AMPLIFIER CO ro ■Z. 3 2 K ° E yYYYV o c— 1 C5 0J o 2 m CO to CD ro -WNr 4.* oo oo m ie-n» CO - £ ^r-Ml E m l -o "\>«>^«s^- CT> ro CO O i— i CO CO -vw ro o° CO 1 " -It- -wv- o ^ r-i ro .-•CO ■vw- CM If) ^M" 4. CO -wv ro ^WV Q UJ L_ O UJ CL CO CO \- CO cj UJ G z o _) o o If) H t 5 o UJ -25 ^ -t> GND .47 25v * > + 25 -182- 1469-173 FILTER IN o 1 -5 330& 1.5K -O OUT I 47/xf 25v 1 -5 -5 NOTES 5% 1. ALL RESISTORS 1/4 W , u vo 2. SEE NEXT PAGE FOR PIN CONNECTIONS. -183- 1469-173 FILTER B o- C o- D o- E o- F o- H o- J o- K o- L o- M o- N o- P o- R o- S o- T o- U o- V o- W o- A o GND 22 o 1 B A D C H K M L N T U ^> 1 -o 2 -o 3 -o 4 -o 5 -o 6 -o 7 -o 8 ^> 9 -o 10 -o 11 -o 12 -o 13 c 14 o 15 o 16 -o 17 -o 18 19 o- -5 LIGHT PEN CABLE DRIVER & ENABLE FILTER O O r-l + UJ LU CO _l Q_ CQ Z> > CQ X EH % 0) -P o o H -4" •H ■187- ■H > -p G O w PQ -p •H o in •H O rH 05 o •H CVI a; •188- •H > U IIW mem ° ry ' one ta ° i-hes fro m screen o „ f"'," tW lnCheS fr0m the ^"^ °f the bcreen. Both points should be placed «hrm+ h a u v x left and right hand edges of the screen Repeat aTp l TV"" ca" d 5 C!7) '1 ^ ertlCal P ° Sltl0n 0t TO ™ 1 (P ?entioMeter 3 # 2 ' card £o ?uL th er t tlCal Sal " ° f TOIMT l (Potentiometer If,' and ta^ & resr aaju " * 2 - 2 ^ngth and Position T,in Pg 1) Replace the 10 KHz oscillator card. Draw one pair of on llt'lT^t T , lnCh apart ^ ° ne ab °- the other/Sdway second iff Jand edge of the screen. Similarly, draw a second set of points on the right hand edge of the screen Construct one line connecting each of the top points -198- indicating the right hand point first (POINT l) . Construct a second line connecting each of the "bottom points indicating the left hand point first (POINT l) . Designate these lines RL and LR respectively. 2) Observe where RL falls in relation to LR. Repeat, indicating RL and LR while adjusting the m/2 gain control (potentiometer #7, Card C28) until the midpoints or RL and LR fall on a vertical axis. Observe also that LR will move faster than RL when the gain control is adjusted. Using RL as the reference line, align LR directly below RL. 3) Adjust the gain of RL and LR by changing the amplitude of the + sin(wt) and - sin(wt) sinusoids. (RL is - sin(wt) poten- tiometer #3, Card Ck, and LR is + sin(wt) , potentiometer #4, Card Ck) . k) Draw one pair of points, about an inch apart, one beside the other, midway on the top edge of the screen. Similarly, draw a second set of points on the bottom edge of the screen. Construct a line connecting each of the left hand points, indicating the bottom point first (POINT l) . Construct a second line connecting each of the right hand points, indicating the top point first (POINT l) . Designate these lines HE and TB. 5) Repeat Parts 2 and 3 with BT and TB in place of RL and LR, until both BT and TB have their end points on horizontal lines. Use the AV/2 gain control (potentiometer #7 , B27) . In this case, TB is the faster moving line. 6) Adjust the lengths of BT and TB with the aspect ratio control (potentiometer #1, Card C9) - Both lengths are adjusted simultaneously with this control. A6.2.3 Dummy Offset for Circles 1) Store a radius, then switch to the LINE mode and construct a line of zero length by indicating the same point twice (don't reset the radius when obtaining the line) , 2) Pull the 10 KHz oscillator card. 3) One person must switch back and forth from the LINE to the CIRCLE mode, keeping the XECUTE CONSTRUCT button depressed. ■199- ICcard ?i7)°a n nd U t S he a vf t' ** ^"^l d ™^ (potentiometer until tli- I vertical dummy (potentiometer #1, Card C17) untxl the line of zero length and circle of zero radius coincide! M Replace the 10 KHz oscillator card. A6.2.4 Shape and Size of Circles and phase of the C0 S (a> 5 ) signal is adjusted to give a ircard 1 "' 6 (P ° ten + Wom f f # 2 > ^rd c\ and potentiometer Cardcf^v' respectively). Adjusting potentiometer #1, Card C4 may alter the lengths of the lines. Hence a read justment of the lengths might be necessary. clteroAT P ° lntS ^ 8 h0rizontal ^ne, one in the and right of the T" T" •*! ° tbep f ° Ur lnches to the *« mim f fin the ct^tI P °f >° IndlCate the center Point as as POINT 2 ^.CIRCLE mode) and the point on the left as fuuu 2. Adjust potentiometer #2 Card P?^ (™ci+- \ T£ XlT'l r- se : through P0 ™ ^1k.«u - t i s } muJt h! •!? ^J^tment of the potentiometer, and circle the riLtT^ % H ° W repeat the 'ajustment procedure with to ™i S 1 P ? lnt and Use Potentiometer 7, Card C22 (rain) the^nt " rC , le "" thr ° Ugh the **<** hand point! R^eat Similrl-f f OCe ?r a « ain to »* "en closer alignment P Similarly draw three points in a vertical line. Usine the passes ? hough SS fc °&£ ^t°» seT^eTaalr" adjustment and a new circle must be rewritten) qi»i^ i a6 '3 Memory Cont rol Adjustment. Several adjustments are located on the Memory Control rack These adjustments should be made uhen necessary. A6 -3.1 150 MELUSEC0T\m MTT.rrTVT orator, Card ^ -, ThS P° tentl o^ters on this card should be adjusted such that the erase gate output is approximately 150 milliseconds. -200- A6.3'2 Pen Threshold Adjustm ent, card Al The pen threshold potentiometer should he set for zero ohms unless a higher threshold level is desired for some reason. A6 . 3 . 3 Video Adders, c a rd A7 and A 8 The video adder cards have four adjustments. These determine the relative amounts of the two inputs that are added together, the amplitude of the overall signal, and the synchronizing pulse amplitude , At card AT adjust for no synchronization output since no synchronization is added at this card. Adjust the relative amplitudes of the DISPLAY video input signal and the POINT video input signal such that the POINT video appears approximately twice as bright on the screen as the DISPLAY video. Adjust the overall gain to give a one volt video output level. At card A8 adjust synchronization level to be 0.U volts negative. Adjust the pen pulse and composite DISPLAY ana POINT video signals such that the pen pulse amplitude is comparable to the POINT video level. Adjust the overall gain to give 1 volt of composite video (including synchronization) . A-6 . 3 . h Discriminator Adjustment Cards A12, A13, Al^ and A15 are discriminators for the video outputs of the various memories. There are two discriminator circuits per card and two adjustments per circuit. These controls permit adjustments in the discrimination level and the output amplitude. At card A12 the upper circuit controls the POINT video which reaches the TEMPORARY memory during the execute erase cycle. This circuit should be adjusted for the lowest possible discrimination level which will not allow background video to pass through the circuit The output amplitude should be adjusted to the one volt level. The lower circuit on card A12 should be set as above but for the DISPLAY memory. ■201- Similarly, the upper and lower circuits on card A13 control the output video from the TEMPORARY memory which passes to the DISPLAY memory and the POINT memory, respectively . These circuits should be adjusted as above. Similarly, the upp,-r and lower circuits on AlU correspond to the video which passes from the ERASE memory to the DISPLAY memory and POINT memory, respectively. Adjust as above. The lower circuit on card AI5 is not used. The upper circuit controls the video level, above which, points in the POINT memory will be allowed to pass to the circuit which forms the logical AND of the pen pulse and the points in the POINT memory. The dis- crimination level should be set as low as possible without allowing indiscrimate pulses to pass through this circuit to the logic. The output level should be set to the one volt level, A 6»3°5 Erase Lev el Adjustment When in the ERASE DISPLAY mode, adjust the synchronization level on the DISPLAY video circuit board of the DISPLAY CAMERA CONTROL UNIT such that an erase point in the ERASE memory causes the video to be lowered just to the black level. Similarly, in the ERASE POINT mode adjust the synchronization level of the POINT video circuit board in the POINT CAMERA CONTROL SITE, Alf6 J 6 1968 «% ?0 %