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UNIVERSITY OF ILLINOIS 
 GRADUATE COLLEGE 
 DIGITAL COMPUTER LABORATORY 
 
 REPORT NO. 86 
 A SET OF BASIC CIRCUITS 
 
 by Gene H. Leichner 
 October 21, 1958 
 
 This work was supported in part by the 
 
 Office of Naval Research and the Atomic Energy Commission 
 
 under AEC Contract AT(ll-l)-Ul5 
 
I 
 
 CO in 
 
 The term y, used In forming s and b ,.-. 
 
 iig b i az.u o i _ 1 , ?ctly< It shouid be: 
 
 y " Vl "l+l v (a i+l v m i+1 ) * 
 " *i+l °i+l v (» 1+ i v » 1+1 )'(c^ 1 v a 1+2 m l+2 ) 
 
 This function cannot be formed with one elpmpnt t+ »<,„«+ ^ „ 
 
 level. B,e following solution Is, hoover ^sslble: ^ "" "" '"^ lD 
 
 one 
 
 Let 
 
 z - P - aj © m i « (a t v m t ) ^ v m^ 
 
 r - i - 7 vt . a 1+1 Vl T ( Vi T Vi) (Ci+i v a ^ „ i+2) 
 
 8114 * " «!♦! Vl - Vl = 1+1 v » ltl c 1+1 
 
 ■ (a lrt v ■id'-'v v c l + l'-< m i + l T W> 
 * " a i+i a i + 2 "ne v °ui a 1+2 " 1+ , 
 
 v a i i0 v »«^)-(n. 
 
 '1 + 1 v »l +2 v "W^ v a 1+2 v m 1+a ) 
 
 Then 
 
 ■ t - P <S> q « (P vq)'(? v q) « (p y 3 vt).g v e-t) 
 * (p v s* v t)-(5 v a).(p* v t) 
 
 'i-1 " p,q " P s v p t 
 
 (P V 8).(p Y t) 
 
 LOADIHO: 
 
 1+1 
 
 i+1 
 
 m 
 
 1+1 
 
 OR Inputs AND Inputs 
 : (1) 
 
 : <M 
 
 : (1) 
 
 *i+i '• M 
 
 #) 
 
 #) 
 
 - 1 - 
 

 { cont d . ) 
 
 
 
 OR inp 
 
 AJTO 
 
 puts 
 
 ^1 ; < 2) 
 
 
 (1^ 
 
 a i : (1) 
 
 
 - 
 
 \ : CM 
 
 
 - 
 
 m 1 : (1) 
 
 
 - 
 
 m< : (U) 
 
 
 - 
 
 
 #) 
 
 Requires a non-standard emitter- follower in the O-side of the flipflop. 
 
 - 2 - 
 
 
3 L 
 
 ai = 8 
 
 in 
 
 
 
 1/ 
 
 1 
 
 
 4 
 
 u' 
 
Introduction 
 
 The logical, or basic building "block, circuits which are presently in 
 use in the new computer design work have certain practical difficulties which it 
 is desirable to avoid. Most of the problems arise from the fact that the AND 
 and OR circuits are non- restoring in nature; that is, the signal levels at their 
 outputs are not returned to some standard condition. Instead each circuit may 
 contribute a level shift due to tolerances within the circuit or to external load 
 differences . 
 
 The set of circuits to be presented here represents a somewhat different 
 viewpoint. Every circuit restores the output signal to a standard condition. In 
 general then, rather than placing diode logic or level changing resistors after 
 emitter follower inputs, as the present circuits do, these circuits have diode 
 logic at their inputs followed by a restoring circuit. 
 
 There are certain members of any logical set which have not been de- 
 signed and which are not included in this report. These circuits are those 
 needed for truly speed- independent designs, namely the F and C elements and the 
 last moving point flipflop. To a first order at least, the new circuits do not 
 hinder or help the present practical difficulties in obtaining speed- independent 
 behavior. 
 
 A number of logical and engineering advantages result from this arrange- 
 ment. 
 
 Logical Advantages 
 
 1. All circuits restore, so infinite cascading is permitted. 
 
 2. All circuits have the same driving capabilities. 
 
 3. The input requirements do not depend on the output loads. 
 
 h. There are only two types of input circuits, so loading is easy 
 to predict. 
 
 5. The complements of AND and OR circuits are available at a cost 
 of an additional transistor each. 
 
 
 -1- 
 

 6. Simple, restoring and fast EXCLUSIVE-OR and EQUIVALENCE circuits 
 can be built. 
 
 7. A large degree of logical flexibility exists within a single 
 circuit (i.e. with a single circuit operation time). 
 
 8. Only one additional transistor is needed for each 5 additional 
 inputs of the same type. 
 
 Engineering Advantages 
 
 1. The transistor a requirement is less severe (0„92 to 1.0). 
 
 2. The maximum reverse V , is half as large (2.1v)„ 
 
 3- The minimum collector voltage is larger so saturation effects 
 are reduced and CC reduction is less. 
 
 h. Minimum diode drop requirements are not needed except for 
 collector bumps . 
 
 5. A 0.2v allowance exists for noise problems under worst case 
 conditions . 
 
 6. Since a greater degree of isolation exists between input and 
 output, a more thorough analysis can be made of worst cases. 
 
 General Properties 
 
 The components and tolerances which were used in the design are as 
 
 follows : 
 
 For All Circuits 
 
 Resistors 
 
 Voltages 
 
 Restored Output Signals 
 
 Input Signals 
 
 + 3"/o 
 
 + 5$ 
 
 + 2.0v 
 + 1.2v mm., ~ -, max, 
 — '-2.lv 
 
 + l.Ov max. required 
 
 _2- 
 
Diodes: 
 
 Collector 
 
 Signal Bump 
 Input Logic 
 
 V > 15v at 100 Lia 
 rev 
 
 V as per Q10 curves of April 2j, 1958 
 
 Q5-250 as per curves of April 23, 1958 
 
 Q10-600 no minimum drop, otherwise as per 
 curves of April 23, 1958 
 
 50 ua maximum at hv reverse 
 
 Transistors: 
 
 All circuits 
 
 All circuits 
 
 V as per curves of October 11,, 1957 
 as revised April 23, 1958 
 
 50 u.a maximum at 2v reverse 
 0„92 < a <_ 1.0 
 
 The maximum load which any circuit can drive is described as follows: 
 
 From any single output (3) AND inputs 
 including flipflops (3) OR inputs 
 
 Each flipflop being set to "1" counts (1-1/2) OR inputs. 
 
 Each flipflop being set to "0" counts (l/2) AND input. 
 
 Some examples of maximum loading are: 
 
 (3) OR + (3) AND 
 
 (1) Flipflop to "1", (1) OR + (h) Flipflop to "0*% (l) AND 
 
 (2) Flipflop to "1 M + (6) Flipflops to "0" 
 
 Circuit Examples 
 
 Examples of the actual circuits are presented on the following pages, 
 although many variations are permissible as will be noted. 
 
 -3- 
 
MAX. 3 
 OTHER 
 
 WMS/STOftS 
 
 0/0 
 a o T N 
 
 6 o 14 
 
 c o ^ H 
 
 AW. .5 
 
 3.3/f 
 
 +0.9 
 
 -2^ 
 
 Q5 
 
 QS 
 
 -1.9 
 
 )l Q/0 
 
 NOTE: 
 
 In all circuits diodes 
 labeled Q5 are Qutronic 
 Q5-250; diodes labeled 
 Q10 are Qutroni< QIC-600. 
 
 Suggested symbol: 
 
 Figure 1 
 AND -NOT 
 
 -k- 
 
MAX. 3 
 OTHER 
 
 TRANSISTORS-^ 
 
 MAX. 3 
 INPUTS 
 
 FREE COLLECTOR 
 MAr BE USED 
 FOR aha BY 
 
 ADDING A W E.F. 
 
 oabc 
 
 Suggested symbol. 
 
 • OR IF A IS 
 
 NOT USED 
 
 Figure 2 
 AND 
 
 -5- 
 
MAX. v5 
 
 INPUTS 
 
 Q/O 
 a o— H" 
 
 b O N 
 
 Q/O 
 
 C — - — y- 
 
 v//r 
 
 ■25 
 
 +25 
 
 /,s/r 
 
 3.3/r 
 
 ^Q5 
 
 +0.9 
 
 A 
 
 Q3 
 
 Q.5 
 
 170 
 
 -/.9 
 
 /.2/f 
 
 -25 
 
 Suggested symbol; 
 
 Figure 3 
 OR -HOT 
 
 lL<?/0 
 
 -4 
 
 •6- 
 
MAX. -5 
 INPUTS 
 
 FREE COLLECTOR 
 MAY B E USED FOR 
 avbvc BY ADDING 
 AN E.F. 
 
 avbvc 
 
 -15 
 
 Suggested symbol; 
 
 Off /FO AS 
 
 A/or USED 
 
 Figur - k 
 03 
 
 -7- 
 
/ GATE 
 
 FREE COLLECTOR 
 MAY P>E USED FOR 
 COMPLEMENT OUTPUT 
 WW AN EXTRA E. F 
 
 Suggest ed symbol- 
 
 I TO SET TO I 
 
 -Z5 
 
 
 / 
 
 
 
 
 
 
 > 
 
 >^ 
 
 /"OUTPUT 
 
 TO SET TO 
 
 Figu r 
 FLIPFLOP 
 
 -8- 
 
A4AA.S 
 
 INPUTS 
 
 MAX, Z 
 OTHER 
 TRANSISTORS 
 
 -23 
 
 Figure 6 
 (a v b v „ „ ) (c v d V „ „ ) 
 
 If desired some of the additional transistors can ' SM [ ' 
 
 that functions such as 
 
 may he formed. 
 
 Suggested symbol 
 for above function: 
 
 ^y 
 
afavak) 
 
 Note: If b and b are interchanged, the output function is abya'b, 
 
 Suggested symbol: 
 
 Off 
 
 Figure 7 
 EXCLUSIVE -05. 
 
 -10 = 
 
+Z5 
 
 +Z5 
 
 +13 
 
 +25 
 
 Qbva 
 
 -25 -Z5 
 
 Suggested symbol: 
 a 
 
 Figure 8 
 EXCLUSIVE -OR WITB. COMPLEMENT OUTFJTS 
 
 -11- 
 
Design Considerations 
 
 The design of this type of building block set is relatively simple 
 since the inputs are effectively isolated from the otuputs, that is, the different 
 loads a circuit may have to drive have no effect on the signal driving the input 
 to the circuit. The bleeder network performance was checked using Program No. 
 928 on Illiac and the results are given in Appendix I. The other design details 
 are also given in Appendix I. 
 
 Two of the design results are of "Importance in specifying transistor 
 
 acceptability. The first is the maximum emitter current required and the 
 
 minimum collector voltage available under the same conditions. The worst such 
 
 case occurs in emitter followers and shows that the transistors should actually 
 
 be tested for their a . =0.92 requirement at an emitter current of about 25 ma 
 
 mm 
 
 and a collector to base voltage of about 1.5 volts. 
 
 The second result affecting transistor acceptability is the degree of 
 saturation or C increase at reduced collector voltage in switching circuits. 
 The minimum collector voltage in this case is 1.0 volts at a maximum emitter 
 current of 15 ma. A switching speed test under these conditions should be made 
 to eliminate unusually slow transistors. Also until it is determined which 
 
 condition is worse, the a . = 0.92 test should be checked at 15 ma and 1.0 volts 
 
 7 mm 
 
 as well as at 25 ma and 1.5v. 
 
 Other calculations showed the maximum static dissipations to be 
 95 mw in emitter followers and 68 mw in the flipflop. Only 50 mw are required 
 in the logic switching circuits. 
 
 Test Results 
 
 Several .circuits were built to check speeds of operation under various 
 load conditions and for different values of transistor a s s„ It was found that 
 the average speed of operation was 12 mu-s„ However when (3) AND or (3) OR loads 
 were used, the operation time increased to 15 mus and when (3) AND and (3) OR 
 loads were used simultaneously the time was 20 mus. For the circuit of Figure 6 
 the operation time is 15 mus when all k terms are formed. 
 
 •12- 
 
The method used in the speed tests is shown in Appendix II together 
 with the detailed results, 
 
 A Modification 
 
 The emitter follower on the output of every circuit is designed to 
 drive at most (3) of any single type of input. In case a larger number of one 
 type is needed, and less than (3) of the other are also needed, the emitter resis- 
 tor can he altered to suit the special requirements. This procedure would be 
 particularly suitable in the internal design of an adder, complementer, or assimi- 
 lator where the special load requirements may be foreseen and provided for,, 
 Figure 9 shows a modified emitter follower designed to drive at most (5) OR inputs 
 and (0) AND inputs. It may be used in place of any of the emitter followers in 
 the set of circuits, including the flip flop. The operation time fully loaded was 
 lk m|_is and when driving a single OR input was 12 mjis. 
 
 + 25v. 
 
 +0.9 v. 
 
 A 
 
 IDENTICAL CIRCUITS 
 
 f 
 -l.9v. 
 
 Figure 9 
 
 I.IK 
 
 -O OUTPUT 
 
 -4 v. 
 
 Applications 
 
 The following applications of the basic circuits show some of the 
 advantages to be gained by the high multiplicity input. These circuits are 
 due to Roger Farrell , as are the equations from which they are derived. 
 
 -13- 
 
hni mi 
 
 rni 
 
 i+l mi + l 
 
 
 O 
 
 
 
 o 
 
 
 V ° 
 
 O A 
 
 3i 
 
 
 
 
 
 
 
 
 c 
 
 ) / 
 
 
 t 
 
 M REGISTER 
 
 n ± * (i s/M 1 )(g ] V M.)(i 2 v M i+1 )(g 3 V M. +1 ) 
 
 m. = (g Q V M ± ) (g x V S 1 )<g 2 V M. +1 ) (g^V M. +1 ) 
 
 Loading: M (2) OR inputs 
 g (53) OR inputs 
 
 Figure 10 
 
 COMPLEMENT: AND DOUBLE GATE 
 
 (7 T/digit, 15 mus) 
 
 -14- 
 
>i + l 
 
 bi-i 
 
 J i + I 
 
 w°X 
 
 i + 1 a i + . 
 
 m '+l F^^V 
 
 / \ a 
 
 C | + , °i + 2 
 
 i + 2 
 
 i + I m i +1 
 
 l+l l+l l+l 
 
 Loading: from A and Complement Circuit 
 
 x = ("c. -,) (a. _ v m. _ ) 
 
 % i+1 v i+2 i+2 
 
 s. = y © z 
 
 b i _ 1 = yz 
 
 y = ( c. . ) (a. ., v m. , ) (a. _V m. _) 
 
 J l+l l+l l+l 1+2 1+2 
 
 z = a. © m. 
 l l 
 
 i+1 
 
 i+1 
 
 m 
 
 i+1 
 
 m 
 
 i+1 
 
 m, 
 
 m, 
 
 'i+1 
 
 Figure 11 
 
 ADDER 
 (30 T /digit, 2k- mus) 
 
 (1 
 
 ) 05 
 
 Input 
 
 (2 
 
 ) OR 
 
 Inputs 
 
 (1 
 
 ) OR 
 
 Input 
 
 (2! 
 
 ) OR 
 
 Inputs 
 
 (I! 
 
 ) OR 
 
 Input 
 
 (3, 
 
 ) OR 
 
 Inputs 
 
 (I! 
 
 ) OR 
 
 Input 
 
 (Si 
 
 OR 
 
 Inputs 
 
 (I! 
 
 AMD 
 
 , (1) OR 
 
 -15- 
 
Oj + I 
 
 a i +1 
 
 c i + I 
 
 ■li + l 
 
 u$j 
 
 f 
 
 9 d li-l 
 
 gi. : = (g a. a. n )(c. . V d--, • -, ) 
 & li-l Xto 1 l+l l+l li+l / 
 
 g d_. . = (g)(a. V a. n V c. . )(a. V a. . V d_. n ) 
 e 01-1 l l+l i+l /v l l+l Oi+l y 
 
 (a. V a. . )(a. V c. ,Vi. , ) (g d_. . ) 
 l l+l l l+l li+l Oi-l 
 
 1+1 
 
 = (a. . v d_. . )(a. . V c. , )(a. , V c . , V d n . n ) 
 
 v l+l Oi+l l+l i+l /v i+I l+l li+l' 
 
 Loading: 
 ( from A and C ) 
 
 a. (2) OR inputs, (l) AND input 
 a. (l) OR inputs, (l) AND input 
 
 a. (3) OR inputs 
 a. (k) OR inputs 
 
 C i+1 ^ 0R in P uts 
 
 c. (2) OR inputs 
 
 d li+l ^ 0R iir P uts 
 
 d 0i+l (3) 0P in P uts 
 
 Figure 12 
 
 ASSIM1LAT0R 
 
 [l9 T/digit, (36 + 12k) mus_, k = length of carry] 
 
 -16 ■ 
 
IDENTICAL 
 CIRCUITS 
 
 53 
 = IT (d V d x ) 
 i=l i i 
 
 Loading: from assimilator circuits 
 d (l) OR input 
 
 d (l) OR input 
 
 Figure 13 
 CARRY COMPLETION 
 (8k T, 2k mus) 
 
 -IT- 
 
APPENDIX I 
 DESIGN CONSIDERATIONS 
 
 Max I for maintained a at high i , Feeding (3) AND inputs 
 
 "■* x e ■ i.a f.97 + (3) { Tinhn + L ; 18 + - 20 > ■ 2k -i ma 
 
 I, diode 
 
 (V = -1.2 v) leak 
 
 e 
 
 Min V . = 3.88 - 1.9 - .30 = 1.68 v . 
 
 CD 
 
 So 0.92 <_ a <_ 1.0 must exist when I = 2^.3 ma and 
 
 V . = 1.68 v . 
 cb 
 
 Min (+) E.F. Overcurrent: Feeding (3) OR circuits 
 
 Min h - l/xlo 3 " (3) ( ITF^f + -f\ - k - 6 m 
 (Vj = + o.i*) f °f e 
 
 e leak 
 
 therefore, min overcurrent per (+) going OR is 1.6 ma . 
 
 Min (-) overcurrent in E.F. (standard E.F.) 
 I = —^ - 18.1 = 29.5 - 18.1 = 11. k ma 
 
 Min V , for saturation, increased C . 
 CD ' c 
 
 occurs in switching positions other than F.F. 
 
 Min V - 3. 45 - 2.^7 = O.98 v 
 
 (i max = 1^.8 ma) 
 v e ' 
 
 
 ■18- 
 
F-F Max Gate Current: 
 (+) - i.e. to "1" 
 
 E = 9.5 v 
 oc 
 max 
 
 R. = 11 // 3.2U = 2.5k 
 in '/ 
 
 I = |;| - 3-8 ma 
 
 Max OR current = 2.67 ma 
 So factor 1 — is safe . 
 
 F-F Max Gate Current: 
 (-) - i.e. to "0" 
 
 F = 2.kQ v 
 oc - y 
 max 
 
 R. = 2.3 11 = 1.9k 
 In 
 
 2.U9 . __ 
 I ■ -y-§ = 1.31 ma 
 
 Max AND current = 2.8l ma 
 So factor l/2 is safe 
 
 Min overcurrent at circuit inputs: 
 
 AND 
 
 ( + J going I . = 775 -, ~ n = 1.30 ma 
 
 x to to mm lo x 1.03 
 
 (V b - v) 
 
 OR 
 
 (-) going I . = in 2 '4 no - 1.18 = O.96 ma 
 min 11 x 1.03 
 
 (V b = v) 
 
 .19- 
 
Max EF W , driving (3) AND circuits 
 
 Max <+) *, ■ 1^97 + (3) <irrbr> - 17.9 
 
 (v e = + 1.67) 
 
 c b Re 
 
 V . = k.12. + 1.31 - -1^ = 5.29 v , 
 
 CD 
 
 W„ = (5.29) (17.9) = 95 mw 
 
 ma 
 
 Max Diode Bump Currents: 
 
 To evaluate max restored outputs: 
 
 (+) worst case occurs in F-F Single Bleeder 
 
 E = l.k v 
 
 oc 
 
 R. =620 || 2.7k = 50l+ 
 
 I = ii. + 2.36 = 5.l4 ma 
 
 maX .50k 
 
 V = O.903 + .U05 = 1.31 v 
 
 msix 
 
 Max (+) output = 1.31 + .68 = +1.99 
 
 (-) worst case occurs in F-F Single Bleeder 
 
 E = 6.2 v 
 oc 
 
 R. n = I.56 j\ 2.7 = 990 
 
 I = %| = 6.27 ma 
 max . 99 
 
 V = I.96 + .k2 = 2.38 
 max 
 
 Max (-) output = -2.38 + .31 = -2.07 v 
 
 -20- 
 
E.F. Modification for Driving OR Inputs Only: 
 Max number of OR loads = 5 
 
 27 
 
 Max I = = — s ! — ;== = 25.2 ma i.e. 0.9 ma more than standard circuit 
 
 e 1.1 x .97 
 
 Min E.F. Over current: 
 
 Mln X e ■ l.l 2 x'?.03 " (5) ( irf^97 + ' 25) = 7 ' 7 ma 
 
 (v = + 0.10 
 
 e 
 Min overcurrent for (+) going OR is 1.5 ma , 
 
 or 0,1 ma less than standard circuit 
 
 Max E.F. W , Driving 2 OR circuits 
 c 
 
 *»* ^ h - 1^97 " (2) ( irrr^3) - *•* 
 
 (V = +1.67) 
 
 e 
 
 Max V . = lj.,12 + 1.31 - -I 1 *- = 5.29 v 
 
 CD 
 
 W = (5-29)(l8.l) = 96 mw 
 c 
 
 Min (-) overcurrent in Modified E.F., driving 2 OR circuits 
 I = 2 -^| - 18.1 = 29.5 - 18.1 = 11.1+ ma 
 
 -21- 
 
Bleeder Circuits For All Logic (Base = 0.00) 
 (Results are from program no«>928) 
 
 RO Rl R2 R3 R4 R5 V E 
 +1.800 +1.200 +.770 +3.300 +950.000 +950.000 +25.000 +25.000 
 
 F G Q S A MIN A MAX A B 
 +25.000 +25.000 +2.000 A. 000 +.910 +1.000 +.030 +.030 
 
 VI IEO ILI IL2 T U W IC 
 WC IE IDI ID3 
 
 +.000 +.000 +.000 +.000 +.929 +9.601 -4.195 +11.640 
 
 +48.834 +12.791 +.000 +.000 
 +.000 +.000 +.000 +.000 +2.345 +11.586 -3.454 +14.429 
 
 +49.837 +14. 1+29 +.000 +4.932 
 
 +.000 +.000 +2.360 +.000 +2.653 +9.776. -3.856 +11.640 
 
 +44.879 +12 . 791 +.000 +I.561 
 +.000 +.000 +2.360 +.000 +3.865 +11.599 -3.^29 +14.429 
 
 +49.471 +14.429 +.000 +6.798 
 +.000 +20.000 +.000 +.000 -7.736 +4.158 -14.765 +.000 
 
 +.000 +.0000 +.000 +.000 
 +.000 +20.000 +.000 +.000 -4.832 +7-243 -12.410 +.000 
 +.000 +.000 +.000 +.000 
 
 +.000 +20.000 +2.360 +.000 -4.850 +5.063 -13.007 +.000 
 
 +.000 +.000 +.000 +.000 
 
 +.000 +20.000 +2.360 +.000 -1.903 +8.108 -10.626 +.000 
 
 +.000 +.000 +.000 +.000 
 
 -22- 
 
Bleeder Circuits For All Logic (Base = -0.6) 
 (Results are from program no. 928) 
 
 R0 Rl R2 R3 R4 R5 V E 
 
 +1.800 +1.200 +.770 +3.300 +950.000 +950.000 +25.000 +25.000 
 
 F G Q S A MIN A MAX A B 
 
 +25.000 +25.000 +.000 -+.000 4.910 +1.000 "0O3O +.030 
 
 VI IE0 ILI 112 T U W IC 
 
 WC IE 1DI H>3 
 
 -.600 +.000 +.000 +.000 +1.042 49.672 =4.058 +11.932 
 
 +41.258 +13.112 +.000 +.14.1 
 -.600 +.000 +.000 +.000 +2.349 +11.589 -3.449 +14. 770 
 +42.077 +14.770 +.000 +5.268 
 
 -.600 +.000 +2.360 +,000 +2,661 +9.782 =30846 +11.932 
 
 +38.727 +13.112 +.000 +1.842 
 
 -.600 +.000 +2.360 +.000 +3.868 +II060O =3o425 +14.770 
 
 +41.725 +14.770 +.000 +7.13 1 * 
 +.600 +.000 +.000 +.000 -7.736 +4.158 =14.765 +.000 
 
 +.000 +.000 +12.886 +.000 
 
 +.600 +.000 +.000 +.000 =^.832 +7.243 =12.410 +.000 
 
 +.000 +.000 +14.454 +.000 
 
 +.6000 +.000 +2.360 +.000 =4.850 +5.063 =13.007 +.000 
 
 +.000 +.000 +12.886 +.000 
 
 +.600 +.000 +2.360 +.000 =1.903 +8.108 =10.626 +.000 
 
 +.000 +.000 +14.454 +,000 
 
 
 •23- 
 
Flipflop Single Bleeder Circuit 
 
 (Results are from program no. 928) 
 
 , RO Rl R2 R3 R4 R5 V E 
 +1.300 +.9^0 +.620 +2.700 +950.000 +950.000 +25.000 +25.000 
 F G Q S A KIN A MAX A B 
 
 +25.000 +25.000 +.000 =4. 000 +.910 +1.000 +.030 +.030 
 
 VI IEO ILI IL2 T U W IC 
 WC IE IDI ID3 
 -.600 +.000 +.000 +.000 +1.118 +9.762 =-3.884 +16.471 
 +5+. 097 +18.101 +.007 +.82+ 
 
 -.600 +.000 +.000 +.000 +2.301 +11.605 -3.4l6 +20.345 
 
 +57.295 +20.345 +.050 +7.797 
 
 -.600 +.000 +2.360 +.000 +2.329 +9.789 -3.831 +16.471 
 
 +53.219 +18.101 +.007 +2.692 
 
 -.600 +.000 +2.360 +.000 +3.527 +11.613 -3.399 +20.345 
 
 +56.939 +20.345 +.050 +9.669 
 
 +.600 +.000 +.000 +.000 =8.115 +3.978 -15.114 +.000 
 
 +.000 +.000 + 17.832 +.000 
 
 +.600 +.000 +.000 +.000 -5.226 +7.064 -12.778 +.000 
 
 +.000 +.000 +19.984 +.000 
 
 +.600 +.000 +2.360 +.000 -5.803 +4.696 -13.721 +.000 
 
 +.000 +.000 +17.832 +.000 
 
 +.600 +.000 +2.360 +.000 -2.876 +7.75.1 -11.363 +.000 
 
 +.000 +.000 +19.984 +.000 
 
 -24- 
 
Flipflop Split Bleeder 
 (Results are from program no. 928) 
 
 RO 
 
 Rl 
 
 R2 
 
 R3 
 
 R4 
 
 R5 
 
 V 
 
 E 
 
 +1.300 
 
 + .9^0 
 
 +2.300 
 
 +11.000 
 
 + .840 
 
 +3.800 
 
 +25 .000 
 
 +25.000 
 
 F 
 
 G 
 
 Q 
 
 S 
 
 A MIN 
 
 A MAX 
 
 A 
 
 B 
 
 +25=000 
 
 +25 .000 
 
 +2 .000 
 
 -4.000 
 
 + .920 
 
 +1.000 
 
 + .030 
 
 + .030 
 
 VI IEO IL1 IL2 T 
 
 WC IE ID1 ID3 
 
 +.000 +.000 +.000 +.000 +.689 
 
 +6+. 192 +17.664 +.000 +.386 
 
 +.000 +.000 +.000 +.000 +1.875 
 
 +68.250 +19.923 +.000 +7.063 
 
 +.000 +.000 +.000 +2.360 +.783 
 +62.367 +17. 664 +.000 +2.183 
 
 +.000 +.000 +.000 +2.360 +1.892 
 +67.850 +19.923 +.000 +8.9+8 
 
 +.000 +.000 +1.630 +.000 +3.809 
 +62.617 +17.66^ +.000 +l.6l4 
 
 + .000 +.000 +1.630 +.000 +5.0+7 
 +67.963 +19-923 +.000 +8.378 
 
 +.000 +.000 +1.630 +2.360 +3.835 
 +62.10+ +17.664 +.000 +3-522 
 
 + .000 +.000 +1.630 +2.360 +5.062 
 +67.606 +19.923 +.000 +10.265 
 
 +.000 +20.000 +.000 +.000 -8.903 
 
 +.000 +.000 +.000 +.000 
 
 +.000 +20.000 +.000 +.000 -5.866 
 
 +3.670 +.285 +.000 +.000 
 
 u 
 
 w 
 
 IC 
 
 + .909 -3»950 +16.251 
 
 +2.121 -3°+26 +19.923 
 
 +2.594 -3.838 +16.251 
 
 +3.791 -3.406 +19.923 
 
 +.939 -3.853 +16.251 
 
 +2.132 -3»4ll +19.923 
 
 +2.607 -3.822 +16.251 
 
 +3.801 -3.393 +19.923 
 
 -8.594 -15.431 +.000 
 
 -5.541 -12.886 +.285 
 
 .25- 
 
Flipflop Split Bleeder 
 (Cont'd.) 
 
 +.000 +20.000 +.000 +2.360 -7.722 -5-832 -1+.017 +.000 
 
 +.000 +o000 +.000 +.000 
 
 +.000 +20.000 +.000 +2.360 -+.690 -2.723 -11. ++8 +.285 
 
 +3.260 +.285 +.000 +.000 
 
 + .000 +20.000 +1.630 +.000 -5.0+1 -7-778 -11+.++5 +.000 
 
 +.000 +.000 +.000 +.000 
 
 +.000 +20.000 +1.630 +.000 -1.885 -k. 729 -11.883 +.285 
 
 +3.384 +.285 +.000 +.000 
 
 +.000 +20.000 +1.630 +2.360 -3.860 -5.016 -13.032 +.000 
 
 +.000 +.000 +.000 +.000 
 
 +.000 +20.000 +I.63O +2.360 -.709 -1.910 -10.445 +.285 
 
 +2.975 +.285 +.000 +.000 
 
 -26- 
 
APPENDIX II 
 SPEED TESTS 
 
 Circuit Speed Tests 
 
 The speed tests were conducted using a relay pulser in order that 
 the individual operation times for each circuit and direction of switching could 
 be evaluated. However, in order to eliminate any special effects due to the low- 
 source impedance of the relay pulser, an extra logical circuit was always inserted 
 between the relay pulser and the circuits under test. 
 
 In addition to checking the speed of each circuit under different load 
 conditions, a check was also made of the speed of one of the circuits serving as 
 the load to determine speed changes caused by differences in available driving 
 signal currents. 
 
 The 517 oscilloscope was used for all tests with a 2 cm vertical deflec- 
 tion. The operation time of a circuit was taken to be the time between the 50$ 
 point of the input signal to the 50$ point of the output signal. The values ob- 
 tained agreed within 1 mus when several circuits were cascaded and measured as 
 a unit. 
 
 
 -27- 
 
_n_* 
 
 _n_ 
 
 NO EXTRA LOAD 
 
 2 MORE AT X 
 
 14 
 
 12 
 
 ->- 
 li 1/2 
 
 12 1/2 
 
 ~N 
 
 Speed of essentially 
 
 the same when 
 
 Q's were 0.92, 0.95, 0.95, 
 
 Lower numbers are 
 for E.F. a = .92 
 J.n second A . 
 
 — 11— INPUT 
 NO EXTRA LOA0 
 
 2 MORE AT X 
 
 II 1/2 
 
 11 1/2 
 
 13 
 
 7 1/2 
 
 b i/2 
 
 7 1/2 
 
 "A 
 
 J 
 
 Speed of last 
 
 essentially the 
 
 same when 
 
 a's were O.92, 0.95, 0.95. 
 
 Lower numbers are 
 for E.F. a = .92 
 in second A . 
 
 Figure ik 
 -28- 
 
JL 
 
 NO EXTRA LOAD 
 
 WITH 2 MORE A AT X 
 
 7 1/2 
 
 12 
 
 13 
 
 12 
 
 13 
 
 Lover numbers indicate 
 
 E. F. a = .92 . 
 
 A a's = 0.95, 0.95, O.96 
 
 AT INPUT 
 NO EXTRA LOAO 
 
 2 MORE A AT X 
 
 13 1/2 
 
 13 
 
 10 
 
 Lower numbers indicate 
 
 E. F. a = .92 . 
 
 A a's = 0.95, O.95, O.96 
 
 J 
 
 Figure 15 
 
 -29- 
 
RELAY PULSER 
 
 TT 
 
 NO LOAD 
 
 MODIFIED E. F. 
 
 NO EXTRA LOAD 
 
 4 MORE AT X 
 
 12 
 
 13 1/2 
 
 -\r 
 
 FROM PULSE 
 
 NO EXTRA LOAD 
 
 4 MORE O AT X 
 
 12 
 
 Figure 16 
 -30- 
 
a only in its socket -- ID mas 
 
 i, b, c, d all in sockets -- 12-1/2 nps 
 
 a only in its socket — 12 nps 
 
 k total — 15 BjJLB 
 
 output 
 
 output 
 
 Figure 17 
 -31- 
 
Transistor Speed Tests 
 
 A check of 550 transistors was made in a standard AND-NOT circuit driven 
 directly "by a relay pulser. The collector base voltage was 1.7 volts during con- 
 duction. A switching time, defined as the time from the 10$ point on the input 
 signal to the 50$ point on the output signal was used as a measure of the speed 
 of the transistor. The test provides a method of locating transistors with un- 
 usually large C . 
 
 Most of the values, 520, were between 17 and 19 mus. Those above 20 mus 
 were recorded separately and are shown in the bar graph of figure 18. If values 
 up to 22 mus were accepted, then only 17 out of 550, or about 3$? would be rejected. 
 
 It was found, in a small sample test, that the fast switching units re- 
 mained so, down to less than 1 v collector to base, but the slower ones (25 mus) 
 slowed further as the voltage was reduced from 1.7 v. A test conducted at 1 v should, 
 show a sharp distinction between fast and slow units. 
 
 -32- 
 
a 
 
 No. Te; 
 
 sted 
 
 No. 
 
 > 20 mus 
 
 >98 
 
 73 
 
 
 
 3 
 
 >98 
 
 8 
 
 
 
 1 
 
 >98 
 
 lU 
 
 
 
 2 
 
 >98 
 
 172 
 
 
 
 8 
 
 Times of those > 20 mus 
 
 B 319 ^0 B 337 21-1/2 
 
 B 320 35 
 B 192 20-1/2 
 B 379 22 
 B 829 21 
 B 335 21 
 B 433 > 100 
 
 B 329 35 
 B 658 24 
 B 839 > 100 
 W 893 21 
 W 573 21 
 W 654 25 
 
 97-98 
 
 112 
 
 97-98 
 
 77 
 
 97-98 
 
 33 
 
 97-98 
 
 21 
 
 11 
 
 
 
 1 
 
 3 
 
 G 36^ 40 
 
 G 358 100 
 
 G 498 21 
 
 G 284 26 
 
 G ^52 21 
 
 G 295 65 
 
 G 771 21 
 
 G I89 21 
 
 G 490 21 
 
 G 19^ 21 
 
 G 463 22 
 
 Y 1+82 23 
 
 Y 914 38 
 
 Y 880 23 
 
 Y 832 32 
 
 <97 
 
 5 
 
 <97 
 
 29 
 
 <97 
 
 5 
 
 TOTALS 
 
 5U9 
 
 1 
 
 
 
 30 
 
 Most values were 17-^19 • 
 14 + 
 
 12 
 
 ID- 
 S' - 
 6- 
 4- 
 2-- 
 
 13 
 
 20 
 
 JUL 
 
 684 21 
 
 8 
 
 30 2 
 mjj sec 
 
 Figure 18 
 
 40 
 
 > 
 
 65 
 
 100 
 
 -33-