WMSmmm BRIBBrh ■WUBUfl H BnSfsllII n ■QWl H if! IBB B9BHI3 H H ■VBbBmBmIBhBI ■ana «?*>. m kibi ■MB ORB IP H ■ H ran w is H MS i H w 81 H Bob v ib ■flBBMnflnKH nn HMD JIHBJWL1I J HUUBmUDli UoU&iil&iaHfl SMI ■till] BHD W M BBfl LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.8+ I46r no. 679-68+ cop. 2 The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN NOV 5 OCT 13 RECD J > « . > '_/ L161 — O-1096 &4/2UIUCDCS-R-7 i *-682 S?UlXH A CORRELATION MODULATION ty Richard Joseph Kowall October, 197 1 * DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS THE LIBRARY OF THE MAR 24 1975 UNIVERSITY OF ILLINOIS UIUCDCS-R-7 1 +-682 CORRELATION MODULATION by RICHARD JOSEPH KOWALL (October, 191k) Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part "by Contract No. N000-lU-6T-A-0305-002i+ and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering, at the University of Illinois. Digitized by the Internet Archive in 2013 http://archive.org/details/correlationmodul682kowa Ill ACKNOWLEDGMENTS , First I would like to thank Dr. W. J. Poppelbaum for his guidance and support over the past two years. The idea of Correlation Modulation came from him and he helped to steer me toward the right goal as this project evolved. A special note of thanks is due to Rob Budzinski for his comments, insights, and circuit designs, all of which have proved invaluable to me. I would also like to acknowledge the efforts of Frank Serio and his crew in the shop who layed out and constructed all of the cards used in Correlation Modulation. They did an excellent job. Last, and most of all, I would like to thank my fiancee, Barb Pienkos, for all the love, help, and support she has given to me since I met her. IV TABLE OF CONTENTS Page 1. GENERAL OVERVIEW 1 2. THEORY OF SHIFT REGISTER SEQUENCES 3 3. THEORY OF OPERATION 8 h. SYSTEM DESCRIPTION . 21 U.l Transmitter ----------------------21 k.2 Receiver ------------------------25 5. CIRCUIT DIAGRAMS 32 6. A GLANCE AT THE FUTURE 53 LIST OF REFERENCES 55 LIST OF FIGURES Figure Page 1 Generalized Shift Register -------------- I4 2 Simple Shift Register Sequence Generator ------- k 3 Sample Random Pulse Sequence ---_----_____ 9 h Transmitter Block Diagram --------------- 10 5 Receiver Block Diagram ---------------- 12 6 Correlation Modulation SRPS Generator ---------15 7 3-Bit SRPS Generator l6 8 U-Bit SRPS Generator 17 9 18-Bit Shift Register and Its Contents 19 10 Detailed Transmitter Block Diagram ----------22 11 Detailed Receiver Block Diagram ------------ 26 12 First Part of the 6-Bit Encoder 28 13 Second Part of the 6-Bit Encoder 29 Ik Part of a Typical D/A Converter Output 31 15 Microphone Amplifier Circuitry ------------33 16 Analog-To-Digital Converter —————————————— 3U 17 System Driving Circuitry ---------------35 18 Digital Delay and Data Selection ----------- 36 19 Digital Delay and Data Selection (continued) ----- 37 20 A/D Latch and Final Data Selection 38 21 Delay Decoding 39 22 Delay Decoding (continued) -------------- 4o 23 Delay Decoding (continued) -------------- hl 2k Delay Decoding (continued) -------------- 1+2 VI Figure Page 25 Delay Decoding (continued) —————————————— U3 26 Delay Decoding (continued) -------------- kk 27 Delay Decoding (continued) —————————————— U5 28 Delay Decoding (continued) —————————————— U6 29 Buffer Circuitry kf 30 Reset Sequencing Circuit --------------- i+8 31 Initial 6-Bit Encoding U9 32 Initial 6-Bit Encoding (continued) ---------- 50 33 Final 6-Bit Encoding 51 3U D/A Conversion and Audio Amplification --------52 1. GENERAL OVERVIEW . The "basic purpose of Correlation Modulation is to encode information in a variable time delay between two identical signals. The length of this time delay represents the information we wish to communicate. The two signals are: (l) a reference signal, and (2) a time delayed version of this same reference signal. The reference is transmitted on one channel and the delayed version is sent on a second channel. When these two signals are received, they must be compared, and the information carried by the time delay extracted by suitable means. One can see that this scheme lends itself well to secretive communi- cations, for each of the two signals by itself is totally meaningless. Only a well-informed observer will be able to get information from the two signals. In fact, Correlation Modulation is an extension of the Wilcox communication scheme used for secret telegraphic communications in World War II. In the Wilcox scheme, white noise was transmitted along with a time delayed version of the same white noise. At the receiver, these two signals were visually compared using a cathode ray tube (oscilloscope). A long time delay was used to represent a "dash" and a short time delay was used to represent a "dot" of the Morse code. These long and short time delays would then be clearly visible on the cathode ray tube. Correlation Modulation extends the number of possible time delays from 2 to 6U. It thus has the ability to approximate an analog signal by a set of digital delays. The time delay can be made to vary with the amplitude of the analog signal by mapping the set of digital delays onto the voltage range of the analog signal. In the mapping the amplitude of the analog signal at a particular instant of time lies nearest to, and thus determines, a single digital time delay. This time delay can now be sent to the receiver via the reference and delayed reference signals. If we represent the reference signal by r(t), then the delayed reference signal can be represented by d(t) = r(t-r) where t = nA = the time delay between the two signals, n = 0, 1, 2, ..., 63 = the number of standard time delays, A = the length of one standard time delay, i.e., the length of one clock period in Correlation Modulation. 2. THEORY OF SHIFT REGISTER SEQUENCES In general a shift register is a set of blocks, called stages, each of which stores a bit of binary information (see Figure l). When this shift register is driven by a clock, information is shifted from one stage to the next on each clock pulse. The first stage of the shift register gives its information (logical 1 or logical 0) to the second stage and takes a new bit of information from an external source. A shift register sequence is formed when one replaces the external source by a modulo 2 adder whose inputs are the outputs of two or more of the shift register stages. A simple example of this is shown in Figure 2. The shift register sequence is the succession of states gone through by the shift register. Theorem 1: The succession of states in a shift register sequence is r periodic, with a period p < 2 - 1 where r is the number of shift register stages. Proof: Each state of a shift register is completely determined by the previous state. Thus if it ever happens that a state is the same as some previous state, then the following states will be the same as those following the previous state, and periodicity is established. Next since there are r stages in the shift register and each one r can be only logical or logical 1, there can be at most 2 states before a repetition occurs. Thus there is a periodicity of P = 2 r . Finally, if the "all logical 0" state ever occurs, the following states will also be "all logical 0." The periodicity in this case Figure 1. Generalized Shift Register V 1 2 3 / f /moc > ADDER Figure 2. Simple Shift Register Sequence Generator is p = 1. Thus any long sequence cannot contain the "all logical 0" r state, and p < 2 - 1. Now it is important to notice that the history of any one stage of the shift register is the history of the first stage delayed by an appro- priate number of clock periods. Thus to study the shift register sequence all one needs to do is study the history of the first stage. Suppose that the history of this first stage is given by a , a , a , ..., a . From the feedback arrangement, a is a modulo 2 sum of the contents of several of D n st the stages of the shift register at the (n-l) state. Since the state of each stage can ultimately be traced back to a previous state of the first stage itself, a can be written in terms of its previous states, n a = c. a , + c_, a _ + ...+ c a n 1 n-l 2 n-2 r n-r' where r is the number of stages in the shift register. Addition is, of course, modulo 2. This type of sequence is called a linear recurring sequence. One may now associate with the history of the first shift register 00 stage a generating function G(x) = Z a x n . The initial state of the n=0 n shift register may be thought of as a , a^g ? • • • 3 a _ • Since the history of the first stage satisfies the recurrence relation, r El ~ L> C . El ■ a n . , l n-i i=l CO v» p 00 we have G ( x ) = Z Z c.a .x = Z c.x Z a .x n=0 i=l i=l n=0 Y> oo G(x) = Z c. x [a . x~ + ... + a n x + Z ax]. 1=1 n=0 r -1 Thus G(x) = Z c. x 1 [a_. x 1 + . . . + a_ x + G(x)], i=l X X and G(x) - Z c. x G(x) = Z c. x (a_. x + ... + a x ). i=l X i=l X X r -1 Z c.x (a_.x +...+ a_ x ) Therefore G(x) = — . 1 - Z c. x i=l X If the initial conditions a _ = a -,-...- a, =0 and a =1, -1 -2 1-r -r c the above expression reduces to G(x) = . 1 - Z c. x i=l X th r The r degree polynomial f(x) = 1 - Z c.x is referred to as the i=l 1 characteristic polynomial of the sequence generated by the shift register. Note that the characteristic polynomial of a shift register is obtained by taking f(x) = 1 - Z x , where the sum is taken over those values of j for which the j tube feeds its output back into the modulo 2 adder. As we shall see in the next section, Correlation Modulation will use a shift register generated sequence with the characteristic equation f(x) =l-x -x -x -x. Theorem 2: If an r-stage shift register sequence A = {a }' = {a , a , ...} obeys the initial conditions a n =a_=...=a n =0, a =1, J -1 -2 1-r -r then the period of A is the smallest positive integer p for which the characteristic polynomial f(x) divides 1-x , modulo 2. 00 Proof: For the stated initial conditions, G(x) = -rn — r = Z ax, t{X} n=0 n i. If A has period p, then — r = ( a_ + a, x + . . . + a -, x ) + x ( a_+ a n x + . . . + a , x ) f(x) " vcl T ^1 A T ■•• T p-1 A ' T * va Q T a l A T ■"• p-1 + x(a_ + a n x+...+a -,x ) + ... U I p-1 1 = (a, + a n x + . . . + a , x P_1 ) (l + x P + x 2p + x 3p + . . . ) f(x) Ka °1 A p-1 (a Q + a 1 x + ... + a p-1 x^ 1 ) f(x) (1 - r*) Thus (l f(x) P) = (a + -1 x + '•• + a p-l X P_1) and f(x) divides 1-x . ii. Conversely, if f(x) divides 1-x , let the quotient be P-1 a„ + a., x + . . . + a , x ^ 1 p-1 p-1 a^ + a n x + . . . + a x^ 1 1 p-1 Then 77^7 = ~ f(x) ± _ x p = (a Q + a x x + ... + a 1 x P_1 )(l + x P + x 2p + x 3p + ...) f(x) HxT = (a o + a i x + *•• + Vi x?_1) + xP(a o + a i a . x p - X ) + ... p-1 x + ... + 1 „ n _ / n n = E a x = G[x) = E a x , f (x) _ n n __ n n=0 n=0 Equating coefficients of like powers of x, one sees that {a } = {a }, so n n that A has p or some factor of p as its period. Thus, the smallest positive integer p for which f(x) divides 1-x is the period of A. Using the information in this section one can construct tables indi- cating what feedback arrangements give sequences of maximum length for a 2 particular shift register. Use of such tables made it easier to implement Correlation Modulation. 3. THEORY OF OPERATION .Correlation Modulation transmits audio (voice, music, etc.) informa- tion using time delay modulation of a pseudorandom sequence of pulses. A random pulse sequence is one in which the occurrence of a rectangular pulse in any particular time slot cannot be predicted ahead of time. Only the probability of occurrence can be established, analagous to the throwing of dice. A sample random pulse sequence is shown in Figure 3- A pseudorandom pulse sequence "looks" like a random pulse sequence, but if we watch it long and closely enough we will see that it repeats a pattern. If, however, this pattern is quite long, the pseudorandom pulse sequence will appear to be a random pulse sequence for all practical periods of time. In Correla- tion Modulation this pseudorandom pulse sequence performs a function simi- lar to that of the white noise in the Wilcox communication scheme. Thus the signals we wish to send are: (l) the reference pseudorandom pulse sequence, and (2) a time delayed version of the reference. A block diagram of the Correlation Modulation transmitter is shown in Figure h. We have chosen to use 6h standard time delays to simplify the implementa- tion of the system. These 6k time delays are obtained by .clocking the pseudorandom pulse sequence (also called a synchronous random pulse se- quence and abbreviated SRPS) into a 64-bit serial-in, parallel-out shift register which is used as a digital delay line . (it should be noted at this point that the pseudorandom pulse sequence generator is driven by the system clock and that the inversion of the system clock drives the 64-bit shift register. Thus a new bit of the pseudorandom pulse sequence will be ready each time the 6U-bit shift register is clocked. ) So, if the input to the shift register is high, corresponding to a logical 1, the output of the first stage will be high after the first clock pulse, T i ME SLOT / HIGH LEVEL ^ ^LOW O 1 > 1 > 1 1 1 1 1 1 1 1 1 1 ! 1 ! 2 j 3 ! 4 | 5 | 6 J 7 j 8 ' 9 j 10 ' II j 12 ] 13 J 1 I I 1 1 | | | | 1 1 I i | | | | 1 i | 1 ' i ' III I'll 1 ill 1 ' • ' , ' 1 I l 1 | .1 1 || I'll 1 ' 1 i i 1 i 1 | 1 1 1 ' 1 i I 1 III 1 1 1 II, 1 1 1 1 > I 1 1 1 1 II 1 1 1 I ■}! i ' i ' i i | i i i i Jl i i i J • i ' ' i i ' i 1 i i i i i ' i i ' i ' i i i i i i i i i i . i i i i i Figure 3. Sample Random Pulse Sequence 10 MICROPHONE AUDIO AMPLIFIER 6-B/T A/0 CONVERTER 5YSTEM CLOCK C, PSEUDORANDOM PULSE SEQUENCE GENERATOR DIGITAL DELAY LINE" 3-BIT COUNTER * *-> A/D LATCH RESET SIGNAL t-£^ W REFERENCE SIGNAL I OF 64- LINES DATA SELECTOR DELAYED REFERENCE SIGNAL V&-J Figure k. Transmitter Block Diagram 11 and the output of the 64th stage will be high after 6k clock pulses. Thus this shift register is able to give us 6k delayed versions of the input to the shift register. For example, the output of the 12th shift register stage is a 12 clock pulses delayed version of the reference signal. As we will see later, sending the output of a specific shift register stage for a certain amount of time will give us information at the receiver about the amplitude of the audio signal entering the transmitter. If we now map 6k six-bit binary numbers onto the voltage range of the audio signal, we can replace the voltage amplitude of this signal by a 6-bit binary number. This function is implemented by the 6-bit A/D con- verter shown in Figure 3- We now have 6k possible digital representations for our audio signal amplitude at any instant of time. Each of these 6k binary numbers ( 000000, 000001, ..., 111111 ) can be used to pick one of the 6k shift register outputs and thus one of 6k possible time delays. The 1 of 6k lines data selector in Figure 3 represents the block of cir- cuitry which performs this last function. Our next step is to decide how long we must look at the output of any one shift register stage in the receiver to uniquely determine what time delay we are dealing with. This consideration not only determines the system clock frequency and the rate at which we sample the audio signal, but it also leads us to choose a particular kind of pseudorandom pulse se- quence. Let us first look at how we would like to deocde our signals at the receiver. A block diagram of the Correlation Modulation receiver is shown in Figure 5. Four wires connect the transmitter to the receiver. The first carries the reference signal, the second carries the delayed reference, the third carries the system clock signal, and the fourth car- ries a reset pulse synchronizing the transmitter and the receiver. In 12 REFERENCE SIGNAL RESET SIGNAL 'DELAY DECODER" d r a' 3' 60* « €2' 6 3' I OF 64 LINES TO 6-BIT ENCODER r 4" v y *y ■*■ 6-BIT D/A CONVERTER LOW PASS ACTIVE FILTER AUDIO AMPLIFIER SPEAKER Figure 5. Receiver Block Diagram 13 the receiver we would like to clock the reference signal into a 6k -bit shift register identical with the one in the transmitter. If we compare the delayed reference signal with each of the parallel outputs of the shift register for an appropriate period of time, we will find that only- one of the shift register outputs exactly matches the delayed reference signal. This shift register stage corresponds to the one in the transmit- ter from which the delayed reference signal came. Once we have this in- formation, we can encode the shift register stage number into a 6-bit binary number. These bits then drive a digital-to-analog converter which, after some signal conditioning, drives the loudspeaker from which we de- rive the transmitted audio information. Let us look more closely at the method used to compare the outputs of the 6U-stage shift register with the delayed signal, i.e. the delay decoder . We compare these two signals in EXCLUSIVE-OR ' s , which will output a logical 1 whenever there is a discrepancy between the delayed signal and the shift register output. The JK-flipflop associated with each EXCLUSIVE- OR will be set to a logical 1 after the first discrepancy occurs, and be- cause of the way the circuit is wired, the JK-flipflop will remain at a logical 1 until the occurrence of a clear pulse. At this time all flip- flop outputs will be returned to zero. As we compare the delayed refer- ence signal with the outputs of the shift register sections, the flipflops will one-by-one be set to a logical 1. Soon all but one of the flipflops will be in the logical 1 state. The only flipflop remaining in the logical 0_ state will be the one at which the delayed reference signal exactly matches the shift register stage output . The shift register stage at which this occurs indicates the time delay between the reference signal and the delayed reference signal. At this point the outputs of the flip- 1U flops are ready to be fed into the 1 line of 6U lines to 6-bit encoder for eventual processing into an audio signal. To determine how long we must compare the delayed reference signal with the outputs of each shift register stage so that all but one of the JK-flip- flops are in the logical 1 state, we must return to the transmitter and look more closely at the generation and the form of the pseudorandom pulse se- quence. A simplified block diagram of the Correlation Modulation SRPS generator is shown in Figure 6. Feedback is taken from the shift register 2 in such a way that a maximum length sequence is formed. For an 8-bit shift register generated sequence, a maximum length sequence is a pattern of o logical l's and logical O's which does not repeat itself for 2 - 1 = 255 clock pulses. A simple example for a 3-bit shift register generated 3 sequence of maximum length is shown in Figure 7> Each clock pulse from the system clock advances the shift register to the next state. Now let us look at the output of any one stage of the shift register, for example, the rightmost stage. During the period of 7 clock pulses, we see that each set of 3 consecutive states is unique. No set of 3 consecutive states is the same as another set of 3 consecutive states, as long as we look at 3 no more than 2 +3-2=9 consecutive states in the pattern. We will show that this is true for any maximum length shift register generated sequence, but first let us look at another example. The example is just that of a k- bit pseudorandom pulse sequence gen- erator. The sequence is maximum length and is shown in Figure 8. In this case no k consecutive bits output from the last stage of this shift register are repeated, as long as we stay within the maximum length of the sequence plus k - 1 = 3 states. We will now show why the h consecutive bits are always different with- in a sequence 18 states long. Let us take the outputs of the last stage of 15 I o \ 2 3 A 5 6 7 8-BIT SERIAL-IN ; PARALLEL-OUT SHIFT REGISTER Figure 6. Correlation Modulation SRPS Generator 16 'N»7 ; AL CONDITION: CLOCK * 3-BIT SERIAL PARALLEL-OUT SHIFT REGIS -IN, TER r* O 1 a 1 ^yV <^r OUTPUT D OUTPUT 1 OUTPUT P 1 1 1 1 1 i "^ 1 1 1 i 1 > 2 3 -l = 7 1 DIFFERENT 1 STATES 1 J BEFORE 1 REPETITION Figure 7- 3-Bit SRPS Generator IT CLOCK 4--BIT SERIAL-IN, PARALLEL- OUT SHIFT REGISTER 0< JTPUT OUTPUT 1 a^TPYT £ oltput :^ Ifc'TIAL CONDITION c. o 1 1 1 o 1 1 1 1 D, 1 1 E. 1 i F. 1 I G I 2 4 -i-!5 ^ H. [ DIFFERENT 1. ! STATES J. 1 BEFORE K. 1 1 REPETITION L. 1 1 1 1 1 1 1 N. I 1 1 Ko. 1 1 1 Figure 8. U-Bit SRPS Generator 18 the SRPS generating shift register and clock these into an 18 bit serial-in, parallel-out shift register. Using the initial condition given in Figure 8, the l8-bit shift register, when full, will have the contents shown in Figure 9» As can be seen in this figure, each k consecutive bits are different states in the maximum length sequence of different states shown in Figure 8. Thus since each set of k consecutive bits is a different state, any set of k consecutive bits in the l8-bit shift register is dif- ferent from any other set of k consecutive bits. This statement can be generalized to any n-bit shift register generating a maximum length ran- dom pulse sequence. Any set of n sequential bits put out by any stage of the shift register will be different from any other set of n sequential bits put out by that same stage as long as we only look at a sequence of 2 n - 1 + (n - 1) = 2 n + n - 2 or fewer bits. In Correlation Modulation, we are using an 8-bit shift register to generate our pseudorandom pulse sequence (see Figure 6). We are feeding the output of the last bit of the SRPS generator into the first bit of our 6k stage digital delay line (Figure k). Since the pseudorandom pulse sequence is 255 bits long before repeating, there will definitely be no repetition in the 6k stages of the shift register. We can thus take 8 bits from any of the 6k stages during 8 clock pulses to obtain a pulse sequence different from any other pulse sequence taken from any other of the 6k shift register stages during the same 8 clock pulses. This is what uniquely determines what time delay we have sent when we are decoding in the receiver. Only that shift register stage output in the receiver cor- responding to the same shift register stage output in the transmitter that gave us the delayed signal will be the same as the delayed signal for 8 clock pulses. For this reason the receiver need only compare the two input 19 AA ,. * : ,4 ^ -— £ i 1 1 1 I 1 \ 1 1 o o 1 I 1 1 1 1 1 1 t L_ 1 3 7 13 9: T GROUP BITS IN GROUP FROM RIGHT TO IF FT CORRESPONDING IN FIGURE £ STATE 1 1010 B a OIOI A 3 101 i "0~ 4 01 IO D 5 1 too K 6 1001 F 7 0010 H 0100 G 3 1000 • J 10 0001 1 II 0011 E 12 on i N 13 n n M 1* 1 1 10 L 15 1 1 0[ c Figure 9. l8-Bit Shift Register and Its Contents 20 signals for 8 clock pulses, and the transmitter can sample the A/D conver- ter output every 8th clock pulse. 21 k. SYSTEM DESCRIPTION We shall now go more carefully through the logical construction of Correlation Modulation. All of the circuitry roughed out in logical or block diagram form here is given in complete detail in section 5. The reader will he referred to the figure in section 5 which contains each block of circuitry at an appropriate point in the discussion of that cir- cuit. Figures 15 through 3*+ can be found on pages 33 through 52. k.l Transmitter A detailed block diagram of the transmitter is given in Figure 10. We start with a microphone or tape audio input and then pass it into the k audio amplifier. The microphone amplifier provides amplification of the audio signal, and the automatic gain control circuitry keeps the audio am- plitude within a voltage range acceptable to the analog-to-digital conver- ter. As one can see by looking at the circuit diagram in Figure 15, both of these functions are performed by standard operational amplifiers. The amplified audio signal now enters the analog-to-digital converter. Here its level is given a final adjustment in the input amplifier. Then it is passed on to the window comparator which compares, the amplitude of the audio signal with the amplitude of the output of the D/A converter. The window comparator instructs the 6-bit counter to either count-up or count-down until the difference between the two signal amplitudes is within a a(a = l/6h x lOv = .156v) window of volts. The counter will then cease counting until the difference between the audio signal amplitude and the D/A converter output amplitude again becomes greater than A. Clock, C-j_» determines the rate at which the 6-bit counter counts up or down. C-]_ op- erates at a frequency of about 3 MHz. A circuit diagram of the A/D con- verter is shown in Figure l6. 22 W J'CPHCKE ' ^MICROPHONE. AUTOMATIC SAIN CONTROL AUDIO AMPLIFIER .-YSTEM CLOCK M0NO5TABUE MONOSTABLE INPUT AMPLIFIER window COMPARATOR 0/A CONVERTER J A/0 clock c, 6-BIT A/D CONVERTER 6-BlT UP/DOWN COUNTER .__ _____-! REFERENCE PSEUDORANDOM PULSE SEQUENCE GENERATOR i I SIGNAL i ***-*- I OF 64 LINE DATA-SELECTOR i 16 — O o * u-uj p - J"» 31 -2i- i 47 h-or o Ll ui ") £1 - j i/> tTryir —A 6-BIT A/D LATCH 10' II' 12' 13' 14' W„ w. ■u Wo w. 5* Oatjj «-*- P«— *- 15' DS DELAYED REFERENCE SIGNAL Figure 10. Detailed Transmitter Block Diagram 23 By means of the 3-bit counter, once every 8 system clock pulses, the A/D latch grabs and stores the output of the A/D converter. The circuit diagram of the A/D latch is given in Figure 20. The 3-bit counter can be found in Figure IT. Since no 3-bit counters are readily available in TTL, a U- bit counter has been used in conjunction with two monostables, so that every time there is a change in the Uth bit of the counter, one of the monostables outputs a pulse enabling the A/D latch. The sampling rate of the A/D latch is thus 1/8 of the system clock frequency. The system clock has been designed to operate at roughly 360 KHz; therefore, we sample the audio signal at about 1+5 KHz, a rate which is at least 3 times as fast as the rate at which the audio signal will vary. (Note: Audio signals range from about 50 Hz to about 15 KHz). Since Nyquist's Criterion states that one need only sample at a rate which is slightly more than twice the highest frequency of the signal to obtain all of the information contained in the signal, this sampling rate is more than adequate for our purposes. The A/D latch drives the 1 of 6k line data selector. Each 1 of l6 line data selector uses the lower order four bits from the A/D latch to pick one output of the 6U- bit shift register. We now have only k candi- dates, one from each group of l6 shift register outputs, for the delayed signal. This circuitry is shown in Figures 18 and 19. Using the two higher order bits supplied by the A/D latch, the 1 of k line data selector deter- mines which of the h candidates becomes the delayed signal. This signal is then sent to the receiver (via a wire in this particular project, but on a radio frequency channel in general). The complete wiring of the 1 of h line data selector is shown in Figure 20. The A/D clock, C , and the system clock, C , are both constructed using complementary monostable multivibrators. Each one in turn triggers 2k the other into its unstable state. Both monostables are designed to re- main in the unstable state the same amount of time, and the output of either monostable is a fairly good square wave . The circuit diagram of the system clock can be found in Figure 17. This clock performs all of the timing functions in the transmitter and is also sent on a wire to the receiver. The system clock is all we need to drive the pseudorandom pulse se- quence generator. This generator consists of an 8-bit serial-in, parallel- out shift register with feedback taken from four of the shift register's parallel outputs. These outputs are chosen so that when they are EXCLUSIVE- ORed together and then fed back into the first stage of the shift register a maximum length pseudorandom pulse sequence is formed. A characteristic of all shift-register generated sequences is that they do not contain the state where all outputs are logical 0. If , by chance, the register should get into the all logical state (in practice this is quite possible) the feedback setup will keep the register in the all logical state indefinitely. This would be disasterous for our coding method because the output of each state of the 6k- bit shift register would be all logical 0's. Thus we would have no way of distinguishing any one time delay from any other. The problem is solved by the addition of a i+-bit counter which is reset to the all logical state every time there is a logical 1 in shift register stage 1. If shift register stage 1 con- tains logical 0's for 8 consecutive clock pulses (implying that the shift register is in the all logical state), the Uth bit of the counter will become a logical 1 and be fed via the OR gate back into stage of the shift register. The counter will again be reset when the logical 1 reaches shift register stage 1. A complete circuit diagram is given in Figure IT. 25 The output of stage 7 of the random pulse sequence generating shift register is the reference signal which is sent to the receiver on a wire. It is also the input of the 61+ -bit delay generating shift register. This shift register is driven out of phase with respect to the random pulse se- quence generator so that both the pulse sequence generator and the shift register are not changing at the same time. The 64-bit shift register is formed from the series combination of 8-bit shift registers as can be seen in Figures 18 and 19. One of the 6U-bit shift register's parallel outputs is chosen and inverted by the 1 of 64 lines data selector to become the delayed reference signal. This signal is a delayed and inverted version of the reference signal and is sent on to the receiver. Finally, the reset signal is derived from the three bit counter and is sent to the receiver to synchronize it with the transmitter. This cir- cuitry is shown in Figure 17. 4.2 Receiver Let us recall that the receiver gets four signals from the transmitter: the reference signal, the delayed reference signal, the system clock sig- nal, and the reset signal. The receiver must process this information in such a way that the end result is an audio signal which is a good approxi- mation of the audio input to the transmitter. A detailed block diagram of the Correlation Modulation receiver is shown in Figure 11. The system clock, C , is inverted to drive the 64-bit serial-in, parallel-out shift register. The delayed reference signal is buffered in simple NOT gates to drive the 64 exclusive-OR gates. In a similar fashion the system clock, C , and the reset, R , are buffered in order to drive the 64 JK-flipflops. The circuit diagrams of the shift register stages, the EXCLUSIVE-OR gates, and the JK-flipflops are given in Figures 21, 22, 23, 24, 25, 26, 27, and 28. The buffers and clock inverting circuitry can be 26 system Clock BUFFER t y v C 2 ^2 ^2 REFERENCE I' I ' 1 MONO STABLE BUFFER ITT R, R, R, SIGNAL < ( 64-IIT SERIAL- IN, PARALLEL-OUT SHIFT RE61STER K CL g — I (|— jjpr^uo' <& r J FF Q c K CL Q 63 (x) HJ FF Ql+63 1 • • • * c, -He KCLfi DS DS| » « » DS DELAYED REFERENCE SIGNAL BUFFER T DS (— » K CL — I •i '• I • • • 63*1 1 OF G4 LINES TO 6-BIT ENCODER MO Nl N2 L__J N3 M N5 E 1 ^ &-»lT p / A LATCH | G-ilT D/A CONVERTER AMPLIFIER LOW PA 55 ACTIVE FILTER AUDIO AMPLIFIER HA SPEAKER Figure 11. Detailed Receiver Block Diagram 27 found in Figure 29- It should be noted at this point that the 6U-bit shift register and the JK-flipflops are clocked out of phase so that they do not both change simultaneously. The outputs of the JK-flipflops drive the 1 of 6U lines to 6-bit encoder. This encoder consists of a number of multiple input NAND and NOR gates. As can be seen from Figure 12, one set (A, B, C, or D) of the 8- input NAND gates gives us the bit-by-bit inverse of the lower order four bits of the 6-bit binary number which represents our analog signal. The actual circuit diagrams of this scheme are shown in Figures 31 and 32. Next, Figure 13 shows how a group of four 4-input NOR gates turns out the lower order four bits of our 6-bit digital signal using the outputs of the 8-input NAND gates of Figure 12. The final combination of NOR's, NAND's, and OR's gives us the correct high order two bits. The circuit diagrams implementing the last two functions can be found in Figure 33. We now have a 6-bit digital signal representing the amplitude of the analog signal at the input of the transmitter. At this point the D/A latch is enabled and stores the 6-bit digital signal. The D/A latch cir- cuitry is shown in Figure 32. The latch enable signal, R, comes once every eight clock pulses from the 3-bit counter in the transmitter (see Figure IT). After the D/A enable pulse is taken away, the latch holds our 6-bit binary number and we are almost ready to begin processing our next 8-bit sequence of reference signals. First, however, we must clear the JK- flipflops to the zero output state. This is done by using the falling edge of the reset signal, R, to trigger a monostable yielding a second reset signal, R , as shown in Figure 30. After this reset signal is buf- fered, it drives the JK-flipflops into the logical output state. This all happens before the rise of the next clock pulse. 28 "to O "oj ■ > " -ao *o "^ "eo ">lnu)inin«oV ^^mifliftin^u) ^^inininintnin Co rQ O (O "o "oj V "10 " O "— "oj (n "^ U» *a N> «o "« o o PQ I vo 0) •P *• "vD "to "o "vfl h- "b "—-"*$- "in "To V> 1o 7 s - "od " "'♦ "u> \o h- "*■ f- *<*> *> — — m a 1 nl rtl ^1 J <\j on M ^ (\J PJ fti W ^ ™ ru <\J OJ oJ rvl ro "O *oj V "Iq c0 o ~0 "— "o "— "hi co "•* "in so h- 29 -> HO ■*• N -> N2 ■* N3 * N* » N5 Figure 13. Second Part of the 6-Bit Encoder 30 In the meantime the D/A converter is transforming the digital output of the D/A latch into an analog signal. This signal is then amplified and passed on to a low pass active filter. The purpose of this filter is to eliminate the high frequency transitions of the D/A converter as it changes from one analog state to another. A typical D/A converter output might look like that shown in Figure ik. We must eliminate the high frequency jumps in voltage to avoid distortion in the audio amplifier. The low pass filter has been designed to have a corner frequency of 8 KHz. It's circuit diagram is in Figure 3^-. The final element of the receiver is the audio amplifier. In Correla- tion Modulation the audio amplifier is a push-pull arrangement driven "by an operational amplifier and connected to an external h^ ohm speaker. The circuit diagram of the audio amplifier can also be found in Figure 3^. 31 LENGTH ONE VOLTAGE STFf CLOCK PERIODS Figure ik. Part of a Typical D/A Converter Output 32 5. CIRCUIT DIAGRAMS This section contains, for reference, all the circuitry used to im- plement Correlation Modulation. Each circuit diagram (i.e., each Figure in this section) contains the circuitry placed on one UU-pin card and used in the Correlation Modulation System. General design considerations were given in Section k. 33 3U I I ,*, 4 BS • s T-„ jd. r * H/VAA- 3 2 2- "4: § ■- \ I — yvA^ Lw- 2 < a. ■1 tfg- a: O o o o o z o o 9 1 **■■ & ft. t^ I—. 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