LIB RAHY OF THE U N I VER.5ITY OF ILLI NOIS 510.84 K6r no. 30 1 -307 cop. 2 The person charging this material is re- sponsible for its return on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN OEC 1 3 ttff APR 6flEpO FEB 1 A.m. L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/algorithmfordela301tumm J I i ■ e J i 301 Report No ' 301 0* 7«aoo - AN ALGORITHM FOR DELAY CHECKING COMPUTER DESIGNS by Jay Merrill Tummelson January 13, 1969 THE UBRAHl Of ■., ^td 17 1969 Report No. 301 AN ALGORITHM FOR DELAY CHECKING COMPUTER DESIGNS* by Jay Merrill Tummelson January 13, 1969 Department of Computer Science University of Illinois Urbana, Illinois 6l801 * This work was supported in part by the Advanced Research Projects Agency as administered by the Rome Air Development Center under Contract No. US AF 30(602)411+4 and submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science, February, 1969. >, 301-30/ ACKNOWLEDGEMENT The author wishes to express sincere appreciation and gratitude to all those persons whose assistance made this manuscript possible. To Professor D. L. Slotnick, Thesis Advisor, who first aroused my interest in the field of Design Automation and then suggested delay checking as a possible thesis topic. To Mr. Arthur B. Carroll, whose assistance in proofreading and rewording sugges- tions proved invaluable to the final content of this paper. To Mr. D. 0. Pearson, who was an invaluable source of knowledge in Design Automation, specifically in the area of delay checking. To Mrs. Frieda Anderson and Mrs. Mildred Pape, who devoted themselves to typing this manuscript as though it were their own. To Mrs. Shirley Brown, Mrs. Diana Higgs and Mrs. Sharon Hardman who typed the lettering for the flowcharts and who would not settle for less than perfection. Finally, to Mrs. Nancy Stone, Mrs. Dianna Smith, and Mr. Jim Stevens, who painstakingly drew the boxes, diamonds, circles, lines, and arrow on the flowcharts. IV ABSTRACT The problem of delay checking computer designs is discussed along with its relation to the design automation problem as a whole. The ILLIAC IV design automation package is described as an example of systems in general. The remainder of the paper describes in detail the delay check algorithm and computer program developed by the author. Detailed description of the data formats, internal structur- ing of data and flowcharts of the program are included for those interested in the application of the algorithm. TABLE OF CONTENTS Page 1. INTRODUCTION 1 1.1 The Design Automation Problem 1 1.2 The I L LIAC IV Design Automation System 1 2. THE DELAY CHECKING PROBLEM 8 3- THE DELAY CHECK ALGORITHM 12 3-1 D evelo p ment of the Algorithm 12 3«2 G eneral Information lU 3.3 T he Compil er 15 3-4 The D elay Propagator 22 h. THE DELAY CHECK PROGRAM 23 APPENDIX 1. FORMAT OF PACKAGE TYPE INFJT 27 2. DESCRIPTIONS OF THE FORMAT OF THE GREX, FLX, and COMPONENT ARRAYS 28 3- DETAILED FLOWCHARTS OF PROGRAM 31 LIST OF REFERENCES 52 1. INTRODUCTION 1.1 The Design Automation Problem The function of design automation is to provide designers of electronic equipment assistance in the process of designing and manufacturing this equipment. Since much of the work associated with designing and manufacturing equipment is long, tedious "busy work and "because people in the computing industry are constantly looking for ways to reduce cost and improve schedules, the use of computers to aid in the design of equipment came quite naturally to the industry. At the optimum level the design automation system permits the designer to input the logic equations which define the machine he wants and the system will generate finished artwork masters, drill tapes, and prints necessary to manufacture the equipment. Unfortunately, not all design automation systems are capable of doing the entire job. Exactly how much of the job can be done by a system is a function of the equipment being designed, the parts available to implement the equipment, the allowable tolerance in the design and, of course, the design automation system itself. 1.2 The ILLIAC IV Design Automation System The ILLIAC IV design automation system is one of those which is not capable of doing the entire job. One of the major diffi- culties is that ILLIAC IV is implemented with the new emitter coupled logic (ECL) for which design specifications and wiring rules are not completely defined. Naturally, since the designers can not define rigid rules for the use of ECL, a program can not be "written to do this. The system must then provide for human interface to correct error situations not anticipated by the designer. This problem has occurred many times before (for example, when transistors first appeared or when printed circuits were first used), and as soon as designers were able to set up rigid rules then design automation was able to catch up with hardware state of the art. The problem is that we are using techniques developed for pre-ECL components to develop an ECL design automation system. It will not work, and we know it, so we must allow for error detection and correction. Because of the problems described above there are two types of programs in the ILLIAC IV design automation system. There are programs which do the actual computations necessary to design the equipment and there are programs which check the output from the computational programs at various stages to see that all the rules set up to insure correct usage of ECL are being followed. If errors are found, then the checking program will list them so that the designer may correct them before allowing the system to finish B design. This human interplay is an unfortunate but necessary part of this system, and accordingly the system was designed around ..spect. It is, therefore, possible for many part of the system to accept input from previous stages of the system as well as input generated by the designers to update or correct the design. This means that after the designer corrects an error he can use the system to insure that he has done so correctly without introducing other errors. The ILLIAC IV design automation system is a set of interconnected computer programs together with provisions for human evaluation and possible updating of intermediate results. A flow- chart for the entire system follows and is followed by a short description of what is done at each step. IO0IC TROUP TRANSCRIPT IMI 10 WIA r • i i _.J mrrxi and •1 load chkt program Lfc CORRECT ERRORS IN PIN LI8T uxnc ASSIORMERT PROGRAM loci-; partttion- dio program a orr/ig ni RIPORT PROGRAM redeftnk design abb ~TAPT over ERROR(Sl VISUAL CHECK Of REPORT by designers I ERROR(S) CORRECT ERRORS AND RETURN TO SYSTEM PLACEMENT 0ROARTZER ROUTER PR INTERPLOT ».- EHRR DW0R(8] ERBQR(S) POST-PROCE880R visiia: nmiGN DELAY-CHECX < gerber/drill nPERATION MAWTACTtmE or BOARD ILLIAC IV Design Automation System LOGIC DESIGN GROUP : The designers make the decision on the specification of the piece of equipment and generate the logic equations which define the machine. TRANSCRIPTION TO DATA CARDS : The design equations are converted to the format required by the program and are punched in data cards to be input to the program. SYNTAX AND LOAD CHECK PROGRAM : This program checks the key punched pin list data for proper format. The program also performs a load check for every source pin in the pin list. All errors are noted so that they may be corrected. CORRECT ERRORS IN PIN LIST : Errors noted above are corrected and the cards are once more input to the syntax and load check program to insure all errors have been corrected. LOGIC PAR TITIONING PROGRAM : This program partitions groups of logic into boards. It is capable of working at the functional level as well as at the physical package level. LOGIC ASSIGNMENT PROGRAM : This program makes assignment of logic to physical I.C. packages. At the same time it modifies all fields in the records affected by the above logic assignment. SORT/USER REPORT PROGRAM : Sorts the records of the pin list file as needed by following programs. The second part of this program gen- erates user reports to be checked by designers for error detection and correction. ■3UA: OF REPORT BY DESIGNERS : At this point, the designers scan the report and check to see that the partitioning and assign- ment has been done correctly. If not, corrections are made and the design process restarted at the assignment, partition, or sort /user report programs. In the case of severe errors, they may wish to redefine their design and start all over. lCEMENT : This program places the components on the board and also arranges the boards on the backplane. ANIZER : This program determines which pins are to be wired together and the sequence in which they are to be wired. UTER: This program routes wires between the pins as specified by the organizer. The output is a record for each segment of the routed wire. :ITER PLOT : This program produces a rough sketch on a line printer of the router solution. - ROCESSOR : This program checks the routed wire solution for ■-■rence to designer defined wiring rules. It also checks the Dading on each net for correctness and calculates wire delay for net. Errors flaged by the post-processor should be corrected signer. He then decides how far back to go (if the errors evere enough, he may have to alter the original design equations art ovr DELAY-CHECK : This program calculates time delay between latches to be checked by the designer for correctness. This is the part of the system that this paper deals with in detail. ARTWORK: This program checks the router solution for physical errors, produces tapes for artwork generation on a Gerber Plotter, and produces tapes for driving a numerically controlled drill for drilling the required holes on the production boards. ^ER^L^mATOT: This section produces the artwork on a Gerber plotter and drills holes on the boards. ^FACTUR^OOC^: ihis section actually finishes the board. This includes placing of components, printing of wires, and final testing of the board. 2. THE DELAY CHECKING PROBLEM In a synchronous machine the signals are retimed at a fixed clock rate. This is accomplished by gating the signals into memory elements (latches) after the signal has gone through several combinatorial gates. The amount of combinatorial logic allowed between latches depends upon the speed of the logic and the length of the clock interval. Below is shown an example net which begins at latches LI, 12, and L3 and ends at latch iA. In the example above when the clock "turns on" the latches LI, 12, and L3, the signals "stored" there are propagated through the combinatorial logic until the "result" finally reaches Ik where it will be stored and "wait" until the next clock pulse comes along to send it from lh through the next set of combinatorial logic. This is where delay checking comes in. Designers must know how long it takes for the signal to get from one set of latches to the next. In the example above, the signal from LI must go through five gates before it reaches L^+; however, the signal from L3 may go through only one (though it can also go through two, three and. four gates to get to Lh) . The example above can be used to show the two kinds of errors that designers try to avoid- Suppose the algorithm for calculating the delay along a. net was D = W + C 2 where W is the number of wires and C is the number of components . Then we can find the following delays: Longest delay from LI to L4: 6 wires + 5 components D x = 6 + 25 = 31 Shortest delay from L2 to L^: 5 wires + h components D 2 = 5 + 16 = 21 Shortest delay from L3 to L^: 2 wires + 1 component D 3 - 2 + 1 . 3 10 Further, suppose that the time between clock pulses is 20 and the length of a pulse is 5 (the units here are not important, so they have been left off). As shown below, the circuit is ill- behaved for two reasons: 1) The time from LI to LU is too long, since the signal gets to iA after the clock pulse to send it on is turned off; 2) The time from L3 to Lk is too short, since the signal gets to Lk during the first clock pulse and thus "runs ahead" of what it should do. CL0CK_ Ll-LU L3-IA L2-IA 20 31 21 Signals are started through net when clock goes on. Notice that the shortest path from L2 to iA, as shown above, gets to iA at the right time. That is, after the pulse that started on its way and before the next pulse was turned off. For a design to be correct, ther-.- must be no nets which exhibit either bad traits the above net shows. Deviations will produce in the equipment. 11 For designs which do not use ECL, delay checking is an easier task. Non-ECL logic speeds are approximately 20-30 nsec Compared to wire speeds (the best wiring runs about 2 nsec/ ft.) this is relatively slow. So slow, in fact, that in computing the delay for a net, the delay along the wires may be effectively ignored. Algorithms to calculate delay would merely need to count the number of components and multiply by the delay per component. With designs for machines using ECL (such as ILLIAC IV), the prob- lem is not so simple. Since ECL component speeds are about 2 nsec, which .is very close to the best wire speeds, delay along wires can no longer be ignored in calculating the dleay for a net. This means that algorithms for delay calculations for designs using ECL will be more complicated than those for non-ECL. With ECL, counting the components along a path as has been done, will not given an accurate approximation to the delay. For example, a net with few components but long wires may take longer than a net with many components but very short wires. 12 3- THE DELAY CHECK ALGORITHM 3.1 Development of the Algorithm The development of the algorithm described in this paper out of the need to delay check the board designs of ILLIAC IV. Since ECL is so new, the problems associated with using ECL are also quite new. Because of this, there was no algorithm available to do the job. One had to be developed. There were many factors which had to be taken into account when deciding what the best algorithm would be. Development time was one of the more important factors. The program had to be work- ing as short a time as possible. Efficiency was considered, but only as a secondary element to time. Therefore, the algorithm had ) be simple and easy to convert to a computer language. The 1 used in writing the program was Burrough's Extended ALGOL. Operations required by the algorithm had to be ones available in that language. Finally, since much of the rest of the ILLIAC IV design automation system already existed, the input data format was fixed. Exactly what data would and would not be available to delay check program was fixed, and could not be changed. With :ontraints in mind, work began to develop the best possible algorithm. 13 First of all, it was decided that the basic element in the model would be a functional element. This was chosen for its simplicity. It would be much too difficult to break up the com- ponent each time a. delay calculation had to be made. The components would be broken into functional elements once, and from that point on, everything would be based on functional elements. Now comes the question of how to store all the information in a data structure. Because of storage limitations, information would have to be packed. That is, many pieces of information would be put into one word of memory. This introduces complexity, because packed information must be unpacked to be used. But, since much of the information is binary in nature (a flag indicating true/ false, or on/off), the ineffi- ciencies of storing one data bit in a 48-bit computer word could not be tolerated. Along with this it was decided to store all information in one array, each element taking as many words in the array as necessary. This brings up the final consideration. Should the record length for the elements be fixed or variable? Fixed is simpler and easier to work with but wastes a lot of space. Because boards are very large (as many as 1000 functional elements), and because some elements require much more space for information than others, it was decided to use variable length records. Each record would start on a word boundary but could be any number of words long. 11+ The record for an element contains backward pointers to all elements which have sources which feed this element directly, forward pointers to all elements having loads for the sources in element, and other information about the element; such as, type, number of reference (forward and backward), and delay infor- mation. Using these pointers, the program is able to follow signals through the nets, adding up wire and component delays as it goes from latch to latch. By doing this, maximum and minimum delay times can be calculated for all nets. The data structure consists of variable length records of packed data. Internal pointers allow for tracing of nets both brward and backward in the circuit. (The actual format of these structures is given in Appendix 2.) 3.2 General Information If a program is to be written for a computer to perform delay check function, an algorithm must be devised which models each net internally so that the delay can be calculated using both component and wire delays. This paper presents such an algorithm and describes a program which was written based on the algorithm. 15 The algorithm consists of two parts: 1) The compiler, which creates the internal model of all the nets, and 2) The propagator, which uses the model to propagate the delays along the nets to find total delay from latch to latch. 3.3 T he Compiler The task of the compiler, as stated above, is to generate the internal model of the nets. The model was designed with the idea in mind that the input data would contain the following infor- mation about every pin in the net. 1) The signal name on the wire connected to this pin. 2) The component name or connector pin name associated with this pin. 3) What type of component this pin is on (or if this is a. connector pin, it indicates this). h) Which pin on the component this is. 5) Whether this pin represents a source or a load to the signal. 6) The delay along the wire from the source to each of its loads. 16 The model consists of several lists: one main information net list and several peripheral supporting lists. The main list con- :ord for each functional element in the net. A given imponent package may be a functional element in itself or it may ontain several functional elements. The criterion for defining a functional element is based on its output. All outputs from a functional element -mist come directly from the same gate within one component. If the output comes from a gate, then through a NOT, and then out of the component, this is also taken to mean irectly from the gate. Shown below are four ILLIAC IV component packages with explanations of the functional element breakdown in each. DILOOU In this package, since both outputs come from the same through a NOT, the other straight out), the entire package mctJ -ial element. IT DILDC In this package there are two functional elements (separated by broken line). Each has two outputs, one the actua] value of the element, the other the NOT of this value. DIL011 In this package there are also two functional elements . Notice that they share one of the inputs. 18 DIL007 In this package there are four functional elements, each sharing one common input and having but a single output. The records are of variable length and contain the follow- ing information about the functional element: 1) Is this a latch? ) Is this a connector pin and, if so, a pointer to a special connector pin list, and is this an input or output connector pin? 3) If this is not a connector pin, how many input pnals are there and how many output signals? Pointers for each input signal to the clement that the source is on. ) The wire delay from the source to the load for ■ 19 6) Pointers for each output signal to the elements to which they go. Shown below is a partial net, together with the main infor- mation net list that, the compiler would generate for it. The net is drawn at the functional element level for simplicity and the compiler puts four pieces of information in each word in the list. Ll. A j L2 L3 LU & L5 Lo 20 WORD ADDRESS (LI) (L2) (L3) (I) (ID 1 2 3 5 6 7 8 9 10 11: (III) 12: 13: 1U: (IV) 16: 17: (V) 18: 20: INFORMA TION latch, not connector pin, inputs, 1 output 6 (Pointer to Element I) , , , latch, not connector pin, inputs, 1 output 6 (Pointer to Element I) , , , latch, not connector pin, inputs, 2 outputs 9 (Ptr. to II), 15 (ptr. to IV) , , not latch, not connector pin, 2 inputs, 2 outputs (Ptr. to LI), 2 (Ptr. to L2), Delay from LI Delay from L2 9 (Ptr. to II), 12 (Ptr. to III), , not latch, not connector pin, 2 inputs, 2 outputs 6 (Ptr. to I), k (Ptr. to L3), Delay from I, Delay from L3 (Ptr. to III), 15 (Ptr. to IV), , not latch, not connector pin, 2 inputs, 2 outputs 6 (Ptr. to I), 9 (ptr. to II), Delay from I, Delay from II 13 (Ptr. to V), 21 (Ptr. to LU), , not latch, not connector pin, 2 inputs, 2 outputs 9 (Ptr. to II), k (Ptr. to Le), Delay from II, lay from L3 (Ptr. to V, 25 (Ptr. to L6), , not latch, not connector pin, 2 inputs, 1 output (Ptr. to III), 15 (Ptr. to IV), Delay from III, lay from IV 23 (Ptr. to L5), , , 21 WORD ADDRESS INFORMATION (iA) 21: latch, not connector pin, 1 input, outputs 22: 12 (Ptr. to III), , , (L5) 23: latch, not connector pin, 1 input, outputs 2k: 18 (Ptr. to V), , , (L6) 25: latch, not connector pin, 1 input, outputs 25: 15 (Ptr. to IV), , , Using the above list, the program can start at latches LI, L2, and L3, and by following pointers go from element to element until it reaches iA, L5, and L6. As the program goes along it keeps track of the delay along each path. It will know when it gets to each of lA, L5, and L6 what the corresponding delays are. Notice that signal names (shown as capital letters) completely disappear in the information list. The input to the compiler would then need to be one record for each "pin" in the design. The pins in the example are shown as small black dots. Thus, in the above example, the input would consist of only 17 records. Each record would contain the signal name, logic component name, a flag indicating whether this is the source or a load for the signal, if this is a. load the "wire delay" from the source, and the type of element this pin is on. The compiler takes the input records and first sorts by signal name. The source for each signal is distinguished from its loads and pointers are formed from the source to each load and from 22 each load to the source. The updated records (with pointers included) are now sorted by logic element name. Now, by extracting the pointers for each signal and discarding signal names, the list shown above can be generated. It should be noted that in an actual application of this algorithm (as in the one described later in this paper), the process can be made more complicated by allowing more complicated components than used above. The basic algorithm, however, would still be the same. The Delay Propagator The propagator is very simple, given the list generated by the compiler. All that need be done is that a copy of the list be made for each of two computations. Both the maximum delay time and the minimum delay time from latch to latch must be calculated. If each calculation begins at input connector pins (a list of which can be easily generated by the compiler) and follows each through the until output connector pins are reached. At this point all delays will be known and output of this information can be gener- ated. The output would describe the delay at each latch from the previous latclv ■ For nets which start on a latch on one board and reach the next latch on a different board, special interfacing must be provided for. This is merely a data handling problem and will not be . ;ed in this paper. 23 k. THE DELAY CHECK PROGRAM The program following the above described algorithm was written to run on a B5500 in Burrough's Extended ALGOL. It is intended to run after the Post-Processor portion of the design automation package furnished by Burroughs to aid in the design of ILLIAC IV. For this reason the program is, in some places, more specifically orientated to the problem of designing ILLIAC IV than a general delay checking program should be. The compiler takes its primary input from a file generated by the Post-Processor. This is the Extended Pin List File (PLF). This file consists of card image records and should contain all information for one board and no more. Each record represents one pin on the board as is formatted as follows: col. 9-1^ Package type col. 16-19 Component identification col. 21-23 Pin number col. 25-36 Signal name col. 33 Source/ load key col. 65-68 Delay (on source pins only) The package type is a six-character alphanumeric code which designates on which of the several types of modules known to the pro- gram this pin is. A list of all such modules should be provided as explained in Appendix 1. Among the possible codes should be one for connector pins and one for latches. If the code is not one of the allowable codes, the program will print an appropriate error message and terminate. 2h The component ID is a unique four- character alphanumeric name given to each component on the board. It is used to group the pins by component for processing by the program. Since this name can be any four- character string, no check is made for correctness and all names are ass ed to be correct. One exception to this is that connector pins will have as their component ID a name of the type: P-xx where xx is a number from 00 to 99* The signalname is a twelve- character alphanumeric name, unique for each signal in the system. The signalname will be the name associated with the delay on all output connector pins. The source/load key is the character S or L. As would be expected, the S indicates that this is a source pin and the L indicates a load. The delay is the amount of wire delay on each source sig- nal. This is the total delay for the signal from the source to the furthest load downstream. It was decided that, even though it is not absolutely correct, this delay would be used as the delay time from the source to each load. Since there is only one delay asso- ciated with each source, it will be present only on records which are marked as sources. The program is written as a series of sequential program segments. Each one performs some transofrmation on the data files until the input has been completely changed into the form necessary for delay propagation. A general flow diagram for these segments, along with a short description of what each does, follows. 25 READPACKAGETYPES READPINLISTFILE SORTB YS IGNALNAME C APT 1 TIYPT r\U .4 SORTB YCOMPONENT ID oUKl lsi 1 Urju.oi»i£jiM j. o ^ 1 r n.T™-RPATP^T.Y fe SCANFLX p FINDSOURCEFORPINS A I I 1L PROPAGATEDELAY ~~1 READPACKAGETYPES reads, from file PACKAGE, card image records which describe the package types allowed on the "board being delay checked. The record also will contain the number of pins in the package and the name, or pin ID, of each pin. READPINLISTFILE reads card image records from file PINLISTFILE. Each record contains information for one pin on the board. This segment checks for errors in package types and pin names. SORTBYS IGNALNAME not only sorts by signal name but also puts the source(s) for each signal ahead of the loads. FINDSOURCEFORPINS puts a pointer in GREX (see Appendix 2) for each load to its source; and for each source puts the number of loads on that source. 26 SORTBYCOMPONENTID does a pseudo-sort by component name, source or load, and pin number. The arrays COMF1 and COMPJ are formed to contain the correct order of GREX as though it were sorted. The sort is done first by component name, then by putting sources ahead of loads, and finally by putting the pin numbers in numerical order. SORTUTTOELEMENTS separates the element(s) in each com- ponent, keeping a count of them for the entire board. It generates an array called COMPONENT (see Appendix 2) with one entry for each component. Each entry contains the package type and lists the ele- ment number(s) of the element(s) in this component. GENERATEFLX generates the FLX array (see Appendix 2) which is the complete model of the board. This is the array which is used to propagate the delay. SCANFLX initiates delay propagation and calls PROPAGATEDELAY to do the actual calculations. This is the part which must be executed once for maximum delay(s) and once for minimum delay(s). PROPAGATEDELAY is a recursive procedure which calculates the delay from one element to the next by following pointers through the FLX array. Detailed flowcharts of the program are in Appendix 3 for those interested; and Appendix 2 describes, in detail, the format of the arrays used by the program to build the internal model of • 27 APPENDIX 1 FOSMAT OF PACKAGE TYPE INPUT First card: cols 1-4 Number of types - 1 cols 5-10 Connector Pin Code cols ll-l6 Latch Code Type cards: cols 1-6 col 8 Repeat this 5 column field un- til all pins are defined (this may take two cards) . Type Code Number of elements in this package Number of pins in this package - 1 Pin name Pin position on package 28 APPENDIX 2 DESCRIPTIONS OF THE FORMAT OF THE GREX, FIX, and COMPONENT ARRAYS 29 pM cq o EH CQ K H I* CM fi £3 o w h a H fa p H O CQ CQ O p p § o P CQ EH H P P P « K o WOh H P O P C/T P O H J? 8R cm LT\ rH o B H PL, o P P O P POP H P K 9 K o o o o ^ Kr tr 9 On LT\ H P o g H P <: CQ K |j Eh M H O O PM PM o § aa P Eh P^ Eh CQ CQ S H CQ P EH Seh p H . a t- 1 M P £ EH P Eh Eh Eh Eh CQ CQ CO SScj H M H rH rH II II hlhWtOE \o o p o CQ P P P O •H -P cd •rl > 9 W K} C o o « w tfr- 55 M - Rj o o K O Oh CO O 3 o CO eg O k5 w «^e H J CO O I — o o En O § Eh 2 Cr< II CO Sq K 5 D H CO H »a O II 1-3 CO Pt, w C o •H ■p a] •H > ^> <: <; o o ^ 8 9 31 APPENDIX 3 DETAILED FLOWCHARTS OF PROGPAM [ MAIS j 32 INITIALIZE ELEMENT DELAY INITIALIZE IPINS AND JPINS ONES 4- LARGEST INTEGER ZERO .-0 READ NUMBER 3F PAGKASETTFES CONNECTOR P» TYPE LATCH TYPE I .-0 READ IN FORMATION FOR PACKAGE(L) ■•;::. - I UTCH TYPE - I REM I'.. XAOETWEfl 33 SKIP 1 RECORD ON THE PLE J «-0 READ PACKAGETYPE, COMPONENTXD[I,J], PINTD, SIGNALNAME[I,J] SLKEY FROM PLF END OF file;parity ERROR ERROR: NOT ONE OF ALLOWED TYPES READPINLISTFILE PUT TYPE NUMBER AHD SLKEY INTO ORECCI.J] K - PIN NUMBER IS PUT INTO GREXfl.J] Vh J - J+l He K ♦- K+l Yes COLUMN[I] - 511 ERROR: NOT ONE OF ALLOWED PINS ERROR: PARITY ERROR ON PLF I - 1*1 ! LOOP! U- COLUMNfl] >- J-l KNDOFFI NUMBEROFPOWS «- I Ul TOO MANY RDB ON PLF (go toA I «-0 L <- J NSTOP .- J M <- I I N *- NSTOP L .- N N «-N+l NSTOP <- N > COLUMNfM'TX. No K *-M L .-N SORTBYSIGNAUiAKF, GO TO I LOOP No No M .-M+l J «- J+l Yes I - 1+1 No GO TO MLOOP Yes SWITCH INFORMATION FOR [K,L] WITH [I, J]] 37 LASTSOURCE *-0 NAME .- BLANK PIHCOUNT *- K .-0 L «- I «- SREX[I,J] .- ONES f GO To\ { ALPHA ] LOADCOUNT «- LOADCOUNT+1 PUT LASTSOURCE AND GRUNCH IN GREX[I,J] » GRUNCH <- No NAME <- SIGN AIM AME [I,J] POT LOADCOUNT AND GRUNCH IN GREX[K,L] LASTSOURCE «- [I,J] LOADCOUNT <- K <-I L <- J 4 PINCOUNT «- PUJCOUNT+1 PINNAME [PINCOUNT] *- NAME PUT LOADCOUNT AND GRUNCH IN LAST GREX[K,L] FINDSOURCEFORPINS £ J .-0 CCHPIfl.J] .-I CCWJ[I,J] »-J J 4- J4l I - 1*1 J - ,, . . -, TjjS' ^Tp,ci a \ source akd •>JP,Q1 NOT s ^SJ/^ 1 m L ~ N i ' P - P Q - S IS 'coMprp,si" = COMP|P,Q] rP^Slt[P,Q] BOTH SOURCES OP BOTH P-COMPI[I,J] Q~COMPJ[I,J] N - NETOP R- COMPI[M,Nl S- C0MPJ[M,N1 JTO 'COMP[R,Sj N 9 \o SWITCH fI,J] WITH [K,L] Yes M <- M+l J ♦- J+l Yes I - 1*1 Yes / GO To\ No No J' GO TO \ "K LOOFM J No J GO TO \ "•I LO0PI1 ) '.1 COMPONENT - COUNT- -1 ELEMENT - COUNT- -1 COMP ID-BLANK I - K«-COMPI[I,Jl L-COMPJ[I,Jl PUT COMPONENT- COUNT AND PIKPCSTTION IN GREX[K,L] -UU_ YES COMPID - COMPONENT ID[K,L] THISTYPE - WHAT TYPE THIS IS FROM GREX[K,L] COMPONENT - COUNT - COMPONENT - COUNT t 1 COMPONT[CGMP- ONENCOUNT] - THISTYPE (WITH ONES PADDED^ SORTINTOELEMENTS 1*2 C0MPH ► BLAn put pin HUMHB H COMPOUENT YES M - 1 EmMEHT- coubt - ELEMgHT- couinvi put eument- COUNT IBTO M* h COMPONENT M ~ M + 1 PUT COMPONENT COUNT AND PINP06ITION INTO ZERO ARRAY f 00 TcA J <- J+l Yes I <- 1+1 CrLUMNHT V Ho PUT PTNCUT[01 INTO GREX[K,L] PUT PTNCNT[1] INTO GEEX[K,L] PUT PIKCNTr2] INTO GREX[K,L] PUT PINCNT[3; INTO GREX[K,L] /GO To\ -H JLOOPll PHICNT[C] PUJCNTrO] • 1 PIT!'".' PTNCNTfl] PINCNT[2] PINCNT[2] 4 1 pinci ; t- PIN'':: ' ] < 1 uu WBV NUMBER OF BOWS - KUMBER OF » 1 part* y:- ; REX{ NUMBER OF ROWS, COLUMN! M*HFOFROWS]1 - ONES JiC_ COLUMN! NUMBER OF ROWSl- COLUMNt NUMBER OF ROWSl * 1 I - I J - I K-COMPIfl.Jl L-COMPJ[I,Jl GO TO i [ MLOOP1 J '■.nnwnTL* SET END OF FORWARD ADDS AT 1/3 POINT YEL' YES, weraiPTP[Ml -WOHDPTR[M] -1 SET END OF FORWARD ADDS AT 2/3 POINT SET END OF backward adds at 1/2 point PINS PEP TT.TTM EMT [M,Ol - 1 ■ljGlxpointefi - PREFLX[ M,N] N -O FLXPOIUTER - FLXPOINTER t 1 «— r SET 2 IJ D HALF OF PRETLX TO ONES NO GO TO MLOOP1 M - FUNCTION - FUNCTION + 1 ELEMENT [FUN- TIONj - FLXPO INTER PUTTHE NUMBER OF FORWARD & _^ BACJWARD AIHffiE IN PREFLX U6 ' . •* ra-iS Yes ' "TPE - M COW Yes Yes Yes □ICOUNT - DJCCWNT-l OUTCOUNT .- OUTCOUHT-.1 PUT COMPONENT NUMBER AND FLXPOINTER IN [NPINSflNCOUNT PUT COMPONENT NUMBER AND FLXPOINTER IN OUTPINSfOUTCOUNTj PUT S/L KEY AND INCOUNT □J PREFUC[0,0; PUT S/L KEY AND OUTCOUNT Di PREFLX[0,0] WORDPTRfM] - FORWARDPTR[Ml BACKWARD PTR -.9 PINSPERELEMENT [M,0] - PINSPERELEMENT fM,ll .- M ~M*1 Yes, PUT THE ELEMENT NUMBER AMD PIN POSITION INTO PREFLX UPDATE FORWARD PTR[M], WORDPTR[M], PIKSPERELEMENI [M] M .- Yea Yes NSUB -r- PLACE IN GRE> THAT THIS SOURCE IS AT NSUB *- NSUB+1 PIND *- WHICH PIN COMP «- WHICH COMP P *-l PCCMP <- WHICH ELEMENT OF THIS CCMP IS THIS P41 No M *- M+l Yes BACKWARD PTR[M] .- 1 SET END OF FORWARD ADDRESSES TO 2/3 POINT UPDATE WORDPTRfM] IF NEEDED M <-M+l NSUB - PLACE IN GREX THAT THIS LOAD IS AT YES M - SET END OF FORWARD ADDRESSES to V 2 p °ra' r BACKWARD- PTR[M] <- 2 M <- M+l Yes 1*8 PCOHP - WHICH ELEMENT OF THIS COMP IS THIS PUT THE ELEMENT NUMBER AND DELAY VALUE INTO PREFLX UPDATE WORDPTR[M], BACKWARD [Ml , PINBPER- ELEMENT[M] J ♦- J*l . Ye.T J > COLUMNf I]^> » I .- 1*1 1*9 ONE 12 - 1023 IPIN - THE Ith INPUT PIN NUMBER FORWARDPTR <- 2 ENDFLAO *- MARK DELAY(I) AS "USED" GO TO GAMMA WORDPTR +- WHERE THIS PIN IS IN FLX GO TO FSW(FORWARDPTR] FORWARDPTR *- 2 ( FSWF2] J ( FSWf3] j FORWARDPTR - 3 FORWARDPTR *-3 WORDPTR <- WORDPTR+1 FLXPTR - WHICH ELEMENT FLXPTN «- WHICH PIN FLXPTR*- WHICH ELEMENT FLXPIN.- WHICH PIN • •- GO TO FSW[ FOR- WARDPTR] FLXPTR «- WHICH ELEMENT FLXPIN .- WHICH PIN No > SCANFLX 50 0PA3ATE- DELAY No FORP ~ 2 WORP •- FIJCPTR . Yai FLXPTR I FEXPDI \ DELAY J Yee FPms •- the NUMBER OF FORWARD ADDRESSES No /isV Sthzs a ^"v \c0hkbctor^ \ pdi / FPTHS 4- 1 1 I IPINS «- WORD THAT FLXPUI POINTS TO U IPINS .- 1st OR 2nd HALF OF WORD THAT FLXPD) POINTS Tfi ' r COMPOTE DELAY FOR PIN THAT FLXPIN POINTS TO < r ADD 1 TO NUMBER OF PUS DONB^FOR THIS ELEMENT No DLAY - THE MAX (OR MTNl OF DELAY ON ALL INPUTS TO THIS ELEMENT FLXPTER <- NEXT ELEMENT TO SEND DELAY TO FLXPN <- WHICH PIN IN ELEMENT TO SEND DELAY 10. PROPAGATED ELAY FLYPTER, FLXPN, DLAY 52 LIST OF REFERENCES [1] Crowley, T. H., "Computers as an Aid to the Design and Manufacture of Systems," 19&3 IEEE International Conv. Rec, vol. 11, pt. k, pp. 4-51. [2] Gill, S., "The Use of Computers in Designing Computers," Industrial Research, vol. 15, pp. 159-l63> April, 1962. [3] Gordon, W. L., "Data Processing Techniques in Design Automation," i960 Proc. EJCC , pp. 205-209. Gray, S. R. and Kisch, R. N., "A Progress Report on Computer Applications in Computer Design," 1956 Proc. WJCC Harming, W. A. and Mayes, T.L., "Impact of Automation on Digital Computer Design," i960 Proc. EJCC , pp. 211-232. Kurtzberg, J., "Computer Mechanization of Design Procedures," Proc. of the Detroit Conf. of the AIIE , October, 196U. [7] Leichner, G. H., "Designing Computer Circuits with a Computer," J . ACM , vol. k, pp. 1I+3-II+7, April, 1957- Warshawsky, E. H., "Design Automation," Datamation , pp. 25-28, June, 1964. UNCLASSIFIED Security Classification DOCUMENT CONTROL DATA R&D (Sacurttr cl.aaltlc.tlon ot mi,. body of .b.lmel .ml lnd..h,g wwflto mu.« b, nfrad Than >/,. .„,.)/ r.p o,, ,. rlm ..„l,dJ_ I originating ACTlvi TY CCorporate author) Department of Computer Science University of Illinois Urbana, Illinois 6l8oi 3 REPORT TITLE ia. REPORT SECURITY CLASSIFICATION UNCLASSIFIED 2b. GROUP AN ALGORITHM FOR DELAY CHECKING COMPUTER DESIGNS 4. DESCRIPTIVE NOTES (Typ, ot rwport and Inclumlr, data,) Research Report S AUTHORISI (Firat mm, middl, initial, laat nam,) Jay Merrill Tummelson ft. REPORT DATE January 13, 1969 •a. CONTRACT OR GRANT NO. U6 -26 -15 -305 6. PROJECT NO. USAF 30(602)4144 10. DISTRIBUTION STATEMENT 7a. TOTAL NO. OF PACES 57 76. NO. OF REFS ORIGINATOR'S REPORT NUMBER(S) DCS Report No. 301 »6. OTHER REPORT NOISI (Any other number, that may b, aaalonod thla rapott) Qualified requesters may obtain copies of this report from DCS. II. SUPPLEMENTARY NOTES NONE 13. ABSTRACT 12. SPONSORING MILITARY ACTIVITY Rome Air Development Center Griffiss Air Force Base Rome, New York 1344-0 The problem of delay checking computer designs is discussed along with its relation to the design automation problem as a whole. The ILLIAC IV design automation package is described as an example of systems in general. The remainder of the paper describes in detail the delay check algorithm and computer program developed by the author. Detailed description of the data formats, internal structuring of data and flowcharts of the program are included for those interested in the applica- tion of the algorithm. )D ,'°?..1473 UNCLASSIFIED Security Classification UNCLASSIFIED Security Classification KEY WORDS ILLIAC IV Design Automation System Delay Check Algorithm ROLE W T UNCLASSIFIED Security Classification