Digitized by the Internet Archive in 2013 http://archive.org/details/topicsinmosfetne851cull I Report No. UIUC DCS -R -77-851 /) UILU-ENG 77 1705 t TOPICS IN MOSFET NETWORK DESIGN by Jay Niel Culliney February 1977 The Ubnty of the APR 19 1977 '■Diversity ot Illinois 'rbsna-Cfwn. DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS Report No. UTUCDCS-R-77-85I TOPICS IN MOSFET NETWORK DESIGN Jay Niel Culliney February 1977 Department of Computer Science University of Illinois at Urbana-Charapaign Urbana, Illinois 618OI his work was supported in part by the National Science Foundation under Grant 0. DCR73-03^21 and was submitted in partial fulfillment of the requirements or the degree of Doctor of Philosphy in Computer Science, January 1977 • Ill This thesis is dedicated to ray wife Yuko without whose help and great patience this work could not have been completed. iv ACKNOWLEDGMENT The author wishes to thank his advisor, Professor S. Muroga, for his invaluable guidance during the preparation of this thesis and during the several preceding years of research, and also for his careful reading and constructive criticism of the original manuscript. The author also wishes to thank Dr. H.C. Lai and Dr. Y. Kambayashi for their helpful discussions and constructive comments. The author is grateful to Zigrida Arbatsky for her typing of the manuscript. The financial support of the Department of Computer Science and the National Science Foundation under Grant No. DCR73- 03U21 is also acknowledged. TABLE OF CONTENTS SECTION Page 1. INTRODUCTION 1 2. BASIC DEFINITIONS 4 3. PROPERTIES RELATED TO OPTIMAL NETWORKS 34 h. OPTIMAL NETWORK SYNTHESIS BASED ON A NEW CONCEPT OF CLUSTERS 65 4.1 Synthesis of G-Minimal, 2-Level Networks 71 4.1.1 Synthesis methods for 2-level networks based on stratified structures 71 4.1.1.1 Liu's synthesis method for G-minimal, 2-level networks 83 4.1.1.2 Nakamura, Tokura, and Kasami's n-cube labelling method as a synthesis method for G-minimal, 2- level networks 97 4.1.2 Synthesis methods for 2-level networks based on non- stratified structures 107 4.2 Synthesis of G-Minimal, Multiple -Level Networks 124 4.2.1 Synthesis methods for multiple -level networks based on stratified structures and corresponding floor or ceiling functions 125 4.2.2 Synthesis methods for multiple- level networks based on stratified structures and corresponding extended floor or extended ceiling functions 144 5. TRANSFORMATIONS BASED ON CONFIGURATION CONSIDERATIONS TO CONTROL MOS CELL COMPLEXITIES 165 5.1 Logic Insertion/Extraction 171 5.2 Logic Duplication/Combination 182 5.3 Logic Integration/Distribution 185 5.4 Redundant Logic Addition/Deletion 194 5.5 Logic Factorization/Defactorization and Other Basic Intracell Transformations 205 vi SECTION Page 6. TRANSDUCTION APPROACH TO MOS NETWORK DESIGN 208 6.1 MOS Network Transduction Procedures 209 6.2 Computer Program Implementation of Transduction Procedures . . . .2^2 6.2.1 Program organization 2kk 6.2.2 Input format 2*+9 6.2.3 Experimental results 268 6.3 Discussion of Transduction Approach 279 7. IRREDUNDANT NETWORKS AND TEST SET GENERATION 285 8. CONCLUSIONS 317 REFERENCES 319 VITA 323 1. INTRODUCTION In recent years, MOS technology has emerged as one of the most important technologies for large-scale integration (LSI). In addition to the practical interest in MOS, it has been found that MOS cells lend themselves to theoreti- cal treatment for certain common network synthesis problems. Theoretically, an MOS cell can be constructed to realize any negative function. This fact leads to the convenient representation of a general MOS cell by a negative gate. The problem of synthesizing a 2-level network with the minimum number of negative gates was first solved by T. Ibaraki and S. Muroga. This work was then extended by T. Ibaraki to minimize either or both of the num- bers of gates and connections in a 2-level network of negative gates, although the method involves the solution of covering problems. Next, results were obtained concerning the problem of synthesizing multi- ple-level networks with minimum numbers of negative gates. Nakamura, Tokura, Tntk 72I and Kasami, pointed out that the older problem of minimizing the num- ber of inverters (NOT gates) in a network, which was solved by both Markov [Mar 58] , „.,., [Mul 58] . , _ . ^ u . . , ,, . , and Muller, is very closely related to the optimal multiple- level negative gate network synthesis problem, and they presented algorithms for the latter problem. Independently, T. K. Liu solved the same problem and also gave another approach to the optimal 2-level network synthe- sis problem. Later, H. C. Lai extended these results and presented algorithms which synthesize multiple -level MOS cell networks with minimum numbers of cells which are, in addition, ' irredundant ' in the sense that no FET's can be removed from the MOS cells of the network without altering the desired outputs of the network. Networks produced by former methods were often not irredundant. T. Shinozaki and K. Yamamoto produced and documented com- puter programs implementing MOS network synthesis algorithms of T. K. Liu and H. C. Lai, respectively. This thesis will further explore topics in MOS network synthesis. Section 2 will provide the background for later discussion by presenting basic defini- tions, theorems, and notation. The operation of an MOS cell will also be ex- plained here. Section 3 will present properties of optimal networks of MOS cells or negative gates and some properties of interest to logic designers which apply to non-optimal networks as well. These results are useful in as- sisting (optimal and/or non-optimal) network synthesis efforts and in facili- tating the recognition of non-optimal networks. After briefly reviewing several existing optimal network synthesis methods in Section k, new methods based on a redefined concept of 'clusters' are pro- posed to obtain improved synthesis results. Section 5 discusses transformation of MOS networks which are based only upon the configurations of the network and the individual MOS cells. These are suitable for use without the aid of a com- puter. An important application of these transformations would be in the transformation of networks of overly complex MOS cells (as often result from optimal MOS network synthesis algorithms) into networks of simpler MOS cells, practical for actual implementation. A new approach to negative gate network synthesis is presented in Section 6. This approach basically consists of procedures for the trans formation and re duction (referred to as 'transduction procedures') of existing networks in order to obtain simplified networks. This differs from the transformations in Section 5 in that these transduction procedures consider the specific functions of the negative gates in a network, as well as the configuration of the network itself. Thus, these procedures are both more powerful and more complex than the transformations of Section 5. Due to this complexity, implementations of the transduction procedures as computer programs are required for the solution of all but the simplest problems. Section 6 also discusses such implementa- tions and gives examples of synthesis results obtained. Section 7 presents a method for the generation of reduced test sets for the diagnosis of irredundant MOS networks synthesized by Lai's algorithm. The generation is most conveniently accomplished during the process of synthesizing the irredundant networks. 2. BASIC DEFINITIONS To facilitate later discussion, some of the basic definitions, symbols, and concepts common to topics in succeeding sections are given at this point. A few closely related basic theorems are also included which are discussed, or related to those discussed, in existing literature, mainly in [Gil 5h] , [IM 71], [NTK 72], and [Lai 76]. Further definitions and basic theorems more pertinent to a topic discussed in a particular section are given in the respec- tive section. A typical MPS (Metal Oxide Semiconductor) cell is shown in Fig. 2.1. It consists of several interconnected field-effect transistors (FET's) of which one is called the load and the rest, often connected in a series and parallel fashion, constitute what is called the driver . The load FET is always conduc- ting and provides a permanent connection between the output terminal and the voltage supply through the load resistance which it represents. The FET net- work constituting the driver section operates exactly like a relay-contact net- work where each FET corresponds to a 'normally open' relay contact: it is con- ductive when its input is a logical '1' (represented by a voltage near the lev- el of the supply voltage), and it is non- conductive when its input is a logical '0' (a voltage near the level of ground). A proper combination of input sig- nals to the driver (e.g., A,D = '!' in Fig. 2.1) creates a conducting path be- tween the output terminal and ground. Because of the relatively high resis- tance represented by the load and the relatively low resistance represented by the driver, this results in a logical '0' at the output terminal (i.e., a volt- age close to ground). When a particular combination of input signals results in no conducting path from output terminal to ground (e.g., D,E = '0* ), the LOAD v. r HI DRIVER VOLTAGE SUPPLY Q B H D HI OUTPUT TERMINAL -O f = (A ^ B)D v CE H HI GROUND Fig. 2.1 A typical MOS cell. output is a logical '1' since it is at a voltage level almost identical to that of the voltage supply. Thus the MOS cell of Fig. 2.1 can be seen to realize the function (A v B)D s/ CE. A two-terminal switching network is a two-terminal graph defined in graph theory (see, for example, [Har 65]) with edges consisting of branch-type ele- ments (in this case, FET's). Discussion in this work is restricted, except where otherwise stated, to two-terminal series-parallel networks to simplify analyses. The transmission function , f , of a two-terminal network N is a Boolean function which is '1' if and only if there is a closed (conductive) path between the terminals of the network. The driver of an MOS cell together with its corresponding output terminal and ground connection constitute a two-terminal network. By the preceding dis- cussion of the operation of an MOS cell, if the transmission function of an MOS cell's driver is f , the function represented by the voltage level of the out- put terminal, referred to as the output function of the cell , is f . Fig. 2.2 shows a typical MOS network (the network shown happens to be a 1-bit adder). In order to facilitate later discussion, three types of connec- tions are distinguished in an MOS network. An intercell connection is a con- nection from an external variable, x., or the output terminal of a cell, g., to the driver of another cell, g., considered as a unit. In other words, re- J gardless of the number of individual FET's g. (or x.) may be connected to in the driver of g., there is considered to be only one intercell connection from J g. (or x.) to g.. There are 10 intercell connections in the network of Fig. 2.2, three to each of cells g and g p , and four to cell g_. A second type of connection is the intracell connection. This refers to connections among the o m ■h © ^ ■ — r- "i ♦ ii T 8 PQ PQ lo £1 o **~-v ■H • .G C £ O •H a ■P ■H •H W *H O CD Ph ^ •o •P (0 •H £> -p •H Xi ^> -P H •H CO CO Xi £ -P H ^ CD O 3 •P. -p CJ u CO CO T3 CO 13 •H CD ,ki CO U jeg o -p 5 -p pj a; o S ^ «H • & to >H H CO H o -P 0) o c -p rt CO -P CO •H o -Q 8 CO 2 -P

2, such that X l X 2 X s each g. is an immediate predecessor of g. , then: g. is called a successor J 2+1 s of g. , g. is called a predecessor of g. , and a path is said to exist from 11 s cell g. to g. . These definitions are extended to allow external variables 1 s as possible predecessors (i.e., substitute external variable x. for cell g. 1 X l in the preceding group of definitions). Let IP(g.), IS(g.), P(g.), and S(g.) denote, respectively, the sets of immediate predecessors, immediate successors, predecessors, and successors of cell g . . A network of MOS cells in which no cell is a successor (or predecessor) of itself is called a loop-free or feed-forward network. In this work, only loop- free networks will be considered. Next, notation, definitions, and basic theorems pertaining to 'negative functions' are developed. The important relation between these 'negative functions' and the MOS cell networks just described will be discussed later. Switching functions of n variables, x , ...,x , will be considered. Let V be the set of all n-dimensional binary (0 or l) vectors. Given two vectors A = (a n ,...,a ) and B = (b_,...,b ) in V : 1 ' n * 1* ' n n A = B denotes the fact that a. = b. for every i = l,...,n; A < B denotes the fact that a. < b. for every i = 1, ...,n, and a. < b. for at least one i. i i If none of the relations A > B, A = B, or A < B holds between A and B, vectors A and B are said to be incomparable . For convenience, let and 1 denote the special vectors (0,...,0) and (l,...,l), respectively. There are many possible ways in which to represent an n- variable switch- ing function. Different representations often have respective unique advan- tages for various purposes. In addition to the familiar Boolean representa- tion (see Fig. 2.3(a)), the well-known truth table representation (see Fig. 2.3(b)) is also often useful. In the theorems and algorithms of later sec- tions, the truth table representation and what can be considered to be a vari- ation of it, the labelled n-dimensional cube, are invaluable. 10 f = X^ sy X 2 X (a) Function f expressed in Boolean representation. x l *2 X 3 f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (b) Function f expressed in truth table representation. 110 10 (c) Function f expressed in labelled n-cube representation. (Labels are the numbers inside boxes. ) Fig. 2.3 Different representations of a function f. 11 An n-dimensional cube (abbreviated to n-cube), denoted C , is defined as follows : (1) Each vector in V is represented as a distinct vertex in C . Hence- n n forth, a vertex in C may be referred to by the vector it represents (e.g., •vertex (101)' ). (2) There is an edge between two vertices A and B if and only if A differs from B in exactly one component (i.e., A and B are of Hamming distance l). (3) An edge between vertices A and B is directed from A to B if and only if A > B and is denoted by AB. A 3-cube, C , is shown in Fig. 2.k. The weight of a vertex A, denoted w(A), is defined as the number of '1' components in vector A. A vector A in V (corresponding to a vertex in C ) can be considered to n n be a combination of values of the n variables x , ...,x where the i-th compo- nent of A represents the value of variable x.. Such a vector A is called an input vector for a function f of x..,...,x . A completely specified function of n variables, x , . . . ,x , is one for which a value is specified for every input vector A e V . An incompletely specified function of n variables, x , ...,x , is one for which no value is specified for at least one input vector A e V . An input vector A for which the value 1 is specified for f is said to be a true vector of f . Similarly, an input vector A for which the value of f is specified to be is called a false vector of f. Input vectors of an incompletely specified function f which are neither true nor false vectors 'i.e., vectors for which f is unspecified) are said to be unspecified vectors of f. 110 10 Fig. 2.1+ A 3-cube, C. 110 10 Fig. 2.5 A labelled 3-cube with respect to f l = X 1 X 2 v X 1 X 3 v x l x 7 and f 2 = ^2 ^ X 1 X V 13 For any given set, Q, of vectors: vector A € Q is a minimum vector of Q if and only if there exists no vector B e Q, such that B < A; A e Q is a maximum vector of Q if and only if there exists no B e Q such that B > A. In particular, if Q is the set of all true vectors of a function f, the max- imum vectors of this set are said to be maximum true vectors of f. Similar- ly, if Q, is the set of all false vectors of f, the minimum vectors of this set are said to be minimum false vectors of f. Let f , ...,f be completely specified functions of n variables. An n-cube C is referred to as a labelled, n- cube with respect to functions f n , n 1' ...,f , denoted C (f , ...,f ), when a binary integer, m . L(A) ■ f(A;f ,...,f ) = £ f (A) 2T 1 , i=l is attached to each vertex A of C as a label. Fig. 2.3(c) shows a labelled 3-cube with respect to the function f = x x v x x , and Fig. 2.5 shows a labelled 3-cube with respect to the functions f, = xx ^ x t x d v x i x q and f 2 = X 2 v V 3 ' Possibly the best-known characterizations of positive and negative func- tions are as given in the following two definitions. Definition 2.1 A (completely specified) Boolean function of n vari- ables, x..,...,x , is said to be a positive function of these variables if and only if it can be represented by a Boolean expression in which only the non- complemented literals x_ ,. . . ,x appear. Definition 2.2 A (completely specified) Boolean function of n vari- ables, x , ...,x , is said to be a negative function of these variables if and only if it can be represented by a Boolean expression in which only Ik the complemented literals x , . . . ,x appear. Using DeMorgan's law, it is easily seen that a negative function is the complement of a positive function of the same variables. Based on a theorem in [Gil 5*+] characterizing positive functions, this similar theorem, appearing as a definition in [IM 71] j can be shown for neg- ative functions as defined in Definition 2.2. Theorem 2.1 A completely specified function, f, of n variables, x. , . . . , x , is a negative function of x , ...,x if and only if for every pair of vec- tors A and B in V such that A > B, f (A) < f(B). Other equivalent characterizations of completely specified negative functions are also useful. The following corollary is obvious. Corollary 2.1 If a completely specified switching function, f, of n variables, x , ...,x , is a negative function of these variables and f(A) = 1 for some A e V , then f (B) =1 for every B e V such that B < A. Simi- larly, if f (A) = for some A e V , then f (B) = for every B € V such that B > A. The following corollary is also obtained from Theorem 2.1. Corollary 2.2 If for a completely specified switching function, f, of n variables, x_,...,x , 7 1' ' n' f (B) = 1 for every B € V for which at least one vector A e V exists J n n such that B < A and f (A) = 1 or f (B) =0 for every B € V for which at least one vector A € V exists n n 15 such that B > A and f (A) = 0, then f is a negative function of x.,.,.,x . The next theorem is from [IM 71] where it was presented in the form of a theorem concerning columns of a truth table. Theorem 2.2 A completely specified function f of n variables, x.. , . . . , x , is a negative function of those variables if and only if for every pair of input vectors, A and B, such that f(A) = 1 and f(B) = 0, there exists a subscript i (1 < i < n) such that a. * 0, b. =1. — — i ' i Proof First consider the 'if part of the theorem. Suppose that f is a completely specified function of x , ...,x and that for every pair of A and B such that f (A) = 1 and f (B) = 0, there exists an i such that a. = 0, b. = 1. Since a. = and b. =1, the relation A i> B must hold between A i I i ' r and B. Next, it will be proved by contradiction that f must then be a neg- ative function of x , ...,x . Assume f is not a negative function of x. ,..., x . Then by Theorem 2.1, for at least one pair of A and B, A > B and f(A) > f(B) (equivalently, f(A) = 1, f(B) = 0). The existence of such a pair con- tradicts the original premise that A ~f> B for every pair A,B such that f(A) = 1 and f(B) = 0; thus the 'if part of the theorem must be true. Next consider the 'only if part of the theorem. Suppose f is a com- pletely specified negative function of x , ...,x . It will be proved by con- tradiction that for every pair of A and B such that f (A) = 1 and f(B) = 0, there exists an i such that a. = 0. b. = 1. Assume for at least one pair l ' i of A and B such that f (A) =1 and f(B) = 0, there does not exist such an i. U &. > b. must hold for i = l,...,n, implying A > B (A and B are assumed 16 to be distinct). By Theorem 2.1, for such a pair A,B, f(A) < f(B), contra- dicting the premise that f(A) = 1 and f (B) =0. Therefore, the 'only if part of the theorem is also true. Q.E.D. This characterization of a completely specified negative function is important in the consideration of truth table representations of negative functions. A combination of a '0' entry and a '1' entry appearing in a column of a truth table for a function f of x n ,...,x is referred to as a 1' n 0-1 pair . A corresponding combination of a '1' entry and a '0' entry in a column for x. (l < i < n) in the same truth table (see Fig. 2.6) is referred to as a 1-0 cover . By Theorem 2.2, a completely specified function f of x , . . . ,x is obviously a negative function of the same variables if and only if every 0-1 pair in a truth table column for f has a 1-0 cover among the col- umns corresponding to x , ...,x . Function f defined by the truth table in Fig. 2.6 can be found to be a negative function of x ,x ,x by verifying that a 1-0 cover exists for each of the 15 different 0-1 pairs in the col- umn for f . Function f given in the truth table shown in Fig. 2.7 is found not to be a negative function of x ,x p ,x since the 0-1 pair corresponding to f(00l) = 0, f (011) = 1 has no associated 1-0 cover. The next definition and following theorem characterize a negative func- tion with respect to its n-cube representation. Definiti on 2.3 A directed edge AB of a labelled n-cube C (f_,...,f ) ° n 1 m is said to be an inverse edge if and only if £(A;f ,, . ..,f ) > i5(B;f -.,- • • > f m )« Figs. 2.8 and 2.9 show C (f ) and C (f p ), respectively, where f- and 17 X 1 X 2 X 3 f l 1 1 1 0*1 o- 1 1/) 1 1 1- 1 1 1 1 1 1 0-1 pair Fig. 2.6 Example of a 0-1 pair and a corresponding 1-0 cover. X 1 X 2 X 3 f £ 1 1 o- 1 1 1 1 1« 1 1 1 1 1 1 1 1 ■0-1 pair having no 1-0 cover (thus f p is not a negative function of x , * 2 ,x 3 ) Fig. 2.7 Example of a 0-1 pair having no 1-0 cover. 18 f are the same two functions of three variables given in the truth tables of Figs. 2.6 and 2.7. In Fig. 2.9, the directed edge (Oil) (001) shown as a bold line is the only inverse edge in the labelled 3- cube with respect to f . The 3-cube labelled with respect to f in Fig. 2.8 has no inverse edges. Fig. 2.5, which shows a 3-cube labelled with respect to two functions, has seven inverse edges (drawn in bold lines). The following theorem appears in [NTK 72] as the definition of a nega- tive function. Theorem 2.3 A completely specified switching function, f , of n vari- ables is a negative function of these variables if and only if there is no inverse edge in C (f), the labelled n-cube with respect to f. Proof First, consider the 'if 1 part of the theorem. Suppose there is no inverse edge in C (f). It will be proved by contradiction that f is then a negative function of x , . . . ,x . Assume it is not. Then by Theorem 2.1 there exists at least one pair of vectors A, and A, in V (correspondingly, vertices A 1 and A^. in C ) such that A > A. and f (A ) > f (A.), f (A_) > f (A^.) implies f(0 = i(A ;f ) = 1 and f (A.) = #(A.;f) = 0. Since A > A., there must exist a sequence of directed edges A A p , A A , ..., A. -A, connecting vertices A and A in C . Since labels with respect to f can only assume values 1 or 0, and since &{k ,f) = 1 and i(A. ;f) = 0, it is obvious that for at least one pair of vertices A. and A. . , 1 < i < k, connected by edge AJL ., £(A. ;f) = 1 and Z(A. ;f) = 0. Thus, edge AJV. - is an inverse edge, contradicting the original premise. Therefore, f must be a negative function of /.,..., x , and the 'if part of the theorem must hold. Next, consider the 'only if part of the theorem. Suppose completely 110 10 19 Fig. 2.8 Labelled 3-cube for function f of Fig. 2.6 which has no inverse edge. 110 10 Fig. 2.9 Labelled 3-cube for function f of Fig. 2.7 which has one inverse edge. 20 specified function f is a negative function of x ,...,x . It will be proved by contradiction that there is then no inverse edge in C (f). Assume there is such an inverse edge, say AB between vertices A and B. Therefore, i(A;f ) > i(B;f ). Since A(A;t) = f (A) and i(Bjf) = f (B), f (a) > f(B). This contra- dicts Theorem 2.1 which states that no such pair A and B can exist for nega- tive function f. Hence, no inverse edge exists in C (f), and the 'only if 1 part of the theorem must be true. Q.E.D. Utilizing Theorem 2.3, it is relatively simple, for small values of n, to check whether or not a completely specified function f is a negative function of n variables by visual inspection of the labelled n-cube C (f ) (tests for larger values of n are better treated by computer). For exam- ple, for n-cubes depicted with vertices of decreasing weights located in increasingly lower physical positions (as in Fig. 2.4), one need only check each edge to see if its 'upper* (i.e., physically higher) vertex has a '1* label while its 'lower' vertex has a '0' label. If such an edge is detect- ed (for example, (Oil) (001) in Fig. 2.9), it is an inverse edge, and the corresponding function f is not a negative function of x , ...,x . Other- wise (for example, see Fig. 2.8), f is a negative function of x , ...,x . Definition 2.4 A directed path from a vertex A n to a vertex A sat- isfying A, > A in an n-cube C consists of a sequence of directed edges, A..A , A A_, . .„, A ,A , connecting the two vertices. 12' ? j q-1 q In Fig. 2.4, (111) (110), (110) (010) and (111)(011), (011) (010) are two directed paths from (ill) to (010). 21 Definition 2.5 In a labelled n-cube, C (f), for a function f of n vari- ibles, the number of inverse edges included in a directed path, p, between :wo vertices A and B, A > B, is called the number of inversions of path p. [he inversion degree of a vertex A with respect to a vertex B in C (f ) is ;he maximum number of inversions over all directed paths from vertex A to rertex B, is defined only for A and B satisfying A > B, and is denoted ) f (A,B). In Fig. 2.10, D f ( (0111), (0001)) = 1, D f (l,(000l)) = 2 (inverse edges ire shown in bold lines ) . Definition 2.6 The inversion degree of a function f is the maximum lumber of inversions over all directed paths from vertex 1 to vertex in J n (f), i.e., D f (l,0). The function f shown in Fig. 2.10 in the form of a labelled U-cube is 3f inversion degree two since D (1,0) = 2. It is apparent that the inver- sion degree of a function of four variables can be no greater than two. It has been shown that the inversion degree of a function is related to the minimum number of MOS cells required to realize it. This will be Us cussed later. Much of the preceding discussion dealt with completely specified neg- ative functions. Next, incompletely specified negative functions will be lefined and characterizations corresponding to those for completely spec- .fied negative functions given. )efinition 2.7 A completion of an incompletely specified function f 22 o (U 0) u bo dj § •H CO ?H > S3 •H O Ch a o •H •P O is repeated here as it contains an algorithm to obtain one negative completion of a given incompletely speci- fied negative function. Theorem 2.U An incompletely specified function, f, of n variables, x_,...,x , is negative with respect to x ,...,x if and only if for each pair of input vectors A and B for which values of f are specified and f (A) = and f(B) = 1, there exists a subscript i (1 < i < n) such that a i = 1 and b =0. 2* Proof The 'only if part of the theorem is easily demonstrated. Sup- pose f is negative with respect to x , . ,.,x , but assume there exists a pair of input vectors, A,B, for which f (A) =0 and f (B) =1 are specified and no i exists such that a. =1 and b. =0. Then no completion of f can be a negative function of x ,...,x by Theorem 2.2, and, consequently, f can not be negative with respect to x..,...,x , contradicting the original premise. Thus, the 'only if part of the theorem must be valid. Next consider the 'if part of the theorem. It is sufficient to show that a negative completion of f always exists given the fact that there exists an i such that a. = 1, b. =0 for each specified pair of values f (A) = 0, f (B) = 1. Consider the completion, f , of f obtained as follows (A,B £ V ): (1) Set f (A) = for every A such that f (A) = 0; (2) Set f (A) = for every A such that f (A) = * and there exists a a B for which A > B and f (B) = 0; (3) Set f (A) = 1 for every A not satisfying rule (l) or (2). It is obvious that f is a completion of f. Now f must be proved to be a negative function of x , ...,x . The proof will be by contradiction: Suppose f is not a negative function of x , ...,x . Then by Theorem 2.3, there must exist at least one inverse edge, say BA, in C (f ). There are the following four possible cases since f (B) = 1 and f (A) = 0: Case 1 f (B) = 1 and f (A) = 0. Tlince BA is an edge directed from B to A, B > A, contradicting the as- sumption that there exists an i such that a. > b.. l l Case 2 f (B) = * and f(A) = 0. 25 By rule (2) above, f ' (B) = 0, f ' (A) = 0, and this contradicts the as- sumption that BA is an inverse edge in C (f')« Case f(B) = 1 and f(A) = *. Since BA is an inverse edge in C (f 1 ), f ' (A) = must hold, f ' (A) = can only be specified by rule (2) above. Hence there must exist a D € V such that D < A and f (D) = 0. Considering vectors D and B, D < A < B, I = 1, and f(D) = 0. However, D < B implies d. ;[ b., i = l,...,n, and this contradicts the assumption that there exists an i such that d. > b.. 11 Case k f(B) = * and f (A) = *. Since BA is an inverse edge in C (f')> f ' (A) = must hold and can only result from rule (2) above. Thus there exists a D e V such that D < A and n f(D) = 0. Since D < A < B, rule (2) also assigns f ■ (B) = 0. This contra- bs the assumption that BA is an inverse edge in C (f ' ). This proves the 'if part of the theorem. Q.E.D. The next two theorems, appearing in [Lai 76], extend the results of Corollary 2.1 and 2.2 to the case of incompletely specified functions. ;e characterizations of incompletely specified negative functions are often useful in determining whether or not a given function — either com- pletely or incompletely specified — is negative. Theorem 2.$ A function f of n variables is negative with respect to le variables if and only if for every vector A e V such that f(A) = 0, either f (B) = or f (B) = * for every vector B € V satisfying B > A. Proof First consider the 'if 1 part of the theorem. Suppose for ev- ery A such that f (A) = 0, f (B) = or * for every B such that B > A. Now r A consider any pair of vectors A,B £ V such that f (A) = and f(B') = 1. Then, by the original premise, B ~f> A must hold. Thus, either B is incomparable to A or B < A. In either case there must exist an i such that a. > b.. By 1 i J Theorem 2.h f must then be a negative function with respect to x , ...,x , and the 'if part of the theorem is true. Now consider the 'only if part of the theorem. Suppose f is negative with respect to x_,. ..,x . The proof will be by contradiction. Assume there exists at least one A € V such that f (A) =0 and at least one B e V n n such that B >A and f(B) = 1. Then for- every completion, f , of f, f ' (A) = and f ' (B) = 1. By Theorem 2.1, no such f ' can be a negative function of x , ...,x . The resulting implication that f is not negative with respect to x-,...,x contradicts the original premise. Hence the 'only if part of the theorem holds. Q.E.D. Theorem 2.6 A function f of n variables is negative with respect to these variables if and only if for every vector A e V such that f (A) = 1, either f (B) = 1 or f (b) = * for every vector B € V satisfying B > A. Proof Proof is similar to that for Theorem 2.5. Corresponding to characterizations previously given for completely specified functions, further characterizations of incompletely specified negative functions can be presented. The following corollary, correspond- ing to Theorem 2.1 for completely specified functions, is obvious from the two preceding theorems. Corollary 2.3 An incompletely specified function, f , of n variables 27 is negative with respect to these variables if and only if f (A) < f (b) holds for every pair of vectors A,B e V , A > B, for which values of f are spec- ified. From the fact that the driver of an MOS cell operates as a two-terminal network of normally-open relay contacts, it is easily seen that the trans- mission function of such a network must be a positive function of its inputs. Furthermore, it is clear that any positive function of n variables, x , ..., x , can (theoretically) be realized by the driver of an MOS cell (obviously, a Boolean expression for f or its completion, in terms of the non-comple- mented variables x ,...,x only, must exist and can be implemented by a two-terminal FET network in a straightforward manner). As pointed out earlier, if the driver of an MOS cell realizes function f, the MOS cell itself realizes f. Hence, by DeMorgan's law, f is a nega- tive function of n variables if and only if f is a positive function of the same variables. Based upon this discussion, the following theorem is obvious, Theorem 2.6 The output function of an MOS cell is always a negative function with respect to the inputs of the cell. A negative function of n variables, x , ...,x , can always be realized by an MOS cell with inputs X^, . . . jX^. While Theorem 2.6 is valid from a theoretical viewpoint, it must be noted that it is actually impractical to construct MOS cells consisting of more than a certain number of MOSFET's. This number, however, is not fixed and depends on such things as the operational mode (i.e., static, dynamic, or complementary) and the required speed. 28 Obviously, any Boolean function f can be expressed as a negative func- tion of x 1 ,...,x k ,x k+1 ,...,x 2k where x^ . = x , j = l,...,k. Thus, any function f can be realized by a single MOS cell if both variables and their complements are available as inputs. This paper will assume complements of variables are not available. The functions available to a network of MOS cells as inputs are n independent variables x n ,...,x which will be referred to as external variables. Let 1' ' n X denote the set of external variables [x n ,...,x }. 1 n Under the restriction that only non- complemented variables are avail- able as inputs, determining the number of cells required to realize a given Boolean function is not a trivial problem. There is, however, an easily derived upper bound on the number of cells necessary to realize a given function. Since the complement, x., of each external variable, x., can be obtained using a single MOS cell as a simple inverter, the complements of all inputs can be realized with n cells. With the resulting availability of all variables and complements of variables, f can be realized with one additional cell — a total of n+1 cells in the network. In general, how- ever, networks of fewer MOS cells can be found. The theoretical model for an MOS cell is the negative gate . A nega- tive gate is assumed to be capable of realizing any negative function of its inputs. Once the desired function has been determined, an MOS cell of a specific structure can be substituted for the negative gate. Correspond- ing to networks of MOS cells are networks of negative gates (also referred to as negative gate networks ). The generalized form of a feed-forward net- work of negative gates is shown in Fig. 2.11: let g. denote the i-th gate 29 1 . u. Fig. 2.11 Generalized form of a feed-forward network of R negative gates. 30 from the left, i = 1,...,R, and let u. (x_,...,x ) denote the completely spec- ified function realized by gate g. with respect to the external variables x , ...,x . Since each gate g. is a negative gate with respect to its inputs, x , ...,x ,g , ...,g. , function u. can be considered an incompletely speci- fied function of these n+i-1 variables: u.(x_,...,x ,u_,...,u. n ). All feed- 1 1' ' n' 1 l-l forward negative gate networks can be obtained from Fig. 2.11 by the dele- tion of some (or no) connections. The form in Fig. 2.11 maintains its gen- erality since variables in functions u. (x , . . . ,x ,u , . . . ,u. ) correspond- ing to deleted connections can be considered to be dummy variables of u. . Terms previously defined for networks of MOS cells are also applicable to networks of negative gates (e.g., immediate predecessor, external vari- ables, etc.)« Further terminology is now defined for both negative gate networks and MOS cell networks. Algorithms given later synthesize MOS cell or negative gate networks to realize either a single function f or a group of functions f >«««>f (the letter m is used exclusively for denoting the number of functions to be realized by a single network). Such an f or f . is said to be an output function of the network (or a network output function ). In a network, each gate (cell) realizing a network output function is called an output gate ( cell ). Networks realizing a single output function are distinguished from those realizing, simultaneously, two or more output functions by referring to the former as single-output networks and to the latter as multiple-out - put networks . Examples of single- and multiple -output negative gate networks appear in Figs. 2.12(a) and 2.12(b), respectively. Fig. 2.2 shows a multiple- output level 3 level 2 31 level 1 (a) Example of a single-output negative gate network of three levels. >-> o-^> (b) Example of a multiple -output negative gate network of three levels. Fig. 2.12 Single- and multiple -output negative gate networks. 32 network of MOS cells (the output functions being f. = S. = A. © B. © C. . and f_ = C. = A.B. ^ A.C. - v B.C. . ). 2 1 11 l l-l l l-l Definition 2.9 The level of a negative gate (MPS cell) , g., in a net- work is defined as the maximum number of negative gates (MOS cells) on any path from g. to any output gate (MOS cell) of the network."*" A negative gate (MOS cell) whose level is I is said to be in level & of the network . A net- work of negative gates (MOS cells) is said to be a network of I levels (or an i-level network ) if and only if the highest level of any gate (MOS cell) in the network is I. By this definition, in the network of Fig. 2.12(b), gates g,_ and g/- are in level 1, gates g_ and g. are in level 2, and gates g 1 and g p are in level 3 of the network; and the network itself is thus a 3-level network. In Fig. 2.2, MOS cells g , g ? , and g are in levels 2, 1, and 1, respective- ly; the network made up of these three cells is therefore a network of only two levels. Definition 2.10 For networks of negative gates and networks of MOS cells, the following types of optimality are defined: A G-minimal network is one having the minimum number of negative gates (MOS cells) among all networks of negative gates (MOS cells) realizing switching function f (or group of functions f , ...,f ). An I-minimal network is one having the min- imum number of intercell (intergate) connections among all networks realizing Although levels are commonly numbered in the reverse order (input gates to output gates), this definition is convenient for later algorithms and computer program implementations which consider a network's gates while generally moving from the output gates to the input gates. 33 switching function f (or f , ...,f ). An F-minimal network of MOS cells is one having the minimum number of FET's (both driver and load FET's included) among all MOS cell networks realizing switching function f (or f _,..., f ). Combinations of the letters G, I, and F can also be used to represent the combination of two or three of the above optimality criteria. For ex- ample, a Gl-minimal network of negative gates for a function f is one hav- ing the minimum number of intergate connections among all those networks having the minimum number of gates among all negative gate networks realiz- ing f. In general: the left-most letter will designate the optimality cri- terion of primary importance; the second letter will designate the criteri- on of secondary importance; and the third letter (if any) will designate the criterion of tertiary importance. 3h 3. PROPERTIES RELATED TO OPTIMAL NETWORKS This section will present a collection of properties related to opti- mal negative gate and MOS cell networks. Some of the properties deal exclu- sively with G-minimal networks, and others, important to the reduction of series -parallel problems with driver FET's in both optimal and non-optimal MOS cell networks, relate indirectly to F-minimal networks. Some of the properties, including the two most important concerning the number of negative gates in two-level-restricted and non- level-restrict- ed G-minimal networks, have appeared elsewhere. The properties in themselves are insufficient to provide a method for synthesizing optimal networks of various types. However, they are useful for: checking designs for optimality; testing for the lack of necessary characteristics of optimal networks in a design or partial design (perhaps, as part of a heuristic or algorithmic synthesis process); and characteriz- ing, at least partially, optimal negative gate and (both optimal and non- optimal) MOS cell networks. The following theorem is demonstrated in [Liu 72]. Theorem 3»1 In a single -out put, G-minimal, negative gate (MOS cell) network, each gate (cell) other than the output gate (cell) must have at least one input from the set of external variables. The next group of new theorems and corollaries relate certain sets of inputs to the numbers of negative gates (MOS cells) appearing in the sec- ond or third levels of a G-minimal network. 35 Theorem 3.2 In a single-output, G-minimal, negative gate (MOS cell) network, the number of gates (cells) in the second level of the network is at most Tlog p (t +1)1 +1 where t is the number of external variable inputs to the output gate (cell). • Proof This theorem can be proved by demonstrating that a contradiction occurs if it is assumed to be false. Assume there exists a single -out put, G-minimal, negative gate network (the use of MOS cells does not affect the proof) for which: the output gate, g , has t external variable inputs, x. , R x ± ...,x. ; the second level consists of s gates, g. ,...,g. ; and s > Tlog p H J l J s (t + 1)1 + 1. (Such a network is illustrated in Fig. 3.1(a).) If there exist additional inputs to g from gates in level three or R higher, duplicate all such gates and use the new duplicates, g , ...,g , 1 q of the gates as inputs to g in place of the respective originals. This R results in a second level of s + q gates (see Fig. 3.1(b)). Next add two inverters to the network in series with the output of g . Since an inverter R is a special case of a negative gate, this adds two more negative gates, g and g , realizing f and f, respectively, to the network (see Fig. 3.1(c)). Now, since it is apparent (refer to Fig. 3.1(c)) that f realized by g is a positive function of IP(g. ) U ... U IP(g. ) U IP(g k ) U ... U IP(g k ) U J l J s 1 q .x ,...,x. }, f realized by g must be a negative function of these same X l x t A variables. Create a new negative gate, g', to realize this negative func- tion and provide one new negative gate to obtain the necessary complement of each of x. ,...,x. (see Fig. 3.1(d)). Actually, it is not necessary h. t to use t negative gates to obtain x. ,...,x. from x. ,...,x. . Due to x l \ X l X t Tpl for a real number p denotes the smallest integer not smaller than p. X, n IP(g< ) subnetwork T consisting of gates in third or higher levels IP(g, ) J s level 2 36 level 1 (a) Network realizing f. Network is assumed to be optimal with s > flog^it + 1)1 4- 1. (b) Network after duplication of every negative gate in level three or higher which was an input of g^. Fig. 3.1 Illustration of the proof for Theorem 3.1. 37 f - (c) Network after adding two negative gates, each acting as a simple inverter, following the output gate. IP(g, ) U J l ... U IP(g. ) U IP(g v ) U ... U IP(g, ) subnetwork T » (d) Network after replacement of gates g. ,...,g. ,g, ,...,g, ,g„, and J l J s k l k 1 R g by a new gate g' and gates realizing the complements of x. , ...,x. Fig. 3.1 (Continued) «H si PQ bO 1^ si bO • • • T3 o C •H w 03 C -P o ,Q •H O -P CJ CD c ^H p CO «H w -P a> -p •H > g X •H & •\ -P C • •H •H • W • O 03 •\ ft w H CD •H w J3 X cO -P i w C T3 ^J bO bD ft ft H H a 1 ^bO ft" bO ft •»_<» , w ^ (!) o H + ■P CO bO ^4 14 o -P CD > P 1 OJ bO •H -P cd bO CD 0) o H •H •H 43 <+H O H W 03 -P C c O CD •H B -p CD •H H T3 ft T3 S 03 O o 1 CD h" ,3 -P + bO •p C v — «* •H OJ tq bO •H O H H ^^ 03 i >a CD Q) fc T3 3 c d w 03 •H CD -p -P •\ c 03 I'M bD u CD &P ^^ !> •H •H N -P •ri H 03 H • bO 03 m CD a U bO -p O •H CO h CD H £1 o3 -P *\ T3 = < C bO 03 CD - CD -H H fH -P 03 CO C 0) bO •H f-i CD ft cO C 39 results obtained independently by Markov and Muller, it is known that the complements of p variables can be obtained using at most riogp(p + 1)1 inverters, i.e., at most l"log 2 (p + 1)1 negative gates plus additional gates realizing positive functions. Their proofs are abstract, but simpler constructive proofs are present- ed in [Ake 68] and [Mur Jl], Ey these constructions, x. ,...,x. can be x l x t obtained as positive functions of x. ,...,x. and the outputs of l"log p (t + 1)1 X l X t negative gates (with inputs only from x. ,...,x. , and each other). Fur- x l X t thermore, a network so obtained is always loop-free. (Fig. 3.2(a) shows an example from [Ake 68], [Mur 71] in which x , ...,x are obtained from x. , . . . ,y^ using only three inverters. The gate used are threshold gates with only positive input weights. Since such threshold gates obviously realize positive functions, the corresponding network of three negative gates and seven positive gates shown in Fig. 3.2(b) can be obtained.) Thus f, cur- rently realized by g', is a negative function of these Tlog„(t + 1)1 neg- ative gates, external variables x. ,...,x. , and IP(g. ) U ... U IP(g. ) U X l \ J l J s IP(gv ) U ... U IP(g v )• The result is a network realizing function f (see ^1 \ Fig. 3.1(e)) in which the s + 1 gates constituting levels one and two of the original network have been replaced by [log p (t +1)1 +2 gates (the manber of gates in the remainder of the network has not been changed). Since the original network was supposed to be G-minimal, the final network aust have at least as many gates. Thus, [log (t + l)l + 2 > s + 1 (i.e., r log_(t +1)1 + 1 > s) must hold. However, this contradicts the assumption that s > [log (t +1)1 +1. Therefore, the theorem must be true. Q.E.D. 1+0 fa) Threshold gate network obtaining x ,...,x from x ,...,x„ with only [Ake 68], [Mar TU ' three inverters. x X 1 — • 7 (b) Equivalent network of negative and positive gates obtaining x 1 ,...,x from X;L ,...,x 7 with only three negative gates. Fig. 3.2 Feedforward networks inverting t (= 7) variables with only riog 2 (t +1)1 inverters. Ul Observing that the proof of Theorem 3.2 can be duplicated with respect to gates other than an output gate, the theorem can be restated in a form applicable to all gates of a G-minimal negative gate network: T-.-c :•■:::. -. . For every gate (cell) g. in a single- output, G-minimal, negative gate (MOS cell) network: the number of gates (cells) having only- one output connection apiece which are inputs of g. (g. may have inputs from other gates (cells) as well) is at most !~logp(t +1)1 +1, where t is the number of external variable inputs to g.. These results can be extended to apply to a group of gates rather than just a single gate, and the restriction on the number of gates with single output connections which can be inputs to the same gate can also be tight- ened in certain circumstances. orollary 3»1 In a single -out put, G-minimal, negative gate (MOS cell) network having an output gate (cell) with no external variable inputs, no more than one gate exists in the second level of the network. For a negative gate (MOS cell) with up to ten external variable inputs in a single- output, G-minimal network, Table 3*1 shows values correspond- ing to the limits given by Theorem 3«3« Theorem 3.^4- In a single- output, G-minimal, negative gate (MOS cell) network, if the number of gates (cells) in the second level equals Tlog 2 (t + 1)1 + 1, where t is the number of external variable inputs to the out- put gate (cell), then there exists a G-minimal negative gate (MOS cell) k2 Number of external ■variable inputs to a gate g.. : (t =) Maximum number of gates with single output connections which are inputs of g i : (riog 2 (t +1)1+1 =) 1 1 2 2 3 3 3 k k 5 k 6 k 7 k 8 5 9 5 10 5 Table 3»1 Relations among inputs to a gate g. in a single-i G- minimal, negative gate network. Maximum number of Number of external second and third variables in set level gates in the IP(lP(g )): network: (r =) (riog 2 (r +1)1 =) 1 1 2 2 3 2 h 3 5 3 6 3 7 3 8 1+ 9 h 10 k Table 3»2 Relations between the number of second and third level gates and the number of external variables in IP(lP(g )) for a single- output, G-minimal, negative gate network. k3 network, realizing the same output function, in which the output gate (cell) performs the function of a simple inverter. Proof If the output gate of the given network does not already perform the inversion function, consider the procedure given in the proof of Theorem 3.2. Let w be the number of gates in subnetwork T (see Fig. 3.1(a)) of the network in this procedure. Then this procedure produces from a G-minimal net- work of w + s + 1 gates, a network of w + l"log p (t +1)1 + 2 gates having a simple inverter as its output gate. If the number of gates in the second level of the original network equals Tlog ? (t + 1)1 + 1 (i.e., s = Clog ? (t + 1)1 + l), then both the original and final networks have the same number of gates. Therefore, the network produced by the procedure is also G-minimal. Q.E.D. When the conditions of this theorem are met, it may be useful in designing several MOS cell (negative gate) networks which are to be interconnected. An output cell configuration which is a simple inverter means the complement, f, of the realized function f requires one less cell. If f is not really needed in explicit form (e.g., if it was just chosen as an intermediate function during the partitioning of a large section of logic), f can sometimes serve just as well as an input to subsequent networks. (As an example, see the 1- bit adder in Fig. 2.2 in which the carry is not realized explicitly, but implicitly as the complement of the carry. ) Theorem 3«5 In a single -output, G-minimal negative gate (MOS cell) net- work, the number of gates (cells) in the second and third levels of the network is less than or equal to Tlog p (r + 1)1 where r is the number of external variables in the set IP(lP(g_,)) and g„ is the output gate (cell) of the network. kh Proof The proof will be by demonstration of the fact that every network of R negative gates can be transformed into a network of R - (p + q) + Tlogp (r + l)l negative gates where p, q, and r are, respectively, the number of gates in the second level, the number of gates in the third level, and the number of external variables in the set IP(lP(g )) of the original network. Thus, if the condition stated in the theorem is not met by a particular net- work, a network of fewer gates realizing the same function can be derived - implying that the original network is not G-minimal. In a given single-output network of R negative gates, let g^ denote the output gate, let x, , ...,x, denote the external variable inputs to g , let 1 v g. ,...,g. denote the gates in the second level, and let g. ,...,g. denote X l X p d l J q the gates in the third level. Also, let the remainder of the network, consist- ing of R - (p + q + l) gates, be designated 'subnetwork T. ' (See Fig. 3.3(a).) It is possible that g^ of the given network has inputs other than external variables and second level gates. Let g be a gate which is such an input to g . For each such g: make a duplicate negative gate g n having the same inputs and realizing the same function as g, disconnect g from g , and connect g Q to g_,. Each such g. becomes a second level gate of the network. Let the new t\ u second level gates be denoted g. ,...,g. , and let the set of external X p+1 x p+s variables which are inputs of the second level gates, g. ,...,g. , be X l X p+s denoted x, ,...,x, . (See the network in Fig. 3«3(b).) Obviously, the network 1 r still realizes the function f. And IP(lP(g r ,)) in the original network (Fig. 3. 3 (a)) is now equivalent to IP(g. ) U ... U IP(g. ). Hence the external X l ' X p-fs variables in the set IP(lP(g )) are x ,...,x, . 1 r It is now possible that the second level gates, g. ,...,g. , have inputs x l X p-H3 ^5 subnetwork T of R - (q+p+1) gates inputs to gates ►in first and second levels inputs from gates in third or higher levels :>*- (a) Original network, r % subnetwork T of • • • ^\ i ^ 1 R - (q+p+l) gates • • • \ • • • *"\ 1 J 1 • • • • • * . • | • 1 • 1 L D^ (b) Network after adding new gates to second level. Fig. 3.3 Illustration of the proof for Theorem 3-5- MS x 1 . n subnetwork T of R - (q+p+1) gates g. \& 'Vio- 'q+t *h. \ r L. (c) Network after adding new gates to third level. Fig. 3»3 (Continued) hi l • • • bO I i •<~3 T -. T H ? bo ! o -p w CD I -P 03 U 0) 3 -p T3 (D t O O bO •H En i +3 CD - W C O I -P w Eh CG bO TJ 1+8 X \ • subnetwork T of R - (q+p+1) gates • • J q+t • • \—\ D (e) Network after first simplification. x, x IP(g !>' " 3 .. U IP(g, ) J q+t subnetwork T of R - (q+p+1) gates ^^ (f) Network after second simplification. Fig. 3,3 (Continued) ^ 1 ,-Y • • • i • • • ^ j 3 ^> w -P ,— MM H bO *£. ^ .H •p g 3 -p 3 ^ <-v °> 3 o5 fn H C /~J bO : g J '— CD a -p + (l) O 1 C ^ ■§ P i W • • • « «H i i o H u ** ^ • • • a o •H O •H ch •H H ft w M •H B and f is completely specified, B must be a true vector for f in order to be consistent with the assumption that A is a minimum false vector for f. For true input vector B there can exist no conducting path through the driver of the MOS cell. If conducting path p for A consisted only of FET's with a proper subset of x. ,...,x. , X l X i-1 x. ,...,x. as inputs, then p would also be a conducting path for B, since X i+1 X k every x. , 1 < J < k, j f= £, is 1 for both A and B. Thus, at least one FET J with x. as its input must exist on path p. Similarly, this is true for H f every x. , I = l,...,k. Hence, there must be a series of at least k (= ^ FMAX ) Ju FET's in the driver of the MOS cell realizing f. Q.E.D. Theorem 3«H For a completely specified negative function f of n variables, x..,...,x , there exists an MOS cell with inputs x.,...,x realizing f f f whose driver has at most w^,,.,, FET's connected in series, where w_... v is FMAX FMAX the maximum among the weights of minimum false vectors of f. 56 Proof It is simple to design an MOS cell to realize f with no more f than \r„ y ,^ r FET's being connected in series in its driver. The transmission FMAX function, f, realized by the driver of the cell can be expressed as the dis- junction of products - one for each false vector of f - of noncomplemented literals corresponding to the l's in the respective false vectors. This can be reduced to a disjunction of products corresponding to only the minimum false vectors of f as all other products are implied by these. A driver realizing f can be constructed directly from this expression. Corresponding to each product of t literals in the expression, a series con- nection of t FET's is made - one FET for each respective literal in the product. Making a parallel connection of these serially connected "strings" of FET's results in a structure obviously realizing the transmission function f. Since the number of FET's in each serially connected string is, by construction, the number of noncomplemented literals in the expression of the corresponding vector and is therefore identical to the weight of the vector, the maximum number of FET's in series in the resultant MOS cell is the same f as the maximum weight, w , among all false vectors. r MAX. Q.E.D. f Theorem 3*12 If w rT „,- rT , T is the minimum among the weights of maximum true 1 1MJJM vectors for a completely specified negative function f of n variables, x , . . . ,x , realized by an MOS cell with inputs x_,,...,x , then the driver of r\ 7 1 n f the cell must have at least n - w ,. FET's connected in parallel (i.e., must TMIN r v ' have a cut set of at least n - \r m ,^ r FET's). TMIN Iheorem 3.13 For a completely specified negative function f of n variables, x ,...,x , there exists an MOS cell with inputs x , ...,x realizing 57 f f f whose driver has at most n - w m ._ T _. T FET's connected in parallel, where wl. „„ TMIN c ' TMIN is the minimum among the weights of maximum true vectors of f. Theorems 3*12 and 3-13 can be proved in a manner similar to the proofs of Theorems 3«10 and 3«H> respectively. Although these four theorems assure the existence of an MOS cell f realization for a given negative function f with the minimum w (driver) r MAX f FET's in series and one with the minimum n - w mi , TTVT FET's in parallel, there TMIN * ' may not exist a single realization which possesses both of these characteristics, Example 3»1 Consider the function f defined by the labelled 4-cube in Fig. J>.h. Since there are no inverse edges in the 4-cube, f is a negative function of x , ...,x, . For f the minimum false vectors are: (1100), (1001), and (0101). f The maximum weight, w ™, AV , among these three vectors is two. Following the r MAX construction suggested in the proof of Theorem 3- 11, f can be expressed in the form: f = Xl x 2 s/ x^ v x 2 x^ which corresponds to the MOS cell implementation shown in Fig. 3.5(a)- This f is one of the possible realizations with only w_ MA „ = 2 FET's in series. Now, from the maximum true vectors for f, (1010), (0110), and (0011), f w m .—. is found to be two. Thus, by Theorem 3.13 and MOS cell realizing f can xMJ_N be constructed which has only two FET's in parallel. Based on the three maximum true vectors, the following expression for negative function f can be obtained: 58 H on B) and B ^ C (B jt C) for every minimum (maximum) vector C of Q satisfying w(C) < w(A) (w(C) > w(A)). 61 Proof First consider the theorem statement concerning the number of f ' £ FET's in series. It is sufficient to show that w„„ BTr > -w„ Tn ,. v for every FMAX - FUMAX J negative completion f of f since, by Theorem 3.10, the driver of every MOS f i cell realizing f with inputs x n ,...,x must have at least w„„.„ FET's connect- 1 n FMAX ed in series. f Let A be one of the vectors of weight w- rn ,. v which satisfies conditions FUMAX (i) and (ii) of the theorem. Let B be a false vector of f such that A < B and no vector D exists such that: D is a minimum vector of set Q,, w(D) < w(a), and D < B. At least one such B must exist since A is assumed to satisfy condition (ii). Now consider the following two cases: Case 1 B is a minimum false vector of f. Since B > A, then w(B) > w(A). Hence: W FMAX ^ W(B) ^ W(A) = W FUMAX' Case B is not a minimum false vector of f. Then there must exist at least one minimum false vector, C, of f ' such that C < B. If w(C) > w(A) then: W FMAX^ W(C) ^ W(A) = W FUMAX> and the theorem statement is valid. Now, suppose w(c) < w(A). Since C < B and, as a false vector of negative completion f of f, C can not be less than any true vector of f , then C € Q. Therefore, there must exist a minimum vector, E, of set q such that E < C. This implies w(E) < w(C) < w(A) and E < C < B which contradicts the assumption that A satisfies condition (ii) of the theorem. Hence, no minijnum false vector, C, of f ' can exist such that C < B and w(c) < w(A). 62 Since the theorem has been shown to hold in each of these two cases which exhaust all possibilities, the theorem statement concerning the number of FET's in series must be valid. A similar proof, based on Theorem 3*12, can be made for the part of the theorem statement concerning the number of FET's in parallel. Q.E.D. In determining a configuration of an MOS cell realizing an incompletely- specified negative function of its inputs, there is freedom both in selecting the negative completion of the function and in choosing the specific con- figuration realizing the negative completion. Only the latter freedom occurs in the case of completely specified negative functions. The following theorem proves the existence of negative completions of a function which permit the achievement of the lower bounds on the number of driver FET's in series or parallel given by Theorem 3«1^» Theorem 3«15 For an incompletely specified negative function f of n variables, x , ...,x , there exists an MOS cell with inputs x , ...,x which f / f realizes f whose driver has at most w„ T „,.^ (n - w mTniT1I ) FET's connected in FUMAX v TUMIN f f series (parallel) where -w^-..^. (w mT „._ T ) is the maximum (minimum) among the FUMAX v TUMIN weights of vectors A satisfying both of the following conditions: (i) A is a minimum (maximum) vector of the set, Q, consisting of all false (true) vectors of f and every unspecified vector which is less (greater) than at least one false (true) vector of f and not less (greater) than any true (false) vector of f. (ii) There exists at least one false (true) vector B such that: A < B 63 (A > B) and B ~f> C (B ^ C) for every minimum (maximum) vector C of Q satisfying w(c) < w(A) (w(C) > w(A)). Proof Consider the part of the theorem statement concerning driver FET's in series. The theorem statement concerning FET's in parallel can be demonstrated in a similar manner. Let T be the set of all vectors A satisfying both conditions (i) and (ii) of the theorem. For every vector B such that B is greater than or equal to at least one vector A, A e T, select B as a false vector of completion f ' of f . All other unspecified vectors of f are selected as true vectors of f . First, f will be shown to be an actual completion of f. Consider a false vector, C, of f„ Since C e Q, there must exist a vector A n satisfying condition (i) such that A < C. If there does not exist another vector Ap, A„ f= A, , such that A p e T and A p < C, then, by condition (ii), A, must also be an element of T. In either case, there exists a vector A e T such that A < C. Thus, by the method of selecting false vectors of f, C is also a false vector of f ' . Now consider a true vector, C, of f. In order to prove C is also a true vector of f ' , assume it is not. Then vector C must be greater than or equal to some vector DeT(bythe method of selection of false vectors of f ' ). This is not possible since D can only be a false vector of f (contradicting the assumption that f is a negative function) or an unspecified vector of f (contradicting the assumption that no such vector in Q, is less than a true vector of f). Since every true vector of f has been shown to be a true vector of f ' and every false vector of f has been shown to be a false vector of f, completely 6k specified function f is thus a completion of f. To prove that f is, in addition, a negative completion of f, assume it is not. Then there exists at least one pair cf vectors, C and D, such that C is a true vector of f, D is a false vector of f ' , and C > D. However, since D is a false vector of f, D > A for some vector A € T. Hence, C > A, and C must also be a false vector of f ' (contradicting the assumption that it is a true vector of f ' ). By condition (i), it is obvious that no two vectors in set T are compar- able. Since the set of false vectors for f ' consists of all vectors in set T plus all vectors greater than at least one vector in T, set T must be the set of minimum false vectors of f. Since the largest weight of any vector in set T is ^ Ywm _ by definition, ^ FUMK = ^ Fmy - • Thus, by Theorem 3. 11, f there exists an MOS cell with at most w__,_ T FET's connected in series. FUMBJ Q.E.D. 65 h. OPTIMAL NETWORK SYNTHESIS BASED ON A NEW CONCEPT OF CLUSTERS New algorithms for the synthesis of both 2-level and multiple -level, G- minimal MOS networks will be presented in this section. These new algorithms are of two types. The first results from an observation of the relationship between Liu's synthesis algorithms (for both 2-level and multiple-level MOS networks) based on 'clusters' and 'stratified structures' and the n- cube labelling method of Nakamura et al. which is a part of the synthesis algorithms proposed in [NTK 72]. This relationship suggests a new type of 'stratified structure' based upon which new algorithms paralleling each of those of [Liu 72] can be easily derived. Synthesis results of generally the same quality as those of the algorithms of [Liu 72] can be expected. The second type employs a new concept of 'clusters' (of true and false vectors). In the case of 2-level synthesis, the resulting algorithms are re- ferred to as algorithms based on non-stratified structures. The new algorith- ms for the multiple -level case are classified as synthesis algorithms based on stratified structures and extended floor (or ceiling) functions. These algo- rithms (for both 2-level and multiple -level cases) involve somewhat more computation than the corresponding algorithms of Liu, but significantly im- proved synthesis results can often be obtained while maintaining the simple derivation of MOS cell configurations which is characteristic of algorithms in [Liu 72]. After a review of existing MOS and negative gate network synthesis methods, this section's discussion will be divided into two parts. Section 4.1 will be concerned with the synthesis of G-minimal 2-level networks of MOS cells (negative gates), and Section k.2 will deal with the synthesis of G-minimal 66 multiple -level networks. In these two subsections, certain network synthesis algorithms and related algorithms of [Liu 72] and [NTK 72] will first be cover- ed in some detail in order to provide the necessary background for the presen- tation of the new algorithms later in the subsections (some of this background will also be vital to the discussion of another topic in Section r j). Before beginning the presentation of the new synthesis algorithms, let us review existing algorithms which have appeared in the literature. This will provide the reader with some basis for assessing the relative advantages and disadvantages of the new synthesis algorithms. In [IM 69] which is the first paper on the synthesis of MOS networks, Ibaraki and Muroga, recognizing the promise of negative gate network design as an approach to the design of networks of MOS cells, proposed and solved the problem of synthesizing a 2-level, G-minimal, negative gate network. The algorithm which they presented in [IM 71] (improved over that given in [IM 69]) is based on a truth table and a simple graph generated from it. Compared to later algorithms, this one might be somewhat more difficult to apply by hand, but there should be no difficulties encountered in carrying out the calculations by computer. An important feature of the algorithm is that it permits incompletely specified functions to be selected as desired outputs of the G-minimal networks to be synthesized. [IM 71] also gives a simple extension of the algorithm which allows G-minimal, multiple -output networks to be synthesized — although only under the restriction that any output function realized by a second level gate must be completely specified (output functions realized by first level gates may be either completely or incompletely specified). An extension of the algorithm to include these restricted cases might involve the solution of a type of covering problem. 67 Being mainly concerned with minimizing the number of negative gates in a 2-level network, [IM 71] does not discuss how to obtain from the truth tables the internal structures of the corresponding MOS cells implementing the negative gate networks. Ibaraki extended the algorithm in [IM 71] to obtain 2-level, MOS cell networks minimizing any given monotone nondecreasing cost function of the number of gates and number of connections. Thus, the algorithm has great generality, and it can yield, among others, G-minimal, Gl-minimal, I-minimal, and IG-minimal 2-level networks. As in [IM 71], incompletely specified functions may be chosen as output functions of the networks to be synthesized. The algorithm can synthesize optimal 2-level, multiple -output networks under the restriction that all out- put functions must be realized by gates of the first level. Not surprisingly for an algorithm of this magnitude of generality, it requires the solution of two minimum covering problems to obtain an optimal network of MOS cells, and certain parts of the algorithm involve calculations which may grow quickly in size as the numbers of external variables or out- put functions are increased. The algorithm in [Iba 71] also gives some consideration to reducing the number of FET's in the drivers of the MOS cells of the networks. A method for finding an 'SCMS' (simplest complemented minimum sum: one with the mini- mum number of literals among those with the minimum number of product terms) or an 'SCMP' (simplest complemented minimum product) expression for a cell's output in terms of its inputs is given which involves a minimum covering problem. These expressions may of course be further factored, in general, to produce expressions of fewer literals (this corresponds to fewer FET's used in the implemented cell). 68 Later, Nakamura, Tokura, and Kasami and Liu 1 U independently developed algorithms for synthesizing both 2-level and multiple- level, G-minimal, negative gate networks. In [NTK 72], the authors first showed the similarity of the problem of synthesizing multiple -level, G-minimal, negative gate networks to the problem of minimizing the number of NOT elements (inverters) in a network — a problem solved independently by Markov ' and Muller (see [Ake 68] or [Mur 71], pp. kl6-klS>, for simplified discussions of their results). Then, an algorithm, based on 'n-cube labelling' (to be discussed more later), is obtained for the synthesis of multiple -level, single -output, G-minimal, negative gate networks. This is extended to the multiple -output case. While the results of the extended algorithm can not be guaranteed to be truly G- minimal, they are G-minimal under the restriction that output function f . is realized by a specific gate (of the generalized form of a feed-forward net- work) g , i = 1, ...,m, chosen prior to the synthesis operation. For both 1 of these algorithms, provisions are made which permit incompletely specified functions to be selected as network output functions. Following these algorithms, [NTK 72] develops an algorithm for synthesizing k-level-restricted, single -output, G-minimal, negative gate networks, though this is actually more complex than the non-level-restricted case. The 2-level synthesis problem can thus be solved as a special case (k = 2) of those falling within the capability of this general algorithm. The statement of this algorithm in [NTK 72] inadvertently omits one condition necessary for guaranteeing an optimal result. The necessary condition, however, should soon become evident to a user of the algorithm. 69 In [Liu 72] Liu presents algorithms for the synthesis of 2-level and multiple -level, single -out put, G-minimal networks for completely specified functions. [Liu 75] essentially repeats the results in [Liu 72] concerning the two-level case. A very significant feature of Liu's synthesis algorithms is the ease with which Boolean expressions are derived which directly represent the internal structures of the MOS cells of the implemented network. Previous- ly mentioned synthesis methods (those in [IM 71], [Iba 71], and [NTK 72]) basically operate in two phases: first, the output functions to be realized by every cell of the network are obtained and represented in truth table forms (either standard truth tables or n-cubes); next, from these representations, negative completions are chosen for each of the functions, and then the actual cell configurations are determined. The algorithms proposed in [Liu 72] and [Liu 75] first create a special structure, called the 'stratified structure', which is really a unique partitioning of the true and false vectors for a given function into 'clusters'. From these 'clusters', negative expressions (and thus, MOS cell configurations can be directly obtained, in the 2-level case for each of the cells in the network. In the multiple -level case, also based on 'clusters' of the 'stratified structure', slightly more work (but still a very small amount relative to comparable steps of the other algorithms) is required to obtain the negative expressions for the cells. Since the creation of the stratified structure is of approximately the same difficulty or simpler than the first phases of each of the preceding synthesis methods, Liu's method can generally obtain a final result with significantly less effort. [Liu 72] also presents a few ideas for reducing the numbers of FET's in [Liu 75] mentions a simple extension to the case of incompletely specified functions. 70 networks synthesized by Liu's multiple- level algorithm and a method for making the complexities of cells in a G-minimal network more nearly uniform. [Lai 76] first gives an algorithm to obtain G-minimal, single -output, multiple-level, irredundant MOS networks for completely specified functions. Irredundant MOS networks are those from which no FET or group of FET's can be removed without causing at least one network output to be in error. Lai's algorithm is later extended to the case of single-output networks for incom- pletely specified functions. Then, further extensions of the algorithm are discussed which, for given sets of completely specified functions, obtain irredundant, multiple -output networks which are G-minimal under either of the following conditions: (i) the correspondence between output functions and the gates of the generalized form of a feed-forward network is fixed in ad- vance of the synthesis; (ii) all output cells are assumed to be in the first level of the network (i.e., have no intercell connections to other cells). It is mentioned in [Lai 76] that these synthesis methods for multiple -output networks can also be modified to deal with incompletely specified output functions in a manner similar to that given (in [Lai 76]) in the case of single- output networks. While the synthesis algorithm of [Lai 76] involves a greater amount of calculation than either of the corresponding algorithms of [Liu 72] or [NTK 72] (Lai's algorithm employs calculations similar to those used in the algorithm of [NTK 72] as well as additional calculations), it is invaluable whenever a G-minimal, irredundant network (which is also diagnosable, as will be discussed in Section 7) is desired. In the beginning of Section U.l.l a new concept of clusters will be pro- posed which can often lead (as will be seen) to improved results (in terms of 71 cells with simplified internal configurations) with a relatively small increase in algorithm complexity over those of [Liu 72]. k.l Synthesis of G-Minimal, 2-Level Networks What is referred to as the synthesis of a 2-level network for a function f (or group of functions, f _,..., f ) is actually the synthesis of a network restricted to at most two levels which realizes function f (functions f , ..., f ). Thus, the result of an algorithm for the synthesis of G-minimal, 2-level networks can be a network of 2, 1, or levels (e.g., a G-minimal network of zero levels would occur for a function such as f = x ). The importance of designing a 2-level network for a given function or set of functions is mainly to minimize the propagation delay between receiving the input signals and producing the output signals. While a 2-level negative gate network theoretically accomplishes this by minimizing the maximum number of gates between any input and output, in practice, the generally large size and complexity of an output cell in an implemented 2-level, MOS cell network may be such that its switching time is considerably longer than that for any of the MOS cells which may be employed in a multiple- level network realizing the same function(s). 4.1.1 Synthesis methods for 2-level networks based on stratified structures This section presents what will be classified as 'synthesis algorithms based on stratified structures.' This includes Liu's algorithm for the synthe- sis of 2-level networks and similar, but new, algorithms which are closely related to the n-cube labelling proposed by Nakamura et al. In addition to pointing out the relationships between the algorithms of Liu and Nakamura et al. , this discussion will establish a basis for the presentation in Section 72 4.1.2 of improved 2-level synthesis algorithms based on a new concept of clusters and corresponding 'non-stratified structures'. The following definitions and properties are important for the discus- sion of synthesis algorithms based on stratified structures. These same properties will also be seen later to be useful in describing synthesis algo- rithms based on non-stratified structures. Def in it ion k . 1 .. 1 . 1 The a- term and ft-term of an input vector are, respect- ively, the product of complemented literals corresponding to the O's in the input vector, and the product of uncomplemented literals corresponding to the l's in the input vector. As special cases, the a-term of 1 and the p-term of are defined to be 1. The product, a • p, is called the minterm of the in- put vector. The concept of 'clusters' appears in [Liu 72], but , in preparation for the later presentation of improved synthesis algorithms, it is necessary to generalize this concept as follows: Definition 4.1.1.2 A true cluster ( false cluster ), with respect to a function f, is a set of true (false) vectors of function f such that for every pair of vectors, A. and A., of the set which satisfies A^ > A , every vector A, satisfying A. > A. > A. x Is. J is also a member of the set. Both true clusters and false clusters may be referred to, simply, as clusters . Some of the notation as well as some of the definitions and properties given here are borrowed or modified from that in [Liu 72]. There are some important differences, however, which must be noted to avoid possible confusion. 73 It is important to note that the term 'cluster' as defined above is more general than the same term defined in [Liu 72] (and [Liu 75]). In [Liu 72], a (true or false) 'cluster' is defined only in the context of a 'stratified structure.' A stratified structure, which will be defined shortly, is actually a unique partitioning of the specified vectors of a given function into several sets of true or false vectors. (For example, the partitioning of input vectors in Fig. 4. 1.1. 1(a) is an actual stratified structure for the function f represented by the 3-cube). Each of these sets is then defined in [Liu 72] to be a (true or false) 'cluster', Hence, 'clusters' defined in this (Liu's) manner are only meaningful with respect to the stratified structure of the function under discussion. (True or false) clusters in Definition 4.1.1.2, however, are defined only with respect to a given function and not with respect to any particular group- ing or partitioning of input vectors. While it is true (and will be seen) that a 'cluster' of [Liu 72] is a cluster under Definition 4.1.1.2, the converse is not true . Hence, each set of encircled input vectors in the stratified structure illustrated by Fig. 4.1.1.1(a) satisfies the definitions of a cluster in both [Liu 72] and Definition 4.1.1.2, while sets of input vectors such as {(1111)}, [(1111), (1110), (0111), (0110)}, [(0111), (0101)}, [(1001), (0010)}, [(1011), (1001), (0011), (0100)}, etc. (see Fig. 4.1.1.1(b)) are clusters only in the sense of Definition 4.1.1.2. Henceforth, unless otherwise stated, the use of the term 'cluster' will indicate a cluster according to Definition 4.1.1.2 (even during discussions of stratified structures). An example of a set of true vectors which is not a true cluster (refer to Fig. 4.1.1.1(b)) is: [Lai 75] contains yet other definitions of clusters, lh 1110 L000 'clusters ' of [Liu 72] 'clusters' of [Liu 72] 0111 1 .0101 1 0011 (a) Stratified structure for a function f. The encircled sets of input vectors constitute 'clusters' as defined in [Liu 72]. true clusters set of true vectors which is not a true cluster false clusters (b) Examples of sets of input vectors which are clusters in the sense of Definition 4.1.1.2. (Note that encircled sets in (a) also satisfy Definition 4.1.1.2.) Fig. U. 1.1.1 Comparison of 'clusters' as defined in [Liu 72] vs. clusters as defined in Definition 4.1.1.2. 75 ((1010), (1000), (0000)}. It is not a valid true cluster since false vector (0010) satisfies: (1010) > (0010) > (0000). Note that a subset of the vectors in a cluster need not contain vectors com- parable to any of those in the remainder of the cluster, i.e., in a sense, a cluster need not be 'connected'. In the case of the false cluster {(1011), (1001), (0011), (0100)} shown in Fig. 4.1.1.1(b), false vector (0100) is in- comparable to the other three vectors of the cluster. Definition 4.1.1.3 The minimum and maximum vectors of a cluster are called, respectively, floor vectors and ceiling vectors of the cluster. In the false cluster { (1011), (1001), (0011), (0100)} of Fig. 4.1.1.1(b), vectors (1011) and (0100) are ceiling vectors of the cluster while (1001), (0011), and (0100) are floor vectors. Note that vector (0100) is both a ceiling and floor function. Definition 4.1.1.4 The ceiling function of a cluster with ceiling vectors A 1 , . . . ,A^ is given by: o^ v ... v a k , where a. is the a-term of ceiling vector A. . The floor function of a cluster l & l with floor vectors B,,...,B. is given by: •*- J 3 v . ■ . ^ 3 . where 3- is the 3-term of floor vector B. . l l For example, the floor function of the false cluster ( (1011), (1001), (0011), (0100)} in Fig. 4.1.1.1(b) is: x 2 v x l x 4 v X 3 X 4' 76 corresponding to its floor vectors, (0100), (1001), and (0011). The ceiling function of the same cluster is: X,-, \y X_X^X| ^2 l 3 h f corresponding to its ceiling vectors, (1011) and (0100). Theorem ^. 1.1.1 Let Q, = [k , . . . ,kA be a cluster of vectors with respect to a function f. Let a. v . . . v a. and p v . . . <• p be the ceiling and °1 J p k l q floor functions of the cluster, respectively, and let A. v . . . s/ A* denote the disjunction of minterms of the vectors A , . ..,A* in set Q. Then: if Q, is a true cluster, A n v- . . . sy Aq , = (a. '1 u p iV l "q k ± s/ . . . v A^ = (a. v... v a. )(p k v . . . v P k ) c f ; or, if Q, is a false cluster, A-. v... \y An = ( Q! . V ... vQ. )( (3, v... V (3, )cf. i * J-l J p k x k q - Proof Consider the case when the set Q is a true cluster. Obviously, the disjunction of minterms corresponding to the vectors of the cluster implies f since the vectors are all true vectors of f. Next, let A. 6 Q, 1 < t < p, 3 t be a ceiling vector of the cluster with a-term a. , and let B, £ Q, 1 < u < q U t U be a floor vector with p-term (3 . Now, since a. =1 for vectors A such u °t that A < A. and & = 1 for vectors B such that B > R , a. & =1 for a t U U U t U vector C if and only if A. > C > B, 't u Since (l) every vector C e Q, must obviously satisfy this condition for at least one pair of A. , 1 < t < p, and B, , 1 < u < q, and (2) every vector C To eliminate the need for introducing another notation, A. will be used both to denote a vector and its corresponding minterm. The intended usage should be clear from the context whenever the notation appears. 77 satisfying this condition must be a member of Q by the definition of a cluster, it can be concluded that: A^ ^ . . . ^ A, = (a s/ ... v a. ) (a v . . . v & ). X J l J p K l *q A similar argument can be made when set Q is a false cluster. Q.E.D. As an example, consider the false cluster { (1011), (1001), (0011), (0100)} of Fig. k. 1.1. 1(b): X 1^2 x 3 x if v X 1 X ^3 X 1* v x *i x 2 x 3 x i+ v ^i x ^3 X li. = (x 2 v x.^ v x 3 x ]+ )(x"2 v/ x^x x^) c f. The true cluster { (1111), (1110), (0111), (0110) } of the same figure is a special case in which the ceiling function is the constant 1: X^XgX X^ ^ X^^I v YgXX^ v X-jXgX x^ = (x g x )(1) c f. It is clear from the preceding theorem that a function f is implied by the disjunction of products of ceiling and floor functions for true clusters with respect to f. Furthermore, if every true vector is a member of at least one of these true clusters, the disjunction is an expression of f itself. Corollary h. 1.1.1 Let Q, = {A.. , . . . ,A*} be the set of all true vectors (false vectors) or a function f, and let Q n ,...,Q, be sets of vectors which represent true clusters (false clusters) with respect to f such that Q = Q 1 U . . . U Q r . Let A. _, — ,A. be the minterms corresponding to vectors in set Q. , and 1,1 ^jS. ! let a. . ^ ... v a. and B. , v ... v 8. be the ceiling and floor 1,1 i,P t i,l H i,q i functions, respectively, of the cluster represented by set Q. . Then: 78 r,s. A, - v ... v A- v ... \/A _ \/ . . . v A 1,1 l,s 1 r,l = (ql , \/ . . . v ql ) (p_ , \/... v/3 n )s/... v v r,l r,p'^r,l r>P r function f can be expressed, according to Corollary k. 1.1.1, as follows: ? = U 1 (0 1,1 h,^ U r (f3 r,l- tv,^' Again, u , ...,u , and f are seen to be negative functions of the variables 80 false cluster II r I Fig. If. 1.1. 2 True and false clusters chosen for a function f. 81 Fig. U.l.1.3 A 2-level network realizing function f of Fig. 4.1.1.2. Network's synthesis is based on true clusters. 82 u l = x f% " x l x 3 c H u i f = u x - u 2 (x lXl| ) f -'t.l.l.'i -level network realizing function f of Fig. H.l.1.2. Network's synthesis is based on false clusters. 83 in terms of which they are expressed. Based on the false clusters encircled in Fig. U.l.1.2, the 2-level network of MOS cells shown in Fig. U.l.l.U can be constructed. If one would be able to give a method for selecting, for a given function f, a number of true clusters (or false clusters) such that (i) every true vector (false vector) of f is included in at least one cluster and (ii) the number of these clusters which have floor functions other than the constant 1 (having ceiling functions other than the constant l) is D (1,0), then one would have an algorithm for synthesizing G-minimal, 2-level networks of MOS cells (see Theorem 3.8). The approach taken in [Liu 72] and [Liu 75 ] represents one such method, but others are also possible as will be seen shortly. As a result of the algorithm given in these two papers for choosing true and false clusters, the clusters generated have special relations to each other — relations which are most completely exploited in the related synthesis algorithm for G-minimal, multiple -level networks (given in [Liu 72]). The synthesis algorithms devel- oped by Liu for G-minimal, 2-level networks will be discussed in the next section. .1.1.1 Liu's synthesis method for G-minimal, 2-level networks Liu's method begins with the creation of a 'stratified structure' for a given function f. A stratified structure is essentially a unique partition of all input vectors of the function into true and false clusters, designated MT, i = 0,...,2r, having special properties (from some of which the modifier 'stratified' results). The following gives Liu's definition of a stratified structure translated into the notation of this paper: 8U Definition k. 1.1.1 The stratified structure of a function f of n f f f • V M l>"-> M 2r' f f f variables is a sequence of subsets of input vectors, (Ml,MT , . . . ,lil ) where r = D (1,0) + 9, 9 -0 if is a false vector and 6 = 1 if is a true vector, defined as: (1) M for i --' 0,1,..., r - 1 contains every true vector, A, of of f such that D X (A,0) = i + 1 - 9. (2) M . for i = l,2,...,r - 1 contains every input vector, A, f which satisfies the following conditions: f (i) A > B for at least one B £ M . ', (ii) A £ B for every B e M 2> ,; (iii) A ft hf 2± _ y f f (3) M„ contains every input vector, A, such that A ^ B for every B 6 M, . f f (h) M p contains every input vector, A, such that A jk M„ . and f A > B for at least one B € NL 2r-l As previously mentioned, Fig. k. 1.1. 1(a) is an example of the stratified structure for function f represented by the labelled n-cube. From top to bottom, f f f f the five encircled sets of input vectors are, respectively, M, , M p , M , M., f f and Mj-. It can be seen that the choice of these M. is the only one which satisfies Definition ^.1.1.1.1. The following properties of the stratified structure have been shown by _. f"Liu 72] , , . Liu (some aspects are obvious from the definition): Property I (Theorem 2.2.1 and Corollary 2.2.1 of [Liu 72]) Mq,M^,. . . ^ are disjoint; all f true vectors are contained in M 2i+1 ,i = 0,1,..., r - 1, and these subsets contain f only true vectors; all false vectors are contained in M .,i = 0,1,..., r, and these subsets contain only fa.lse vectors; Property II (Theorem 2.2.3 of fLiu 72 J) f for every two subsets M and f-i". , i < ,j, (1) A £ is for every pair of input vectors 85 f f f A € M. and B € M., and (2) for every B e M. there exists at least one input f vector A e M. such that B > A. Theorem k. 1.1. 1.1 Each subset, M.,i = 0,1,..., 2r, of input vectors in the stratified structure for a function f constitutes either a true cluster or a false cluster. Proof To be a cluster, either a true cluster or a false cluster, a sub- f set of input vectors, M. , must satisfy the conditions of Definition 4.1.1.2: f for every pair of vectors, A. and A*, of M. which satisfies A. > k g . every 3 * ! 3 * vector A, satisfying A. > A, > A* is also a member of the set. Assume this is not true for some subset MT and input vectors A., A, , A*. Then A, £ M where p f i. If p > i, then A. > A, contradicts Property II above. If i > p, A, > kg contradicts Property II. Thus, each MT in the stratified structure of a function f must be a cluster. Q.E.D. [Liu 72] proves that the following algorithm generates the stratified structure for a given function f. (This algorithm is slightly different from the form in which it appears in [Liu 72].) Algorithm 4.1.1.1.1 Algorithm to obtain a stratified structure for a given function f (SS). "" f Step 1 If is a false vector of f, assign it to M Q . Otherwise, assign it to MT. Set w = 0. Step ; w = w + 1. Step ; If w > n, stop. Step h For each vector A of weight w, let Q be the set of vectors B of weight w - 1 such that A > B, and then assign A to M where: t = max[p +1, q], % f p is the maximum subscript such that M contains at least one vector in Q of f the opposite type as A, and q is the maximum subscript such that M contains at least one vector in Q. of the same type as A. Go to Step 2. Upon completion of this algorithm, all vectors in V belong to one of f the M. ,1 -- 0,1, . .. ,2r. After obtaining the stratified structure for a given function f, the rest of Liu's synthesis method is straightforward. Based on the stratified struc- ture, an expression of f is written (corresponding to either of those given here by Corollary 4.1.1.1) from which the cell configurations of the desired MOS cell network can be directly determined. This expression can be based on either the true or false clusters of the stratified structure, corresponding to Liu's two different synthesis algorithms, respectively. In [Liu 75 1 it is mentioned that these synthesis algorithms can be used for incompletely specified functions as well by ignoring unspecified input vectors (only specified true or false vectors are included in the M. ). This can be accomplished during the construction of the stratified structure by ignoring unspecified vectors in Step k of the preceding algorithm. In the preceding Fig. 4.1.1.2, the selection of clusters for the function f was exactly that which would have been obtained by Algorithm k. 1.1. 1.1 (SS). f Following Algorithm SS, all vectors of false cluster I are assigned to NL f all vectors of true cluster I are assigned to M, , all vectors of false cluster II are assigned to M^, and all vectors of true cluster II are assigned to M . This stratified structure leads, of course, to the MOS cell network shown in either ' . I*. 1.1. 3 or Fig. h.l.l.h, depending on whether true or false clusters are chosen to express f, respectively. Thus, these two figures represent the results of Liu's synthesis algorithms for the output function f. 87 Due to the special nature of the clusters obtained from the stratified structure, the following theorem can be demonstrated. Theorem 4.1.1.1.2 For any two distinct subsets of input vectors, M. and NT, i > j, of the stratified structure, (Mt,IC, . . . ,M ? ), of a function f: where 0. , v ... v p. and 8- t v ... ^ 8- are the floor functions of 1,1 i,^ 0,1 K J,q. clusters MT and IC, respectively. f Pro Consider each 8-term, 8- v of the floor function of M. . Let B. , be the floor vector corresponding to 8- v « Ey Property II of the stratified structure, there must exist a vector C e IC such that B. , > C. And, i,k by definition of the floor vectors of a cluster, there must exist a floor vector, B. p (with 8-term, 8- /?), of M. such that C > B. „. Thus B. , > B. . Since 0,* , " ' "" 0," 1 , K 0,* the 8-term of a vector A has the value 1 for an input vector if and only if the input vector is greater than or equal to A, 8- v = 1 ^ or an i- n Put vector only if 8- n =1. Therefore, for every 8- v among B. ,,...,8. there exists a 8. r among 8- ,...., 8- such that 8- i c 8 • J • Although neither of Liu's synthesis algorithms for 2-level networks utilizes the property of the stratified structure given in Theorem k. 1.1.1. 2, this ''}'. c c f -o a Fig. .. 1.1.1.1 Generalized configuration of a 2-level I40C cell network synthesized by Liu'r algorithm based on true vectors. 89 (a) (b) Fig, h. 1.1. 1.2 Alternative output cell configurations for the generalized network of Fig. 4.1.1.1.1. 90 property can be used to obtain alternative and sometimes more desirable config- urations of the output cells in the networks synthesized. For example, suppose the stratified structure for a function f has already been obtained. From this, the following equation based on true clusters, Ml. , , i = 0,1,..., r - 1, can be written (let f and f , respectively, represent the ceiling and floor functions of cluster M. ) : l 11 3.3 .5.5 „2r-l 2r-l a p a p af, a p The corresponding MOS cell network configuration is shown, in generalized form 1 2r-l (remember that either or both of f„ and f could be the constant function l), v pa " in Fig. 4.1.1.1.1. In this figure, each of the FET's with an input from a second level cell realizes the transmission function f ' . Based on the fact that f Q ' 3 f_ P P — P for i > j, several other configurations of the output cell are also possible. Two of these are shown in Fig. 4.1.1.1.2. From a practical viewpoint, the configuration of Fig. 4.1.1.1.2(a) may be more desirable than the configuration of the output cell in Fig. 4.1.1.1.1, since it will have, in general, fewer FET's in series (in practice, the number of FET's in series is often more critical than the number in parallel). It should be noted that while the three output cells shown in these figures ~~1 ~3 ~~2r-l realize different functions of their inputs (i.e., if x_,,...,x , f_,fr,...,f_ 1' n p p p were all independent variables), they all realize function f because of the ~1 ~3 ~2r-l special relations among the functions f ,f":,...,f realized by the cells of the second level. :milar alternative configurations of the output cell exist for the synthesis f of the networks based on false clusters M ,i - 0,1,..., r, of the stratified 91 structure. In this case, the alternative configurations depend on the fact that f? 1 c f? J for i > j (Theorem 1*. 1.1.1. 2). p — p The clusters, true or false, used in Liu's 2-level synthesis methods are, as discussed, both disjoint and 'stratified' (i.e., satisfy the conditions re- quired for a stratified structure). Actually, the clusters from which an expression is derived for a given function f (according to Corollary 4.1.1.1) need be neither. In fact, without these constraints, improved results (i.e., networks with fewer FET's) can often be obtained. Section 4.1.2 will propose new synthesis methods based on non-stratified (and often, non-dis joint ) clusters, The following algorithm to label an n-cube for a function f is given in [Lai 76] as an essential part of Lai's method for synthesizing G-minimal, ir- redundant (i.e., no FET's may be removed from the network without creating erroneous outputs for some input vectors) networks of MOS cells. By observing the correspondence between Liu's stratified structure and the labelled n-cube resulting from this algorithm, the relation between Liu's stratified structure algorithm and Nakamura et al. 's minimum n-cube labelling algorithm is suggested (as will be seen in Section 4.1.1.2). Algorithm 4.1.1.1.2 Algorithm based on maximum labelling with a minimum number of bits ( MXL ). Let L (A) be the binary label attached to each vertex A e C by this mx J n algorithm for a given function f. Let R f = l"log 2 (D (1,0) +1)1 +1. Step 1 Assign L (0) = 2 - 2 + f(0). Set w = 0. ■ ■ r — mx Step ; w = w + 1. This algorithm will also be important for the discussion in Section 7. 92 Step 3 If w > n, stop. Step h For each vertex A of weight w, let Q. be the set of vectors B of f weight w - 1 such that A > B, and then assign as L (A) the largest binary integer satisfying the two conditions: f (i) The least significant bit of L (a) is f(A); [TLX. (ii) L f (A) < L f (B) for every B e Q A . v ' mx — mx A Go to Step 2. In the labelled n-cube resulting from Algorithm MXL, each bit of each binary label is important for (multiple-level) network synthesis as will be discussed later. It can be demonstrated that each set consisting of all vectors, A, having f ~* identical binary labels, L (A), is a cluster. Furthermore, if f(0) = 1, iILX {a| A e V and L f (A) = 1} = pf ' , n mx ^f 2 -i and if f(0) = "P "P (a|a £ V and L (A) = i} = M n mx R 2 -2-i In other words, the results of Algorithm MXL can be interpreted as a partition- ing of the input vectors for a given function into a stratified structure. Fig. k. 1.1. 1.3 and Fig. 4.1.1.1J4 allow a comparison of the results of Algorithm ^.1.1.1.1 (SS) and Algorithm MXL for a function f. D f (l,0) = 2 and R = 3- Since f(0) - 1, L f (A) i- j = 2 f = 8 for every vector A £ U f .. As f ' mx J j can be seen from the figures, grouping the vertices given the same labels by Algorithm MXL results in the stratified structure. 93 M oonioio 1 0110 l ~"~^^ ( 1000 1 ![T \pioo 0000 Fig. 4.1.1.1.3 Stratified structure obtained for a function by Algorithm h. 1.1. 1.1 (SS). .110 vertices with label Oil vertices with label 100 lOOj 11010 101 0110 101 ^~-«^ /^ V- (1000 111 ^j \pioo 110 vertices with label 101 vertices with label 110 vertices with label 111 Fig. U. 1.1. 1.4 Labelled 4-cube obtained by Algorithm h. 1.1. 1.2 (MXL) for same function appearing in Fig. 4.1.1.1.3. Vertices having identical labels are grouped together. * Theorem h. 1.1. 1.3 Given a completely specified function f of n variables, for each input vector A £ V assigned to M. by Algorithm J+. 1.1.1 (So), the f R f label L (A) = 2 - 20 - i is assigned to vertex A e C by Algorithm h. 1.1. 1.2 mx v ' to n ° (MXL), where R f = riog 2 (D f (1,0) +1)1 + 1, = if f(o) = 1, and = 1 if f(0) = 0. Proof This proof can be accomplished by induction on the weight w of in- put vectors. For w = 0, i.e., for 0, there are two cases: f - R f Case 1 f (0) =0. By Step 1 of Algorithm MXL, L (0) = 2 - 2. By Step 1 — — — mx ~* f of Algorithm SS, is assigned to M„, and the theorem is true in this case. Case : f (0) = 1. By Step 1 of Algorithm MXL, L (0) = 2 - 1. By Step 1 1 ' ' ulX "* f of Algorithm SS, is assigned to M, , and, again, the theorem is true. Nov/ suppose the theorem holds for all vectors of weight w. Let A be any true vector of weight w + 1. Let (B , ...,B } be the set of all false vectors such that B., 1 < j < k, is of weight w and A > B.. Let {C ,...,C g } be the set of all true vectors such that C, 1 < j < i is of weight w and A > C. Let b . = L (B. ), j = 1, . . . ,k, y - - j j mx v 3 and c. = L (C.), 0* = !,...,&. j mx v j" ■f By Step k of Algorithm MXL, L ^ (A) is clearly minfb - 1,..., \ - 1, c. ,. . . ,c /,}. Since the theorem is true for vectors of weight w, B , ...,B , f f C ,...,'_' ; are assigned by Algorithm SS to M ,...,M , 2 f -29-b n 2 f -20-b M f fi Ik f' f M R , respectively. Thus, by Step h of Algorithm SS, 2 f -20- Cl 2 f -26-c Jl f R f R f vector A belongs to M. where i = max{2 ' - 20 - b + 1,...,2 ' - 20 - b + 1, R f f 1 R f - ,,...,' ' - 20 - cJ = 2 -20+ maxCl -• b_,...,l - b. , - c_,..., - o 3 : „ k f R f f - -0 - min(b, - l,...,b. - 1, c,.....cj = 2 ' - 20 - L (A). Thus, * 1 ' ' k ' 1' ' Ji mx ' 95 the theorem is true for every true vector of weight w + 1 if it is true for every vector of weight w. A similar argument can be made for any false vector A of weight w + 1. Hence, by induction, the theorem statement is valid for every input vector A of f. Q.E.D. It is also interesting to note that the results produced by the algorithm for synthesizing G-minimal, 2-level networks in [IM 71] and the results pro- duced by the corresponding algorithm in [Liu 75] or [Liu 72] are very closely- related . This similarity of results arises due to the relation between clusters of the stratified structure of [Liu 75] and compatible sets of essential supplemen- tary columns chosen in [IM 71] from graph G„ developed for a given function f. Corresponding to the results of Liu's synthesis algorithm based on the true clusters of a stratified structure, second level cells of identical con- figurations can be obtained by the synthesis algorithm of Ibaraki and Muroga under the following conditions: (1) When obtaining negative completions for the conjoints of the com- patible sets of essential supplementary columns, assign the value for all unspecified vectors greater than existing specified false vectors. Assign the value 1 for all other unspecified vectors. (2) From these negative completions given in truth table form, develop an expression for the function of each required second level cell based on minimal false vectors (i.e., based on the floor function of the single cluster consisting of all false vectors). The configuration of each second level cell can be obtained directly from the respective expression. 96 Corresponding to the results of Liu's synthesis algorithm based on the false clusters of a stratified structure, second level cells of identical configuration can be obtained by the synthesis algorithm of Ibaraki and Muroga under the following conditions: (1) When obtaining negative completions for the conjoints of the compatible sets of essential supplementary columns, assign the value 1 for all unspecified vectors less than existing specified true vectors. Assign the value for all other unspecified vectors. (2) From these negative completions given in truth table form, develop an expression for the function of each required second level cell based on maximum true vectors (i.e., based on the ceiling function of the single cluster consisting of all true vectors). The configuration of each second level cell can be obtained directly from the respective expression (since all of the variables in the ceiling function are complemented, disjunction and conjunction in the expression correspond to conjunction and disjunction in the configuration, respectively). Furthermore, after the selection of second level cells realizing functions identical to those realized by second level cells chosen by Liu's algorithm, Ibaraki and Muroga' s algorithm can also allow the creation of an output cell identical in configuration to that resulting from Liu's algorithm. Thus, the networks producible by Liu's 2-level synthesis algorithm are a subset (in general, a proper subset) of those producible by Ibaraki and Muroga 's algorithm. Observation of the correspondence between Ibaraki and Muroga 's algorithm and the two algorithms of Liu enables a more thorough understanding of the relation between the algorithm based on true clusters and the algorithm based on false clusters of the stratified structure. 97 4.1.1.2 Nakamura, Tokura, and Kasami's n-cube labelling method as a synthesis method for O-tainimal^ 2-level networks In the preceding section (4.1.1.1) the correspondence between the maximum labelling of an n-cube with a minimum number of bits (i.e., the result of Algorithm 4.1.1.1.2 (MXL) and the stratified structure (the result of Algorithm 4.1.1.1.1 (SS)) was demonstrated. There exists a counterpart to the stratified structure defined by Liu which has equivalent properties enabling it to be used in both new 2-level and new multiple -level, G-minimal network synthesis algorithms. This counterpart is related to the n-cube labelling scheme used in [NTK 72] (as a means to synthesize multiple-level, G-minimal networks) in the same manner in which Liu's stratified structure is related to the scheme for maximum labelling, Algorithm MXL. Although the new class of synthesis algorithms thus created produces results of generally the same quality as those of [Liu 72] (since the clusters on which they are based have the same 'horizontal' characteristic as the clusters of Liu's stratified structure), for a given function, the new algorithms may obtain a superior result (and vice versa). The following algorithm, proposed in [NTK 72], for labelling an n-cube for a function f of n variables will be referred to as the algorithm based on minimum labelling (as named in [Lai 76]). Algorithm 4.1.1.2.1 Algorithm based on minimum labelling (MNL). Let L (A) be the binary label attached to each vertex A e C by this mn v J n algorithm for a given function f . Step 1 Assign L (l) = f(l). Set w = n. Step w = w - 1. 'r' Step 3 If w < 0, stop. Step h For each vertex A of weight w, let Q, be the set of vectors B of weight w + 1 such that B > A, and then assign as L (A) the smallest binary & } o mn integer satisfying the two conditions: (i) The least significant bit of L (A) is f(A); (ii) L f (A) > L f (B) for every B e Q A . mn — mn Go to Step 2. The following theorem was proved in [Lai 76]: ■p Theorem h. 1.1. 2.1 L (A), the label attached to vertex A by Algorithm k. 1.1. 2.1 (MNL) for a function f, has the value L f (A) = 2D f (l,A) + f(A) for every A e C . n As a consequence of this theorem, the label attached to vertex by Algorithm MNL is 2D f (l,0) + f(0). Theorem ^-.1.1.2.2 Each set consisting of all vectors A € V correspond- ■£ ing to vertices assigned identical binary labels, L (A), by Algorithm k. 1.1. 2.1 (MNL) for a function f of n variables, is a cluster. Proof Let Q denote any set consisting of all vectors for which the associated vertices are assigned identical labels by Algorithm MNL for a function f. It is clear by condition (i) of Step k of the algorithm that no two vectors of opposite types (i.e., one true vector and one false vector) can be members of the same set Q. Now suppose Q is not a cluster. Then, by the definition of a cluster, there must exist three vectors, A e Q, B ft Q, and : e Q, such that A > B > C. By condition (ii) of Step h, of the algorithm, 99 L (c). This implies B € Q, which contradicts the assumption that B £ Q. Thus, no set of vectors, A, B, and C, satisfying the above conditons can exist, and set Q must be a cluster. Q.E.D. Clearly L (0) = 2D (1,0) + f(0) is the greatest possible label which can be assigned by Algorithm MNL to a vertex in C (if it were not, condition (ii) of Step k could be used to show a contradiction). Since the label assign- ed to the vertex of a true vector always has a '1' as its least significant bit, the maximum possible number of different labels assigned to vertices re- presenting true vectors (i.e., the maximum number of true clusters) is D (1,0) + 1 if is a true vector and D (1,0) if is a false vector. In either case, following Corollary h. 1.1.1 it can be seen that a network consisting of D (1,0) + 1 cells (D (1,0) second level cells and one output cell) can be constructed. (Recall that if is a true vector, the cluster which includes it will have the constant '1' as a floor function, and no cell corresponding to this cluster is necessary.) By Theorem 3«8, a 2-level network of D (1,0) + 1 cells is a G-minimal, 2-level network for a given completely specified function f. In a similar manner, a G-minimal, 2-level network can be constructed based on the false clusters (in the sense of Theorem k. 1.1. 2. 2) created by Algorithm MSL. As an example of the n-cube labelling produced by Algorithm MNL and the G-minimal, 2-level networks which can be obtained from it by grouping into clusters all vectors corresponding to vertices assigned the same label, 100 consider the function f shown in Fig. 4. 1.1. 2.1 (this same function was considered in Fig. 4.1.1.1.3 and Fig. 4.1.1.1.4). The labelled n-cube re- sulting from Algorithm MNL is given in Fig. 4.1.1.2.2. This figure also shows the grouping of vertices having the same labels (note that the resulting clusters are significantly different from those produced in a similar manner by Algorithm 4.1.1.1.2 (ML)). Based on the true clusters in Fig. 4.1.1.2.2, the following expression for f can be obtained according to Corollary 4.1.1.1: f = l(x 2 x ) ss (x 2 x^ v x^x )(x x v x^) v, (xLjX^x 3X^)1 This, in turn, suggests a G-minimal, 2-level realization consisting of three MOS cells, g.., g , and g~,> realizing the following functions, u, , u„, and u = f. respectively: U l = X 2 X 3 u 2 = x ± s, x h U 3 = u i^ x 2 s x 1+ )(x 1 v x ) v u 2 )(x v x 2 v X v x^_) = f . The corresponding network is shown in Fig. 4.1.1.2.3(a). Based on the false clusters in Fig. 4.1.1.2.2, the following expression for f can be obtained: f = (x 2 v x 3 )(x 1 x g v x^ ss x^) ss (a^x x^ v x 1 x 2 x 1+ )(x 2 v/ x ) Tho functions, u , u , and u (= f) of the three cells, g , g , and g in the corresponding G-minimal, 2-level network are: u l = X 2 X 3 u 2 = ( x 1 - x 4^ x i ^ x ? v x )^ U 1^"1 X P " W , ),) - U ;J (X 2 w x ) - f. The corresponding network is shown in Fig. '1.1.1.2.3(b). 101 Fig, h. 1.1. 2.1 Function for demonstration of Algorithm 4.1.1.2.1 (MNL), true cluster true cluster vertices with label 001 vertices with label 010 )011 010 vertices witnS.OOOl label 100 Oil vertices with label Oil vertices with label 101 Fig. U. 1.1. 2. 2 Labelled U-cube obtained by Algorithm if. 1.1. 2.1 (MNL) for function appearing in Fig. k. 1.1. 2.1. Vertices having identical labels are grouped together. 102 H A 3 H bO OJ T^r yyi OJ bO OJ OO X X 'Tjt J- X OJ X en H X H on bo bC S3 °~p r^__f OJ -H OO OJ bO TF" Hi 'O 03 O c •H •H P 03 S3 P> fit 'O O •H cq 13 fH H 0) CD • c -P OJ bO w • •H 3 H GQ H • GQ o H 03 -* S3 GQ o H • • cC bO Ch ^-v

OJ -ct- rQ •H > bO • J*i

bO -P d C 01 CD o •H 0) S •H ft CQ -P 3 — O o ^~N c fH^-N r^ p

CD -H CD ?H fH H I O cq bO OJ ^ d CD j • 03 2 & CQ a rH Sh •H a cq CD a H P •H £ CD 3i f O ,Q fn 03 H cs cp H o 0) 3 on S • +3 OJ CI H o • H T3 • 0) J- GQ 0? * c^ bO ^ pB, h o £ +3 0) a H 103 Let pictorial representations for certain relationships among input vectors be introduced in Fig. 4.1.1.2.4. For a given cluster of input vectors, Q e V : region I in Fig. 4.1.1. 2. 4(a) represents all vectors not in Q, which are greater than at least one vector in Q; region II in (a) represents all vectors either less than or incomparable to every vector in Q,; region III in (b) represents all vectors either greater than or incomparable to every vector in Q; region IV in (b) represents all vectors not in Q which are less than at least one vector in Q. With this representation, the stratified structure of a function f can be illustrated as in Fig. 4.1.1.2.5. In this figure, the relative positions of the clusters are shown with the same V-shapes as Fig. 4.1.1.2.4(a). This representation is also indicative of the origin of the name 'stratified structure. 1 Using the chevron shapes of Fig. 4.1.1.2.4(b), Fig. 4.1.1.2.6 illustrates the relation of the clusters which result from the grouping of vertices of C assigned the same label by Algorithm 4.1.1.2.1(MNL) for a function f. The clusters created by Algorithm MNL (i.e., the n-cube labelling method of [NTK 72]) have properties which correspond to those (e.g., Properties I and II and Theorems 4.1.1.1.1, 4.1.1.1.2, etc.) of Liu's stratified structure (which can be obtained through the use of Algorithm 4.1.1.1.2 (MXL)). It has just been shown that G-minimal, 2-level networks can easily be derived, based on these new clusters, in much the same manner that Liu proposed based on the clusters of his stratified structure. In addition to this, the parallel between the structure consisting of clusters created by Algorithm MNL and the stratified structure will also enable the synthesis of G-minimal, multiple- 104 (a) vectors greater than at least one vector in Q vectors less than or incomparable to every vector in Q (b) vectors greater than or incomparable to every vector in Q vectors less than at least one vector in Q Fig. 4.1.1.2J4 Pictorial representation of certain relationships among input vectors. 105 Fig. U. 1.1.2. 5 Pictorial representation of a stratified structure (i.e., among clusters created by Algorithm 4.1.1.1.2 (MXL)). Fig. U. 1.1.2. 6 Pictorial representation of relationships among clusters created by Algorithm k. 1.1. 2.1 (MNL). 106 level networks based on the former (in a manner similar to that in which it is accomplished, based on the latter, in [Liu 72]). For the convenience of future discussion, let Liu's stratified structure for a function f (Definition ^.l.l.l.l) be referred to as the BU-stratif ied structure (Bottom Up) for a function f. Let the structure represented by the clusters obtained, as described, through the use of Algorithm MNL be called the TD-stratified structure (Top Down) for a function f. Consider the following structure consisting of sets of input vectors for a given function. Structure I Let (wt,WT,. . . ,Wp ) be the sequence of subsets of input vectors defined as follows for a function f of n variables, where r = D (1,0 ) + 9, 9 - if is a false vector and 9 = 1 if is a true vector: (1) WI. for i = 0,1,..., r - 1 contains every true vector, A, of f such that D (l,A) = i. (2) WZ. for i = l,2,...,r - 1 contains every input vector, A, of f which satisfies the following conditions: (i) A < B for at least one B € WZ. _, ; 2i-l (ii) A ^ B for every B e W ; (iii) A € W^. +1 . (3) WI contains every input vector, A, such that A ^ B for every B € VL. (h) Wp contains every input vector, A, such that A ft Wp and A < B for at least one B e WZ 2r-l It can be shown that the structure (w£,wf ,. . . ,WI ) defined above is 0' 1' ' 2r actually the TD-stratified structure obtained by Algorithm k. 1.1. 2.1 (MNL) (i.e., grouping vertices of the same labels assigned by Algorithm MNL produces Wq,W£,.. .,W 2 ). Furthermore, the TD-stratified structure can be demonstrated to have properties exactly paralleling those of the BU-stratified structure. 107 4.1.2 Synthesis methods for 2-level networks based on non-stratified structures The true and false clusters of the stratified structure which form the basis of the synthesis algorithms presented in Section 4.1.1.1 and 4.1.1.2 possess special properties which are actually unnecessary in the synthesis of G-minimal, 2-level networks. For example, the clusters of both the BU- and TD-stratified structures are disjoint and they have the 'stratified' relations pictured in Fig. 4.1.1.2.5 and 4.1.1.2.6. Furthermore, in order to produce these properties, the characteristics of the individual clusters are generally not the most desirable (compared with other selections of sets of clusters which are not necessarily stratified)for obtaining a G-minimal, 2-level net- work having a relatively small number of FET's. A typical cluster in a stratified structure tends to be rather 'horizontal' in shape when viewed in the context of an n-cube (i.e., there is usually not a wide variation among weights of the different vectors in the same cluster). T This 'horizontal shape' generally results in relatively large numbers of floor and ceiling vectors. These, in turn, lead to large numbers of literals in the corresponding floor and ceiling functions, and these literals have a 1-to-l cor- respondence with the number of FET's in the resulting MOS cell network. Of course, the expressions (see Corollary 4.1.1.1) corresponding to the MOS cell configurations can be factored to obtain cells of fewer FET's. However, the large number of original literals increases the factorization problem. Furthermore, if clusters with simpler floor and ceiling functions are selected, factoring the simpler expressions can often lead to a final result with still fewer FET's. 108 To produce a G-minimal, 2-level network for a function f based on true or false clusters, Q. , i = l,...,r, as outlined near the end of the intro- duction to Section 4.1.1, only the condition on the Q. given in Corollary 4.1.1.1 need be met for r = D (1,0) + 9. Clusters need be neither disjoint nor stratified nor have the property that every pair of vectors, A and B, in the same cluster satisfies D (l,A) = D (l,B) or D (A,0) = D (B,0) - these being characteristics of the clusters of the TD- and BU-stratified structures. Free of these restrictions, clusters can be selected for use which are more 'vertical' in shape (i.e., have relatively fewer floor and ceiling vectors for a given number of vectors in the cluster) than those resulting from either Algorithm 4.1.1.2.1 (MNL) or Algorithm 4.1.1.1.2 (MKL). As discussed, a synthesis based on such clusters seems likely to lead to 2-level MOS networks having relatively small numbers of FET's. The desired algorithm, based on the new concept of clusters introduced in Definition 4.1.1.2, can be stated gener- ally as follows: Algorithm 4.1.2.1 General algorithm, based on a non-stratified structure, to synthesize a G-minimal, 2-level network of MOS cells implementable with a small number of FET's for a given function f of n variables ( GNS )„ Step 1 Determine the inversion degree, D (1,0), of function f. Step c Decide whether the synthesis will be based on true clusters or false clusters of f . Step 3 Determine the number of true clusters (false clusters, if so decided in Step 2), r, which must be chosen to yield a G-minimal network: r = D f (l,0) + 0, where: Q = 1 if is a true vector (1 is a false vector); 6 = if is a false vector (1 is a true vector). 109 Step k Select r true clusters (false clusters), ft..,..., ft , such that ft, U . . . U ft is the set of all true vectors (false vectors) of f. Attempt to choose the ft. such that: the numbers of ceiling and floor vectors are as small as possible; the weights of the ceiling vectors are as large as possible; and the weights of the floor vectors are as small as possible. Step Express f (f) in terms of the ceiling and floor functions of ft.: (0 l,r ,,,vfl i l p l % l r ,MV ^ v . . . v (a r,l a r,P r )(P r,l ^qj = f (=^> where: p. and q. are, respectively, the numbers of ceiling vectors and floor vectors of cluster ft.; a. . v ... v a. and p. , v . . . v p. are, respec- tively, the ceiling and floor functions for cluster ft. . Step 6 Define u. as the complement of the floor function (ceiling function) for true cluster (false cluster) ft.. Express u_,...,u , and f as follows : U-. = P-, - v . . • v P. 1,1 i*q x u =6 , v • • • v B r ^r,l H r,a : (a, n ... a, ^ vuj . . . (a, ., . . . a v u r ) (a L,l •'• ^"V ' ' * (a r,l (u i=*L,l *•• «L,p. u = a ..... a r r,l r,^ f =V P 1,1 V '-- "^q^ " * ' ' vU r (a r,l^-" ^r,^ } 110 Step 7 The configuration of a G-minimal, 2-level network consisting of x + 1 - 6 MOS cells can be obtained directly from the r + 1 expressions re- sulting from Step 6. Each expression defines the output function and con- figuration of a corresponding cell of the network, with the possible exception of one expression for a u. , 1 < i < r, which, when 0=1, is the constant (constant 1, if synthesis is based on false clusters) and requires no cor- responding cell. Example 4. 1.2.1 Consider once more the function f of Fig. 4.1.1.2. Let Algorithm GNS be employed for this function. In Step 1, it is determined that D (1,0) = 2 (consider the directed path (111) -> (101) -> (100) -* (000)). Suppose it is decided in Step 2 that the synthesis will be based on true clusters. By Step 3, the number of clusters to be chosen, r, is two. The following two true clusters are selected in accordance with Step 4 (see Fig. 4.1.2.1): Q 2 = {(111), (011)}, Q^ = {(110), (100)}. Following Step 5, f can be expressed as: l(x 2 x ) s, x x ± = f. Step 6 gives expressions which correspond to the output functions and configu- rations of individual cells in the network being synthesized: U-. — XpX„ u 2 =x 1 f = U X (X v Ug) By Step 7, the MOS cell network is constructed as shown in Fig. 4.1.2.2. Compare this result with that in Fig. k. 1.1.3 obtained based on the true Ill clusters of a BU-st ratified structure for f. The number of driver FET's has been reduced from ten to six while the optimum number of cells has been maintained. Results obtained by the other three methods based on stratified structures would be as follows: synthesis based on false vectors of BQ- stratified structure, nine FET's (reducible to eight FET's if expressions of Step 6 are factored); synthesis based on true vectors of TD-stratified struc- ture, ten FET's; synthesis based on false vectors of TD-stratified structure, nine FET's (reducible to eight FET's if expressions of Step 6 are factored). Example 4.1.2.2 As a second example of the improved results obtainable through the use of Algorithm GNS, consider the function f shown in Fig. 4.1.2.3 with its BU-stratified structure. In Step 1 of the algorithm, it is determined that D (1,0) = 2. Again, suppose it is decided in Step 2 to base the synthesis on true clusters. In Step 3, 9 = 1 since is a true vector, and the number of true clusters to be chosen is consequently determined to be three (i.e., r = 3)« The following three true clusters can be selected in accordance with Step 4 (see Fig. 4.1.2.4) q 1 = {(nil), (mo), (ion), (0111), (ioio), (oiio), (ooii), (ooio)} Q^ = {(1110), (1100), (1010), (1000)} ^ = {(1010), (1000), (0010), (0000)}. As evident from Fig. 4.1.2.4, the chosen true clusters are neither disjoint nor 'stratified.' Following Step 5, f can be expressed as : l(x ) s, (x 1+ )(x 1 ) v (x^)l = f. From Step 6, the following expressions are obtained which correspond to the output functions and configurations of individual cells in the network being synthesized: 112 Fig. 4.1. 2.1 Function f of Fig. 4.1.1.2 with chosen true clusters of non-stratified structure encircled. (Example 4.1.2.1.) 9 S- Q . x sH[ u, 5 <» o -L l M ■x Fi g. 4.1.2.2 O-minimal network resulting from Algorithm 4.1.2.1 (GNS) which realizes function f of Fig. 4.1.1.2 and Fig. 4.1.2.1. (Example 4.1.2.1. ) 113 rig. 4.1.2.3 Given function f with corresponding BU-stratified structure, (Example 4.1.2.2. ) Fig. 4.1.2.4 Function f of Fig. 4.1.2.3 with chosen true clusters of non- stratified structure encircled. (Example 4.1.2.2.) 114 u 1 =x 3 u 2 = x 1 u 3 . i . o f = (0 ^ u 1 )(x 1+ n, u 2 )((x 2 v X^) v- u^) = u 2 (x^ v u 2 )(x 2 v x^). By Step 7, the MOS cell network can be constructed as shown in Fig. 4.1.2.5. Note the absence of an MOS cell corresponding to the expression for u . This network consists of three MOS cells and seven driver FET's. The obvious simplification can be made in the output cell (corresponding to the factored expression: f = u, (u p x v x, ) ) to reduce this to a total of only six driver FET's. For comparison, let a second network be constructed which is based on the true clusters of the BU-stratified structure for f . There are three such clusters (see Fig. 4.1.2.3): M^ = {(1010), (1000), (0010), (0000)} M^ = {(1110), (1011), (0111), (1100), (0110), (0011)} r£ = {(mi)}. Employing the floor and ceiling functions of these clusters, the function f can be expressed as follows (in accordance with the algorithm given in [Liu 72], TLiu 751): f = ^ X 2 X U^ 1 v ^1 v X 2 v *l±)( x ± x 2 v X 2 X 3 v X 3 X 4^ v l( x r x 2 X 3 X l4)' Still following the algorithm of TLiu 72], [Liu 75], variables u and u are introduced such that f can be expressed as a negative function of x , ...,x , U l' U 2' and bath u i and u 2 can be expressed as a negative function of x..,...,x : u l ? v *2?3 v X 3 X 4 115 u 2 ~ X 1 X 2 X 3 X U f = ^ X 2 X 4^ v ^ X l v X 2 v X 4^1 v ^2 = (x 2 ^ x i+ )(x 1 x 2 x 1+ v U^Ug. The MOS cell network corresponding to these expressions can be seen in Fig. Fig. 4.1.2.6. The network employs three MOS cells and 17 driver FET's. The configuration of the cell corresponding to the expression for u, can be obviously simplified to reduce the total number of required driver FET's to 16. Thus the network of Fig. 4.1.2.5 represents a 59$, decrease in the number of driver FET's used to realize function f. For this problem, a synthesis based on the false clusters of the BU- st ratified structure in Fig. 4.1.2.3 would have yielded a network of three cells and 12 driver FET's (11, if simplified). Employing Algorithm GNS in a synthesis based on false clusters would have yielded a network of three cells and seven driver FET's (though having a different configuration than the net- work shown in Fig. 4.1.2.5). Algorithm GNS did not suggest how a minimum number of clusters Q. , upon which the syntheses are based, could be selected from the set of all possible input vectors. Although it is a trivial task to group true or false vectors into subsets Q. satisfying Corollary 4.1.1.1, it is not a trivial task to insure that the number of such Q. is minimal. Furthermore, it seems unlikely that any procedure suitable for hand computation can be given which directly (i.e., without 'branching' or 'backtracking' ) obtains a minimal number of such sets Q^ while secondarily minimizing the total number of literals in the expressions of their corresponding floor and ceiling functions (which have a direct correlation with the number of FET's in the implemented network) for every given function. This objective can be realized, however, in computer 116 Ch r> bO ~fa^" 0) d -p o C 3 o £ -p T3 W • CD m W 'U • o3 0) CVI ,0 -H • Ch H T3 -H • (U -p J- > 03 •H ?H • ?H -P bO 0) W •H T3 1 fe £> ^ m 3 Ph a Ch £ •H CD CO 1 *H ^ O -P <+H W VD CM • H -d- bO •H fr ^o H CM 3 CM bO O- J~ o !h CH hO "O bO • a C •H CM •H o3 P-4 • -P CM H-— <+H • 3 £ O H w S • 0) c5 CH -t U w fl a> ^j H O H fH • •H ft O CM -P S £ • o 03 -P H CD • pi H £ -d- Ch s_ H g a3 ,2 bO Fi -P •h on •H -H N • C ?H •H OJ •H O H • S hO 03 H 1 H a) • Cs < ?H J" CM bO 117 program implementations of the algorithms (e.g., through the use of integer programming). Hence, to maintain generality in Algorithm GNS, no specific procedure was mentioned for this portion of the algorithm. The following Algorithm 4.1.2.2 (SNS) for synthesizing G-minimal, 2- level networks of MOS cells does include a specific procedure for choosing a minimum number of sets Q. which have relatively few literals in the expressions of their corresponding floor and ceiling functions. (It can be shown that a synthesized network always involves a number of FET's smaller than or equal to that of a network synthesized by the corresponding algorithm in [Liu 72] or [Liu 75] for the same function.) As mentioned, an algorithm such as this, i.e., without a 'backtracking' capability, cannot be expected to give G- minimal solutions with a minimum number of FET's as often as an algorithm having this capability. Although heuristic or enumerative methods could achieve better results in the selection of the 0. , the use of these more complex algorithms might tend to nullify the main advantages of the synthesis algorithms based on non- stratified (and also stratified) structures: simplicity and feasibility of hand calculation. Although the following Algorithm 4.1.2.2 (SNS) may seem at first relative- ly complicated, it is fairly simple in principle and, with use, can soon become easy to apply by hand without the need to refer to the detailed steps. This algorithm employs the BU-stratified structure (a similar algorithm can easily Even if such a procedure is given, it would not necessarily lead to an algorithm to synthesize 2-level, GF -minimal networks since: (1) The type of synthesis algorithms being discussed here, i.e., those based on Corollary h. 1.1.1, can produce only a subset of the possible 2-level, G-minimal networks. (2) Even a selection of Q. minimizing the number of literals in the floor and ceiling functions before factoring does not always correspond to the minimum number of literals possible after factoring. 118 be created employing the TD-stratified structure). Clusters, either true or false, of the BU-stratified structure are altered to produce floor and ceiling functions of fewer literals than in the original clusters. This can be seen to lead to synthesized networks of fewer FET's. Algorithm 4.1.2.2 Specific algorithm, based on a non-stratified structure, to synthesize a G-minimal, 2-level network of MOS cells for a given function f of n variables (SNS). f f f Step 1 Obtain the BU-stratified structure, (M n ,M, , . . . ,M p ), for function f by the use of Algorithm 4.1.1.1.1 (SS). Step 2 Decide whether the synthesis will be based on true clusters or false clusters. si:e P 3 If the synthesis is to be based on true clusters, set i = 2r + 1. If it is to be based on false clusters, set i = 2r + 2. Initially, sets Q^,Q , . . . ,Q 2 ^ are empty. Step h i = i - 2. If i < 0, go to Step 8. StepJ? Let ^ = m£ - (Q i+2 U Q ±+lf U ... U Qg r _ t ) where t = 1 if the synthesis is to be based on true clusters and t = if it is to be based on false clusters. ste P 6 Attempt to extend the 'ceiling' of cluster Q. . If the set of ceiling vectors of Q, ± is a subset of the set of ceiling vectors of M f , go to Step 7« Otherwise: (a) Attempt to select a ceiling vector, A, of Q. which is not a ceiling f vector of M. . l (b) If no such vector A exists, go to Step 7. Select a ceiling vector, B, of M? such that B > A. (Such a vector will always exist. ) 119 (d) Add to set Q i every vector C ft Q,. such that B > C > D for at least one floor vector D of Q,. Return to Step 6a. Step 7 Attempt to extend the 'floor' of cluster 0. . (a) Seek a vector, A £ Q,. , satisfying: (i) there exists a floor vector B of Q. such that A < B, and (ii) Q. U (c|c ^ Q. and A < C < D for at least one ceiling vector D of Q. ) is a cluster. (b) If no such vector A exists, go to Step k. (c) Otherwise, add to set Q. every vector C ft Q,. such that A < C < D for at least one ceiling vector D of Q,. . Return to Step 7a. Step 8 Let Q. ,...,Q,. be the resulting non-empty sets among Q n ,Q n ,..., J_ s Qp . Express f in terms of the ceiling and floor functions of the Q,. : i C f if synthesis based on , v , N I true clusters t Q s,l v '•• v0! s,p nP s,l ^ '" ^ ^ Sf a } = \ f if synthesis based on s I false clusters where: p. and q. are, respectively, the number of ceiling vectors and floor vectors of cluster Q. ; a. , v . . . v a. and 6. -. v ... v 6. are, 3 ± ' i^l i,Pj_ i;l i^ ' respectively, the ceiling and floor functions for cluster Q. . J i Step 9 Define u. as the complement of the floor function for cluster Q. if the synthesis is being based on true clusters. If the synthesis is °i being based on false clusters, define u. as the complement of the ceiling function for cluster Q. . Express u,,...,u , and f as follows: If the J i synthesis is being based on true clusters: 120 U l = \l - '•• - Pi, q . ■1 s s,l V . . . V s,q c f = (ct, _ ... ol vu. ) ... (a _ ... a \/ u ); 1,1 l,p, 1' s,l s,p o r y ' If the synthesis is being based on false clusters: 1 1,1 l,p. u = a ..... a s s,l s,q c f = u (P 1 1 v ... i,q 1 s> K s,l s ^ s Step 10 Let 9 = 1 if either: the synthesis is being based on true clusters and is a true vector; or the synthesis is being based on false clusters and 1 is a false vector. Let 0=0 otherwise. Then, the configura- tion of a G-minimal, 2-level network consisting of s + 1 - 6 MOS cells can be obtained directly from the s + 1 expressions resulting from Step 9- Each expression defines the output function and configuration of a corresponding cell of the network, with the possible exception of one expression for a u., 1 < i < s, which, when 0=1, is the constant or 1 and requires no corresponding cell. This algorithm was designed to synthesize G-minimal networks of a smaller or equal number of FET's than networks synthesized by corresponding algorithms (i.e., based on true vectors or based on false vectors) in [Liu 72] or [Liu 75]. Steps 6 and 7 insure that each chosen cluster has at most as many, and often . total literals in the expressions of its floor and ceiling functions 121 as the respective cluster of the BU-stratified structure. In turn, this means the synthesis of a G-minimal, 2-level network with generally fewer FET's. Example 4.1.2.3 Consider once again the function of Fig. 4.1.2.3 (Example 4.1.2.2). Step 1 of Algorithm 4.1.2.2 (SNS) gives the BU-stratified structure (note, 2r = 6): M^ = ((1010), (1000), (0010), (0000)} M^ = ((1001), (0101), (0100), (0001)} M^ = ((1110), (1011), (0111), (1100), (0110), (0011)} mJ = ((1101)} m? = (din)} Suppose in Step 2 it is decided to base the synthesis on true clusters. Thus, by Step 3, i = 7. Note that sets Q. , Q_, and Q^ are empty at this point (see row 1 of Table 4.1.2.1). By Step 4, i = 5. In Step 5, Q 5 = *£ = ((llll)} (row 2 of Table 4.1.2.1). Step 6 is skipped since the ceiling vector of Q, is the ceiling vector of M-. In Step 7a, selecting (0010) as vector A jt Q- satisfies both conditions i) and ii). Step 7c adds vectors (1110), (1011 ), (0111), (1010), (0110), (0011), and (0010) to set Q (row 3 of Table 4.1.2.1). Return- ing to Step 7a, no new vector A ^ Q_ can be found satisfying the conditions. Returning to Step 4, i = 3. By Step 5, (^ = M^ - Q 5 = ((I100)}(row 4 of Table 4.1.2.1). In Step 6a, vector A = (1100) is found to be a ceiling vector of 0- and not of M_. In Step 6c, only ceiling vector B = (1110) is found to have the relation B>A. Step 6d adds vector (1110) to set Q (row 5 of Table 4.1.2.1). Returning to Step 6a, the only ceiling vector, (1110), of 0^ is also ~ O o o o ^ •*/——. s~- s o o o o o o o o o /— * II H O II * — "»*_ o V •\ »\ H ■®L. ■Sl. •«L. "SL. "SL ^Sk o o o o o o o o H H N -— ** O O ^— ^ H O ^-^v — , •\ V-— ' s — ^ O H O H ~ *— V — o O o o O o *—n /— n o o o .-■ ^^ N H H H H H s • Sw' H H •v •\ •\ H O r— t ^ — s ^— ^ y — s. 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CJ M •H ^ PH O o H o r-i H O l+H cp M H o C3? M •s s ro •H (3? H •H •v (U LTN O C3? 03 ra +3 CQ CD •H CO -P •H • • oo W • CD OJ +3 • cd H o • •H J- T3 C QJ •H H PV U s O c3 -P X o w rjj > crj H • ^ CM O • H H • fi> -3- M 0) o H 0) crj > rH o rQ cd M aj ^3 < 123 f a ceiling vector of M,, so nothing more can be added to Q-, in Step 6. In Step 7 vector A = (1000) satisfies the two conditions of Step 7a. In Step 7c, vectors (1010) and (1000) are added to set Q (row 6 of Table 4.1.2.1). Returning to Step 7a, no new vector A )t Q can be found which satisfies the conditions. Re- turning to Step k, i = 1. By Step 5, 0^ = M^ - (0^ U Q^) = {(0000)} (row 7 of Table 4. 1.2.1). In Step 6a, vector A = (0000), a ceiling vector for Q , is found not to be a ceiling vector of M. . Since only one vector, (1010), of VL is a ceiling vector, it is selected as vector B in Step 6c. By Step 6d, vectors (1010), (1000), and (0010) are added to set Q (row 8 of Table 4.1.2.1). Return- ing to Step 6a, no additional vector A can be selected. In Step 'Ja, no vector A exists satisfying the conditions. Returning to Step 4, i = -1. By Step 8, Q,, , Q , and Q_ are the non-empty sets, and they lead to the following expression of f (refer to last row of Table 4. 1.2.1): By Step 9: u. = 1 = u 2 =x 1 U 3= X 3 f = ((X 2 v X^) ss U X )(X^ ss U 2 )(0 ss U 3 ) = ( x 2 v ^V^ v u 2 ) u 3» By Step 10, the corresponding network can be determined (see Fig. 4.1.2. 5) • By coincidence, the synthesized network is equivalent to that previously derived in Example 4.1.2.2 through the use of Algorithm 4.1.2.1 (GNS). The chosen true clusters are identical in both cases; however, this will not be true in general. It was already seen that this network is greatly improved over that derived based on true vectors of the BU-stratified structure (see Fig. 4.1.2.6). 124 4.2 Synthesis of G-Minimal, Multiple-Level Networks If a network to realize a given function or set of functions is not restricted to two levels, even fewer negative gates are required, in general (see Theorems 3«8 and 3»9)« Several new synthesis algorithms will be proposed in this section which produce G-minimal, multiple -level MOS networks for given functions. Section 4.2.1 will first discuss the synthesis algorithm of [Liu 72] for G-minimal, single -output, multiple level networks of MOS cells. Liu's algo- rithm is based on the floor functions of both true and false clusters (M. ) l composing the BU-stratified structure of a given function. Also in Section 4.2.1, it will be demonstrated that a corresponding synthesis algorithm can be developed based on ceiling functions of the clusters (WT ) of TD-stratified structures. Generally this new algorithm should produce results of comparable quality (in terms of numbers of FET's used) to those of the algorithms of [Liu 72], but for particular given functions the algorithm based on the TD-stratified structure can produce a better result (and vice versa for other functions). Additional new algorithms will then be discussed in Section 4.2.2 which can produce improved results (again, in terms of numbers of FET's). These algorithms first determine the (BU- or TD-) stratified structure of a given function. The clusters NL,M_ ,...,M or w£,wf,...,w£ form the basis for the 0' l 7 » 2r 0' 1 ' 2r selection of a new set of clusters called 'extended M. ' or 'extended WT ' , 1 1 ' respectively. Based upon the floor functions of the extended M. or the ceiling- functions of the extended WT, configurations of the cells in a G-minimal MOS network realizing the given function can be easily determined. The new algo- rithms obtain networks of fewer FET's than the corresponding algorithms of Sec- tion 4.2.1, while maintaining the ease of derivation of the cell configurations whi of the latter'. 125 4.2.1 Synthesis methods for multiple -level networks based on stratified structures and corresponding floor or ceiling functions The approach taken in [Liu 72] to the G-minimal synthesis problem is based on the same BU-stratified structure used in the synthesis algorithms for the 2-level-restriced case. In the multiple -level case, however, the synthesis involves an additional labelling procedure. Instead of assigning a label to each vertex of an n-cube as in Algorithm h. 1.2. 1.2 (MXL) or Algorithm 4.1.2.2.1 (MNL), this labelling assigns a label to each cluster M. of the stratified structure (all vertices involved in a single cluster implicitly receive the same label). Generally several different such labellings (corresponding to different network configurations) will exist, for a given function, which satisfy required conditions. Liu's synthesis method has the advantage that, once the BU-stratified structure and labelling have been determined, the detailed configuration of the corresponding network of MOS cells can almost immediately be obtained. At this point in other algorithms, significantly (in a relative sense) more effort is needed, in general, before arriving at the configurations of the MOS cells (the extent of this effort being dependent on the amount of acceptable redun- dancy). Furthermore, [Liu 72] shows (Theorems 4.2.1 and 4.2.2 of [Liu 72]) that only the special type of labelled n-cubes mentioned above (i.e., all f vertices in the same M. receiving the same label) need be considered when either a G-minimal or Gl-minimal network is desired. t f Actually, the floor functions of the M. are also needed, but these can be obtained quite easily during the determination of the BU-stratified structure as a by-product of the calculation. 126 For the development of new MOS network synthesis algorithms in this and the following section (4.2.2), Liu's synthesis algorithm will be presented after first giving certain necessary preliminary definitions (much of the ter- minology and notation is as given in [Liu 72]). The following definition (using a notation developed in [Lai 76]) will also be important for the discussion of Section r J. Definition 4.2.1.1 A negative function sequence of length R for function f of n variables, denoted by NFS (R,f) is an ordered set of R functions in C — ' J n ' n (i.e., functions of x ,...,x ), u..,...,u R , such that: (i) u is a negative function of x_,...,x ; (ii) u. is a negative function with respect to x , . . . ,x , u_,...,u. - for i = 2,. . . ,R; and (iii) u R = f. It can easily be seen that the NFS (R,f) represents the functions real- ized by the negative gates in the generalized form of a feed-forward network of R negative gates given in Fig. 2.11. Gate g. in Fig. 2.11 realizes function u. (or any negative completion) of NFS (R,f). Due to this correspondence, the problem of finding a G-minimal negative gate network is equivalent to the problem of finding an NFS (R,f) = (u , . . . ,u_, = f) such that R is minimized. n x R Let the notation R_ be used to denote the number of negative gates in a G- minimal network for a given function f and let NFS (R f .,f) denote a minimum negative function sequence for f . The following crucial theorem was first proved in [NTK 72]. This theorem provides the basis for multiple- level synthesis algorithms in [NTK 72], [Liu 72] (Liu uses a similar but independently derived theorem), and [Lai 76]. 127 Theorem 4.2.1.1 A sequence of functions, u. .....U-. in C is an NFS ' 1 R' n n (R,u ) if and only if the labelled n-cube with respect to U-,...,u_, i.e., R 1 R C (u , ...,u ), has no inverse edge, n 1 K Algorithm 4. 1.1. 2.1 (MNL) was proposed in [NTK 72] as a means of obtaining, for a given function f, a labelled n-cube, C (u , . . . ,iO such that: (i) u„ = f: n 1 K R (ii) C (u,, ...,u ) has no inverse edge; and (iii) the maximum bit length of the binary labels £(A;u,, . . . ,u R ), A € C , is minimized, i.e., R = R_. This is done by assigning the minimal possible label, i(A;u, , . . . ,u ) to each vertex A e C under conditions (i) and (ii). It is quite obvius that Algorithm MNL actually accomplishes this goal. An example of the n-cube labelling resulting from Algorithm MNL was shown in Fig. 4.1.1.2.2 for the function f of four variables given in Fig. 4.1.1.2.1. Note that while several inverse edges exist in the 4-cube of Fig. 4.1.1.2.1 (bold lines), none exist in Fig. 4.1.1.2.2. The NSF, (3,f) corresponds to the generalized network of three negative gates in Fig. 4.2.1.1(a). Fig. 4.2.1.1(b) shows one of the specific forms of a negative gate network corresponding to the NFS. (3>f) created by Algorithm MNL. To obtain specific forms, negative completions of the u. with respect to x , . . . ,x , u , ...,u. must be chosen. In this particular case, u and \i only have one negative completion each. For u (as expressed in Fig. 4.2.1.1(b)) one of several possible negative com- pletions with respect to x , x , x , x, , u , u~ was selected. Basically, the G-minimal synthesis algorithm of [NTK 72] consists of applying Algorithm MNL for the given function f and obtaining negative com- pletions of the u. of the NFS (R f .,f ) corresponding to the resultant labelled n-cube. (Continuing the preceding example, the algorithm of [NTK 72] would 128 (a) Generalized form of a negative gate network for f. (b) A negative gate network for f where: U l = X 1 u 2 = (x x k X 2 X ^ x )(x. . " V : U- u 3 = X 2 X 3 " X 1 X 2 X 1+ v X 1 X 3 X 1+ u. = f » 3_ _ 1 x rV c 3 [uTj u ? )(x x^ '•' u 1 )(x 1 ' u 1 )( x 1 ^7" ' • ; . • .1.1 -minimal, negative f r ate notworks based on minimal labelling /nthesis algorithm of [NTK 72 1 ) for function f of Fig. 'ul. 1.2.2. 129 obtain the network of MOS cells shown in Fig. 4.2.1.2.) As will be seen, Liu's synthesis algorithm effectively produces a labelled n-cube having no inverse edges. This labelling, however, is of the special type (corresponding to the BU-stratified structure) previously mentioned which allows the easy deriva- tion of expressions for the u. as negative functions of their predecessors. The derivation of corresponding expressions from the more general labelled n-cubes (without inverse edges) produced in the algorithm of [NTK 72], however, requires significantly more effort. Definition 4.2.1.2 Let (MI,M-. , . . . ,M p ) be the BU-stratified structure of a function f . A function u is called a stratified function of f if u has f the same value (0 or l) for every input vector in the same M., i = 0,1,..., 2r. The notation u(MT) denotes the value of u for the input vectors in M. . It should be recalled that the clusters, M , of the BU-stratified struc- ture are uniquely determined for a given function f . Definition 4.2.1.3 Let u n ,...,u_. be a set of stratified functions of f a function f . A stratified truth table with respect to f , denoted STT , with u,,...,u R is defined as the table in Fig. 4.2.1.3 where the entry in row M. and column u is u.(M.). If either or both of M_ and MI is empty, the correspond- ing row or rows may be deleted. Examples of STT 's are shown in Fig. 4.2.1.4. Definition 4.2 .1.4 Let u,,...,u be stratified functions of a function f. f The STT for u_ ,. . . ,u_ is called a realizable stratified truth table with _1_ ft _______________________________ — — . — f respect to f , denoted RSTT , if and only if u , ...,u is a negative function sequence of length R for f, NFS (R,f). 130 00 * bO O % OJ CH O s 43 -P •H fn O bO H cti >> 43 ^ CD N •H W 0) £ -P C >> : w H • W OJ H • H H 0) • o H ro j- o s • bO ^(M^) • • • V4r> « • • • • • • • • • • • < U^) u 2 (M^) • • • u R (M^) < n ± (M f ) V M } • • • V M 0> Fig. 1+.2.1.3 Stratified truth table based on BU-stratified structure. U l U 2 U 3 I s f < 1 «3 1 < 1 1 f 1 1 M f 1 1 f f (a) STT which is not an RSTT . Fig. U.2.1.U Examples of stratified truth tables u i U 2 u = f < 1 < 1 1 4 1 < 1 1 < 1 1 f f (b) STT which is not an RSTT . u i U 2 u 3 = f K 4 1 4 1 4 1 1 < 1 1 f f (c) STT which is an RSTT . Pir,. Jt.r'.Ut ( Cont i nued ) 133 f f f The STT given in Fig. 4. 2.1.U(a) is not an RSTT since u D = f. The STT K given in Fig. 4.2.1.4(b) is not an RSTT since the corresponding labelled n- cube must obviously have an inverse edge (consider two vertices A £ NL and a B € MI such that A > B). The STT given in Fig. 4.2.1.4(c) is an RSTT . It is shown in [Liu 72] and is fairly obvious from previous discussions in this paper (e.g., Theorem 4.2.1.1) and others (e.g., [NTK 72]) that: an f . f STT for u_ , . • . ,u_ is an RSTT if and only if u_= f and the binary label J. K K i(A;u..,...,u ) is greater than i(B;u. ,. . . ,u T3 ) for any pair of vertices A € MT, B £ MT ,, i = 0,1,..., 2r - 1 (i.e., the values of the rows of the STT viewed as binary numbers are ascending from the top to the bottom of the table). It f is also shown that an RSTT with only R- columns, u_ , . . . ,u , always exists for i J. Kp a function f (generally, more than one exists). Definition 4.2.1.5 Let u.(MT) be a '0' entry in an RSTT . Row M^ is said to be a blocking row of u.(M.) if k is the largest integer such that: (i) k < i; (ii) u^M^) = 1; and (iii) no I < j exists such that \in(m.) > u^(M, ,). If no integer k exists for which these three conditions are satisfied, f f blocking row of u.(M.) is defined to be the bottom row of the RSTT . Definition 4.2.1.6 Let u.(MT) be a '0' entry in an RSTT , and let row Mr be its blocking row. A product, u. ... u. , is said to be a prohibiting * x J l J s product of u.(MT) if : (i) j 1 < ... < j g < j; (ii) u (Mf) = ... =U (lA f ) = 1; J l J s '< u x u 2 u 3 u k 23h M M r < 1 !■'_ m; i o u (M ). Its blocking -* f row is M . Its prohibiting product is 1. (M ). Its blocking 3 V 3 row is M-, . Its prohibiting product is u . < < u. (M n ). Its blocking f row is M . Its prohibiting products are: u -i u o an( ^ u 2 u . Fig. U.2.1.5 An RSTT for a function f illustrating blocking rows and prohibiting products. 135 f (iii) for each i > k such that u.(MJ = 1, there is at e (j,,...,J } such that u (M^) = 0; and (iv) if any of u. , ...,u. is deleted from the product, condition (iii) J l 3 s is no longer satisfied. If column u. has no '1' entry above u.(NL ), then the prohibiting product J J k-± of u.(M.) is defined to be the constant function 1. J i Choosing the blocking row and a prohibiting product for a '0' entry of an f RSTT is important in Liu's generation of an expression of each u. as a negative function of x , ...,x , u_,...,u. , , i = 1,.. ,,R. Note that while a '0' entry has a unique blocking row, it may have more than one distinct prohibiting product. Consider the '0' entry u^N?) in the RSTT f in Fig. 4.2.1.5- The blocking row for u (M f ) is row l£ since k = 3 satisfies Definition lj-,2.1.5. Since there is no '1' entry above u 1 (m£), its prohibiting product is the constant function f f 1 by Definition 4.2.1.6. Now consider the '0* entry u (M 3 ) in the same RSTT . Row n£ can not be the blocking row of u~(m;) since there exists an I = 2 < 3 -P -P for which u^(M^) > Ug(M^). Its blocking row is row M 1 since u^Mq) = 1, and no I < 3 exists such that Ug(M?) > Ug(Mg). The choice of u 2 as the prohibiting product of u (M?) can be seen to satisfy the conditions of Definition 4.2.1.6. Next, consider the '0' entry u^(m£). Its blocking row must be M Q since no lower rows exist. Its prohibiting product may be either u^ or u^. Product u u u violates condition (iv) of Definition k.2.1.6, while the remaining pos- sibilities violate condition (iii). Based on these definitions, the synthesis algorithm of [Liu 72] for G- minimal networks can now be given. 136 Algorithm 4,2.1.1 Let f be a given function of n variables. f f f f Step 1 Obtain the BU-stratified structure (M n ,M , . . . ,M p ). Let £. f represent the floor function of cluster M.. Step 2 Construct an RSTT f for u , ...,u R = f , R = riog 2 (D f (1,0) + 1)1 + 1 as follows: (a) Set entry u (M.), < i < 2r, to 1 if i is an odd integer and to 0, l\f> •■■ otherwise. Omit entries and rows for M n and W if they are empty. (b) Assign or 1 to each remaining entry u.(M.), j f R such that: R f R f -1 - R R -t f 2 2 \(\) < E 1 2 u (C ), k = l,2,...,2r t =1 t =1 (i.e., such that if each row of the table is considered as a binary number, the value of each row will be greater than that of the row above ) . Step Obtain an expression for each u. of u , ...,u as a negative function of x n ,...,x , u n ,...,u. _ as follows: 1' xv l 7 ' 1-1 (a) Set j = 0. (b) Set j= j + 1. If j > R , go to Step k. Otherwise, let h be the constant function initially, and let I, initially, be the set of all indices i such that u.(M.) =0. Go to substep (c). J -'- (c) If I = 0, set u. = h and go to substep (b). Otherwise, select the f smallest index i remaining in set I. Let row M be the blocking row K. of u.(MT). Then form a new function h: J i f t h<^= h v L u. . . . u. , k J l J s The arrow indicates that the value of the variable on the left is to be replaced by the current value of the right-hand side. 137 where u. ... u. is a prohibiting product of u.(M.). If the prohibiting product is the constant function 1, set u. = h and J return to substep (b); otherwise, continue to substep (d). (d) If index 1 e I exists such that u (M*) = ... =u. (M?) = 1, J l l J s l set I«^ I - {i}. Repeat this step until no such I remains in I. Return to substep (c). Step k Using the irredundant disjunctive forms of the floor functions, f _ C.'s, construct an MOS cell, g., from the expression of each u., j = 1,...,R , J J J- in the obvious way (i.e., series connections of FET's for conjunctions, parallel connections of FET's for disjunctions). Example U.2.1.1 Suppose a G-minimal network is desired for the following function of seven variables: f = X^ V X^ v X^X 7 v X X X 3 X 7 v, XjX^X^Xj V X 1 X 2 X 3 X i+ X 7 ss \ X 2 V^7 v x 2^3 x l^5 x 7 v x "i x 2 x l+ x 5 x 6 x 7 v X 2 X 3 X 1+ X 5 X 6 X 7 v X 1 X 2 X 3 X U X 5 X 6 X 7 * Following Algorithm 4.2.1.1, in Step 1 it is determined that the BU- stratified f f f structure of f consists of eight non-empty clusers, M n ,NL ,. . . ,M_. Floor functions, expressed in irredundant disjunctive form are found to be: This function was given in an example (Example h.k.k) in [Liu 72]. Floor functions of the clusters of the BU-stratified structure were derived, and a network was synthesized. However, the derived floor functions are not consist- ent with the expression given for f, probably due to typographical errors. In any case, the result given here is based on the function expression in [Liu 72] and will therefore differ from the result given in [Liu 72] (based on the floor functions) even though the same synthesis algorithm is being used. 138 ^ = x x v x v x v x 2 x ]4 C 2 = x ± x h v x^ v x^ v x 2 x u x 5 C 3 = x x x 2 x 4 v x 2 x 3 x^ v x 2 x 4 x ? s, x 3 x^x 7 ^ = X 1 X 2 X 1 + X 5 v x l x 3 x li x 7 v X 2 X 3 X U X 5 v X 2 X 1+ X 5 X T ^5 = X 1 X 2 X 3 X 4 X 5 v X 2 X 3 X 4 X 5 X T v X 2 X 1+ X 5 X 6 X 7 ^6 " x i x 2 x 3 x 4 x 5 x 7 it. h - x i x 2 x 3 x i| x 5 x 6 x 7 f Step 2 of the algorithm constructs an RSTT . From the BU-stratified structure, D (1,0) = k. Thus R_ = riog (h + 1)1 +1=4 columns are required in the RSTT . Fig. 4.2.1.5 shows one possible RSTT which can be selected during Step 2 (others also exist). Expressions for the u. are derived in Step 3» One set of expressions consistent with the selection procedure in Step 3 is: u i = "3 u 2 = ^ V $* U3 = ^U 2 s, ^ u 4 = ^o u l u 3 v ^ U 2 v ^6 U 3 Step h of the algorithm defines the configurations of the MOS cells of the synthesized network. First, the irredundant disjunctive forms of the floor functions are substituted into the expressions of the u.: 139 u l = X 1 X 2 X U v X 2 X 3% v x 2 x i+ x 7 v X 3 X 1+ X 7 u 2 = (x lXl| n, x 3 x u v x u x ? v x 2 x j4 x 5 )u 1 v x 1 x 2 x 3 x 1+ x 5 X 2 X 3 X 4 X 5 X 7 v x 2 x i+ x 5 x 6 x 7 U 3 = (X x n, X n, X ? n/ X^j^JUg v X-jX^X^XgX u^ = u x u 3 ~ ( x ! x 2 x lf x 5 v x l x 3 x i+ x 7 v X 2 X 3 X ^ X 5 v X 2 X 4 X 5 X 7' U 2 (x l x 2 x 3 x i+ x 5 x 7 )u 3* From these expressions the network configuration, shown here in Fig. 4.2.1.6, can be directly obtained. The result is a G-minimal network. Factoring the expressions for the u. can reduce the number of driver FET's in the network by approximately 37% in this case. [Liu 72] proves that this algorithm always yields a G-minimal network for a given, completely specified function. For given, incompletely specified functions, G-minimal networks can also be obtained by ignoring unspecified vectors during the synthesis. If Algorithm 4.1.1.1.2(MXL) is used to obtain the BU-stratified structure, unspecified vectors will automatically be speci- fied during the labelling process, and thus one need not give any special consideration to incompletely specified functions. A similar synthesis of G-minimal networks can be carried out based on the TD-stratified structure for a given function f. Before presenting an algorithm to accomplish this synthesis, a few definitions, paralleling those for the BU- stratified structure case, must be given. Stratified functions of f with respect to the TD-stratified structure are simply defined by substituting 'WT' for every occurrence of 'M.' in Definition 4.2.1.2. For the TD-stratified structure case, a stratified truth table with Ih-0 c •H «H C • O ra •H - -P EH o H C (JH 3 Ch £h 0) 0) > 43 -H P H T3 ^1 O VQ 5 CQ rQ -P w 13 -H Kl isi C ■H O w o (D ^ ^ -P 5h £§ CO -p m a h o £ : P> H cp . C H H OJ ctf • 6-=r •H C 0) •H H S ft I B t5 cd X < H VD H OJ -=f bp ■H Pn 141 respect to f (corresponding to Definition 4.2.1.3) is defined as the table in Fig. 4.2.1.7. RSTT 's (Definition 4.2.1.4) are defined for both BU- and TD-stratified structures. f Blocking rows and prohibiting products are also defined for RSTT 's based on TD-stratified structures. In this case, however, the definitions are for ' 1' entries rather than for '0' entries: Definition 4.2.1.7 Let u.(W. ) be a 'l 1 entry in an RSTT . Row WT is J 1 K said to be a blocking row of u.(WT) if k is the largest integer such that: (i) k < i; (ii) u (w£ -;L ) = 0; and (iii) no I < j exists such that u*(W7) < ^(wf ). If there is no k satisfying these three conditions, the blocking row of u.(WT) f is defined to be the top row of the RSTT . Definition 4.2.1.8 Let u.(WT) be a '1' entry in an RSTT , and let row WT be its blocking row. A product, u. ... u. is said to be a prohibiting product of u.(WT) if: '1 .(tf) if: (i) $ 1 < ... < J s < j; (ii) u (wf) = ... = u. (wf) = 0; 1 J s (iii) for each I > k such that u.(Wg) = 0, there is at e (j ,...,j } such that u (Wn) = 1; and (iv) if any of u. ,...,u. is deleted from the product, condition (iii) J l J s is no longer satisfied. If column u. has no '0' entry below u.(wf ), then the prohibiting product of u.(WT) is defined to be the constant function 1. J 1 142 u i u 2 . . U R 4 ^(ng) u 2 (W^) . . V^ < u^) u 2 (W^) . , u R (V^) 4 2r u l (w 2r } "a^r 5 u R <4) Fig. 14.2.1.7 Stratified truth table based on TD-stratified structure. 143 Based on the preceding definitions, a new synthesis algorithm for G- minimal, MOS-cell networks can be given which is the counterpart of Algorithm 4.2.1.1 based on the BU-stratified structure. Since the synthesis based on TD-stratified structures so closely parallels the case of the synthesis, developed in [Liu 72], based on the BU-stratified structure, the proof of its validity will be omitted, being easily obtainable by relatively simple modifi- cations of the proof of the validity of Algorithm 4.2.1.1 given in [Liu 72]. Algorithm 4.2.1.2 Let f be a given function of n variables. Step 1 Obtain the TD-stratified structure (wt,VL, . . . ,wt ). Let GC represent the ceiling function of cluster WT . Step (Same as Step 2 of Algorithm 4.2.1.1 except WT is to be substituted for M..) l Step ; Obtain an expression for each u. of u^,...,u as a negative function of x n ,...,x , u_.....u. , as follows: 1' ' n' 1' ' l-l (a) Set j = 0. (b) Set j = j + 1. If j > R f , go to Step 4. Otherwise, let h be the constant function initially, and let I, initially, be the set of all indices i such that u.(WT) = 1. Go to substep (c). (c) If I = 0, set u. = h and go to substep (b). Otherwise, select the J smallest index i remaining in set I. Let row WT be the blocking row of u.(WT). Then, form a new function h: f- - h C > B. Suppose such a C does exist for some pair A,B. It will be shown that this -p f -p supposition always leads to a contradiction. Since C ^ M. , C £ M. also. By f ' f ' f f ' the definition of M. and the fact that f. ~> £., t. (D) = 1 for every vector D l l — s i' l f ' f ' f f in M. . Hence, £. (B) = 1, and, consequently, £. (C) = 1 since £. is a f f ' positive function and C > B. If £.(c) = also, C would be a member of M. by f f Definition 4.2.2.2 (a contradiction). So assume £.(C) =1. Since £. can be expressed as the disjunction of p-terms corresponding to the floor vectors of MT (by Definition 4.1.1.4), there must exist a floor vector E of M. such that f f E < C (E = C can not occur since C ft M. ). However, E < C < A where E, A € M. f f and C ft M. is a contradiction of the fact that M. is a cluster. Therefore, no r i l ' •p such C ft 14. can exist, and the theorem statement is correct. Q.E.D. Definition 4.2.2.3 The extende d range of an EFF, C f ' , of a cluster M f — • -,_ x of the BU-stratified structure for a function f is defined to be cluster M f 3 where j is the smallest index such that there exists a vector A € M . satisfying 149 f ' f £. (A) =1. A vector B and the cluster, M. , to which it belongs are said to f ' f ' be within the extended range of an EFF , £. , if and only if ^ (B) = 1 and k < i. f Consider again the M. and EFF's of the example illustrated in Fig. 4.2.2.1, MT is in the extended range of £ . Vector (0011) is in the extended range f ' f f ' of £. , and cluster NL is the extended range of £ . Although not seen in this f f example, it is possible that clusters M. and M. can be in the extended range f ' f of some £. "while a M*, j > & > k, is not. f f Theorem 4.2.2.3 If M. and M. are any two clusters of the BU-stratified i i j ^ f structure for a function f such that M. is in the extended range of an EFF, £. , of MT, then i - j is an even integer. Proof Consider any vector A e MT which is in the extended range of £.. j f f £.(A) = 0, since £.(A) = 1 would imply that A > B for some floor vector B of MT, violating Property II of the BU-stratified structure. By definition of f ' f ' being in the extended range of an EFF, £. (A) = 1. Thus, A e M. , the extended MT. Since MT c M. and M. is a cluster, f(A) = f (M. ). Considering f(A) = f(MT) also, M. and MT must both be true clusters or both be false clusters of f, i.e., i - j must be an even integer. Q.E.p. As seen by the above example, expressions for EFF's may have significant- ly fewer literals than expressions for the corresponding floor functions (it is also possible that they can have more, but such EFF's will not be selected by the methods given in this section). Since in Algoritlun 4.2.1.1 each literal corresponds to an FET of the synthesized network, the ability to substitute 150 EFF's for floor functions in the algorithm can lead to substantial reductions in the numbers of FET's in the synthesized networks (later examples will show reductions of as much as 29/0). In general, EFF's can not be freely substituted for floor functions in the expressions for the u. developed in Algorithm 4.2.1.1 without causing the synthesized network to realize some function other than the intended one. Conditions will be given under which a particular EFF can be substituted for the corresponding floor function. Actually, however, such a substitution can be made under much wider circumstances which are significantly more complex to state and to check. Since empirical evidence seems to suggest that situa- tions in which EFF's can not be used exclusively in place of floor functions are infrequent, it may be more practical to actually test whether the sub- stitution results in as incorrect network output function rather than to at- tempt to check whether one of several complex conditions exists. A simple method to accomplish this test will be given later and demonstrated. Theorem 4.2.2.4 Consider an expression for a function u. developed by J Step 3 of Algorithm 4.2.1.1 during the synthesis of a network for a given f ' f function f. An EFF t. with extended range M. _ can be substituted for floor s i ° i-2q f f ' function £., < i < 2r, note that not all t. need be substituted in this expression if, for each t = l,2,...,q, either: (1) M7 „, is not in the extended range of f. ; (2) u.(r/f_ 2t ) = 0; or f f (3) if the prohibiting product for row M. is u. u. , u. (M. „ , ) = 1 J l 3 s J k 1_ ^ for at least one k, i < k < s. Proof The expression developed by Algorithm 4.2.1.1 for function u. be written as: 151 f where there is no occurrence of £. in the expression Y (it is clear from f Steps 3c and 3d of the algorithm that no £. can appear twice in the expression for u . ) . f f » £. and £. can both be represented by disjunctions of minterms correspond- f • f f ing to their respective true vectors. Since £. 3 L; every minterm of £. f ' f f ' is a minterm of £. . So replacing £. by £. in expression (4.1) for u. is equivalent to writing: _ Y s, u. . .. U. Q. v U. . . . u. y. sy ... v u. . . . u. y (k.2) J l V 1 J l J s 1 J l J s p l ; where r« represents the minterm corresponding to vector A* for which ^.(Aj = f ' and £. (A«) = 1. It will be shown that (4.2) is an alternate expression for u. under the conditions of the theorem. Obviously, the equivalence of expressions (4.1) and (4.2) can only be in doubt for vectors of the set {A,,..., A }, i.e., vectors in the extended f f f f range of £. , i.e., certain vectors in clusters M. ? ,M. _,,... ,M._ 2 . Thus, it is sufficient to show that (4.1) and (4.2) have identical values for each f vector in M. ^., t = l,2,...,q, when at least one of the three conditions of the theorem statement are met. Expressions (4.1) and (4.2) clearly have identical values for each vector f £ f ' in MT _. , 1 < t < q, if M. ^ is not in the extended range of t. (condition i-2t' - H ' i-2t 1 (l) of the theorem). f ' Now consider each vector An, I = l,...,p, in the extended range of {;. . Let A» € MT and assume either condition (2) or (3) is met by M. ~. . If condition (2) is true for MT ^, , then u.(A«) = 0. Hence, Y v u . .. u £ = 1 for vector A» (by expression (4.1)), and expression (4.2) also has the value 152 regardless of the values of its other terms (e.g., u. ... u. y ). If f J l °s l condition (3) is true for M. p , , u. (A*) = must hold for at least cne k, J k 1 < k < s. Thus, also under this condition, expressions (4.1) and (4.2) clearly have identical values for every vector in V . Therefore, if at least one on the three conditions of the theorem is met f f f ' by every M. „, , t = l,2,...,q_, £. can always be replaced by £. in an expression X"* C—Tj 1 1 for u. as developed by Algorithm 4.2.1.1. Clearly the same argument can be f ' f made for substitutions of t. for c. for additional i. Q.E.D. Corollary 4.2.2.1 An extended floor function t. can be substituted f for each corresponding floor function t. appearing in the expression for u l K„ (i.e., the function to be realized by the output gate or cell) developed by Step 3 of Algorithm 4.2.1.1 during the synthesis of a G-minimal network for a given function f . f f f f Proof Since only t. corresponding to M. for which \i (M. ) = f (M. ) = can appear in the expression for u , every cluster in the extended range of f f ' £. must be a false cluster for f. Therefore, condition (l) or (2) of Theorem f f 4.2.2.4 is satisfied for each cluster M. „, , t = l,2,...,q, where M. „ is i-2t' ' ' ' ' i-2q f ' the extended range of (. . Q.E.D. Theorem 4.2.2.4 permits the use of EFF's under conditons which maintain the same functions u., j = 1,...,R , constructed by Algorithm 4.2.1.1 for a given function f. Actually, however, functions u. for j = 1,...,R - 1 may be J changed as long as u. remains equal to f. This may seem difficult since u_, is dependent on u, . ...,u_ n (as well as x.,...,x ), but it has been found \ ' ' R f -1 1' n ' 153 (by empirical evidence) that the changes in the functions u., j = 1,...,R, - 1, caused by substituting EFF's for floor functions in the expressions (as de- rived by Algorithm 4. 2.1.1) for the u. often do not induce changes in u R.p (i.e., do not cause the synthesized network to realize an incorrect function). Hence, Theorem 4.2.2.4 and Corollary 4.2.2.1 cover only a portion of the cases in which EFF's can be used. Example 4.2.2.1 Consider the synthesis described in Example 4.2.1.1 for a function f of four variables. The RSTT selected in Step 2 of Algorithm 4.2.1.1 is shown in Fig. 4.2.1.5, and the expressions for u , ...,u, chosen in Step 3 are: U l = h „f ,f u 2 = ^ v (; 5 f f u 3 = ^l u 2 v ^7 u 4 = ^0 u l u 3 v ^4 U 2 v ^6 U 3 f Suppose. the EFF's shown in Table 4.2.2.1 are chosen for the clusters, M., of the BU-stratified structure of f. The difference between the number of literals in the expression for an EFF and that in the expression for the corresponding floor function (see Table 4.2.2.1) is exactly the savings, in terms of numbers of FET's, which can be achieved by each replacement of an occurrence of the floor function by the corresponding EFF in the expressions for u. determined f f f f in Step 3 of the algorithm. In this case, only £. for u and £_, t^, £,- for u, are found to satisfy the conditions of Theorem 4.2.2.4 for replacement by f ' f ' their respective EFF's. However, since only £. and t^ of Table 4.2.2.1 are PEFF's only they can contribute to a reduction of the number of FET's in the synthesized network: 11 FET, in this case. Choosing alternate RSTT 's can sometimes improve the number of floor a •H CD

a> m Cm ,a Q)

X ir\ X no *OJ OJ x X m X > LT\ X J" X OJ X c- OJ m OJ OJ t~- X _d- X > -cj- LiA X X OJ -=t- X X > > fv. -=t- IT— X X en > X > on X > H X X H OJ OJ CD H ■3 *_n x_n »ji x-n j^yi

B). H«^=H U (clc € V . B£-i > • • • , ^ be the set of EFF's proposed for substitution, in f f f place of occurrences of f „,£_,..., £ ? , respectively, into the expression U., j = l,...,R f , developed in Step 3 of Algorithm 4.2.1.1. J Step 1 Prepare a blank truth table of the following type (see Fig. 4.2.2.3): (a) For each cluster M. , i = 0,1,..., 2r, determined to be within the f ' f ' extended range of EFF's L ,...,£, , create a group of one or more adjacent 1 P t f rows of the truth table (call this group rows of M. one row corresponding P i .X ~ „f ' „ „ „f * „ ..f to each non-empty set among the 2 sets: M. fl MT fl , . . fl M7 fl ML ; 1 "p. -l p. *i l f f f ""f f f ~f f f f* M i nM k n --- ni \ n \ ;M.n^ n . . . n m£ nr ; m. n m£ n i p i -i p t i p t -i Pi i ... nc n mj" ; . . . ; m: n m£ n . . . n m£ n ml^ ; m ± n mjj. n...n p r i Pi i Pi" 1 Pi i ">'» ~f ~f f ML" fl ML" ; where MT denoted the set V - ML. p. -1 p. l l (b) For each function u., j = l,...,R f , for which an expression has been J determined in Step 3 of Algorithm 4.2.1.1, create a column of the truth table. Let e denote the entry at the intersection of row i and column u . ij d Step . Determine the entries of the truth table. (a) j = 0. (b) j=j+l. If j > R f , go to Step 3- (c) For expression u., determine the entries of column u. as follows. J Consider each term Ug . . . Uj jj in the expression: For each row k among (i) all rows of M f and above and (ii) those rows of M^ and below representing 159 f vectors in the extended range of £ (i.e., rows corresponding to non-empty f ' sets in the intersection of M. with other clusters and extended clusters), set e k . = if and only if e^ = ... = e^ = 1. (d) For all remaining blank entries in column u. , set e . = 1. J kj Step , EFF's may completely- replace floor functions in the expressions developed in Step 3 of Algorithm 4.2.1.1 without affecting the output function of the synthesized network if and only if, in column u , all entries for rows f f f of M ? ., i = 0,1,..., r, are and all entries for rows of M . ., i = l,2,...,r, are 1. It is simple to see the validity of this algorithm when it is realized that the calculated truth table is just a 'condensed' truth table for the functions realized by the gates (cells) of the synthesized network resulting from Algorithm 4.2.1.1 after substituting EFF's for floor functions. If the condition in Step 3 of Algorithm TFEFF is not met, it implies that the net- work will have the incorrect output for a true vector of function f or the incorrect output 1 for a false vector of f. xample 4.2.2.2 Reconsider the synthesis of a G-minimal network to realize the seven-variable function given in Example 4.2.1.1. Let the set of f ' f ' EFF's , £_ ,...," , in Table 4.2.2.1 be proposed replacements for the floor f f - — functions, ? ,...,f , in the expressions for u , . . . ,u, developed in Example 4.2.1.1: .f U 1^3 V U 2 = ^2 U 1 >f ,f U 3 = ^ s, S ? % = ^o u l u 3 v ^4 U 2 v 4 U 3* i6o rows of M rows of M 2r f 2r-l rows of M 2r-2 rows of M f 2r-3 rows of f M 2r-^ rows of 4 r > r v U l U 2 ' ' ' U R f M 2 2r M f 2r-l f f ' 2r-2 2r f ~f ' 2r-2 2r m^ n m 2r-3 2r-l ^r-3 n C-l 4r-k n M 2r n 41-2 m i n yr n m 2v-k " 2r " u 2r-2 f ~f*' f" M 2r-lt " M 2r " «4r-2 4rJt " M 2r n C-2 • • • • • • m^ n m£' n ... n m^' 2r 2 • • • m£ n m£ n ... n m£' 2r 2 r'ig. U.2.2.3 Generalized truth table constructed by Algorithm 1+.2.2.2 (TFEFF), Rows corresponding to empty sets will be omitted in the actual truth table. 161 Use Algorithm 4.2.2.2 (TFEFF ) to test the feasibility of the proposed substitution. The truth table shown in Fig. 4.2.2.4 is constructed in ac- cordance with the algorithm. In Step 1, it is found that: vectors ( 0101111 ), (0111111), (1101111) of MZ are in m£ ; vectors ( 1011001), (1011011), (1011101), (1011111), (1111001), (1111011) of mJ are in M^ ; vectors (0101100), (0101110 ) of m£ are in mJ' ; vectors (0100111), (0110111), (1100111), ( 1110111 ) of M^ are in m£' fl M?' fl m£'; vectors (1110100), (1110101), ( 1110110 ) of f/ are in f/'fl m£' fl m£'; vector f f ' ~f ' ~"f ' (0010011 ) and many others of M are in M DM fl M . Also each cluster has at least one vector not in the extended range of an EFF of another cluster. This determines the 15 rows in 8 groups shown in the figure. There is one column for each of the four functions u , ...,u, . Step 2 determines the entries of the truth table as shown in the figure. Finally, the condition in Step 3 of the algorithm is seen to be satisfied by the truth table, allowing the complete replacement of the floor functions by the EFF's: U l = h ,f« ,r U 2 = *2 U l v ^ - f ' f ' u 3 = i ± u 2 v C 7 - f f f u 4 = *o u l u 3 " ^4 u 2 v K 6 u 3* Continuing the synthesis of a G-minimal network with these expressions, Step 4 of Algorithm 4.2.1.1 obtains: u l = x l x 2 v X 2 X 3 v X 2 X 7 v X 3 X 7 u 2 = (x^ ^ x 3 x u v x u x 5 - x^y^ - ^2 X 3 X 5 - V3V7 - X 2 X 5 X 6 X 7 162 U^ = U-jU^ v (X^X v X^^^X )U 2 v X X X X^X U From these expressions, the network configuration shown in Fig. 4.2.2.5 is obtained. The synthesized network consists of four cells and 54 driver FET's. This represents a 29$ reduction in the number of driver FET's compared to the previous result obtained without the use of EFF's (see Fig. 4.2.1.6). Of course, the expressions defining the network configurations can be factored to improve both results, but there will still be 17$ fewer driver FET's re- quired for the design using EFF's (an additional consideration is that expres- sions containing the simpler EFF's are easier- to factor). Concepts were developed in this section for the improvement of the results obtained by Algorithm 4.2.1.1 which is based on BU-stratified structures. Similarly, concepts of extended ceiling functions, extended WT's, etc., can be developed for TD-stratified structures and thus enable a corresponding improvement of the results obtained by Algorithm 4.2.1.2. 163 u i U 2 U 3 \ ■4 1 4 1 f f • m c n m„ 5 r 1 f ~f r m c n mz 5 r 1 1 mJ n m^' 1 mJ n^' 1 3 1 1 m^ n m£' 1 1 f ~"f • m 2 n m^ 1 1 m? n m£' n m?' 13 5 f n mi 1 m? n m?' n m£ ~f ' n m 1 1 m? n m£' n re 13 5 n m£' 1 1 n m£' 1 1 1 m£ n m£' 1 1 m£ n m^' 1 1 1 Fig. 4.2.2.4 Truth table constructed by Algorithm 4.2.2.2 (TFEFF) for Example 4.2.2.2. 164 O ^ CD O T3 x: c CD H « H h CM • PL, ^ H OJ ft • &OJ X OJ H • J" O S O •H O -P •H o c<3 LT\ OJ OJ J- P-H 165 5. TRANSFORMATIONS BASED ON CONFIGURATION CONSIDERATIONS TO CONTROL MOS CELL COMPLEXITIES While many MOS network synthesis procedures in the literature produce 'minimal' (e.g., [3M 71], [Iba 71], [NTK 72], [Liu 72], [Shi 72], [Lai 76], [Yam 76]) or * irredundant ' (e.g., [Pai 73], [Lai 76], [Yam 76]) networks, the MOS cells of the synthesized networks may frequently be too large for practical implementation. Transient response of a cell or cell layout area, or both, may be unacceptable due to an excessive number of FET's connected in series or parallel in the cell's driver. Although at least one paper, [Liu 72], attempts to deal with this problem (see Liu's scheme (2), page 155, and Algorithm 5.h.l, p. ikk, of [Liu 72]), the proposed methods - one of which maintains cell minimality - are not design- ed to meet any specific limitations on the number of FET's in series or parallel in a cell's driver. Thus, after synthesis, the generated network may still be inappropriate for practical implementation. This section will offer relatively simple transformations which may be performed on MOS networks, taking into consideration a network's configuration only. These may be used to render the networks synthesized by more sophisticat- ed methods into practicable configurations. Or, they can simply be used to 'massage' any MOS design in an attempt to satisfy some desired creteria which might be difficult or inconvenient to obtain by computer programming. Since the primary reason for presenting these transformations is their utility in obtaining practical networks, extensions to more powerful versions involving the consideration of more complex factors (e.g., the functions realized by the cells) will be avoided so that the transformations themselves 166 do not become impractical. Computer program implementations, however, could probably benefit by employing more sophisticated extensions of these trans- format ions . Furthermore, a discussion of a systematic application of the transformations proposed in this section will be omitted since the approach taken is strongly dependent on the result sought, and, also, any general approach which may be specified would likely not yield the best results in many cases. The transformations to be presented are divided into the following five classes: logic insertion/extraction, logic duplication/combination, logic integration/distribution, redundant logic addition/deletion, logic factorization/defactorization, to be discussed in Sections 5.1 through 5*5, respectively. The last of these classes consists of strictly intracell trans- formations. The next-to-last class, redundant logic addition/deletion, is also made up of intracell transformations, but these are based partly on considerations of connections outside the transformed cell. The reason for class names being of the form 'logic P/q' is that all of the transformations are presented in complementary pairs - transformation in one direction being designated ' P', and in the other, 'Q'. To facilitate the illustration of transformations in the next several sections, let the following symbolic conventions be established: A figure such as Fig. 5.1 should be understood to represent an MOS cell with an unspe- cified or arbitrary driver. In general, let the symbol in Fig. 5.2 represent any two-terminal (terminals labelled a and b in this example) network of FET's. Fig. 5*3 is an example of a partially specified driver and set of inputs. It is to be understood that the specified portion is only connected to the remainder of the driver through terminals a and b. 167 The following definitions will also be necessary for subsequent discussion. Definition 5.1 The S -deletion of a two-terminal subnetwork of FET's from the driver of an MOS cell is the replacement of this subnetwork by a short- circuit (i.e., a direct connection) between its two terminals. The O-deletion of a two-terminal subnetwork of FET's from the driver of an MOS cell is the replacement of this subnetwork by an open-circuit (i.e., no connection) between its two terminals. Fig. ^.h gives examples of S-deletion and O-deletion. Fig. 5»M a ) shows an MOS cell with a two-terminal subnetwork of FET's encircled. The S-deletion of this subnetwork results in Fig. 5.k.(b). The O-deletion gives the MOS cell of Fig. 5.Mc). Definition 5.2 The S-addition of a two-terminal subnetwork of FET's to the driver of an MOS cell is the replacement of a short-circuit (i.e., a direct connection) between two terminals by this subnetwork. The O-addition of a two-terminal subnetwork of FET's to the driver of an MOS cell is the connection of this subnetwork between any two existing terminals in the driver. Examples of S-addition and O-addition are given in Fig. 5«5« The original MOS cell and two-terminal subnetwork of FET's to be added are shown in Fig. 5.5(a). One possible S-addition of the subnetwork to the cell's driver is shown in Fig. 5.5(b); one possible O-addition is given in Fig. 5«5(c)(S- and O-additions may also be made in several other locations in this MOS cell). While the presentation in this section will generally be made with series - parallel FET networks in mind, the two preceding definitions also apply to 168 Fig. 5.1 MOS cell with unspecified or arbitrary driver. Fig. 5.2 Symbol for unspecified or arbitrary FET subnetwork. output from another cell Fig« 5»3 MOS cell with partially specified driver. 169 VT ■-vH I- w a ^ o *-" P (D O w o pq Tr ->H M o o a o •H ■P •H

O P o3 S >J C 0) JH •H p O bO I > •MOP SH £ . . (It is also possible that g. may control FET's in the driver of g. other than the one shown, but any such FET's are actually redundant and could be eliminated by transformations described in Section 5-5.) Non-output cell g. (g*. in N' ) is an input only to cells g, ,..., g, , and it may control one or more FET's in each of these cells. Finally, cell g^^ in N* may or or may not exist (a fact represented by the encircling dashed line in Fig. 5.1.1) depending on whether or not it has outputs to cells other than cell g, of IT. J 172 SUBNETWORK N Logic insertion: Transformation INS (a) r L V A Logic extraction: Transformation EXT (a) SUBNETWORK . v ir;. y.1.1 First pair of logic insertion/extraction transformations: INS (a) and EXT (a). 173 The symbols a and(3 in Fig. 5.1.1 indicate two-terminal networks of FET's. It is easily seen that for N or N' to satisfy the loop-free condition, FET's controlled by g, , . . . ,g, can not appear in a. k l k t The transformation from subnetwork N to subnetwork N' is classified as 'logic insertion' since the 'logic' realized by the driver of cell g., a, is 'inserted' into each of the cells g , . . . ,g by the transformation. This k l \ particular transformation is designated Transformation INS(a)('INS' being an abbreviation of 'logic ins ertion' and the '(a)' being added to differentiate it from a second transformation of the same type which will be introduced shortly). Transformation INS (a ) When a cell g. controls at least one FET along every path through the driver of a second, non-output cell, g., then: (l) every J FET controlled by the output of g . can be replaced by a parallel connection J of that FET and a two-terminal network of FET's in the same configuration as the driver of g. and (2) all FET's controlled by g. in the driver of g. can be S-deleted. Theorem 5.1.1 The transformation of a subnetwork of a given network by INS (a) does not alter the network's outputs. Proof For each possible input vector, A, one of the following two cases must occur. Let N and N' denote the altered subnetwork before and after transformation, respectively. Let g'. denote the function of cell g. after the S-deletion of all of the FET's controlled by g. in its driver. Case 1 There is a conducting path through the driver of g. for input vector A. Thus, in N, g.(A) = 0, and g.(A) = 1 since at least one FET controlled by g. appears along each path through the driver of g.. Hence 1 J every FET controlled by g . in an immediate successor is conducting. In N T , 17*+ the parallel configuration substituted for every FET controlled by g . in N is also conducting for A. Thus, the outputs of g. and every immediate successor - and therefore every successor (including any output cells) - of g. remain J unchanged for A. Case 2 No conducting path exists through the driver of g. for input vector A. Thus, in N, g. (A) = 1, and g. with input g. = 1 is obviously function- ally equivalent to g. "with FET's controlled by g. S-deleted, i.e., g . (A) = J J- J g f . (A). Thus, g'. (A) is the transmission function realized in N by every FET J J controlled by cell g. in the driver of an immediate successor. In N' , the J parallel configuration substituted for every FET controlled by g . in N has no J conducting path through the portion corresponding to the driver of g.. Thus the transmission function corresponds to g'. (A) as in the case of N. Hence, for this case also the outputs of g. and every immediate successor and successor of g . remain unchanged for A. J It is clear that the functions of any output cells which are not successors of g . can not be affected by the transformation. Q.E.D. The inverse of Transformation INS(a) is Transformation EXT(a). It trans- forms subnetwork N' of Fig. 5.1.1 into subnetwork N and is classified as 'logic attraction' sinoe 'logic' realized by the FET configuration a in the drivers of cells g , ...,g is 'extracted' by the transformation. K l *t Transformation EXT (a) Consider a non-output cell g'. and a two-terminal J FET subnetwork of configuration a and transmission function g. . Further suppose that none of the FET's in the subnetwork are controlled by cell g'. . If every FET controlled by g'. is in parallel with a subnetwork of configuration J , then this parallel configuration can be replaced in every case by a single FET controlled by any cell g. obtained as follows: (l) if no cell g. having 175 a driver of configuration a currently exists in the network, one is created; (2) a cell g. is then obtained from cell g 1 . by the S-addition of at least one J J FET controlled by g. along each path through the driver of g'. . J Theorem 5.1.2 The transformation of a subnetwork of a given network by EXT (a) does not alter the network's outputs. Proof Let N 1 and N denote the altered subnetwork before and after Transformation EXT(a), respectively. Ey Transformation INS (a), N can be trans- formed to a network N" while maintaining the outputs of N. By the definitions of the two transformations, network N" can be chosen to be identical to N' (while this is always true, for some subnetworks N, it is also possible to obtain one or more N" different from N' through INS(a)). By Theorem 5.1-1, N and N", and therefore N and N f , must have identical outputs. Q.E.D. It should be noted that the proofs of Transformations INS (a) and EXT (a) do not actually depend on the identical FET network a being in both the driver of g. and the drivers of g ,...,g . Actually it is sufficient for physically I k 2 k t different Q subnetworks to have identical transmission functions rather than being required to have identical structures. However, so that the transforma- tions discussed in this section, Section 5, remain simple enough to be applied by hand, it is desired that they depend only upon consideration of configuration and not upon analysis of realized functions. It may be apparent to the reader that if more sophisticated considerations based on function were permitted, restrictions on the different subnetworks designated a in Fig. 5.1.1 may be relaxed still further until even identical functions need not be required u under appropriate circumstances. 176 The second pair of logic insertion/ extraction transformations is illustrat- ed in Fig. 5.1.2. The transformations of this pair are designated INS(b) and EXT(b), and they are quite similar to INS (a) and EXT (a), respectively. Whereas the driver of g . in Fig. 5.1.1 contains, in series with FET network 3, an FET J controlled by g., the driver of g . in Fig. ^.1.2 has an FET controlled by g. in parallel with FET network p. Also, the 'inserted' logic, FET network a, is placed in series with each FET controlled by g. rather than in parallel as in J the previous case. Again, for the purposes of Transformations INS(b) and EXT(b), the FET network 3 need not be free of FET's controlled by g., although such FET's can easily be shown to be redundant. The two transformations of this second pair are given as follows: Transformation INS(b) When a cell g. controls one or more FET's in a second, non-output cell g., at least one of which is the sole FET along a path J through the driver of g., then: (l) every FET controlled by the output of g. can be replaced by a serial connection of that FET and a two-terminal network of FET's in the same configuration as the driver of g. and (2) all FET's controlled by g. in the driver of g. can be O-deleted. Transformation EXT(b) Consider a non-output cell g'. and a two-terminal J FET subnetwork of configuration a and transmission function g.. Further suppose that none of the FET's in the subnetwork are controlled by cell g'. . If every J FET controlled by g'. is in series with a subnetwork of configuration a, then this serial configuration can be replaced in every case by a single FET controlled by any cell g. obtained as follows: (l) if no cell g. having a driver of config- J 1 uration a currently exists in the network, one is created; (2) a cell g. is then J obtained from cell g'. by the O-addition of FET's controlled by g. to its driver - at least one of which is added in parallel to the existing driver. SUBNETWORK N Logic insertion: Transformation INS(b) r 1 \ / v / K SUBNETWORK N 1 Logic extraction: Transformation EXT(b) Fig. 5.1.2 Second pair of logic insertion/ extraction trans- formations: INS(b) and EXT(b). 178 It might be noted that the condition in both Transformation EXT (a) and EXT(b) prohibiting the existence of FET's controlled by g'. in a is actually J redundant under the practical assumption that the discussion is limited to MOS cells with a finite number of FET's. It is fairly obvious that to have an FET controlled by g'. in a subnetwork of configuration a and to still satisfy the conditions of the logic extraction transformations which require every FET con- trolled by g'. to be in series or parallel with a subnetwork of configuration a, would necessitate an infinite number of FET's in configuration a. Theorem $.1.3 The transformation of a subnetwork of a given network by either INS(b) or EXT(b) does not alter the network's outputs. Proof Let N and N' denote the altered subnetwork before and after Trans- formation INS(b) (after and before Transformation EXT(b)), respectively. It is sufficient to show: (l) that N' can be obtained by INS(b) from N if N can be obtained from N' by EXT(b) and (2) that INS(b) preserves the outputs of cells g.?jgv >*",g, for every input vector. From this, it can be deduced that 1 k l k t both INS(b) and EXT(b) preserve outputs of cells g.,g, , ...,g, , and as these i k 1 k t are the only possible cells connected from subnetwork N (N* ) to the rest of the network, the outputs of all other cells outside of N (N' ) are also preserved - hence the theorem statement. By a comparison, INS(b) and EXT(b) can easily be seen to be inverse transformations; consequently (l) is true. To demonstrate (2), consider each possible input vector A to the network. For each A one of the following two cases must occur. (Let g'. denote the J function of cell g. after the O-deletion of all of the FET's controlled by g. in its driver. ) 179 Case 1 There is no conducting path through the driver of g. (FET sub- network a) for input vector A. Thus, in N, g.(A) = 1, and obviously g.(A) = 0. Hence every FET controlled by g in an immediate successor is non-conducting. In N' , a in the serial configuration substituted for every FET controlled by g . in J N is also non-conducting. Thus the outputs of g.,g, ,...,g, remain unchanged i K ± k t from N to N 1 for A. (Any change in the output of g . is unimportant since it has J no immediate successors outside of the subnetwork nor does it realize a network output function. ) Case 2 There is a conducting path through the driver of g., a, for A. Thus, in N, g.(A) = 0, and g. with input g. = is obviously functionally equiv- -L J -L alent to g. with FET's controlled by g. 0-deleted, i.e., g.(A) = g*. (A). Since there is a conducting path through a for A, it is easy to see that the transmission function realized in N by every FET controlled by g . is the J same as that realized by every substituted serial configuration in N' for A. Hence, for this case also, g.,g, ,...,g, remain unchanged from N to N' for A. i K ± k t Q.E.D. The third pair of transformations is illustrated in Fig. 5»1»3« These transformations, designated INS(c) and EXT(c), can be viewed as essentially degenerate cases of the preceding insertion and extraction transformations, although this is not formally true due to the non-existence of FET's controlled by g' in cells g, ,...,g . In this pair of transformations, a again J K l K t represents the FET subnetwork being inserted or extracted. The transformations are defined as follows: Transformation INS(c) When a cell g. controls the sole FET in the driver of a second cell g., then: (l) every FET controlled by g. can be replaced by 3 J J '''/j SUBNETWORK N Logic insertion: Transformation INS (c ) r L o Si V A Logic extraction: Transformation EXT(c) o g k. SUBNETWORK N' Fig. >.1.3 Third pair of logic insertion/ extraction trans- formations: INS(c) and EXT(c). 181 a two-terminal network of FET's, a, in the same configuration as the driver of g. and (2) if g. is not an output cell, cell g. can be removed from the network 1 j j along with its input connection. Transformation EXT(c) When one or more cells, g , ...,g , of a k x k t network contain a common two-terminal FET' subnetwork a realizing transmission function g., Q can be replaced in every case by a single FET controlled by an MOS cell, g., whose driver consists of a single FET controlled by cell g. with J driver configuration a. Theorem 5. l.k The transformation of a subnetwork of a given network by either INS(c) or EXT(c) does not alter the network's outputs. Proof Let N and N' denote the altered subnetwork before and after Trans- formation INS(c) (after and before Transformation EXT(c)), respectively. The function realized by cell g. is just the complement of the transmission function realized by FET network a. '.Jhus the function realized by cell g. is identical to J " : ;he transmission function of Q and so is the transmission function of every FET controlled by g.. Clearly then, the outputs of cells g.,g v ,,..,g, are un- J i k 2 °k t affected by the transformations. Thus the outputs of all cells outside the sub- network are also unaffected. Q.E.D. Some of the possible uses of logic insertion in general are: to reduce the number of cells in a network, to reduce the number of levels of cells between network inputs and outputs, and/or to prepare for further transformations, Possible uses of logic extraction include: the reduction of the total number of FET's in the network (especially if g. already exists elsewhere in the net- work), the simplification of overly complex drivers, and the alteration of the [network configuration in preparation for further transformations. 182 Fig. 5.1.U(a), (b), and (c) demonstrate logic insertion/ extraction. A three level network (a) of three cells, g , g ? , and g employing 1, 7, and 1 driver FET's respectively, is transformed into a three-cell, two-level net- work with 9 driver FET's evenly distributed among the cells. This is accom- plished by first extracting by Transformation EXT(b) a subnetwork a, consist- ing of the parallel connection of three FET's controlled by x , x , and x, , from g to form the driver of a new cell gi (Fig. 5-1- Mb))- Reducing this four-cell network to a three-cell network, Transformation INS(b) inserts a parallel connection of two FET's controlled by x, and cell g. into cell g_ in series with the FET controlled by g'. The final network is shown in 2 Fig. 5.1.Mc). 5.2 Logic Duplication/Combination This class of transformations consists of the single pair of trans- formations illustrated in Fig. 5-2.1. These transformation are quite simple and are probably most useful prior to or subsequent to other transformations. The conditions on subnetwork N in Fig. 5-2.1 are as follows: g.,..., r g. are a set of cells with identically configured drivers and g, ,...,g K l \ 1 r are the set of cells having at least one input from the set g.,-...,g.. In subnetwork N' , g ,...,g constitute the set of immediate successors k l k t of cell g. . i The transformations, designated DUP for logic duplication and COM for logic combination, are described as follows: Transformation DUP A cell g. with immediate succesors g ,...,g 1 K l k t can be replaced by a set of (duplicated) cells, g.,...,gT, with driver configurations identical to that of g. if each FET formerly controlled by g. 9 8- OSr 9 183 HE Ht " o- Q o- i \rz f "XjX^X vXl (x 2 vX vX^) • % * 3 H 1 Xi HI L x uHC x 5 H[ (a) Original network before transformation. 9°\ «i HC 1 o- 4 og; Qg- HC (1 o- . HC «,-€ HC >i - — T ' ' — r — HC '» o- extracted subnetwork a: o CHI HI i *«,< 2 IL 1 3 dl 5 X (b) Network after Transformation EXT(b). inserted subnetwork CC: I ^ HC x iH[ T (c) Network after Transformation INSfb). Fig. 5.1.U Demonstration of logic insert ion/ extract ion. 181 SUBNETWORK N Logic duplication: Transformation DUP V A / \ Logic combination: Transformation COM SUBNETWORK N* .g. ';.'■'.! Pair of logic duplication/combination transformations: DUP and COM. 185 in the drivers of g ,...,g is replaced with an FET controlled by one 1 \ of the cells in the replacement set. If g. is an output cell of the network, one or more g , 1 < J < r, is regarded as an output cell realizing the same function as the replaced g.. 1 r Transformation COM A set of cells g.,...,g. with drivers of identical configuration, a, can be replaced by a single cell, g., also having driver 1 r configuration a, if each FET formerly controlled by g.,..., or g. is re- placed with an FET controlled by g. . If one or more of the g*? , 1 < j < r, is an output cell of the network, g. is regarded as an output cell realizing the same function as the replaced g. . Theorem 5«2.1 The transformation of a subnetwork of a given network by either Transformation DUP or COM does not alter the network's outputs. 1 r Proof Since g.,g.,...,g. all have identical drivers, they must realize the same function. Obviously, their outputs can be interchanged without affecting the outputs of any of their successors - including the output cells of the network. Q.E.D. The most obvious use for Transformation COM is in the reduction of the number of cells or FET's of a network. Possible uses for DUP include obtain- ing a network configuration suitable for the application of other transfor- mations or reducing the fan-out of a particular cell. 5.3 Logic Integration/Distribution Three pairs of transformations are discussed for this class. Two of the pairs are basic and are combined into the generalized third pair of transfor- mations. Unlike the preceding transformations, logic integration creates a 186 new cell by 'integrating' the drivers of the cells it replaces into the larger driver of the new cell. Logic distribution, the reverse process, breaks apart a single cell by 'distributing' portions of its driver to form the drivers of several new replacement cells. The first basic pair of logic integration/distribution transformations is shown in Fig. 5«3'1« The transformation from subnetwork N to N' is called MAND (for merge AND) since the series, or 'AND' connection, of FET's shown in the driver of cell g, of N is 'merged' into a single FET in g, of N' . Similarly, the transformation from N' to N is called DAND (for divided AND) since the single FET shown in the driver of g in N' is, in a sense, 'divided' into the several FET's 'ANDed' together in g of N. The second pair of basic transformations MOR (for merge OR) and DOR (divide OR) are illustrated in Fig. 5' 3' 2 and can be seen to be very similar to MAND and DAND. The FET's formerly in series in the driver of g in subnetwork N are now in parallel. Also, the FET networks a ,..,,a. formerly in parallel in g. of N' are now in series. J The conditions for the two pairs of transformations are quite simple: g.., ...,g. and g. must be non-output cells having only g, as an immediate successor and controlling only those FET's shown in the figures; cell g, may have inputs other than those shown. It should be noted that transformation DUP can often be helpful in altering a network's configuration to satisfy this condition. The descriptions of the two pairs of transformations are combined in the following: Transformation MAND (MOR) When non-output cells g ,...., g. with driver configurations OL,*»*,Ct , respectively, each control only a single FET and 187 SUBNETWORK N Logic integration: Transformation MAND V II o » k Logic distribution: Transformation DAND Ml > o- °i ' SUBNETWORK N' Fig. 5.3.1 First basic pair of logic integration/distribution transformations: MANX) and LAND. 188 Logic integration: Transformation MOR SUBNETWORK N V / A \ SUBNETWORK N* Logic distribution: Transformation DOR o &k r'ig. >. • :ond basic pair of logic integration/distribution transformations: MOR and DOK. 189 these i FET are connected serially (in parallel) in the driver of a cell g, , then this series (parallel connection) of FET can be replaced by a single FET controlled by a new cell g. whose driver is formed by a parallel (serial) con- J nection of the two-terminal FET networks a , ..,,a.. Transformation DAM) (DOR) When a non-output cell g. controls only a single FET, in a cell g, , and the configuration of the driver of g. can be partitioned into i two-terminal FET networks, a , ...,a., connected in parallel (series), then g can be replaced by i new cells g, ,...,g. with respective driver configurations a,,..., a. such that the single FET formerly controlled by g. is replaced by a serial (parallel) connection of i FET - one controlled by each of the cells g,,...,g.. The proofs that these four transformations preserve network outputs are omitted since the transformations are really special cases of the more general pair of transformations illustrated in Fig. 5»3»3« The conditions for this pair of transformations are similar to those for the two basic pairs, with the exception that the cells g r ...,g. and g. are no longer constrained to controlling a single FET: g-,,..., and g. must be non-output cells having only g, as an immediate successor and controlling only FET's in a FET subnetwork 3; £ must have inputs only from g-,,..., and g. ; g. must be a non-output cell with only one output controlling a single FET in J the driver of g ; and cell g, may have inputs other than those shown. The following describes the two generalized logic integration/distribution transformations: Transformation DFf Suppose g_,...,g. are non-output cells with driver con- figurations a,,..., a., respectively. Further suppose that all of the FET's con- trolled by g , ...,g. constitute a two-terminal FET subnetwork of configuration 190 Logic integration: Transformation INT V A A \ Logic distribution: Transformation DIS J k Fig- >• -. • General pair of logic integration/distribution transformations: INT and DIS. 19] 3 in the driver of a gate g . Then, this subnetwork in g can be replaced by a single FET connected to the output of a new cell g. whose driver is J constructed as follows: (l) the dual network, 3 , of 3 is determined; (2) for l,...,i, each FET in 3 controlled by g* is replaced by an FET subnetwork d ' of configuration 0%; (3) the resulting FET network, 3 , is the driver of the new g . . Tranformation PIS Suppose a non-output cell g. has only one output con- J nection, to an FET in the driver of a cell g, . Further suppose that the FET d' network constituting the driver of g., p , can be partitioned into p two- J terminal subnetworks of i(i < p) different configurations, a,,..., a.. Then the single FET in g, controlled by g. can be replaced with an FET subnetwork k J 3 determined as follows: (l) i new cells g_,...,g. are constructed having drivers of configurations a,,..., a., respectively; (2) an FET network 3 is d' then derived from 3 by replacing each two-terminal subnetwork of configuration a* by single FET controlled by go, .■•> = l,...,i; (3) 3 is then obtained as the dual network of 3 • Theorem 5.3.1 The transformation of a subnetwork of a given MOS network by either Transformation INT or DIS does not alter the network's outputs. Proof First consider Transformation INT. With g ,...,g. designating the functions realized by cells g 1 , ..., g., respectively, let the transmission function of the FET subnetwork 3 to be replaced be f^(g , . . .,g. ) . Then the dual network 3 of 3 must realize the ~P _ - d dual transmission function, f p (g , ...,g ± ), and replacing each FET in 3 connected to the output of g* with a.* (whose transmission function is obviously go) for : = l,...,i, to form configuration 3 d will result in the transmission 192 function f (g-, , ...,g. ) for the driver of the new cell g.. Hence, cell g X J. J J will realize the function f (g, , .. .,g. ) which will, therefore, also be the transmission function of any FET connected to the output of g . . J Transformation INT replaces a two-terminal FET subnetwork of the driver of g. with a single FET of the identical transmission function. Thus the function realized by cell g will be unchanged. Since g , ### ,g. are non- output cells and have no other output connections than to cell g, , the outputs of any network of which cells g , ...,g. and g. form a subnetwork will have -L X K its outputs unaffected by Transformation INT. The proof for Transformation DIS is similar but basically proceeds in reverse order. Q.E.D. Initially, the pre-transformation conditions given for INT or DUP may appear to be restrictive. For example: g , ...,g. and g. can only have J- J- j output connections to one other cell; the inputs from g,,...,g. to g, must J- IK be the only inputs to FET subnetwork p; cell g. can control only a single FET J in g, ; etc. The appropriate use of logic duplication and/or logic combination, however, can circumvent many of these apparent limitations. For example, if g, ,«»»,g. were connected to two identical FET subnet- works p_ and p p in g rather than the single p specified, then: g , ...,g. could be duplicated by Transformation DUP; Transformation INT performed based on p (as p) and then on p , to obtain g. and g. in N 1 , respectively; and, ^- J O •H P 53 o •H H T3 P cd o ?H •H bO hO D O P ■ a •H <4H O 0) w 3 o •H bO O H Ch >■'.. Second pair of redundant logic addition/deletion transformations: KAD(b) and RDE(b). 197 Trans format ion RAD (a) (RAD(b)) Consider an FET subnetwork of configura- tion a which appears in the drivers of one or more cells in an MOS network, N. Consider also a non-output cell g. in N such that neither g. nor its successors control any FET in configuration a. If, along every path from g. to an out- put cell of N, there exists a non-output cell for which every FET controlled by its output is in series (parallel) with an FET subnetwork of configuration a, then one or more FET subnetworks of configuration a can be S-added (O-added) anywhere in the driver of g.. Transformation RDE(a) (KDE(b)) Consider an FET subnetwork of configura- tion a which appears in the drivers of one or more cells in an MOS network, N' . Consider also a cell g. in N' such that neither g. nor its successors control any FET in configuration a. If, along every path from g. to an output cell of N' , there exists a non-output cell for which every FET controlled by its out- put is in series (parallel) with an FET subnetwork of configuration a, then one or more FET subnetworks of configuration a can be S-deleted (O-deleted) any- where in the driver of g.. Theorem j?.U.l The transformation of a subnetwork of a given network by either Transformation RAD(a), RAD(b), RDE(a), or RDE(b) does not alter the network' s outputs . Proof Consider Transformation RAD(a) first. Suppose the theorem state- ment is not true. In other words, assume there exists a network N for which the function of at least one output cell, g., is changed due to the S-addition J of FET subnetworks of configuration a to the driver of a cell g i satisfying the conditions of Transformation RAD(a). ] 98 Since the configuration of g is the only one changed by RAD(a), only the functions realized by g. and its successors may change as a result of the transformation. Let g^ be a successor of g. for which every FET connected to g/s output is in series with an FET subnetwork of configuration a. Whether or not the function realized by g, is changed as a result of the transformation. JO ■ it can be shown that it cannot contribute to any change of function in any of its immediate successors. Consider the following two possible cases for an input vector A of the network, noting that the transmission function of FET subnetwork a is invariant under the transformation since no input of a is g. or a successor of g.: Case 1 The transmission function of a is 1 for A. Since Transformation RAD (a) only replaces short circuits in the driver of g. by FET subnet- works of configuration a and since such FET subnetworks effectively become the short circuits they replace for input vectors A for which a is conducting, the transmission function of the entire driver of g. for each such A must be invariant under the transformation. Thus, for A, the outputs of g. and its successors, including g g and its successors, are unchanged by the transformation. Case 2 The transmission function of a is for A. Since every FET, F, connected to g/s output is in series with an FET subnetwork of config- uration a, for such an input vector A, no conducting path through the driver of an immediate successor of g* can include F. Thus, for A, the functions of the immediate successors of g* are independent of any change in the function realized by g, which may result from the transformation. 199 Now consider the output cell g. whose realized function is changed J by RAD(a). Since the configuration of cell g. is not altered by the trans- J formation, the only other possible cause of a change in function is an input of g. whose realized function is also changed by RAD(a). Since the external variables obviously can not be affected by RAD(a), this means at least one cell, g , for which at least one FET connected to its output is not in series with a subnetwork a, is an immediate predecessor of g. whose realized function J is affected by RAD (a). The same argument can be made for the existence of a similar immediate predecessor, g , of g and so forth. Due to the assumption of a loop-free, finite network, a 'chain' of cells created in this manner, realizing functions altered as a result of RAD(a), must eventually be found to originate with g. (since only g. was directly affected by RAD(a), only the functions realized by its successors may be changed). Thus, this chain of cells represents a path extending from g. to g . along which no cell g*, I f j, exists for which every FET connected to its output is in series with an FET subnetwork of configuration a. The existence of such a path, however, contradicts the assumption that network N satisfies the condi- tions of Transformation RAD(a) for a cell g.. Therefore, no network exists whose network outputs are altered by the proper use of Transformation RAD(a), and, consequently, the theorem statement concerning RAD(a) is true. Similar arguments can prove the theorem for the other three transforma- tions: RAD(b), RDE(a), and RDE(b). Q.E.D. It may be noted that the conditions required for the preceding two pairs of MOS network transformations have a rough counterpart in the generalized 200 triangular connection configuration for networks of NOR gates (among others). (This configuration is a special case of Property 3 given in [LNM 7^].) This configuration is illustrated in Fig. 5.M3* NOR gates in subnetwork S have output connections only to each other or to gates k , . ..,k . NOR gate j -L S has an output connection to each of L,..#,k . In such a case, connections from j to the NOR gates of subnetwork S may be added or removed as desired without affecting the output functions of k , ...,k or their successors. J- s (A slightly less generalized triangular connection configuration for NOR gates is shown in [BILM 69].) Transformations RAD(a) and RAD(b) may be used to change the configuration of a cell in anticipation of further network transformation (e.g., by Trans- formation COM). An obvious application of RDE(a) or RDE(b) is the reduction of the number of FET's in a network. Fig. ^.k.k and Fig. 5.M5 show two examples of such usage of RDE(b). The two original networks used in these figures are taken from [Shi 72], p. 116, which discusses a computer program implementation and subsequent results of the non-level-restricted MOS network synthesis algorithm proposed in [Liu 72]. In the network of Fig. ^.k.k(a) the connection from cell g, to g„ is actually unnecessary. The fact can be recognized and the FET in g p connected to the output of g deleted through the use of RDE(b) as follows: (l) The driver of cell g in Fig. 5.MM a ) can be transformed into the new configura- tion in Fig. 5.^. Mb) by simple 'logic defactorization' (discussed in Section 5.5). (2) Considering an FET connected to the output of g to be the necessary FET configuration a, it can be seen that a occurs in the driver of g ? and in parallel with the only FET connected to the output of g ? . The conditions for 201 -3- Lf\ •H 202 *h c; •H > >Al •H O Jh rl T3 'rA OO a; W) -p r 1H «H cd O *j C ?H O o •H £ -P ■p cd O O p> CD o3 C •H hO •H O S fl fe o •H P -P £ 03 03 13 O 3 CH TD w CD fl M 03 5h <+H -P O U CD H -P & <+H • g 03 *"-"* 03 ,Q X ^ w CD Jh W O R P > s w P !m .0) >5 •H S ^ Pn -3- •H C\J bO <4-i O Trl x x H' H bO J °T 1= r H o •H -p CTJ ts) •H *H O -P o cfl •H i -p CD -P C CD +3 a in CD O W -p 3 03 T3 « c o •H •p 03 o w C 03 U XX X ! -P H 03 > O 5) of the driver of g to achieve the final result in Fig. 5.4.4(d). While deriving the final network in this example formally involves the additional use of intra-cell transformations (logic factorization/defactoriza- tion), an experienced user could skip these steps by recognizing that the FET in g connected to the output of g p is 'effectively' in parallel with a sub- network of configuration a in the original network. A second example of the capability of KDE(b) is illustrated in Fig. 5.4.5. In this case, the subnetwork configuration a consists of FET's connected to external variables. The example proceeds as follows: (l) The driver of cell g in Fig. 5.4.5(a) is first reconfigured by logic defactorization (resulting in Fig. 5.4.5(b)). (2) The serial configuration of three FET with connections from x_, x , and x, is selected to be a. In Fig. 5.4.5(b) a appears both in the driver of g and in g in parallel with the only FET connected to g . Actually, the three FET's of a appear in a different serial order in g p , but if this configuration can not be recognized as being equivalent to a (e.g., when transformations are being performed by machine), a basic intracell trans- formation discussed in Section 5-5 is capable of permuting the series of three FET's into the exact configuration a. (3) With this choice of a, Transformation KDE(b) is seen to be applicable, and the FET subnetwork of configuration a. can can be 0-deleted from the driver of cell g, to obtain the result in Fig. (c). 205 For this example, in addition to the FET removed by RDE(b), a second FET can be saved by logic factorization of the driver of cell g. (the two FET" s connected to x can be combined — see Fig. 5. h. 5(d)). 5.5 Logic Factorization/Pefactorization and Other Basic Intracell Transformations This class of widely known and basic transformations of FET networks is included just for the logical completeness of the proposed set of transforma- tions based on configuration considerations. They are often necessary in situations where the transformations described in previous sections (5-1 through 5-^) are applied rigorously (as in computer implementations). In hand applications, these intracell transformations often need not be actually carried out, the recognition of the equivalence of dif- ferent FET configurations sufficing to enable the evaluation of the applica- bility of more sophisticated transformations (e.g., not all of the detailed steps in the two examples at the end of the preceding section need be carried out in practice). The transformations are illustrated in Fig. 5.5-1 and Fig. 5- 5.2. a, p, and y are three possibly different FET subnetwork configurations having the respective transmission functions f , f , and f . The two pairs of logic factorization/defactorization transformations (Fig. 5«5.l) can simply be justi- fied by the logical equivalence of the Boolean forms (f v f B ) f T and f a f y v f a f i and of f f A v f and (f v f )(f a vf ), respectively. The remaining basic a$ y a y p y intracell transformations (Fig. 5«5«2) are even more obvious. 206 Factorization ¥ Defactorization Fig. 5*5«1 Logic factorization/defactorization (intracell) t rans format ions . <=#> 207 1 T X: — 7 T ^> * HI ^ — 7 \ 1 T Fig. 5.5.2 Other basic intracell transformations. 6. TRANSDUCTION APPROACH TO MOS NETWORK DESIGN In Section h, methods to synthesize networks, usually G-minimal or G- minimal under certain restrictions, were discussed. A different approach to the design of networks of MOS cells is proposed here: Given a desired set of (completely or incompletely specified output functions, f , . ..,f , and an existing network realizing these functions (it need not be G-minimal), the network is transformed by a procedure which attempts to reduce the numbers of cells and intercell connections and/or to 'simplify* the functions realized by the cells (allowing a reduction of the number of FET's employed). Such procedures will be called transduction ( trans formation and re duction ) procedures. The transduction procedures to be proposed here are, in a sense, more powerful than the transformations described in Section 5 which are based on the consideration of the cell and network configurations. Transduction pro- cedures are based on a consideration of the specific function realized by or required of each cell of the network. The transduction approach to MOS design was suggested by the success of the research group - of which the author was a member - led by Prof. Muroga of the Department of Computer Science, University of Illinois, in the use of transduction methods to obtain 'near-optimal' networks of NOR gates within a reasonable expenditure of computational effort. [Cul 75l[CLK lk][KC 76][KM 76] [KM tbpHKKM 75HIA1 75][M mOC 75HLK 75] ^ thoueh there are similarities in the transduction approaches to the design problem for negative gate networks and that for NOR gate networks, the two approaches are also dif- ferent in many respects - stemming mainly from the fact that the actual function 209 realized by a negative gate is not fixed as in the NOR gate case. The relation- ship of these two design problems will be further discussed later as different aspects of the proposed transduction approach to MOS network design are developed. Section 6.1 will treat the theoretical development of transduction pro- cedures for MOS networks, and Section 6.2 will discuss actual computer program implementations of these transduction procedures, as well as examples of results obtained. The usefulness of the transduction approach will be dis- cussed in Section 6.3. 6.1 MOS Network Transduction Procedures Consider a negative gate or MOS cell network with inputs x , ...,x , (completely or incompletely specified) output function f, and gates g , ...,g realizing functions u, , . . . ,u = f (with respect to x. ,. . . ,x ). For each negative gate, g., realizing function u., u. must be a negative function of its inputs. In other words, according to Theorem 2.4, for every 0-1 pair of u., one of the inputs of g. must provide a 1-0 cover. As long as this condition is met, g. can remain a negative gate realizing function u. — even if those values of its inputs not involved in the 1-0 covers are changed and even if new inputs are added, old inputs are removed, and/or new inputs are substituted for old. Transduction procedures are based on the fact that if 1-0 covers provided by inputs of a gate are 'guaranteed' for all 0-1 pairs of the gate's Compare this with the case for NOR gates: (l) for each specified '1' of u. (suppose u. is the function of NOR gate g.), the function of every input of II 1 g. must be a '0'; (2) for each specified "0' of u., at least one of the inputs must provide a '1' cover. 210 output, then all of the other values of all of its inputs, i.e., those not involved in any such 1-0 cover, may be considered to be *'s with respect to that particular gate. The following definitions will allow a presentation of systematic pro- cedures for network transduction. Definition 6.1.1 Let an augmented truth table for a gate g . in a network J n N with n external variables and R negative gates be a truth table with 2 rows, one for each input vector A £ V , and R + p. columns, one for each gate, g , . . . ,g , plus p. supplementary columns , s ,...,s . An entry in row A and A J J_ JJ . v column g. of the augmented truth table is g.(A), which may be 1, or * (un- specified). Each supplementary column s. corresponds to a distinct pair con- sisting of a entry and a 1 entry in column g. (i.e., a 0-1 pair of function J u.)« A supplementary column has only two non-blank entries duplicating the J pair of and 1 entries to which it corresponds. Example 6.1.1 An example of an augmented truth table for a gate g^ in a network consisting of three negative gates (see Fig. 6.1.1) is shown in Fig. 6.1.2. Column g has three 1 entries and five entries and therefore j requires the 15 supplementary columns shown. Assume that external variables x , x 9 and negative gates g , g are inputs of gate g . Additional rows for illust rational purposes have been added below the supplementary columns. In this case, inputs which have corresponding 1-0 covers for each 0-1 pair of g_ are noted. For example, the 0-1 pair of g- represented by supplementary column s has corresponding 1-0 covers in both x and g p . Inition 6.1.2 Let an augmented truth table be constructed for a gate g^^ with inputs x^ ,...,x k , g^ ,...,g^ , in a network N. An assignment '1 Is 211 1 g l : Fig. 6.1.1 Network of Example 6.1.1 realizing f = x x v x x . X-i x_ ^o S-i So So s l s 2 s 3 s 4 s 5 s 6 S T S 8 s 9 s 10 s ii s l2 s l3 s li+ s 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 existing x l x 3 cr °1 X x X X X X X X 1-0 covers X X X X X X X X X X X Fig. 6.1.2 Augmented truth table for g of Example 6.1.1. of covers for column g. with respect to the set of columns x ,...,/ , gp ) 1 r 1 . . . ,g , , is a selection of one 1-0 cover in the set of columns for each 0-1 s pair in a supplementary column of the truth table. The entry and 1 entry of the table involved in each such 1-0 cover will be called, respectively, a necessary and a necessary 1 for column g.. If exactly one 1-0 cover exists among columns x , ...,x , gp , ...,g„ for a particular supplementary 1 r 1 s column, this 1-0 cover will be called an essential 1-0 cover with respect to the 0-1 pair and the set of columns x , ...,x , g„ , ...,g« . Further- 1 v r 1 's more, the external variable or gate corresponding to the column containing the essential 1-0 cover is called an essential input of gate g. with respect to the set of inputs x , ...,x , g* ,...,gn . 1 r 1 s Note that in the worst case, when half of the values in column g. are 0's ' i and half are l's, there are 2 x 2 " = 2^ 0-1 pairs which require the assignment of 1-0 covers — a number which grows rapidly with n. Fortunately, as can be seen in the computer program implementation of the transduction pro- cedures (described in Section 6.2.1), by properly organizing the assignment of covers, not all covers need be explicitly assigned (some are implicitly assigned by the assignment of others). Example 6.1.2 Fig. 6.1.3 again shows the augmented truth table of , / Rzample 6.1.1 for a gate g assumed to have inputs x , x , g , and g . An j 1 3 1 d assignment of covers for column g q has been made as indicated in the rows below the supplementary columns. As seen in Fig. 6.1.2, supplementary columns In the case of NOR gates, no more than 2 'covers' need be assigned for any single gate. Also, a 'cover' in the case of NOR gates is a single value, while a cover in the case of negative gates is a pair of values. 213 X.. Xp X^ g_ gp g n S,- S^ So S^ S^S^S.-S^S^S. '1 °2 °3 h "5 6 "7 8 "9 *10 o iri2*l3*l^l5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 assigned 1-0 covers f 1 X 3 g l * gp X X X X X X X X X X X X X X X Fig. 6.1.3 Augmented truth table with covers assigned for g_ of Examples 6.1.1 and 6.1.2. X, Xp X g.. gp g_ ! 9 S 12 S 13 14 15 1 ■ftr 0-*± +0- H- 1--1--1--1 Fig. 6.1.U Determining necessary l's and O's in gp of Examples 6.1.1 and 6.1.2. s 1 , s 2 , s,, s^, s^, s , b^, s 12 , s 13 , b^, and s^ have corresponding essential 1-0 covers. 1-0 covers assigned in column g for 0-1 pairs of column g., create the four necessary l's and two necessary 0's in column g as shown in Fig. G.l.k. After all of the 1-0 covers have been assigned for every column repre- senting an immediate successor of a gate g., all of the 1-0 covers required to be provided by g. are known, and hence all of the necessary l's and neces- sary 0's of g. are known. Every other entry of column g. which is not a neces- sary 1 or necessary can then be changed to a 'don't care' since their exact values are not important at this stage. The only exception is when g. is an output gate of the network which must realize some output function f .. In such J a case, all specified 0's and l's of function f . must also be considered neces- 2 sary 0's and l's of column g. since any change of these values would obviously cause an erroneous output. Example 6.1.3 Since the only immediate successor of g in Examples 6.1.1 and 6.1.2 is g , the only necessary 0's and l's (shown in Fig. G.l.k) of column j g 2 are the necessary 0's and l's resulting from 1-0 covers assigned for g . Hence the two remaining values, in the first and third rows of column g„, may be changed to 'don't cares.' An assignment of 1-0 covers can now be made for column g , with respect to columns x ,x , and g (corresponding to inputs of ;e g in the network), ignoring the ' *' entires of the column. The aug- mented truth table for g and one possible assignment of 1-0 covers is shown 6.I.5. In this case, g provides no 3-0 covers for g , and it is thus ;een that the connection from g to g can be removed. It is important to had the entry in row 1 and column g, not been recognized as being 215 'don't care,' g.. would have been regarded as an essential input of g , e.g., due -L 2 to the 0-1 pair in rows 1 and 2 and column g (see Fig. 6.1.2) which would other- wise exist and for which only g could provide a 1-0 cover. Now consider column g... Since the only necessary l's and O's in column g are a result of provid- ing three 1-0 covers for g , all of the other components, unnecessary l's and O's, can be set to 'don't cares' (see Fig. 6.1.6). The augmented truth table for g.. 'Fig. 6.1.7) shows that only x is an essential input for g , and it is alone sufficient to cover every remaining 0-1 pair of g . Thus, the connections from x and x to g can also be eliminated as redundant. At this point, the corresponding negative gate network is shown in Fig. 6.1.8 with its associated truth table. The preceding examples have demonstrated how a negative gate network who, e individual gate outputs are known can be transformed, while maintaining re- quired output functions, on the basis of Theorem 2.k and the concept of 1-0 cover assignment. Note at this point that the transformed network is expressed only as an abstract negative gate network — a specification of connections among external variables and gates and a truth table giving the output function of each gate of the network. If an MOS implementation of this negative gate network is desired, additional computations are required, regardless of whether or not an MOS implementation of the original network was known. This will be discussed further later. The type of transduction procedure exemplified above is referred to as a pruning procedure since it transforms a network only by 'pruning' existing + fCLK 7U] and [LC lh] discuss pruning procedures for NOR gates. 216 X l X 2 X 3 g l g 2 'l °2 s 3 B U s 5 s 6 s 7 S 8 1 * 1 1 1 1 1 -x- l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 f X 2 X X X X existing 1-0 covers < X X X X X X r : x i U as* l-( sigi ) cc led 3ve] "S 1 X X X X X X X X Fig. 6.1.5 Augmented truth table with covers assigned for g 2 of Examples 6.1.1 - 6. 1.3. x l X 2 X 3 • • • J v n+R denote negative gates g,,...,g ; respectively, of which v ...... v , realize network output functions f_,...,f , ntl 7 7 n+m * 1' ' nr respectively; v _.,..., v denote 'output terminals' whose sole connections n+R+1 n+Rtm * are from gates v ..,..., v , respectively; n+1' ' n+m' J ' c. . denotes a connection from v. to v. (undefined for i > n + R + 1 or j < n); f (v. ) denotes the function realized at v. . l i The correspondence between the v. and the gates, external variables, and output functions is illustrated in Fig. 6. 1.9. For simplicity, input and out- put terminals will be omitted in subsequent illustrations. definition 6.1.3 If, by replacing the function realized by a particular external variable, gate, or connection with a function f, the function realized by every (other) gate of the network remains negative with respect to the func- tions of its inputs and all the network outputs remain as specified, then f is said to be a permissible function for that external variable, gate, or con- nection, respectively. Let (G(v. ) and G(c.) denote a set of permissible func- tions ("not necessarily inclusive of all possible permissible functions) for gate or external variable v. and connection c. ., respective! . -missible functions and CSFF's were first introduced for NOR gates in " ?6]. These corresponding definitions for negative gates take into account the fact that a negative gate can realize any negative function. 220 w a p o ft •H -p p CJ 2 c 3 P DO V ■§ bO — « 13 — o ■P u o C o u - 0) -p a H w r' C rH -■ U - V- •H • H Ch OJ «H OJ A OJ W CD 0) O O *H ft c o p CJ CO a Sh P >> rQ T3 0) P c3 p 03 ,Q O P w o p 0)

vo bO 221 Definition i . : . If a set of permissible functions is chosen for ea gate, external variable, and connection of a network such that the following condition is satisfied for each gate g. , then these sets are called compatible sets of permissible functions (CSPF's): If any function f * is selected from the set of permissible functions of each immediate predecessor, v, or g. or the set of permissible functions of its connection c. . , then there exists a function f ! in the set of permissible functions for g. such that f! is negative with respect to the choice of f ' . k A compatible set of permissible functions for a connection c. . is denoted G (c. .). The CSPF's dealt with here will also be expressed in vector notation. Three preference orderings of network elements (i.e., external variables and/or gates) will be defined in a general sense (the user will have some latitude in selecting the specific orderings) for use- in the pruning procedure. These orderings are defined by three functions, cr , cr , and a , which assume lower values for more preferred elements. For example, cr (v.) < cr (v.) indicates that v. is more preferred than v. in preference ordering cr, . i J 1 Preference ordering cr is an ordering of gates for selection for pruning. This ordering must satisfy cr (v. ) < cr (v. ) if v. e S(v.). Preference ordering a is an ordering of gates and external variables according to their desirability for disconnection as inputs to other gates. During pruning, if a choice occurs of inputs to be disconnected from a certain gate v., the gate or external variable input, v., v/ith lowest value ^(y^) among J them is selected for disconnection (i.e., c is removed from the network). ■*-tJ See footnote on preceding page. y^ Preference ordering cr is an ordering of gates and external variables according to their desirability for providing 1-0 covers. Generally, external variables are considered more preferable for covering since the 0's and l's involved in such covers do not create 0-1 pairs which, subsequently, must them- selves have assigned 1-0 covers (as is the case when a gate is assigned a 1-0 cover). Algorithm 6.1.1 Procedure to 'prune' redundant connections from a negative gate network (PP). A network N of n external variables, m output functions, and R negative gates will be transformed into a network N' having the same external variables and output functions. The number of connections among gates and external vari- ables in N' will be less than or equal to that in N. Step 1 Select a specific ordering a of gates and specific orderings ov> and a of gates and external variables (input terminals). . Step 2 Set G (c. . _) = f. , i = (n + l),. . . , (n + m). Step 3 Initially, let I be the set of all gates in N. Step k Select v. € I such that a (v. ) < cr (v) for every v e I, v f v.. Step 5 Compute a CSPF for v. as follows: G (v. ) = G (c. .). + C 1 „__ / \ C 1J V.€lS(V. ) ° 3 i . ■_■ ■ 'elect an irredundant input set for v. with respect to G (v.) as follows (this step performs the actual pruning): alculation can be expedited by the use of the vector representations of the sets involved. It can be shown that: Cr ^(v.) 1 if and only if at least one G { '(c..) is a 1; -;" '(v.) if and only if at least one G^(c.) (d)iJ c i , > c xj is a 0; and ( '(v. ) » if and only if every 0^ ; (c. .) is a * (no other cases c i c 1J will occur). (a) Seek a v. £ IP(v. ) such that: J i (d) (i) there exist no indices, d, e, satisfying: G (v.) f (e) (v ) = 0; G {e) (v.) = f (d) (v.) = 1; and either f (d) (v) = (e) or f (v) = 1 for every v c TP(v.), v / v.. (This condition n be illustrated as follows: d e G c (v.): ( 1 ) f(v.): ( 1 ) ) IP(v.) - {v.l: < or -1 )• If such indices, d and e, did exist, f K (v.) and f (v.) J J would be an essential 1-0 cover and, hence, v. would be an essential input of v..); and (ii) for every other v, € IP(v. ) satisfying condition (i), V 1 i G (c .).. every 0-1 pair among specified values of f ' fv. ) has a 1-0 cover <- J _ » - 1 - x s X atnons; specified values of functions f'(v. ),...,f'(v. ). Therefore, f (v. ) can h J s. X be realized by negative gate v. with input connections c. A ,...,c. l It only remains to show that N' realises the correct network output functions. By Step 2 of the algorithm, all specified 0's and l's on each net- work output function, f^...^ become specified 0's and l's respectively, of VW,n+R4a ) ''-'> G c ( W,n+R-+m ) * Iater > by Step 5 > the selecte d G,(v n+1 ), *** ,G c^ V n4m^ ^ ff ^ v n+l^ ,, " ,,f, ^ v n4m^ ° an ° nly consist > respectively, of sub- sets of the sets of permissible functions G (c , ) G (c ). c x n+l,n+R+l" ' c v n+m,n+RW ^ V n-tl^* ,, ' f ' ( v n-HeJ wil1 contain a11 specified 0's and l's of f -,,..., f m , respectively (and since v^, . . . ,v^^ are connected to output terminals V n+R+l'"*' V nH<-i c J 2' pair G^Mv.) = 0, G^Mv.) = 1. With the suggested modification, G^'(c. . ) * C 1 ' C 1 C Jyl and G (c . . ) = 1 have first been assigned since they are involved in 1-0 covers for 0-1 pairs G^ 2 '(v. ), G^'(v. ) and G^(v.), G^ '(v.), respectively. v.. _1_ \-> -L. v. -I- n—- J- Hence, the assignments of G^ (c . .) and G^ (c. .) to cover the 0-1 pair C Jr,^ 1 *~ 3 n>^~ G wy (v.), G VJy (v.) can be skipped due to the existence of a previously assigned 1-0 cover. The consequent increase in the number of *'s in the vector for G (c. .) could lead to more *'s in the vector for G (v. ). In turn, this would mean fewer required 1-0 covers for G (v. ), and the chances of pruning c J 2 connections to v. would be enhanced. Jo ;-:-; c o r s g T-l £ -p •H -p «5 ro * H o O H O ?H >H O O <4h <■ — ' MiH O 3*8 C5 e *•* -> >>> •H P T3 •\ T3 -P OJ •r-D H * * * * O 0) W O -p 0) ^ — ' O bO O 0, g, CS cd w /*"~N w •H X! •\ w -p T3 H * o o * * £* O CQ Ph O O Ph e •H H •\ CO 1-3 * H o o H o •H U bflP-i ^— ' •H Ph o *h c5 ° P* '-o-P •H ,D -H *\ ^H OJ ^3 o •r-D H * o * H o CD hO O -P H ^-^ O < O CD CS H «h CD O • S W •H a •N W o H •r"D H * o o * * fa W fa ?H O W CD o O > C5 ^ •H O O H H O H O C5 ro T"D O H o O H o > «H ^^ OJ •i~D H O o H H o ^M , , H •i~D !> H o o O O H N^^ TI Ph a; H •H <+H II •H TJ O ro F! •r-D > CH •s O OJ •r"D -P f> O •\ CD H CH •rs CD ' — ' «H O • J- C • o H •H • -P VO ctf ^H CD +> H w Ph pi HC A H VO bO •H fa ro 229 Along somewhat similar lines, a second modification can be proposed. Suppose gate v. has immediate predecessors v. ,...,v. in StepY of the algo- 1 s i rithm. Since these immediate predecessors must follow v. in ordering cr , at this stage G (v. ),..., G (v. ) have not yet been evaluated (in Step 5). It C J l C J s. l is possible that some of these immediate predecessors are gates which have other output connections whose CSPF's have already been assigned during Step '( for previous v.. For example, G(c. ,), k / i, may already be known. Since it can be seen that 1-0 covers assigned to a gate's output connection are even- tually assigned to the gate itself (through Step 5), all existing assignments of necessary l's and necessary 0's to output connections of v. ,...,v. can J l °s. l actually be considered to be assignments of necessary l's and 0's to respective G o (v.. ),..., G^(v_. ). Combining this information (necessary 0's and l's as- i c h c J s signed for other output connections of v.'s inputs) with the strategy suggested in the first modification of making use of existing 1-0 covers, still further reductions in the number of assigned l's and 0's are possible. This, in turn, means generally larger sets of CSPF's and a greater possibility of pruning connections. Example 6.1.5 An example of the benefit of the second modification of Algorithm PP is illustrated by the subnetwork in Fig. 6.1.11. It is assumed that x the 0-1 pair G^Mv.), G^ d Mv.) due to the high preference of v . If the * c v l ' c v 1 Jo second modification of the algorithm is implemented, however, the existence of the previously assigned G^(c. , ) - and G; e ^(c , ) = 1 is recognized c J-j^ Jl*^ 230 o H II II S-*. ^— v M ^i *\ »^ H H f-3 •r-D O O TJ CD - — O •> — O o O * II H •1-3 H T3 O CtS H O II II 13 CD c5 es * * II II •H •H •\ »\ m m •ra •l~D o o T3 C5 C5 H VO 0) H Q> 1 •H T3 CD W W o W •H 'a u o -p CD w d a o •H ts ■p •H W •H !h 0) > O o O H •<~3 T"3 5> > 13 CD H O ii II •r-3 CM •r"3 T3 CD v n+ 2> v n +3 are network output gates realizing output functions f , f p , and f , respectively. The situation in Fig. 6.1.12 occurs just after Step 2 of the algorithm (for simplicity, assignments made to a gate's output connections will be considered as being made to the gate itself). Suppose that f (v.), f (v.) is an essential J a 1-0 cover of the 0-1 pair G^Vfl^ ^ {Y n+l ) and f ^V' f(d)(v j } is an essential 1-0 cover of G (v „), G (v ). Then it is known that assign- c v n+2 " c ^ n+2 y ments G; a) (v ) = G^ d) (v ) = and G (b) (v.) = G^(v.) = 1 must eventually be C J C J cjcj made. Further suppose that f^ (v ), f (v ) is an essential 1-0 cover of G^(v.), G^ e '(v.), then it is axso known that G^ a '(v, ) = 1 and G^Vv ) = c d c J c v k' c v k y will be assigned. Now suppose that Step 7 of Algorithm PP is reached for v. = (a) (e) V r,,Q> and a 1_0 cover is sought for the 0-1 pair G v ; (v _), G y ' (v _). Since n+3 c v n+3" c v n+3 y °l^ v n+ -3^ < °i( v -j)> G ^ v -)> and hence G (c, .), would not yet have been determin- ed by the unmodified algorithm. Thus, even with the first two modifications suggested, the algorithm would select G,; (vg), G^(v^) (actually G^ a ^(c^.), (e) (c^)) as the 1-0 cover to assign. With the addition of the third modi- fication, however, ^ (\) - 1, G^(v ) =■- would be known after the pre- assignment step and could be utilized at this point as the 1-0 cover of (V .), G (e) (v ). n+y' c ^ n+3' Is easy to make the pre-assignment step into a systematic procedure. ?he necessary procedure, to follow Step 2 of Algorithm PP, would be very similar , 5, 7, and 8 of the algorithm - Step 6 being omitted and covers :gned in Step 7 only when essential 1-0 covers exist. After this pre- c v n+1 G (b) (v J =0 c v n+1 f (a) (v k ) - 1 f (e) (v k ) = f (a) (v.) =0 f (b) (v°) - 1 3 f (d) (v.) = 3 f (e) (v.) =1 3 G (d) (v ) = 1 c v n+2' G (e) (v _) = c n+3 G (a) (v _) = c v n+3' G (e) (v .) = 1 c v n+3 f (a) (v £ ) - 1 Fig. 6.1.12 Covering situation in subnetwork discussed in Example 6.1.6. cr (v^) < ^(\) and ^(v^) < CT i^ v j^ y^ assignment of necessary 0*s and l's, the rest of Algorithm PP (with the addition of the second suggested modification to take advantage of the pre- assigned values) would follow normally. After pruning has been completed by Algorithm PP, or one of its previously described modifications, for a negative gate network, negative completions (i.e., specifications of values for all vectors in V ) are obtained for the resultant incompletely specified functions, f ' (v _),... ,f (v), realized by gates in N' . Negative completions may be obtained either independently or in combination with the implementations of the negative gates as MOS cells. In either case, pruning may be repeated after a negative completion has been obtained, and it is possible that additional connections may be removed. This occurs since the negative completions may be different from the original functions realized by the gates and may produce new possibilities for cover assignments. Obtaining the configurations of MOS cells implementing the negative gates can involve considerably more calculation than obtaining only simple neg- ative completions, and negative completions are usually sufficient if it is intended to repeat the pruning process. MOS cell configurations can be deter- mined following the last repetition of Algorithm PP. Since negative completions have been discussed extensively in the litera- . , . ., .. . .. . r IM 7l],[Iba 71], [Lai 76] , . ture as related to other synthesis methods " ' and since the exact method used is generally incidental to the presentation of trans- duction procedures, only a simple method will be given here (this method is similar to the one offered in the proof of Theorem 2.k): bhm •,.!.?. Algorithm to obtain negative completions of incompletely specified functions, f ' (v ),..., f ' (v ), realized by negative gates in a ' esulting from Algorithm PP (NC). 235 Functions x^,»..,x^ f f ' (v .j^), . . . ,f ' (v ) are assumed to be expressed in truth table form. Step 1 Select a specific ordering cr, of gates. Let f"(v ) = x. , k = 1, . . . ,n. Step < Initially, let I be the set of all gates in N 1 . "tep Select v. € I such that a (v. ) > cr (v) for every v e I, v / v. . Step j Let IP(v. ) = (v. ,...,v. }. Form a negative completion, f"(v.), J l J s of f ' (v. ) as follows. i i (a) Seek a row, d, of the truth table containing entry * in column v a(- S- ) °f the truth table. If none exists, go to Step 5. (b) If the input vector composed of the d — entries in columns v. , . . - , 1 v. , (f" (v. ),..., f (v. )), is less that or equal to any existing true J s. J l 3 s. l l vector of f"(v. ) (i.e.., the input vectors corresponding to existing 1 entries in column v.), assign the * in column v. the value 1. Otherwise, assign it the value 0. Return to substep (a). : tep [ T < I - (v.). If I is not empty, return to Step 3« Otherwise, terminate the algorithm. The negative completions f"(v ),..., f"(v ) are expressed as columns of the completed truth table. Example 6.1.7 Continuing with the pruning problem discussed in Example 6.1-3, negative completions are obtained by Algorithm NC for the functions realized by gates g , g p , g_ which are given in the truth table in Fig. 6.1.8. The negative completions are shown in Fig. 6.1.13- Algorithm 6.1.1 (PP) is repeated for the network shown in Fig. 6.1.8 whose gates realize the functions given in Fig. 6.1.13. During this second application of the algorithm, two 236 additional connections are pruned from the network. The resulting network and set of negative gate functions are shown in Fig. 6.1.14. Negative completions are once again obtained by Algorithm NC, giving the truth table in Fig. 6.1.15. From these functions, the MOS cell implementation of the negative gate network of Fig. 6.1.14 is easily obtained. It is also shown in Fig. 6.1.15. A third application of Algorithm 6.1.1 (PP) is found to result in no further pruning (the network in Fig. 6.1.15 actually contains the minimum numbers of MOS cells, intercell connections, and FET's). For comparison, an MOS network implement- ing the original negative gate network of Fig. 6.1.1 (discussed in Example 6.1.1) is shown in Fig. 6.1.16. As previously discussed, pruning procedures only remove connections. Next, a transduction procedure will be considered which allows new connections to be added. Let this type of transduction procedure be referred to as 'general' transduction procedures to distinguish them from the pruning type. The general transduction procedure which will be given follows many of the same steps as the pruning procedure Algorithm 6.1.1 (PP). The basic difference is that before the selection of an irredundant input set (Step 6 of Algorithm 6.1.1 (PP)) for a gate v., new input connections are added to v.. These new connections are 1 1 given lowest priority for removal to maximize the possibility of obtaining (in Ctep 6) an irredundant input set containing 'fresh' (i.e., previously non- connected) inputs. Unlike the pruning procedure, the general transduction procedure does not insure a final result having the same or smaller number of connections as the nal network. Should such networks occur, they may of course be simply dis- parable transduction procedures for NOR gates are discussed in ("Cul 75] 237 : 1 X 2 X 3 g l So S-3 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 ] 1 1 1 Fig. 6.1.13 Negative completions obtained by Algorithm 6.1.2 (NC) for functions in truth table of Fig. 6.1.8. Example 6.1.7. O^ x l X 2 X 3 cr "1 cr "2 cr °3 1 * 1 1 ¥■ 1 * 1 1 1 -*(■ 1 1 1 • 1 1 -«- 1 1 -*- 1 1 1 1 1 Fis. 6.1.1U Results of application of Algorithm 6.1.1 (PP) for network of Fig. 6.1.8 whose negative gates realize functions given in Fig. 6.1.13. Example 6.1.7. 238 x l Z 2 x 3 0' °1 g 2 S 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fig. 6.1.15 Negative completions for functions in truth table of Fig. 6.1.14 and MOS cell implementation of cor- responding negative gate network. Example 6.1.7* *1 d o- *i-l j *g-C * 3 lj 3 x ihG3 JH Fig. 6.1.16 MOS cell implementation of original negative gate net- work of Fig. 6.1.1. For comparison with the MOS network of Fig. 6.1.15 obtained through two applications of Algorithm 6.1.1 (PP) (as discussed in Examples 6.1.1, 6.1.2, 6.1.3, and 6.1. 7). 239 carded, or the general transduction procedure may be repetitively applied for a predetermined number of iterations (obtaining negative completions between iterations) while saving only the best result obtained. Empirical experience has shown that even though the number of connections may increase for an application of the general procedure, a subsequent application (for the resultant network) may decrease the number of connections. Algorithm b.1.3 General transduction procedure to add and remove connec- tions from a negative gate network (GP). A network N of n external variables, m output functions, and R negative gates is transformed into a network N' having the same external variables and output functions. Step 1 Select a specific ordering cr, of gates and orderings ov and cr n of gates and external variables (input terminals). Step 2 Set G (c. . _,) -- f . , i = (n + l), . . . , (n + m). =■ — c i,i+R i-n' ' ' Step ; Initially, let I be the set of all gates in N. Step k Select v. £ I such that a (v. ) < cr (v) for every v e I, v f v.. -.- i- Compute a CSPF for v. as follows: G (v ) = G (c ..). c x v.eIS(v.) C 1J Step 6 Find all connections c . . such that c . . does not currently exist in the network and the addition of c . . would not cause a feed-back loop in the network. Add all such connections to the network. Let NIP(v i ) denote the set of new immediate predecessors of v. resulting from these connections, and let OIP(v. ) denote the set of old immediate predecessors. (lP(v i ) = NIP(v i ) U OIP(v.).) Form an ordering satisfying 0" 2 ( v k ) < CT 2^ V P and either v n , v* S OIP(v. ) or v, , v, € NIP(v. ). Gtex^ 7 Select an irredundant input set for v. with respect to G (v. ) as follows : (a) Seek a v. € IP(v. ) such that: J i (i) there exist no indices d,e satisfying G (v.) - f (v.) = 0; g' 6 '(v.) = f^^v.) - 1; and either f^(v) = or (e) f (v) = 1 for every v g IP(v.), v j= v.; and (ii) for every other v e IP(v. ) satisfying condition (i), cr;(v ) < cr;(v ). (b) If no such v. exists, continue to Step 8. Otherwise, J IP(v. ) J ( ci) or equivalently, in f v (v.) after Step 9). The reason is that 1-0 covers are J (d) provided for all existing 0-1 pairs of G (v.) during execution of Step 8 for v.. If an further necessary 0's or l's were introduced into vector G (v.) 3 c J at a later time, there would be no guarantee that the new 0-1 pairs so created would be covered by v.'s inputs. The algorithm excludes this possibility in J Step 9 by immediately changing f(v.) to G (v.) after assigning all 1-0 covers <] c J for v. in Step 8. This can be seen to prevent Step 8 from later assigning ad- J ditional necessary 0's and l's to G (c.) (and hence to G (v. ) and f(v.)). J c x ji' c j j 2*+2 Based on consideration of the two transduction procedures presented above, many variations and extensions can be suggested which emphasize different aspects of the transduction process to produce different results (some, for different objectives). A discussion of these will be left to another occasion. Except for relatively small problems, Algorithms 6.1.1 (PP) and 6.1.3 (GP) require too much computation to be practical for hand calculation. For this reason, the algorithms have been implemented in a computer program to demonstrate and test the feasibility of using the algorithms for larger problems. The computer program implementation and experimental results will be discussed in the following Section 6.2. 6.2 Computer Program Implementation of Transduction Procedures A computer program called MOSTRA (for MOS network TRAnsduction) has been coded in FORTRAN for IBM 360/75J computer to implement Algorithms 6.1.1 (PP) and 6.I.3 (GP) of the preceding section. The program occupies approximately 250K bytes of memory and, with certain exceptions, can handle problems involv- ing networks with up to 10 external variables, 10 MOS cells, and 10 output functions. It is intended that the current program will be expanded at a later time to increase its flexibility. As currently structured, the program accepts a set of output functions for which it first synthesizes, according to the method of , an initial negative gate network. Transduction procedures are then applied to this initial network and the networks subsequently derived from it. This structure was selected for its convenience during experimentation : program, i.e., initial networks did not need to be developed by hand, my pra- applications of the program, it should be modified to accept 2k3 pre-designed networks (such a modification is not difficult). When program- designed initial networks are desired, it is also possible to incorporate ad- ditional network synthesis methods into the program which would afford the user a choice of initial networks. Also, further transduction procedures can be added, and a choice of se- quences in which procedures are applied can be made available for the user. Currently, the user can only choose between repetitive application of the prun- ing procedure and repetitive application of the general procedure (i.e., no combination of the two is available). The selected procedure is applied repetitively, beginning with the original network, until the network cost (de- fined as 1000 x (the number of gates) plus 1 X (the number of connections)) no longer decreases, or for a minimum of two applications. The output of MOSTRA can be determined by the user to be either in the form of a negative gate or MOS cell network. In the former case, the output consists of a listing of connections among gates and external variables and a truth table expressing the functions realized by all gates of the network. For the latter case, in addition to listing intercell connections and cell output functions (in truth table form), configurations of the cell's drivers are print- ed out in pictorial form. Section 6.2.1 will discuss the organization of the program. Following this, the preparation of input data for the submission of synthesis problems to the program is given in Section 6.2.2. Finally, the results of the programmed trans- duction procedures for certain selected problems will be discussed in Section 6.2.3. 2kk 6.2.1 Program organization MOSTRA consists of 12 subroutines: ASGNCV, COMPR, CONFIG, GENER1, IRINPT, MAIN, NEGCOM, OUTPUT, PRUNE1, STEPZ (a system-supplied timing routine), SUBNET, TESTSQ. The general organization of the program is shown in Fig. 6.2.1.1. An arrow from block i to block j denotes the fact that the subroutine represented by block i calls the subroutine represented by block j. The functions performed by the different subroutines are as follows: MAIN (62'7 cards; 57I+ FORTRAN statements) reads input data for each problem, checks it for errors and inconsistencies, stores the required output functions, synthesizes an initial network realizing the functions, and prints heading information for the problem and the synthesized initial network. Sub- routine TESTSQ is then called. TESTSQ (53 cards; 4 3 FORTRAN statements) is called by MAIN to apply dif- ferent sequences of transduction procedures for testing purposes. Logically, the subroutine is an extension of MAIN and the two can be merged after the development of the program is considered complete. The separation of this code from MAIN allows the program to be changed without the necessity of recompiling MAIN. PRUNE1 (109 cards; 8l FORTRAN statements) controls the execution of the pruning procedure. Arrays are initialized, and cells are ordered for consid- eration by the pruning procedure. For each cell, an irredundant input set is first chosen by calling IRINPT. Then, covers are assigned among these inputs by callin . Finally, the resulting CSPF's and intercell connections are printed. The implementation of the pruning procedure incorporates the first two Bted modifications of Algorithm 6.1.1 (PP). 2k$ T— v^ v n v o ->- co u V Ox] w CO n A If IP 2 EH CO 9 M o ft o a o •H -p cti tsl •H a cd bO u o o o o CO u QJ £ 0) n a bC •H 21+6 GENER1 (124 cards; 108 FORTRAN statements) similarly controls the execution of the general transduction procedure. The ordering in which gates are considered for a reevaluation of their input sets (i.e., ordering i < Call GENER1. Simple negative Simpl comp letions Cell \ Complet f ions v. desired or also cell ^< «. ^\ „. , . ^"^Configurations ^n. configurations ^^ \ t fall IJTinrtruLi NETCST = cost of new network. Call CONFIG. (^ a i. i. im l^VJV. . OLDCST = NETCST. NO Return. Fig. 6.2.1.3 Flowchart of subroutine TES 252 Enter subroutine Determine the level of each gate of the network. R is number of gates, Mark, in array CSPE, the and 1 output values required for the network output gates. Order the gates, in array PRNODR, for pruning accord- ing to level in the network. 1 = 1 + 1. Assign a 1-0 cover to one of VI 's remaining in- puts for each 0-1 pair in column VT of truth table P$. NO Print gate outputs and intergate connections. Return. YES VT = PRNODR(l), In column VI of truth table P$, change all entries to *'s except those 0's and l's involved in 1-0 covers assigned to column VI (these assignments have been marked in array CSPF). Determine an irredundant input set for gate VT by calling subroutine IRINPT. Kig. G.P.l.U Flowchart of subroutine PRUNE1. Enter subroutine Determine the level of each gate of the network. Ls number of gates. ->- Order the gates, in array ORDERT, accord- ing to level in the network. V 1=0. Mark, in array CSPF, the and 1 output values required for the network output gates. Assign, by call- ing subroutine ASGNCV, a 1-0 cover to one of VT's remaining inputs for each 0-1 pair in column VI of Print gates' outputs and intergate connections. In column VI of truth table P$, change all entries to *'s except those 0's and l's in- volved in 1-0 covers assigned to column VI (these assignments have been marked in array CSPF). Return . Connect all gates to VI which are not successors of VI and whose input sets have not yet been evaluated by this subroutine. Determine an irre- dundant input set for gate VI by call- ing subroutine TRINPT. Newly con- nected inputs are preferred. Fig. 6.2.1.$ Flowchart of subroutine GENER1. 25*+ Enter subroutine. Chain rows containing O-entries and chain rows containing 1-entries in column VI of truth table P$. For each exist- ing input of VI, determine its numbers of 1 half-covers and half-covers, respectively. (A 1 half-cover is a 1- entry in the same row as a O-entry for VI. A half-cover is similarly defined. ) Determine preference ordering of gates and external varia- bles for retention as an input of VI. Inputs with higher products are more preferred: (no. of 1 half -covers) X (no. of half -covers) . The longer of the two chains for 0- and 1-entries of VI is designated "fast chain" (it will be moved through faster). The shorter is designated the "slow chain." Move to first row in the slow chain. Call the entry of column VI in this row, $SL0W. At this point, no exist- ing inputs of VI are considered essential. Move to next row in slow chain. Let •tSLOW be the entry of VI in this row. List in array HAVBIT, all exist- ing inputs having half covers for $SL0W. Fig. (j.'.'.I.G Flowchart of subroutine IRINPT. Fig. 6.2.1.6 ^Continued) "ark input '[ as a new es- sential input of VI, / k NO Move to next row in fast chain. Let ,f>FAST be the entry of VT in this row. Search for an input of VI which provide;: a 1-0 caver for the 0-1 pair consisting of truth table en- tries $SL0W and ST. Fig. 6. . !1 .6 ( ontinued) 257 For each input determined to be essential, create a new chain of truth table rows (i.e., 'supplemental chains'). Rows are chained in which the essential input provides no half-covers for the entries of the newly evaluated fast chain. Again chain rows contain- ing O-entries and rows containing 1-entries in column VT, but include only those rows in which covers were assigned to non-essential inputs. These chains will be the new fast and slow chains. Within these rows, count numbers of and 1 half- covers provided by each non-essential input. YES Disconnect lowest priority mon-essential input of VI. Reorder existing inputs of VI in array POTCOV: P0TC0V(1 ),..., POTCOV ( I ) are the I essential in- puts to VI ordered by increasing length of sup- plemental chains; POTCOV (I+1),...,P0TC0V(K) are the inputs not yet determined to be essential. Remove non-essential inputs of VI which had no covers marked. Fig. 6.2.1.6 (Continued) , ; : For each new essential input, create a new chain of truth table rows. Chain rows in which the new essential input provides no half-covers for the entries of column VI in rows of the fast chain. Call these 'supplemen- tal chains' of the respective inputs. Reorder existing inputs of VI in array POTCOV: POTCOV(l), ... ,POTCOV(l) are the I es- sential inputs to VI ordered according to increasing length of supplemental chains; P0TC0V(I+1), . . . ,POTCOV(K) are the non-essential inputs to VI. NO Update arrays to reflect new essential inputs YES Remove connections between VI and its existing inputs. Add connections to VT from all inputs determined to be essential. Return. Fig. 6.2.1.6 (Continued) 259 Enter subroutine. Order inputs to VI in array POTCOV according to preference for covering 0-1 pairs of VI. POTCOV(l) is most preferred, etc tables are given highest preference. Among gates: if NEGKEY = 1 (user specified), preference is given to higher »1 gates; if NEGKEY = 2, preference is given to lower level gates. In rows containing 0-entries and chain rows containing 1- antrieF in column VI of truth table P$. The longer of the two chains is designated the "fast chain." The shorter is desig- nated the "slow chain." Form a "supplemental chain" of rows for each input of VI: for external variable inputs, chain rows of fast chain in which the external variable does not provide half-covers for column VI; for gate inputs, chain rows of fast chain in which the cell provides no half-cover for VI which is part of a 1-0 cover pre- viously assigned to the gate (for a previous VI ). re to first row in slow chain. Let the entry for column VI be designated LOW. Form, in array HAVBIT, an ordered list of those inputs having half-covers for $SL0W. Inputs are listed in the same preference ordering in which they occur in POTCOV. List in array ACNCVC, all external variables and those gates listed in HAVBIT whose half-covers of $SL0W are part of 1-0 covers previously assigned the gates. ' ;. 6.2.1.7 Flowchart of subroutine A. r 'GNCV. : .60 YES Move to first row in fast chain. Call the entry of column VI in this row, &FAST. NO Select the input in list ASNCVC whose corresponding supplemental chain is the shortest in length. Designate its supplemental chain as the new fast chain (replac- ing the current one). [■tove to next row in slow chain. $SLOW is the corresponding entry for column VI. YES NO . .1.7 (Continued) ' ect first (most preferred) input, I, in list HAVBIT which provides a 1-0 cover for the - pair consisting of truth table entries $SL0W and $FAST. Move to next row in fast chain. Let $FAST be the entry of VI in this row. Assign the half-cover to gate I for .$FAST by marking array Also, remove the row containing .tFAST from I's sup- plemental chain. Fig. 6.2.1.7 (Continued) 262 5 YES Remove I from list POTGCH. NO If input I's sup- plemental chain is shorter than current fast chain, I's sup- plemental chain becomes the new fast chain. y Assign the half-cover to gate I for .$SLOW by marking array Vi . Add input I ^ list ASNCVC. Add input I to list POTGCH. This is a list of inputs whose supplemental chains are potential can- didates for future use as fast chains. . 6.2.1.7 (Continued) 263 e W H TD ,0 u u O : D *H O • X CD S§ c -p ft -p O Ch O fH CD O & -P 0) «h H O 05 •H -P -P O C O -H Pruning Procedure, M0STRA DIMN of [Yam 76] Best cost with cover preference: l)ex. vars. 2)high level cells 3) low level cells (ORDERING 1) Best cost with cover preference: l)ex. vars. 2) low level cells 3)high level cells (ORDERING 2) Cost of synthesized network 16 5 2 V26/88 y 26/76 4/26/82 4/26/83 17 5 2 4/26/84 4/26/78 4/26/78 4/26/66 18 5 3 6/42/145 6/38/142 6/40/143 6/38/102 19 5 3 5/35/117 5/35/117 5/35/117 5/35/117 20 5 3 6/43/160 6/37/H4 6/38/125 6/39/90 21 6 1 3/21/83 3/20/80 3/20/80 3/20/88 22 6 2 5/39/260 5/33/237 5/35/236 5/35/204 5/36/236* 23 6 3 6/49/279 6/43/279 6/45/281 6/43/234 24 7 1 4/34/2 3 4 4/30/201 4/30/195 4/25/176 25 7 2 5/^5/503 5/44/4.65 5/44/459 5/44/408 26 7 6/57/738 6/56/707 6/56/691 6/54/607 27 8 1 V 38/1+97 4/35/462 4/36/462 4/33/410 28 8 2 i/5oAnv 5/50/1127 5/50/1115 5/50/921 29 8 C763A570 6/63/1481 6/63/1473 6/63/1336 This colutior iavi bhe 'best cost'; however, it has the least number of FET's among those solutions obtained. ■ ' ',.:...! (Continued) given are the lowest attained during the repetitive application of each trans- duction procedure for each synthesis problem. In each case except the one noted in Table 6,2.3.1 (the pruning procedure with ordering 1 for problem 22) a sol- ution with fewest connections also had the fewest FET's. It should be noted that the jell configurations derived are 'unfactored. ' Factoring can reduce the numbers of FET's. To provide some basis for comparison, the results of program DIMN ' are also included. For six of the test problems the prun- ing procedure, with one or both of the two different orderings, achieved results of lower costs than did DIMN, while DIMN obtained results of lower costs in nine instances. Any comparison, however, of the results by MOSTRA and those by DIMN should recognize the fact that MOSTRA is starting with an initial network which is synthesized by a method which does not attempt to minimize the number of intercell connections or MOSFET's used. It is quite possible that the use of a different type of initial network would improve the results obtained by MOSTRA. The pruning procedure with ordering 1 (cover preference: external variables, high level cells, low level cells) reduced the number of connections of the initial network in 66% of the cases. With ordering 2 (cover preference: external variables, low level cells, high level cells), the numbers of con- nections were reduced in 69$ of the cases. For both orderings, the number of FET's was reduced in 86% of the cases. The largest percentage decrease in the iber of connections was 22$ for problem 13 (ordering l). Among problems in which reductions in the numbers of connections were achieved, the pruning pro- cedure with ordering 1 averaged a 10$ decrease while the same procedure with ordering 2 averaged a 9$ decrease. Sightly better improvements were obtained WP with respect to the numbers of FET's Among problems in which reductions in the numbers of FET's were achieved, the pruning procedure with both ordering 1 and ordering 2 averaged an 11$ decrease in numbers of FET's. The largest per- centage decreases were 30$ for problem 7 (ordering 2), and 29$ for problems 9 (both orderings) and 20 (ordering l). For the majority of the problems, the pruning procedure was applied (iteratively) only twice by MOSTRA after synthesizing the initial network. For ordering 1, the pruning procedure was applied three times for nine of the prob- lems. In the case of ordering 2, three applications of the pruning procedure were used for only five of the 29 problems. Two examples are given, in Figs. 6.2.3.2 and 6.2.3.3* in which the initial networks are compared with the best results achieved by applying the pruning procedure. (The networks are shown as they appear in the actual printout. Only the driver sections of the MOS cells are shown. The notation 'UI' in the figures denotes an FET controlled by the output of cell I, while 'XI' denotes an FET controlled by x . Fig. 6.2.3.1 shows an example of this straightforward correspondence between the computer printout of a driver's configuration and the constructed MOS cell.) Fig. 6.2.3.2(a) shows the initial network synthesized by MOSTRA for problem 13. The network consists of 3 cells, 18 intercell con- nections, and 50 driver FET's. After the second application of the pruning procedure (ordering l) starting from this initial netwoj-k, the network in Fig. 6.2.3.2(b) is obtained. This network also consists of 3 cells, but contains only lU intercell connections and 39 driver FET's. The initial network synthesized by MOSTRA for problem 20 is shown in Fig. 6.2.3.3(a). It consists of 6 cells, U3 intercell connections, and 160 driver FET's. After two applica- tions of the pruning procedure (ordering l), the result shown in Fig. 6.2.3.3(b) 273 0— -XI— X3— X5-- -XI— Xh -X2-- U2 — (a) Driver configuration as appearing in computer printout. input from cell 2 (b) MOS cell corresponding to (a). Fig. 6.2.3.1 Example of correspondence between computer printout of a driver's configuration and the constructed MOS cell. 274 CELL: 1 2 3 LEVEL FED BY: / V XI X2 X3 Xk X5 2 / 2/ XI X2 X3 xk X5 3 / 3/ XI X2 X3 xk X5 ** NETWORK COST 3018 CELL 1 C— -xi— X3— xk— X5-- -XI— X2— X3— X5— -XI— X2— X3— X4— 0&-- X5— U2 -X2— Xk— U2 -XI— X5--U2 -XI— X4— U2 -XI— X2— U2 -X2--U3 — CELL 2 0— -XI— Xk— X5— -XI— X2— X5— -X1—X2— X4— -X2— X3 -XI— X3 — CELL 3 C— -X2— Xk— ■X5 ■X3 -XI — TOTAL NUMBER OF DRIVER FET'S IN NETWORK IS 50, 'a) Initial network synthesized by MOSTRA. Fig. 6.2.3.2 Example of pruning results, CELL: 1 2 3 275 u ]VEL FED BY: 1 V XI X2 X3 Xh X5 //< XI X2 X3 Xh X5 1 2/ X3 X5 ** NETWORK COST = 30lU CELL 1 0— -XI— X3— Xh— X5— -XI— X2— X3— X5— -XI— X2— X3— Xk-~ ■Xh— U2— U3 -XU— X5— U2 ■X2— U2— U3 -XI— X5— U2 — —XI—] ih— X5— — XI— X2— X5-- CELL 2 0— — X1--X2— xh— --X2--X3 — XI— X3 CELL 3 0— — X5— — X3— — — TOTAL NUMBER OF DRIVER FET'S IN NETWORK IS 39- (b) Network derived by two applications of pruning procedure (with ordering l). Fig. 6.2.3.2 (Continued) 276 CELL LEVEL 1 /I/ 2 / 2/ 3 / 3/ k / V 5 / 5/ 6 / 6/ FED BY: XI X2 X3 Xk X5 2 3 4 5 XI X2 X3 xk X5 3 1* 5 6 XI X2 X3 Xh X5 1+ 5 XI X2 X3 xk X5 5 6 XI X2 X3 xk X5 6 XI X2 X3 xk X5 ** NETWORK COST = 60if3 CELL 1 0— CELL 2 0— -X1--X3— xk— X5- -XI— X2--X3— U5- -X5--U2--UU -X4~U3~U^ -X1+--X5— U5 ■ -X^— X5— u^ ■ -X3--UU— U5 ■ -X3-- X5--U5 -X3-- xk— U5 ■ -X2-- X5— U5 • -X2-- X^ — U5 -X5-- U3— U4— U5- -X3— X4~ U3— U4- -XI— U3--UU— U5- -XI— X3— X5— U5- -XI— X2-- X5--U4- -Xi+— X5--U4 -X3— UU— U5 -X3— xk— U5 -X2-- tA— U5 -XI— X2— U5 — --0 CELL 3 0— CELL k 0— -X2— X^~ X5— tft- -XI— X5-- U4— U5- -XI— XU— X5— U^- -X1~X3^-X^~U5- -XI— X3--X4— u^- -Xl+— X5— U5 -X2— X5— U5 -X2— Xk— U5 -X2— X3— X4— X5- -XI— X2— X4— X5- -X4— X5— U5 -X3-- X5-- U5 -X3— XU— U5 -X2-- X5--U5 -X2— Xk— U5 -X2— X3--U5 -XI— x4— U5 -XI— X3--U5 -XI— X2--U5 -u6 — — Fig. 6.2.3»3 Example of pruning results. 277 CELL 5 0— -X3--X4— X5- -X2-- Xk — X5- -X2— X3--X5- -X2-- X3— X^- -XI— X4— X5- -XI— X2--XU- -u6 — CELL 6 0— -X5— -XU- -X3-- -X2— -XI— — TOTAL NUMBER OF DRIVER FET'S IN NETWORK IS l60. (a) Initial network synthesized by MOSTRA. Fig. 6.2.3.3 (Continued) 278 LEVEL FED BY: / 1/ XI X2 X3 xk X5 2 3 4 5 / 2/ XI X2 X3 xh X5 3 4 5 6 / 3/ XI X2 X3 xk X5 i+ 5 / V XI X2 X3 xk X5 5 / 5/ XI X2 X3 xk X5 / 3/ xk CELL 1 0— CELL: 1 2 3 k 5 6 NETWORK COST = 6037 —XI— X3— X^--X5- — XI— X2— X3--U5- — X5--U2--UU — XU--UU--U5 — Xh— U3— u*+ -■Oft-- X5--U** — X3— U4— U5 — x3— X5— U5 — X3— X^~U5 — X2— X5— U5 — CELL 2 0— — U3— U^--U5— U6- — X3— Xk— U3— Uk- — X2--X^--X5--U5- — XI— xU— X5--U^- --X1— X3— X5--U5- --X3— X4— U5 — XI— X2— u6 — CELL 3 0— CELL k 0— ■XI— X5— TJ*4- — U5-- ■XI— X*+— X5— ift— ■XI— X3— Xk— U5-- ■XI— X3— X^— U^~ -X4— X5— U5- : ■X2--X5— U5 — ■X2— XU— U5 ■X3— X5— U5— -X2--X4— X5— ■X2— X3— U5 — ■XI— Xif— U5— ■XI— X3—U5-- --0 — CELL 5 0— -X3— Xk— X5- -X2--X3— X5- ■X2— X3— X4- ■xi— xi+— X5- -XI— X2--X4- — CELL 6 Xk TOTAL NUMBER OF DRIVER FET'S IN NETWORK IS Ilk. 'b) Network derived by two applications of pruning procedure (ordering l) Fig. 6.2.3.3 ( Cont inued ) 279 is obtained: a network of 6 cells, 37 intercell connections, and only llU driver FET's. Noting the failure of the general transduction procedure to improve upon the results of the pruning procedure for the 29 test problems, it was con- jectured that the general transduction procedure might be best applied in cases in which a relatively large number of network output functions are required. Such networks seemed to offer more 'flexibility' for the exchange of input connections performed by the general transduction procedure. 28 more test problems were chosen involving arbitrarily selected 4- and 5-variable functions and 3-, 4-, 5-, and 6-output networks. The MOSTRA program was run with these problems in an effort to find problems in which the ability of the general transduction procedure to add new connections was utilized. In the solution of of these problems, new connections were found to have been added to the network. Of these, five problems showing the largest reductions in numbers of connections and FET's were rerun by MOSTRA using the pruning procedure (with ordering 2). From initial networks of costs 7/38/85, 8/47/99, 9/54/98, 9/54/108, and 6/29/48, the general transduction procedure obtained networks of costs 7/37/64, 8/46/80, 9/48/81, 9/51/93, and 6/25/37, respectively, while the pruning proce- dure obtained networks of costs 7/38/85, 8/47/81, 9/49/87, 9/52/84, and 6/27/41, respectively. Discussion of Transduction Approach Judging from the results of the previous section, the transduction approach can obviously be utilized to improve networks synthesized by certain other methods, and the combination of a simple synthesis method and the transduction procedures can itself be considered a synthesis method. 280 Compared with the methods of [Lai 76] (programmed by Yamamoto ' which produce irredundant MOS networks, the transduction approach offers flexibility. Two apparent drawbacks of the transduction approach, however, are: (l) the transduction approach generally requires several iterations (i.e., applications of the transduction procedures) and, hence, generally more computation time and (2) at least for the initial network synthesis algorithm used in the preceding examples, the results of the transduction approach seemed slightly inferior in many cases. The former problem could be minimized by not deriving MOS cell configura- tions until after the last application of a transduction procedure (this de- rivation is generally much more time-consuming than the transduction procedure itself — often by a factor of more than ten). The user is not currently offered such a choice. The latter problem might be lessened by the identification of a more suitable algorithm for initial network synthesis in MOSTRA and/or the imple- mentation of modifications discussed in Section 6.1 which are not currently included in the program. Also, new transduction procedures can be created, and different transduction procedures can be used together for improved results, (in the case of NOR gates, the 'error-compensation' class of transduction pro- cedures were the most powerful found. They were also the most complex. Comparable transduction procedures for MOS networks might also be more powerful than the pruning or general transduction procedures. The creation of 'error-compensation' -type transduction procedures for MOS networks is not considered in this work, however, due to the lack of sufficient avail- able research time. ) ; !8] While the performance of the general transduction procedure was less than anticipated (theoretically, it could have reduced the numbers of cells in some of the multiple -output networks of the test problems, although this did not occur), it does appear useful for networks having several outputs. Also, improvements in the general transduction procedure itself (e.g., more sophisticated methods of deciding which new connections to add and which old connections to retain) or its implementation as part of a computer program (e.g., as discussed in the description of subroutine GENER1 in Section 6.2.1, certain new connections which are possible under Algorithm 6.1.3 (GP) were not permitted by the subroutine) could lead to better results. The greatest potential for the transduction approach, however, is not in competition with G-minimal synthesis methods such as those of [Lai 76], but in another area. As can be seen by the test results in the preceding section, cells in G-minimal networks rapidly grow too large for practical implementation as the number of external variables increases. The transduction approach obviously need not use G-minimal networks as starting points (i.e., as initial networks). Thus, for example, the pruning procedure can be applied to a net- work of practical sized cells (possibly obtained by hand or by a procedure — perhaps employing the transformations of Section 5 — programmed for this purpose), and the result can generally be anticipated to be a reduced network still con- sisting of cells of a practical size. Another possible application of the general transduction procedure is in the combination of two or more separately designed networks into a single network of lower cost. In the case of the general procedure, however, there is a somewhat greater risk that the result, after starting with an initial network satisfying practical limitations, may be '/'-> impractical to implement. In the event of a failure, any impractical networks can always be discarded in favor of the initial network. It is hoped that the current state of the MOSTRA program will be improved with: the capability to accept pre-designed initial networks; the capability to generate initial networks by several different algorithms selectable by the user; the addition of new transduction procedures (possibly some considering maximum fan-out, maximum FET's in series, the division of overly complex cells, etc.); the improvement of existing transduction procedures; and the capability of the user to control the types and sequences of transduction procedures to be applied to a given problem. It may be of interest to make some final comments on the success of the transduction approach for NOR network synthesis (see [Cul 75], [CLK 7^], [KC 76] , [KM 76], [KIM tbp], [KLCM 75], [Lai 75], [LC 7^], [LC 75], [LK 75]) versus the results obtained thus far of the transduction approach to negative gate (MOS cell) network synthesis. In the NOR case, initial networks chosen for the transduction procedures generally contain a significant percentage of 'redundant' gates (i.e., a number of gates in excess of the minimum number required to realize the given function or functions). This is due to the relatively large amount of computational effort required to obtain an initial network with an optimal or near-optimal number of gates (in fact, one of the reasons to use the transduction approach ic to avoid this very type of computational effort). On the other hand, it is relatively easy to obtain a negative gate network having the minumum number of gates required to realize a given function (in the multiple -output case, it is to obtain a network of the minimum number of gates, but networks 283 having a near-optimal number are obtained as easily as for the single-output case). If such initial networks are used (as in the preceding experiments), the transduction procedures for negative gate networks obviously have little or no possibility to remove gates and fewer chances to 're-configure' (i.e., change the interconnection pattern among external variables and gates) net- works than in the NOR gate case. This, in turn, means fewer opportunities to pursue in the search for solutions of lower cost. In the case of NOR networks, many of the redundant gates in the initial networks can be easily removed by transduction procedures. Perhaps a more significant consideration is the greater ' interdependency' among negative gates (as opposed to NOR gates) caused by the required 1-0 covers. As previously mentioned, the number of covers required for a negative gate is generally much greater than that for a NOR gate in networks with the same number of external variables. This, coupled with the fact that the minimum number of negative gates required to realize a given function (or set of func- tions) grows very slowly (proportional to log p ) with an increase in the number of external variables, makes the removal of connections from negative gate net- works with optimal or near-optimal numbers of gates exceedingly difficult, if not impossible, as the number of external variables grows. In the case of NOR networks, many redundant connections can exist even in a network of an optimal or near-optimal number of gates. In other words, if Gl-minimal negative gate and NOR gate networks having the same number of gates were compared, the negative gate networks would, on the average, contain many more connections. It is conjectured that in many of these cases, the negative gate networks for a given function or functions may require the maximum possible numbers of connec- tions (i.e., no connections can be deleted from the generalized form of a feed- forward network of negative gates in Fig. 2.11). 284 For these reasons, transduction approach improvements of network costs in the negative gate case can not be expected to be of the same magnitude as those in the NOR gate case. Furthermore, applying transduction procedures for negative gate networks can be anticipated to require significantly more compu- tational effort. While established transduction procedures for NOR gates can serve as guide- lines for the development of corresponding types of transduction procedures for negative gates, the differing characteristics of negative gates (e.g., the stronger covering requirement, the 'non-fixed' function of a negative gate, the 'connectability' of any external variable or gate not causing a loop in the network (NOR gates have more restrictive conditions for connectability), etc.) will require much more than a straightforward adaptation of the transduction procedures for NOR gates. 285 7. IRREDUNDANT NETWORKS AND TEST SET GENERATION [Lai 76] gives an algorithm which can synthesize G-minimal, single- output, irredundant networks of MOS cells for given completely or incompletely specified functions (Algorithm 8.6 in [Lai 76]). The term 'irredundant' means that no FET or group of FET's can be extracted (i.e., replaced by a short- or open-circuit) from the network without changing the desired (specified) out- put of the network. A network which is irredundant is a 'diagnosable network. ' Diagnosable networks of MOS cells are also treated in [Pai 73]. The net- works synthesized by the algorithm of [Pai 73] are, however, 2-level, non-G- minimal networks, and require the accessibility of auxiliary test points within the network. The networks synthesized by the algorithm of [Lai 76] require no extra terminals for the administration of tests to detect faulty FET's (i.e., only network inputs and outputs need be accessible). Sets of input vectors are proposed in [Lai 76] which constitute 'test sets' for the detection of certain classes of faults. These test sets are quite large, however (the test for all possible faults being V itself), due, at least in part, to their 'universal' nature . This section (Section 7) will propose a method for obtaining smaller test sets 'tailored' to a particular irredundant network synthesized by the algo- rithm of [Lai 76]. First, a background must be established for the presentation of the algorithm of [Lai 76] and the algorithm for test set generation. The following notation and definitions are adopted from [Lai 76]: Since the algorithm requires a number of second level cells equal to the number of prime implicants in an irredundant disjunctive form expressing the desired function, there can be up to 2 n-1 cells in the second level - substantially more than the maximum of L (n + l)/2J cells in the second level of a 2-level, G-minimal network. 286 An incompletely specified function will be denoted f . A completion of f will be denoted f. A completely specified function can be considered a special case of an incompletely specified function, i.e., it is possible that f s f . Definition 7«1 An FET is said to be in the stuck-at-short failure mode (or stuck-at-short fault ) if it becomes permanently conductive. Definition 7»2 An FET is said to be in the stuck-at-open failure mode (or stuck-at-open fault ) if it becomes permanently nonconductive. The justification of this fault model is supported by an engineering analysis in [SK 69] as discussed in [Pai 73]. Definition 7«3 An MOS network is said to be diagnosable if and only if every individual or set of stuck-at-short and/or stuck-at-open faults in the network (referred to as single fault and multiple fault, respectively) can be detected by a comparison of the network's actual output with the required (error-free) output function. Note that this definition of 'diagnos ability' only requires the detection of faults and not the location of faulty FET. It is clear that a network is irredundant if and only if it is diagnosable. Let N denote an MOS network consisting of k driver FET's, D ,...,D, , and realizing a function f (N) (the actual output of a network is always com- pletely specified in terms of its inputs) of n variables. Network N with one or more faulty FET's is denoted by N(F) where F is the set of faulty FET's with their respective failure modes expressed as D. if D. is stuck-at-short and D i if D. is :;tujk-at-open. f(N(F)) denotes the output function of N(F). 287 Also, let f(N,A) and f(N(F),A) denote the outputs of networks N and N(F), respectively, for input vector A e V . Definition 7.U A test for a faulty network N(F) is an input vector A e V for which f(N,A) £ f(N(F),A). Definition 7.5 A pure output cell fault (POCF), F , for a network of IT MOS cells is a single or multiple fault which involves FET's only in the output cell. )efinition 7»6 A non-pure output cell fault (NPOCF), F , for a network of MOS cells is a single or multiple fault which involves at least one FET which is not in the output cell. Let denote the set of all possible POCF's and <£> denote the set of p K n all possible NPOCF's in a network N. Obviously, the set of all possible single and multiple faults, $. ,is the union of and . * ' t' p n lefinition 7.7 A sufficient test set , A, for a class of faults, 1>, in a network N of MOS cells is a set of input vectors, Ac V, such that for each fault F € $ there exists an input vector, A e A, satisfying f(N,A) f f(N(F),A), i.e., A is a test for N(F). lefinition 7.8 An inverse pair in C (f ) is an ordered pair of vertices, (A,B), A,B e C such that: (1) A > B; (2) f(A) = 1 and f(B) = 0; and (3) For each vertex C for which A > C > B, f(c) = *. >'■;-, Note that in the special case where AB is an inverse edge, (A,B) is an inverse pair. Definition 7«9 The characteristic input set of an incompletely specified function f, denoted S (f), is the set of vectors each of which is in at least one inverse pair of C (f). The following theorem is demonstrated in [Lai 76]. Algorithm DIMN (from [Lai 76] ) will be given later. Theorem 7*1 The characteristic input set, S (f ), for an incompletely specified function f is a sufficient test set for the set of all possible non- pure output cell faults, $> , for a network N synthesized by Algorithm DIMN for f . The next theorem, also appearing in [Lai 76], is clear from preceding definitions. Theorem 7.2 Set S = (A|f(A) f *}, i.e., the set of specified vectors for f, is a sufficient test set for all possible single or multiple faults, $,, in a network N synthesized by Algorithm DIMN for f. Although this theorem gives the entire set of 2 input vectors, V , as a sufficient test set when f is a completely specified function, non-irredun- dant networks may require more than 2 tests (auxiliary test points are needed) i For example, one network discussed in [Pai 73] for which n = 3 requires nine tests for the output cell alone although the number of different input vectors is only 2 3 = 8. 289 Algorithm DIMN can, in general, synthesize more than one ir redundant network to realize a given function f. Test sets given in Theorems 7.1 and 7.2, however, depend only on f and not on the specific synthesized network. In this sense, these test sets are 'universal.' sample 7.1 A completely specified function f is shown in Fig. 7.1. Ey Theorem 7»1> a sufficient test set for in any network N synthesized by Algorithm DIMN for f consists of 13 input vectors: f(Hll), (1101), (1011), (0111), (1100), (1010), (0110), (1001), (1000), (0100), (0010), (0001), (0000)]. By Theorem 7*2, a sufficient test set for <£> in the same networks consists of all lb input vectors in VV. A considerably smaller sufficient test set for in a particular network synthesized by Algorithm DIMN for f will be derived in a later example through the use of a proposed test set generation algorithm. Suppose there exist two functions, f and f p , related in the following manner: (l) for all vectors A e V which are specified vectors of both f and f p , f, (A) = f p (A); and (2) the number of specified vectors of f, exceeds the number of specified vectors of f p . Further suppose that Algorithm DIMN can synthesize the identical irredundant network N for both f, and f_. Then, by Theorem 7.2, the set of specified vectors for f ? is a sufficient test set for J>. in N. Hence, although f.. may have many more specified vectors than f p and the sufficient test set given by Theorem 7.2 for network N synthesized for f would include all of these specified vectors, the smaller set of specified vectors for f will actually suffice. Therefore, the problem of finding a smaller sufficient test set for \ (than that given by Theorem 7.2) in a net- work N synthesized by Algorithm DIMN for a function f, can be solved by finding a function f , having fewer specified vectors, for which Algorithm DIMN can The number shown above each ver'-ex is the input vector corresponding to that vertex. 290 cu •H H TD H O ,0 O J3 w CO (1) ho -•a cu 0) w cu g M H f O Ch • • • > x n ' (2) (u 1 ,...,u i ) is a NFS n (i,u i ); (3) u. ,...,u _ are completely unspecified functions (i.e., all com- ponents of the vectors representing these functions are *'s); and (k) u = f is an incompletely specified function with respect to x_,...,x . A set of complete specifications, u. .,..., u_. - f, of u. ,,..., u„ . , u D = f , l+± i\ 1+J. R— J K with respect to x ,...,x , results in a completion of NFS X (R,f) , (u , ...,il = f). i / ~"\ A feasible NFS (R,f) is one for which there exists at least one completion of NFS n (R,f) which is a NFS (R,f). Such a completion is called a feasible completion of NFS (R,f ) . Any completion which is not an NFS (R,f ) is called an infeasible completion of NFS X (R,f) , and an infeasible NFS 1 (R,f) is one for which every completion is an infeasible completion. Only the case in which R = R~ will be important for subsequent discussion. 292 The following three algorithms, given in [Lai 76], will be incorporated into Algorithm DIMN. Algorithm 7»1 Algorithm for conditional minimum labelling of an n-cube for a feasible NFS X (R,f) ( CMNL ). The conditional minimum labelling of C for a feasible NFS 1 (R,f) (R = R~) is a feasible completion of MFS 1 (R,f), denoted NFS 1 (R,f ) = (u , ...,u. , u. , . . . ,u , f), for which, in C (u-,...,u./u. _,..., u„_, f), the label I (A; ~\ f i XL^,...,U^, u_ i+1 , . . . ,u R _ 1 , f), denoted If^ (A), assumes for every A e C the minimum possible value among all feasible completions of NFS 1 (R,f). n l f >if7\ - v o R ~ k . Step 1 If f(l) = *, assign IT'^l) = Z 2 il (l); otherwise, assign mn k=1 k L mn i( ^ = * 2 R "\(1) + f(l). Set w = n. k=l Step 2 w = w - 1. If w < 0, go to Step k. Step 3 For each vertex A of weight w, let Q be the set of all vectors of weight w + 1 such that B > A for every B e Q A , and then assign as L f,:L (A) ' ° mn v ' the smallest binary integer satisfying the three conditions: (i) The k-th most significant bit of I^U) is u. (A), k = l,...,i; If f(A) j= *, the least significant bit of L f,1 (A) is f(A); and mn (iii) if' 1 (A) > L f,i (B) for every B € Q A . mn — mn Go to Step 2. ■"tep *+ The k-th most significant bit and the least significant bit of are denoted u^A) and f (A), respectively, for each A e C . The feasible completion NFS^(R,f) ■.-. (u n ,...,u., u. , . . . ,» , , f ) of NFS^R.f) has been obta : 293 Algorithm 7.2 Algorithm for conditional maximum labelling of an n-cube for a feasible NFS 1 (R,f) ( CMXL ). The conditional maximum labelling of C for a feasible NFS 1 (H,f) ( R = H ) is a feasible completion of NFS X (R,f), denoted NFS 1 (R,f) = (u n , . . . ,u. ,u. , , u , N n n 1' ' 1' i+l' ' R-i> f), for which, in c n (^ 1 ^--^.,u i+1 ,...,u R _ 1 ,f), the label 0(A; U;L , . . . .u^u , ^ "~\ fix '" ,U R-l ,f ^ denote d, L^ (A), assumes for every A € C the maximum possible value among all feasible completions of NFS X (R,f). n v ' ' SteP 1 ^ ?(0) = *, assign l£' X (0) = L 2 R_k n(0) + 2 R ~ X - 1; otherwise i . k=l k assign L^CO) = Z 2 R_k i^(0) + 2 R " i - 2 + ?(o). Set w = 0. k=l Step 2 w = w + 1. If w > n, go to Step h. Step ; For each vertex A of weight w, let Q, be the set of all vectors of weight w - 1 such that A > B for every B € Q, , and then assign as L ,X (A) the largest binary integer satisfying the three conditions: -P ' (i) The k-th most significant bit of L ,X (A) is u.(A), k = l,...,i; ii) If f(A) £ *, the least significant bit of L f ' X (A) is f(A); and "(iii) ^(A) < ^(B) for every B € Q A « Go to Step 2. Step The k-th most significant bit and the least significant bit of f i ^ ~ L ' (A) are denoted u, (A) and f(A), respectively, for each A e C . The -•— *- j\. n /\ ± „ ^ ^ £ i ~ feasible completion NSF (R,f) = (u , ...,u., u. ,...,il , f) of NFS (R,f) has been obtained. lefinition 7.11 The maximum permissible function u. for a feasible partially specified negative function sequence of length R~ and degree i for function f, NFS (R f ,f) = (u ,, . ..,u., u. ,...,u _i> f ) is an incompletely specified function for u. . such that: 29k (1) u. 1 is negative with respect to x , ...,x , u..,...,u.; (2) every negative completion u. , of u. . yields a feasible NFS (R.p,f) -x- -x- ~ = (u.^ . . . >u i+1 , u i+2 , . . . ,u R _ ± , f ); and (3) any function u! which is not a negative completion of u yields i+1 * * ~\ an infeasible NFS n (R f ,f) = (u^. . . ,\i^, u£ +1 , u i+2 ,...,u R _ ± , f). Algorithm 7*3 Algorithm to obtain the maximum permissible function u. for a given feasible KFS 1 (R,f) = (u , . ..,u., u ,...,u , f) (MEF). Step 1 Obtain the completion NFS (R,f) = (u , . ..,u., u. _ , . . . ,u_ , f ) of NFS (R,f) according to Algorithm CMNL. Step '<. Obtain the completion NFS (R,f) = (u..,...,u., u. , ...,u ., f) of NFS 1 (R,f) according to Algorithm CMXL. Step 3 For each vertex A e C : — - n (a) assign u. (A) the value if and only if u. _ (A) = u. . (A) = 0; (b) assign u. , (A) the value 1 if and only if u. (A) = u. _ (A) = 1; (c) otherwise, assign u. n (A) the value * (i.e., A is an unspecified vector for u. _ ). l+l The validity of these algorithms is demonstrated in [Lai 76]. On the basis of the preceding definitions and theorems, Algorithm DIMN of [Lai 76] can now be given: Algorithm "J.k Algorithm to design an irredendant MOS network with a minimum number of cells (G-minimal) for a given function f ( DIMN ). Step 1 Let NFS n (R,f) :. (u^ . . . ,u R-1 , f). (R = R~ is the minimum number of cells necessary to realize f. This value, if unknown, can be found during t execution of Step 2, i.e., after applying Algorithm CMNL to obtain ,f).) Set i = 0. :• (5 Step 2 Apply Algorithm MPF to obtain the maximum permissible function u. +1 for NFS*(R,f). Step 3 Obtain a complemented irredundant disjunctive form or a complement- ed conjunctive form for a negative completion of u. with respect to x...... l+JL 1 X , u 1 ,...,u i such that the deletion of any literal, term, or alterm from the expression would result in a function which is not a negative completion of u. , ([Iba 71] and [Lai 76] offer algorithms which produce such expressions). From this expression, create an MOS cell configured in the usual way (i.e., conjunctions (or terms) correspond to connections in series, disjunctions (or alterms) correspond to connections in parallel). Let u. denote the function realized by this cell 'completely specified with respect to x , . . . ,x ). ' ■: :: If i = R - 2, create an MOS cell for f as in Step 3 and terminate the algorithm. Otherwise, set i = i + 1 and return to Step 2. The following theorem is demonstrated in [Lai 76]. Theorem 7»3 A network of MOS cells synthesized by Algorithm DLMN for a function f is irredundant with respect to f. Due to the flexibility in Step 3 of Algorithm DLMN, more than one ir- redundant network for a given f can be synthesized in general. It should also be noted that the special expressions required in Step 3 are relatively easy to derive due to the fact that the functions involved are negative functions rather than general functions. xample 7.2 Suppose an irredundant, G-minimal network of MOS cells is desired for function f of Example 7.1 (shown in Fig. 7-1 )• In Step 2 (which is actually Algorithm MPF) of Algorithm DLMN, the NFS, (3,t) and NFS^(3,f) are 296 II 31

• • • • e CJ CO 00 • • • w H 297 T3 •H -P C O U OJ bO •H 298 T3 1 •H ■s O o CM bO •H [x. 1000 (e) NFSjJ(3,f) = (u-^u^f) ?ig. 7.2 ( Cont inued ) 300 first obtained, by Algorithms CMNL and CMKL, respectively, as shown in Fig. 7.2(a). A comparison of u, and u, then results in u.. as shown in (b). In Step 3 of Algorithm DIMN, any of the three expressions (x ), (x. ), or (x x ) could be selected. Assume x is chosen: u, = x . The corresponding MOS cell configuration will be given later. Returning to Step 2, NFS) (3,f ) = (x , Up, f = f ) and NFS, (3,f) = (x , u , f = f ) are obtained as shown in (c). The resulting u p is given in (d). In Step 3, let x x s, x.u be the expression chosen for the second cell of the network. Since R = 3, NFS. (3,f) = (u, y u o> f) is a completely specified minimum NFS with respect to x , x , x (see (e)). In Step h, the synthesis is completed, letting XpX.u., •/ x,u s/ u u be the expression selected for the output cell. The corresponding G-minimal, ir- redundant network of MOS cells is shown in Fig. 7«3- The sufficient test sets for $ and $, determined in Example 7*1 can be used to diagnose this network (as well as other possible networks resulting from Algorithm DIMN for f). The sufficient test set (for cB ) generation method which will be proposed can be applied subsequent to the synthesis of a network N by Algorithm DIMN (the test set generation algorithm to be given will be stated for application in this manner), but it will be most efficient if combined with Algorithm DIMN itself. This is due to the fact that certain information derived during the application of Algorithm DIMN is also needed for the algorithm generating the test set. A generated sufficient test set will not, in general, be a suf- :ient test set for networks other than a particular N generated by Algorithm DIMN for the given function. The following definitions will be needed for the presentation of the pro- posed test set generation algorithm, Algorithm TSG. 301 "£, J- X on w Tx. X X > N on Tv, x H X > J- IX CO X T3 CD IsJ •H CO CD J2 •P c >> . w oj ^) t- u O CD > H •P ft cu e C CO -P £ c cd c •n -h c 3 B ^o : a CU H *n O *h •H S ^4J H -rH Cd f-i B O ta •H < e , i :>> o ,a PO • : • h .-; ■ 302 Definition 7 .12 For a given NFS (R,f) = (u^...,^, Si+i» • • • *&ui' £) and corresponding labelled n-cube, C (u_, ...,U., u. , • * • >Hr_i' — ^ ^ n wil ^- cl1 every vertex A e C has the label L ' (A) = i(A: u_,...,u., u. . ,...,u_ _ , f ) , <* n mn ± i — l+l — R-l' — - a vertex B is said to be an upper-supportive vertex ( USV ) of a vertex A, with respect to the conditional minimum labelling, if and only if: (i) BA is an edge of C ; rr (ii) I^ i (A)> I 2 R " k u k (A) +1; and k=l (iii) The label, 1/ (A), which would result from Step 3 of Algorithm CMNL for vertex A if the label L ' (C) were for every vertex C, C ^ B, in the set {c|CA is an edge of C } (L ' (b) retaining its original value), satisfies Not every vertex in such a labelled n-cube has a USV, and some may have more than one. Obviously, the vertex 1 has no USV since no vertex B satisfy- ing Bl exists. In Example 7.3 which will be given after the following def- inition, examples of other vertices without USV s can be seen. Definition 7.13 For a given NFS 1 (R,f) = (u , ...,u., u. , . . . >u > £) and corresponding labelled n-cube, C (u ,...,u., u , . . . ,u , , f), in which every vertex A € C has the label L ,X (A) = l(k\ u n ,...,u., u. ..,..., u„ . , f), n mn K y v ' 1' ' l' — 1+I 7 — R-l — a sequence of vertices (B- , . . . ,B/?) is said to be an upper- support i ve chain C) of a vertex A, with respect to the conditional minimum labelling, if and only if: B^B ? , B^B ,...,B^_ 1 B^, B^A are edges of C n ; B. is an upper-supportive vertex of B. . , i = 1,.. .,& - 1, and B« is an upper-supportive vertex of A; and 303 (iii) No upper- supportive vertex exists for B. . If a vertex has no USV, its USC is the null chain. Several USC's may exist for the same verte . Example 7.3 The conditional minimum labelling corresponding to NFS?(3,f) in Example 7.2 (see Fig. 7.2. (a)) is reproduced in Fig. 7.h. All USV's for vertices in the U-cube are shown by arrows (not to be confuted with directed or inverse edges) from the USV to the vertex it "supports." Only vertices (1111) and (1110) have no USV's. Several vertices (e.g., (1000), (0100)) have three or more USV's. Two of several possible USC's for vertex (0100 ) are: ((1111), (1101) ,(1100)) and ((llll), (0111), (0110)). Definition 7.IU For a given NFS (R,f) = (u_,...,u., u. , ,...,u„ T , f) and corresponding labelled n-cube, C (u , ...,u., u. , ..., u , f ), in which f ■? ^ /S " •*> every vertex A e C has the label L ' (A) = i(A; u,,...,u., u. , .....u_ , , f), J n tax v ' v ' 1' ' i' i+I' ' R-l' a vertex B is said to be a lower-supportive vertex ( LSV ) of a vertex A, with respect to the condtional maximum labelling, if and only if: (i) AB is an edge of C ; „ 1 n (ii) L f}± < I 2 R "\l (A) + 2 R " i - 2; and mx . . k ' k=l (iii) The label, L'(A), which would result from Step 3 of Algorithm CMXL for vertex A if the label \^(C) were 2 R - 1 for every vertex C, C ^ B, in the set (clAC is an edge of C } (L ,X (B) retaining its original value), satisfies 1 ^ & n mx L»(A) = I^Wa). mx v Definition 7.15 For a given NFS (R,f) = (1^,...^, U I+1'"* , ' U M' f ^ and corresponding labelled n-cube, C (u_,..,,U., u i+1 , . . . ,u R _ 1 , f), in which ... ^ f i ^ 7t\ every vertex AeC has the label L^ (A) = 4 (A; u 1 ,...,u i , u i+1 » • • • > u ;. ; _!^ f '> 30U a sequence of vertices (B, ,...,Bn) is said to "be a lower- supportive chain ( LSC ) of a vertex A, with respect to the conditional maximum labelling, if and only if: (i) AB p BgBg^, B^_ 1 B^_ 2 ,...,B 2 B 1 are edges of C n ; (ii) B. is a lower-supportive vertex of B. _,i = x,...,l - 1, and B« is a lower- supportive vertex of A; and (iii) No lower-supportive vertex exists for B.. . If a vertex has no LSV, its LSC is the null chain. /v Example 7«^ The conditional maximum labelling corresponding to NFS. (3,f) in Example 7*2 (see Fig. 7* 2(a)) is reproduced in Fig. 7«5« All LSV's for vertices in the h- cube are shown by arrows from the LSV to the vertex it 'supports.' Only vertices (1000), (0100), and (0000) have no LSV's. Several vertices have three LSV's. One LSC for (llll) is: ((1000), (1010), (1011)). The four preceding definitions are actually slightly more general than they need be for use in Algorithm TSG. Alternative definitions will be dis- cussed later, but these are somewhat more complex and less convenient for hand calculation. Definition 7.16 Let u. , be an incompletely specified negative function and u . _ be a negative completion of u. with respect to x , ...,x , u , ..., u. . A vertex A e C , . corresponding to vector A € V .is said to be a branch- n+i ^ & n+i determinative vertex ( BDV ) for u. with respect to u. if and only if: A :i pecified) false vector of u. , i.e., u. (A) = 0; and If {B.,...,B,} B. c V . , j = l,...,k, is the set of minimum false 305 0000 > B is USV of A Fig. 7.U Illustration of USV's for Example 7.3. B is a LSV of A Fig. 7-5 Illustration of LSV's for Example l.h. 306 vectors of u. _, A > B. for exactly one B., 1 < j < k. (Vector B. will be referred to as the minimum false vector of u. - corresponding to branch-de- terminative vector A. ) For an arbitrary negative completion, u. , of u. , BDV's may not exist. However, the concern here will be with certain 'irredundant' completions of u. , (used in Step 3 of Algorithm DIMN) for which every minimum false vector will have one or more corresponding BDV's. Definition 7-17 Let u. , be an incompletely specified negative function and u be a negative completion of u. with respect to x , . . . ,x , u, , ...,u.. A vertex A € C . corresponding to vector A € V .is said to be ' l n+i n+i a blocking vertex (BV) of a branch-determinative vertex B e C . for u. , with respect to u. if and only if: (i) A is a (specified) true vector of u. , i.e., u. _ (A) = 1; and (ii) For the minimum false vector C € V . of u. , corresponding to B, n+i l+l * & ' at least one vector D e V . exists such that CD is an edge in C . and D < A. n+i & n+i - A complete set of blocking vertices for branch -determinative vertex B is a set of vertices {A , . . . ,A«} such that: (i) Each vertex A., j = l,...,k, is a blocking vertex of B; and J (ii) If C is the minimum false vector of u. corresponding to B, then for every vector D € V . such that CD is an edge in C . , there exists at n+i & n+i' least one A. e Q such that D < A.. - J A complete set of BV's for a BDV need be neither unique nor irredundant (in the sense that the removal of a vertex from the set would not result in a complete set of BV's). Example 7.5 Consider the function u (shown in Fig. 7.2(d) as a function of X-, , . , x^) of Example 7.2 and its selected negative completion with respect to x_, \ . , x. , u , u = x i x ? v X U U V of the same exam P le « u o as an incompletely specified function of five variables, x , x , x , x,, u , is shown in Fig. 7.6. Vectors ( 11110 ), ( 11011 ), ( 11001 ), ( 10011 ), ( 01011 ), and (00011) satisfy the first condition (see Definition 7.16) necessary for being a BDV for uL. Since the minimum false vectors of \i are (11000) and (00011), vectors (11110), (11001), ( 10011 ), ( 01011 ), and ( 00011 ) also satisfy the second condition necessary for being a BDV for u p . (11011) does not satisfy the second condition since there are two minimal false vectors less than vector (11011). Minimum false vector (11000) or u corresponds BDV's ( 11110) and (11001). Minimum false vector ( 00011 ) of u 2 correspond BDV's ( 10011 ), (01011), and ( 00011 ). BV's of BDV ( 11110 ) are: ( 10110), (OHIO), ( 10100), (01100), (10001), and ( 01001 ). A complete set of BV's for BDV (11110) is {(10110), (01110)} (others also exist). BV's of BDV (10011) are: ( 10110 ), (OHIO), (10001), (00110), (01001), and (00001). One complete set of BV's for BDV (10011) is ((10110), (10001)}. Algorithm TSG for the generation of a sufficient test set for all faults of an irredundant network N synthesized by Algorithm DIMN can now be given. The algorithm is stated for the case in which the complement of an irredundant disjunctive form (rather than the complement of an irredundant conjunctive form) has been chosen for each U in Step 3 of Algorithm DIMN during the .thesis of network N. The case in which the complemented irredundant con- junctive forms are chosen in Step 3 for some U. - can be treated in a similar manner and will not be given explicitly here. 308 CD H I XI w o CM O •H -P O S3 faO g 0) O CM H W -p P C H o H cfl CD O •;0 I Algorithm y.5 Algorithm to generate a sufficient test set for all possible single and multiple faults, , in an irredundant network of MOS cells, N, synthesized by Algorithm DIMN for a given function f ( TSG ). Let u.,...u be the functions for which the complemented irredundant dis- junctive forms were selected in Step 3 of Algorithm DIMN to determine the con- figurations of the MOS cells of network N. Also, let u, , . . . ,u be the maximum permissible functions obtained in Step 2 of Algorithm DIMN during the synthesis of network N, and let u_= f . Step 1 Set i = 0. Initially, let the set T = 0. i = i + 1. If i > R, set T constitutes a sufficient test set for $>. of N; terminate the algorithm. Otherwise, go to Step 3* Step For the pair of functions u. and u.: (a) Determine all minimum false vectors of u.: C,,...,C 1 . (b) Determine the branch-determinative vertices for u. with respect to u.. Corresponding to each minimum false vector, C, select one corresponding X J branch-determinative vertex B., j = l,...,k. Let Q denote the set {B 1 , 'V BV r (c) Select a complete set of blocking vertices, Q = IA. ,,..., A. }, for each B., j = l,...,k. Step Let R BDV ,R? V ,...,^ V be sets of n-dimensional specified vectors of BDV BV u. corresponding to sets of (n + i) -dimensional vectors of u^, Q , 0^ , ...,Q^ V , respectively (i.e., each vector (a^.. • ,* n+± ) f° r ^ corresponds to the vector (a.,...,a ) for u^). (a) For each vector B (D ,...,D £ ), of B with respect to NFS^" 1 (R,f), and set T^=T U {B^,. . . ,Dg). (a) For each vector B 6 R BI)V , determine a lower- supportive chain, 310 RV RV (b) For each vector A € R U . . . U R, , determine an upper- supportive chain (D n ,...,D«) for A with respect to NFS 1 " (R,f), and set T<^= T U (A,D n , ...,Dj. Return to Step 2. Example 7.6 Consider, once again, the function f in Fig. 7.1 and the cor- responding irredundant network N of Fig. 7*3 synthesized (in Example 7-2) by Algorithm DIMN to realize f . Suppose a test set for the set of all possible faults in N, <$> , smaller than that given by Theorem 7-2 is desired. Let Algorithm TSG be applied for network N and function f = f . The expressions for u , u , u selected in Step 3 of Algorithm DIMN (see Example 7«2) during the synthesis of network N are: u 1= x 3 u 2 = Xl x 2 v x i+ u 1 u = XgX^ v x^u 2 v u 1 u 2 . The maximum permissible functions, u and u p , developed in Step 2 of Algorithm DIMN are shown in Fig. 7.2(b) and 7.2(d), respectively, u = f. Initially, T is the empty set. In Step 3a of TSG, vector (0010) is found to be the only minimum false vector of u . (llll) is found, in Step 3b, to be the only BDV for u_, with respect to u . Thus, C is (0010) and B is (llll), and Q ((llll)]. In Step 3c, a complete set of BV's for B is selected: Q {(1000)}. In Step h, R BDV = {(llll)}, R BV = {(1000)}. A LSC, ((1000), (1010), (1011)), for vertex (llll) is chosen in Step ka, and an USC, ((llll), (1011), (1010)), for vertex (1000) is chosen in Step 'rt>. Set T following Step k is: (llll), (1011), (1010), (1000)]. Returning to Step 3 for u 2 and u 2 , : (00011) are found to be the minimum false vectors of .BDV .BV Up. As discussed in Example f.k, five vertices are BDV's for u . Selecting two of these, B 1 = (11110) and B = (10011), to correspond to C and C , respectively, the set Q = {(11110), (10011)1 results. As also discussed in Example J.k, {( 10110 ),( 01110 ) } = Q^ V is a complete set of BV's for BDV (1110), and {(10110), ( 10001 )} = Q^ V is a complete set of BV's for BDV(lOOll). In Step h, R mv = {(nil), (looi)}, r^ v = {(ion), (oiii)}, r* v = {(ion), (iooo)}. a LSC for (1111) with respect to N?sJ(3,f) is ((1011)); a LSC for (1001) is ((1000)); an USC for (1011) with respect to NFsJ(3,f) is ((llll)); an USC for (0111) is ((1111)); an USC for (1000) is ((1001)). (These selections can be easily verified by the use of Fig. 7.2(c) in which both NFS^(3,f) and NFS. (3,f) are shown.) Following Step k, T = { (llll), (1011), (1010), (1001), (1000), (0111) } . Continuing the algorithm for u and u , the final set T = { (llll), (1101), (1011), (0111), (1100), (1010), (1001), (1000)}, (1101) being added as a BDV for u with respect to u , and (1100) being added as a BV. Set T is a sufficient test set for network N realizing function f. This set contains 50$ fewer vectors than the test set given by Theorem 7-2 for $, and even 38% fewer vectors than the test set given by Theorem 7.1 for t> , the set of all possible NPOCF's. The following lemma, Lemma 7.1, is given and demonstrated in [Lai 76] (see Lemma 8.1 of [Lai 76]). It will be used in the proof of Lemma 7.2. Lemma 7.1 Let f, and f ? be incompletely specified functions of n variables such that f,(A) = fp(A) for every A e S c (? 2 ). Let (u x , . . . ,u R _ x , f ± ) be a ne- gative function sequence for f.. (i.e., f, is a completion of f..). Then (u_,..., u n ,,f ), with the same u.,...,U- ? , is a feasible partially specified NFS of length R and degree R - 1. 312 Lemma 7.2 Let f, and f p be two partially specified functions of n variables having the relation: f (A) - 1 if f 2 (A) - 1 and f^A) =0 if fg(A) = 0, i / ** \ / "* ■Jt ' • • >Hr_i> lg)* of NFS^R,^) and HFS*(R,? 2 ), respectively, satisfy: f i f i L L (A) > L d (A) mn v — mn v for every A € V . (3) Conditional maximum labellings of the n-cube, corresponding to feasible completions NFS^R,^) = (u^...^., uj +1 , . . . ,u^_ 1 , f ] _) and NfV(R,? 2 ) = (u^ ^2 ^2 ~ i ~ i ~ •••'V U i+1'"' ,U R-1' f 2^ 0f ^^(R^i) and NFS n (R,f 2 ), respectively, satisfy: L ^ (A) < L d (A) mx — mx for every A e V . n -1 '0 Let u . - be the maximum permissible function for NFS 1 (R,f ) and let <■ U i+1 be the maximuin Permissible function for NFS (R,f ). Then: 313 Sj +1 (A) = 1 if u^ +1 (A) = 1 and Sj; +1 (A) = if uJ +1 (A) = for every vector A t V . Proof First consider part 1 of the lemma. Functions f, and f p clearly satisfy the conditions of Lemma 7.1. Hence, if NFS (R,f n ) is a feasible i n ' 1 partially specified NFS, NFS (R,f p ) must also be one. Next, part 2 of the lemma will be demonstrated. First, consider vertex 1. f\,i _ f ,i _ Clearly, by Step 1 of Algorithm CMNL, L (l) > L (l). Now suppose that for every vector A of weight j, L (A) > L c (A). Then for each vector B u ' mn — mn f-,,i ? 2 ,i of weight j-1 by the conditions of Step 3 of Algorithm CMNL, L (B) > L (B) must hold. By induction, the second statement of the lemma is true. Part 3 of the lemma can similarly be proved by consideration of Algorithm CMXL. Finally, consider part h of the lemma. By Step 3b of Algorithm MPF, if U? _(A) = 1, U? , (A) = u? _(A) --- 1 (where u 2 . . and u 2 . are from NFS 1 (R,f Q ) 1+1 ' —1+1 i+l — l+l i+l n d ^ i ~ and NFS (R,f_), respectively). Then by parts 2 and 3 of this lemma, and the fact that u , ...u. are the same for both NFS X (R,f 2 ) and NFS^R,:^) as well as both NFS 1 (R,f ) and NFS 1 (R,f, ), u} Ak) = u*(A) = 1. Therefore, by Step 3b n ' 2 n v ' 1 ' -i+l i+l of Algorithm MPF, u. (A) = 1. ~1 ~2 It can similarly be shown that u. (A) = if U i+1 ( A ) = °- Q.E.D. Theorem 7 .h The set of vectors, T, resulting from Algorithm 7.5 (TSG) for a function f and a network N synthesized by Algorithm DIMN to realize f, constitutes a sufficient test set for all possible single and multiple faults in N. 31U Proof As previously discussed, it is sufficient to show that, for function f defined as: f • (A) = f (A) for every A € T and f f (A) = *, otherwise, Algorithm DIMN can synthesize the same network N for function f ' also. (For convenience, let the synthesis of network N for function f by Algorithm DIMN be referred to as 'Synthesis DIMN,' and let the synthesis of network N' (to be shown identical to N) for function f ' by Algorithm DIMN be referred to as 'Synthesis DIMN'.' ) Then, by Theorem 7*2, the set of all specified vectors for f, a subset of set T, constitutes a sufficient test set for all faults in network N. Thus, T would constitute a sufficient test set for all faults in N. For each maximum permissible function u! .. determined in Step 2 of Syn- thesis DIMN', it will be shown that an expression for u , a negative com- pletion of u! n with respect to x.,...,x , u n ,...,u., can be chosen identical l+l ^ 1/ ' n* 1' ' i' to that selected for u. in Synthesis DIMN and consistent with the conditions of Step 3 of Algorithm DIMN. The proof will be by induction on u.: first it will be shown that the same expression for u , i.e., the same negative completion with respect to x ,...,x , can be chosen in both Synthesis DIMN and Synthesis DIMN'; then assuming identical u , ...,u. have been chosen in both Syntheses DIMN and DIMN', it can be shown that the same u. can then be chosen for both cases. Consider now the selection of u, in Synthesis DIMN'. The maximum permis- sible function u' is obtained in Step 2 of Algorithm DIMN by the use of Algo- rithm MPF: NFS°(R,f' ) ; By part k of Lemma 7.2, ~ ^ ~ ~ rithm MPF: MFS (B,f f ) and NFS (R,f ' ) are obtained and compared to yield u'. 315 u-^A) = 1 if u^(A) = 1 and u^A) = if u^(A) = 0. Therefore, any negative completion of u with respect to x ,...,x is a neg- ative completion of u' with respect to x.,...,x . In particular, the negative completion u_ of u_ selected during Synthesis DIMN is also a negative com- pletion of u' . Since u is a completely specified negative function with respect to x , ...,x , a complemented irredundant disjuctive form of it must be the complement of the disjunction of p-terms of the minimum false vectors of u : m ± = 3 2 v ... p k . (7.1) If it can be shown that this expression satisfies Step 3 of Synthesis DIMN', i.e., if it can be shown that the deletion of any literal or term from the expression would not result in a negative completion of u' , then clearly u, can be selected by Synthesis DIMN' , yielding a cell of the same configuration as the first cell in network N. Suppose a term p., 1 < j < k- , can be deleted from expression (7'l) with the resulting expression, u' 1 = (3. v ... v- B. 1 v (3 . -, ^ ... v f3, , still a negative completion of u' . Let C . be the minimum false vector of u corre- sponding to 3-term p.. Then the BDV, B., corresponding to C. and all of the J J E. Hence there exists a vector A such that u' (A) = 1, u"(E) = 0, and A > E. This contradicts the assumption that u' 1 is a negative completion of u' . Therefore, no literals can be deleted from expression (7«l) without realizing a function which is not a negative completion of u' . Similarly, it can be shown, for functions u',...,u', that the same neg- ative completions u ,...,u can be chosen in Synthesis DIMN' as were chosen in Synthesis DIMN. Thus, the identical network N can be obtained by Synthesis DD4N' as obtained by Synthesis DIMN. Q.E.D. J17 8. CONCLUSIONS Some theoretical properties related to MOS cell/negative gate network:. were discussed in Section 3. Certain of the properties can be employed in identifying certain non-optimal networks, and some of the properties may be useful in the development of further synthesis algorithms. Section h discussed and compared published MOS network synthesis methods. In particular, a comparison of the approach of [Liu 72] with that of [NTK 72] yielded a new set of synthesis algorithms paralleling those of [Liu 72]. In addition, still other synthesis algorithms based on a new concept of 'cluster- ing' were proposed which employ theidea of [Liu 72] enabling a relatively simple determination of cell configurations in the synthesized network. These new algorithms, however, often produce networks of fewer FET's than those generat- ed by corresponding algorithms of [Liu 72], though they involve somewhat more extensive calculations than those of [Liu 72]. In the preceding sections, several methods for the design of G-- minimal MOS networks were discussed. Since a single negative gate is very powerful (in the sense that it can realize any negative function), the implementation of of G-minimal negative gate networks as MOS networks tends to become impractical as the number of variables involved grows beyond a relatively small number. When such impractical designs are produced, the logic designer will find the transformations of Section 5 useful in reducing cell complexities, though no systematic method of applying these transformations was given due to the large number of different possible objectives motivating their use. A new approach to MOS network design was proposed in Section 6. In this approach, networks are designed by the transformation of existing designs, 318 though this approach does not guarantee optimal networks (except in certain cases in which the pre-existing networks are known to be optimal). The approach seems useful for network synthesis for small values of n (i.e., the number of external variables), or for the simplification of previously designed networks, for large or small n, consisting of cells of a practical size. Cer- tain improvements of, extensions of, and additions to the program implement- ing the transduction procedures were discussed which could lead to better results and new applications. Section 7 proposed a new method of generating sufficient test sets for the sets of all possible single and multiple faults in irredundant MOS net- works designed by the algorithm of [Lai 76]. This method operates most efficiently when incorporated into the synthesis algorithm of [Lai 76]. An example was given which showed a large percentage difference in the size of a test set for a network compared with the size of the previously best known test set. 319 REFERENCES [Ake 68] S. B. Akers, Jr., "On maximum inversion with minimum inverters," IEEE Trans. Comput., vol. C-17, pp. I3I+-I35, Feb. I968. [Ake S. B. Akers, Jr., "Universal test sets for logic networks," IEEE Trans. Comput., vol. C-22, pp. 835-839, Sept. 1973. [BUM 69] C. R. Baugh, T. Ibaraki, T. K. Liu, and S. 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News, pp. ^7-56, Sept. 19690 [Yam 76] K. Yamamoto, "Design of irredundant MOS networks: A program manual for the design algorithm DIMN," Report No. UIUCDCS-R- 76-78*1, Dept. of Comp. Sci., Univ. of 111., Urbana, 111., Feb. I976. 32j VITA Jay Niel Culliney was born in Bethlehem, Pennsylvania in 19^7 • At the University of Illinois, he completed his B. S. degree in Liberal Arts and >nces and his M.S. degree in Computer Science in 1969 and 1971> respectively. From I969 to 1976 he was employed as a research assistant in the Department of Computer Science at the university. He is currently employed by Rockwell International in the area of MOSLSI design. Jay Niel Culliney is a member of Sigma Xi and the Association for Computing Machinery. BUOGRAPHIC DATA EET 1. Report No. IJIUCDCS-R-77-85I * r and Subt 11 le TOFICS IN MOSFET NETWORK DESIGN 3. Recipient's Accession No. 5- Report Date February 1977 6. ulliney 8- Performing Organization Kept. No - UIUCDCS-R-77-85I . tnizaiion Name and Address Department of Computer Science rsity of Illinois at Urbana-Champaign 'Jrbana, Illinois 6l801 10. I'roiect 'Task/Work Unit No. 11. Contract /Grant No. NSF DCR73-03J+21 Sponsoring Organization Name and Address . onal Science Foundation lflOO ' Street, N.W. Va-:.ington, D.C. 20550 13. Type of Kcport 8i Period Covered Technical 14 ^^■cmrniary Notes • ■ -ikis This paper addresses several topics in the logic design of feed- forward (i.e., oop-free) networks of MOS cells (gates) to realize specified (sets of ) output functions Be section presents properties of optimal networks of MOS cells or negative gates ibstnu-t MOS cells) and some properties of interest to logic designers which apply non-optimal networks as well. In another section, new optimal network synthesis s based on a redefined concept of 'clusters' are proposed to obtain improved •esis results. A third section discusses transformations of MOS networks which re based only upon the configurations of the networks and the individual MOS cells. 1 new approach to negative gate network synthesis is given in a fourth section. This ach employs more powerful 'transduction procedures' to modify and simplify ex- Hg networks. Actual computer program implementations of these procedures are dis- ^Kd. A final section presents a method for the generation of reduced test sets for diagnosis of irredundant MOS networks synthesized by the algorithm of Lai. '. Kev lords and Document Analysis. 17o. Descriptors logic design, logic curcuits, logical elements, programs (computers). %i Identifiers Opcn-fclnded Terms Optimal, "OS, FET, design, two-level, multiple -level, cluster, stratified structure, sformation, transduction, irredundant, test set, test set generation, diagnosis, .^osable Fie Id /Group ability Statement Release Unlimited '-•w WTIS-3B I 10- 70 1 19. -sci. urity ( lass (This Report ) I'M' ■ ASSIHI-D 20. security ( lass I Th LN( l.A-sSH II 1) 21. No. of I'.i. ;« s 329 22. Price USCOMM-DC 40329-P7! ■r * " 1979 •>^> m