Uk ■UMUfl HDIBRIh BBbBBSp SbB bB BBjRfiHBS ra TBI nun 1 BV.< II k>'^' Wfc (*<• Sara H nHH lis rail assHs B— 1 « KM HHBHOBfiOflul StiMfflcw I mra OM m LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 5/0.84 no. -5SS-&0O cof>.2. '*'*-* ,UIUCDCS-R-T3-595 yuoSts ,w. %j October 1973 COO-1U69-023H DESIGN OF A HIGH NOISE IMMUNITY ANALOG FREQUENCY COUNTER by Mark Christian Loessel DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS THE LIBRARY OF THE NOV 2 8 1973 UNIVERSITY OF ILLINOIS Digitized by the Internet Archive in 2013 http://archive.org/details/designofhighnois595loes UIUCDCS-R-73-595 DESIGN OF A HIGH NOISE IMMUNITY* ANALOG FREQUENCY COUNTER by Mark Christian Loessel October 1973 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS Supported in part by the Atomic Energy Commission under contract US AEC AT(ll-l)lU69, and submitted in partial fulfillment of the requirements of the Graduate College for the degree of Master of Science in Computer Science. 5 /V'*r 111 ty ACKNOWLEDGMENT I wish to thank Professor James Robertson, Allan Wennerberg, Dr. Donald Knoop, my parents, and my wife Carol for their confidence in my ability to obtain a MS degree; Dr. Michael Faiman for his help as thesis advisor; and Mrs. Barbara Armstrong for preparation of the manias cript. IV TABLE OF CONTENTS ^ (p Pa g e 1. INTRODUCTION 1 2. DESIGN OBJECTIVES 2 2.1 Specifications of Currently Produced Counters 2 2.2 Advantages of Proposed Counter Design 3 3. DESIGN OF SENSING CIRCUITRY 5 3.1 Methods of Implementing a Comparator 5 3.2 Data Sheet Search for Usable Devices 8 3.3 Response of L.M301A, LM311D , and HA2-2623 8 3.1+ Design of Comparator Stage Circuitry 13 k. DESIGN OF DIGITAL CIRCUITRY . 20 i+.l Digital Stage Design Philosophy 20 \.2 Selection of Logic Family and Display 21 k.3 Derivation of Timing Functions 2h k.h Digital System Operation 25 5. SUMMARY 28 LIST OF REFERENCES 29 APPENDICES A. SYSTEM PACKAGING 30 B. OPERATING INSTRUCTIONS 3^ LIST OF TABLES Table Page 1. High Noise Immunity Counter Design Parameters k 2. Major Specifications of Selected Devices 8 3. E TT vs. K T when E„ = 12 volts and R = 10 kilohms ... 15 H H max 3 LIST OF FIGURES Figure Page 1. Magnetic Speed Pickup Output Waveform 2 2. Output Voltage vs. Input Voltage when Hysteresis is Used . 3 3. Bode Magnitude Plot for a Typical Internally Compensated Operational Amplifier 7 h. Static Input Resistance Measurement 9 5. Circuit Used to Measure Gain -Bandwidth Response 9 6. Comparator Circuit Using Hysteresis 11 7. Better Methods of Clamping Comparator Outputs 13 8. Comparator Configuration for Symmetric Hysteresis Levels when a dc Reference is Used ik 9. Effect of Capacitance Across R to Eliminate Switching Spike of E 16 n 10. Minimum Trigger Sensitivity Dependence upon Slew Rate of the Input Signal 17 11. Comparator to Logic Interface 19 12. Schematic Diagram of Comparator Stage 19 13. Block Diagram of Digital Section 20 1^. Waveforms Showing Response of Single Shot Made from CMOS Gates 25 15. Logic and Timing Diagrams for Digital Section .27 A-l. Packaged Prototype of Counter System 32 A-2. Circuit Board Layouts 33 1. INTRODUCTION This thesis discusses the design of a unique analog frequency counter. Frequency response is not as high as some counters currently on the market, being only to 100 kilohertz. However, the technique used to convert analog input frequency to digital pulses provides more immunity to false triggering than any popular counter of today. The low-cost counter uses state-of-the-art components. 2. DESIGN OBJECTIVES 2.1 Specifications of Currently Produced Counters The frequency counter was designed expressly for tachometer applications in a factory environment. Shaft speeds are frequently sensed using a magnetic pickup. The output waveform is basically a sinusoid with both amplitude and frequency increasing as shaft speed increases. The amplitude variation is not necessarily proportional to shaft speed variation. Usually there is considerable electrical noise on any signal in a factory. Brush motors, arc welders, and the 60 hertz standard frequency of ac power all contribute to distortion of the expected sinusoidal waveform. The output waveform of the magnetic speed pickup tends to approach that shown below: SEVERAL ZERO VOLTAGE CROSSINGS Time Figure 1. Magnetic Speed Pickup Output Waveform Many of the commercially available frequency counters, such as Dana, Monsanto, and Tektronix, have only the following operator controls: (l) + pulse, - pulse, or composite; (2) trigger slope, to trigger on leading or trailing edge of waveform; (3) trigger level, 0, +2, -2 volts are the choices if this control is present at all; (U) trigger sensitivity: (5) input attenuation level; and (6) ac or dc coupling. No combination of settings of these controls can prevent spurious counting of base line voltage crossings as shown in Figure 1. Increasing the trigger sensitivity control will only change the location of the waveform where false triggering will occur. This control determines only the voltage level to be added to the trigger level setting and does not provide hysteresis. Capacitive coupling does little to attenuate the noise especially when the noise frequency approaches the signal frequency. Even adjusting input attenuation such that the noise amplitude is less than the minimum sensitivity of the counter will not work when the input amplitude varies as a function of frequency. 2.2 Advantages of Proposed Counter Design The proposed method of elimination of noise counts is to incorporate a hysteresis control. The false triggering can then be eliminated by adjusting for more hysteresis than the magnitude of the noise voltage. Purposely limiting bandwidth, in this case to 100 kilohertz, will prevent the counter from seeing fast noise spikes. -E HYSTERESIS ^HYSTERESIS -*E 1N Figure 2. Output Voltage vs. Input Voltage when Hysteresis is Used By using a variable dc trigger level, one would not have to ac couple any input signal. Input sensitivity could be 50 millivolts rms to match typical ll counters. Counter output should be computer compatible for measurement and control of shaft speed. Since an operator has no instantaneous information regarding the data a computer is taking, a numeric display would be desirable. Twenty millisecond response time to .1% full scale accuracy provides a good combination of speed and accuracy. Since input frequency is not high enough to warrant 50 ohm coaxial cable terminations, the input impedance of the counter should be as high as possible to reduce the effects of loading. With the present day trend toward mini aturatizat ion and integration, the counter design should be adaptable, if possible, to LSI (Large Scale Integration) techniques. Max. Input Frequency. . . 100 kilohertz, 5 microsecond minimum pulse width Max. Input Voltage. . . . +15 volts Input Impedance Greater than 100 kilohms Trigger Level -15 to +15 volts continuously variable Trigger Sensitivity . . . Hysteresis +50 millivolts to +_500 millivolts Response Time Less than 20 milliseconds Accuracy 0.1$ full scale Outputs Digital display, computer compatible Other Features High noise immunity, low cost, design applicable to LSI techniques Table 1. High Noise Immunity Counter Design Parameters 3. DESIGN OF SENSING CIRCUITRY 3.1 Methods of Implementing a Comparator There are two "basic methods of frequency counting: (l) frequency to analog voltage output, and (2) frequency to digital outputs. In either case, the analog input must first be converted to a digital signal. Many devices are available — bipolar transistors, optical couplers, FET's, and integrated circuit Schmitt triggers and comparators. FET's, especially MOSFET's, would provide very high input impedance. Bipolar transistors probably have the fastest response time. Optical couplers are too slow for the frequency range to 100 kilohertz. Remembering that the proposed counter should be readily adaptable to LSI methods , it would ease design if one could find a currently produced integrated circuit which, with a few external components, could meet the design requirements. LSI techniques use transistor configurations to replace capacitors, resistors, and diodes. Attempting to breadboard the hundreds of transistors usually found in an LSI package one could easily have reliability or oscillation problems, especially with high gain circuitry. Therefore, the prototype of an LSI design would be very difficult without the help of an IC manufacturer. Schmitt triggers, comparators, and operational amplifiers are all very high gain circuits available as monolithic IC's. Schmitt triggers that are part of a digital IC logic family have an internally fixed trip level, which would not allow the variable trip level and hysteresis specified in Figure 3. Advances in recent years have led to new comparator types such as the LM311 [l]. Compared to older industry standards such as Fairchild's UA711, the LM311 is slower (200 ns vs. Uo ns response time), but the LM311 has much better stability and output short circuit protection. A more general purpose integrated circuit is the operational amplifier. The important specification for selection of an integrated circuit for comparator applications are: (l) gain-bandwidth product to insure minimum specified trigger sensitivity at 100 kilohertz; (2) sufficient output slew rate to allow full output swing at 100 kilohertz; (3) output compatibility with IC logic families; i.e., rise and fall time limitations and ability to source or sink current at the logic voltage levels; (h) input impedance high enough such that the amplifier does not load external component networks; and (5) input voltage range. Most internally frequency compensated operational amplifiers have a frequency response which approximates a single pole rolloff. This is done because a second order pole response gives 180 degrees of phase shift at unity gain causing positive feedback and subsequent oscillation and destruction of the amplifier [2]. Therefore, dc gain and unity gain crossover frequency are all that are required to completely characterize the frequency response of an internally compensated amplifier. 20 log -S SINGLE POLE ROLL-OFF -20 dB/ DECADE UNITY GAIN FREQUENCY log U) Figure 3. Bode Magnitude Plot for a Typical Internally Compensated Operational Amplifier Since the logic family to be used could require a high logic level of +10 volts, the gain required at 100 kilohertz is 10 volts divided by the minimum sensitivity of 50 millivolts, or k6 dB. An amplifier with a gain of U6 dB at 100 kilohertz and a single pole rolloff of -20 dB/decade would require a unity-gain crossover frequency of 20 megahertz. For uncompensated amplifiers , usually the unity gain crossover frequency is not specified as this can be greatly varied depending upon the frequency compensation technique used. For slew rate, assuming +15 volt swing on output at 100 kilohertz, the minimum slew rate is 3 volts/microsecond. This is slower than the rise time requirement of any IC logic family. The dc offsets internal to the comparator or amplifier are relatively unimportant as the external dc reference can be used to' null the internal offset. Monolithic IC drift, especially for ceramic packages, is better than the drift of the discrete components used in the configuration. Latch-up protection and output short circuit protection are desirable features 3.2 Data Sheet Search for Usable Devices After cross-referencing a D.A.T.A. [3] book for specifications and Semiconductor Specialists catalog [k] for pricing and availability, three devices were chosen on the basis of their performance /price ratio: (l) an LM311 comparator, which has high gain, high speed, and high stability when contrasted with other comparators; (2) an LM301A operational amplifier, which is probably the cheapest , most widely second-sourced, moderate performance operational amplifier currently being sold; and (3) the HA2-2625 op amp which has a very high gain-bandwidth product and very high slew rate. LM301A LM311D HA2-2625 A (gain at dc) Max V in common mode Max V. in differential Unity gain bandwidth Slew rate Cost Input Impedance * Comparators usually specify response time. Table 2. Major Specifications of Selected Devices 25,000 200,000 80 ,000 +12 v +15 v +15 v +30 v + 30 v +30 v 100 MHz 5v/us 200 ns* 20v/us 75<£/l $U/1 $8/1 2 Mohms ___ 1+0 Mohms 3.3 Response of LM301A, LM311D , and HA2-2625 Data sheet parameters are usually only given for a specific set of operation conditions such as R. = 100 ohms , R_ , - 2 kilohm and power * in load supplies are set at +15 volts dc. Circuit parameters at other operating conditions must be obtained empirically. To determine whether input resistance is a function of input voltage level, measurements were conducted as in Figure h. A Fluke Model 8200A digital voltmeter was used for accuracy. By resistive divider: R in " Figure 6. Comparator Circuit Using Hysteresis Since the maximum value of R and R without oscillation was found to be 10 kilohms , and the minimum R. of the comparator was found to be 3 megohms, in there should be no interaction. Dynamic switching observation will verify the absence or presence of interaction. In calculating an expected hysteresis voltage by the formula given in Figure 6, one notes that since the output is internally clamped to swing between zero volts and +V _, , and never negative, a negative hysteresis supply voltage is impossible. This unsymmetric dead zone provided by hysteresis could provide false triggering of the waveform shown in Figure 1. One of the design parameters was to provide as much noise immunity as possible. Subsequently, the LM311 design was abandoned with the hopes that the HA2-2625 could be used successfully. 12 The HA2-2625 , the last of the three selected devices, was also tested for frequency response and gain as in Figure 5. As the HA2-2625 is an operational amplifier, the output swing is approximately centered about zero volts with the output swing maximum being approximately two volts less than the power supply voltages being used. Of four devices ordered for testing, three did not have sufficient slew rate for full output swing at 100 kilohertz, and the fourth's slew rate was 15 volts per microsecond — less than the manufacturer's stated minimum of 20 volts per microsecond. Slew rate and minimum trigger level of +20 millivolts were independent of R provided maximum output current of 18 milliamps was not exceeded. Values J_j of R and R up to 100 kilohms and the use of clamp diodes showed no discernible change. Since the comparator output should be able to interface to any logic family, various methods of clamping output levels were tried. National Semiconductor recommends using a zener diode from the bandwidth control pin to ground [6]. This point is the high impedance base circuitry of the pnp emitter follower output stage. The addition of the emitter follower diode drop provides output logic levels of zero volts and V + .7 volts. If the zener were placed at the output, the logic levels would be V and * * zener -.7 volts. Connecting the zener diode as shown in Figure 7 utterly destroys frequency response. The reason is that a slow switching zener diode cannot receive enough current from the high impedance connection. Better clamping methods are shown in Figure 7- Now the zener is not required to switch: onlj low capacitance signal diodes which are much faster. Resistive dividers may be substituted for the zeners provided the resistance of the divider network does not interact with the internal resistance seen at the amplifier terminal. If one were using an operational amplifier which were not latch up protected, 13 Figure 7 provides a method of keeping the op amp out of saturation and subsequent damage. PROVIDES 0,+V OUTPUT LEVELS CLAMPING PIN 8 SUPPLY PROVIDES IV OUTPUT | t>f LEVELS CLAMPING q_ PIN 8 SUPPLY -VsuPPLY Figure 7 • Better Methods of Clamping Comparator Outputs 3.J+ Design of Comparator Stage Circuitry Figure 7 was used to calculate resistor values for various hysteresis levels. For the most general case, when R 9 is not grounded but tied to the dc reference input, the equation for the hysteresis voltage is: Tp — -CI _l_ f-UI _ Tp \ °- H dc ref v " dc ref' R 2 + R^ E is fixed and E is plus or minus depending upon the output state To eliminate the unsymmetric hysteresis and provide more noise immunity, the configuration shown in Figure 8 should be used. lU INPUT dc REFERENCE f — OE, E » " R 3 + \ E ° Figure 8. Comparator Configuration for Symmetric Hysteresis Levels when a dc Reference is Used. E = E R /(R +R ) , and hysteresis is symmetric and independent of the dc reference setting. The circuit operation is as follows: E. - E^, _ < -E TT , output goes high in dc ref H ° E. - E, _ > E TT , output goes low in dc ref H In all other cases, output stays in past state. Thus, for input levels between -E and +E , no triggering can occur. n n Note that in this configuration, assuming R = R , the input voltage swing is now twice the minimum trigger level required when only the input signal is placed on the inverting input terminal of the operational amplifier. 1% low temperature drift resistors are used for R and R for accuracy. In selecting resistors R ,• R , and R , the design trade-off is that large resistor values give higher input impedance while lower resistor values tend to decrease the amount of signal fed back, and minimize the voltage offset due to bias currents. Choose R = R = 20 kilohms. 15 The Thevenin resistance looking out from each amplifier input terminal should be the same to reduce the effect of input offset currents. Therefore, R„ should equal the parallel combination of R and R or 10 kilohms. In selecting the value of the hysteresis resistors, the parallel combination of R and R should be approximately equal to R to keep the 5 a 3 Thevenin resistance the same. As R^ approaches infinity, the hysteresis voltage goes to zero, so there is no upper limit on hysteresis resistance. Discrete values of R^ were chosen rather than a potentiometer to enable one to more easily check if hysteresis levels will change as a function of frequency. Since E is approximately equal to the supply voltages u nisix minus two volts , hysteresis levels are dependent upon supply voltage levels E : +25 +50 +100 +250 +500 millivolts H — R: U.7 2.U 1.2 .UT .22 megohms C TT vs. R.. when E_ =12 volts and R_ H H max 3 Table 3. E TT vs . R^ when E n __ _ = 12 volts and R„ = 10 kilohms Above, E does not include inherent minimum trigger sensitivity of the n operational amplifier. Hysteresis voltage increases above that calculated as the upper limit frequency of 100 kilohertz is approached. When observing E (the n + input terminal of the amplifier) , a switching spike shown in Figure 9 was seen. At high frequencies, this spike does not decay fast enough to reach its final value established by the hysteresis level setting. Constructing the circuit on a printed circuit card with ground plane, decoupling the power supply with U7 microfarads in parallel with .01 microfarads located right at the amplifier terminals , did not noticeably 16 help. This spike must be internal to the amplifier. Possibly reducing all external resistors by an order of magnitude would help. An alternate method is to shunt R with a capacitor. Too little capacitance and the spike is not reduced; too much capacitance and the capacitor will not charge and discharge fast enough to give proper hysteresis levels. The- capacitor value of .001 microfarad was optimized empirically with the results shown in Figure 9. With .0015 /i.fd Capocitor Horizontal: f =~I00 KHZ Vertical -20 mv/square No Capacitor E in = ±100 Mi Vertical: 200 mv/squore "~~ l~l r i i ; 1 i i i i - 1 h i i i \ / i ' i ll 1 H T^ i ' / i v ■ ' V i ! 1 ! 1 ! I 1 1 i i l E in =tl00 Millivolts ! 1 —■ 1 N K ' f .... — - With .0015 /ifd Capacitor No Capacitor Horizontal : f = 1 KHZ, E in =±l00 Millivolts Vertical 200 mv/square Figure 9. Effect of Capacitance Across R to Eliminate Switching Spike of E H 17 Input voltage slew rate affects the minimum trigger sensitivity. Square wave, sinusoid, and triangle, respectively, require more magnitude. This is because the response time of the amplifier requires that the signal he present for a certain time period. In actuality, the fastest pulse the counter will "see" is +_50 millivolts for 3 microseconds. A square wave with essentially no rise time could be only 3 microseconds wide, but a triangular waveform would have to be of either greater magnitude or smaller frequency to meet the requirement. See Figure 10. U 3^.S *|*3 /i-S * * 3/i.S *\ I*— 3 MICROSECONDS + 50 mv dc LEVEL Figure 10. Minimum Trigger Sensitivity Dependence upon Slew Rate of the Input Signal Approximately 3 to 5 millivolts of dc offset was observed in the switching levels. The manufacturer recommends a resistor between pins 1 and 5 j which adds resistance to one of the collector loads of the differential amplifier stage. This is not a good idea for temperature stability. Assuming I doubles for every 10°C. temperature change, the collector voltages would become unbalanced as temperature changes. A better technique would be to incorporate this offset into the dc reference control setting. 18 For R = R = 20 kilohms , the maximum current drawn from the source of the waveform being measured occurs when (E. - E, J is at in dc ref the maximum of 30 volts. Then I. = 30/i+0 kilohms = .75 milliamperes , with the sign being either + or -. To increase the impedance of the comparator configuration, an operational amplifier connected as a follower was used. High input impedance, high slew rate, and a flat frequency response to 100 kilohertz are required of the amplifier. The HA2-2625 also works well in this application. The open loop input impedance is Uo megohms , providing kO megohms input resistance in the follower con- figuration [7]. If an amplifier were used, the dc level and noise would also be amplified and the hysteresis and dc reference control settings would be harder to figure out. For the lower gain of a follower, the frequency response is more nearly constant for a greater frequency range. The sensitivity requirement has been met without the use of an amplifier. The dc reference control was buffered using a iiPJjhl in the follower configuration. Gain-bandwidth and slew rate are unimportant for dc applications so the low cost amplifier may be used. This allows a larger resistance potentiometer and, therefore, less current from the power supply without causing interaction with the resistor R . An inverter logic gate on the output of the comparator will provide a choice of +_ trigger slope. Two inverters in series insure that the risetime of the logic signal presented to the counter stage will have the same risetime independent of which trigger slope is selected. Output level shifting from +E of the comparator to the levels U ID.3.X required by the logic family can be accomplished as in Figure 11. 19 COMPARATOR! 'LOGIC SUPPLY TO LOGIC ■+CI — i — o WITH 0,+Vs LOGIC LEVELS COMPARATOR o— WV- TO LOGIC -Oj — t— ° W 'TH 0,-Vs LOGIC LEVELS -V LOGIC SUPPLY Figure 11. Comparator to Logic Interface Notice the output swing of the comparator stage was left at its maximum to allow interfacing with any logic family. If one were to choose TTL logic for the counter stage, where the maximum voltage level required is only +3 volts, rather than +12 volts, only one-fourth the gain is needed, and the LM301A would have sufficient gain. Or, using the gain of the HA2-2625, the minimum input signal required for triggering would be 13 millivolts rather than 50 millivolts. Because E changes, the hysteresis levels would also change, dc REFERENCE CONTROL BUFFER ON/OFF SW. NYSTERESIS LEVEL SWITCH OUTPUTO- Figure 12. Schematic Diagram of Comparator Stage 20 k. DESIGN OF DIGITAL CIRCUITRY h. 1 Digital Stage Design Philosophy The digital section consists of counters, buffers, latches, display, and a clock function to periodically open a time window for counting and closing the window for latch and reset functions. DIGITAL INPUT o COUNTERS BUFFER DISPLAY \J j_ij-ij.v^n.jiio HO 1 LD i 1 RESET COMPUTER ENABLE MASTER DISPLAY ( :lock CLOCK Figure 13. Block Diagram of Digital Section To determine the type of code to be used as output of the counter stage, remember that 12 bit straight binary or any other code is computer compatible. Software can provide the interpretation. Since the specifica- tions call for a digital display, the counter outputs should be BCD as then BCD to seven-segment decoder /drivers can be used for the display. Other codes do not have the decoder/driver function on a single chip and many packages would be required. An accuracy of 0.1$ full scale and 100 kilohertz full scale input frequency require that the counter be accurate to 100 hertz. The period of the 100 hertz is 10 milliseconds , so the minimum time the counters are enabled is 10 milliseconds. Assuming a square wave clock signal, where the counters are enabled for 10 milliseconds and the latch plus reset time equals 10 milliseconds, the counter response time is the 20 milliseconds specified. 21 One hundred kilohertz full scale +_. 1 kilohertz requires three digits for BCD outputs. BCD counters will be used as then the counters are directly interfaceable to the displays. Hence, there is lower part count, less cost, and greater reliability. The clocking function must be a highly stable periodic waveform to enable the counters for exactly 10 milliseconds, and provide latch and reset signal while the counters are disabled. Latches will be used to provide a stable display while the counters are enabled. Single shots could be used for the latch enable and reset signals. The displays should have a separate clock, slower but synchronous with the system clock. Ten millisecond update time provides an update rate of 100 times per second which no human eye can follow if the frequency varied during each clock pulse. A slower rate on the order of five readings per second would be desirable. Since 100 readings per second is not too fast for a computer, the computer enable signal should be left fast to keep the specified response time. 4.2 Selection of Logic Family and Display The function blocks require decade counters with provision for enable and reset, 4-bit buffers to convert outputs to TTL logic levels if another logic family is used, 4-bit latches for the display, a 3- digit display, a 100 Hertz clock, and single shots. Before proceeding further, the logic family should be chosen for two reasons: (l) it is possible that some chips, such as the BCD counters are not available in all logic families, and (2) logic ones and zeros may not perform the same function in all logic families, i.e., the counter reset signal required may be a "l" in CMOS and a "0" in TTL. 22 RTL, DTL, TTL, CMOS, ECL, and high noise immunity logic such as manufactured by Teledyne and Motorola were considered. All of the logic families have the packages needed except for single shots, and they can be made from gates. In choosing a logic family, one is concerned with speed (maximum clock rate), availability, logic level voltages and current source and sink requirements, noise immunity, power consumption, and compatibility with LSI. With a maximum input frequency of 100 kilohertz any of the mentioned logic families is fast enough. Voltage levels and current requirements can be taken care of through the design of the interface to the comparator stage. RTL is being phased out by suppliers, all other logic families are readily available. High speed logic (fast rise time) requires special layout considerations to provide noise immunity. For this reason TTL and ECL will not be considered. The logic families with the best noise immunity are high noise immunity logic (NHiL) , CMOS, and DTL. According to RCA, the noise immunity of their COSMOS is typically one-half the supply voltage. Considering power requirements , CMOS can be operated from any supply voltage in the range of +3 to +15 volts dc. CMOS power required is a function of frequency, requiring approximately 1 milliwatt at 100 kilohertz. Each TTL low input sources 1.6 milliamperes from a 5 volt supply for 8 milliwatt. CMOS could be operated from the comparator power supply. With the higher power requirements of TTL, only MSI is possible because of thermal dissipation limitations. This is true for all bipolar 23 saturated logic. The best logic type for LSI chip density is PMOS , but this is not available in discrete package functions for breadboarding. Usually, bipolar and MOS semiconductors are not placed on the same chip, so the comparator would have to be on a separate chip. Madhu B. Vora of IBM has recently announced a "BIFET" method for making both MOS and bipolar on the same chip with the same processing steps [8]. If his method proves unfeasible, the logic and comparator could easily be placed on separate chips as there would be few interconnections. On the basis of the above discussion, CMOS was chosen to implement the logic functions. Price was not used as a determining factor because the newer logic such as CMOS has not yet been produced in great enough volume for the price to bottom out as with TTL, and discrete package costs do not necessarily reflect the cost of a mask for LSI When using CMOS, the ideal display would be a liquid crystal display such as RCA's TA8032 because of the low power requirement. At $25 per digit without a decoder driver, the cost was prohibitive. The display used was Hewlett-Packard's 5082-7300 series display. The latch, decoder- driver, and a .29 character height seven segment display are all integrated into one package. Inputs are BCD and TTL compatible. The TTL levels require power buffering. Texas Instruments make equivalent displays in their TIL306 series , but the cost is higher. As the price of the liquid crystal display falls, the LCD can be used without changing design fundamentals. 2k h. 3 Derivation of Timing Functions A Signetics NE555 timer module was used for the master clock signal. This low cost (75^) monolithic chip has a temperature stability of 50 ppm/° C. With only a 3-digit display the accuracy requirements do not warrant the cost of a crystal controlled clock. The output voltage ' levels of the NE555 depend upon supply voltage and will directly interface to CMOS when operated from the CMOS supply voltage. T = .685 K.C and t ... - .685 (R. + 2 R_)C. From these formulas it is seen that one can high A B never have less than a 50% duty cycle. Using C equal to .01 microfarad, R^ is 15 kilohms and R is 1.1*3 megohms to provide the 10 millisecond and .1 millisecond waveform. A polystyrene capacitor and 1% metal film resistors were used for temperature stability. The use of a counter with a nonsymmetric duty cycle allows reduction of the time required for latch and reset. Reducing this time to a hundredth of the counter enable time (or .1 milliseconds) , the response time is reduced to 10.1 milliseconds. This still allows plenty of time for the latch and counter reset signals. RCA's CDl+000 series of CMOS does not include a single shot package. RCA recommends circuit configurations for both go high and go low single shots using gates [9]. Resistor values must be kept large because of the low source and sink capabilities of a CMOS gate. One disadvantage of using gate configurations for single shots is that both out and out are not available without going through an inverter and increasing package count. Figure 15 shows the poor response time of gates in a single shot configuration. 25 33E i i HORIZONTAL- 20 MICROSECONDS / DIVISION VERTICAL- 2 VOLTS / DIVISION Figure ik. Waveforms Showing Response of Single Shot Made from CMOS Gates k.h Digital System Operation A complete system logic diagram and system timing diagram are shown in Figure 15. The various signals were derived from a configuration which kept package count at a minimum. Except for the buffers, which are only used for compatibility with the TTL inputs of the display, all gates of every package are used. Both the clock (^ and clock (b) signals are present as (b) is needed for the counter enable signal, but less than a 50% duty cycle is not obtainable from the timer module. The master clock Qy triggers a single shot (cj which is used as a computer latch enable. The pulse width is set to approximately 50 microseconds as this is more easily observable on an oscilloscope. Counter reset (b) occurs after computer latch (c) , but while the counters are still disabled. If a single shot were used to obtain Co) 26 there is a possibility of a malfunction occurring. The counter could be enabled before the single shot had timed out, causing both reset and enable to be present at the same time. A NAND of (a) and [C^ makes sure the counters are enabled when they should be and also allows one NAND gate rather than two for a single shot. A seven stage binary counter is used to divide down the main clock rAJ to obtain a slower update rate for the display. A rotary switch selects one of the seven counter outputs to provide display update rates of 100 to approximately 3/*+ hertz. The display counter \Ej is triggered on the falling edge of the master clock (iy . A NAND of the computer latch (c) and the display clock Qy insures that the display enable (f) is synchronized with the computer latch enable. A second single shot (Hj is used to insure that the display counter reset signal is present for the minimum reset pulse width of 600 nanoseconds. The decade counters were connected as parallel counters to insure that the outputs would all change synchronously. In the ripple count mode, the carry must propogate through the counter outputs one by one, causing an error if the disable signal occurs before the final status of each bit has been determined. 27 '4C04010A f ^ COMPUTER \S ° LATCH O^ i T3« reset jj CD4029A £ 10 c ' c A B Q» Or 0« Q; 2 14 V V V V V 111 6 ® V.CD40UA 4 BIT LATCH l_l I I CLOCK RESET E C04029A £ 10 B Cu 5 Qz Qi 4 BIT LATCH vvvvv DIGITAL INPUT CD4010A 4 BIT LATCH HP5082-7300 n n n n n _rr _n MASTER CLOCK ® (D MASTER CLOCK (5) COMPUTER LATCH (F) COUNTER RESET (F) DISPLAY CLOCK (f) DISPLAY ENABLE (g) DISPLAY ENABLE (h) DISPLAY COUNTER RESET Figure 15. Logic and Timing Diagrams for Digital Section 28 5 . SUMMARY This thesis discusses the design of a unique analog or digital frequency counter. An accurate count is obtained even when large magnitudes of electrical noise are present. The sensing technique used is an IC comparator with variable threshold and hysteresis settings. A noise immunity of 7-5 volts is obtained in the digital circuitry through the use of CMOS logic. A to 100 kilohertz +. 1% counter was constructed using this design. The counter uses low cost monolithic circuits and could be built on a single chip using LSI techniques. The counter was tested using a 6-digit counter and oscilloscope for comparison. All design specifications were met or exceeded. 29 LIST OF REFERENCES [l] Dobkin, R. C. , et al, Linear Applications , National Semiconductor Corporation, ANUl (1972). [2] Bode, H., NETWORK ANALYSIS AND FEEDBACK AMPLIFIER DESIGN, D. van Nostrand Co., Inc.: New York (19^5) pp. ^51-530. [3] Lepow, F., Linear Integrated Circuit D.A.T.A. Book , D.A.T.A., Inc. (1972) [k] Stock and Price List , Semiconductor Specialists, Inc. (1972). [5] Tobey, G. , et al , OPERATIONAL AMPLIFIERS: DESIGN AND APPLICATIONS, McGraw-Hill Book Co.: New York (1971) pp. 158, l80-l83. [6] Dobkin, R. C. , et al, Linear Applications , National Semiconductor Corporation, ANU2 (1972). [7] Schilling, D. L. and Belove , C. , ELECTRONIC CIRCUITS, DISCRETE AND INTEGRATED, McGraw-Hill: New York (1968) pp. 588-90. [8] Vora, Madhu B. , "BIFET Promises Faster and Denser ICs," Electronic Design , 20, #26 (1972) p. 30. [9] Dean, J. A. and Rupley, J. P. ,"A-stable and Monostable Oscillators Using RCA C0S/M0S Digital Integrated Circuits," COS /MPS Digital Integrated Circuits , 1973 Edition, RCA Corporation (1972) pp. 353-360. 30 APPENDIX A SYSTEM PACKAGING 31 The counter system prototype is shown in Figures l6 and IT. The system was constructed on printed circuit cards to eliminate broken wire problems and minimize logic signal interactions. The packaging method shown incorporated materials on hand and is not intended as an optimum packaging design for production. Three cards were used: (l) comparator, (2) clock and counter, and (3) display and associated circuitry. Card 3 may be eliminated if only computer interfacing is required. Card 2 may be eliminated if a computer is available for timing and counting and only the comparator stage is required. The entire circuit could be constructed on one printed circuit card 3-1/2" x 9" with all switches and potentiometers mounted on the PC board. A one card system reduces interconnections and corresponding assembly labor. The ultimate in packaging would be to put the whole system on one or two LSI chips . The present comparator design requires an external power supply providing 50 milliamperes at +_ 15 volts and 550 milliamperes at +5 volts. The comparator operational amplifier has a power supply rejection ratio of 90 dB , enabling one to calculate the ripple and requlation requirements of the power supply. 32 \ Figure A-l. Packaged Prototype of Counter System 33 Figure A-2. Circuit Board Layouts 3U APPENDIX B OPERATING INSTRUCTIONS 35 The operator controls are as follows: INPUT BUFFER ON/OFF, DC REFERENCE, DISPLAY REP RATE, and HYSTERESIS. INPUT BUFFER ON /OFF allows the user to select an input impedance of Uo megohms in the ON position. In the OFF position, the maximum current drawn in .75 milliampere. The ON position buffer provides a fixed slew rate to the comparator of 20 volts /microsecond, and therefore decreases effective risetime of the input waveform. This is noticeable only for square wave input. DC REFERENCE should be set at the ac midpoint of the input waveform. If the control is not set on the midpoint, the capacitor from the non-inverting input to ground does not charge and discharge at the same rate resulting in unbalanced hysteresis levels. DISPLAY REP RATE allows the user to select 3A to 100 display changes per second. HYSTERESIS should be set for a value less than the input signal amplitude of the waveform to be measured but greater than the maximum expected noise pulse. Form AEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIF C AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) 1. AEC REPORT NO. C00-lU69-023 1 + 2. TITLE DESIGN OF A HIGH NOISE IMMUNITY ANALOG FREQUENCY COUNTER 3. TYPE OF DOCUMENT (Check one): \y\ a. Scientific and technical report I I b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): IyI a. AEC's normal announcement and distribution procedures may be followed. ~2 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. ] c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) W. J. Poppelbaum Professor and Principal Investigator Organization Department of Computer Science University of Illinois at Urban a -Champaign Urbana, Illinois 6l801 Signature //. Z7. Pc//t crrT^c&t q/^mk Date October 1973 FOR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: 8. PATENT CLEARANCE: LJ a. AEC patent clearance has been granted by responsible AEC patent group. LJ b. Report has been sent to responsible AEC patent group for clearance. I I c. Patent clearance not required. 3IBLI0GRAPHIC DATA iHEET 1. Report No. UIUCDCS-R-73-595 3. Recipient's Accession No. . Title and Subtitle DESIGN OF A HIGH NOISE IMMUNITY ANALOG FREQUENCY COUNTER 5. Report Date October 1973 6. Author(s) •„ , —, . , . _ ., Mark Christian Loessel 8- Performing Organization Rept. No. Performing Organization Name and Address Department of Computer Science University of Illinois at Urb ana-Champaign Urbana, Illinois 6l801 10. Project/Task/Work Unit No. 1 I. Contract /Grant No US AEC AT(ll-l)lH69 2. Sponsoring Organization Name and Address US AEC Chicago Operations Office 9800 South Cass Avenue Argonne , Illinois 13. Type of Report & Period Covert d Thesis rese arch 14. >. Supplementary Notes -H it. Abstracts This thesis discusses the design of a unique analog frequency counter. Frequency response is not as high as some counters currently on the market, being only to 100 kilohertz. However, the technique used to convert analog input frequency to digital pulses provides more immunity to false triggering than any popular counter of today. The low-cost counter uses state-of-the-art components. Key Words and Document Analysis. 17a. Descriptors analog frequency counter digital pulses l>. Identifiers /'Open-Ended Terms 1 • ( OSATI Field/Group ■ Availability Statement unlimited distribution C'M NTIS-35 ( 10-70) 19. Security (lass (This Report ) UNCLASSIFIED 20. Security ( lass (This Page UNCLASSIFIED 21. N't) of Pa^t >*3 22. Pnc USCOMM-DC 4 03S0-P' tf* s <$> MDwwH HnVHK ami*** UNO** U*BM** m Hi H ■ H ■ m '&•«&* ! ^•*j ■ HIV: ■ ■ ■■ ^^H HHBdhB H mHH HH KfflBSBBHB nB mfnfltlWBHli flfa illilllilllMll mwera ram HV