The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN eport No. k62 jTt^L^Cti A BRANCH-AND-BOIMD ALGORITHM FOR OPTIMAL AND-OR NETWORKS (The Algorithm Description) hy Tomoyasu Nakagawa ne 1971 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS Digitized by the Internet Archive in 2013 http://archive.org/details/branchandboundal462naka -X- A Branch-and-Bound Algorithm for Optimal AND-OR Networks (The Algorithm Description) by Tomoyasu Nakagawa Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part "by the National Science Foundation under Grant No. NSF GJ-503. INTRODUCTION The branch- and-bound algorithm is applied by E. S. Davidson to the synthesis problem of optimal combinational networks for arbitrary switching functions using NAND gates by introducing the desirability order and other speed improvement gimmicks. So far, his algorithm is one of the few algorithms which obtain "optimal" networks within a reasonable period of computational time for functions of few variables, and also for some func- tions of more variables provided that the configurations of the networks are simple. Since his original algorithm is based on the concept of "cov- ering" the gate outputs with external variables and/or other gates, the algorithm can be applied to the logical design problem of synthesizing optimal networks using any combination of conventional simple gates. (By conventional simple gates we mean: AND gates, OR gates, NAND gates, and NOR gates. ) In this report, we formulate the branch- and-bound algorithm for the logical design problem of optimal combinational networks with a mixture of AND and OR gates. 1. Definitions and the basic form of the algorithm . The problem to solve is the synthesis of optimal combinational net- works for arbitrary switching functions using a mixture of AND and OR gates. By "optimal network", we mean a network which has the least cost C, where C is defined as a weighted sum of the number of gates and the total number of connections and interconnections, i.e., C= A x R + B X I where R is the number of gates I is the total number of connections and interconnections (i.e., the connections of external inputs to gates and the interconnections among gates), i.e., the number of gate inputs, and A and B are non-negative constants, (i.e., weights.) Different combinations of A and B imply different optimization problems. For example, A > and B = implies the minimization of the number of gates, A » B > implies the minimization of the number of gate inputs after first minimizing the number of gates, A = and B > implies the minimization of the number of gate inputs only, and so on. In the algorithm explained below, we will represent the given switching functions in terms of a truth table. Suppose m switching functions of n variables are given, i.e., f , h = 1, . . . , m. (in the following, we call the given switching functions the output functions . ) Let us assume that both uncomplemented and complemented input variables are available to a network to be synthesized. Let x p , £ = 1, ..., n, and y „ = x » £ = 1, ...,n, denote the uncomplemented external variables and the complemented external variables, respectively. By the use of x, and y., £ = 1, . . . , n, the truth table of the given problem is written as in Fig. 1.1 where x. are given j binary values, or 1. X. x. X n Yr n x, x. x^ x. «y o y * 1 y n y n x. 2 n -l x. 2 n -l X n 1 X n • ♦ • 2 n -l X n y l 1 y l • • • 2 n -l y l 1 2 n -l Yr y. 2 n -l n m f° f 1 1 1 ,2 n -l 'I ,0 JL ? n -l f • • • f m m m Fig. 1.1 The m output functions, f, , of n variables are represented in terms or the truth table, where y/s are complemented x,'s ; i.e., x/ e s. For example, in the case of m = 1, if the output function f is x x x s/ x (x 2 ss x ), then the truth table is as in Fig. 1.2. x l 1 1 1 1 X 2 1 1 1 1 x 3 1 1 1 1 y l 1 1 1 1 y 2 1 1 1 1 y 3 1 1 1 1 f i 1 1 1 1 Fig. 1.2 The truth table of f = x x x v x (x 2 v x ) m We' will exclude from our discussion the case where some of the output functions (among the m output functions) are identical to other functions or to external input variables Xp, y». Therefore, we always need at least gates to realize the m output functions f , ' s simultaneously. Let us assign one gate, labeled gate h, to each f, h = 1, . . . , m. Notice that since our problem is the construction of a network using a mixture of AND and OR gates, each gate must be specified to AND or OR. When each gate is specified to AND or OR, it is said to have a mode AND or OR, respectively. Let us first take a network of m gates, such that each gate h, h = 1, ... , rn, is assigned the given output function f, but is not yet assigned a definite mode AND or OR. We call this network (a network consisting of m isolated gates with no input connections and no assigned modes) a primitive solution . Fig. 1.3 is the primitive solution to the problem of an output function f-j_, where f^ = x x o x o v x i ( x o v x o)> for a special case of m = 1. gate 1 (00011110) Fig. 1.3 The primitive solution to f = x x x \s x (x v x ). The output gate 1 is specified as f , but the gate is not yet assigned a definite mode, AND or OR. The symbol inside the circle denotes that this gate is of an unas signed mode. Since each gate h, h = 1, ... , m, must assume a mode of either AND or OR, there are 2 m combinations of assignments of modes to the m gates of the primitive solution, as shown in Fig. l.h. mode assignment gate 1 gate 2 . . . gate m- ■1 gate m 1 OR OR • • • OR OR 2 OR OR • • • OR AND 3 OR OR • • • AND OR • . • • • • ' • 2 m AND AND • • • . AND AND jn Fig. l.k 2 assignments of modes to the m gates of the primitive solution. Let us call the network in which the m gates of the primitive solution are assigned one of the 2 m combinations of modes an initial solution . Obviously we have 2 m different initial solutions. Our algorithm starts with an initial solution, then expands the initial solution by connecting external variables, by introducing new gates, or by making interconnections among gates, so that a resulting loop- free network realizes the m given output functions simultaneously. A number of net- works are generated in sequence by making the above connections or inter- connections or introducing gates, in different combinations in such a way that the cost of one network is lower than that of the previous one. Even- tually we will get an optimal network. In accordance with Fig. 1.1, the output of every gate to be introduced into a network is represented in the form of 2 -tuple, (P , ..., P , ..., P n 1 ), where each P , j=0, ..., 2 -1, may assume the values or 1. Notice, however, that we will not assign a definite value, or 1, at once to all components, P ' s of a gate. Accordingly we use the symbol * to denote that the value of P is unassigned. 2 n -l Let us find out a necessary condition that the output (P , ..., P ) of a gate must satisfy with respect to other gates and/or external variables. Consider two gates, gate i and gate k, where gate i is connected to gate k. 2 n -l 2 n -l Let (P., ..., P. ) and (P, , ' ..., P, ) denote the outputs of gate i and gate k, respectively. If the mode of gate k is AND, then the components P? and P^ must sat- isfy the following condition, no matter what the mode of gate i is (i.e., AND, OR), or whether gate i and gate k have other inputs, because the gate k performs AND operation: P? = for all j such that P? - k ° l and P"? = 1 for all j such that P_ J = 1 l k (1.1) gate k gate i (and) i i I I 1 ) 1 ) Fig. l.k The O-components of gate i force the corresponding components in gate k to 0, and the 1-components of gate k force the corresponding components of gate i to 1, no matter what the mode of gate i is, or whether gate k and gate i have other inputs. If the mode of gate k is OR, then the components PV and Pr. must satisfy the following condition no matter what the mode of gate i is (i.e., AND, 0R)^ or whether gate i and gate k have other inputs, because gate k performs OR operation: R J = 1 for all j such that F 3 . = \ k i and P? = for all j such that P. J = l k (1.2) gate k gate i ( i t i 1 i i ( 1 1 i l I I o ) — ) Fig. 1.5 The 1-components of gate i force the corresponding components of gate k to 1, and the O-components of gate k force the cor- responding components of gate i to , no matter what the mode of gate i is, or wheter gate k and gate i have other inputs. A similar condition must also hold between the output of gate k and an external input x.(or yj when x„ (or y .) is connected to gate k, (regardless of other inputs to gate k. ) If the mode of gate k is AND, then PjJ. = for all j such that xj = (or yj = 0), -\ and xj = 1 (or yj - l) for all j such that p£ = 1 If the mode of gate k is OR, then (1.3: p£ = 1 for all j such that xj (or y m, with external inputs x., y is said to be an " intermediate solution " if the network satisfies the following conditions: (i) The entire network has no loops, (ii) a. The first m gates (i.e., gate i for i = I, . . . , m) are assigned the m output functions. In other words, the output of gates i is 2 n -l (f., . .., f. ), for i = 1, . . . , m. These gates may or may not be connected to other gates, (ii) b. The outputs of the other gates (i.e., gate i for i = m+1, ..., R), if any, are completely or incompletely specified. Each gate i, for i = m+1, . . . , R, is connected to at least one of the other gates in the network. (iii) The assignment of the output of each gate is feasible. Notice that the initial solution defined previously is a special case of an intermediate solution.. The network corresponding to an intermediate solution may or may not realize .the given set of output functions f , h=l, . . . , m. An inter- h mediate solution whose network realizes the given set of output functions is said to be a feasible solution . A feasible solution whose cost is the least among all feasible solutions is an optimal solution . In order to construct feasible solutions, we introduce the concept of "cover" . Definition (Covered component and uncovered component . ) A component p£ = of an AND gate k is said to be covered , if gate k has at least one input, (i.e., the output of another gate i or external in- put x», y J, whose j-th component (F? or x^ (or y J )) is 0. pjj = of an AID gate k is said to be uncovered , if P^. is not yet covered. 10 A component P, , =1 of an OR gate k' is said to be covered , if gate k' has at least one input, a gate i or an external input x Q (or yJ whose £ £' an OR i ' i ' i ' i ' j'th component , ( Pr or x J p (or jp )), is 1. If not, Pr, = 1 of gate k' is said to be uncovered . Fig. 1.6 is an example of an intermediate solution, where some components are already covered and others are not. (The covered components are underlined.) gate 1 (00010000 ) AND (=x 1 ) 11110000) (00110011) (00011110) AND ) (000*1**0 ) gate 3 or) (****i**o) gate k Fig. 1.6 Example of an intermediate solution to f = x x x v x (x v x ), where some components are covered and others are not. (The covered components are underlined. ) In order to develop a design algorithm, let us introduce the concept of possible covers for an uncovered component. As seen from the definition below, possible covers are only available external inputs and/or gates for covering the uncovered component under consideration. 11 Suppose P in gate k is an uncovered component in a given inter- mediate solution. Definition (Possible covers of uncovered component P ) The case where the mode of gate k is AND , (i) An external input x* (or y.) which is not yet connected to gate k is a possible cover of P, =0 if x„ (or y „) satisfies the following con- dition AND-(i): x . = (or y. = 0), and AND-(i) .J '0 V x° 1 (or y„ w =1) for all j such that PjJ = 1. (ii) A gate i which is already connected to gate k is a possible cover of P, =0 if gate i satisfies the following condition AND-(ii): AND-(ii) P. = * (unassigned). (iii) A gate i whieh is not yet connected to gate k is a possible cover of P = if gate i satisfies the following condition AND- (iii): AND-(iii) r \ K a connection of gate i to gate k will not form any loops, J P. = or *, and l P? = 1 or * for all j such that P, J = 1. i k (iv) In addition to the above external inputs and gates, an OR or AND gate which is not yet incorporated in the given intermediate solution is a J possible cover of P = 0. Such a gate is called a new gate . A new gate has the following property: 12 AND-(iv) the output components are all * (unas signed) . When a given intermediate solution has R gates, "both gates are numbered R + 1. The case where the mode of gate k is OR . (i) An external input x,(or y .) which is not yet connected to gate k is a possible cover of P =1 if x. (or yj satisfies the following condition OR-(i): r OR-(i) < x^ =1 (or y ^ =1), and x 3 „ =0 (or y\ =0) for all j such that pj 5 = 0. (ii) A gate i which is already connected to gate k is a possible cover of J P, = 1 if gate i satisfies the following condition OR-(ii): OR-(ii) P. = * (unassigned) . (iii) A gate i which is not yet connected to gate k is a possible cover of J P], = 1 if gate i satisfies the following condition OR- (iii): r OR a connection of gate i to gate k will no form any loops, -(iii) / P. = 1 or *, and V_ P? = or * for all j such that P n J = 0. l k (iv) In addition to the above external inputs and gates, an OR or AND gate which is not yet incorporated in the current intermediate solu- J tion is a possible cover of P = 1. Such a gate is called a new 13 gate . It has the following property: OR-(iv) I the output components are all * (unassigned) When a given intermediate solution has R gates', both gates are num- bered R i 1. With each of the possible covers defined above, we can cover an uncov- ered component P, of gate k in a given intermediate solution according to the following procedure, called the implementation of possible cover. Procedure (implementation of possible cover) : The case where an uncovered component P, is in gate k of mode AND Step 1. If the possible cover is not yet connected to gate k, then connect it to gate k; otherwise do nothing. Step 2. If the J _ "th component of the possible cover is not yet assigned, then assign to it; otherwise do nothing. Step 3» Assign necessary O's and/or i's to unassigned components of other gates in the network so that the assignment of the output of each gate in the resulting network be feasible. The case where an uncovered component P, is in gate k of mode OR Step 1. If the possible cover is not yet connected to gate k, then connect it to gate k; otherwise do nothing. Step 2. If the j -th component of the possible cover is not yet assigned, then assign 1 to it; otherwise do nothing. Step 3. Assign necessary O's and/or I's to unassigned components of other gates in the network so that the assignment of the output of each gate in the resulting network be feasible. It is worthwhile to mention that at 'step 3 of the procedure of the implementation of a possible cover, an assignment of O's and/or I's to the Ik output of a gate may 'propagate' throughout the entire network, as explained in the following. Suppose gate p is under consideration, and some of its unassigned com- ponents P are given O's and/or Vs. These O's propagate to the corre- sponding unassigned components of all immediately succeeding AND gates of gate P, and these l's propagate to the corresponding unassigned components of all immediately succeeding OR gates of gate p, regardless of the mode of gate p. Furthermore, if gate p is AND, then the same l's progate backwards to the corresponding unassigned components of all immediately preceding gates of either mode, or if gate p is OR, then the same O's propagate backwards to the corresponding unassigned components of all immediately pre- ceding gates of either mode. A similar situation now occurs with every gate to which O's or l's propagate. By repeating this process, therefore, the assignment of O's and/or l's given in gate p may propagate throughout the network. Fig. 1.7 illustrates this process. ) ( ; AND y gatepf^ , it I I . ' ' '1» ( * ■* ) • • '0' ) ( * gate p t t * Fig. 1.7 Illustration of the propagation of O's and l's to immediately preceding/succeeding gates of gate p. 15 By implementing a possible cover for an uncovered component P fc in gate k of the given intermediate solution, we obtain another intermediate solution. We call this new intermediate solution an augmented intermediate solution of the original intermediate solution. The amount of cost increase in augmented intermediate solutions depends on the kinds of possible covers implemented. Fig. 1.8 is a table of the amount of cost increase incurred by implementing one possible cover. kind of possible cover to be implemented cost increase a possible cover which is not yet connected to a gate that contains the uncovered one connection component under consideration (possible cover (i) or (iii) •) a possible cover which is already connected to the gate that contains the uncovered none component under consideration (possible cover (ii) . ) a new gate. (possible cover (iv) . ) one gate plus one connection Fig. 1.8 The amount of cost increase in an augmented intermediate solution generated by the implementation of different possible covers. See the definition of possible covers. 16 By applying the procedure of implementation of possible covers repeat- edly to uncovered components of an intermediate solution, we eventually obtain an intermediate solution in which all O-components in all AND gates and all 1-components in all OR gates are covered. In order to enumerate all of such intermediate solutions systematically, we introduce the following set of rules. Definition (SCUC and IPPC) : 'he selection criterion of uncovered components (SCUC) is a criterion under which an uncovered component is selected from a given intermediate solution. The implementation priority of possible covers (IPPC) is a priority under which the order of implementation among the possible covers for the selected uncovered component is determined. By using the concepts defined above, let us discuss an algorithm to design an optimal network with a mixture of AND and OR gates, modifying the basic form of Davidson's branch-and-bound algorithm for designing network with NAND gates. In the algorithm below, we use a parameter C which we call the cost ceiling (or the incumbent cost ) ; the C is used to preclude all intermediate solutions whose cost exceeds the current best feasible solution. Initially C is set to a sufficiently large number. The basic form of algorithm for designing an optimal network with AND and OR . Step (Start) step 0-1. Start with the given primitive solution. Set k = 0. Set C to a sufficiently large number. 17 step 0-2. Check whether or not there are unenumerated combinations of modes AND and OR to the primitive solution. If yes, then assign one of the unenumerated combinations of modes to the primitive solution, forming an initial solution S . Set k = 1. Go to step 1. If no, then go to step 9- Step 1 . Calculate the cost C, of the current intermediate solution S, . k k Compare C with C. If C, is greater than C T, then go to step 7-1; otherwise go to step 2. Step 2 . Search for uncovered components. If there are none, then go to step 8; otherwise go to step 3- Step 3 - Select one uncovered component from S , using the selection criterion of uncovered component (SCUC). Denote it with P. Step k . Make a list of all posible covers of p. ' If we replace »C k > C» by f C k > C', then the algorithm obtains only one optimal network, instead of all optimal networks. 18 Step 5 . Store P and the list of possible covers in a working space. Label k to this portion of working space. Select one possible cover from the list, according to the imple- mentation priority of possible covers (IPPC). Step 6 . Increase k by 1. Implement the possible cover selected at step 5 , generating an augmented intermediate solution. Let S denote the augmented intermediate solution. Go to step 1. Step 7 (Backtrack) Step 7-1. Decrease k by 1. If k becomes 0, then go to step 0-2; otherwise go to step 1-2.. Step 7-2. Retrieve P and the list of possible covers of label k from the working space. Search for unimplemented possible covers in the list retrieved above . If there are no unimplemented possible covers, then go to step 7-1; if there is at least one, then go to step 7-3. Step 7-3. Reconstruct S . Select one of unimplemented possible covers from the list, accord- ing to the IPPC. Step 7-U. Increase k by 1. 19 Implement the possible cover selected at step 7-3, generating an augmented intermediate solution, S . Go to step 1. Step 8 (Solution). Print S . Replace the value of C hy the cost C of S . Go to step 7-1. Step 9 (Stop). Stop. 20 2. Heuristics of the set of SCUC and IPPC. In this section, we present the set of the selection criterion of uncov- ered components (SCUC) and the implementation priority of possible covers flPPC) that was employed in our algorithm. In order to state the set of the SCUC and the IPPC, we introduce the concept of types, modifying the concept which Davidson defined in his algorithm. Based upon the property of networks of AND and OR gates, we define the types of possible covers as follows. Definition (Types of possible covers.): 3 Q Ty pes of p ossible covers for an uncovered component p = in AND gate k. — ■ ' $£ G*A: A gate i of mode OR is said to be a possible cover of type G*A if gate i is connected to gate k and P. = * (unassigned) . (G* stands for a Gate i which is already connected to gate k, and whose j -th component is *. A denotes the mode of gate i being different from the mode of gate k. ) G*B: A gate i of mode AND is said to be a possible cover of type G*B if gate i is connected to gate k and P. = *. (G* has the same mean- ing stated above. B denotes the mode of gate i being the same as the mode of gate k. ) VC*: An external input x, (or y.) is said to be a possible cover of type VC* if x» (or yj is not yet connected to gate k and x. = (or y» = 0) (VC* stands for a Variable whose Connection is * (unassigned).) 21 GC*A: A gate i of mode OR is said to be a possible cover of type GC*A if gate i is not yet connected to gate k, the connection of gate i to gate k would not form any loops, P. =0, and P: = 1 or * for all i such that Pp = 1. (GC* stands for a Gate i whose j -th k - J com- ponent is 0, and whose Connection to gate k is * (unassigned") . A denotes the mode of gate i being different from the mode of gate k. ) GC*B: A gate i of mode AND is said to be a possible cover of type GC*B if gate i is not yet connected to gate k, the connection of gate i to gate k would not form any loops, P. =0, and P. = 1 or * for j such that P, = 1. (GC* has the same meaning stated above. B denotes the mode of gate i being the same as the mode of gate k. ) G*C-*A: A gate i of mode OR is said to be a possible cover of type G*C*A if gate i is not yet connected to gate k, the connection of gate i to ^0 i gate k would not form any loops, P. = *, and Pr = 1 or * for all j such that P J = 1. (G*C* stands for a Gate i whose j -th.compo- nent is * (unassigned) , and whose Connection to gate k is # (unas- signed). A denotes the mode of gate i being different from the mode of gate k. G*C*B: A gate i of mode AND is said to be a possible cover of type G*C*B if gate i is not yet connected to gate k, the connection of gate i i to gate k would not form any loops, p = ■*, and ¥. = 1 or •* i i for all j" such that P^ = 1. (G*C* has the same meaning stated above. B denotes the mode of gate i being the same as the mode of gate k. ) 22 NWJA: A gate of mode OR which is not yet incorporated in the current intermediate solution is said to be a possible cover of type NWGA. All components are *, and the gate number is assigned the value R + 1, i.e., gate R + 1, when the highest gate number of the current intermediate solution is R. (NWG stands for a NeW Gate. A denotes that the mode of this gate is different from the mode of gate k. ) NWGB: A gate of mode AND which is not yet incorporated in the current intermediate solution is said to be a possible cover of type NWGB. All components are *, and the gate number is assigned the value R + 1, i.e., gate R + 1, when the highest gate number of the current intermediate solution is R. (NWG has the same meaning stated above B denotes that the mode of this gate is the same as the mode of gate k. ) Types of possible covers for an uncovered component P ° = 1 In OR gate k.t A gate i of mode AND is said to be a possible cover of type G*A if gate i is connected to gate k and P. * (unassigned). G*B: A gate i of mode OR is said to be a possible cover of type G*B if gate i is connected to gate k and p.° = * (unassigned). An external input x^ (or y^) is said to be a possible cover of type VC* if x ^ for y^) is not yet connected t o gate k and x , = 1 (or y. The following mnemonic names for types are given in the same way as the case of P k for the AND gate. Therefore we eliminate the explanation of these mnemonic names. 23 GC*A: A gate i of mode AND is said to be a possible cover of type GC*A if gate i is not yet connected to gate k, the connection of gate i to gate k would not form any loops, P. = 1, and T. = or * for all j such that p£ = 0. GC*B: A gate i of mode OR is said to be a possible cover of type GC*B if gate i is not yet connected to gate k, the connection of gate i to J A gate k would not form any loops, P. = 1, and P. = or * for _ all j such that P, = 0. G*C*A: A gate i of mode AND is said to be a possible cover of type G*C*A if gate i is not yet connected to gate k, the connection of gate i J A to gate k would not form any loops, P. = *, and P. = or * for all j such that P fc = 0. G*C*B: A gate i of mode GR is said to be a possible cover of type G*C*B if gate i is not yet connected to gate k, the connection of gate i d A to gate k would not; form any loops, P. "*• *? and P. = or * for all A such that P^ = 0. NWGA: A gate of mode AND which is not yet incorporated in the current intermediate solution is said to be a possible cover of type NWGA. All components are *, and the gate number is assigned the value R + 1, i.e., gate R + 1, when the highest gate number of the current intermediate solution is R. NWGB: A gate of mode OR which is not yet incorporated in the current 24 intermediate solution is sai 1 to be a possible cover of type NWGB. All components are *, and the gate number is assigned the value R + 1, i.e., gate R + 1, when the highest gate number of the current intermediate solution is R. Since each uncovered component has two or more possible covers T, let us order the types of possible covers from the viewpoint of desirability. G*A, VC*, GC*A, G*C*A, G*B, GC*B, G*C*B, NWGA, NWGB. We call this order the desirability order ; in this order G*A is the most desirable, and NWGB is the least desirable. Defining the desirability order is based on the following observations. (One could define desirability orders differently by investigating proper- ties of possible covers from different points of view. Defining details of the desirability order is subject to experiments. ) First, the connections among gates of different modes, i.e., AND gates to OR gates, or OR gates to AND gates, are more likely to exist in optimal solu- tions than connections among gates of the same mode, i.e., AND gates to AND gates, or OR gates to OR gates. Therefore types G*A, GC*A, and G*C*A are more desirable than types G*B, GC*B, and G*C*B. Secondly, external variables are more desirable than the gates whose mode is the same as the mode of the gates under consideration. Therefore type VC* is more desirable than types G*B, GC*B, and G*C*B. Thirdly, a gate which is already connected to the gate under considera- tion is more desirable than other gates and external variables. Therefore, type G*A is more desirable than types VC*, GC*A, and G*C*A. Similarly, type G*B is more desirable than types GC*B and G*C*B. Each uncovered component has at least two possible covers, i.e., type NWGA end type NWGB possible covers. 25 Fourthly, between types GC*A and G*C-*A, type GC*A is more desirable than G*C*A, since with a possible cover of type GC*A we can cover the com- ponent under consideration without changing the value of the corresponding component, while with a possible cover of type G"*C*A we cover the component by assigning a value or 1 to the corresponding component. For the same reason, type GC*B is more desirable than G"*C*B. Finally, new gates are less desirable than external variables and exist- ing gates because a new gate costs not only a connection but also a gate. Between types NWGA and NWGB, type NWGA is naturally more desirable than type NWGB. Summarizing the above considerations, we chose the above desirability order. Using the above desirability order, we define the types of uncovered components as follows. Definition (Types of uncovered components. ) The type of an uncovered component is defined as the most desirable type among the possible covers for this uncovered component. Based on the above concepts, we establish the following set consisting of the selection criterion of uncovered components (SCUC) and the implemen- tation priority of possible covers (IPPC). The SCUC Select an uncovered component which has the fewest possible covers. If there are two or more such uncovered components, then select one of the least desirable type. 26 The IPPC Implement the possible covers of the selected uncovered component accord- ing to the desirability order. G*A--VC*--GC^--G^*A--G*B--GC*B--G^*B--IJWGA--NWGB. The possible cover of type G*A is assigned the highest priority. The motivation of establishing this set of an SCUC and IPPC is as follows . An uncovered component which has a less number of possible covers is 'hard to cover' in a sense, since if we postpone a covering of this uncovered component until later, this uncovered component will more likely lose any possible covers except two new gates (i.e., an AND new gate, and an OR new gate. ) Therefore it seems a good rule to cover first an uncovered component which has the fewest possible covers in a given intermediate solution. In the case where there are two or more uncovered components which have the same fewest number of possible covers, then let us select one whose type is the least desirable among them. Thus, we have the above selection criterion of uncovered components. Once an uncovered component is selected, we cover this uncovered component with each of its possible covers, having an augmented intermediate solution corresponding to each possible cover. We have to order these possible covers such that we generate a 'good' augmented intermediate solution first, i.e., one which is as close to a feasible solution as possi- ble. The desirability order seems one of good amies for this purpose. This is a major difference of our heuristics from Davidson's. This difference may be illustrated in the following way. The entire searching 27 process of the branch- and- bound algorithm is represented by a certain tree (called a search tree) in which the root mode corresponds to the initial solution of the problem, and non-terminal nodes and terminal nodes corre^ spond to intermediate solutions and feasible solutions, respectively. Davidson's SCUC is based on minimizing the length of paths from the iroot node to terminal nodes. Therefore, the search tree corresponding to his SCUC is shallow in depth, but it may become broard in width. On the con- trary, our SCUC is based on minimizing the number of branches originating from each node. Therefore the entire search tree corresponding to our heuristics is generally thin in width. In the next section, we introduce the lower bound of cost with res- pect to a possible cover. For this purpose we define the types of gates in the following. Definition (Types of gates.): COV: A gate k is assigned the type GOV, if gate k has no uncovered components. (Gate k may have unassigned components *. ) G*X: A gate k is assigned type G*X, if every uncovered component is of type G*A or G*B. VC*: A gate k is assigned type VC*, every uncovered component is one of types G*A, VC*, or G*B, and there is at least one uncovered com- ponent of type VC*. GC*X: A gate is assigned type GC*X,if every uncovered component is one of 28 types G*A, VC*, GC*A, G*B, or GC*B, and there is at least one uncovered component of type GC*A or GC*B. G*C*X: A gate is assigned type G*C*A, if every uncovered component is one of types G*A, VC*, GC*A, G*C*A, G*B, GC*A, or G*C*B, and there is at least one uncovered component of type G*C*A or G"*C*B. NWGX: A gate is assigned type NWGX, there is at least one uncovered com- ponent of type NWGA or NWGB. Comparing with the case of NOR problems [3], COV, G*X, VC*, and NWGX corre- spond to COV, G*, VC*, and GWG, respectively, GC*X corresponds to the com- bination of GC*0 and GC*0*, and G*C*X corresponds to the combination of G*C*0 and G*C*0*. 29 3. Lower bound c of cost with respect to a possible cover . Suppose we are given a possible cover with which we are going to cover an uncovered component of a given intermediate solution S. When we imple- ment this possible cover, we will have an augmented intermediate solution. Let S' denote this augmented intermediate solution. Sometimes the cost of S' will exceed the cost ceiling. Or some other times, the cost of S' may be below the cost ceiling, but the cost of every feasible solution derived from S' will exceed the cost ceiling. In such cases, we do not need to actually generate S', in other words, we may abandon the given possible cover without implementing it. In order to efficiently determine whether or not we may discard the given possible cover, we introduce the concept of the lower bound of cost with respect to a possible cover. Definition (Lower bound C of cost with respect to a possible cover. ) Suppose we are given an intermediate solution S and a possible cover for an uncovered component in S. Let S' denote the augmented intermediate solution which is generated from S by implementing the possible cover. The lower bound C of the cost with respect to a possible cover is the estimated lower bound of the costs of all feasible solutions that are to be derived from S' . Let us find a formula for the C which utilizes only information about S and the possible cover' under consideration (i.e., we want to calculate The following argument is for the problems which have no fan-in or fan-out constraint. For the problems^which have the fan-in and/or fan -out constraints, the formula for C must be modified 30 the C without generating S 1 .) For this purpose, let us first mention two properties of optimal AND-OR networks. (i) In any optimal AND-OR network, there is no gate i which has only one input connection. Every gate must have at least two input connections [Figs. 3-1 (a) and (b).] gate q gate i ^T") gate p gate p 1 gate p gate p 2 2 (a) (b) Fig. 3.1 A redundant gate i. If gate i has only one input connection as shown in ( a) , then we can generate a better network as shown in (b), by eliminating gate i. The network (b) has one gate and one connection less than the network (a). In any optimal AND-OR network, there is no gate i that is connected to other gates all of whose modes are the same as the mode of gate i [Fig. 3.2 (a) and (b).] 31 gate p gate q, j^Z) gate p-: gate q gate q gate q r AND gate p gate p r gate p. Fig. 3*2 A redundant gate i. If gate i and all of its immediately succeeding gates p. are of the same mode, as shown in (a), then we can generate another network with fewer gates as shown in (b) by eliminating gate i. By this reconfiguration, however, the number of connections could be increased. Notice, however, the second property holds only in the case where the number of gates is primarily minimized. Next let us investigate the properties of intermediate solutions in terms of cost evaluation. A gate of type G-*X does not require additional input connections to cover its components. A gate of type VC* requires at least one input connection from an external variable. A gate of type GC*X of G*C*X requires at least one input connection from another gate. A gate of type NWGX requires at least one gate and three input connec- 32 tions (two of them are to be connected to the new gate). However, if there are two or more gates of type NWGX in an intermediate solution, then only one among them requires at least one gate and three input connections, but the rest of them then require at least one input connection. (The reason is, by connecting a new gate to one of these gates, the types of the others may change from NWGX to GC*X or G*C*X. ) By considering the first property of optimal AND-OR networks T and the properties of intermediate solutions, we obtain a formula for computing the C with respect to a possible cover for a given intermediate solution. Let us assume that the uncovered component we are going to cover is in gate k. First, we obtain the following values with respect to the gates in the S. C, = the number of gates (excluding gate k) whose types are GOV or G*X, and which have only one input connection. Cp = the number of gates (excluding gate k) whose types are VC*, GC*X, G*C*X, or NWGX, and which have no input connection yet. CL = the number of gates (excluding gate k) whose types are VC*, GC*X, G*C*X, or NWGX, and which have input connections. Then, we find the values of d and e with respect to the possible cover under We do not take the second property into consideration, mainly in order to avoid complexity of of the formula for C. consideration. 33 -{ I 0, if the type of the possible cover under considera- tion (let us call this the pc ) is G*X, and gate k has two or more input connections. 1, if, either, the type of the pc is G*X, and gate k has only one input connection, • or the type of the pc is one of VC*, GC*X or G*C*X, and gate k has one or more input connections. 2, if the type of the pc is one of VC*, GC*X, or G*C*X, and gate k has no input connection yet. 3, if the type of the pc is NWGX, and gate k has one or more input connections. h, if the type of the pc is NWGX, and gate k has no input connection yet. e = 1, if the type of the pc is NWGX 0, otherwise. By using the above values c , c , c , d, and e> we have the formula for C: C = C + A C, where C is the cost of the given intermediate solution S, and A C = A x e + B X (c. + 2c 2 + c_ + d) . (A and B are the weights of the cost function. ) 3^ In the algorithm presented in the next section, we calculate the C for each possible cover of an uncovered component which is selected from the current intermediate solution. Then, by comparing the C's with the cost ceiling C, we accept the possible covers whose corresponding C's are not greater than the C. 35 k. Description of the entire algorithm. Incorporating the heuristic of the SCUC and IPPC and the lower hound of the cost with respect to possible covers into the basic form of the algorithm, we complete a branch- and -bound algorithm for optimal AND-OR networks . Step (Start). step 0-1: Start with the given primitive solution. Set K = and BTK = 0. (BTK counts the number of backtracks.) Set the cost ceiling C to a sufficiently large number. step 0-2: Check whether or not there are unenumerated combinations of modes AM) and OR to be assigned to the primitive solution. If yes, then assign one of the unenumerated combinations of modes to the primitive solution, forming an initial solution S . Set K = 1. Go to step 1; If no, then go to step 9« Step 1: Calculate the cost C„ of the current, intermediate solution S ; the cost is defined by A X R + B X I, where R is the number of gates, I is the number of connection, and A and B are given non- negative weights. Step 2: Search for uncovered components in the current intermediate solu- tion S^.. If S has no uncovered components, then go to step 8 (solution); 36 otherwise go to step 3« Step 3: Select one uncovered component from S , using the selection ' criterion of uncovered components (SCUC) explained in Section 2. Let P denote the selected uncovered component. Step 4: List all possible covers of P. Calculate the lower bound C of the cost for each possible cover by using the formula give in Section 3« Accept only the possible covers for which C < C holds, then sort those remaining according to the implementation priority of possible covers (IPPC), and go to step 5; in the case where there is no acceptable possible cover, go the step 7 (backtrack). Step 5; Make a double-entry list (possible cover and the corresponding C for each item) of the accepted possible covers such that the first item is the possible cover of the highest priority and its corresponding c , the second item is the possible cover of the second highest priority and its corresponding C, •••, and the last item is the possible cover of the lowest priority and its corresponding Q. Store the P and the double- entry list into a working space. Label K to this portion of working space. We call this working space the possible cover list (PC-list), and we refer to the P and its corresponding double-entry list as the K-th P and the K- th block of the PC-list, repectively. Select the first possible cover from the K-th block of the PC- 37 list. Go to step 6. Step 6: Increase K by 1. Implement the first possible cover taken at step 5, generating the augmented intermediate solution, S . Go to step 1. Step 7 (Backtrack). step 7-1: Decrease K by 1. If K becomes 0, then go to step 0-2; otherwise go to step 7-2. step 7-2: Retrieve the K-th P and the K-th block of the PC-list. If there remain no unimplemented possible covers at all, or the lower bound C of the cost for every unimplemented possible cover exceeds the cost ceiling C , then go to step 7-1; otherwise go to step 7-3. step 7-3: Reconstruct S . K Select from the K-th block of the PC-list the possible cover which was implemented last time: If the type of this possible cover is G*A or G*B, then set P. , the J n -th component of gate i, to 1 if gate k is of mode AND, or set P. to if gate k is of mode OR, where P = P, and gate i is the possible cover under consideration. Go to step 7-k; If the type of this possible cover is one of VC*, GC*A, and GC*B, then impose the condition that this possible cover (an external The following part of step 7-3 is our backtracking scheme for the AND-OR design problem, modifying Davidson's. (See [3l«) 38 variable or a gate) be prohibited from connecting to gate k in any succeeding intermediate solution. Go to step 7-^-j if the type of possible covers is different from G*A, G*B, VC*, GC*A, or GC*B, then do nothing. step 7-^: Select from the K-th block of the PC- list the possible cover immediately following the possible cover taken at step 7-3* (This possible cover has the highest priority among the unimple- mented ones in the block. ) Increment K by 1. Implement this possible cover, generating the augmented inter- mediate solution, S K - Go to step 1. Step 8 (Solution). step 8-1: Print s . Replace the value of C by . the cost C of S K . Go to step 7-1* Step 9 (Stop). Stop. All the printed feasible solutions of the lowest cost are the optimal solutions. 39 REFERENCES 1. C.R. Baugh, T. Ibaraki, T.K. Liu and S. Muroga, "Optimum network design using NOR and NOR-AND gates by integer programming, " Report No. 293> Department of Computer Science, University of Illinois, January 1969. 2. E.S. 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