LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510o84 II6r no. 111-130 cop . 3 The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. To renew call Telephone Center, 333-8400 UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN BUILDING SEP 21 1^80 SEP 2 1930 USE ONLY L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/designofcircuits127smit JULftTIC onr iio. 127 August 31, 19o2 URBfiHA, IU th The Pattern Art. Lt (PAU) which Ms bee© descri'. es a central core of IQ&k identical processing modules cs ^-dimensional array with only local connectivity. Two pc suit realisations of the stalactite will be described here. Th< s are not independent and other combira of the component cir< possible, though es described follows a somewhat differ. ■f either design will contain about 50 trans i? 50 resistors,- and 50 capacitors.. ACTITE GRGA M A schematic representation of the stalactite organisation at coa File Ho. k-$3 is shown in Figure 1. Four salient features may he observed. 1. Eight input lines fhich data fro® eight nearest - neighboring stalactites Bay be received;, .An output capable of returning signals to these eight neighbors » An input and output associated with register M, and used in communication to other devices* the Transfer Memory, and Pyramidal Readout . A logic assembly controlled by ko externally-actuated costrol lin^ The majority of the control lines are comson to all 10 erated at the same time for each. Thus identical commands are gi in all modules at once c However, the process whicl/. results in each "ferent a' -nds in general on the behavior of the neighboring al processors o ■"•?he Design of a Pattern Recognition Digital Computer by ko "The Design of a Patt- ognltion Digital Computer with Appiicat- Scanning of Bubble Chamber Hegat:: by I k and R. Narasimhan. CO O 1 -H O CO H Each input to the stalactite, including one representing the st& m output, is ir -electable by INPUT SELECTORS. This ectioa may be made conditional or not on the contents of a corresponding ?flop, depending on the setting of the CONDITIONAL GATE line e In either Be the result of se >n is fed to an IMPUT OR circuit, whose output may be gated via a CQ14PLEMEHTER to the bank of ten flipfiops or alternatively bypassed to the OUTPUT OH. The signal is gated to any or all of the eleven destinations by the actuation of a gate control line common to all stalact The required fanout and double gating of the flipfiops is achieved FLIPFLOP SIGH&L DRIVERS implied by the INCIDENT jus labelled in Figure I. The output of any flipflcp may be selected and combined in an OUTPUT AHDo The resulting information passing through the OUTPUT CQMHLEME&F suit may be complemented or cot before being combined with the bypass from the input in the OUTPUT OR. The resulting signal feeds an OUTPUT DRIVER which ?n feeds the output lines Besides the normal gates on all flipfiops and the cable driven entry to the M flipflop, an additional set of BUBBLING GATES can control eight of the ten flipfiops as a BUIBBLING REGISTER.* •.; THE BUBBLING REGISTER CONNECTION The BUBBLING GATES are controlled by UP and DOWN drivers which may be operated separately or simultaneously „ In the restricted case that only time-separate actuation of the UP and DOM drivers is allowed, the register is limited to the stacking operation only and the mechanism is termed STACKING GATES. In either case the action of the gates is inhibited by a zero on the INCIDENT BUS. Provided this bus is a one, the UP gate controls the transfer of information to a receiving flipflop from its neighbor below (having the next lower index) while DOW controls transfer to a flipflop from its neighbor above. A truth table description of the required operation for separate UP and mm pulses 'is shown in Figure 2, In the event of an UP * Report Ho. 122 . « o o H ^» O 03 H § PQ o o H O o • o 1 5 2 1 O s! l> a i) 8 O abilityo This simple sit is to the ease in whJ obling response to "simult* and T ses is required* Here, will be shown, temporary previous state essary, ?jad the required logic shall necessitate some compromise betwsei circuit complo It lenient to compare the siraiit&nsous Bubbling case with the problems >f design of simple, capacitor-driven, comrautating, binary must be sure in both cases that part way through a transit induced by one of the ir e flipflop is not loaded or "second- aer input u In the most naive 3 problem is skirted ive pulse about equal to the flipflop regeneration time but :o its settling time. The fli yy of its previous -red in the coramutating or spe apacltors hel^s ensure that the fli will settle in in which it began. M° 7 'jy providing additior raes - al charge in o^ ng capacitor- -barge must be established bef gating is again possible, false triggering due to long drive pulser e same problem of false retriggering is found in the Bubble :ase of -simultaneous inputs » Here, also, it will le temp storage of previous flipflop state as the str t that these are cone th the adjec: ien rex element shall Indicate that both girafcea and the receiving flipflop aiatiov the correct condition for a drive puis* up te in the receiving flipflop. DES1GH OF STACKING LOGIC illustrates a gating connection to a standard Tl ch v ?lc fc ion ry is simple anr ^ntlonal, being- and identic? ,hat used gister design 1 MODE OF OPERATIOH The priming information or temporary storage of the state c Uing flipfl. A, is stored in In the quies state, with UP and BOWH drivers off, C^ is charged positive through if A ■ sr is charged negative via R~ if A *= 0. During a ate of D 2 will depend on the **11 c the flipflop f A he- *ise rem: ring this Ls also chan/; eration on B is w on C and the exi<. '■- .o be C >f thit; vi .riving the i lipfLc a C, i at for th The t ;:de of spends tram* £, the value of the ble ae&up he, sit, . to remove he transistor during L1 i pre of S 1 and. the vol a it r< /Ms til ilso a strong being a1 ident i ■:l drive pi -ad the is* If P^ is returns ; - . d for a given diseb the current in IL 4d from the neighboring flirflop vbile it is in the aero state, Tger that flipfloi •6 offer's a reatsonabl ■ i t s lar£ 1 ma of > OA volts while D c a. Th sat drive on the flipflop base vill not excee ia. The The minimum DOWN pulse which the driver of Figure 2-13 will is 3.8 volts. The minimum primed voltage at the R, - D p node before results from the maximum diode drop and Vce voltages. It may he ? negative as » 0.6 - 1.2 volts. Thus when the DOWN pulae is av s node will tend to go at least to +2.6 volts and the case of transistor shall ten 2.1 vc In order that the flipflcp he gated properly its base must be above ground for the regeneration time of about 20 usee, supporting of R^, after supplying the charges te D-, the transistor base and the speedup capacitor Thus for a DOWN drive rise t: me 20 nsec, the in R^, about k ma, must be supported for about *K) nsec. Thus C- ^16*0 pc for this reason „ The stored charge in D„ is < 25 pc and that 2N960 series transistors with these operating conditions is < 100 pe. charge required for a 0. change in 25 pf is 15 pc. Thus, charge transmitted by C. must be less than 300 pc, and C, ** 150 pf sh< adequate in view of the minimum 2*1 volts available. Under the previous conditions one should investigate the re period which must be allowed between the finish of one UP/DOWN pulse a next. The maximum drive pulse available from the driver of Figure 2- depends on the -6 volt supply. The pulse varies from U.8 to 5.3 as the covers the range - 5„7 to - 6<3. In order that the flipflop be unaff by the drive pulse the tor voltage must begin sufficiently low tto will not cause D g to conduct even with the largest transistor base vo] Thus the C^ - D p node must remain below -0.6 + 0.2 or -0.U volts and therefore have been below -5.2 or -5,7 (depending on the supply voltage before the DOWN pulse can be safely applied after a previous gating c flop. Thus the C, - D p node must recover about 90 percent of its swing, a feat which can be accomplish 2.5 time constant- - A faster, though mo? design is possible using c:= diodes to -6 volts in the flipflop collectors. In this case R. can be returned with no danger to -12 volts to produce a much faster capacitor recovery. 111.0 DE3IGK OF 3UB3LIHG LOGIC Figure 2-7 illustrates gating connections to a standard fllpf: which will perform Bubbling logic. This circuit embodies an eaetension t the ideas described in connection with the Stacking Logic circuit design, 111.1 mm OF GEERATIOB As in the case of Stacking Logic design, capacitor C i provides the temporary storage of the priming information, which, however, in thin is a function of the states of both the flipflop to be gated, B, and its neighbor, A. Because of its two binary inputs £ is required to stor >rraa tion related to four states, only one of which^ the primed state, indicates that the flipflop will reverse in the event of a DOWH pulse, say. Refe: to the voltage level of the nodes U and L at the upper and lower ends capacitor C^, the gate conditions can be summarised as in Table 1. TABLE 1 1) 2) k) Input from Adjacent Flipflop (A) Input from Gated Flipflop (B) Bode U Kode L + unprlme J si ai prxiazd stat '3 •11- /ERSITY OF ILLINOIS LIBRARX In the event of a positive going DOWN pulse case k or the primed Ls the only one for vhich conduction of D 2 and gatiiig o occur, In cases 1 and 3* EU does not conduc- tive via D^ -while in case 2, though D~ conducts, node U has be^ and the added pulse voltage at will be insufficient to cause V p to CIRCUIT DESIGN The flipflop design is similar to that used with Stacking Logic, *h the load-driving requirements are more stringent. Each flipflop m irt a minimum static lead consisting of its own R« and the R 3 of the :ent flipflop,. The transient load present during the charging of C.^, ^ed but may assume various values depending on the particular states of flipflops . The -worst case occurs when the flipflop is gated directly by the LL gates shown in Figure 2»7, at a time whan flipflop A, being a >rting the current in R x and flipflop B being a 1 has released the current R p . The m a x tflMro current, partly coupled through the storage capacitors of C will be approximately (32 + i/R_ + (6 + 6)/R- + 12/Rp for the -6 volt connections to R^ and R g shown. Though, as in the case of the :king logic design, the speedup capacitor C g is of so»e help, the chargi of C 1 will be sufficiently slow as to require the Kajor part of th t as static load-carrying capability in the flipflop. jpongnte The static design of the gating elements follows generally the ideas as have been demonstrated with the Stacking Logic design., For same reasons as previously stated D^ is a silicon diode. A silicc dj de is also used for D^ where the added drop at very small currents allows the sr system to support a larger part of the load of R g than it might .'wise do. rage Capacitor A tolerance design for the determination of the value of capacitor ill not be given here due to its length* The details are similar ags those discussed previously, though the existence of additional eonjponents in the driving path via D^, introduces sufficient variability that a coin worst case design does »eem advisable. The penalty for accom?aoda= the unlikely event of accumulated tolerance would be greatly reduced sto. normal operation . As this seems to be a large price to pay, the recommended ign will, fail the usual worst case transient analysis. Though a value c .?f 150 pf has been recommended, capacitors of one third this value we: nd satisfactory on a small scale test. The time for recover;/ of cape before Stacking/Bubbling operations can proceed is estimated to be ah 500 nsec DIRECT AHD COHDITVOML IHPOT GATES ASH) XBHJT OR The two designs shown in Figures 1-1 and 2 • this function similar ir. their use of diode input logic, and differ mainly in the .evel shifting used Gating is controlled hy a separate diode gate f< sach signal input as well as by a COEDXTICISAL GATE CONTROL (Figure 1-1 and which provides cae of a pair of mutually exclusive signals to eaer Sate via resistors . With this control set to DIRECT, gating is straight- forward. With the control set to C08DXTOT&L, another level of diode log Ls caused to operate making the input gating additionally conditional upon ;he state of the corresponding register fllpflop. The result of gating a negative K l w is a negative voltage fed ihe last stage of diode logic where a negative OR function of all gated 1 Inputs is formed and amplified. :V.l CIRCUIT DESIGN The current level in the diode logic is established by the chc.< ►f the resistor labelled R x in Figures 1-1 and 2-1, which determines the linimum positive driving capability of the diode logic . Once this ehol s made the negative driving characteristic must foil t is inve rue that a design able to support some minimum load at its negat supply considerably a»re current when tolerances are nominal or at their >r ©actress This excess current, though perhaps unnecessary, must be ported by various gates, clamp diodes, saturated bases, etc., and in this i6 a powerful influence on the rest of the design,, The excess current be reduced if the load driving capability of the logic in the negative action is reduced, or alternatively it can be used to advantage —in the sent case to increase speed of operation . The former approach is followed ohe circuit of Figure 1-1, the second by that of Figure 2-1 . In Figure 1-1 an emitter follower is used to drive the outp arter, supplying it a large turaon drive, limited by the diode negative Iback, and controlling the tumoff drive from the 2.7K resistor to 46 volts, base of the emitter follower is quite easy to drive, certainly in a static se, and will require virtually no DC base current. Thus, the 8.2IC resistor 1 46 volts is used to supply leakage and stray capacity for positive going *als and represents the only static load for which the rest of the circuit X be designed. In Figure 2-1 an W8 inverting circuit is used to drive the first put transistor . Though this configuration has considerable current gain still requires a large static base current. This and various stray effects 1 < 'toe 5. IK resistor to +6 volts. The logic must be able to negative on the 5. IK as well as supply excess current for transistor 3off . Since the voltage swing at the base is limited by the conducting and a bumping diode, charging of stray capacitance is not too important. gh the logic as designed will supply only 0.3 ma of turnoff current is *wst case, its nominal operation, and thus typical speed will be much oved. JOJ^LEMESIT CIRCUITS Complement circuits (Figures 1-2, 1-7, 2-3, 2-11} are interposed i signal path between the USSMS OR and flipflop gates and between the 0U5 znd OITCFUT GR circuits. Their function is the usual one of providing sr the ixip-it signal, I, or its complement as an output, $, under control Complementers of Type 1 and 2 differ somewhat In circuit deta:i though the input and output complementers of each type are virtually the same. Each of the designs is based on +5# power supplies , +10J& resisto Veb sat " Vec sat - °' 6 ' v diode - °' 6 9ad a Binln5Um £ as indicated adjacent to the transistor in the figures (either 20 or 30). In circuits of Type 1 over-current is supplied to a large degree by the speedup capacitor of ' pf «, In those of Type 2 a speedup is not used, though the current levels co be reduced somewhat if it were. Because of the simple drive used in th case and tha loading effects of the capacitors on the drive circuit as falls negative, a smaller speedup capacitor < 20 pf would be most satisfactory. VI. OUTPUT AHD C (ROUTT The OUTPUT AHD Circuit shown in Figures 1-7 and 2-10 are identical directly to parts of the IHPOT OR circuit of the same type. Since a negative OR doubles as a positive AHD, the notation is consistent with positive w l* l s available from each flipflop's zero side output. Because of the simpler gating logic required, the diode gate input used in the IKPUT OR can be replaced by a gate signal on the gate resistor. This simplification was not available at the input due to the need for iditional gating, The external community gating drivers used, can !>e identical to the input part of the COHDITIOHAL GATE COHTROL of Figure 2 UP AHD DOWN DRIVERS Bubbling Logic and to a lesser extent Stacking logic requires UP and DOWR drive signals of well-controlled amplitude, duration and rise time. -15- purpose e >vn in Figure and - :: x _ differences are :-.-.*lated only to the input requirements of Type 1 aud Typ circu; The signal output labels are controlled by saturating trans ist> and diode bumps vhere necessary. Regeneration, designed to operate as the output signal begins to scove pos it ive ? ensures a fast -rising edge. T regenerating capacitor also serves the purpose of pulse stretching so that the minimum length of the UF and BOtfl driver can be assured by this means. Diode inputs to the base of the output transistors allow the Zr signal at the output of the IKHJT COMPLEMENT circuit to inhibit the app at the UP/DOWH drives . In order that the UP and DO!® drives be as nearly possible sim for Kibbling Operations, a separate driver used to gate both UF and IXMf incorporated, VIIXc CAHLE BtXVStS AKD TSROTHAEORS A cable driver and a cable termination gate is required for outp from and input to, flipflop M. Circuits for these purposes are shows in Figures 1-8, 1-9, and 2-9. The cable to be used lias a 93 ohm nominal impedance and is match at the receiving end by a 91 ohm termination„ During the time for wh&ch the cable driver is on, the sendiag end is also matched „ Signals of 2 to 3 volt nominal amplitude a?& transmitted in this way. Two basic designs of terminators are shown. The diode -coupled design of Figure l-9a presents only a small loading of the cable when ga and a negligible loading when not, Thus it may be used for multiple te, on a long cable if need be The transistor-coupled design of Figure l-9b presents a somewhat greater load to the cable which depends on the precise circuit configuration (Figure 1-9©). In the worst case shown the load may be as small as 300 ohms during gating but this should not cause serious reflections „ -16- te board are many and var Che majority tee di 7.istor gates negative through • to 9 volt swing, some operate via diodes at standard signal levels, • - a single one used for flipf lop gating in Type 2 circuits must go from zero to +5. Though the detailed designs are incomplete as yet and are not included in this report, they are generally similar to circuits which have been described, namely aditional Gate Control, Flipf lop Signal Drivers, the Output Driver, etc. By the use of currently available, medium power, silicon, npn, transistors li3se the Motorola MM ^C8, semi -saturating drivers capable 200 or 300 ma are easily designed, giving a fanout of perhaps 20 or so the worst case. Because of the reasonably small fanout there should be nee: for special cable or termination resistors. Gate signals which are fed through diodes in the manner of logic signals constitute a rather special problem with respect to noise allowance . The noise margin allowed in the logic is small and consistent with the snort distance over which a signal must travel from one stalactite board to the next. Gate signals on the other hand are less local and problems of inter- ground noise voltage, etc., may exist. This is particularly important for the positive swing of signals derived from grounded emitter amplifiers. Accordingly the positive signal swing of this type of gate should be e>: to about +1 volt or so. X. EXPERIMENTAL VERIFICATION Thus far, a complste Stalactite board has not yet been assembled. However, tests have been made to varying degrees on various component pt:~ts. The greater part of the effort thus far has been spent on developing an adequate Bubbling Logic system. The complexity of thic part of the stalactite alone mates it extremely difficult to perform complete tests wit out a complex logical control. However, considerable success has bee using three and four coupled flipflops and special purpose test-pulse generating equipment.* Since the complete findings of these experime will be reported on elsewhere, a brief description of the measurement tech- bs and some results only will be described here. * Test equipment has been fabricated and tests performed by D. C. Hall. -17- Tated with a group of DOWN pulses, The numbe; in ? 3 variable as was erlap of the pulse trains. By adjustment of the overlap an alternating set of UP and DC- he preceded by scans adjustable number of either e Burls period between pulse groups the flipflops could be reset to any desir initial state* Thus it was possible to controllably repeat some pulse sequence of Interest while observing flipflop behavior. Of course , in addition to the possibility of alternating pulses., overlapping pulse c were easily generated. In this way the response of the register to "simultaneous" pulses could be observed r Initial experiments were done on several different designs Bubble Logic on which the final design of Figure 2~7.» for example, is based* The designs for which most data is available differed from that of Figure 2 in the respect that the impedance level was generally higher by perhe 50 percent and the storage capacitors were disproportionately lower. There is no very valid reason, in hindsight, for lowering the impedance level the circuit to that of Figure 2-7- A marginal improvement in speed, le noise susceptibility and increased power consumption seem to be the or important factors. Measurements on the prototypes indicated that simultaneous opera- tion was possible for UP and DOWN drives coming within 60 nsec of eac and that alternate pulse operation, was guaranteed for pulses farther 270 nsec apart, using a 70 nsec pulse width. This measurement compar reasonabiy with the critical time constant of about 300 nsec for the particular circuit. The flipflop settling time measured from 10 perc c in, to 90 percent out of the last moving collector was 65 nsec. Though some confidence has been achieved by measurements of limited sort., no means is presently available for detecting false operation which may occur randomly and/or at a low rate. A devi.ce is about to constructed, with similar circuits to those already used, to make clc pulse generation conditional upon the correct flipflop having operated during the last clock pulse. Thus when the cycle stops due to failure t,he offending fl and triggering condition may be detected. -18- Is pa ' all I litions of l, ;he IKHIT OR including the total operat bime of the COR I the m percent input to 90 per an 95 nsec. The ope, -" " OT 0R > be about kO nsec from 50 percent a taken with a sir s« Th !T BRIVEE' l0ad with three 11.5 pf probes on JT DRj ms 3 been illusi bat as. However, a decision b, :uit s tier large scale tei Dr FT^ASH-THROUGH operation has been s Sype 1 circu .ouid indicate hapS a rer cu ^ possible while aents cf j ions of Type - -m the can b, capacri its. fli] and CONDITIONAL Gifi?E CONTROL were i and i ild be an obvioi; -20- -& ?55 NPN T7 £N90S MBE^S ME. XT TO TRANS ■3TES MltsHN^UM £ Ca IV£S NOMINAL ' TO IMP' CO»v^ PAN IN Or 9 I^UTt, o $$* ?3 D4- MO\T>OYA>\\. -J4J O PROWS FF-n S\DTL OUTPU (Pig kc»; \M OUT Of 9 aK rt <& 0\R.E.e-r ao M5 * FUP1 SIGK DRW (RC, J -3 SIGNAL FROhA INPUT O^. -Co TO DIRECT TR/SWSFER (F««3 1-7) INPUT COMT»V.£t«Afc*VT G,fcTE 9 »"2 ^.MfcNT TO "O" SIGN a buss (Pig »-<&»; V ■(* 520 TO tNVMBST <*ATH ON U^ DOWN DRWER5 (f\<2 1-4) o~ ~( j--rt I.8K 50 ff — -5.9 — O UP DR\VE (u) £*20 J Volts LOWVeb So.+. ATE DOWN O ^ — I GATE. Down DRIVE (O) N Hi {$. t UP M4D OOWSf DRIVERS ■4 ?^V.O? i 5 ul a 5 z *** 4 J u- t>» in J ut !S> I'- ll/I < tf i 3 & l~ i> & Z s - WOUT MENT 4.3K '£_ D\^^C" DIRECT IOKS 1 N I ' 4..3K >2.7 vTpV IQKs -fv- <3io ZENER _q V.OCAU.V DISTRIBUTED 5\GMAL JTPUT 470 > ?ROW| PP -n O S\Ot OUT PUT ( F • 3 1 -(>) 'Cm OUT GATE OUTPUT ANO, COMPtcMtHT D\^,CT TRANSVtV UTPUT QRNV -»o t 3D "POM O p* Qv^ >|= M ?..7K TERMINATOR v»o- 95 .jl COAX 0*\V£H •+ TO C*> 5fcO M TRAMS - ! - a * > a£K e.^vc ^j : ; , or* 1 t> 8-2-K yg_ as.K -% & o—v**— ■: '''■'}' IN -fc Q R\ 5. IK GATE -* INPUT -n ~(e> 'TO INPUT D\R^.CT "TRAMSFHR ^ n 8.- II ) FROM FF -n "l" SIDE OUTPUT rig 2-6. or a~?y FROM CONO\TVOh4AV- GATE. CONTRO l. •4>| 0\OOS.5 TlSt TRA^ S PKR 2»>i96>5 NPN 2h 79 7 Nuw>ae«. v\h-x»t to TR.AN&/5TOR iNDtCATfi'S MINIMUM £ FO« OE-SJOj/sj INPUT OR CATt ^19 a- 1 ITROU ~i2~ ~y!r-'~ FRT An — $ 4-"7 K I.SK .■■■•"' COMPUMH.NT Ti H£R C * I °7» ME.TAV. FILM TO U/D JNHVBIT (f. 3 &-SJ TO FMP^LoP GATE SIGNAL "O' -O-- P\ — * — jfljj O RE. SET POS. TO Gate j* PA&rr F.g 2-fe, 2-7 2 M^LG,. TO QATE •>ft"3L "I 8* • — ra-- ' DO err f V ORivE 4.7* T4 i*i . — — ©- \ooo si*. to ci=, ? ^-7; -}«.' JM >=ew>^ack: la UJ 1/7 O in A li- <\i K -S* 5T> 3 0- O < - Y >3 0- itf 3 h* 3 J- i o ^ "3 8 8 > *o 7 tn ** !0 z c _> -1 v > N ^ « o FROM :abue gate input ^U\p FI.O? (Fig 2-4 J ^io 2-e SDK 2.aK PROM O- I.Ak TO 93-*- CABLE. OUTPUT CABL^. QRlyg^ 5,<2»fc O TO PF-M GATE IWPur 4^-k: FRO M °—- TRAfcNSFHR TJLRJvnN^TEJO C^BuE GATE. M-FP CONNECTIONS P.g 2-9 ■O To Output q t e. O 'I OUT?U AUO OtA»*tE. F.$ 2-\0 r, 9 MO) TO L0C4 LA-Y DISTRIBUTED SIGNAL OUTPUT CO H\f> \Jc.*A*.UCr Ca ATE. ; OUT PUT OR y ^MD OUTPUT ORWCRS p^ a-n -2v O TO INPUT OR (Fig 8.-1) OUTPUT A NO f 1=1.3 2-1 o; input comb. (.f.^e-s) output comp.( p ^2-H) ~&. 13 ~ 2.-2S * PRECISION* \% ME.TAL.FILM + S^A-^-C"TE.D FOT3. H\G»H» £,UDW Veb Ud AT ^io -»^ DE S»G,N £- 30 \/«.b -,S TO.fc AT 4-0 >v,ct a vouT SuPRy t=i 5 2-iE, 5K 20 t — r \ tO S 5oj> ■o -o.t -Q.fe -4.4 -5.4 CO LECTORS &20 Output £\rcuit fo^ STACKmC? LOGIC UP/DOwv O^R-WER F^2.-I3 "HE* 1 npn zr- REilST DIODE DIODE ZENER COMDITI COMTRQ -} FROM EXTERN* DRIVER Q a: < o CO 4 »— < 3 OUTPUT AND, COMPLEMENT HA.TE. OUTPUT OR. OUTPUT DRIVER I «VK£N HOT SPtC.FHO EftFATA TO REPORT MO. 127 In F . ' fold -out schematic of the entire stalactite contains several errorv in the gating circuits between the flip flops o r ieking/Bubblin& register. The schematic, as shown, indicates that ihe 3." side of flip^lop N gates down to the base of the "1" side* of f lipf lop (N 4 11. It also shows the K 0" side of f lipf lop N as gating up to the "0" side of f lipf lop (N - 1). aaliy s however, as iniicc ted in the correction, each f lipf lop v s collector getes to the "opposite" base of the appropriate f lipf lop. Changes are indicated b;- a dashed ( • — — ••———•} line.