LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 ho. 22-^ co t>-Jf *L /JUiStff T 'JLlg n? -*- DIGITAL COMPUTER LABORATORY y^ t Jf UNIVERSITY OF ILLINOIS 4-\ URBANA, ILLINOIS • REPORT NO. 37 ERROR DETECTION AND CORRECTION IN BINARY PARALLEL DIGITAL COMPUTERS by James E. Robertson THE LIBRARY OF THE DEC 1 2 1969 UNIVERSITY OF ILLINOIS August 1, 1952 Retyped October, 1964 (This was submitted in partial fulfillment of the requirements for the Ph.D. Degree in Electrical Engineering, May 29, 1952.) DIGITAL COMPUTER LABORATORY UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT N0 o 37 ERROR DETECTION AND CORRECTION IN BINARY PARALLEL DIGITAL COMPUTERS by James E. Robertson August 1, 1952 Retyped October, I96U (This was submitted in partial fulfillment of the requirements for the Ph„D, Degree in Electrical Engineering, May 29, 1952.) Digitized by the Internet Archive in 2013 http://archive.org/details/errordetectionco37robe TABLE OF CONTENTS I. INTRODUCTION ... ...... 1 1.1 Purpose 1 1.2 Procedure 1 _L • j5 -t\6 SU.-L u S •■•••••••••••••■•••••••••••• 3 II. GENERAL CONSIDERATIONS ......... ...... 5 2.1 Introduction ............. . 5 2.2 Logical design techniques 8 2.21 Preliminary discussion . 8 2.22 Correspondence between vacuum tube circuits, logical diagram symbols, and operations of boolean algebra . . 10 2.3 Evaluation of reliability factors lh 2.31 Malfunctions and errors lh 2.32 Assumptions and approximations for reliability calculations ....... . 17 2.33 Decomposition of logical symbols into elementary circuits 19 2 . 3^ Order of magnitude of probability of elementary circuit malfunctions 20 2.35 Limitations imposed by the assumptions 20 2.36 Reliability and reliability factors 22 2 . 37 Errors introduced by first order approximations in probability calculations 22 2.k Description of single error detection and single error correction codes 2h 2.Ul The single error detection code . 2h 2.42 The single error correction code . 25 2.^3 Matrix formulation of the single error correction code. 28 2.5 Error detecting and correcting circuitry ..... 33 2.51 Introduction .... ...... 33 2.52 Half -adder circuits .......... 3^ 2.53 Parity check circuitry ............... . 35 2.5^ Circuitry for information transfer 38 2.55 Information transfer with single error detection ... 38 2.56 The correction matrix . ........ kl 2.57 Information transfer with single error correction ... 4 3 2.58 Information transfer with single error correction and double error detection ... ^7 2.6 Calculation of reliability factors . . ^7 2.61 Introduction ........... ^7 2.62 Error detecting and correcting circuitry switching . . 51 2.63 Reliability factors for the single error detecting system 51 2.6*4- Reliability factors for the single error correcting system ........... ..... 5^ 2.65 Reliability factors for the single error correcting, double error detecting system .... 56 2.66 Summary of results of reliability calculations .... 58 2.7 Concluding Remarks ........ . 6l -111- TABLE OF CONTENTS (Cont'd) III. THE ARITHMETIC UNIT ..................... 65 3-1 Introduction ........ 65 3.2 Representation of numbers ........ . 67 3.3 General organization of arithmetic unit 68 3.4 Effect of single error definitions on arithmetic unit design ...... 69 3*5 Addition, subtraction, and carry assimilation 71 3.6 Series of additions and subtractions 79 3.7 Positive multiplication 80 3.8 Division 82 3.9 Conclusions 86 IV. GENERATION OF REDUNDANT DIGITS FOR ARITHMETIC UNIT TRANSFORMATIONS ....... 92 4.1 Introduction 92 if. 2 Right and Left Shifts 96 4.3 Clearing all digits to zeros or ones 109 4.4 The half -adder and logical multiplier transformations . . 110 4.5 Complementation 113 4.6 Single digit modification Il4 4.7 Counter design 115 4.71 General remarks 115 4.72 Useful digit transformations for counting Il6 4.73 Redundant digit transformations for counting .... 119 4.74 Advantages and disadvantages of counter design . . . 123 V. CONTROL DESIGN CONSIDERATIONS FOR A GENERAL PURPOSE COMPUTER . 125 5.1 Introduction 125 5.2 Representation of orders 126 5.3 Non-arithmetic orders ..... 128 5.4 Control design 130 5Al Function of the control 130 5.42 Features 130 5.^3 Geometrical analogy for control design 133 5-44 Flow diagram for internal programming 135 5.5 Design details of control for general purpose computer . . 137 5.51 Introduction . 137 5.52 Order extraction and decoding 138 5.53 Orders included in simplified design 139 5.54 Flow diagram and geometrical analogy for simplified design ...... l4l 5.55 Concluding remarks l45 5.6 Error correction in control circuitry l46 VI. CONCLUSIONS ............. 1^9 6.1 Logic, information and arithmetic 150 6.2 Informational coding 152 6.3 Non- informational coding 153 6.4 Future prospects 153 BIBLIOGRAPHY 155 -iv- INDEX OF FIGURES 2.1 SYMBOLS, CIRCUITS AND EQUATIONS OF LOGICAL DESIGN 11 2.2 FLIPFLOP CIRCUIT AND LOGICAL DIAGRAM SYMBOL 13 2.3 LOGICAL SYMBOL AND DIAGRAM FOR HALF-ADDER CIRCUIT 13 2.4 MATRIX FORMULATION OF SINGLE-ERROR CORRECTING CODE FOR.m.=.4, ri = 3 . 30 2.5 CIRCUITRY FOR PARITY CHECK ON FIVE FLIPFLOPS 36 2 . 6 TRANSFER FROM REGISTER A TO REGISTER B 39 2.7 TRANSFER WITH SINGLE ERROR DETECTION k-0 2.8 THE CORRECTION MATRIX k-2 2.9 TRANSFER WITH SINGLE ERROR CORRECTION kk 2.10 SINGLE ERROR CORRECTING, DOUBLE ERROR DETECTING SYSTEM 48 2.11 DETECTION AND CORRECTION CIRCUITRY SWITCHING 52 3.1 ADDITION AND S UBTRACTION WITH CARRY ASSIMILATION 75 3.2 CIRCUITRY FOR ADDITION SEQUENCES 76 3.3 CIRCUITRY FOR CARRY ASSIMILATION SEQUENCES 77 3A CIRCUITRY FOR DIGITWISE COMPLEMENTATION 78 3.5 SERIES OF ADDITIONS AND SUBTRACTIONS 8l 3.6 CIRCUITRY FOR. MULTIPLICATION SEQUENCES 83 3.7 POSITIVE MULTIPLICATION 84 3.8 NON-RESTORING DIVISION ...... 87 3.9 CIRCUITRY FOR CARRY ASSIMILATION WITH LEFT SHIFT 88 3.10 SYNTHESIS OF ARITHMETIC UNIT CIRCUITRY 89 3.11 LOGICAL EQUIVALENT OF ORDVAC ARITHMETIC UNIT 90 4.1 GENERATION OF REDUNDANT DIGITS FOR TRANSFORMATION T (ONE REGISTER SENSED) 93 -v- INDEX OF FIGURES (Cont'd) k.2. GENERATION OF REDUNDANT DIGITS FOR TRANSFORMATION T (TWO REGISTERS SENSED) 93 k.3 6x6 MATRICES FOR SHIFT FORMULATION 98 k.k k2xh2 MATRICES USED IN SHIFT FORMULATION 99 4.5 MATRICES FOR SELECTION OF PERMUTATION GROUP FIRST NUMBERS .... 105 k.6 SEQUENCES OF BINARY NUMBERS FOR COUNTING 117 4.7 USEFUL AND REDUNDANT DIGITS FOR SHIFT COUNTER 121 5.1 INCORRECT METHOD OF PROGRAMMING T , T , and T 132 5.2 PREFERABLE METHOD OF PROGRAMMING T , T , and T 132 5.3 GEOMETRICAL ANALOGY TO SEQUENCE OF TRANSFORMATIONS OF FIGURE 5.2 . 13^ 5 . k FLOW DIAGRAM AND THREE CUBE MODEL FOR CARRY ASSIMILATION SEQUENCE 136 5.5 FLOW DIAGRAM FOR SIMPLIFIED CONTROL DESIGN lU2 5.6 TWO-DIMENSIONAL REPRESENTATION OF SIX CUBE 1^3 5.7 SIX CUBE ANALOGY TO FLOW DIAGRAM ikk -vi- INDEX OF TABLES 2 . 1 PROPERTIES OF A BOOLEAN ALGEBRA ........ 15 2.2 CALCULATION OF SINGLE MALFUNCTION PROBABILITIES; SINGLE ERROR CORRECTING SYSTEM ............ k6 2.3 CALCULATION OF SINGLE MALFUNCTION PROBABILITIES; SINGLE ERROR CORRECTING, DOUBLE ERROR DETECTING SYSTEM ^9 2.4 ERROR PROBABILITIES FOR ERROR PROTECTION SYSTEMS 60 3.1 ADDITION TABLE FOR TWO BINARY DIGITS 72 4.1 ARITHMETIC AND CODING ADDRESSES 107 5.1 LIST OF ORDERS FOR SIMPLIFIED COMPUTER DESIGN . lUO -VI 1- CHAPTER I INTRODUCTION Section 1.1 Purpose Within recent years, techniques have "been developed for suitably coding redundant information for transmission with message information in such a way that single errors in the received infor- mation can he detected or corrected. It is the purpose of this thesis to present the design considerations essential for the application of the Hamming single error detecting and correcting codes' to the cor- rection of errors occurring during a digital computation, The theory developed for single error correction during transmission of infor- mation can he applied for correction of a single error occurring during transfer of a set of message and redundant binary digits, a single error being defined as a change of a single digit of the given set. For error correction in a binary parallel digital computer, we must extend the theory to apply not only to transfers of sets of binary digits, but also to the transformations upon sets of binary digits required for effecting the operations of arithmetic, Section 1.2 Procedure We first present, in Chapter II, the fundamental considerations necessary for the design of a digital computer employing automatic error detection or correction. In particular, logical design techniques, reli- ability considerations, a description of the Hamming error correcting and detecting codes, and a description of circuitry for correction or detection of errors during information transfers are presented. -1- -2- A digital computer is ordinarily subdivided into four functional units: the input-output unit, the memory, the arithmetic unit, and the control. The major problem in the application of error detecting or correcting codes to digital computation arises in connection with transformations upon the digital information. We need pay only cursory attention to the input -output and memory units, since the functions of these units are transfer and storage of information. The arithmetic and control units, however, involve information trans- formations; there is, furthermore, little similarity between the infor- mation transformations required for control purposes and the trans- formations necessary for arithmetic operations. We therefore treat the arithmetic and control units separately. Use of the Hamming single -error correcting code imposes rather severe restrictions upon the design of the arithmetic unit. Two features of this code — namely, the definition of a single error as a change in a single binary digit, and the fact that protection against no more than two simultaneous errors is provided- -render con- ventional arithmetic unit designs useless for our purposes. The diffi- culty arises in connection with addition with carry propagation; a single malfunction in the carry propagation circuitry can produce errors in all digits through which the carry would otherwise propagate. In Chapter III we describe an arithmetic unit design based on transformations logically more fundamental than addition with carry propagation. Further difficulties in the design of the arithmetic unit arise in connection with the redundant digits. The redundant digits are related to the u seful digits in such a way that the set of useful and redundant digits conveys sufficient information to specify the correct configuration of the useful digits, even though a single error has occurred. When an arithmetic transformation is made upon the useful digits a transformation must also be made upon the redundant digits in such a way that the aforementioned property of the total set of digits is maintained. The numerous difficulties arising in redundant digit generation are described in Chapter IV. Attention is next turned to the control unit. The nature of the information transformations necessary for control purposes and tech- niques of control design are discussed in Chapter V. Information con- siderations lead to a minimum flipflop control design. Various problems, as yet unsolved, arising in connection with error correction within the control unit are also described. The final chapter is devoted primarily to a discussion of automatic error detection and correction from a general viewpoint. A variety of possible methods of automatic error correction are described, with a qualitative, and in some cases conjectural, discussion of diffi- culties to be encountered with each method. Section I. 3 Results Numerous problems arise in connection with the design of a digital computer with error correction facilities. Some solutions to problems presented in the following pages are generally applicable in the field of digital computation; other solutions possess limited applicability. -h- In particular, the arithmetic unit design presented in Chapter III has several features which warrant its consideration in future parallel computer designs . The control design techniques leading to the minimum flipflop design presented in Chapter V were successfully applied (7) in a limited way in the design of the ORDVAC, Solutions to problems arising in connection with redundant digit generation are specifically applicable only to the design of a computer employing the Hamming single error correction code. Techniques of solution may, however, provide some insight for solution of similar problems for an error correcting computer based upon the same definition of a single error- CHAPTER II GENERAL CONSIDERATIONS Section 2,1 Introduction The necessity for increased reliability is a major problem in the digital computer field. In this chapter we shall show that the single-error detection and correction codes of Hamming can be used to increase the reliability of the transfer of information. In the pro- cess, several design restrictions peculiar to an error-correcting computer become apparent. It is necessary to discuss several fundamental considerations. The design techniques typical of the digital computer field, a method of evaluating reliability quantitatively, and a description of the single error detection and correction codes of Hamming are presented. Specific circuit designs for error detection and error correction are then discussed and reliability of transfer of information with and with- out error correction is calculated. The use of vacuum tube or analogous circuits in an off -on fashion permits idealizations which allow a computer design to be carried out in two phases. The first is the logical design phase in which, for an asynchronous design, timewise steps are translated into successive flipflop states and the flipflop states are interpreted by "and," "or," and "not" operations to produce desired signals. The logical design phase involves preparation of a logical diagram composed of block symbols for flipflops, and "and," "or," and "not" circuits. The second design phase is one of translation from the logical diagram ■5- -6- to a detailed circuit design. The latter phase is to a very great extent dependent upon the circuit techniques employed, Given equiv" alent logical diagrams, detailed circuit designs vary widely from one computer group to another,, In order to preserve generality designs presented in following sections will he logical designs. Section 2„2 of this chapter will he devoted to a discussion of logical design assumptions and techniques . It is essential that we define explicitly a number of terms ordinarily used rather loosely . We define the term malfunction as the failure of a circuit to produce the correct response from a given set of stimuli . If a malfunction affects a given set of binary digits in such a way that one of the digits is incorrect, we refer to the result as a single error in the set of digits. To evaluate reliability quantitatively, we calculate a figure called the reliability factor indicative of the mean error-free time of the complex of circuits under consideration, We calculate the reliability factor in the following way: We decompose each symbol appearing on a logical diagram into an integral number of elementary circuits, (An elementary circuit for vacuum tube designs corresponds to a single triode unit or diode unit.) We assume that the probability of a malfunction in each elementary circuit is the same. We then approximate a typical situation for an operating computer with the assumption that all circuits are initially operating correctly and proceed to calculate the probability of a malfunction (or perhaps a given sequence of malfunctions) during an arbitrary number of _7- operations. For the calculation the additional assumption is made that the probability of a malfunction in an elementary circuit is dependent upon the number of times the elementary circuit is used. For circuit systems in which circuits are not provided for error detection or correction, the calculation of the probability of an error during a given sequence of operations consists of determining the number of times each elementary circuit is used and summing over all elementary circuits utilized during the sequence of operations „ When error detecting or correcting circuits are employed, the calculations are more complicated, since we must not only consider probabilities of detectable errors, correctable errors, and non-detectable errors; but we must also take into account the fact that some errors are caused only by multiple malfunctions occurring in a given time sequence. It is clear that several approximations are inherent in the calculation of the reliability factor discussed in the preceding paragraphs. The number of elementary circuits associated with a logical diagram is only an approximation to the number of circuit components in an equivalent physical design. The decomposition of the logical symbols into elementary circuits also is an approximation. Finally, the simple summing of prob- abilities of malfunctions of individual elementary circuits to yield an over-all probability of failure is a first order approximation valid only when the probabilities are quite small. The assumptions and approximations are discussed in section 2.3i it will be shown that the approximations are reasonable for circuits currently used in digital computers „ The theoretical basis for single-error detection, single-error correction, and single-error correction with double-error detection -8- as originally described in Hamming's "Error Detecting and Error Correcting Codes' is summarized in section 2.4. A matrix formulation of the single- error correction code necessary for subsequent considerations is also presented in section 2.4. The remainder of Chapter II is devoted to a comparison of various systems for protection against error during information transfers. Logical diagrams of circuits used for transfers and for error detection and correction are presented in section 2.5. Effects of single malfunctions in transfer circuitry are also discussed. A system of detection or correction circuitry switching for sequences of transfers is described in section 2.6; reliability factors for transfer systems with various degrees of error protection are then calculated. The relative merits of the various transfer systems are discussed in section 2.7. Section 2.2 Logical Design Techniques 2.21 Preliminary Discussion The use of vacuum tube or analogous circuits as off-on devices permits idealizations which simplify digital computer design techniques. The idealizations lead to what is called logical design. We shall subdivide logical design into two phases, the static and the dynamic. For the static phase, certain circuits are represented in terms of the logical operators "and," "or," and "not." Complexes of circuits can be represented in two simplified forms: (l) as logical diagrams composed of block symbols for "and," "or," and "not," and (2) by corresponding equations of Boolean algebra. The static design phase is subject -9- to analysis "by Boolean algebra techniques and "by techniques developed by the Harvard Computation Laboratory and others . The binary variables considered in the static design phase usually arise from flipflops, or from equivalent bistable circuits.. A typical static logical design problem consists of sensing n flipflops to produce one binary output signal o The n flipflops are capable of assuming 2 states. It is specified that the output signal is stimulated for some subset of the 2 states and not stimulated for the remaining states. Many arrangements of "and," "or," and ,: not" circuits sensing the n flip- flops to produce the desired output signal can be found, corresponding to many factorizations of the Boolean polynomial describing the output signal . The particular factorization corresponding to a logical diagram having the least number of logical elements will be presented in future designs. The corresponding physical circuit design may or may not have the least number of circuit elements or may be undesirable from circuit considerations beyond the scope of a logical design, It is clear that time does not appear as a variable in a static logical design; the speed of operation of physical circuits does not appear in a Boolean equation. A logical diagram may represent equally well relay circuits requiring milliseconds to operate or vacuum tube circuits requiring microseconds to produce a signal. We shall present, particularly in connection with sequencing circuits, logical diagrams in which it is implicit that a finite time is required for a particular flipflop state to produce an output signal.. In describing the action of computer cir- cuits, one says that operation number 1 is followed by operation number 2. -10- Circuitwise, a set of flipflops is sensed to stimulate a signal producing operation number 1. Operation number 1 is used to change one or more of the flipflops sensed. The change to a different state of the flipflops turns off the signal producing operation 1 and stimulates a signal producing operation number 2. Such a system is described as being kinesthetic — that is, one operation is sensedto produce the next--and asynchronous --that is, no synchronous source of pulses is used for sequencing operations. Such kinesthetic systems can be represented by logical diagrams; because of the necessity for sequencing no method of analysis other than intuitive trial and error is at present available for finding a minimal kinesthetic system. Further discussion of the dynamic logical design phase is deferred until Chapter V, where sequencing circuits are described. 2.22 Correspondence between vacuum tube circuits, logical diagram symbols, and operations of Boolean algebra. In Fig. 2.1 are indicated the Boolean algebra notation, the logical diagram symbols, and vacuum tube circuits corresponding to the logical operations of "and," "or," and "not." The vacuum tube circuits shown are standard circuits used by the Electronic Digital Computer Department at the University of Illinois and are based upon the assumption that a negative signal is the stimulating signal. For example, for the "and" vacuum tube circuit shown the output signal z is negative only if input signals x and y are negative. If the opposite assumption that positive signals are stimulating signals is made, the roles of the "and" -11- OPEeATlON VACUUM TUBE CIRCUIT LOGICAL DIAC3EAK/1 SYMBOL 4 BOOLEAN AL1A GJC CIRCUIT X X LOGICAL DIAGRAM SYMBOL.. F1G.2.Z- FLIPFLOP CIRCUIT 4 LOGICAL DIAGRAM SYMBOL X-t-Y X4-Y x-t-y-^xvYYx'VY') X-HY X+Y - XY'VX'Y FIG. £3 ^ LOGICAL SYMBOL log 2 m For five to eight flipflops, k = 3? for nine to sixteen flipflops, k = k, etc. The probability of a single malfunction in the half -adder circuitry for a parity check on m flipflops is l(ra.-l )p. We assume that each possible malfunction will produce an error in the parity check signal e, although for certain flipflop states this may not be true. ■36- FLIPFLOPS *4 PAI2IXY CUECK UALF -ADDEES G> X,+ X O X 3 4-X« Civ e - x , + x z -h x 3 + x 4 4 X v~^r^r^ x FIG. 2.S- CICCUITCY «*2, PABITY CMECk. ON FIVE FLIP- FLOPS. -37- As discussed in section 2„53; the parity cheers output signal may "be in error in two ways . Most error-producing malfunctions will cause "both e and its inverse e' to be in error; however, a malfunction in the inverter of the final half -adder of the parity check circuitry may cause e : to be in error while the signal e is correct . The latter case is important in the error detecting and correcting systems to be considered. The exact expression for the probability of one or more malfunctions would include, in addition to the first order term 7(m-l)p, terms in 2 3 F > P } etc., arising both from probabilities of multiple malfunctions and from the approximation inherent in the calculation of the proba- bility of the single malfunction . The higher order terms can be neg- lected for elementary circuit malfunction probabilities of the order encountered in a reliable digital computer circuit design. A question which arises in connection with detection and correction circuitry parity checks is this: what is the probability that a parity check malfunction followed by a flipflop or gating mal- function will be such that the flipflop or gating malfunction will not affect the parity check output signal? A malfunction in the final half- adder of the parity check circuitry will mask completely all ensuing gating or flipflop malfunctions; a malfunction in a half -adder sensing two flipflops will mask subsequent malfunctions affecting only the two flipflops sensed. For a parity check on 2 flipflops, it is evident that the desired probability is — . For m flipflops, where m ^ 2 , we 2 n shall approximate the desired probability by — where n is the smallest integer which exceeds log p m„ -38- 2. 5^- Circuity for information transfer Figure 2.6 illustrates a technique which can he used for transferring information held, hy four digits x , x , x , x< of register A to corresponding digits y , y , y , y. of register B hy a gating stimulus G„o h The prohahility of an error in the transfer is simple to calculate. We need only calculate the first order approximation to the prohahility of a single malfunction, hased upon the assumption that the information in register A is correct and ignoring the proh- ahility of failure of the gating signal G,,. Since there are six elementary circuits per digit, the single error prohahility for m digits is simply 6mp. 2.55 Information transfer with single-error detection Figure 2.7 illustrates the method of transferring four bits (binary digits) of information from register A to register B with a fifth redundant digit added for detecting a single error. The redun- dant flip flop, which may be any one of the five flipflops of register A, is initially set so that the number of ones in the five flipflops is even. If no malfunctions are present, the error indi- cation signal will indicate 0, the inverter output indicating 1, which enables the gating signal G^ to transfer the contents of register A to register B. We shall calculate the probabilities of single malfunctions in the system of Fig. 2.7. For m useful digits, the probability of a malfunction in one set of gates and one set of flipflops is 6(m+l)p. ■39- -*-f <*Mn0) ~@- -—{fai & G& •— t rtG.Z.G^TQ/lNSFEQ FROM REG/STER 4 TO QEGfSTER 6. B (t> *-KkoS — »~ -*-^M^— *»- ERROR G s iNDiCA T/OA/ FIG. 2.7- TMNSFEG WITU SINGLE EQQOQ DETECT! OM . -kl- The probability of a malfunction in the parity check circuitry is 7mp, the figure 7 being based upon a half -adder consisting of a total of three "and" and "or" circuits and an inverter. The probability of a malfunction in either the inverter or the "and" circuit associated with the error indication and gating signals is 3P° For the circuitry of Fig. 2.7, any single malfunction which changes the error indication signal and its inverse are detectable. 2.56 The correction matrix A rather common logical design problem is the decoding of n independent binary input signals to generate 2 output signals. A cir- cuit effecting this decoding is called a matrix. One characteristic of the matrix circuit is that only one output signal is stimulated for any one state of the input signals. For single error correction, a matrix must be provided for the decoding of the parity check signals. An example of the type of matrix design suitable for error correction is indicated in Fig. 2.8, The design shown requires 2k elementary cir- cuits; for n input variables, n» 2 elementary circuits are required. (2) For n > 3, matrix circuits can be more economically designed; however, a design of the type shown insures that no single malfunction in the matrix circuitry will affect more than one output signal. Any single malfunction in the matrix circuitry will affect only one output signal. The "0" output signal and the m + n output signals associated with the useful and redundant digits have different effects; malfunctions in these circuits must be considered separately. ■k2- -~-WHP) < ~ e' — / ■W4/X0} ■^L \ -+-{0rtl>\ -~2 ■H- •A «-»»« — ^ ? FJG.2.S*. TUE C0ZZ£CT7ON MATg/X -43- The probability of a single malfunction affecting the n 0" signal is np; for the m + n digits, the probability is (m+n)(np). 2.57 Information transfer with single-error correction The circuitry required for single-error correction is shown in Fig. 2„9° The circuits shown will correct single errors in the four useful digits x , x , x^-, x , and in the three redundant digits x , x , Xi . The: redundant digits have previously been determined by the coding process discussed in section 2=42. The checking pro- cess is effected by three parity check circuits whose outputs are the error location signals e., e p , e in Fig. 2.9- The n = 3 error location signals are converted to 2 -1=7 correction signals and a no- error signal by the correction matrix. Each of the correction signals is applied to a correction half-adder; the other input to the correction half -adder is the corresponding sensed flipflop of register A. Gating circuits are provided for transferring the correction half-adder out- puts to the flipflops of register B. The operation of the error-correcting circuitry is fairly straightforward. Let us assume, corresponding to our example in sec- tion 2.4 (Fig. 2.4), a single error in the flipflop representing the digit x^. The flipflop is sensed in the two parity checks which yield the error location signals e, , e . Since x^ is in error, e. and e are stimulated. The corresponding matrix output "6" is stimulated so that the output of the correction half -adder associated with digit 6 is correct. The gating stimulus G^ will then transfer the corrected Jd I -kS- information to register B. The occurrence of the single error was indicated by the fact that the no-error stimulus failed to appear . Two features of the single-error correcting system require further comment. First, the parity checks are independent; that is, no parity check half -adder is used for the generation of more than one error location signal. For example, two separate half-adders are used to generate (x^ + x ) which appears in the generation of both e, and e . The practical effect of parity check independence is that a single parity check malfunction will not introduce an error in any of the useful digits, but only in one of the redundant digits. The second feature of the error- correcting system is that it is permissible that one of the flipflops of a register be in error. If there are no malfunctions in the correcting circuits, the outputs of the correction half -adders are correct; errors resulting from any subsequent gating or flip- flop malfunctions are corrected during the next transfer of information. One might say that the gating cycle is out of phase with the correction cycle; the former occurs from register flipflop to register flipflop, the latter from correction half -adder output to correction half -adder output. The dis- tinction between gating cycles and correction cycles becomes more important when transformations other than the special case of information transfer are considered. It is necessary to consider the effect of malfunctions in all circuits of the error-correcting system. Effects and probabilities of various types of single malfunctions are summarized in Table 2.2. Malfunctions of the inverters of the final half-adders of the parity check circuits are considered separately from the remaining parity check malfunctions, since the effect of these malfunctions on correction matrix outputs is different. Discussion of effects of multiple malfunctions is deferred to section 2.6. -k6- M EH M H PQ O Ph O M EH O >> a -P o •H H •H H bO -P •H !=! CJ ,0 -H d co ra 3 £> , j Si m cO ,£J -P co g a +3 3 •H s B 2 O rH H u aj W •H P O o ch EH O co ^ p a; •H ,o cm 3 s O CJ 2 f» S d ?H >3 fH ft cO p CO p •rl 2 3 o CJ -H •H w P O CD Cm cm CO cb p P •H CO 3 o CJ •M fn t3 •H « o a) . 3 P Jh •H •H i Ch G •H H u =H ft •H O P p rH •H CO CO CO H X M s B 43 ch CJ CJ cu CU G S3 a ^ .3 B O O o a o CJ •H P •H p •H p CO >i t>a CJ O CJ bO p -P 0) » •H H g P a a CO o ft B o M p p H 3 g ch ft O CO ft XI p ■H H P M H O •H o Ch £ ft H B P CO ft H a C! O cO bO H ■rf •H ch • r_J to ft H p •H CO >d M H a o ch bO M M •H M P to M a o | cO M o ^d O H a a M d ^s M ch tj p 1 CO CO u o 3 H a ^s a a B •H •H •H CJ P M 2 H CO o T5 o M O *H o M H fn p ft H f>j •H H rH r-\ CO bO P bO ch a S3 G •H •H M to a to cO ,£ CO s to P • ^ •H H CJ CJ CO 3 ft rt ^ bfl O a O ^ -H M cO ^ S to OJ o -4- -V7- 2:58 Information transfer with single-error correction and double-error detection The single-error correcting, double-error detecting system is in a sense a combination of the single-error detecting and single-error cor- recting systems* As is indicated in Fig. 2.10, an error detection digit x is added to each register . A detection parity check on x and on all useful and correction redundant digits produces a detection signal e_ which indicates whether an even or an odd number of errors has occurred. Correction signals for the detection and correction redundant digits and for the useful digits are enabled only if a single error has occurred. Error indication signals for no error, a single error, and double errors are pro- vided. The operation of the single-error correcting, double-error detecting circuitry is analogous to that of the single-error correcting system, except that a double error in the register flipflops will not be erroneously "corrected. " Calculation of probabilities of various types of single malfunctions and a listing of their effects is given in Table 2..3» Discus- sion of multiple malfunctions and their effects is presented in section 2.6. Section 2.6 . Calculation of reliability factors 2„6l Introduction Thus far we have considered circuitry for a single transfer from one set of flipflops to another, with and without error detecting and cor- recting circuitry. Effects of single malfunctions during the transfer 4 9 - ft 2, ft ft ft >H CQ °<\ CQ ft W ft H H EH EH H ft 1-3 H h EH ft H > a p cu o •H H -H H W)P •H Pi O ft p -h a ft- cd co ^ H ,£> , ft O ft H m o cd Ph S !>> h H cd ft P co B Pi ft pi 0) •H ft S 3 cu O H H Fh cd W •H P O o ft ft o rQ ft 3 S o o PS H O m >i OJ u P^ cd P p CQ •H p) P Pi cu •H CJ B Pi H cu CJ •H H Fh O W •H O p o cu ch <+h co CU P P •H cd pi o O -H M T3 o Pi o •H P •H CJ a CU pi P ch O H a cd P s o O Ch ft O -4- H H r-t ft E ft ft- H t- ft CM ft H i ft? + ft H i ft ft OJ + CM + H ai OJ + ft OJ + OJ + 3 OJ + OJ ft + + s ft- ft + a + VD MJ CO OJ M CO 00 OJ cu P CO p p •H ft p 1 •H M Pi H •H !>j Pi CU CJ cd M (h CJ > M a •H P u ps ■H bO ^ •H •H •H O •H Pi o CO Td a CJ J*i J*i P! o m M ^ O CJ M cd •H co ■H o CU cu o P P O *> >s 1 cu u m Jn o :>> p p o co o co •H •H p •H •H a PS o M a bo •H 14 H CU o H cd cd ^ ft H cd ft ft oo ... T3 o ft X X cd H a ps Pi ■H •H i ft o a o o ?H H ft ft •H o •H •H p P ft •H p •H P P cd cd cd ft cd P CJ O g B ^ ft o O CU CU ■H CU M M PJ P! P! TJ 13 P H H O o o Pi PI CU o O •H ■H •H cd ■H <6 O O P CJ P O P O W M u u H CU CU CU Pi o o o o M M M •H M H M M H H H P M M H H O o o cd W ft w ft O o ft ft P Pi cd -tf Pi pi tH CU H Pi o •H P CJ CU H M O CJ U o ft Pi ft (U CO Pi P CJ CU ft ft cd ft p o o ft Pi ft ft co •H cu ft o ft T5 o P •* ft Pi CO cd cd ft a > rO CU p pi ft o cu pi — - — '- 2 065 Reliability factors for single-error correcting, double-error detecting system We now calculate reliability factors for the single-error correcting, double-error detecting system of Fig. 2.10 with gates pro- vided for correction circuitry switching as discussed in section 2.62. For this system we wish to determine the following error probabilities during a sequence of r transfers: 1) The probability of a detectable error 2) The probability of a correctable error 3) The probability of an error which is neither detectable nor correctable. A detectable error results if the double -error indication signal is stimulated. Any of the following single malfunctions stimulate the double- error indication signal: 1) A malfunction in the error detection or correction parity check circuits 2) A malfunction in the correction half -adder or "and" circuits associated with the "0" signal 3) A malfunction in the gating and flipflop circuits associated with the error detection digit ■57- k) A malfunction in the double error indication circuitry The probabilities of single malfunctions in these circuits are, respec tively, 7 (m + n) + — (m + n - l)n p, (n + 9)p, lOp and 8p„ The relia- bility factor for r transfers is then -J7 (m + n) + -(m + n - l)n + (n + 27) r rp A correctable error results if any single malfunction occurs in the gating or flipflop circuits, correction half -adders, or matrix "and" circuits associated with the useful or correction redundant digits. The probability of such a malfunction during a single transfer is (19 + n)(m + n)p and the reliability factor is (19 + n)(m + n)rp We now wish to determine the probability of an error which is neither detectable nor correctable. A sequence of at least three mal- functions is required to produce an error of this type. The malfunctions may occur in such a way that correctable errors occur for a time, but not in such a way that a detectable error is produced. We designate by the letters, A, B, C the occurrence of malfunctions in three groups of cir- cuitry, as follows : A represents the occurrence of a single malfunction in the half-adder or inverter used for generation of the double error indication signal. -58- B represents the occurrence of a single malfunction in the matrix "and" circuits, the correction half-adders, or the gating or flipflop circuits associated with the m+n useful and correction redundant digits - C represents the occurrence of a single malfunction in the correction parity check circuits.. The following sequences of triple malfunctions lead to an error which is neither detectable nor correctable: ABC, ACB, ABB, BAB, BAC. Corres- ponding to A, B, and C are probabilities p A , P B , and p c (during a single transfer) as follows: P B = (m + n)(l9 + n)p n P c = £(m + n - l)np The probability of the occurrence of the sequence ABC during r transfers becomes r i r I ( Z 1P A P B )P C = £ |J(J + 1)P A P B P C = l (r2+ 3r + 2)P A P B P C j=l i=l ~ 3=1 The desired reliability factor is | (r + 3r + 2)p A P B (2p B + 3P C ) which after substitution of values of p , p , and p , yields I (m + n)(!9 + n) PI 2(m + n)(l9 + n) + — (m + n - l)n p 3 (r 3 + 3r 2 + 2r) 2 066 Summary of results of reliability calculations The following reliability factors have been calculated: l) Transfer without error protection 10 mpr -59- 2) Transfer with single error detection a. Detectable error (17m + 10)pr b« Undetectable error 35n(m + l)p (r + r) 3) Transfer with single error correction a. Correctable error (IT + 'n)(m + n) + Mm + n - l) - 1 npr b. Non-correctable error I J 7(m + n - 1)-, 2 (17 + n)(m + n)n + (17 + n) 2 (m + n) 2 | p 2 ( r 2 + r) k) Transfer with single error correction, double error detection a. Detectable error 7 (m + n) + — (m + n - l)n + (n + 27) r Pr b. Correctable error (19 + n)(m + n) pr Co Non-correctable undetectable error (m + n)(l9 + n) 21 2(m + n)(l9 + n) + — (m + n - l)n p 3 (r 3 + 3r 2 + 2r) As an example, we now calculate numerical values of these reliability factors for the values of the variables : -60- m = ko n = 6 pr = 10~ (r > 10 for p < 10" 12 ) The value of p is that calculated in section 2.34. The value of r is sufficiently large that all but the leading terms in the polynomials in r appearing in the expressions for reliability factors can be neg- lected.. Substitution of the values listed yields the numerical results given in Table 2.4. Also given for comparison purposes are the number of elementary circuits required for the various systems. TABLE 2.4. ERROR PROBABILITIES FOR ERROR PROTECTION SYSTEMS Transfer without, error protection Transfer with single error detection a. Detectable error b. Undetectable error Transfer with single error correction a. Correctable error b. Non- correctable error Transfer with single error correction and double error detection a. Detectable error b. Correctable error c. Non-correctable undetectable error pr = 10 0.04 -4 O0O69 0.00009 0.2 0.016 0.13 0.12 0.000008 Elementary Circuits Required Error Transfer Protection Total 480 820 920 940 280 1564 2007 480 1100 2484 2947 ■61- The numerical values listed in Table 2 ok are results of rather gross calculations "based upon a number of pessimistic assumptions . The formulas developed have also the distinct disadvantage of holding only when terms on the order of m n p r are small, which limits r to values smaller than those which are of greatest interest . Despite the numerous limitations, the results do provide some insight into the relative merits of the various systems , Section 2.7 Concluding remarks The four transfer systems can be compared with the following characteristics in mind: 1) Reliability factors 2) Protection against computational errors 3) Ease of troubleshooting k) Expense, i.e., number of elementary circuits required The transfer system without error protection is the least expensive, provides no protection against computational errors, and is the most difficult to troubleshoot . The transfer system with single-error detection requires more than twice as many elementary circuits for a double register system with detection circuit switching and provides protection against computational errors, with roughly 75 per cent increase in the prob- ability of error. Troubleshooting is somewhat simplified, since an indication of which register has the faulty component can be obtained for gating or flipflop malfunctions. -62- For the system involving single-error correction, the amount of circuitry is increased "by a factor of 5 with a corresponding increase in the probability of errors, an error being defined in this case as the absence of the "no-error" indication signal. Such errors resulting from single malfunctions are correctable; information is available during the correction process specifying the location of the malfunction within a small group of circuits. It would seem "best to record such information automatically when corrections are made and to allow the computation to proceed after the information is recorded- At the completion of the com- putation, the recorded information would be quite useful in trouble- shooting. The positive assurance that no malfunctions had occurred during the computation, indicated by the absence of recorded information, would eliminate doubt concerning the accuracy of computed results often encoun- tered in computers without error protection. The single error correcting, double error detecting system has advantages not possessed by the single error correcting system. Malfunc- tions in the detection and correction circuitry, which are the cause of the majority of the detectable errors, could conceivably be repaired by human intervention without affecting the computation. Correctable errors could be recorded and corrected automatically with very little loss of computation time. The probability of a non-correctable, undetectable error is seen to be quite small for the particular value of pr of the numerical example. The major advantage of the detection-correction system ■63- over the correction system is this; after a single malfunction resulting in a correctable error has occurred, the occurrence of a second, malfunction will produce a double error indication signal; for the correction system a second malfunction produces a triple error invalidating the computation. The double register transfer system described is misleading in several respects* In a digital computer, a large percentage of the circuitry is required for transformations of register contents rather than for transfers; circuitry for more than a pair of registers and a pair of transfers is necessary. Thus, the factor of 6 in the amount of circuitry required for the correction, detection system as compared to the transfer system without error protection is greater than the corres- ponding factor for a complete digital computer. A second characteristic of the transfer case not typical of the general case is that each flip- flop is always in the same state and each logical circuit is either always stimulated or always not stimulated. Generally the states of the flipflops and logical circuits change as the information stored in the registers is transformed . Certain types of parity check malfunctions become detectable--the error detection system is an example--if it is assumed that the register information changes. The calculations of the reliability factors were based on a number of pessimistic assumptions. One of these—that all malfunctions are permanent --merits further consideration. The elementary circuit mal- function probability p is the probability of either a permanent or tran- sient malfunction. In the calculation of double malfunction probabilities, -Gi- lt was assumed that both malfunctions were simultaneously present, although it might be expected that in many cases the first malfunction was transient and had disappeared before the second malfunction occurred. Thus, multiple malfunctions are less likely than the calculations indicate. Future designs will be based upon the single -error correcting, double-error detecting system. It will be assumed that any single flip- flop of a register may be in error, as discussed in section 2.57° The latter assumption affects future designs, particularly those described in Chapter IV. CHAPTER III THE ARITHMETIC UNIT Section 3° I Introduction The primary function of the arithmetic unit of a binary parallel digital computer is the transformation of sets of binary digits representing operands in addition, subtraction, multiplication and divi- sion into sets of binary digits representing the results of the operations The arithmetic unit must have storage facilities for the operands and for intermediate and final results, as well as circuitry for suitably trans- forming the sets of binary digits so that desired arithmetic results can be obtained o The logical design of the arithmetic unit is affected to a very great extent by two considerations: 1) The representation of numbers within the arithmetic unit. 2) The selection of the fundamental transformations from which the arithmetic operations are compounded. The arithmetic unit design presented here may perhaps best be (7) described as a departure from designs for the ORDVAC and Institute for (3) Advanced Study computers. Points of similarity include the represen- tation of numbers, described in section 3-2, and the general logical structure of the arithmetic unit, described in section 3 '3° The point of difference is that the transformation of addition with carries con- sidered fundamental in the ORDVAC is replaced by two transformations logically more fundamental, namely, digitwise addition module 2, and ■65- -66- logical mult iplicat ion . The necessity for this difference in logical structure arises from the digitwise definition of a single error, as discussed in section 3°^-° In the design presented here, the accumulator register of the ORDVAC is replaced by two shifting registers, called the carry register and the accumulator register- In executing the addition of two numbers, the addend and augend digits are sensed to produce carry digits in the carry register; results of a digitwise half -adder transformation upon the addend and augend digits are placed in the accumulator register. A sequence of carry assimilation transformations, in which contents of the accumulator and carry registers are sensed, is then executed until all digits of the carry register are zero. The correct sum then appears in the accumulator. This process, with examples is described in section 3° 5° The use of a separate register for carry digits has a number of advantages. In contrast to ORDVAC -type addition circuits in which time must be allowed for propagation of carries over the full length of the register; the addition time, or more properly, carry assimilation time, is a function of the particular digits of the addend and augend. Also, in executing sequences of addition, only one carry assimilation transfor- mation is necessary between successive incorporations of addends into the accumulator and carry registers. Circuits for executing a series of additions and a proof that only one carry assimilation transformation per addend is necessary are presented in section 3=6. -67- Multiplication is programmed as a sequence of additions; it is not necessary to assimilate carries completely at each step. Circuitry and an example of a positive multiplication are presented in section 3«7< In the programming of non-restoring division, it is necessary to sense the sign digit of the accumulator register at each step; the assimilation of carries must be complete before such sensing can occur. The division process is discussed in section 3'8« An integrated arithmetic unit design must provide facilities for addition and subtraction, and for programming multiplication and divi- sion as simply as possible . A logical diagram, showing necessary half- adders and carry generation circuits and showing the required memory- accumulator-carry register interconnections, is presented in section 3 '9* Section 3-2 Representation of numbers In the arithmetic unit of the ORDVAC and Institute for Advanced Study computers forty binary digits are dealt with in parallel. The left- most digit is the sign digit; the remaining thirty-nine digits represent the number itself if the number is positive or the ones complement of the number if the number is negative . Numbers used in computation lie in the range from -1 to +1, -1 being included in the range, +1 excluded. Examples + | 0.101 - ^ 1.101 + i 0.011 - i 1.011 ■68- It is essential to distinguish quite carefully in the case of negative numbers between the number itself and the machine representation of the number. A negative number x is represented in the machine as 2 + x if the sign digit is included. It is clear that a shift to the left of one place is equivalent to a multiplication by two if the range of the machine is not exceeded. Thus, 0.011 shifted left is 0.11; equivalent ly, 2 x 2- 3 d X 8 ~ k For an arithmetically correct right shift, the sign digit must be propagated; for example, 1.101 shifted right becomes 1.1101. In the process we have divided by two, for 3 • P 3_ ' 8 ' 2 - " 16 the equivalent of 1.1101. S ection 3-3° General organization of arithmetic unit The arithmetic unit has facilities for storage of the operands and the results of the arithmetic operations as well as circuitry for exe- cuting the transformations necessary to compound the arithmetic operations. The storage facilities of the arithmetic unit include the memory register, the accumulator, and the arithmetic register. As the name suggests, the accumulator is used for accumulating sums and for accumulating partial pro- ducts during a multiplication. The arithmetic register is used for storage ■69- of multiplier and quotient digits- Both the accumulator and arithmetic register are designed so that their contents can he shifted either to the right or to the left. The memory register stores the operands read from the memory, namely, the augend, subtrahend, multiplicand, and the divisor in the respective operations » In the Institute for Advanced Study and University of Illinois machines, specific orders are included for the fundamental arithmetic operations of addition, subtraction, multiplication, and division. In addition and subtraction, the augend or minuend is in the accumulator, the addend or subtrahend is held by the memory register, and the sum or difference is placed in the accumulator . Provision is made for clearing the accumulator to zero before the operation; that is, setting the addend or minuend equal to zero. Provision is also made for taking the absolute value of the addend or subtrahend. For multiplication, the multiplier is placed in the arithmetic register, the multiplicand is stored in the memory register, and the most significant digits of the product are placed in the accumulator. The least significant digits of the product appear in the arithmetic register. In division, the dividend is in the accumulator, the divisor is stored in the memory register, and the quotient is placed in the arithmetic register. Sectio n 3-^- Effect of single error definitions on arithmetic unit design The digitwise definition of a single error of the error detecting and error correcting codes of Hamming has important consequences affecting arithmetic unit design. There are two possible definitions of a single -70- error in a binary number; the first is an arithmetic definition in which the number in error differs arithmetically by one unit from the correct number. The change from 1001 to 0111 would be a single error by the amount 0010 under the arithmetic definition. The second, or digitwise, definition of a single error involves having only a single digit different between the correct and incorrect numbers. The distinction lies in the method of comparison of correct and incorrect numbers; either the binary representation of the arithmetic difference or of the digitwise sum, modulo 2, has a single one. Under the digitwise definition of a single error, it becomes quite important, particularly for systems with protection against only single or double errors, to design circuitry in such a way that the digits are independently determined. Otherwise, a malfunction in a single ele- mentary circuit sensed to determine two (or more) digits will produce two (or more) errors. Digitwise independence is not maintained in conventional parallel adder circuitry in which carries are propagated. A single mal- function in the carry circuitry can produce errors--in the digitwise sense-- in all digits through which the carry would otherwise propagate. Adders with propagating carries in which digitwise independence is maintained can be constructed, but are so expensive in terms of circuitry that they are not practical- Fortunately, addition can be programmed with the logically simpler half -adder and logical multiplier (or digitwise "and") transfor- mations. Use of these transformations requires that the accumulator shift- ing register of a conventional arithmetic unit be replaced by two shifting -71- registers, which we call the carry register and the accumulator register. Circuits and examples of arithmetic operations are discussed in the fol- lowing sections. One objection has "been raised to the use of the Hamming codes for protection against error during arithmetic operations. The objection is that protection against error is provided equally for all digits, whereas the effect of an error upon the computation is more serious if the error occurs in one of the more significant digits. The objection is valid only if numerical data exclusively is operated upon within the arithmetic unit; we shall see in Chapter V that orders controlling the course of the computation are often treated as numerical data and modi- fied in some fashion within the arithmetic unit. For orders, it is essential that all digits be correct; errors in digits which are not sig- nificant arithmetically can seriously affect the computation. It should perhaps be emphasized that the arithmetic unit design presented here is a logical consequence of the digitwise definition of error and is applicable to any error protection system which is based upon the digitwise concept of error. The arithmetic unit also has several advan- tages which make it worthy of consideration for use in parallel binary digital computers not employing error protection. Section 3- 5 Addition, subtraction, and carry assimilation The basic transformations used for programming addition are the half -adder transformation, logical multiplication, and the left shift. In -72- these transformations, each digit is treated in the same manner. We therefore describe these transformations in terms of the ith digit, (i = 0,1, ••, 39) For the half -adder transformation two binary digits x., y. are sensed to yield a third digit z., such that z. = x. + y. = x.y! ^ x!y. l l l 11 11 in logical design notation. The half -adder transformation is a digit - wise addition modulo two. For the logical multiplier or digitwise "and" transformation two digits x. and y. are sensed to yield a digit w., such that w. = x.y. i 11 The left shift, which here corresponds to assigning double weight to the carry digit, may be represented as u. n = w. l-l l so that u. , = x.y. l-l li Note that the digits u and z. form the addition table for the digits x. and y. . (Table 3.1) TABLE 3.1. ADDITION TABLE FOR TWO BINARY DIGITS X. 1 y. 1 Vi z. 1 1 1 1 1 1 1 1 •73- For compounding arithmetic operations, the transformations of the half-adder and logical multiplier are applied to specific ways to digits in the memory, accumulator, and carry registers to yield trans- formed digits which are stored in the accumulator and carry registers „ We use the following notation: M - memory register, comprising forty flipflops m - ith digit of memory register i = 0,1, ..., 39 A,A - upper and lower 40-digit registers of the accumulator register a, a - ith digits of A and A respectively C,C - upper and lower 40-digit registers of the carry register c,c - ith digits of C and C, respectively R,R - upper and lower 40-digit registers of the arithmetic register r,r - ith digits of R and R, respectively Addition, in the conventional sense, is executed in two parts; the first we call the addition sequence, the second consists of one or more carry assimilation sequences. The addition sequence consists of the fol- lowing transformations: 1) a. = a. + m. l —li 2) c. .. = a.m. c„„ = 1-1 -i l 39 3) a. = a. + c. h) %-l = Yi % = ° The carry assimilation sequence consists of the following transformations: ■7k- l) a..- = a. + c . 1 —l—i 2) c. t = a.c. n „ = l-l -i-i 39 3) a. = a. + c . —i 11 4) c. , = a.c. c_„ = -i-i -i-i -39 A conventional addition consists of one addition sequence followed "by a variable number of carry assimilation sequences; the addition is complete when all digits of C are zeros, that is, when all carries have been assimilated into the accumulator register A. A numerical example of the addition process with carry assimilation is given in Fig. 3»1« Circuitry required for the addition and carry assimilation sequences is shown in Figs. 3-2 and 3-3- The addition sequence consists of the incorporation of the information in the memory register into the accumulator and carry registers followed by what might be called the propagation of the carry through one digit. The carry assimilation sequence effects the propagation of the carry through two digits . If the addend and augend are random, the average (3) longest carry propagation is 4.62 digits, which corresponds to the addi- tion sequence followed by two carry assimilation sequences. A carry prop- agation over forty digits would require twenty carry assimilation sequences. Subtraction requires a complement gate which generates the digitwise complement of the number held in M. Circuitry required for digit- wise complementation is shown in Fig. 3-k. Also required is the insertion of a one in the least significant (39th) digit. This insertion is made into the carry register digit c . The subtraction sequence is thus: ■75- 00101000111 M 00100111101 A 00001111010 A 01001110000 A 00000000000 c 01000001010 c 00000010100 c 0.236k + 0.2^ = 0.5020 (octal) 01001100100 A 01001000100 A 01000000100 A 01010000100 A 00000100000 c 00001000000 c 00010000000 c 00000000000 c 11010111001 M 00101000110 M' 00100111101 A 00001111011 A 01001110010 A 00000000000 c 01000001001 c 00000010010 c 0.2364 - (-0. 2^3*0 = 0.5020 01001100000 A 01001000100 A 01000000100 A 01010000100 A 00000100100 c 00001000000 c 00010000000 c 00000000000 c FIGDEE 3.1- ADDITION AND SUBTRACTION WITH CARRY ASSIMILATION ■77- 4 ■ o _> 4 d' d» ■+ 0' W5 cd— 01 cji —I 2 (fe— u z a) Or Lil 50 2 J en < 8 2 h D O o CO* O -79- 1) a. = a. + m! 1 —11 2) c. , = a.m' c__ = 1 i-l -i i 39 3) fij = a. + c.. k) c. , = a.c. c„ n = -i-l ii ~39 A numerical example of a complete subtraction with carry assimilation is shown in Figure 3-1' Section 3 6> Series of additions and subtractions A major advantage of the arithmetic unit described here is that a series of additions or subtractions does not require complete assimilation of carries between incorporation of successive addends into the registers A and C. The addition (or subtraction) sequence, with a slight modification, is sufficient for the incorporation of a single addend. The modified sequences are, for additions 1) a. - a. + m. l —ii 2) c. .. = a.m. ^ c. c,_ = i-l -i i -i 39 % = 3) a. = a. + c . —i ii *0 c . -, = a.c . —i-l l l and for subtraction: 1) a. = a. + m! i —l l 2) c.,=a.m;^c. n c _ _ = 1 i-l -i l -i-l 39 3) a. = a. + c. —i ii *0 c. , = a . c . c._ = —i-l ii —39 ■80- We shall show that in the transformation 2), the terms £. and a.m. (or a.m! ) cannot simultaneously be 1. It suffices to show that —li—ii' c_ and a. cannot simultaneously be 1. On the previous set of trans- formations 3) and h) , a. and c were determined by the relationships: a. = a. + c . —i li c . ., = a.c. —l-l l l If a. =1 and c. = 1 so that c. .. = 1, then a. = 0. On the other hand, if i i —l-l —i a. + c. = 1 = a., then c. , =0. Therefore the terms c. , and a.m. (or 11 — l —i-l —l-l —i l a.m!) cannot simultaneously be 1, and there can be no conflict between —ii digits in the carry register and digits introduced by incorporation of memory register information into the carry register. Thus, a series of additions can be reduced to a series of addition sequences followed by the necessary number of carry assimilation sequences. Indeed, it is unncessary to assimilate carries at all during many sequences of arithmetic operations. Carry assimilation is required only under two conditions : 1) The sign digit of the accumulator a is to be sensed. 2) The number is to be transferred from the accumulator to some other part of the machine, e.g., the memory. A numerical example of a series of additions and subtractions is given in Fig. 3.5. Section 3°7 Positive multiplication Multiplication of positive numbers can be reduced to a series of additions. The multiplicand is stored in the memory register; the multiplier ■ 81- 01100011011 M 10011100100 M' 00111100001 M 01000010110 M 00001000001 M 11110111110 M' 01000111101 M 00100010111 A 10111110011 A 10111111010 A 10000011011 A 11111011001 A 10111001111 A 00111101011 A 11001010101 A 10100001000 A 11100110101 A 01110001111 A 00000000000 c 00000001001 c 00000000010 c 01111000010 c 00000000100 c 10000100100 c 00000001000 c 01101011101 c 10010101010 c 10010111010 c 00001100000 c 01111101111 A 01111101111 A 00000000000 c 00000000000 c 0.2134 - 0.6154 = -0.4-020 -0.4020 + 0,3604 = -0.0214 -0.0214 + 0.4130 = 0.3714 0.3714 - 0.0404 = 0.3310 0.3310 + 0.4364 = 0.7674 FIGURE 3.5o SERIES OF ADDITIONS AND SUBTFACTIONS ■82- is initially stored in the arithmetic register. At each step of the multiplication process, the least significant digit of the arithmetic register r is sensed. If r = 1, the addition sequence with right shift is executed. If r_ Q = 0, the carry assimilation sequence with right shift is executed. A right shift is executed in the arithmetic register in either case, "bringing the next multiplier digit into r . The exact sequences are as follows : % = 1 i) = a. + m. —i l 2) c . , = a.m. v c. , l-l —ii —1-1 3) a. , = a. '.+ c. 1 —l+l i i V = a.c . l i e 39 = a — o a 39 "* L i % = ° l) = a. + c . —1 — 1 2) c. _ = a.c. l-l —l—i 3) a. n = a. + c . ' -i+I i i h) c . = a.c . —i ii = 39 = ° a = — o a 39 " £ 1 Circuitry required for one step of the multiplication process with r = 1 is shown in Fig, 3°6. A numerical example of the positive multiplication process for an eleven-digit register is given in Fig. 3-7. Section 3°8 Division Division is considerably more difficult to program than multiplication. In the arithmetic unit described here, it is necessary to use non-restoring (3) division. At each step of the division process, sensing of the sign digit a of the accumulator is required; it is thus necessary to assimilate carries at each step. 00101100111 M -8k- 00000000000 A 00101100111 A 00010110011 A 00010110011 A 00001011001 A 00100111110 A 00011011110 A 00110111001 A 00010011011 A 00111111100 A 00010111001 A 00111011110 A 00010001000 A 00001000110 A 00010101011 A 00010101011 A 00001010101 A 00100110010 A 00011011100 A 00110111011 A 00010011000 A 00000000000 c 00000000000 c 00000000000 c 00000000000 c 00000000000 c 00010000010 c 00000000010 c 00010001110 c 00010001000 c 00010001110 c 00010001100 c 00011001110 c 00011001110 c 00100010000 c 00000000000 c 00000000000 c 00000000000 c 00010001010 c 00000000010 c 00010001010 c 00010001010 c 01100111101 R 01110011110 R 01111001111 R 00111100111 R 01011110011 R 00101111001 R 00010111100 R 00001011110 R 01000101111 R 00100010111 R 01010001011 R After Carry Assimilation 00100100010 A 00000000000 c 01010001011 R (0.263k) (0.636k) = 0.22121+26 (octal) FIGURE 3-7. POSITIVE MULTIPLICATION ■85- -'7) The ORDVAC ■ ■ employs the restoring division process., Restoring division can be used in a computer of this type since both the partial remainder and the difference between the partial remainder and the divisor are simultaneously available, the former being stored in the accumulator and the latter appearing as output signals from the adding circuitry. In the design proposed here, a difference must be formed through a subtraction sequence and several carry assimilation sequences; the partial remainder is destroyed in the process. Restoring division is therefore not feasible for our proposed design, For each of the thirty-nine steps of a non-restoring division process, either an addition or subtraction sequence is required, followed by a variable number of carry assimilation sequences, and concluded by a carry assimilation sequence with a left shift. At the conclusion of one step of the division, the following decisions must be made in the order listed: 1) When all digits of the carry register are zero, shift the the contents of the accumulator to the left, storing the sign digit of the unshifted number. 2) On the basis of the stored sign digit, determine a quotient digit and insert it into the least significant digit r of the arithmetic register when the contents of the arithmetic register are shifted left . If forty-digit transformations are executed sequentially, and if sensing of carry register digits is based upon the digits in C, the fol- lowing sequence could be used: -86- l} c i-l = *±Z± c 39 = ° 2) a. = a. + c . 1 —1 —1 3) %_! = a.c. c^ = If all c. = 0. then —1 h) a. = a. + c. a 0r , = -l-l 1 1 -39 5) r. = r. 1 —1 6) r. _ = r. r- = q. -i-l 1 -39 J where q. is the quotient digit based on the sensing of a . J -o The non-restoring division is terminated by a correction and round-off process; the correction involves changing the sign digit of the quotient and the round-off requires insertion of a 1 in the least signif- icant digit of the quotient. A numerical example of a non-restoring division is given in Fig. 3-8« Circuitry for a carry assimilation sequence with a left shift in the accumulator is shown in Fig. 3«9- There is no necessity for left shifting facilities in the carry register for the division process, since all digits are zero when the left shift is to be executed. Section 3-9 Conclusions For a complete arithmetic unit, the various circuits required for the arithmetic operations discussed must be synthesized, as shown in Fig. 3-10* For comparison purposes, a logical equivalent of the ORDVAC- type arithmetic unit is presented in Fig. 3-H- ■ -87- 0011011 M 0001001 0001001 A A 0000000 c 0000000 R 1100100 M 0010010 A 0000000 c 000001- R 1110110 A 0000001 c 1 1101110 A 0000000 c 000010- R fcs ■ °- 25 1110101 A 0010100 c (octal) 1100001 A 0101000 c 1001001 A 1000000 c 0010010 A 0000000 c 000101- R 1110110 A 0000001 n 1 1101110 A 0000000 c 001010- p. 1110101 A 0010100 c 1100001 A 0101000 c 1001001 A 1000000 c 0010010 A 0000000 c 010101- R 1110110 A 0000001 c 1 1101110 A 0000000 c 101010- R Corrected Quotient 0010101 R FIGURE 3„8„ NON-RESTORING DIVISION 1 -89- >- h o 2 y E i < u. u) I- > I Q 52 -91- Not shown in either F ig. 3°10 or 3°U is the arithmetic register. The arithmetic register is a simple shifting register capable of three transfers i 1) R 2) R 3) R R; i.e., r. = r. l—i R; with left shift; i.e., r. ., = r. — —l-l l R with right shift; i.e., r r — o i+1 i r o % = 4 j -1 ' a 39 Inasmuch as multiplication and division are compounded of 39 similar steps, a device for counting to 39 must be provided „ The shift counter, as this device is cllled in the ORDVAC, presents unique prob- lems when error correction must be considered, and will be discussed in Chapter IV - It is necessary to provide for clearing all digits of the A and C registers to zeros as an optional preliminary to the addition and multi- plication orders. In particular, we wish to note for future reference that the following fundamental transformations are necessary for the compounding of orders in the arithmetic unit discussed: Transfers Left shifts and right shifts Clearing all digits to zeros Half -adder transformation Logical multiplier transformation Complementation Modification of a single digit CHAPTER IV GENERATION OF REDUNDANT DIGITS FOR ARITHMETIC UNIT TRANSFORMATIONS Section 4.1 Introduction For each of the arithmetic transformations listed in Chapter III, it is necessary to generate redundant digits. Using the matrix notation developed in section 2>k, we initially have a set of useful digits X and a set of redundant digits X related by the coding equation X = B X r u where B is the coding matrix. An equivalent expression is ox t = o where C is the checking matrix, X represents the set of useful and redundant digits, and is a lxn matrix with all entries zero. In many cases we wish to effect a transformation T upon the X to yield transformed digits Z . The redundant digits Z must also be gen- erated, generally by a transformation T on the X , in such a way that the checking equation is satisfied; i.e., cz t = o The process is indicated in block diagram form in Fig. K.l. In some cases, notably the half -adder and logical multiplier transformations, two sets of useful digits X and Y are sensed for generation of the u u transformed digits Z . In these cases, the Z are generated by a trans - u r * i formation T upon the X and Y as illustrated in Fig. 4.2. . -92- -93- 1 \ rcxu) T*(X t ) i . C£ t*° F/6. 4.1 ~ GENERAT/ON OF REDUNDANT DIGITS FOR TRANSFORM- ATfONT.(ONE RE6/STBQ SENSED.) T(X Ut Y u ) T*(Kt>V ill *r F/64.2, ~ GENERATION OF REDUNDANT DI6ITS FOR TRANSFORM AT/ON T. (TWO REG tSTB OS SENSBO) ■9k- In this chapter we find a transformation T for each of the transformations T necessary for compounding the arithmetic operations. Our criteria for a best transformation T , in order of precedence, are: 1) Maximum protection against error should "be provided. A single error in the x. or y. should preferably affect only a single digit of the z., this producing a correctable error. It is permissible for a single error in the x. or y. to produce a detectable error in the z.. Double errors, and in many cases an integral multiple of two errors, in the z. are detectable. Undetectable, non-correctable errors 1 7 should be avoided. (Use of the single-error correcting, double-error detecting code is implied by this criterion. ) 2) The amount of circuitry should be minimized. In the mathematical discussion to follow, individual arithmetic digits before transformation will be designated as x. or y. and digits after transformation by z . , the subscripts denoting the address of the binary digit under consideration. The corresponding column matrices we have designated as X , Y , and Z . It is convenient to use two sets of u u u addresses for the same arithmetic digits. To each digit is assigned an arithmetic address indicative of the arithmetic value associated with the digit. For example, the arithmetic address of the sign digit is 0, that of the least significant digit is 39* For the correction code, a second set of addresses is needed. These addresses will be called the coding addresses, which will be assigned to the same digits. These coding addresses for convenience will be represented by a set of octal numbers ■95- selected from all two-digit octal numbers from 01 to 77; inclusive. Of course the octal numbers 01, 02, Ok, 10, 20, kO are reserved for the cod.ing addresses of the associated redundant digits, the remaining 57 octal numbers being available for assignment as coding addresses for the arithmetic digits. The designer is free to select from these 57 octal numbers the subset of coding addresses needed for the arithmetic digits and he is also free to select any particular permutation of this set of coding addresses. The factors affecting these two selections arise in connection with the generation of redundant digits for the right and left shift transformation. These transformations are there- fore discussed first in section 4.2. The remaining transformations are discussed in the sections following. The process of clearing a register to zeros or to ones is discussed in section 4.3° The half -adder and logical multiplier trans- formations are discussed in section 4.4. Complementation is discussed in section 4.5. It is also necessary to modify single digits during the execution of an arithmetic operation; for example, the least signif- icant digits of a product are inserted singly into the arithmetic register during a multiplication. Single digit modification is discussed in section k.6„ Finally, a shift counter design satisfying our design criteria is described in section 4«7» -96- Section k.2 Right and left shifts It is convenient for the mathematical formulation of the shift problem that the number of coding addresses selected for the arithmetic digits should be a multiple of the number of redundant digits; for this reason it will be assumed that there are 42 arithmetic digits. It is also convenient to consider only end-around shifts; that is, the last digit of the group of digits under consideration is shifted into the first digit of the transformed group for right shifts, and vice versa for left shifts. The method of attack on the shift problem is as follows : the set of k2 coding addresses will first be broken down into seven groups of six. It will then be shown that if end-around shifts are performed within each group of six, that under certain conditions which shall be determined, the generated redundant digits can be derived from the original redundant digits alone. The conditions are such that the selection of the first address of the group of six determines the remaining addresses of the group. The final step in the attack involves the formulation of the end-around shift of the set of forty-two arithmetic numbers in terms of the group- wise end-around shifts of six numbers. Considerations arising from this formulation are a guide in the selection of the first addresses of the seven groups, and a best (in terms of the criteria above) selection and permutation of coding addresses can be made. For the mathematical formulation, matrices B, X , and X are > ' u r defined as in Chapter II with m = k2 and n = 6, recalling that no particular -97- pe mutation is as yet specified for the k-2 columns of B and the corresponding k-2 rows of X . X and X represent the original arithmetic and redundant u u r digits, the digits as transformed by the shift being represented by Y and Y o Matrices L and R must also be defined. These matrices represent r n n end-around left and right shifts of sets of n arithmetic digits . L is the n nxm matrix obtained by permuting the rows of the nxn identity matrix, the ith row being permuted into the (i+l)st row for i = 1,2, ..., n-1, with the nth row being permuted into the first row. R is similarly defined, with the (i + l)st row being permuted into the ith row, the first row being permuted into the nth row. It follows that R" 1 = L L" 1 - R n n n n The particular values of n of interest in this discussion are 6 and k-2. Examples of R/-, L/-, Rk p > and L, are illustrated in Figs. 4-3 and k.k. The original condition of the X is given by the coding equation X = BX . Ultimately the same conditions must hold for the Y. . That is r u t Y - B Y r u Next consider B to be composed of seven blocks of 6 x 6 entries each; similarly the X and the Y are broken up into seven blocks of 6 x 1 u u entries. These blocks are designated as -.B^-, ^B^, ..., „B^. and _,X , 16 2 6 7 o 1 u -X ..... _X , -Y , _Y , . ..,„Y respectively. Thus the coding equation 2 u Tu 1 u 2 u 7 u can be written as X = n B. X + ... + _B^ JC l>. rl62u 7ofu ■98- R^ = = 1 10 10 10 10 10 L^ = 1^ = '0 1 ; 1 1 1 1 1 1 1 1 1 1 1 1 = 1 1 = 10 5 = 10 10 10 10 ' 1 5 = 10 10 10 10 1 FIGURE k.3. . 6 x 6 MATRICES FOR SgMT JFQRMULATIOW -99- R 1 R 1 L L R R L L R R L L \ 2 - R R \2 = L L R R L L R R n L ,L p 1 R 5 R L L R^ 1 L^ Rg Lg R^ L^ 7 R 6 = Rg 7 L 6 = L/- R^ Lg Rg L^ R 6 o w o | D = r R 1 R 1 R 1 R °1 R R ± R ± R D l = R R R R R 1 R L L L L L L L L L L L L L L FIGURE Ik Ik 42 x 42 MATRICES USED IN SHIFT FORMULATION All Entries are 6x6 Blocks of the Type Illustrated in the Preceding Figure, -100- Similarly, the coding equation for the Y can he rewritten as Y = ,B,- _Y + _B. _Y + ... + _B. Y (4.2' rlolu262u 7 o 7 u ' It should he re -emphasized that in all these matrix operations any one column of a B matrix when read from the hottom up yields the address of the digit in the corresponding row of the X or Y . u u Suppose that the .Y are generated from the .X by an end-around J u j u right shift . That is , n Y =R, n X Y = R. X ... ^Y c = IV JC (4.3) lu 6 1 u 2u 62u 7b 6 7u v -" Substitution in (4.2) yields Y r " 1 B 6 R 6 l X u + 2 B 6 R 6 2 X u + • • • + 7 B 6 R 6 A (k.k) If a set of redundant digits Y' is generated from the X by an end -around r r right shift, then Y' = IV X r or Substituting for X from (4.1) yields Y = IV n B^ n X + R^.^B^. X '+ ... + IV n^r V X /j. c-\ r blfalu 626 2u 6 7o Y u (^OJ Comparison of equations (4.4) and (4.5) indicates that Y r = Y r if j B 6 R 6 = R 6 j B 6 f ° r eVery J = 1 ' 2 ' "■•' T - Since L r = R^ 1 ; it follows that Y = Y 1 if bo r r B^ = R^ .B c L^- = W .B, IV for each j (4.6) j 6 6j66 bjbb The same condition for equivalence of Y and Y 1 is obtained if groupwise end- around left shifts are considered. -101- A matrix .B/- is of the form J o b ll b 12 b 21 b 22 J l6 '26 b 6i b 62 •*■ b 66 where the "b., = or 1. lk It can he shown that the condition {h.6) is equivalent to the conditions b ll = b 22 = b 33 = V = b 55 = ^66 b_„ = b b. = h ^ = b, 12 _ u 23 " 3^ ~ ^5 " 56 " u 6l h , = h _ = b 13 " 24 - u 35 " ^6 - u 5l ~ %2 \k = b 2 5 = b 36 = \i = b 52 = b 6 3 b l 5 = b 26 = b 3 l = \2 = b 53 = h 6h h r = h , = b_ = h 16 - u 2l - u 32 - U V3 " ^ " u 65 Therefore, for condition (ho6) to be satisfied, each matrix .B/- is of the form b ll b i2 b i 3 \h b i 5 b l6 b i6 b n b i2 b i 3 \h b i 5 b l5 b l6 b il b i2 b i 3 \h \k b i 5 b l6 b ll b l2 b i 3 b l3 \h b i 5 b l6 b n b i2 b l2 b i 3 \h b i 5 b l6 b n -102- If each column of .B/- is viewed as a six-digit binary number, each set of six binary numbers corresponding to the columns of a matrix .B^ forms a J o permutation group, the permutation being an end-around left shift. The first element of the permutation group is sufficient to define the group. The permutation groups of the set of six digits binary numbers are listed below. For brevity, two octal digits are used for each six-binary- digit number Six zeros 00 Five zeros 01 02 04 10 20 40 Four zeros 03 06 14 30 60 4l 05 12 24 50 21 42 11 22 44 Three zeros 07 l6 34 70 6l 43 13 26 54 31 62 45 15 32 64 51 23 46 25 52 Two zeros 17 36 74 71 63 47 27 56 35 72 65 53 33 66 55 One zero 37 l6 75 73 67 57 No zeros 77 There are a total of nine permutation groups having six elements. Of these, the five- zero group is reserved for the redundant digits. Con- siderations governing the selection of the seven permutation groups for the forty-two addresses of the useful digits and governing the selection of first members for these seven groups are yet to be determined. At this point the following has been proved. If the useful digits X are selected and permuted in such a way that they form seven permutation groups of six elements each, and if furthermore the useful digits Y and the redundant digits Y are obtained from X and X by end-around shifts r u r (right or left) of the groups of six, then y = e y u The end-around right shift has been formulate-! in terms of 6 x 6 blocks as follows : .Y = F.£ .X 3 = 1, 2, ..., 7 (M) It is convenient to define a matrix „Ra in the following way, R/- is a 42 x 42 matrix composed of a 7 x 7 array of blocks, each block consisting of a 6 x 6 array of entries. Along the main diagonal of blocks are 6x6 arrays of entries of the form R--. Each of the remaining 6x6 blocks is composed of zeros. The matrix Bs is exhibited in Fig. 4,4,, The equation (4-. 3) can now be written as Y = R. X (4.7) u 7 o u Also, Y = R, X . The Y and X are derived from the Y and X by the rcr rr u u coding equation Y = B Y X = B X r r u From these relations, the following identity is obtained: Rz- X = Y -BY - B „R, X (4.8a) o r r u I b • For the Left shift, a similar- Identity holds: h c X = B l.v- X (4.8b) 6 r 7 o u The definition of LV is analogous to that of 7 Ra° (See Fig. 4.4.) The i Lght and left shift transformations considered for arithmetii O] ra1 ions have been shifts of the set of all digits; therefore it is nec- essary now to consider end-around shifl of 42 digits The shifted digits y" are determined by u ir" ■■ \ 2 \ (*-9) -104- In order to relate R. to Rg, the right deviation matrix D is defined as D r " \2 + 7 R 6 Since entries in all matrices are from the field of integers modulo 2, it follows that E te ■ 7 R 6 + D r Substitution in equation (4.9) yields Y" = (^ + D)X = „R,; X +D X u | d ru 7°u ru The redundant digits Y" are obtained by use of the coding equation Y" = B Y" = B -R c X + B D X r u 7 o u r u By the identity (4.8a) r o r r u Similarly, for the left shift Y" == Rg X^. + B D^ X, (4.10a) Y" = W X + B D n X (4.10b) r o r 1 u The relations (4.10) indicate that the redundant digits Y" associated with the shifted useful digits Y are found by correspondingly shifting the redundant digits X with some additional sensing of the X . r u For sensing of the X to be minimized, the number of non-zero entries in u the matrix products B D and B D n must be minimized. This minimization is r 1 accomplished by a suitable selection of the arrangement of the seven per- mutation groups and by selection of the first numbers of these groups. The nature of the matrix product B D is indicated by the equations of Fig. 4.5. B and D are first broken into 6x6 blocks to yield a pro- duct B D with blocks of the form r ( .Ba + . n B^) n R v j 6 j+1 6 ; 1 -105- B D r = lli B 6 2 B 6 3 B 6 A A 6 B 6 lV R R R R R R R R R R R R R R = il i R <2 B 6 + 3 B 6 } 1 R ( 3 B 6 + AA R '" <6 B 6 + 7*6 >i R ( ? B 6 + A)i R H j p l J P 6 / 5 * * • A j+A j+A j+A • • j+A j P 2 j p i /6 • • • A j+A j+A j+A • * j+A • B £ = J o J P 3 J P 2 A • • • A j+A " j+A j+A j+A • • j+A A A A •• • A A = ( j+A j+A j+A • 3,1 • j+A v j 6 j+1 6'1 00000 A + J+ A 00000 /2 + j + l P 2 ooooo . P3+ . +1 p 3 ooooo jV j+1 3 u ooooo .p tr +. -,p c j 5 J+l 5 o o .p,+ . ,p. FIGURE +.5. MATRICES FOR SELECTION OF PERMUTATION GROUP FIRST NUMBERS ■106- Entrywise operations then indicate that the columns in the jth block of B D consist of zeros, except for the sixth and last column. This last column corresponds to the digitwise sum (modulo two) of the first numbers of the jth and (j+l)th permutation groups. The first numbers of adjacent groups are therefore selected so that they differ by only one digit. These numbers, in the order of the groups, are as follows: 1 P 6 1 P 5 A 1 P 3 1 3 2 A = 000011 = 03 (octal) 2 P 6 2 P 5 ... 2 P 1 = 000111 = 07 (octal) 3% 7 P 6 3 P 1 = 001111 = 17 (octal) k?± = 001011 = 13 (octal) 5 P 1 = 101011 = 53 (octal) 6 P 1 = 101001 = 51 (octal) 7 P 1 = 101000 = 50 (octal) The criterion for minimization of non-zero entries of B D is the same. For the product B D , 6x6 blocks of the form ( . n B A + .BjL \i-l 6 .id'. 1 are obtained. All columns of these blocks consist entirely of zeros except the first. This first column corresponds to the digitwise sum (modulo two) of the last numbers of the permutation groups. The selection of the permutation groups and their first numbers completely specifies the coding addresses of the useful digits. In Table 4.1, the coding addresses corresponding to the arithmetic addresses are listed. This particular selection of addresses will be used in all subsequent designs and calculations. -107- TABLE 4.1. ARITHMETIC AND CODING ADDRESSES Arithmetic Address Coding Address (Decimal) (Octal) (Binary) - 03 000011 06 000110 1 14 001100 2 30 011000 3 60 110000 h 41 100001 5 07 000111 6 16 001110 7 3^ 011100 8 70 111000 9 61 110001 10 ^3 100011 n 17 001111 12 36 011110 13 74 111100 ll+ 71 111001 15 63 110011 16 hi loom 17 13 001011 18 26 010110 19 54 101100 Arithmetic Address Coding Address (Decimal) (Octal) (Binary) 20 31 011001 21 62 110010 22 h5 100101 23 53 101011 24 27 010111 25 56 101110 26 35 011101 27 72 111010 28 65 110101 29 51 101001 30 23 010011 31 46 100110 32 15 001101 33 32 011010 3^ 64 110100 35 50 101000 36 21 010001 37 42 100010 38 05 000101 39 12 001010 _ 24 010100 -108- One further calculation is necessary to complete the discussion of the shift transformations, namely, the calculation of the redundant digits indicated by equations (4.10). The digitwise equations corresponding to equations (4.10) are as follows for the right shift: y i = x 4o + x 64 + x 2k I y 2 = x i + x 6 5 + x 24 I *k = X 2 + X 4l + X 47 (4.11a) y l0 = x 4 + x 4 3 + x 24 I 7 20 = X 10 y 4o " x 20 + x 45 + x 24 For the left shift *y 1 = x 2 + x + x ^2 = \ + X 7 + X 13 I % = x 10 + x 3 + X 1T (k ° 1Ib] ^10 = X 20 ^20 = X 40 + X 3 + X 53 %0 = x l + x 3 + x 50 The detection digit y can be easily determined for the end- around right shift. We first note that, for the end-around right shift Z y = Z x u u Z V = Z X + X, , + X, „ + Xi. r + X, „ + X^i. + X r r ki T A 43 T "45 T "47 T "64 T "65 where the x , are the redundant digits and the x are the useful digits r u The detection digits x and y are defined as to o o -109- x = Z x +L x our y. = E y u + Z y r = x o + x ki + x h 3 + x 4 5 + X ^T + x 6h + x 6 5 (2Kl2a) The detection digit for the left shift can be similarly determined, with the result % = x o + X T + X 13 + x l7 + x 50 + x 5l + x 53 ( ^ ol2b) The effect of single errors in the x. can he predicted from the equations (4.1l) and (4.12). We note that the digits appearing in equation (4.12a), other than the detection digit x , have addresses which are last numbers of the permutation groups selected. A single error in any of these digits of the x. produces two undetectable non-correctable errors in the transformed digits. For example, if x.,- is in error, the digits y^?, ^Un' and y will be in error. This combination is treated by the correction circuitry as a single error in y n , the end result being two errors in the useful digits y,-_ and y _ and a third compensating error in y^ n ° The same combination of errors results regardless of the selection of first numbers for the permutation groups. Section h„ 3 Clearing all digits to zeros or ones Generation of redundant digits for the clearing transformations is quite simple. For clearing to zeros, the redundant digits are corres- pondingly cleared to zeros. That is B X = B || x || = B || || =0 u u" " " where is a 1x6 matrix with all entries zero. ■110- The associated correction digits needed for checking that all useful digits have been cleared to ones are similarly calculated. B X = B • ||x || = B -Hi ||= || x k|| k = 0, 1, ..., n-1 U ., u i| ; <- The x k depend upon the number of digits sensed in each correction parity- check. For the selection of addresses indicated in Table k.l, an odd number of digits is sensed for each of the six correction parity checks so that each Xpk = 1. Thus, all digits of X are cleared to 1 for this transformation. The detection digit should be cleared to zero for both types of clears, since an even number of identical correction redundant and use- ful digits are involved. Section k.k- The half-adder and logical multiplier transformations The half-adder and logical multiplier transformations are unique in that, for each of these transformations, the contents of two registers are sensed to produce one set of transformed digits. For the half-adder transformation, the correct redundant digits are generated by a half -adder transformation upon the input redundant digits. If the input digits are X and Y with associated redundant digits X and Y , ^ to u u r r' the digits resultant from the transformation are Z = X + Y u u u Z = X + Y r r r The Z are correct since r Z = X +Y =BX +BY = B (X + Y ) = B Z rrr u u uu u The detection digit z is similarly determined. z = x + y o o o -111- Generation of the redundant digits for the logical multiplier transformation is more difficult. Each result digit z is related to u. 1 the corresponding input digits x and y by i i z = x y u. u. 'u. 1 11 (the u. are the coding addresses of the useful digits) or, equivalently x y u. u. l l The corresponding redundant digits z can be generated in the following manner. First generate x ^ y for each of the m useful digits. Next, u. u. l l code the corresponding m signals to form n redundant signals; that is, form B x v y u. u. l l Finally, form Z = X + Y + B r r r x v y u. u. 1 1 (^13) It is to be proved that C Z = The checking process can be represented as CZ -Z + B Z t r u Substitution yields C Z, X + Y + B r r x v y u. u. 1 1 + B x y u. u. i l X + Y + B r r x y u. J u. l i x ^ y u. u. l l X + Y + B r r x y + x s/ y u. u. u. u. li i l (^.l*) -112- For two binary variables, u, w UW + U v W = U + W Therefore CZ, =X+Y+B II x +y |-X+Y+B(X+Y) t r r " u. u. " r r v u u 1 1 = X +Y +BX +BY (4.1S r r u u v y Thus C Z = if no error has occurred. The detection digit may be determined in several ways . Perhaps the best method is to form the sum of the signals x v y for all the i i useful digits, then add the sum of the n signals corresponding to the coding process B | x v y 1 1 , and finally add the detection digits i i x + y . That is o o z + Z (x >• y ) + o +x +y (4.16) o u. u. n o o u. 1 i l Where a is the sum of the n signals corresponding to the n entries of the n matrix product B x v y " u. u. I i We prove equation (k.l6) to be an identity by use of the following: z = Z z + Z z o r. u. l l x = Z x + Z x o r. u. l l y = Z y + Z y l l Zz =Zx +Zy + o from equation (4.13) r. r. r. n ill Zz =Zx y =Z(x vy )+Zx +Zy u. u. u. v u. u. u. u. i 11 11 i i Calculation of the value of z from the last two expressions yields o z =Z(x v y )+Zx +Zy +Zx +Zy +o o u. u. u. u. r. r. n II 1111 = Z(x v y ) + a +x +y u. u. n o o i i -113- It should be noted that a single error in the X^ or Y^ will indeed be ° t t detected . A single error in the X will change one of the x and will u u. 1 change the B X terra of equation (4.15), yielding the correct indication of error in the correction digits. Similarly, a single error in the Y , X , or Y will affect the corresponding term in equation (4.15) and the location of the error will be indicated by the correction digits. The effect of a single error upon the detection redundant digit z is rather complicated to describe exactly; however, the digit z is such as to indicate a single error which can be corrected or will indicate a double error which can be detected. Simultaneous errors in corresponding digits x and y cannot be detected, u. u. l l Section 4.5 Complementation Complementation is essentially a half -adder transformation with the augend the number to be complemented and the addend consisting entirely of ones. The redundant digits corresponding to the useful digits of the augend are also all ones. Since the half -adder transformation applied to augend and addend correction redundant digits yields the correct trans- formed correction redundant digits, the set of correction redundant digits corresponding to complementation is generated by simply complementing these digits. Mathematically, Y = 111 + x II ■ i " u. " l = B • ||l || + B X = i||l + x || k The detection redundant digit should be left unchanged when the remaining digits are complemented. Y = B Y = = B • 1 + x r u 11 u. 1 ■111*- Section k.G Single digit modification In section k.2., the generation of redundant digits for the end- around right and left shift transformations was discussed. Consideration of end-around shifts was purely for mathematical convenience, since in practice the end-around shift is not executed. Generally, during a right shift, the rightmost digit is either lost or transferred to a different register; the leftmost digit is filled from an external source. We can consider a right shift of the type described as an end-around right shift followed by modification of a single useful digit, namely, the leftmost digit. If the leftmost digit is assigned the coding address 03, we must also modify the redundant digits with addresses 02 and 01, in order that the checking equations will he satisfied. To describe this modification process mathematically we use the following notation: x. - digit at coding address i before modification x* - digit at coding address i after modification y - digit inserted from external source during modification process For the example above x* = y x* = x 2 + x + y x* = x 1 + x^ + y If the inserted digit y is incorrect, the checking equations will still be satisfied. Some means of insuring that digits inserted in this way are correct must be adopted. Since digits to be inserted elsewhere from a -115- register are either the sign digit or the least significant digit, these digits have been duplicated with separate coding addresses assigned. Thus, in Table ^.1, the duplicated sign digit occupies both digits at coding addresses 3 and 6j the least significant digit occupies digits at coding addresses 12 and 2^. Such duplication must necessarily occur in all registers of the arithmetic unite Section *+.7» Counter design t„71 General remarks For the cyclic programming of multiplication or division of two m digit numbers, some device having m unique states is necessary so that the cyclic routine can be halted at the end of the desired number of similar steps. What is needed is a device which, after being reset orig- inally, can accept m-1 stimuli and thereupon provide an output stimulus signalling completion of the sequence of m-1 steps. In the ORDVAC, a six-digit binary counter, called the shift counter, is used for programming multiplication and division.. The number held in one of the two registers of the shift counter is increased by one during each step. A counter of this type is not feasible for an error- correcting computer, since the counting process involves addition with carries. Several alternative possibilities suggest themselves: l) An m-digit shifting register can be used. Initially the register is cleared to zeros, with a single one in the least significant digit. The one is shifted left one place during each step. When the one appears in the most significant digit, m-1 steps have been executed. -116- 2) The addition process in a six-digit counter can be programmed, using a six-digit counter accumulator and a six-digit counter carry register. The number of steps required for a counter of this type would vary, depending upon the carry length. 3) It is conceivable that the counting process can be programmed feasibly using two transformations. A method possessing several unique features is described in section 4.72. The generation of redundant digits for this counting method provides an example of a type of problem as yet unsolved for an error-correcting system. The redundant digit generation is described in section 4.73* 4.72 Useful digit transformations for counting Corresponding to a set of n binary digits there are 2 binary numbers. For our design here, we require a device capable of assuming forty states; we therefore set n = 6. The corresponding six flipflops of a counter assume a sequence of states which correspond to a sequence of six binary-digit numbers. In the ORDVAC shift counter, the sequential flipflop states correspond to binary numbers arranged in numerically increasing order. Here we investigate the possibility of using a sequence of binary numbers arranged in such a way that two successive numbers :v> - involve a change in only one binary digit. One such sequence, known as the Gray code, has been in use at the Bell Telephone Laboratories for a number of years. This sequence is listed in Fig. K.6 in the column headed W. Also shown in Fig. 4.6 in column Y is a sequence of numbers, each number having a single 1 indicating the particular digit next to be changed in the -117- w X Y 000000 000000 000001 000001 000001 000010 000011 000010 000001 000010 000011 000100 000110 000100 000001 000111 000101 000010 000101 000110 000001 000100 000111 001000 001100 001000 000001 001101 001001 000010 001111 001010 000001 001110 001011 000100 001010 001100 000001 001011 001101 000010 001001 001110 000001 001000 001111 010000 011000 010000 000001 011001 010001 000010 011011 010010 000001 011010 010011 000100 011110 010100 000001 011111 010101 000010 011101 010110 000001 011100 010111 001000 010100 011000 000001 010101 011001 000010 010111 011010 000001 010110 011011 000100 010010 011100 000001 010011 011101 000010 010001 011110 000001 010000 011111 100000 w X Y 110000 100000 000001 110001 100001 000010 110011 100010 000001 110010 100011 000100 110110 100100 000001 110111 100101 000010 110101 100110 000001 110100 100111 001000 111100 101000 000001 111101 101001 000010 mill 101010 000001 111110 101011 000100 111010 101100 000001 111011 101101 000010 111001 101110 000001 111000 101111 010000 101000 110000 000001 101001 110001 000010 101011 110010 000001 101010 110011 000100 101110 110100 000001 101111 110101 000010 101101 110110 000001 101100 110111 001000 100100 111000 000001 100101 111001 000010 100111 111010 000001 100110 111011 000100 100010 111100 000001 100011 111101 000010 100001 111110 000001 100000 111111 100000 FIGURE 4.6. SEQUENCES OF BINARY NUMBERS FOR COUNTING ■118- corres ponding number of column W. Column X shows the sequence of numbers arranged in numerically increasing order. The location of the 1 in a given number of column Y is also indicative of the length of carry necessary for the change in the number of column X. The w., x., and y. are related as follows: 1 l l x = w,- + w, + w_ + w~ + w., + w w = x + x n o 5 ^ 3 2 1 o ool x 1 = w + w^ + w + w 2 + w w l = x l + x 2 x 2 = w + w^ + w + w 2 w 2 = x 2 + x x 3 = w 5 + ™k + w 3 W 3 = X 3 + X 4 x h = w 5 + w^ w^ = x^ + x 5 x 5 = w 5 . w 5 = x 5 y o = X o j+i y o = j y o y i = X o X i j + i y l = % /o y 2 = X o X l X 2 j+l y 2 = W l W o j y o y 3 = X o X l X 2 X 3 j + i y 3 = "2 W i V o /o y 4 = X o X l X 2 X 3 X i- j + l y * = W 3 W 2 W i W o /o y 5 = x o x l x 2 x 3 x k j + l y 5 = W 3 V 2 v l v o j y l . n w. = .w. + y. for each i (i = 0, . .., 5) j+1 1 J 1 1 The subscript i designates the digits of the binary numbers involved, being the least significant and 5 the most significant digit. -119- The prescripts j and j+1 indicate recursion relationships for generating a number from the previous one. The last two sets of equations from which the x. have been eliminated suggest the following design: two registers, each having two sets of six flipflops each, are employed, We designate the sets of flipflops as W, and W, and Y and Y, with digits w. , w., y . , and y., respectively (i = 0, . .., 5)» The necessary transformations are then: w i = *i y o = K for each i y n = w y 1 — o o Y 2 = % K ^o ^3 = -2 *i ^o ^o ' ,, i ,, > y k = £3 * 2 w 2 W Q y Q Y 5 = w« w« w' w; y Q w. = w. +• y. y. = y. for each i —i 11 —ii Generation of redundant digits and selection of coding addresses for the above transformations are discussed in the next section. 4„73 Redundant digit transformations for counting It should be noted that the number of error correction redundant digits and the number of binary digits required for a shift counter are the same for any given number of paralleled register digits. A consequence of this fact is that each of the 2 numbers formed in sequence by the redundant digits for the W register can be unique. A necessary and sufficient con- dition for uniqueness is that the coding matrix, which here is a 6 x 6 matrix, ■120- has an inverse. When the coding matrix has an inverse, the redundant digit registers (corresponding to the W and Y registers) considered alone form a counter in which the digits assume a series of 2 unique states. The design process is in a sense duplication, but is more powerful than duplication in that the error correction procedures can be applied. The particular coding matrix B selected is the entrywise complement of the 6x6 identity matrix. This matrix has the property that it is its own inverse. The coding addresses of the digits of the W and Y registers are then ^6, 75* 73> 67, 57> and 37 in octal notation; the address of the least significant digit is listed first. For this coding matrix, all detection redundant digits are always zero, if no errors occur. We designate the redundant digit registers associated with W and W as A and A, respectively, with digits 0C. and a.; similarly T and T with digits 7. and 7. correspond to Y and Y, respectively. Here i has the octal values 1, 2, k, ..., kO. The sequences of numbers held in the W, Y, A, and T registers are listed in Fig. ^-7- Contents of the remaining registers are related to those listed by identity transformations. It follows from the properties of the matrix B selected that : llajl = B llwjl llw.l! = B \\a ± \\ II9LJI = B ||w.|| ||w.|| = B Ha.ll ll^ll = B Fill Pill =B H^ll IIZJI = B II4II llxjl -B II4II where i for the w. and the y. has the values 76, 75, 73, 67, 57 and 37- ■121- W W 000000 000001 000000 111110 110000 000001 110000 111110 000001 000010 111110 111101 110001 000010 001110 111101 000011 000001 000011 111110 110011 000001 110011 111110 000010 000100 111101 111011 110010 000100 001101 111011 000110 000001 000110 111110 110110 000001 110110 111110 000111 000010 111000 111101 110111 000010 001000 111101 000101 000001 000101 111110 110101 000001 110101 111110 000100 001000 111011 110111 110100 001000 001011 110111 001100 000001 001100 111110 111100 000001 111100 111110 001101 000010 110010 111101 111101 000010 000010 111101 001111 000001 001111 111110 mill 000001 111111 111110 001110 000100 110001 111011 111110 000100 000001 111011 001010 000001 001010 111110 111010 000001 111010 111110 001011 000010 110100 111101 111011 000010 000100 111101 001001 000001 001001 111110 111001 000001 111001 111110 001000 010000 110111 101111 111000 010000 000111 101111 011000 000001 011000 111110 101000 000001 101000 111110 011001 000010 100110 111101 101001 000010 010110 111101 011011 000001 011011 111110 101011 000001 101011 111110 011010 000100 100101 111011 101010 000100 010101 111011 011110 000001 011110 111110 101110 000001 101110 111110 011111 000010 100000 111101 101111 000010 010000 111101 011101 000001 011101 111110 101101 000001 101101 111110 011100 001000 100011 110111 101100 001000 010011 110111 010100 000001 010100 111110 100100 000001 100100 111110 010101 000010 101010 111101 100101 000010 011010 111101 010111 000001 010111 111110 100111 000001 100111 111110 010110 000100 101001 111011 100110 000100 011001 111011 010010 000001 010010 111110 100010 000001 100010 111110 010011 000010 101100 111101 100011 000010 011100 111101 010001 000001 010001 111.110 100001 000001 100001 111110 010000 100000 101111 011111 100000 100000 011111 011111 FIGURE 4.?. USEFUL AND REDUNDANT DIGITS FOR SHIFT COUNTER -122- The transformations in the redundant digit registers are a. || oB .||w.|| = B '||v.||= ||a. «!» = B • II "j.1 - b • !!«, + y ± \\ =11"! + y % 2,1 =B.|^J -B- y ± =1(7, The matrix B also determines the relationship between the 7 . and the OL. l—i and 7., given the relationship between the y. and the w. and v.. Since — i i — i •H the latter equations cannot be expressed in the form of an nxn matrix, the derivation of the 7 . cannot be made in the same simple way as the other derivations. The derivation of the 7. is essentially based upon an enu- meration of cases for each digit. The 7. can be expressed as follows: \ =2- \ =Z x -a{-22 r io = Z x v «[ v % v -4 The error detection digit should be zero in all cases . We next consider the effect of any single error in the digits of W and Y sensed for the generation of the y. . We consider errors in digits senset in turn. l) An error in y affects y only half of the time for a correctable single error. The remaining times y and a second digit of Y are in error for a detectable double error. -123- 2) An error in w produces no effect half of the time. One-fourth of the time y only is in error and one-fourth of the time y and one other digit are in error. 3) Similarly, the probability that an error in w produces a correctable error is one-eighth; the probability of a detectable error is one-eighth. h) For an error in w , the probabilities of resultant correctable and detectable errors are each one-sixteenth. 5) An error in w produces a detectable error one-sixteenth of the time. The effects of errors in 7, and in the CC. upon the 7. are quite similar to —1 —1 1 those discussed for the corresponding useful digits. The selection of the coding matrix B for the counter design was made on a trial-and-error basis. The relations between digits in the A and V registers can be determined with some difficulty after the matrix B has been selected. Protection against errors within the system and amount of equip- ment required for the system can then be determined. The inverse problem — namely, how does one select a best coding matrix B--has not been solved. k.^k Advantages and disadvantages of counter design As noted in section 4.71, the conventional counting process involves the addition of one, and cannot be used directly. The Gray code counter des- cribed possesses advantages over either of two alternatives which seem appli- cable. The Gray code counter requires less equipment than a shifting register and does not require the special programming of the accumulator-carry register conventional addition counter. -124- Two disadvantages of the counter design discussed are obvious . In the system proposed, effects of some single malfunctions cannot he corrected o The complexity of the system is considerably greater than that of the counters used in computers not employing error protection. Further investigation into the process of coding matrix selection may lead to better protection against error; it may also be possible to reduce both the over-all redundancy and the complexity of the system without reducing the protection against error provided. CHAPTER V CONTROL DESIGN CONSIDERATIONS FOR A GENERAL PURPOSE COMPUTER Section $.1 Introduction A general purpose digital computer is classically subdivided into four functional units; the arithmetic unit, the memory, the input -output mechanisms, and the control. For an error-correcting computer, we visualize that numbers are handled by these units in the following fashion: the orig- inal numerical data is sensed and associated redundant digits determined as a preliminary step in the input process. The coded set of useful and redundant digits is transferred by the input mechanism to the memory. For com- putation, the coded numerical data is transferred from the memory to the arithmetic unit where the sequence of transformations which effect the desired arithmetic operation is executed. The transformed — and still coded- -data may then be transferred back to the memory. One of the features of a general purpose computer is that the orders which the machine is capable of executing are themselves coded numerically and are stored in the memory. We discuss in a general way the representation of orders in section 5-2. In Chapter III we discussed the programming of the specific orders of addition, subtraction, multiplication, and division, i.e., the arithmetic orders. For a general purpose machine several non-arithmetic orders are useful; these orders we discuss in section 5«3« ■125- -126- One major problem remains, namely, the control problem. Functionally the control unit provides the sequence of stimuli which effect execution of the various orders. We discuss here in section 5.4 the general design consid- erations for kinesthetic asynchronous control and in section 5.5 we discuss the detailed design of a control embodying certain features which may be applicable to an error-correcting computer. The problem of generating control stimuli with automatic correction of errors affecting the stimuli is one which has not been solved. Various facets of the problem are discussed in section 5.6. Section 5»2 Representation of orders In order that a computing machine be independent of the human operator after a computation starts, it is necessary that the machine be capable of storing not only the numbers used during the computation, but also the instructions which govern the actual routine of the computation. It is convenient, furthermore, that the instructions be reduced to a numer- ical code in such a way that they can be stored in the same memory with the numerical data. The precision of numbers used in computation in the Institute for Advanced Study and the University of Illinois machines is k-0 binary digits. A memory capacity of 1024 = 2 such k-0 digit words is provided. These machines employ a single address code; that is, a par- ticular order often involves some designation of an operation to be per- formed and the memory address of the number used in the operation. It is evident that ten digits are required to specify the memory address; -127- six more are sufficient to specify the operation desired. Actually, ten digits are assigned to identify the operation, so that a total of twenty binary digits are used for each order. Since a word consists of forty digits, orders are stored in the memory in pairs . It should he remarked that a word selected at random from the memory cannot be positively identified as a number or as a pair of orders. Order pairs are placed at adjacent memory addresses and the control nor- mally consults memory locations in sequence as pairs of orders are exe- cuted. A ten-stage binary counter, called the control counter, is pro- vided for remembering the location of orders. Use of the described technique for handling orders in an error- correcting computer presents a number of difficulties. As discussed thus far, a set of redundant digits is assigned for detection and correction of errors in the set of digits consisting of the redundant digits and a block of forty useful digits. In the handling of orders, it is necessary to sub- divide the blocks of forty digits into smaller blocks of twenty digit orders and finally into the ten digit blocks which specify operations and addresses, Each ten digit block must be accompanied by a set of five redundant digits for checking and correcting purposes. Generation of redundant digits within the machine is not easily accomplished, for an allowable single error in the block of forty digits results in incorrect generation of the set of redundant digits associated with one of the blocks of ten digits. Thus, it is necessary that the redundant digits for the blocks of ten be generated external to the high speed organs of the machine. -128- A second difficulty arises in connection with the control counter. It will he seen that digitwise independence cannot he maintained in counters having a number of stages in excess of the number of error correction digits. The necessity for a control counter can he eliminated by use of a two-address code such that each order specifies the location of the next order to be executed as well as the address of a number and an operation to be performed. A block of forty digits will therefore be subdivided in the following way. Two blocks of fifteen digits each contain addresses and redundant digits for checking and correcting addresses. The ten remaining digits contain information pertaining to the operation to be performed and the associated redundant digits. It should be noted that double redundancy is used for orders, since the block of forty digits used for a single order has associated with it a set of seven more redundant digits. Orders can he treated in the memory and arithmetic unit as numbers; however, in changing addresses, the corresponding change must be made in the associated address redundant digits. Section 5.3 Non-arithmetic orders Preliminary decisions which must be made in the design of a digital computer include the selection of a set of orders available for external programming of problems and the selection of a set of trans- formations from which the orders are internally programmed. There is a logically minimal set of orders for a general purpose computer; additional -129- orders are included in the set to simplify the coding of problems for the machine. Obviously, the nature of the problems which the machine is to solve dictates to a large extent the set of orders available for external programming . Actually, the designer must achieve a balance between the usefulness of additional orders on the one hand and the cost and unreliability inherent in the corresponding increase in equipment on the other. The use of a single address code or of a double address code of the type described in section 5°2 necessitates inclusion of specific transfer orders . The R order transfers numbers from the memory to the arithmetic register, the A order transfers numbers from the arithmetic register into the accumulator, and the S order reads numbers from the accumulator into the memory. Use of the double address code removes the necessity of providing unconditional control transfer orders. A conditional control transfer order is necessary in order that decisions based upon previous calculations can affect the nature of further computation. Provisions for arithmetically correct left or right shifts are included. The shifts effectively multiply or divide the numbers stored in the accumulator and arithmetic register by two. Provision is made in the ORDVAC for changing addresses in orders by means of the partial substitution orders. For the arithmetic unit des- cribed in Chapter III, the extract or logical multiplication order is simpler to achieve than a partial substitution order. Finally, orders for stopping the machine and for communicating with the input-output mechanism are included. These orders are the stop, input, and print orders. •130- Section ^ oh Control design 5c4l Function of the control The function of the control circuitry is to supply the necessary stimuli to the memory and arithmetic unit in the proper sequence to execute the orders of the machine. The control circuits must also interpret the "binary digits representing the orders and automatically consult the memory for further orders when an order is complete. 5 A2 Features The design discussed here is that of a control which is asynchronous and kinesthetic in nature. Rather than employing a central source for all stimulating pulses, the control proceeds to the next step of the sequence of transformations upon receipt of a signal that the previous step has been executed. The control employs a set of flipflops, which shall be referred to as the control flipflops. If there are n of these flipflops, there are correspondingly 2 unique states. A particular transformation occurring in the execution of a given order will he enabled by one of these 2 states. The stimulus executing the transformation will be used to change one or more of the n flipflops, and the set of flipflops assumes another of the 2 states. Corresponding to this second state, the next transformation of the sequence is enabled. The process by which a transformation is effected will be described in more detail. In the OFDVAC, negative voltages are used as stimuli. When a transformation is not to be executed, the stimulating voltage assumes its -131- most positive value. If the set of flipflops then assumes a state corresponding to the transformation, the stimulating voltage goes negative- When it reaches a certain negative value, the transformation will be effected. The circuitry is designed so that the stimulating voltage must go even more negative before any change occurs in the set of control flipflops. Thus if the stimulus gradually becomes weaker (goes less negative) over a period of time, the first failure to occur will be that the set of control flipflops will fail to change. The computation will then be halted with no loss of arithmetic data. A restriction on designs of this sort becomes apparent. The nature of this design restriction is indicated in the circuits of Figs. 5-1 and 5.2, illustrating incorrect and correct methods of programming three suc- cessive transformations T , T , and T using two control flipflops A and B. In both circuits T is enabled by A = 0, B = 0; T by A = 0, B = 1; and T by A = 1, B = 0. In the circuit of Fig. 5.1, the stimulus effecting T is applied to both control flipflops A and B, changing A from to 1 and B from 1 to 0. If flipflop A is slow in turning over, B will turn to while A is still and T stimulus will momentarily be enabled. One method of preventing the false T stimulus is to ensure that A is turned to 1 before B turns to by use of the circuitry shown in Fig. 5.2. Here the T stimulus turns A to a 1 and the ensuing control state A - 1, B = 1 is used to change B to 0. Of course a simpler way of effecting the three transformations is to assign -132- i J i oo A fe) T, ? 1 01 ^ *- ^ 1 r 1 ©-J 2 —- T3 B i 1 1 I A B o o o I T, B — ) I O T, T. A -*■ \ . e> — o o FI6.5.I INCO&fcEGT METUOO OF PROGQAMMING T M T X1 4 T-: T 3 CJ 1 ■ A l 00 { 4- ■1 1 01 J 1 ©- U 1 1 1 i Bt IO '3 y B \ a b 1 1 CO I A— 1 \J ©^O \ Zk-^o FIG. 5.2 PREFERABLE METHOD OF PUOGCAMMING T,T^4T 3 . -133- state A = 1, B = 1 to the transformation T , leaving the control state A = 1, B = free for other transformations. In all subsequent designs, whenever possible only one flipflop will be changed between successive transformations; if two or more flip- flops must be changed, intermediate control states will be designated and will not otherwise be assigned. 5.^-3 Geometrical analogy for control design It is convenient in subsequent control designs to use a geometrical model. For a control system employing n flipflops, the anal- ogous geometrical figure is a unit n-dimensional cube. Each of the n flipflops corresponds to one of the n dimensions. The 2 possible con- trol states correspond to the 2 vertices of the n-cube. A change from one control state to the next involving only one flipflop change is equivalent to traversing one of the edges of the n-eube. The circuitry shown in Fig. 5-2 will be discussed as an example. The analogous geometrical model is a square as indicated in Fig. 5°3° A change in flipflop A corresponds to traversing a hori- zontal edge; a change in flipflop B corresponds to traversing a vertical edge. The transformation T enabled by A = 0, B = corresponds to the lower left-hand vertex of the square. The sequence of transformations of the circuit of Fig. 5°2 corresponds to traversing the edges of the square in a clockwise direction. -13^- Ol • •- II oo T 3 10 A PIG. 5.S - GEOMETEICAL ANALOGY TO SEQUENCE OF TT2AKJSFO-C.M ATIONS OF HGUEE 5.2., -135- 5.44 Flow diagram for internal programming We have noted that, in the control, sufficient flipflops are provided so that a unique flipflop state can be assigned to each trans- formation executed within the machine . The process of assigning flip- flop states requires, as a preliminary step, the preparation of a flow diagram, or its equivalent, showing all sequences of transformations for all orders executed . A portion of such a flow diagram indicating the carry assimilation process is shown in Fig. 5-4. We assume that the carry assimilation process, which requires four transformations in the accumulator and carry registers, is pre- ceded by a transformation T and is followed by a transformation T p , for a total of six transformations considered. Three flipflops are required to provide six unique states. Two types of blocks appear on the flow diagram. The first type is a transformation box indicating the sequence of transformations . The second type of block is the decision box. Here arithmetic information is sensed to determine which of two possible transformations is to be next executed. In the example of Fig. 5° 4, after each carry assimi- lation sequence of four transformations a decision box is encountered. The arithmetic information is obtained by sensing the carry register C. If not all digits of C are zero, the carry assimilation sequence is begun again; otherwise the transformation T is executed. The assignment of flipflop states is indicated by the three digit binary numbers written above the transformation boxes. The assignment of flipflop states is considerably simplified by consideration of paths traced along edges of the corresponding 3 _ cube shown in Fig. 5»4. -137- Note that when a particular vertex of the 3 -cube can "be left by two possible paths , a decision box is encountered in the flow diagram. Section 5»5 Design details of control for general purpose computer 5 . 51 Introduction We now apply the techniques of the previous sections to the design of a control of a simplified general purpose computer. The term "general purpose" has certain implications in regard to the logical structure of a machine. These implications affect the design in two ways : 1) The machine must be capable of extracting symbols indicative of orders from the memory in a desired sequence, and must also interpret each order symbol and execute each order correctly. 2) There is a minimal set of orders which must be included in the design of a general purpose machine. Specific techniques for extracting, interpreting, and executing orders are described in section 5»52. A list of orders included in our sim- plified designs is discussed in section 5 • 53 » The detailed flow diagram and the analogous 6-cube paths are discussed briefly in section 5°5^« -138- 5.52 Order extraction and decoding The orders stored in the memory can he decomposed into three parts, as described in section 5-2. These parts are: i) The function digits, which specify the order to be executed. 2) The number address digits, which specify the address in the memory of the number used in the execution of the order. 3) The order address digits, which specify the address in the memory of the next order to be executed. For the design discussed here, four registers are involved in the order extraction and decoding process. These registers are: 1) The memory register M, which stores both orders and numbers after their extraction from the memory. 2) The address register AR, which stores address digits specifying the memory address consulted during all transfers to or from the memory. 3) The control register CR, which provides temporary storage for order address digits during execution of an order. k) The dynamic function register FR, which comprises two sets of flipflops, a set of six order sequencing control flipflops and a set of two control sequencing flipflops. The extraction of an order from the memory takes place in the following way. When the execution of an order is complete, the order -139- address specifying the location of the next order is transferred from the control register to the address register. The order is then transferred from the memory to the memory register, with the address register digits specifying the memory location consulted. The three parts of the order are then transferred from the memory register in turn. The four function digits are transformed to yield six digits which are then transferred to the function register. The number address digits are transferred to the address register, and the order address digits are transferred to the control register. The execution of the order is then begun. 5.53 Orders included in simplified design A list of orders included in the simplified computer design is presented in Table 5.1. The orders listed include a positive multiplication order and four addition-subtraction orders. Programming of these five arithmetic orders is described in Chapter III. Left and right shift orders are also included. These orders correspond to multiplication and division by two, respectively. Three orders are provided for necessary number trans- fers as discussed in section 5«3» It should be noted that carries are assimilated as a preliminary step for orders requiring sensing of the sign digit of the accumulator, as in the C and RS orders, and for the transfer from the accumulator of the S order. Execution of the conditional control transfer order requires elaboration. For this order, the order address digits specify the location of the next order to be executed if the number in the accumulator is negative, If the number in the accumulator is positive, the number address digits specify the location of the next order to be executed -Ro- table 5.1. LIST OF ORDERS FOR SIMPLIFIED COMPUTER DESIGN 1. +c S(x) -> Ac+ 2. -c S(x) -» Ac- 3. +h S(x) ->• Ah+ 4. -h S(x) -> Ah- 5. X S(x)XR -* A 6. R S(x) -* R 7- A R - A 8.* C c C -* S(x) c 9** S A -> S(x) 10. LS LS 11.* RS RS Addition Subtraction Orders Positive Multiplication Order Transfer Orders Conditional Control Transfer Order Store Order Left Shift Arithmetically Correct Right Shift ^Require carry assimilation ■llH- 5-5^« Flow diagram and geometrical analogy for simplified design The control design techniques discussed in preceding sections are applied in this section for the assignment of control flipflop states to transformations for our simplified design. The first step of the pro- cess is the preparation of the flow diagram of Fig. 5-5; showing all sequences of transformations required. The flow diagram is essentially a synthesis of all flow diagrams for individual orders, plus the flow diagram for the order extraction sequence. It may he noted that if two or more orders are concluded by exactly the same sequence of trans- formations, the flow diagrams of the orders may be merged. The addition orders exemplify this feature. The total number of transformations required for order execution is 5k. (if the same transformation occurs during execution of two orders, it is counted twice.) The minimum number of control flipflops required for order sequencing is therefore six. Four additional transformations are required for the order extraction process. Correspondingly, two flipflops are required for the order extraction sequencing. The two sets of flipflops, the one set of six for order sequencing and the second set of two for order extraction, must be treated separately since the former set is changed during order extraction controlled by the latter set. The assignment of control states to the transformations is similar to the process described in section 5'kk. The geometrically analogous figure is the 6-cube, illustrated in Fig. 5.6. The particular edges traversed and vertices used are indicated in Fig. 5«T- The assignment of control states is governed by the following considerations: -1U2- ■1^3- 1 is PP- 5^-H^- 7. Meagher, R. E., and Nash, J. P.; "The ORDVAC," Review of Electronic Digital Computers (Proceedings of Joint AIEE-IRE Computer Conference, Philadelphia, December 10-12, 1951 ) American Institute of Electrical Engineers, 1952; pp. 37-^3. 8. Shannon, Claude E., and Weaver, W„; The Mathematical Theory of Communication . Urbana: The University of Illinois Press, 19^9* P» ^8« 9° Staff of Applied Mathematics and Computer Engineering Sections of Physics Division, Argonne National Laboratory, "Progress Report on the Argonne-Oak Ridge Digital Computer," (ANL-4600), Argonne National Laboratory, March 5, 1951, pp. 20-21. 10. Staff of Harvard Computation Laboratory, Synthesis of Electronic Computing and Control Circuits . Cambridge: Harvard University Press, 1951. -155- FEB to im y* uONO,