■HBHHHHflfl U.S. DEPARTMENT OF COMMERCE • National Oceanic and Atmospheric Administration • National Waattw Se^tcu Instruction Manua Isolation Distribution Equipment (IDE) ENGINEERING DIVISION INSTRUCTION MANUAL NO. 6-1 18/6-1 19 U. OF I. ! LIBRaUY tf CHaHPalGH BOOKSTkCKS INSTRUCTION BOOK ISOLATION DISTRIBUTION EQUIPMENT VOLUME 1 CONTRACT DOT FA78WA-4211 WITHDRAWN University of Illinois library CONTRACTOR ELECTRODYNAMICS, INC. 1200 HICKS ROAD ROLLING MEADOWS, ILLINOIS 60008 MADE FOR U.S. DEPARTMENT OF COMMERCE NATIONAL WEATHER SERVICE • f « ^gjJOgte- '""■MemofC* Instruction Manual Isolation Distribution Equipment Engineering Division Silver Spring, Md. February 1981 U. S. DEPARTMENT OF COMMERCE Malcolm Baldrige, Secretary National Oceanic and Atmospheric Administration Anthony J. Calio, Deputy Administrator National Weather Service Richard E. Hallgren, Assistant Administrator . RECORD OF CHANGES Specification No FAA-D-2494/la FAA-D-2494/2a CHANCE TO 1ASIC SUPPLEMENTS OPTIONAL USE CHANCE TO • ASIC SUPPLEMENTS OPTIONAi USE FAA Form 1320-5 (j-48i supersedes p«vious edition «»0 ilMOI-IM-lll VALIDATION PERFORMANCE TITLE OF DOCUMENT: CONTRACTOR : SUBCONTRACTOR: APPLICABLE CONTRACT AND PURCHASE ORDER NUMBERS: SECTION NUMBER PARAGRAPH AND PARAGRAPH NUMBERS DATE OF VALIDATION COMPLETION CHECK BELOW IF NOT VALIDATED AUTHORITY VALIDATE [G OFFICER SIGNATURE OF VALIDATING OFFICER VALIDATING OFFICER'S TITLE « 11 Section Paragraph 1 1.1 1.2 1.2.1 1.2.2 1.2.3 1.3 1.4 1.5 ■» •> TABLE OF CONTENTS Page GENERAL INFORMATION AND REQUIREMENTS 1 1 Introduction Equipment Description Purpose RRWDS Modifications Equipment Description Equipment Specification Data Equipment and Accessories Supplied Equipment Required But Not Supplied 1-13 2 TECHNICAL DESCRIPTION 2-1 2.1 Introduction 2-1 2.2 Data Format 2-1 2.3 Block Diagram Functioning 2-1 2.3.1 IDE Functioning 2-1 2.3.2 Battery Charger CCA N1A1A1 Functioning 2-4 2.3.3 Display Mounting No. 1 and No. 2 CCAs N1A1A3/A2 2-4 2.3.4 Power Supply No. 1 and No. 2 CCA N1A2A1/A2 Functioning 2-4 2.3.5 Synchro Converter CCA N1A2A3/A4 Functioning 2-6 2.3.6 Synchro Output CCA N1A2A5 Functioning 2-8 2.3.7. DE Receiver CCA N1A2A6 Functioning 2-8 2.3.8 Clock/Display CCA N1A2A7 Functioning 2-11 2.3.9 DE Transmitter CCA N1A2A8 Functioning 2-11 2.3.10 Input Buffer CCA N1A2A9 Functioning 2-14 2.4 Detailed Functioning 2-14 2.4.1 DE Power Supply No. 1 and No. 2 CCA N1A2A1/A2 2-14 2.4.2 Synchro Converter CCA N1A2A3/A4 2-19 2.4.3 Synchro Output CCA N1A2A5 2-26 2.4.4 DE Receiver CCA N1A2A6 2-26 2.4.5 Clock/Display CCA N1A2A7 2-29 2.4.6 DE Transmitter CCA N1A2A8 2-31 2.4.7 Input Buffer CCA N1A2A9 2-33 3 OPERATION 3-1 3.1 Introduction 3-1 3.2 Controls and Indicators 3-1 3.3 Operating Procedures 3-1 3.3.1 Connections 3-1 3.3.2 General 3-1 3.3.3 Equipment Turn-On 3-1 3.3.4 Clock Set 3-4 3.3.5 Miscellaneous 3-5 4 STANDARDS AND TOLERANCES 4-1 4.1 Introduction 4-1 5 PERIODIC MAINTENANCE 5-1 5.1 Performance Checks 5-1 5.2 Other Maintenance Checks 5-1 in TABLE OF CONTENTS (Cont) Section Paragraph Page 6 MAINTENANCE PROCEDURES 6-1 6.1 General 6-1 6.2 Performance Tests 6-1 6.3 Other Maintenance Task Procedures 6-5 6.3.1 Routine Inspection 6-5 6.3.2 Air Filter Cleaning and Inspection 6-5 6.4 Special Maintenance Procedures 6-5 7 CORRECTIVE MAINTENANCE 7-1 7.1 Introduction 7-1 7.2 Semiconductor Devices/Integrated Circuits Precautions 7-1 7.3 Circuit Board Component Replacement 7-2 7.4 Test Equipment 7-3 7.5 Troubleshooting Procedures for the IDE 7-3 7.5.1 Introduction 7-3 7.5.2 Symptoms 7-3 8 PARTS LIST 8-1 8.1 General 8-1 8.1.1 Reference Designation 8-1 8.1.2 Indenture Letter 8-1 8.1.3 Name of Part and Description 8-1 8.1.4 Manufacturer's Code 8-1 8.1.5 JAN, MIL, or Manufacturer's Part Number 8-1 8.1.6 Notes 8-1 8.2 Reference Designation Assignment 8-1 9 INSTALLATION, INTEGRATION, AND CHECKOUT 9-1 9.1 Introduction 9-1 9.2 Unpacking and Handling 9-1 9.3 Power Requirements 9-1 9.4 Isolation 9-1 9.5 Installation Procedures 9-1 9.5.1 Wall Mounting 9-1 9.5.2 Installation Check 9-1 9.5.3 Special Instructions 9-1 9.5.4 IDE Wiring 9-3 9.5.5 Connections 9-8 9.6 Final Checkout 9-8 9.6.1 Equipment Turn-On 9-8 9.6.2 Radar Trigger Adjustment 9-8 9.6.3 Status Check 9-8 10 TROUBLESHOOTING SUPPORT DATA PART 10-1 IV •> •t LIST OF ILLUSTRATIONS Section Figure Page 1 1-1 Isolation Distribution Equipment 1 2 1-2 Isolation Distribution Equipment Front Access Panel Removed 1 3 1-3 Isolation Distribution Equipment - Normal Maintenance Position 1-4 1-4 Isolation Distribution Equipment — Normal Maintenance Position with Connector Panel Removed 15 2 2-1 Serial Radar Data Format 2-2 2-2 Isolation Distribution Equipment/Block Diagram 2-3 2-3 Power Supply No. 1 and No. 2 CCA N1A2A1/A2, Block Diagram 2-5 2-4 Synchro Converter CCA N1A2A3/A4, Block Diagram 2-7 2-5 Synchro Output CCA N1A2A5, Block Diagram 2-9 2-6 DE Receiver CCA N1A2A6, Block Diagram 2-10 2-7 Clock/Display CCA N1A2A7, Block Diagram 2-12 2-8 DE Transmitter CCA N1A2A8, Block Diagram 2-13 2-9 Input Buffer CCA N1A2A9, Block Diagram 2-15 2-10 Input Rectifier and Filter 2-16 2-11 Control IC Supply 2-17 2-12 Switching Converter with 5 Vdc and ±12 Vdc Output Voltages 2-18 2-13 Switching Converter with Isolated 5 Vdc Output 2-21 2-14 Quadrant Representation and Actual Polarities for Sine and Cosine 2-23 2-15 Quadrant Selection and Output Polarities 2-23 2-16 Operational Amplifier Summer Equivalent Circuit 2-24 2-17 DVIP Data Timing Diagram 2-32 2-18 Typical Input Isolator Stage 2-34 3 3-1 Isolation Distribution Equipment, Controls and Indicators 3-3 9 9-1 Typical Wall-Mount Installation 9-2 9-2 Connector Assembly, WSR-74 System Trigger Cable 9-4 9-3 Connector Assembly, WSR-74 Data Cable 9-4 9-4 Connector Assembly, WSR-57 Synchro Cable 9-5 9-5 Connector Assembly, WSR-57 Data Cable 9-5 LIST OF TABLES Section Tab 1 1-1 1-2 1-3 2 2-1 2-2 3 3-1 5 5-1 5-2 6 6-1 7 7-1 7-2 8 8-1 8-2 9 9-1 9-2 Page Equipment Specifications 1-7 IDE Equipment and Accessories Supplied 1-10 Equipment Required But Not Supplied 1-13 Contents of PROM A and PROM B for Azimuth Angles 2-27 Contents of PROM A, C, 1,2 and 3 for Elevation Angles 2 28 IDE Controls and Indicators 3-2 Performance Checks 5-1 Other Maintenance Tasks 5-1 Isolation Distribution Equipment Performance Tests 6-2 Test Equipment Required 7 3 Symptoms and Index to Troubleshooting 74 Parts List 8-2 List of Manufacturers 8-62 WSR-74 Connections 9-6 WSR-57 Connections 9-7 VI SAFETY NOTICE The attention of operating and maintenance personnel is directed to FAA Instruction 6000 .1 [> "Maintenance of Airway Facilities" for instructions on the subject of safety precautions to be observ- ed, and to FAA Order 3900.19 "Occupational Safety." This equipment employs voltages which can cause severe burns. Caution shall be exercised when working with equipment. KEEP AWAY FROM LIVE CIRCUITS Operating and maintenance personnel must at all times observe all safety regulations. Do not change plug-in components with high voltage supply on. Under certain conditions, potentials may exist in cir- cuits with power controls in the off position due to charges retained by capacitors. RESUSCITATION Maintenance personnel should familiarize themselves with the technique for resuscitation found in the manual of first aid instructions. PRECAUTIONARY NOTICE, SEMICONDUCTOR DEVICES/INTEGRATED CIRCUITS (a) Semiconductor devices are delicate. There are three principal abnormalities that are most harmful to semiconductors. These are (1) excessive voltage or current, (2) excessive temperature, and (3) excessive shock. Semiconductors are unusually susceptible to static discharge because of their low operating voltages and the construction of the semiconductor junction. The following are samples of various abnormalities encountered in practice, but it is important that personnel who work with semiconductors be proficient enough to realize the semiconductor's capabilities and limitations so that they can do maintenance with confidence. (b) Static discharge can be avoided by eliminating all external connections to the circuit that can provide a ground path. Leads which have a high capacity to ground, such as ac power or antenna transmission lines and the elements of soldering irons, should not be touched to semiconductor cir- cuits while the circuits are grounded. First, discharge the lines, and then connect them. The human body can also accumulate sufficient potential to discharge a damaging spark. (c) Capacitors connected in the circuit should not be touched with external leads and should not be connected or disconnected while iney still retain a charge. But both capacitors and semicon- ductors can be damaged by discharging the capacitor through a direct shunt. The capacitor should be allowed to discharge normally through the circuit RC time constant or be discharged through an exter- nal bleeder. Nothing in a semiconductor circuit should be connected or disconnected with power applied. (d) Defective circuit components can provide excessive capacitive or resistive leakage currents that damage semiconductors either directly or because of bias changes that increase power consump- tion. For example, any coupling capacitor is capable of this if it should leak and provide abnormal for- ward bias to the following semiconductor. (e) Always use some form of heat sink (usually pliers) between the semiconductor body and the soldering iron. The tendency is to use irons of too high a wattage rating (stay below 50 watts). The use of soldering guns should be avoided. The best soldering tool is one with replaceable tips of various wattages plus the unsoldering devices and vacuum tools for removal of excess solder. Do not unsolder a component known to be bad if it can be cut loose from the circuit. Then, only the leads need un- soldering, and this can be done quickly. If the leads are very short, cut the body of the component with side cutters. (f) Cutting semiconductor leads with a side cutter causes an appreciable shock wave to be transmitted to the junction; this shock can cause rupture. The lead to be cut should be held with pliers between the body of the semiconductor and the place of cutting to absorb the shock. Similar damage VII may be caused if the transistor is dropped. Striking a transistor case in search of intermittents is poor practice. Another cause of mechanical damage is overtightening of stud-mounted semiconductors. The mount should be mechanically secure, but the electrical efficiency of the joint is a matter of cleanli- ness in the joining surfaces. Never strike a circuit board against the bench to shake off solder. (g) Ohmmeters used for continuity checks should never be used on the lowest ranges or on the highest ranges. Only general warnings can be given to this instruction book; no ohmmeter should ever be used with semiconductors until its instruction book has been studied. An ohmmeter has doubtful value as a service tool for semiconductors out of the circuit. Use a transistor tester with at least the capability to test gain and capacitive leakage. (h) Applying operating voltage of incorrect polarity can ruin semiconductors. A simple way to ensure proper polarity is to take a spare diode and connect it to the circuit so that it will block the supply if it is connected in reverse. This diode can be tack-soldered to the circuit board input or to the incoming lead from the power supply. The diode should, of course, be capable of handling the voltage and current requirements of the circuit plus the surges of the supply. WARRANTY (a) Notwithstanding inspection and acceptance by the Government of supplies furnished under this contract or any provisions of this contract concerning the conclusiveness of said inspection and acceptance, the Contractor warrants each item delivered under the contract against defects in design, material or workmanship, and against any damage caused prior to delivery to the Government. Unless otherwise specified, this warranty extends for a period of one year from the date of first use by the Government or two years from date of delivery, whichever occurs first. (b) Upon notice in writing, the Contractor shall, within 30 days after receipt of such notice, repair or replace all defective or damaged items delivered under the contract, f.o.b. an\ point or points designated by the Government with the 48 contiguous states and the District of Columbia, at no cost to the Government. In the event the contractor is unable to effect such repair or replacement within the aforesaid 30 days, he shall, within 50 days after receipt of notice, submit in writing a schedule of repair or replacement to the Contracting Officer. The Contractor may elect to have any replaced item returned to his plant at his expense. (c) Unless they fail as a result of improper application by the Contractor, electron tubes, batteries, natural rubber, and material normally consumed in operation are excluded from this war- ranty, but shall in any event be warranted by the Contractor to the extent of any warranty received by the Contractor from his supplier. (d) If twenty percent (20%) or more of the total quantity of any part of a component to which this warranty applies (but not fewer than two of any such part or component) fails in normal service, that fact shall be conclusive evidence that the desgin, material, or workmanship of the item delivered under the contract is unsuitable for the purpose intended. Upon notice of this failure rate, the Contrac- tor shall: (i) replace all quantities of the part of component with a corrected part or component in a manner satisfactory to the Government, and at no cost to the Government, and (ii) if necessary to en- sure correction of the deficiency, redesign the item delivered under the contract, or any portion thereof, in a manner satisfactory to the Government and at no cost to the Government. The provisions of this paragraph (d), however, shall not apply to any part or component to be furnished which is specifically identified in the contract by brand name; provided, however, that the Contractor shall war- rant such part or component to the extent of any warranty received by the Contractor from his supplier. (e) For a period of one year from the date of its first use by the Government or two years from the date of its replacement or redesign, whichever occurs first, each item (or portion thereof) or part or component, which is replaced or redesigned pursuant to paragraph (d) above, shall itself be war- ranted in accordance with the terms of paragraph (d). vuj 1 •• •> (f) The warranty periods specified herein shall exclude any period of time ;in item fail:, to per form satisfactorily due to defects or damage to which this warranty applies. (g) For the purpose of this "Warranty" clause, the term "item" is defined as the contract line item. In the event any item part, or subpart, or component thereof fails, the Contractor shall be responsible for all actions necessary to correct such failure and return the contract line item to operating order. (h) Failure to agree upon any determination to be made under this clause shall be a dispute con- cerning a question of fact within the meaning of the "Disputes" Clause of this contract. IX FAMILY TREE CHART ISOLATION DISTRIBUTION EQUIPMENT FRONT PANEL ASSEMBLY 3260044 BATTERY CHARTER ASSEMBLY 8501287 DISPLAY MOUNTING BOARD FINAL ASSEMBLY 4260081A1 N1A1A1 BATTERY CHARGER CCA 4260079 N1A1A2 DISPLAY MOUNTING BOARD NO. 1 4260077A1 N1A2A1 POWER SUPPLY NO. 1 4260067A1 N1A2A2 POWER SUPPLY NO. 2 4260067A1 N1A2A3/A4 SYNCHRO CONVERTER CCA 4260061A1 N1A2A5 SYNCHRO OUTPUT CCA 4260062A1 N1A2A6 D.E. RECEIVER CCA 4260065A1 N1A2A7 CLOCK/DISPLAY CCA 4260066A1 N1A1A3 DISPLAY MOUNTING BOARD NO. 2 4260078A1 N1A2A8 D.E. TRANSMITTER CCA 4260064A1 N1A2A9 INPUT BUFFER CCA 4260063A1.A2 N1A2A11 EXTENDER CARD 4260080A1 N1A2A12 BACKPLANE ASSEMBLY 4260068 A 1 FUNCTIONAL INDEX MAJOR FUNCTION MAJOR DESCRIPTION FRONT BLOCK FUNCTION SCHEMATIC DETAILED PARTS WIRING MATTER DIAGRAM TEXT DIAGRAM THEORY ALIGN DATA DIAGRAM PAGE NO. PAGE NO. PAGE NO. PAGE NO PAGE NO PAGE NO PAGE NO PAGE NO. Manual Description Integrated Circuit Data 10-77 Data Format 2-1 IDE 2-3 2-1 Battery Charger CCA N1A1A1 2-4 10-23 Display Mounting No. 1 and No 2 CCAs 2-4 10-25 N1A1A3/A2 10-27 Power Supply No. 1 and No. 2 CCAs N1A2A1/A2 2-5 2-4 10-29 2-14 Synchro Converter CCA N1A2A3/A4 2-7 2-6 10-31 2-19 Synchro Output CCA N1A2A5 2-9 2-8 10-37 2-26 DE Receiver CCA N1A2A6 2-10 2-8 10-37 2-26 Clock/Display CCA N1A2A7 • 2-12 2-11 10-41 2-29 DE Transmitter CCA N1A2A8 2-13 2-11 10-45 2-31 Input Buffer CCA N1A2A9 2-16 2-14 10-49 2-33 xi/xii r ' - SECTION 1. GENERAL INFORMATION AND REQUIREMENTS 1.1 INTRODUCTION. The purpose of this information book is to provide all data needed to properly operate, maintain, and repair the Isolation Distribution Equipment (see figure 1-1) (hereinafter referred to as IDE). The IDE is part of the Radar Remote Weather Display System (RRWDS). For complete coverage, this instruction book must be used in conjunction with the RRWDS instruction books. 1.2 EQUIPMENT DESCRIPTION. 1.2.1 Purpose. — The purpose of the IDE is described below: 1.2.1.1 The Isolation Distribution Equipment (IDE) interfaces with National Weather Service (NWS) WSR-57, WSR-74C, and WSR-74S radars, the FAA Radar Remote Weather Display System (RRWDS), and non-governmental display remoting equipment. 1.2.1.2 The IDE accepts 8-bit parallel, filtered radar data and status information from the government furnished Digital Video Integrator and Processor (DVIP) and converts it into a composite serial format for distribution to multiple users, providing complete isolation between the radar and the equipment. The IDE also provides optical isolation and synchro-to-digital conversion of antenna position and azimuth information from the WSR-57 radar. 1.2.1.3 The IDE provides optical isolation between the radar and multiple user equipment. The output from the IDE will drive a 75-ohm line, requiring the user equipment to be interfaced with an opto coupler. Opto coupling provides sufficient isolation to prevent loading by the IDE or any external equip- ment, thus eliminating the possibility of ground loops between equipment. 1.2.2 RRWDS Modifications. - Since the RRWDS must interface with both FAA and NWS radars, the RRWDS Type IV Weather Digitizer (FA-9901/4) and Type V Weather Digitizer (FA-9901/5) equipment must be modified to accept the serial data provided by the IDE. This modification involves removing the parallel interface, the azimuth and elevation synchro modes, the digital video integrator and pro- cessor, and the digital clock. To accommodate the serial interface, a serial receiver and a communica- tion processor card must be added to the RRWDS. Operation and maintenance instructions for the RRWDS Types IV and V Weather Digitizers are given in Tl 6340.15. 1.2.3 Equipment Description. — The physical arrangement of the IDE is shown in figures 1-2 through 1-4. The major physical assemblies are described in paragraphs 1.2.3.1 through 1.2.3.3 1.2.3.1 Enclosure. 1.2.3.1.1 The aluminum enclosure for the IDE is designed for wall mounting. Hardware is provided to allow the on-site mounting of the equipment on a masonary surface. Installation details are covered in Section 9. 1.2.3.1.2 Except for front panel and connector panel components, all electrical parts are mounted on plug-in printed circuit card assemblies (CCAs) which are accessible from the front of the enclosure by swinging open the front panel assembly. The front panel assembly is swung open by releasing five 1/4-turn, quick-release fasterers. All connections to the IDE are made via the connector panel on the bottom of the enclosure. 1-1 ENCLOSURE CONTROL PANEL ACCESS PANEL r r 1-2 Figure 1-1. Isolation Distribution Equipment r ENCLOSURE ACCESS PANEL TO BACKPLANE Figure 1-2. Isolation Distribution Equipment — Front Access Panel Removed 1-3 FRONT PANEL ASSEMBLY POWER SUPPLY NO. 2 POWER SUPPLY NO. I Figure 1-3. Isolation Distribution Equipment — Normal Maintenance Position 1-4 MOUNTING PAD FRONT PANEL ASSEMBLY POWER SUPPLY POWER NO. 2 SUPPLY NO. I SYNCHRO TRANSIENT PROTECTION ASSEMBLY CONNECTOR PANEL ASSEMBLY ^A— ** - s o 1 ! o o o o o o o r ! ft ft ft 1 :o: i i i i ! ! Q y w y i* L5U o i — -J o o o Figure 1-4. Isolation Distribution Equipment - Normal Maintenance Position with Connector Panel Removed 1-5 1.2.3.2 Front Panel Assembly. 1.2.3.2.1 The swing out front panel assembly consists of a display, all controls and indicators, a removable access panel, and a circuit card rack. The upper part of the front panel assembly is devoted to the display and control functions. This section is recessed approximately 1 inch to prevent any ac- cidental control operation. The controls and displays are grouped according to functional operation. 1.2.3.2.2 The front panel assembly has an access panel which can be removed to gain access to the backplane assembly connections. This panel will not be removed for normal type maintenance. 1.2.3.2.3 A card rack, mounted on the back face of the front panel assembly, houses the IDE circuit cards. Circuit cards are separated by function and contain both test points and adjustments that are accessible without the use of card extenders with the CCAs mounted in the card rack. Test points are provided for the measurement and observation of voltages and waveforms required for servicing, testing, and maintenance of individual units. Each CCA is individually keyed to its mating connector and also has an internal card ejector which provides a convenient means of removal of the mating halves of the connection and for grasping for removal from the rack. The printed circuit card extenders supplied with each unit are located in a spare block CCA receptacle position. The redundant power supplies are also packaged as plug-in circuit card assemblies. 1.2.3.3 Connector Panel Assembly. — The connector panel assembly mounts to the bottom of the enclosure. Since this panel is a separate assembly, the entire, completely wired system can be re- moved from the enclosure by removing the fasteners on the connector panel and lifting the front panel assembly from its hinges. A synchro transient protection assembly is mounted on the connector panel assembly as shown in figure 1-4. The AC line also has an EMI filter included in the entry power connector. 1.3 EQUIPMENT SPECIFICATION DATA. - Table 1-1 provides equipment specification data including functional characteristics, output characteristics, electrical power requirements, and environmental characteristics. 1-6 Table 11. Equipment Specifications FUNCTIONAL CHARACTERISTICS Radar Inputs: All digital inputs (from the radar) have open collector out puts. Signals common to both radars are as follows: Computer Data Bus The computer data bus is the 8-bit parallel filtered data C7-C0 (WSR-57) output with no STC correction. All 8 lines are open VOL 8 - VOL 1 collector outputs (i.e., receiving device provides pullup (WSR-74 only) resistor). The data is "low" true (i.e., Low - On; Data ="high" true. High = Off). Each output has its own return to ground which should be twisted with the original signal. Data is updated at 6.7 usee intervals. Data Ready This signal is a "low" true, open collector data strobe for the computer data bus. Clocking on the negative going transition is preferable. Test Level This open collector output indicates the state of the DVIP unit (High = NORM: Low = TEST). Range Coverage This open collector output indicates the number of kilometers being sent from the DVIP (High - 450 Km; Low = 230 Km). Selected Time Sample This DVIP open collector output indicates the azimuth resolving time sample of 15 or 31. WSR-57: (High = 31; Low = 15) WSR-74: (High = 15; Low = 31). Attenuate Bypass (IFATBPM) This open collector output indicates the state of the IF (WSR-74 only) attenuator (High = Attn in use; Low = Normal). Digital Synchro Data Five-wire synchro data is described below: (WSR-57) Accepts standard 5-wire (three stators, two rotors) 90V synchro information from the WSR-57 azimuth (31TX6) and elevation (23TR6) axes. These lines are isolated and transient protected. Synchro to digital converters for both azimuth and elevation are included. The elevation data from the WRS-57 is 2.5 times the true elevation. The elevation data is electronically multiplied by 0.4 (divided by 2.5) to yield true elevation data before distribution. AZ and EL BCD (0.1 through 200.0) These open collector outputs indicate the antenna azimuth or elevation angles in BCD degrees. System Trigger Positive-going pulse of between and 40 volts, 0.5 to 2.5 microseconds in width; leading edge starts zero range. Isolation The IDE is electrically isolated from all other equipment by the use of isolation transformers or optical isolators on all inputs and outputs. 1-7 Table 1-1. Equipment Specifications (Continued) FUNCTIONAL CHARACTERISTICS Inputs Outputs Different Radars All digital inputs are optically isolated including power supply isolated from the remainder of the distribution equipment. The synchro INHIBIT signals from the IDE to the radar are treated similarly. The WSR-57 synchro lines use transformer for isolation. The distribution equipment does not affect operation of the radar. All users are equipped to optically isolate with floating power supply when attaching to any of the eight serial outputs. All outputs are short circuit protected. Shorting any output does not affect the performance of any other output. Each output is capable of driving its signal into a characteristic 75 ohms impedance at the end of up to 200 feet of type RG59U or equivalent coaxial cable. The IDE accepts data from two basic radar systems: the WSR-57 and the WSR-74. IDE OUTPUT CHARACTERISTICS IDE Serial Output Data Format: General Format DVIP Data Data Block AZ (or EL) INHIBIT Antenna Position Data: Azimuth Position Elevation Position Output format is bit-serial, in an asynchronous format, with one start and one stop bit per 8-bit byte, plus an odd parity bit (1 1 -bits total). The least significant bit within each field is transmitted first. The serial bit rate is 1.789772 MHz, (one-half the NTSC standard T.V. subscriber frequency 3.579545 MHz ± 10 Hz). 8-bit (byte) per data point; 1 to 230 or 1 to 450 Km, in 1 Km increments, binary format. One full radial of data transmitted for each trigger pulse of the radar. Starting auxiliary data sync byte = HEX FF This "low true" signal from the distribution equipment to the radar freezes the output buffer of the converter allow- ing collection of data (High = Conversion in process; Low = Data "frozen"). BCD format: 000.0 to 359.9 DEC, 01 contained in two bytes. DEC resolution. Elevation position: BCD format, 000.0 to 359.9 DEC, 0.1 DEC resolution, contained in two bytes. Data between 000.0 and 065.0 are positive upward angles and data from 359.9 to 350.0 are negative downward angles when substracted from 360. 0. 1-8 Table 1-1. Equipment Specifications (Continued) IDE OUTPUT CHARACTERISTICS DVIP Status: Operating mode: normal or test. Azimuth response: effective sample size 15 or 31 Range coverage: 0-230 or 0-450 Km Manual IF attenuation (WSR-74 only); in use? Yes or No Bit-0: "1" = Normal "0" = Test Bit- 1 : "1" = 31 "0" = 15 Bit-2: "1" = 450 "0" = 230 Bit-3: "1" = IN "0" = Out (Note: Bit numbering assumes "0" = LSB, first transmitted; bit 4-7 not used = "0"). ELECTRICAL POWER REQUIREMENTS Voltage Amperage Frequency Phase Power Consumption 105 - 125 Vac 0.25A 60 ±2 Hz Single Phase 55W, Continuous, Fully Populated; 80W Surge ENVIRONMENTAL CHARACTERISTICS Ambient Temperature Range Relative Humidity Range Altitude Range + 10°C to +50°C 10% to 80% to 10,000 feet above sea level. 1 .4 EQUIPMENT AND ACCESSORIES SUPPLIED. Equipment and accessories supplied with the IDE are listed in Table 1-2. This includes an inventory of the Spare Parts Kit and the Installation Kit. 1-9 Table 1-2. IDE Equipment and Accessories Supplied QYT NOMENCLATURE PART NUMBER FSCM SPARE PARTS KIT SPK-R541 (WSR-74) Serial Receiver CCA 4260065A1 10236 DE Transmitter CCA 4260064A1 10236 Input Buffer CCA 4260063A2 10236 Clock Display CCA 4260066A1 10236 Battery Charger CCA 4260079A1 10236 Power Supply CCA 4260067A1 10236 Extender Card 4260080A1 10236 Display Mounting Assembly 4260081 A1 10236 2 Lamp 7230016-1 10236 2 Lamp 7230016-4 10236 2 Lamp 7230017-1 10236 2 Display, 7 Segment 7230023-1 10236 2 LED 7030057-1 10236 10 Fuse, 1/2A SLO 7260011-15 10236 1 Switch 7152050-1 10236 1 Switch 7152051-2 10236 1 Switch 7152052-1 10236 1 Switch 7152051-1 10236 1 Switch MS90311-21 1 96906 INSTALLATION KIT 1130065A2 (WSR-74) 1 Interconnect Cable (System Trigger) 2260020A1 10236 1 Interconnect Cable (Data) 2260019A1 10236 1 Connector, Straight Plug MS3116J-22-55P 96906 1 Connector, BNC UG-260C/U 81349 1 Cord, Power, 3 Wire 8030046 10236 8 Terminator, 75 Ohm 7010048 10236 4 Bolt, Lag MS16992-199 96906 4 Anchor, Screw 8141114-1 10236 4 Anchor, Screw 8141114-2 10236 1-10 Table 1-2. IDE Equipment and Accessories Supplied (Continued) QYT NOMENCLATURE PART NUMBER FSCM 4 Washer, Flat MS15795-810 96906 4 Washer, Flat MS15795-814 96906 4 Shield, Exp. FF-S-323 81349 AR Solder SN60 81349 SPARE PARTS KIT SPK-540 (SWR-57) DE Receiver CCA 4260065A1 10236 DE Transmitter CCA 4260064A1 10236 Input Buffer CCA 4260063A1 10236 Clock Display CCA 4260066A1 10236 Battery Charger CCA 4260079A1 10236 Synchro Converter CCA 4260061A1 10236 Synchro Output CCA 4260062A1 10236 Power Supply CCA 4260067A1 10236 Extender Card 4260080A1 10236 Display Mounting Assembly 4260081 A1 10236 2 Lamp 7230016-1 10236 2 Lamp 7230016-4 10236 2 Lamp 7230017-1 10236 2 Display, 7 Segment 7230023-1 10236 2 LED 7030057-1 10236 10 Fuse, 1/2A SLO 7260011-15 10236 1 Switch MS9031 1-221 96906 1 Switch 7152050-1 10236 1 Switch 7152051-2 10236 1 Switch 7152052-1 10236 1 Switch 7152051-1 10236 INSTALLATION KIT 1130065A1 (WSR-57) 1 Interconnect Cable (Data) 226001 7A1 10236 1 Interconnect Cable (Synchro) 2260018A1 10236 1-11 Table 1-2. IDE Equipment and Accessories Supplied QYT NOMENCLATURE PART NUMBER FSCM 1 Connector, Straight Plug MS3106A-32- 414S 96906 12 Terminal, Ring Lug 8240053-1 10236 Clamp, Cable AN3057-20 88044 Cord, Power, 3 Wire 8030046 10236 Bushing MS3420-8 96906 Bushing MS3420-10 96906 Bushing MS3420-12 96906 Bushing MS3420-16 96906 Bushing MS3420-20 96906 30" Insulated Sleeving Class I, Clr. 81349 8 Terminator, 75 Ohm 7010048 10236 4 Bolt, Lag MS16992-199 96906 4 Screw, Anchor 814114-1 10236 4 Screw, Anchor 814114-2 10236 4 Washer, Flat MS1 5795-810 96906 4 Washer, Flat MS1 5795-814 96906 4 Shield, Exp. FF-S-325 81349 AR Solder SN60 81349 1-12 1.5 EQUIPMENT REQUIRED BUT NOT SUPPLIED. Equipment required but not supplied is listed in Table 1-3. Table 1-3. Equipment Required but not Supplied NATIONAL STOCK NOMENCLATURE PART NUMBER NUMBER FSCM Pliers 5110-00-240-6209 81348 Pliers 5120-00-293-3481 81348 Stripper, Wire 5110-00-268-4224 81348 Screwdriver, Flat Tip 5120-00-278-8502 81348 Screwdriver, Flat Tip 5120-00-278-1267 81348 Screwdriver, Phillips 5120-00-240-8716 81348 Screwdriver, Phillips 5120-00-227-7293 81348 Crimper 1963 79061 Handle, Soldering .750 78976 Heater, Soldering 1237-S 78976 Tip, Soldering PL-151 78976 Tip, Soldering PL-155 78976 Alignment Tool 35F818 72653 Wrench, Adjustable 7760 79061 1-13/1-14 ' > > SECTION 2. TECHNICAL DESCRIPTION 2.1 INTRODUCTION. This section contains the technical details for the Isolation Distribution Equip ment (IDE). Presentation of the data is intended to provide adequate technical detail to (1) support a qualified maintenance technician in his maintenance task, (2) support formal training courses for the IDE, (3) support on-the-job training, and (4) provide adequate technical data for a technician self-train program. 2.2 DATA FORMAT. The IDE accepts 8-bit parallel, filtered radar data and status information from the Government furnished Digital Video Integrator and Processor (DVIP) and converts it into a bit serial asynchronous format with one start, one stop, and one parity bit per 8-bit byte. For each radial of data, an auxiliary block of information containing the DVIP status, azimuth position, antenna position, time of day, and date will be transmitted as shown in figure 2-1. 2.3 BLOCK DIAGRAM FUNCTIONING. 2.3.1 IDE Functioning. (See figures 2-2 and 10-19) 2.3.1.1 The IDE consists of an input buffer circuit card assembly (CCA), serial transmitter and serial receiver CCAs, a clock/display CCA, synchro converter and synchro output CCAs, two power supply CCAs, a battery charger assembly, and miscellaneous components on the front panel and connector panel. 2.1.3.2 Isolation between the radar and multiple user equipment is provided by optocouplers on the input buffer CCA. Every signal coming from the radar to the IDE is optically isolated for the WSR-74. The inputs from the WSR-57 are also optically isolated on the input buffer CCA except for antenna position. The antenna position inputs are three-wire synchro signals for antenna azimuth and eleva- tions. These synchro signals are transformer isolated and converted into digital form on the synchro converter CCA. The input buffer CCAs also provide optically isolated elevation and azimuth inhibit signals required by the WSR-74 radar. 2.3.1.3 The function of the asynchronous transmitted CCA is to serialize the 10, 8-bit wide, parallel data bits provided to its input via the data bus. The parallel inputs to the transmitter CCA include data and status information from the DVIP (both radars) and WSR-57 azimuth and elevation information provided via the synchro output CCA. Data transfer via the data bus is controlled by the transmitter CCA. The baud rate of the serial output is approximately 1.8 MHz. 2.3.1.4 The receiver CCA monitors the serial bit stream from any selected output line and provides parallel information to the front panel for readout of status information, and to a digital-to-analog (D/A) converter on the display/clock CCA for analog presentation of DVIP data on an oscilloscope. 2.3.1.5 The display/clock CCA provides two separate functions: provides time and data information to the serial transmitter CCA and latches data from the receiver CCA for display on the front panel. The clock/calendar function requires the use of a battery back-up system. A battery charger assembly located on the front panel assembly keeps the battery charged. 2.3.1.6 Redundant power supplies provide the dc voltages required for operation of the IDE. Each power supply is complete on a single CCA and supplies all four voltages required for system operation. These are +5 Vdc, +12 Vdc, and -12 Vdc and an isolated 5 Vdc for radar interface circuits. 2-1 -I °"l L l Hi 1- U__ < Q >- cr < X < CO or < t- LU < a n w LL. cr O \- CO ? _l LU < 1- co > < CO cr -I LU _i N X < LU < LU Q < < H LL. z 7* > O z Z cu III LU LU o S H h- z Z Z > H < < CO a. 2£§ z < x CO Q LU CO a w re ■o re cr CO CM O) < Q cr LU co Try~>r\ DRIVE Vcc PWM (SGI526) 'fb 'fb MOSFET POWER SWITCH -*- 'c OUTPUT RECTIFIER ~~ '6 - - - - T 5 DRIVE | Vcc PWM (SGI526) fb fb L-C FILTER FILTER/ REG. L-C FILTER + 5VDC 5A -I2VDC IA 5VDC I A ISOLATED Figure 2-3. Power Supply No. 1 and No. 2 CCA N1A2A1/A2, Block Diagram 2-5 2.3.4.5 The ±12 voltages are derived from auxiliary taps and rectifiers coming from the IDE system + 5 volt supply. They are regulated by a positive and negative three-terminal regulator IC. 2.3.4.6 The isolated +5 volt supply shares the line rectifiers and filters but is fully output-isolated from both the ac line and the IDE system. Again the isolation is obtained through isolation transformers for output, gate driver and current sample. 2.3.4.7 Each of the outputs has an indicator lamp on the front panel. 2.3.5 Synchro Converter CCA N1A2A3/A4 Functioning. (See figure 2-4) 2.3.5.1 The block diagram for the synchro converter CCA is shown in figure 2-4. As shown, the syn- chro converter CCA comprises a Scott T transformer, a quadrant selector circuit, sine and cosine multipliers, operational subtractor, error demodulator, VCO, threshold detector, integrator, and up- down counter. 2.3.5.2 Three-wire synchro angle data is presented to a Scott T transformer, which provides isolation from converter ground, and translates the synchro input data into two signals, one proportional to the sine of 9 and the other proportional to the cosine of G. The exact signal can be represented mathematically as a sine sinwt and a cos0 sinwt. Where w is the carrier frequency, this frequency will be removed by demodulation. 2.3.5.3 A quadrant selector circuit enables selection of the quadrant in which it lies, and automatical- ly sets the polarities of the sine0 and cos9 signal appropriately for computational significance. The sineG and cos9 outputs of the quadrant selector are then fed to the sine and cosine multipliers. 2.3.5.4 The sine and cosine multipliers are digitized by programmed, resistive networks. The transfer function of each of these networks is determined by a digital input which switches in proportioned resistors, so that the instantaneous value of the output is the product of the instantaneous value of the analog input and the sine or cosine of the digitally encoded angle 0. If the instantaneous value of the analog input to the sine multiplier is cosG and the digitally encoded "word" presented to the line multiplier is 0, the output is cosG sinO. Thus, the outputs of sine and cosine multipliers are cos6 and sinO and sinG cosO, respectively. These outputs are fed to an operational subtractor, so that the input to the demodulator is sinO cosO- cosG sinO = sin (G - 0). 2.3.5.5 The right-hand side of the trigonometric identity indicates that differencing-junction output represents a carrier frequency sine wave with an amplitude proportional to the sine of the difference between the angle to be digitized and (the angle stored in digital form in an up-down counter). 2.3.5.6 The demodulator is also presented with the reference voltage, which has been isolated from the reference source, and appropriately scaled by the reference isolation transformer. The output of the demodulator is at analog dc level, proportioned to sin (Q - 0). In other words, the analog dc level is proportional to the sine of the error between the actual angular position of the synchro and the digitally encoded angle 0, which is the output of the counter. Note that the small errors (G - 0) = G -0. This analog error signal is then fed to the circuit block labeled "error processor" and VCO. This circuit consists essentially of an analog integrator whose output (the time integral of the error) con- trols the frequency of a voltage-controlled oscillator. The "sense" of the error (0 too high, or too low) is determined by the polarity of (G - 0) and is used to generate a counter control signal, which determines whether the counter moves upward or downward with each successive clock pulse fed to it. The "sense" comparators also have a small deadband that locks out the pulses to prevent the synchro converter from from toggling when the error is less than the required resolution, i.e., less than 0.1°. The up-down counter, like any counter, is functionally an integrator — an incremental integrator, but nevertheless an integrator. Therefore, the tracking converter constitutes in itself a closed-loop ser- vomechanism with two lags. This is called a type II servo. 2-6 ) T o —i cc Oo CO CO LLI LU CC h- Z£i LU h- a CO o o > ) CO C/3 w ® CO z o CO o cc a > > > > uj X CC LU I C3 o o o CO CO CO ISI ISJ << CO OQ CM =3 OO d cj -j oo coco o u CO _l 'YYY > Hi' CO CO rsi —i < LU CM OJ CO CO M -I < LU E co O) co Q jc o _o CD < CO < < < O O <3) > C o o o c CO <* CN a> *- 3 CO CM CO CO CO CN CC 2-7 2.3.5.7 The 14 bit BCD angle stored in the up-down counter is the encoded synchro angle informa- tion that is provided to the output CCA. The synchro converter CCAs are identical and are used for both the azimuth and elevation synchro conversion. The 14-bit converter output is a pseudo BCD code in that the lower order digits are BCD and the high order digit is in fact quadrant information. The syn chro output CCA thus accepts the 14-bit word, level-shifts the lower order digits and through ROM look-up tables converts the quadrant information into the high order BCD digits required. The azimuth angle digits are then multiplexed to the data bus. 2.3.5.8 The Elevation 14-bit code goes through this same conversion to yield a pure BCD angle. However, the elevation angle goes through another set of ROMs, which shifts the numerical value to correct for both antenna 2.5 to 1 synchro ratio and to obtain plus and minus angles for elevations above and below horizontal. The elevation angle data is then applied to the IDE mux data bus. 2.3.6 Synchro Output CCA N1A2A5 Functioning. (See figure 2-5) 2.3.6.1 Figure 2-5 shows a block diagram of the synchro output board. It is divided into two sec- tions. One section is for the azimuth synchro information; the other section is for the antenna eleva- tion. Also, the isolated synchro reference transformer is contained in the board. 2.3.6.2 The function of the synchro output board is to provide a look-up table for mapping the digital- ly encoded (12 bits for 0° to 89.9° and 2 bits for quadrant) angle information into the normal (0° to 359.9°) angle format. 2.3.6.3 All the signal lines from the synchro converter board are level-translated and inverted through the FET bilateral switches. 2.3.6.4 In the azimuth section, the tenths and unit digit information from the synchro converter board are used directly to form the tenths and units digits of the final output angle. The tens digit and quadrant information, however, must first go through a loop-up table PROM to map into the hundreds and tens digits. 2.3.6.5 The basic operation is the same for the elevation section except there is a 2.5 to 1 gear ratio involved with the elevation synchro. Thus additional look-up tables are involved, and the outputs of these tables must be added together to form the correct BCD representation of the true elevation angle. 2.3.6.6 The final BCD outputs of both angle information are tied together through the tri-state buffers and form a data bus to the transmitter board. Strobes from the transmitter board determine when to latch the correct angle information into its bus. 2.3.7 DE Receiver CCA I\11A2A6 Functioning. (See figure 2-6) 2.3.7.1 Figure 2-6 shows a block diagram of the IDE serial receiver CCA. The main purpose of this board is to test/monitor the serial data by reconstructing and displaying on LEDs and oscilloscope. The receiver is an asynchronous system operated at 14.31818 MHz (8 times the input data rate). Syn- chronization with incoming data depends upon the detection of level transitions and the correct fram- ing of data bits (valid start bit, parity bit, 8-bit data, and stop bit). This is accomplished by the edge detecting circuit, the parity generator, and the framing logics. The divider counter and decoding circuit are used to generate strobe signals at the center of each data bit time to ensure noise free data latch. An 1 1-bit counter keeps track of the number of bits shifted into the serial-in-parallel-out (SIPO) shift registers, thus checking the framing of a data field (1 1 bits). When a correct framing of data field is recognized, the 8-bit data will be latched into the data latch. At the same time a DATA strobe will be generated to enable the data latch at the clock display board. 2.3.7.2 The sync byte decoder detects an FF in the 8-bit data. If an FF is detected, the serial data coming in will consist of auxiliary data bytes, and the auxiliary data byte counter will be enabled to count from to 9. Its BCD outputs are decoded by a BCD to decimal decoder to give 10 data strobe signals for each auxiliary data byte. These sequential data strobes are used by the clock and display board to latch the corresponding data bytes to the 7-segment displays. 2-8 + 5 AZIMUTH SYNCHRO CONVERSION SECTION AZSO TO AZS7 SWITCH CONT OUT n TRI- STATE BUFFER EG + 5 AZS8 TO AZ SI3 n SWITCH CONT IN OUT EL SO TO ELS7 n SWITCH CONT IN OUT EL SO TO - ELSI3 SWITCH CONT OUT J*l I / 8 » 8 / ^ D0 TO 07 LOOK UP OUT PROM TRI- STATE BUFFER EG I -¥-=-ii TABLE LOOK- UP PROM AL •AH ANTENNA ELEVATION SECTION TABLE LOOK- UP TABLE LOOK- UP PROM ADDER TRI STATE BUFFER I y-i) ISOLATED SYNCHRO REFERENCE TRI STATE BUFFER Rl O R2 ► REF I EL EH Figure 2-5. Synchro Output CCA N1A2A5, Block Diagram 2-9 — o X _J CO o z ft I M X £ 5 I < < UJ UJ »- H CO oo Q lo QC X 5 O (M 1- _l rO x=! sf CO o Q. o >- CO tr CD X § _J o a> cc to i- tr £ o? 00 +• o ^ 2-10 2.3.8 Clock/Display CCA N1A2A7 Functioning. (See figure 2-7) 2.3.8.1 The block diagram for the clock/display CCA is shown in figure 2 7. As shown, the board is functionally divided into two sections: the clock section and the display section. 2.3.8.2 The display section receives parallel data from the IDE receiver CCA. This data is multiplexed data continuing the DVIP video data and the auxiliary data and is gated into two sets of latches. The first set is used to latch the DVIP data, which is then fed to a D/A converter to provide an analog presentation of the video signal. The current source output of the DAC is converted into a voltage out- put by an operational amplifier whose output is fed to a transistor driver to drive the BNC output con- nector on the front panel. The other set of latches is used to latch the auxiliary data (time, day, status, azimuth and elevation). Only the desired information selected by the front panel monitor switch will be latched. This is done through a pair of data selector/multiplexers. The encoded monitor switch function selects the data strobe to clock the latches. The outputs of the latches will be used by display mounting board No. 1 , where they will be converted into 7-segment format. 2.3.8.3 The clock section provides the data and time DVIP data for the IDE. The time keeping func- tion is performed by a single integrated circuit clock chip. A crystal controlled oscillator and a clock divider provides the 60 Hz time base for the chip. Time and date outputs are 7-segment outputs with four digits, and they share the same output lines. Four 7-segment to BCD decoders are used to con- vert the output to BCD format before they are stored in latches. An oscillator/timer and a select logic circuit are used to externally multiplex the clock chip so that it will put out date and time information alternately at its output by controlling the calendar/snooze input of the clock. The select logic also pro- vides strobes to latch the BCD information into the latches. There are two sets of latches: one set is for storing the time information, and the -Other is for storing the date information. The tri-state outputs of these latches are tied together and buffered before they are routed to the data bus of the transmit- ter board. Data strobes from the transmitter board enable the latches to allow either the time or the date information to get onto the bus. Time and date settings of the clock are done by decoding the clock mode select switch signals from the front panel and with the activation of the FAST, SLOW, HOLD buttons (also on the front panel). The clock section also includes a power failure monitor which will detect a low battery voltage during power failure and indicate the condition by jamming invalid time information to the displays. 2.3.9 DE Transmitter CCA IM1A2A8 Functioning. (See figure 2-8) 2.3.9.1 A block diagram of the transmitter CCA is shown in figure 2-8. It is comprised of a 14.3 MHz crystal oscillator, a shift clock counter, 1 1-bit counter, auxiliary data byte counter, BCD to decimal decoder, various logics to generate clock signals (the DATA/AUX DATA detect circuit, one shot and flip-flop), tri-state buffers, parity generator, parallel-to-serial shift register, transistor arrays and an 8-to-1 multiplexer. 2.3.9.2 The crystal oscillator is divided by the shift clock counter to 1.79 MHz, which is the data rate at which serial data is to be transmitted. 2.3.9.3 Parallel 8-bit data (DVIP data and auxiliary data byte) from the input buffer board are con- verted into an 11 -bit serial format (one stop bit, 8-bit data, one odd parity bit, and one stop bit) and ouptut to different channels in the transmitter CCA. This conversion into serial bit stream requires the latching of data bytes at a time when all data bits are stable on the data bus. This timing is provided by the DATA READY from the radar for DVIP data, and the 1 1-bit counter for the auxiliary data. Clocking of DVIP data at the negative-going edge of DATA READY is desired. These two latching- enable signals are gated together at the OR gate and enable the shift clock counter to clock the shift registers through the one shot and flip-flop circuits. 2.3.9.4 The DATA/AUX DATA detect circuit is a retriggerable monostable multivibrator circuit which provides a low output at Q during DVIP data time. At the end of the DVIP data, it goes to HIGH and enables the 1 1-bit counter and the AUX DATA BYTE counter to count. The AUX DATA BYTE counter counts the number (10) of auxiliary data to be serialized. Its BCD c oded o utpu ts are decoded b ■ a BCD-to-decimal decoder which provides the 10 data stroke signals (DAT, SYN, AH, AL, EH, EL TH, TL, ST, and MO) to latch the appropriate data byte onto the bus. 2-11 DATA BUS DATA MONT H SYNC TIME HI EL HI AZ HI DAY STATUS TIME L P EL LP AZ LP TP FRONT PA NEL I STATUS SELECT | SWITCH ¥■ DVIP DATA MONITOR OUTPUT S0 SI S2 8 TO -I SELECTOR OUT u u S0 SI S2 8 TO -I SELECTOR] OUT ♦4. 8 LATCH CLK I -HiED— O LATCH CLK HIGH 'BYTE LATCH CLK LOW BYTE DISPLAY SECTION CLOCK SECTION TO CLOCK MODE/ SELECT SWITCH! + I2V 3.579 MHz F/F S BCD TO DECIMAL DECODER ^ TIME SET SWITCHES ON FRONT PANEL POWER FAILURE MONITOR I CLOCK DIVIDER d 60 Hz ODAYS /I0 HRS OSC TIME/DATE SELECT LOGIC CLK TIME LATCHES OE 1% CLK DATE LATCHES INVERTING BUFFER DATA BUS TO TRANSMITTER BOARD MO/ DA TH/ TL Figure 2-7. Clock/Display CCA N1A2A7, Block Diagram 2-12 in > ) > > 12 t |< >- IX |_l II |_l II l-J |H lO lo Ico l< l< Ilu Ilu Ik Ih l 15 tttttttttt „l SERIAL \~_ > OUTPUT *[ CHANNE i ft" CHANNEL ► OUTPUT MONITOR CHANNtL SELECT SIGNALS t L c ( c Ll Ll 3 BCD TO DECIMAL DECODER $ *K C 8 TO 1 MULTI- PLEXER '. : V f \ < »— ft >— • ENB R 1 1-BIT COUNTER h- o i ( CLK SHIFT/ LOAD S + SHIFT 7 REGISTERS P S i i Cft O u. h-. 5 R SHIFT CLOCK COUNTER > ' 1 '--L 1 + H <(- oo COCO £ *Hll cc •- If 3 < CO o h p oc PARITY GENERATOR E wj 14.3 MHZ OSC |z L— t ' l c > GO DATA /AUX DATA DETECT CO > •* Ik ^ TRI-STATE INVERTER BUFFERS ENB TRI-STATE INVERTER BUFFERS ENB t ) T >- p« CO V u ?*- 5 E o o CO CO < CM < < O O LU Q CO CNJ d) 3 2-13 2.3.9.5 The 8-bit data bytes to be serialized are input from the data bus. Additional tri-state buffers are gated to the bus to provide the sync byte (FF) and the unused most significant four bits (zeros) for the status byte. The four LSBs for the status byte are already on the data bus. 2.3.9.6 In order to generate an 1 1-bit pattern mentioned earlier, a start bit, an odd parity bit generated by the parity generator, and stop bits are inserted in their appropriate places in the shift registers. The serial output is then used to drive an array of transistor drivers to distribute the data to 8 different channels. All these channels can be monitored separately on a scope through an 8-to-1 multiplexer and select lines from the front panel switch. 2.3.10 Input Buffer CCA N1A2A9 Functioning. (See figure 2-9) 2.3.10.1 The block diagram for the input buffer CCA is shown in figure 2-9. As shown, the input buf- fer CCA comprises the opto isolator section, schmitt trigger inverters, tri-state data buffers and driver circuits. 2.3.10.2 Radar output signals to the input buffer board include system trigger, DVIP data (8 bits), data ready, and radar signals (time sample, range coverage, test level, and IF attenuation bypass mode) for both the WSR-74 and WSR-57 radars. In addition to these, the WSR-74 also provides the Azimuth BCD information and the antenna elevation BCD information. All these signals are optically isolated from the radar and are mulitplexed onto an 8-bit data bus through the use of tri-state buffers. Signals from the transmitter board, the data enable strobes, are used to enable the required data to be latched onto the data bus at the required time. 2.3.10.3 The system trigger input is first conditioned through a comparator before being isolated and buffered. It is used to provide a sync hronized trig ger output for external triggering. For the WSR-74 radar, it is also used to generate the AZ INHIBIT and ANT ELEV INHIBIT signals required by the radar. 2.4 DETAILED FUNCTIONING. 2.4.1 DE Power Supply No. 1 and No. 2 CCA N1A2A1/A2. (See figure 10-23) 2.4.1.1 The IDE power supply is a redundant system employing dual, independent off-line switching converters. Each power supply is complete on a single circuit card assembly and supplies all four voltages required for system operation. These are +5 Vdc, +12 Vdc, -12 Vdc and an isolated 5 Vdc for radar interface circuits. In addition, all output voltages are isolated from the ac line by transformers. Each of the two circuit cards has a full-wave bridge to recify the ac line and a L-C filter. This off line voltage is used on the primary side of two switching converters to be discussed later (see figure 2-10). 2.4.1.2 A small ac line transformer T7 supplies a separate dc voltage to each of the pulse width modulation (PWM) ICs (see figure 2-1 1). The secondary of transformer T7 has two windings. The out- put voltage of these windings is rectified and filtered. One output is grounded through the system ground, and the other is floating and isolated. 2.4.1.3 A switching converter with 5 Vdc and ±12 Vdc output voltages (see figure 2-12) is an off- line half bridge converter. The dc voltage is switched at 100 KHz rate in the primary winding of the transformer T4. Two power MOSFET transistors, Q4 and Q5, are connected in a half-bridg3 configura- tion, which acts as the power switch. The transistors' gates are driven by a low power transformer T6. The primary of the transformer is coupled to the output of the PWM IC. This IC has all the control needed for voltage regulations and current-limiting. The voltage regulation is achieved by sampling a scaled value of the output voltage. This voltage is fed to the input of the error amplifier of the IC. The result of this control loop is a pulse width modulation to the primary of the output transformer which maintains the output regulation. 2.4.1.4 The current-limiting is a separate input to the IC from 1:1 ratio transformer T5 used as a cur- rent sampling in the primary of the output transformer T4. The current limit is a foldback mode, which triggers the ICs slow start circuit. 2-14 > DVIP DATA 8 -f- DATA READY- STATUS 4 14 > AZ BCD INPUT ANT. ELEV. BCD INPUT *«— SYSTEM TRIGGER COMP- ARATOR 00 < Q UJ I or: -► DATA READY DATA BUS TT DATA SELECT ENABLE AZ 8 ELEV LATCH STROBES MONO- STABLE OPTO ISOLATOR ANjH INH I AZ. I _INH_| OUTPUT DRIVER SYS TRIG TO FRONT PANEL Figure 2-9. Input Buffer CCA N1A2A9, Block Diagram 2-15 c (0 o 0) cc 3 a c CM 3 6 6 2-16 > Hi' 00 le O o > {> < o o If) > o > o r- oo o. Q. C o O 3 • < > — i o N^ — 0. 0. — eg f^- < V J I 2-17 V) 0} u> ro "5 > 3 a 3 O u T3 > +1 T3 C (0 o > in .c > C o o O) c 5 QUADRANT A B U2 X 12 Y u; X 21 Y I I - cos e + cos e + SIN - sin e II I I - sin e + sin e -cos e + cos e III + cos e - cos e - sin e + sin e IV I + sin e - sin e + cos e - cos e Figure 2-15. Quadrant Selection and Output Polarities 2-23 32K vx cose — wv- 16 K vx cose — wv- 32K Vx SIN e — wv I6K -Vx SIN6 WV 9O°-0 I6K wv <» f wv O I6K t> ■+■ Vo where V x = K Sinwt (w - 2 tt 60 Hz) Figure 2-16. Operational Amplifier Summer Equivalent Circuit 2.4.2.5 Rq is actually a weighted resistor network, whose value is determined by the digital angle 0. The BCD coded angle switches in weighted resistors through the bilateral switches U2 through U5 and the FET switch Q1. Rgo°-0 ' s a ' so a weighted resistor network except it is controlled by 9O°-0 instead of 0. This is done by inverting the angle through inverters U1 1 and U12 and then adding it to 90 by adders U13 through U16. The B inputs to these adders are preset at 10 except U16, which is preset to 9 (most significant digit). With the carry inputs at zero, this is the BCD equivalent of adding 90. The output of these adders then switches in resistors through switches Q2 and U17 through U20. It can be easily shown that R = 1.28 M ohm = 90 14 22 K ohm R 90-0 = _ 1.28 90-0 M ohm 90 90-0 14.22 K ohm Thus the output voltage Vq is equal to v = R f r V xcos9 + v xsin9 + v xvis9 V xsin9 32K 32K 16K+16K R 16K + 16K R 9O-0 = V x R f 32K 90-0 25O-0> sin9 cos9 ,0+160; VxRf 32K v x Rf 32K 1 sin9 cos9 - cosO sinO sin (0-9) 2-24 2.4.2.6 Thus for = 0, the voltage ouptut Vq has to be zero. This output voltage is, therefore, used as an error signal voltage to correct for as in a close loop servomechanism action. The error voltage first goes through a noninverting amplifier U28A with a gain of about 5.5 I 1 -t- 68K I . After it is \ 14K / amplified, it goes into a demodulator/sign inverter consisting of U28B and U28D, Q4 and Q5. FET switches Q4 and Q5 are controlled by the reference voltage, which is derived from the synchro references R18R2. It is transformer isolated in the synchro output board and then voltage-limited by diodes inside the transformer block. U28D is an open-loop buffer amplifier to square up the reference signal and is then used to turn on or off Q4 and Q5 through diode CR6. When the reference voltage is positive, Q4 and Q5 are both off so that the output of U28B is the sum of the voltages through the noninverting amplifier gain and the inverting amplifier gain for the same error voltage. The result is an amplifier with a positive unity gain. When the reference is negative, Q4 and Q5 are ON so that the error voltage will go through the inverting amplifier with negative unity gain. 2.4.2.7 After demodulation, the error voltage is integrated by integrator U28C with adjustable offset control R73. This adjustment should be set at the factory or depot using a synchro standard and is not meant for field service. The time changing integrator output is then fed to a window detector (U29C and U29D) and a full wave rectifier (U29A and CR5), which, in turn, drives a voltage com- parator operational amplifer with hystersis built into it through feedbacks. The output of the com- parator acts as a voltage-controlled current source to charge C30 for the LM555 oscillator. The charg- ing rate of the capacitor determines the frequency of the oscillator; hence we have a voltage- controlled oscillator (VCO). 2.4.2.8 The window detector has its threshold levels set to ±70 mV by resistor dividers. The outputs of comparators U28D and U28C are gated together at U23A so that if the integrated absolute output voltage increases above 70 mV, the 555 is triggered, and its output will go high. U23D inverts the output delayed through the RC combination R53 and C40 to disable U32D so that the trigger input is only a small, negative-going pulse. When the trigger input is low, C30 is discharged through an inter- nal transistor. Now C30 will begin to charge up by the current source. When it reaches 2/3 of the 14-volt VCC (+ 7 V — (— 7 V) = 14 V), the threshold of 555 is reached; and it will reset its output to low, thereby enabling U32D again. If the error voltage is still within the window of detection, another trigger pulse will be generated. The capacitor will be discharged again, and the process repeats until the error voltage is close to zero. 2.4.2.9 The error correction is done by generating up-count and down-count pulses to the decode counter. U32C gating the output of 555 and its delayed inverted output will provide negative-going pulses for this purpose. These are, in turn, gated with the output of the window detector to determine whether it should be down-count or up-count pulse. U32A gates the pulses with the positive error to give down-count pulses while U32B gated them with negative error to give up-count pulses. 2.4.2.10 These clock pulses will clock counters U6, U7 and U8 cascaded together. U6 is the least significant digit (hundredth degree). The tens degree counter (U9) and quadrant counter (U25)) are clocked by other means. 2.4.2.11 U1A decodes "0" at the tens degree counter, and U1B decodes an "8." If the tens degree is when a borrow occurs at pin 13 of U8 due to a down-count pulse, U23B and U24C are disabled so that U9 will not be counted down. Instead, the BRW pulse will reset a JK flip-flop U27A and clock another JK flip-flop U27B to the "one" state (since both J and K inputs are "1" and its previous state is "0"). Thus Q1 is HIGH to enable the borrow pulse to go through U24D and will load U9 with an "8." 2.4.2.12 If U9 counts to "8" and a carry occurs at pin 1 2 of U8 due to an up-count pulse, U1B will disable U23C and U24B. The carry-pulse will clock U27A to "1" state and reset U27B. Q2 being HIGH will allow the carry pulse to clear U9 to "0" through U24A and U10F. 2.4.2.13 The quadrant counter will count up when the tens degree is an "8" and a carry pulse occurs at U8. This is done through U26B. It will count down if the tens degree is "0" and a borrow occurs at U8. U26C gates these two conditions to give the down-count pulse. 2-25 2.4.3 Synchro Output CCA N1A2A5. (See figure 10-25) 2.4.3.1 The tenths and unit azimuth information lines AZSO through AZS7 are used to control the bilateral switches U24 and U25. A low on the line (-7.5 V) will turn off the switch; and the output side of the switch is therefore high due to the pull-up resistors (4.7 K). A high on these lines ( + 7.5 V) will turn on the switch and connect the grounded inputs to the outputs. Thus, U24 and U25 invert the signal polarities and also provide a level translation to the signal. Outputs of U24 and U25 are fed to tri-state buffer U17, and they provide the tenths and unit BCD information of the azimuth angle. 2.4.3.2 The tens and quadrant azimuth information lines (AZS8 through AZS13) are used to control switches U23 and U22. A complemented AZS13 is obtained through U21A as an additional input. Thus, AZS13 is used as a chip select signal for selecting the lookup PROMs U19 and U18. In the I and II quadrants, AZS13 is low; thus U19 (PROM A) is selected. In the III and IV quadrants, U18 (PROM A) is selected. The output from the switches is used as address lines to read out the PROM contents. The contents for PROM A and B are given in table 2-1. The outputs of U18 and U19 are pulled up by resistors and fed to tri-state data latch U20. 2.4.3.3 Thus, U20 provides the first two digits (hundreds and tens) and U17 provides the last two digits (unit and tenths) of the azimuth angle. Their outputs are tied together to the input data bus of the transmitter board. Strobe AL from the transmitter board wil enable U17 while AH will enable U20. 2.4.3.4 The tenths and unit elevation information (ELSO through ELS7) is used to control switches U3 and U4 whose outputs become the address lines to PROM 1 (U10) and PROM 2 (U9). These two PROMs are essentially look-up tables which divide the tenths degree and the unit degree by 2.5 (see table 2-2). 2.4.3.5 The tenths and quadrants information (ELS8 through ELS13) is used to control switches U1 and U2, whose outputs become address lines to PROM A (U7) and PROM C (U6). ELS13 and its in- version through U21B select either PROM A or PROM C, depending on the quadrant. In quadrant I or II PROM A is selected. It serves as a look-up table for another address used to read another look-up table, PROM 3 (U8). PROM 3 is another divided by 2.5 look-up table for the number of tens degree. If the angle is in quadrant III or IV, PROM C is selected. The address data readout from PROM C would then be used to read PROM 3. PROM 3 again gives a value equal to 1 2.5 of the number of 10s degree for this angle. 2.4.3.6 U1 1 through U14 are BCD adders which put the tenths, unit, tens and hundreds degrees together. U14 adds a 0.03 degree to the resultant angle readout from the PROMs so that it will round off the angle to the tenths degree. U13 adds the tenths degrees from PROM 2 and PROM 1 together. U12 adds the unit degrees from PROM 2 and PROM 3 together, and U14 adds the tens degrees from PROM 3 and PROM C or A together. The hundreds degree is derived from PROM A or C. 2.4.3.7 The outputs of the adders then go into 2 tri-state inverting buffers U15 and U16. The strobe from the transmitter board EL and EH will enable either the HIGH byte or LOW byte to get on the data bus. 2.4.4 DE Receiver CCA N1A2A6. (See figure 10-26) 2.4.4.1 During power up, the RC charging time constant created by R1 and C22 serves as a reset signal to clear flip-flop U17B and preset counters U2 to 1010 and U13 to 1011. Resetting of U17B enables U10A (which clocks the shift registers U15 and 16 and 11-bit counter U13), and disables U7A which, in turn, enables U9A so that only U7C can clock U17B. 2.4.4.2 The shift register clock is derived from the clock divider counter U21, whose input clock is the 14.31818 MHz crystal controlled oscialltor (U4A, B, and U3A). U21 is cleared whenever there is a level transition in the input data stream. This is done by flip-flops U18A and U18B, which are clocked by opposite polarity input data. U19A gives an OR function so that either a low to high or a high to low transition in the data will clear U21 . Clearing of U21 will synchronize the input data with the in- ternal clock. 2-26 Table 2-1. Contents of PROM A and PROM B for Azimuth Angles QUADRANT I and II III and IV \. PROM ADDR \. A (AZS13 - 1) B (AZS13 = 0) DATA (HEX) REPRESENTING ANGLE DATA (HEX) REPRESENTING ANGLE i L 0° 1F FF 0° ET 180° 10° 1E FE 10° E6 190° o 20° 1D FD 20° DF 200° II 30° 1C FC 30° DE 210° CN 40° 1B FB 40° DD 220° CO N 50° 1A FA 50° DC 230° < 60° 19 F9 60° DB 240° 70° 18 F 8 70° DA 250° \ I 80° 17 F7 80° D9 260° I I 0° OF F6 90° D8 270° 10° 0E EF 100° D7 280° T 20° OD EE 110° D6 290° II 30° OC ED 120° CF 300° CN 40° OB EC 130° CE 310° C/> N 50° OA EB 140° CD 320° < 60° 09 EA 150° CC 330° 70° 08 E9 160° CB 340° 1 f 80° 07 E8 170° CA 350° OTHER FF FF ADDRESSES < ' \ ' 2.4.4.3 The input data bits are to be latched at the bit center time, which is about the 4th clock cy- cle (0.28 ixs) after the start of a level transition or start of a data bit. This clock is obtained by decoding a 3 from the outputs of U21, using gates U3D and U20A. Thus at the 3rd clock cycle, out- put of U20A will go low so that at the 4th cycle it will go high to give the clock edge for latching and shifting U15 and U16. This same clock is also used to clock the 11 -bit counter U13 which resets for every 1 1 bits (data frame length) of data shifted in. 2.4.4.4 At the end of the 1 1th bit count, if Qc (start bit position of U16) and Qa (stop bit position) of U15 are HIGH and LOW respectively, indicating a valid start bit and a stop bit are in their positions, both outputs of U7B and U6A will be LOW, and output of U10C HIGH to enable U7C. If these two bits do not meet the right polarities, nothing will happen; the data bits will be shifted in continuously until the conditions are met. 2-27 v> a> c < c _o > LU CO ■a c ro CM < O DC a. >^ o CO +■> c +■> C o o c\i C\l _a> i o o o o o O -si" 00 CM CD ■vj- < <~ LU < 1- < a - LL fc O^OOCNCOO^OOCNCO OOO'-'-CNCNCMOOOO LL -. LL ^~ ^ LL ^ o3> X CJ LU I r^COLL.LUOODO<0") OOQOOOOOO 00MOlLLUQUCQ< < LU X u_ujQ(JDQoor^ LL.LuOOooooi^co oooooooooo DC ■ LU DC i a o < / ° oooooooo o OOOOOOOO Ot-CMro^mcDr^oo oooooooo o oooooooo O'-cNcO'si-Lncor^co ^ n — ■* i ^ ~n «i ^ (J O L o IJ ^ * L do U •*" 2-28 2.4.4.5 U9B and U10B, which decode a 1 or 9 (6 cycles after the shift clock), clock U17B to latch the next data bit in and reset U13. If this next data bit is low at 2D, indicating the start bit of the next data frame, the above process will repeat. If the next data bit is HIGH, indicating the possibility of extra stop bits or end of DVIP data, U10A will be disabled by the 2Q output of U17B. Thus, the shifting of data is disabled. 2Q, however, will enable U7A. The condition at U7B is held as previously, thus forcing output of U7C to be HIGH. U9A is, therefore, enabled. Now, U17B will be clocked at 1.79 MHz by U9B until a valid start bit is again latched into U17B. 2.4.4.6 At the end of each 1 1th bit count, certain logic will perform a data framing check to ensure that the 1 1-bit pattern of data shifted in truly represents a data frame of the correct format. U1C, U6B and U10C already checked the start bit and stop bit polarities as mentioned previously. The parity of the middle 9 bits is continually being checked for ODD parity (HIGH is ODD). If the framing is cor- rect at the 1 1th bit count, U9D will give a data strobe DATA/AUX DATA at its output. If parity is not odd at the end of the 1 1th bit count, an ERROR will be decoded by U9C. 2.4.4.7 U30 checks the 8-bit data for sync byte (FF). U20C further verifies the sync byte by gating in the start bit and, if valid, will be clocked by the shift clock to reset the auxiliary byte counter U2. Subsequent shift clocks then clock U2 to keep track of auxiliary data bytes until the count of 12 is reached, at which time U6C decodes the two most significant bits to disable U2. During auxiliary data time (i.e., before U2 counts to 1100), U6C will give a HIGH output to U10D, which, in turn, disables U6B. During other times, U6B is enabled, and any valid data frame will indicate a valid DVIP data. Thus, U6B will provide the strobe DATA for DVIP data only. This signal is used by the clock display CCA. When U2 is active, its outputs will be decoded by U5 to provide the appropriate data strobes for the auxiliary data. The input to the d ecode r is enabl e d only fo r valid data frames b y OR gates U 8A thro ugh U 8D. These data strobes are DAY, MONTH, STATUS, TIME LO, TIME HI, EL LO, EL HI, AZ LO, AZ HI and SYNC. Together with DATA, they are used by the clock display CCA to latch the cor- rect information for display and monitoring purposes. 2.4.5 Clock/Display CCA N1A2A7. (See figure 10-27) 2.4.5.1 The multip le xed data bus. (DO through D7) from the re c eiver b oard is demult i plexed with the data strobes (DATA, DAY, STATUS, TIME LO, TIME HI, EL LO, EL HI, AZ LO, AZ HI, SYNC, MONTH) and stored in latches. U3 and U4 are Hex D-type flip-flops used to latch the DVIP data. The digital data is converted by a digital-to-analog converter (u5) into an analog presentation of the radar video for scope monitoring. U28 is an operational amplifier which converts the current output of U5 into a voltage output. Q1 is a transistor driver used to drive the scope monitor output. 2.4.5.2 U1 and U2 are octal D-type latches used to latch the auxiliary data bytes for front panel monitoring. Only one word (two bytes) can be monitored at a time on the four 7-segment displays. Selection of the word to be monitored is done by the data selector/multiplexers U7 and U6. The select lines to the selectors come from th e encode d thr ee-wi r e signa ls of the fron t panel M ONIT OR switc h. Thus, only on e pair o f da ta strob es (MONTH and DAY, SYNC and STATUS, TIME HI and TIME LO, EL HI and EL LO, AZ HI and AZ LO) is allowed to go through to latch U1 and U2. 2.4.5.3 During the sync byte time, the SYNC strobe is also used to clear U3 and U4 so that the DVIP data at the monitor output will be zero during the auxiliary data time. 2.4.5.4 The outputs of U2 represent the most significant byte (HIGH BYTE), and the output of U1 represent the least significant byte (LOW BYTE) of the displayed word. These outputs are used by the display mounting board No. 1. 2.4.5.5 U13 is the single chip clock/calendar. Its time base is derived from the 3.579 MHz crystal oscillator and the clock divider U9, which divides it to 60 Hz. 2.4.5.6 The 7-segment outputs of U13 are open-drain outputs so they require pull-down resistors (100k) to convert them to voltage level outputs. U14, U15, U16 and U18 are 7 segment-to-BCD con- verters which convert the clock outputs to four digit BCD representation. U16 decodes the 10s digit of hours and days; U15 the units digit; U14 the 10s digit of minutes or months; U18 the units digit. The clock is preselected and wired to display a 24-hours clock. 2-29 2.4.5.7 Since the clock chip does not multiplex its outputs between data and time information, a 555 timer chip (U17) is used to externally multiplex the clock outputs. It is set up at approximately 3 KHz, determined by R42, R43 and C40. It will output approximately a 7 /*s pulse for every 300 /*s. These pulses will clock a D flip-flop (U8A) in a divide-by-2 mode so that its Q output will select calendar or time information alternately from the clock chip. A HIGH from Q will force output of OR gate U12A HIGH, thus selecting calendar output from the clock while a LOW at Q will select time, provided that the other input to U12A is LOW. 2.4.5.8 In order to be able to retrieve the DATA and TIME information at any time, two sets of latches are used to store this information. U26 and U24 are used to store HOUR and MINS, respec- tively, while U27 and U25 are used to store the DAY and MONTH information. The inputs to U24 and U25 are wired together as are U26 and U27. When the Q output of U8A is high, calendar is selected, and U11B is inhibited so the clock from U17 cannot go through. On the other hand, Q of U8A is LOW, so U1 1A is enabled; and the clock from U17 can then latch the data information from the decoders to the D-type latches U25 and U27. When Q output of U8A goes LOW at the next stage, the reverse will happen and the time information will be latched into U24 and U26. 2.4.5.9 Setting of time and date can be done through the front panel switches. A four CLOCK CON- TROL position rotary switch on the front panel controls the mode of the clock chip. This is done by encoding the switch positions with a pair of signals (S1 and S2). The encoded switch positions are then decoded by a BCD-to-decimal decoder U10. Only 3 of the 10 outputs are used on U10, and only one will be HIGH at one time. The 1 and 3 outputs are wired-OR together through diodes CR5 and CR6 and pulled to ground with R7. They correspond to the TIME and SEC/HOLD switch positions. At these switch positions, U8A will be reset by the junction of the two outputs above. This will inhibit the clocking of the MONTH/DAY latches while enabling HOUR/MIN latches to be updated. In addition, in the SEC/HOLD position, the 3 outputs will select the clock chip to put out minute-second informa- tion to the outputs. The 2 output corresponds to the DATE position. At this position, it will set U8A to disable the clocking of HOUR/MIN latches while enabling the MONTH/DAY latches. At the same time it also selects the clock mode to display calendar information through the OR gate U12A. 2.4.5.10 The clock chip is powered by the 12V bus and a back up battery supply through redundant diodes CR9 and CR10. The battery voltage (nominal 10.8V) is being monitored continuously at the negative input to the comparator U29. A reference voltage of 6.2 V is set up at the noninverting input through R41 and CR1 1 . Since a voltage divider (R1 5 and R40) is implemented at the inverting inputs if R15 +R40 the battery voltage drops below 9.1 volts \6.2 V x R40 J the noninverting input becomes more positive than the inverting input, and the output of U29 will go HIGH to set flip-flop U8B. The HIGH output at Q will then enable the invert control to the 7 segment-to-BCD decoders. The inverted 7 segment information is read as invalid input by the decoders, whose outputs are tri-state. U20A and U20B decode all HIGH (tri-state actually) conditions at the 1st and 3rd digits; because of the exclusive OR gate U19 and U21, the inputs to the latches are the 1st and the 3rd digit positions which are all LOWs. On the other hand, the outputs from U18 and U15 go directly to the latches and all will look like HIGHs. The low battery condition is then indicated by an "OFOF" displayed on the 7-segment displays. 2.4.5.11 The clock chip itself has a power failure indicator by flashing its on segments simultaneously at 1 Hz rate. Since the clock has back-up battery supply, this indication will occur if power failure causes the battery to drop below 9.1V or if the clock display board has been unplugged temporarily. In either case, when power resumes, the display will be flashing between OFOF (low battery indica- tion) and 8888 (blanking displayed inverted by INCOT of the 7-segment to BCD converters) at a 1 Hz rate. 2.4.5.12 Note that power failure indication is different from the low battery voltage indication. Both conditions can be cleared by setting the time and day. 2-30 2.4.6 DE Transmitter CCA N1A2A8. (See figure 10 -28) 2.4.6.1 The DATA READY signal is provided by the radar for clocking the DVIP data onto the data bus. Its timing is shown in figure 2 17. ISince clocking in the negative-going transition is preferred by the specification (bit center time). I Besides clocking parallel DVIP data in, it is used to clock the retrig gerable monostable multivibrator U20A at the inverted input 1A. The time constant of U20A is deter- mined by R40 and C32 (about 18 / > o > in > o 2 E re re c re Q > Q CM 0) w 3 UJ h- Q. >- o < UJ < 2-32 2.4.6.10 The serial bit stream is buffered by U11C into two open collector drivers, Q1 and Q2, which invert the signal. They, in turn, switch 8 pairs of push-pull driver amplifiers (contained in U1 through U4) in order to drive 8 separate output channels at 75 ohms impedance (OUT 1 through OUT 8). 2.4.6.11 Each output channel can be monitored throught the 8-to-1 multiplexer U8. Select lines A, B and C come from the front panel channel select switch to select which channel is to be monitored. U9 is a buffer amplifier which provides the monitor output to the receiver CCA. 2.4.7 Input Buffer CCA N1A2A9. (See figure 10-29) 2.4.7.1 Table 2-1 lists all radar signal outputs to the IDE and indicates whether the true state (logical "1") of the data bit is high or low. All outputs are applicable to both WSR-74 and WSR-57 radars with the exception of azimuth and elevation information. Azimuth and antenna elevation information for the WSR-57 are provided by three-wire synchro signals and the synchro reference signals. 2.4.7.2 U1, U2 and U18 through U37 are Hewlett-Packard HCPL-2531 optical isolators. (See detail "A" in schematic.) The radar outputs are all open collector outputs. An isolated 5 V supply in the IDE is used to pull up the open collectors through 300 ohm resistors and the input diode of the optical isolator. This arrangement completely isolates the IDE from the radar. The output of each optical isolator is also an open collector circuit requiring pull-up resistors (5.6K) connected to the IDEs +5 V supply. 2.4.7.3 A typical input isolator stage is shown in figure 2-18. The outputs of the optical isolators are all buffered by schmitt trigger inverters (U11-U17) to refine the logic levels of the signals. The DVIP data and several of the status signals are of opposite logic levels for the two types of radars. This is accommodated for by using inverting or noninverting buffers (U8 = 54LS244 for WSR-74 or U8 = 54LS240 for WSR-57) to gate the DVIP data onto the data bus while the difference in status signal polarities is accommodated for by preset jumper options (E5 through E16). Jumper positions for the two types of radar are shown in Paragraph 9.5.3 of Section 9). 2.4.7.4 The system trigger input is fed to voltage comparator U38, powered by the isolated 5V supply. The input is terminated in 75 ohms, (R4). R6 and R5 attenuate the level of the input signal, which can be between and 40 V. R8 and R16 set the reference for the threshold of logic 1 state and is adjustable through R16. The conditioned system trigger signal is then optically isolated and buffered before it is used for the transmitter board and as a scope trigger. Q1 is an output driver for the external trigger at the front panel. 2.4.7.5 The system trigger signal at U12, pin 12 is also used to generate the azimuth inhibit and antenna elevation inhibit signals required by the WSR-74 radar. This is accomplished by the monostable multivibrator U4. The system trigger will trigger U4 to give 6 ^s pulse s (deter mine d by R14 a nd C4) at its ouptut. The negative-going pulses at Q will be used to provide EL INH and AZ IN- HIBIT signals through the opto isolator U2 and buffer inverters U3A, B and C. The positive pulses at the Q output are used to latch the AZ and ANT ELEV information at U6, U9, U10 and U7. 2.4.7.6 U5, U8, U6, U9, U10 and U7 are tri-state buffers, whose outputs are all wired together. They are used to latch the related groups of signals (DVIP data, status information, azimuth BCDs and antenna elevation BCDs) onto the data bus. Since only four status bits are provided, they are latched onto the least significant bits of the data bus. Both the AZ BCD and elevation BCD information require two buffers, one for the hundreds and tens BCDs and the other for the units and tenths BCDs. To eliminate bus conflict, only one buffer would be enabled at a time. This is done by the data strobes provided by the transmitter board. These signals include DA, ST, AL, AH, EL and EH. 2-33 > in-* + CO o m o J2 3 a c to u '5. 00 I 3 2-34 > i < < SECTION 3. OPERATION 3.2 CONTROL AND INDICATORS. - All operator controls and indicators for the IDE are described in table 3-1 and illustrated in figure 3-1. 3.3 OPERATING PROCEDURES. 3.3.1 Connections. 3.3.2 General. — The function of the IDE is to accept digital radar weather data, analog or digital radar azimuth and elevation data and radar status data; and to output this data, along with time and date data generated within the IDE, in serial form on eight output channels. An onboard decoder reconstructs the original data from any one of the eight output channels determined by the channel selection switch, so that the performance of the equipment may be checked at any time. A check of all the parameters (i.e., azimuth, etc.) on a single channel indicates the processing performance of the IDE. Since all eight channel outputs are indentical, only one parameter need be checked on each chan- nel to demonstrate that all eight channels are functional. 3.3.2.1 Inputs. a. Line cord plugged into 115V, 60 Hz outlet. b. Coax cable connected to trigger input plug. c. Multi-pin connector to WSR74 plug or multi-pin connector to WSR57 plug and to synchro plug. 3.3.2.2 Outputs. From one to eight output coax cables connected to output channel plugs 1 through 8. 3.3.3 Equipment Turn-On. a. Note that the battery charger lamp is on.* b. Set the power switch ON. 1. POWER indication lamp is on.* 2. Two indicating fuse lamps are off. (System will operate with one lamp on. Maintenance is required.) 3. All eight power supply voltage status indicator lamps are on. (System will operate if one of each type (i.e., +12V) indicator lamp is on. Maintenance is required.) 4. STATUS display — all four characters light with any digit. System may be functional without. Maintenance is required. 3-1 Table 3-1. IDE Controls and Indicators INDEX NO. CONTROL/INDICATOR FUNCTION 1 POWER ON/OFF switch Applies 1 1 5V, 60 Hz power to the power supplies. 2 POWER lamp (amber) Indicates 1 1 5V power is applied to the power supplies. 3 Indicating fuse 2 Lights amber when fuse to # 2 power supply is blown. 4 Indicating fuse 1 Lights amber when fuse to # 1 power supply is blown. 5 BATTERY CHARGER lamp Indicates battery charger is operating. Lights (green) when IDE line cord is connected to 115V, 60 Hz outlet. 6, 7, 8, 9 POWER SUPPLY #2 Each lamp indicates the associated voltage is output voltage indicators being applied to the circuits from power supply (green lamps) #1. 10, 1 1, 12, 13 POWER SUPPLY # 1 Each lamp indicates the associated voltage is output voltage indicators being applied to the circuits from power supply (green lamps) #1. 14 CHANNEL MONITOR Selects one of the eight output channels for selector switch decoding and display on the STATUS indicator. 15 CLOCK CONTROL Used to set clock functions (seconds, minutes, selector switch hours, day and month). 16 STATUS SELECT Selects any of the five status functions selector switch (decoded from the selected output channel) and routes it to the STATUS display. 17 SLOW/SET pushbutton Used in setting the clock functions as a fine (slow) control. 18 FAST/SET pushbutton Used in setting the clock functions as a fine (slow) control. 19 STATUS indicator The indicator is a four-character numeric display. Decimal points and colons appear ap- propriately between the characters. 3-2 > ^ f en 3 — < — V) > 1 UJ a >- k- UJ ^_ CO ►- cr LU a _j o CO 3 X £ o t- Ul UJ CO CO V. ~n " a ■» ^ 3 2 c CO Jfl O c o o c 0) E a "5 a- UJ c o ♦3 (A Q c ,o «3 JO O (A CO a> 3 3-3 c. Clock Functions 1. Set the CLOCK CONTROL switch OFF. 2. Set the STATUS SELECT switch to TIME. If the STATUS display is flashing 0000, OFOF, then the time, data and second functions must be set. If the incorrect time is displayed, the time and second functions must be set. If the correct time is displayed, continue to step 3. 3. Set the STATUS SELECT switch to MO/DY. If the incorrect month (left two characters) or incorrect day (right two characters) appears, the MO/DY functions must be set. If the correct month number appears in the left two characters and the correct day number appears in the right two characters, continue to step 'd' below. d. Processing Checks 1 . Set the STATUS SELECT switch to AZ. A steady, increasing or decreasing four digits number (between 000.0 and 359.9) will appear, with the decimal point in front of the right most digit. 2. Set the STATUS SELECT switch to ELEV. A steady or changing four-digit number (from 350.0 to 065.0) will appear, with the decimal point in front of the last digit. 3. Set the STATUS SELECT switch to SYNC STATUS. The left two digits are always F F. The right center digit is always 0. The last digit may be any number from to 9 or any letter from A to F. 3.3.4 Clock Set. 3.3.4.1 Time Set. a. Set the STATUS SELECT switch to TIME. b. Set the CLOCK CONTROL switch to HOLD. c. Press the HOLD/RESET SEC button until a local time standard just reaches 00 seconds (start a new minute) and immediately release the button. This synchronizes the IDE clock's seconds function with the local time standard. d. Set the CLOCK CONTROL switch to TIME. The left two display digits indicate the hour based on a 24-hour day. The right two digits indicate the minutes. e. Press the FAST/SET button to advance the hours to the correct hour of the day. Do not let the minute function pass the present minutes required, since the hour function will increase by one every time the minute function passes 59. f. Press the SLOW/SET button to advance the minutes to the correct minute required. 3.3.4.2 Month Day Set. a. Set the STATUS SELECT switch to MO/DY. b. Set the CLOCK CONTROL switch to MO/DY. 3-4 c. Press the FAST/SET switch until the correct month number appears in the left two digits. Do not let the day function pass the present day required since the month function will increase one month every time the day function passes 28, 30, or 31. d. Press the SLOW/SET button until the correct day number appears in the right two digits. e. Set the CLOCK CONTROL switch OFF. 3.3.5 Miscellaneous. - The IDE clock has a battery backup feature which allows for a power failure for up to a maximum of two hours without losing the correct time or date. When power is reapplied, the correct time will be displayed when the STATUS SELECT switch is set to TIME. In the event of a power failure, it is not necessary to make any switch changes to the IDE. When power is restored, the IDE will automatically function correctly. 3-5/3-6 SECTION 4. STANDARDS AND TOLERANCES 4.1 INTRODUCTION. - This section provides a list of essential equipment parameters, the standard value assigned to each parameter, and the tolerances/limits imposed on each standard as shown below. PARAGRAPH PARAMETER REFERENCE STANDARD TOLERANCE/LIMIT Ac line power 120 Vrms 110 - 130 Vrms + 1 2V supply 6.2 12.0V 10.70 - 11.90V - 12V supply 6.2 -12.0V -10.70 - 11.90V + 5V supply 6.2 5.0V 4.75 - 5.25V + 5V isolated supply 6.2 5.0V 4.75 - 5.25V Battery charger output 6.2 11.4V 11.0 - 14.0V (with no battery) Digital clock 6.2 16.66667 ms ±0.16 lis Clock period Transmit/receive clock 6.2 14.318182 MHz ±720 Hz AZ INH/EL IHH pulse 6.2 6.0 /*s ±0.1 /is 4-1/4-2 ^ SECTION 5. PERIODIC MAINTENANCE 5.1 PERFORMANCE CHECKS. See table 5-1. 5.2 OTHER MAINTENANCE TASKS. See table 5-2. Table 5-1. Performance Checks PERFORMANCE CHECK REFERENCE PARAGRAPH STANDARDS & TOLERANCES MAINTENANCE PROCEDURES Power Supply Voltages STATUS display 4.1 6.2 Table 5-2. Other Maintenance Tasks PERFORMANCE CHECK REFERENCE PARAGRAPH STANDARDS & TOLERANCES MAINTENANCE PROCEDURES Routine Inspection Air Filter Cleaning and Inspection 6.3.1 6.3.2 5-1/5-2 SECTION 6. MAINTENANCE PROCEDURES 6.1 GENERAL. The preventive maintenance procedures contained in this section should be used with the information provided in Sections 4 and 5. The first step in testing the equipment is an inspec- tion of the equipment with power off. Whether or not all or a portion of the trouble may be found in this manner, it is always a good practice to make visual inspection and basic continuity checks on equipment whose condition is unknown. These are the major elements of inspection. (1) Electrical connection. (2) Mechanical joints and linkages. (3) Unauthorized or nonstandard repairs or modifications. (4) Damaged parts. Check for corrosion, breakage, burning, etc. (5) Cleanliness and finish. The second step is performance testing and the final step is adjustments. Troubleshooting information is contained in Section 7. Performance test procedures in this section provide data which is represent- ative of a correctly operating system. Indications obtained from the equipment under test are com- pared with the corresponding indications contained in this section to evaluate the equipment and to assist in troubleshooting. Maintenance records should be kept and as much data as possible recorded to assist in future repairs. List abnormal indications and describe what was done to correct the fault. Records should include actual measurements taken before and after a repair so that a work history is accumulated. This practice will aid in finding potential troubles before they start interferring with the performance of the equipment. 6.2 PERFORMANCE TESTS. — The IDE makes use of status indicators and built-in-test equipment (BITE) to facilitate performance testing. Performance tests for the IDE are given in table 6-1. These tests are performed with the IDE connected in normal system configuration. 6.3 OTHER MAINTENANCE TASK PROCEDURES. - The following paragraphs describe how to per- form the maintenance checks listed in table 5-2. 6.3.1 Routine Inspection. — Perform the following procedure for routine inspection. a. Check wiring for kinked, frayed, loose, or burned wires. b. Ensure cable connectors are free from corrosion and are properly secured. c. Check components for evidence of overheating, breakage, corrosion, or loose connections. d. Check capacitors and transformers for leaks, bulges, or loose connections. e. Inspect switch contacts for pits and arcing. f. Ensure that all circuit card assemblies are firmly sealed in mating connections. 6-1 Table 6-1. Isolation Distribution Equipment Performance Tests POINT OF MEASUREMENT PROCEDURE PERFORMANCE STANDARD STEP INDICATOR/TEST POINT LOCATED ON 1 Connect the IDE to a 115 VAC, 60 Hz outlet. BATTERY CHARGER lamp Front panel Lit 2 Set POWER ON/OFF switch to ON. POWER indicator Front panel Lit 3 Set POWER ON/OFF switch to OFF. Remove fuse from POWER 1 fuseholder and reinstall the fuseholder with blown fuse. POWER 1 fuseholder Front Panel N/A 4 Set POWER ON/OFF switch to ON. POWER 1 fuseholder Front panel Lit 5 Set POWER ON/OFF switch to OFF. Remove fuse from POWER 2 fuseholder and reinstall the fuseholder with blown fuse. POWER 1/POWER 2 fuse- holders Front panel N/A 6 Set POWER ON/OFF switch to ON. POWER 2 fuseholder Front panel Lit 7 Set POWER ON/OFF switch to OFF. Reinstall good fuse in POWER 1 fuseholder. Disable power supply No. 2 by removing the 1/2A fuse from POWER 2 fuseholder. POWER 1/POWER 2 fuse- holders Front panel N/A 8 Set POWER ON/OFF switch to ON. Front panel N/A 9 Measure the output voltages of power supply No. 1 as indicated below. Connect the DVM bet- ween the test points indicated. Refer to figure 10-16 for loca- tion of test points on the power supply No. 1 CCA. -12V supply TP3( + ) and TP1(-) Power supply No. 1 CCA -10.70V to -11.90V + 12V supply TP4( + ) and TP1(-) Power supply No 1 CCA + 10.70V to + 11.90V + 5V supply TP2( + ) and TP1(-) Power supply No. 1 CCA + 4.75V to + 5.25V Isolated +5V supply TP5( + ) and TP7(-) Power supply No. 1 CCA + 4.75V to + 5.25V 6-2 Table 6-1. Isolation Distribution Equipment Performance Tests (Continued) POINT OF MEASUREMENT PROCEDURE PERFORMANCE STANDARD STEP INDICATOR/TEST POINT LOCATED ON 10 Set POWER ON/OFF switch to OFF. Reinstall fuse in POWER 2 fuseholder. Disable power supply No. 1 by removing the 1/2A fuse from POWER 2 fuseholder. POWER 1/POWER 2 fuse- holders Front panel N/A 11 Set POWER ON/OFF switch to ON. Front panel N/A 12 Measure the output voltages of power supply No. 2 as indicated below. Connect the DVM bet- ween the test points indicated. Refer to figure 10-16 for loca- tion of test points on the power supply No. 2 CCA. -12V supply TP3( + ) and TP1(-) Power supply No. 2 CCA -10.70V to -11.90V + 12V supply TP4( + ) and TP1(-) Power supply No. 2 CCA + 10.70V to + 11.90V + 5V supply TP2( + ) and TP1(-) Power supply No. 2 CCA + 4.75V to + 5.25V Isolated +5V supply TP5( + ) and TP1(-) Power supply No. 2 CCA + 4.75V to + 5.25V 13 Set POWER ON/OFF switch to OFF. Reinstall fuse in POWER 1 fuseholder. Front panel N/A 14 Set the POWER ON/OFF switch to ON. POWER SUPPLY 1 and 2 -12V lamps Front panel Lit POWER SUPPLY 1 and 2 + 12V lamps Front panel Lit POWER SUPPLY 1 and 2 + 5V lamps Front panel Lit POWER SUPPLY 1 and 2 ISOLATED +5V lamps Front panel Lit 6-3 Table 6-1. Isolation Distribution Equipment Performance Tests (Continued) POINT OF MEASUREMENT PERFORMANCE STEP PROCEDURE INDICATOR/TEST POINT LOCATED ON STANDARD 15 Set STATUS SELECT switch and CLOCK CONTROL switch to TIME. Depress the FAST/SET pushbutton. STATUS display Front panel All seven seg- ments in all characters of STATUS display illuminate and indicate correct time. 16 Set STATUS SELECT switch to MO/DAY and CLOCK CON- TROL switch to DATE. STATUS display Front panel Correct month and day indi- cated. 17 Set STATUS SELECT switch to AZ. STATUS display Front panel A steady, in- creasing or decreasing four- digit number (between 000.0 and 359.9) will appear with the decimal point in front of the right-most digit. 18 Set STATUS SELECT switch to ELEV. STATUS display Front panel A steady or changing four- digit number (from 350.0 to 060.0) will ap- pear, with the decimal point in front of the right-most digit. 19 Set STATUS SELECT switch to SYNC STATUS. STATUS display Front panel The left two digits of the display should be FF, the right- center digit 0, and the right- most digit may be any number from to 9 or any letter from A to F 6-4 g. Visually inspect AC power cords, plugs, and connectors to ensure that they free of cracks, cuts, loose connections, and safety hazards. h. Visually check all coaxial cables for loose connections and damage. 6.3.2 Air Filter Cleaning and Inspection. a. Open the panel to the card rack assembly to gain access to the air filter. b. Using a straight slot screwdriver, remove filter clamps on backside of panel. c. Lift out filter. d. Hold filter in front of bright light and observe whether light is visible. If not visible, replace with a new filter. Otherwise replace old filter. e. Using a straight slot screwdriver, reinstall filter clamps. f. Close panel of the card rack assembly. 6.4 SPECIAL MAINTENANCE PROCEDURES. - No special maintenance procedures are required. 6-5/6-6 SECTION 7. CORRECTIVE MAINTENANCE 7.1 INTRODUCTION. — This section contains the information necessary to perform corrective maintenance and overhaul procedures. Table 7-1 provides a listing of test equipment required to per- form the procedures provided herein. Table 7-2 contains the symptoms and index to troubleshooting. This section should be used in conjunction with the schematics and diagrams in Section 10. 7.2 SEMICONDUCTOR DEVICES/INTEGRATED CIRCUITS PRECAUTIONS. - CAUTION: Semiconductor devices are delicate. There are three principal abnormalities that are most harmful to semiconductors. These are (1) excessive voltage or current, (2) excessive temperature, and (3) ex- cessive shock. Semiconductors are unusually susceptible to static discharges because of their low operating voltages and the construction of the semiconductor junction. The following are examples of various abnormalities encountered in practice, but it is important that personnel who work with semiconductors be proficient enough to realize the semiconductor's capabilities and limitations, so that they can do maintenance with confidence. 7.2.1 Static discharges can be avoided by eliminating all external connections to the circuit that can provide a ground path. Leads which have a high capacity to ground, such as AC power or antenna transmission lines and the elements of soldering irons, should not be touched to semiconductor cir- cuits while the circuits are grounded. First discharge the lines and then connect them. The human body can also accumulate sufficient potential to discharge a damaging spark. 7.2.2 Capacitors connected in the circuit should not be touched with external leads and should not be connected or disconnected while they still retain a charge. But both capacitors and semiconductors can be damaged by discharging the capacitor through a direct shunt. The capacitor should be allowed to discharge normally through the circuit RC time constant or be discharged through an external bleeder. Nothing in a semiconductor circuit should be connected or disconnected with power applied. 7.2.3 Defective circuit components can provide excessive capacitive or resistive leakage currents that damage semiconductors either directly or because of bias changes that increase power consumption. For example, any coupling capacitor is capable of this if it should leak and provide abnormal forward bias to the following semiconductor. 7.2.4 Always use some form of heat sink (usually pliers) between the semiconductor body and the soldering iron. The tendency is to use irons of too high a wattage rating (stay below 50 watts). The use of soldering guns should be avoided. The best soldering tool is one with replaceable tips of various wattages plus the unsoldering devices and vacuum tools for removal of excess solder. Do not unsolder a component know to be bad if it can be cut loose from the circuit. Then, only the leads need un- soldering and this can be done quickly. If the leads are very short, cut the body of the component with side cutters. 7.2.5 Cutting semiconductor leads with a cutter causes an appreciable shock wave to be transmitted to the junction; this shock can cause rupture. The lead to be cut should be held with pliers between the body of the semiconductor and the place of cutting to absorb the shock. Similar damage may be caused if the transistor is dropped. Striking a transistor case in search of intermittents is poor practice. Another cause of mechanical damage is overtightening of stud-mounted semiconductors. The mount should be mechanically secure, but the electrical efficiency of the joint is a matter of cleanliness in the joining surfaces. Never strike a circuit board against the bench to shake off solder. 7-1 7.2.6 Ohmmeters used for continuity checks should never be used on the lowest range or on the highest. Only general warnings can be given in this instruction book; no ohmmeter should ever be used with semiconductors until its instruction book has been studied. An ohmmeter has doubtful value as a service tool for semiconductors out of the circuit. Use a transistor tester with at least the capability to test gain and capacitive leakage. 7.2.7 Apply operating voltage of incorrect polarity can ruin semiconductors. A simple way to ensure proper polarity is to take a spare diode and connect it to the circuit so that it will block the supply if it is connected in reverse. This diode can be tack-soldered to the circuit board input or the incoming lead from the power supply. The diode should, of course, be capable of handling the voltage and current requirements of the circuit plus the surges of the supply. 7.3 CIRCUIT BOARD COMPONENT REPLACEMENT. -- Some of the circuit boards in the system have been coated with a polyurethane compound which prevents the formation of current leakage paths or fungus on the boards in high humidity environments. If it is necessary to replace a component, the coating must also be replaced. CE-1 164 protective coating is compatible with the circuit board coating and is MIL-l-46058 approved. CE-1 164 is available in aerosol cans from CONAP Incorporated, Olean, New York 14760. a. Either of two methods may be used to remove the coating and expose the faulty com- ponent. The coating must be removed and replaced on both sides of the board and the leads of the new component should be clipped as close to the board as possible. 1 . Using a soldering iron of approximately 50 watts, circle the component as closely as possible with the soldering iron tip. The coating will soften and partially evaporate. (It may be necessary to circle the component several times, following the same path each time.) 2. Use a sharp knife to peel the coating from around the component. Remove the coating so that a complete circle of board around the component is exposed. b. Replace the faulty component, observing the semiconductor precautions. NOTE Wear rubber gloves and, at all times, handle only the edges of the board. c. Dip and agitate the affected portion of the printed circuit board in a container of 1-1-1 trichloroethane (Dow Type VG) to remove any grease oily residue, or flux. d. Using isopropyl alcohol conforming to TT-1-735 and stiff-bristled brush, scrub the repaired area. e. Immerse or rinse the board in deionized or distilled water and agitate the board slightly to ensure complete coverage. Remove excess water. NOTE After cleaning, handle the board with cotton gloves for masking or with plastic gloves for coating. Do not touch the boards with your skin. If boards remain at room temperature longer than 2 hours before coating, steps f and g must be repeated to ensure that all moisture is driven from the boards. f. Dry the board in an oven at 167°F (75°C) for at least 1 hour, preferably 1.5 hours. g. Remove the board from the oven and let it stabilize to room temperature. h. Use latex masking, available from Contronic Devices, Westminster, California 92683, to mask areas that are not to be coated, such as connectors and heat sinks. 7-2 i. Using the aerosol can of CE-1 164, apply a liberal coat to the repaired area of both sides of the board, lapping the surrounding areas to ensure a good seal. Allow the coating to cure until it is tack-free, approximately 20 to 30 minutes, then spray on another coat. The coating will be tack-free in approximately 20 to 30 minutes and will cure in 24 hours at room temperature. Optimum physical and electrical properties require 5 to 7 days curing at room temperature. An alternate cure of 3 hours at 60°C plus 2 to 3 days at room temperature may also be used. j. Remove latex masking. k. Inspection may be assisted by use of an ultraviolet light which causes a dye in the coating to fluoresce. Assuming the board remains unsoiled at this step, coating touchup may be done without recleaning. 1 . For cleaning tools and equipment and for removing uncured coating, CONAP S-8 sol- vent is recommended. 7.4 TEST EQUIPMENT. — All test equipment required for maintenance is listed in table 7-1. 7.5 TROUBLESHOOTING PROCEDURE FOR THE IDE. 7.5.1 Introduction. — This section gives a condensed procedure to troubleshoot any malfunctioning of the Isolation Distribution Equipment. In general, the front panel displays and monitor output provide sufficient indication of any malfunction that may occur. The following section will list these indications and provide guided procedures in troubleshooting the problem down to the board level. The philosophy is that if proper signals enter a board correctly, the outputs (response to the inputs) should be correct for a good working board. Otherwise, the board is at fault. Table 7-1. Test Equipment Required NOMENCLATURE PART NO. MANUFACTURER FSCM Oscilloscope 7704A TEKTRONIX, INC. 80009 Dual Trace Amp 7A18 TEKTRONIX, INC. 80009 Dual Trace Amp 7A26 TEKTRONIX, INC. 80009 Time Base 7B80 TEKTRONIX, INC. 80009 Delay Time Base 7B85 TEKTRONIX, INC. 80009 Logic Analyzer 7D01 TEKTRONIX, INC. 80009 Probe, Passive P610 TEKTRONIX, INC. 80009 Probe, DAP P451 TEKTRONIX, INC. 80009 Multimeter 260 TEKTRONIX, INC. 80009 7.5.2 Symptoms. — A table with common failure symptoms and troubleshooting procedures is given in table 7-2. Even if a failure symptom is not listed in the table, troubleshooting can still be performed by starting with 7.5.2.1 and proceeding onward. 7-3 Table 7-2. Symptoms and Index to Troubleshooting SYMPTOMS PRELIMINARY INFERENCES TROUBLESHOOTING PROCEDURES REFER TO: Power on light does not light. Fuse & Power Connections All indicators for LVPS 1(2) do not light up. Power Supply Board 1(2) One or more indicators for LVPS 1(2) do not light up. Power Supply Board 1(2) No DVIP data or noise at monitor output for all 8 channels. Transmitter, Receiver, Clock Display 7.5.2.7, 7.5.2.6 7.5.2.5, No DVIP data or noise at monitor output for one or more channels. Transmitter 7.5.2.7 Burnout segments No display on 7-segments Clock Display Display Mounting 7.5.2.6, 7.5.2.2 Step i. Erroneous display for all functions Clock Display Receiver, Transmitter 7.5.2.7, 7.5.2.6, 7.5.2.5 7.5.2.2 Error time or date cannot set time or date Clock Display Front Panel Switches 7.5.2.6, 7.5.2.6, Step h. Step i. Error in Azimuth Display * Input Buffer/ + Synchro Converter /+ Synchro Output 7.5.2.8, 7.5.2.4 7.5.2.3 Error in Elevation Display * Input Buffer/ + Synchro Converter 7.5.2.8, 7.5.2.4 7.5.2.3 Error in Status Byte Input Buffer Board 7.5.2.8 Battery cannot be fully charged (low battery) (indica- tion for power loss less than 2 hrs) Battery, Battery Charger 7.5.2.1 * For R541 IDE + For R540 IDE 7-4 7.5.2.1 Battery Charger CCA N1A1A1. a. Check ac input to transformer at the 2-terminal side. b. Check output of transformer at TB1-6 and 7; output should be 1 2 V p-p ac. c. Check output of regulator at TB1-3; it should be about 13V. d. Unscrew wire going from the positive terminal of the battery to TB1-1. Measure current go- ing into the battery. If current is about 6-10 ma, battery charger is good. Replace battery. 7.5.2.2 Display Mounting CCA N1A1A2/A3. a. Select one of the status words to be displayed on the 7 segments. b. Test inputs to the display mounting board. The inputs should be the same as the outputs of U1 and U2 of the clock display board when the particular status strobe is active (refer to 6.1.7). The following gives a correspondence between the outputs of the clock display board and the inputs to the display mounting board. CLOCK DISPLAY BOARD DISPLAY MOUNTING BOARD P1-40 P1-59 38 61 36 63 34 57 48 47 46 49 44 51 42 45 56 35 54 37 52 39 50 33 59 23 57 25 55 27 53 21 7.5.2.3 Synchro Converter CCA N1A2A3/A4. a. Turn power off. Unplug the synchro data connector from the IDE. Pull out azimuth synchro converter board (Slot XA4-1) or elevation synchro converter board (Slot XA3-1). Put extender into its place and plug the converter board onto the extender. Reconnect the synchro data connector. Turn power on. b. Check power: TP10 - 12.0V + 0.6V TP11 - -12.0V ± 0.6V If voltages are out of spec, check power supplies. 7-5 c. Input a fixed azimuth or elevation angle to the IDE. 1 . Verify inputs to the Scott-T transformer T1 . P1-6, 2 and 4 are the inputs which are 90V; ac signals differ only in phases. 2. Verify the correct quadrant representation at AZS13/ELS13 (P1-49) and AZS12/ELS12 (P1-47) according to figure 2-14 in the theory of operation. 3. Verify the correct BCD representation of the AZ/EL angle at AZSO/ELSO through AZS11/ELS11 (P1-23 through P1-45 odd pins). This angle is less than 90° (measured counterclockwise from quadrant boundaries). AZS1 1-ELS1 1 is the MSB of the tens degree, and AZSO/ELSO is the LSB of the tenths degree. 7.5.2.4 Synchro Output CCA N1A2A5. a. Turn power off. Unplug the synchro data connector from the IDE. Pull out synchro output board. Put extender board into place and plug back the synchro output board onto extender. Discon- nect the synchro data connector. Turn power on. b. Check Power: TP4 = 12.0V ±0.6V TP3 = 12.0V ±0.6V TP1 = 5.0V ±0.25V If voltages are out of specification, check power supplies. If problem is in azimuth section, go to Step c. If problem is in elevation, go to Step d. c. Input a fixed azimuth angle to the IDE. 1. Verify the correct quadrant representation at AZS13 (P1-4) and AZS12 (P1-3) accord- ing to the convention described in the theory of operation. 2. Verify the correct BCD representation of the azimuth angle at AZSO through AZS1 1 (P1-15, 16, 13, 14, 11, 12, 9, 10, 7, 8, 5, 6). This angle is less than 90° (measured counterclockwise from quadrant boundaries). AZS1 1 is the MSB of the tens degree and AZSO is the LSB of the tenths degree. 3. Verify the BCD output angle at DO through D7 (P1-17 through 31, odd pins) using AH and AL to qualify the data on the data bus. The angle should correspond to the input angle. d. Input a fixed elevation angle to the IDE. 1. Verify the correct quadrant representation at ELS13 (P1-52) and ELS12 (P1-51) using the convention described in the theory of operation. 2. Verify the correct BCD representation of the elevation angle at ELSO through ELS1 1 is 2.5 times the true angle. This angle is less than 90° (measured counterclockwise from quadrant boun- daries). ELS1 1 is the MSB of the tens degree. ELSO is the LSB of the tenths degree. 3. Verify the BCD output angle at DO through D7 (PI -1 7 through 31, odd pins) using EH and EL to qualify the data on the bus. The angle should be 0.4 times the input angle, i.e., the true elevation. 7-6 7.5.2.5 Serial receiver CCA N1A2A6. a. Turn power off. Pull out serial receiver board. Put extender board into slot and plug receiver board into extender. Turn power on. b. Check power = A6TP4 - GND A6TP5 -+5V + 0.25 V If voltage is out of specification, check power supplies. c. Check Clock (TP1): 14.32 MHz d. Check serial input at TP2 - should be the same as in 4.1.4 except inverted. If not, go to 4.1.4. e. Check U1-9 for DATA valid strobe (DATA). .4 jts 6.7 /is one radial f. Check U1 - Pin 5 for error indication. If ERROR strobe (negative going) occurs, randomly or consistently, receiver board is not functioning correctly (if transmitter board is checked out already). g. Check data bus DO through D7 using DATA as trigger. Verify that the bus output cor- responds to the input DVIP data. (A fixed DVIP data may help.) An easier approach would be to use a logic analyzer. h. Verify the data strobes generated at the receiver. Observe the relationships on page 7-8 (be- tween each strobe and data bit DO). i. Verify other data bits for state transmissions (D1 through D7). j. If result is different from above, receiver is at fault. 7.5.2.6 Clock and Display CCA N1A2A7. a. Turn off power. Pull out cock and display board. Put extender board into slot and plug the card back into the extender. Turn on power. 7-7 DATA BIT TRANSITION DO 5V I I I I I I I I SYNC AZ HI AZ LO EL HI EL LO TIME HI TIME LO STATUS MONTH DAY b. Check power: (using TP1 as GND) A7TP2 - 5.0 V ± 0.25 V A7TP5 - 12.0 V ± 0.6 V A7TP3 - -12.0 V ± 0.6 V If voltages are out of spec, check power supplies. c. Check DVIP data bu s (PI -1 8 throu gh P1-32, even pins) in relation to DATA (P1-7) by triggering on the rising edge of DATA. DATA should go low at every data byte transition and last for a duration of about .4 /xs and should be high between radar dead times. If result is different, go to 7.5.2.3, step 8. 7-8 d. Monitor DVIP analog output at P1-41. A tedt level may be used as input to the IDE to verify the correct level output at P1-41. The LSB (DO) is worth about 20 mV, D1 about 40mV, D2 about 80mV, etc. e. Verify data strobes (SYNC, AZ HI, AZ LO, EL HI, EL LO, TIME HI, TIME LO, STATUS, MONTH, DAY) as in procedure 5.1.8. f. Check function select switch encoding by turning the switch to each individual position and verify the following levels on P1-33, 35, and 39. MO/DAY STATUS TIME ELEVATION AZIMUTH ZO (P1-33) V 5 V V 5 V V Z1 (P1-35) V 5 V 5 V V V Z2 (P1-39) 5 V V V V V g. Verify that the output words at outputs of U1 and U2 correspond to the actual inputs. Data strobes going into U6 and U7 and the function selection switch should be used to interpret the data at U1 and U2. h. Verify the control inputs to the clock chip. 1 . U13 pin 24 should toggle every 300-450 /*s with the clock control switch in the OFF position. Selecting TIME should go LO and DATE should go HI. 2. U13 pin 32 is normally LO unless in the HOLD position. 3. U13 pin 33 should go HI when SLOW SET is pushed. 4. U13 pin 34 should go HI when FAST SET is pushed. i. Verify t he t ime and date outputs of the clock. Monitor both the inputs and outputs to U22 using strobes TL, MO, TH, DA to interpret the data. j. Check voltage comparator: If voltage at U29 pin 3 is greater than pin 2, U29 and pin 7 should be LOW. Otherwise it should be HIGH. k. Any discrepancy from the above means the clock board is bad. 7.5.2.7 Transmitter CCA N1A2A8. a. Turn off power, pull out transmitter board, put extender board into the slot, and plug the transmitter onto the extender. Turn on power. b. Check power to board (using TP1 as ground): A8TP9 - 5.0 V ± 0.6V A8TP3 - 12.0 V ± 0.6V A8TP2 - 12.0 V ± 0.6 V If voltages are out of specification, check power supplies. 7-9 c. Use a dual trace oscilloscope to monitor the data ready strobe (TP7) and data bits (DO through D7) on P1-17 through P1-31 (odd pins). Use the system trigger as external trigger. Start with data bit DO (P1-17) and observe that the trailing edge of DATA RDY occurs at the bit center of the data bit . Check othe r data bits to verify that the data bit transitions do not fall close to the trailing edge of the DATA RDY. If bad, go to 7.5.2.1. Monitor the serial output at U9 - pin 6 (or at R33), us- ing the system trigger as trigger, and observe the serial output. Select all 8 channels of the select switch. System Trigger: Serial Output: 5V OV d. Now use the sync byte strobe (U16 - Pin 2) as trigger (negative edge) (oscilloscope horizontal, 2 /ts/div.) the bit pattern: observe Sync Byte Strobe: 7 us —a Serial Bit Output: Sync Byte 2 bit time 5 V V one bit time = 560 ns 10 bit time Monitor the serial outputs at the BNC output channels. Verify also that the HIGH bit time and LOW bit time are about the same, i.e., 560 ns and no excessive rounding occurs at the transi- tions. (Make sure that the channels are terminated.) 7-10 ( e. Observe the relationships between the data strobes and auxiliary data strobes: System Trigger DAT (U16 - Pin 1 SYN (U16 - Pin 2) c c 9 C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1N1 E BATTERY CHARGER ASSEMBLY 10236 8501287A1 BT1 BATTERY 10236 7060002-1 E1 INSULATOR PAD, MICA 10236 8500699-1 E2 WASHER, INSULATOR 10236 8141047-1 E3 WASHER, INSULATOR 10236 8501049-1 MP1 CLAMP (Electrodynamics 8062048-1) 06915 V-1006 T1 F TRANSFORMER (Electrodynamics 7160050-1) 70674 3-20706-000 VR1 F IC, VOLTAGE REGULATOR (Electrodynamics 7100370-1) 27014 LM117K N1A1A1 F BATTERY CHARGER CCA 10236 4260079A1 C1 G CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 470/uF - 10%, +30%; 30 V; MIL-C-39018/3 81349 M3901 8/03-0629 C2 G CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 /uF ±10%; 50 V; MIL-C-39014/1 81349 M39014/01-1473 CR1 G SEMICONDUCTOR DEVICE, DIODE: Voltage suppressor; MIL-S-19500/1 16F 81349 JAN1N4148 CR2 G Not Used CR3 G SEMICONDUCTOR DEVICE, DIODE: 200 Peak Input Voltage; 1A maximum, MIL-S-19500/427B 81349 JAN1N5614 CR4 G Same as CR3 CR5 G Same as CR3 CR6 G Same as CR3 MP1 G END BARRIER (Electrodynamics 8240064-1) 33333 776-0001 MP2 G PRINTED WIRING BOARD 10236 6260079-1 R1 G RESISTOR, FIXED, COMPOSITION: 121 ohms ±1%; 1/10W;MIL-R-55182/1 81349 RNC55H1211FS R2 G RESISTOR, FIXED, COMPOSITION: 10 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G100JS R3 G RESISTOR, FIXED, COMPOSITION: 100,000 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G104JS TB1 G TERMINAL BLOCK: 7 Position (Electrodynamics 8240061-1) 33333 JB6-P101-01 8-5 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) ■D C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes B DISPLAY MOUNTING BOARD FINAL ASSEMBLY N1A1A2 C DISPLAY MOUNTING NO. 2 CCA DS1 D SEMICONDUCTOR DEVICE, DISPLAY: 7-segment display (Electrodynamics 7230023-1) D D SEMICONDUCTOR DEVICE, LIGHT EMITTING DIODE: (Electrodynamics 7030057-1) D Same as DS1 Same as DS1 MP! PRINTED WIRING BOARD 10236 10236 28480 50579 4260081A1 4260078A1 HDSP-3531 LD464 10236 6260078-1 8-6 Table 8-1. Parts List (Continued) PARTS LIST Ref Des <-> c s -a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A1A3 C DISPLAY MOUNTING NO. 1 CCA 10236 4260077 A 1 C1 D CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 juF ±10%; 50 V; MIL-C-39014/1 81349 M39014/0M473 C2 D CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 2.2 /uF ±10%; 20 V; MIL-C-39003/1 81349 M39003/01-2283 MP1 D PRINTED WIRING BOARD (Electrodynamics 6260077-1) 10236 6260077-1 R1 D RESISTOR, FIXED, COMPOSITION: 240 ohm ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G241JS R2 D Same as R1 R3 D Same as R1 R4 D Same as R1 R5 D Same as R1 R6 D Same as R1 R7 D Same as R1 R8 D Same as R1 R9 D Same as R 1 R10 D Same as R1 R11 D Same as R 1 R12 D Same as R1 R13 D Same as R 1 R14 D Same as R1 R15 D Same as R1 R16 D Same as R 1 R17 D Same as R1 R18 D Same as R 1 R19 D Same as R1 R20 D Same as R 1 R21 D Same as R1 R22 D Same as R1 R23 D Same as R1 R24 D Same as R1 R25 D Same as R1 R26 D Same as R1 R27 D Same as R1 R28 D Same as R1 R29 D Same as R1 8-7 Table 8-1. Parts List (Continued) PARTS LIST f Ret Des c 03 c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R30 R31 D U1 D U2 D U3 D U4 D XU1 D XU2 D XU3 D XU4 D RESISTOR, FIXED, COMPOSITION: 180 ohms ±5%; 1/4 W; Ml L-R -39008/1 Same as R1 IC, 7-SEGMENT DECODER/DRIVER (Electrodynamics 7100444-1) Same as U1 Same as U1 Same as U1 CONNECTOR, IC SOCKET: 16 pins; low profile (Electrodynamics 7180132-3) Same as XU1 Same as XU1 Same as XU1 81349 07263 RCR07G181JS 9370 00779 641262-1 8-8 Table 8-1. Parts List (Continued) PARTS LIST Ref Des *-> c o C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A2A1/ A2 C1 B D.E. POWER SUPPLY NO. 1 CCA 10236 4260067A1 C CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 2.2 /L/F ±10%; 20 V; MIL-C-39003/1 81349 M3900/01-2283 C2 C Same as C1 C3 C CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 2.2 mF ±10%; 15 V; MIL-C-39003/1 81349 M39003/0 1-2271 C4 C Same as C3 C5 C CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 4.7/iF±10%; 10 V; MIL-C-39003/1 81349 M39003/01-2254 C6 C CAPACITOR, FIXED, ELECTROLYTIC: aluminum; 470 fit -10%, +30%; 10 V; MIL-C-39018/1 81349 M39018/01-0611 C7 C CAPACITOR, FIXED, MICA DIELECTRIC: 750 juF ±5%; 500 V; MIL-C-39001/5 81349 CMR06F751JPDM C8 C CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 47/iF ±20%; 6 V; MIL-C-39003/1 81349 M39003/01-2245 C9 C CAPACITOR, FIXED, ELECTROYLTIC: tantalum; 100 juF, ±10%; 20 V; MIL-C-39003/1 81349 M39003/01-2301 C10 C Same as C9 C11 c CAPACITOR, FIXED, MICA DIELECTRIC: 2200 pF ±5%; 500 V; MIL-C-39001/5 81349 CMR06F222JPDM C12 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: 1.0 /iF ±10%; 50 V; MIL-C-39014/1 81349 M390 14/02- 1407 C13 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: .01 /uF ±10%; 100 V; MIL-C-39014/1 81349 M39014/0M455 C14 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 juF ±10%; 50 V; MIL-C-39014/1 81349 M39014/01-1473 C15 c Same as C14 C16 c Same as C5 C17 c CAPACITOR, FIXED, ELECTROLYTIC: aluminum; 2200 juF -10%, +30%; 10 V; MIL-C-39018/1 81349 M3901 8/03-061 3 C18 c CAPACITOR, FIXED, ELECTROLYTIC: aluminum; 10/uF -10%, +30%;250 V; MIL-C-39018/1 81349 M39018/01-1171 C19 c Same as C14 C20 c CAPACITOR, FIXED, MICA DIELECTRIC: 510 pF ±5%; 500 V; MIL-C-39001/5 81349 CMR06F511JPDM C21 c CAPACITOR, FIXED, ELECTROLYTIC: aluminum; 150 /jF -10%, +30%; 150 V; MIL-C-39018/1 81349 M3901 8/07-031 7 C22 c Same as C21 C23 c Same as C9 C24 c Same as C9 C25 c Same as C7 C26 c Same as C8 8-9 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c CD Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes C27 C Same as CI 2 C28 C Same as C14 C29 C Same as C13 CR1 Not Used CR2 C SEMICONDUCTOR DEVICE, DIODE: MILS- 19500/477 81349 JAN1N5802 CR3 C SameasCR2 CR4 Not Used CR5 Not Used CR6 C SameasCR2 CR7 c Same as CR2 CR8 c SameasCR2 CR9 c SEMICONDUCTOR DEVICE, DIODE: MILS- 19500/286 81349 JAN1N4245 CR10 c Same as CR9 CR11 c SEMICONDUCTOR DEVICE, DIODE: Ml L-S- 19500/1 16 81349 JAN1N4148 CR12 c SEMICONDUCTOR DEVICE, DIODE: 100 Peak Input Voltage; 1A maximum. Ml L-S-1 9500/429 81349 JAN1N5619 CR13 c SameasCR2 CR14 c SameasCR2 CR15 c Same as CR2 CR16 c SameasCR2 CR17 c SEMICONDUCTOR DEVICE, DIODE: 30 Peak Input Voltage; 8A maximum (Electrodynamics 7030056-1) 04713 1N5825 CR18 Not Used CR19 c SEMICONDUCTOR DEVICE, DIODE: 400 Peak Input Voltage; 2A maximum; Ml L-S- 19500/286 81349 JAN1N4246 CR20 c Same as CR 19 CR21 c Same as CR 19 CR22 c Same asCRl9 CR23 c Same as CR17 CR24 c Same asCRl7 CR25 c Same as CR 11 CR26 c Same as CR9 CR27 c Same as CR9 CR28 c Same as CR9 CR29 c Same as CR9 8-10 Table 8-1. Parts List (Continued) PARTS LIST Ref Des *-> c 0) Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes CR30 C Same as CR9 CR31 C Same as CR9 CR32 C Same as CR9 CR33 C Same as CR9 L1 C INDUCTOR, CHOKE: 0.120 MH 10236 7190048-1 L2 C INDUCTOR, CHOKE: 1.250 MH 10236 7190049-1 L3 C INDUCTOR, CHOKE: .0715 MH 10236 7190047-1 MP1 C PRINTED WIRING BOARD 10236 6260067-1 MP2 C INJECTOR/EJECTOR (Electrodynamics 8501044) 22589 NE-3001-W MP3 c HEATSINK, TO-5 THERMACLIP 10236 7070040-1 MP4 c HEATSINK, DE POWER SUPPLY 10236 7070039-1 MP5 c CLIP, COMPONENT (Electrodynamics 8062049-1 1 ) 06915 V-1010 MP6 c CLIP, COMPONENT (Electrodynamics 8062049-10) 06915 V-1009 MP7 c CLIP, COMPONENT (Electrodynamics 8062049-3) 06915 V-1002 Q1 Not Used Q2 Not Used Q3 c TRANSISTOR: MOSFET; (Electrodynamics 7040049-1) 81483 IRF420 Q4 c Same as Q3 Q5 c Same as Q3 R1 c RESISTOR, FIXED, FILM: 499 ohms ±1%; 1/10 W; MIL-R-55182/3 81349 RNC55H4990FS R2 c RESISTOR, FIXED, FILM: 619ohms ±1%; 1/10 W; MIL-R-55182/3 81349 RNC55H6190FS R3 c RESISTOR, FIXED, COMPOSITION: 20,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G203JS R4 c RESISTOR, FIXED, FILM: 5,1 10 ohms ±5%; 1/4 W; MIL-R-55182/3 81349 RNC55H5111FS R5 c Same as R4 R6 c RESISTOR, FIXED, COMPOSITION: 8,200 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G822JS R7 c RESISTOR, FIXED, COMPOSITION: 1,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G102JS R8 c RESISTOR, FIXED, FILM: 7,500 ohms ±1%; 1/10 W; MIL-R-55182/3 81349 RNC55H7501FS 8-11 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) -o Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R9 c RESISTOR, FIXED, COMPOSITION: 30,000 ohms ±5%; 1/4 W; Ml L-R -39008/1 81349 RCR07G303JS RIO C RESISTOR, VARIABLE, WIREWOUND: 50,000 ohms±1%;3W (Electrodynamics 7010045-1) 91637 RS-5-51K R11 C RESISTOR, FIXED, COMPOSITION: 5,100 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G5R1JS R12 C Same as R7 R13 C RESISTOR, FIXED, COMPOSITION: 20,000 ohms ±5%; 1 W;MIL-R-39008/3 81349 RCR32G203JS R14 C Same as R13 R15 C RESISTOR, FIXED, WIREWOUND: 1 ohm ±1%; 1 W;MIL-R-39007/9 81349 RWR81S1R00FR R16 C Same as R9 R17 C Same as R7 R18 C Same as R7 R19 C RESISTOR, FIXED, FILM: 576 ohms ±1%; 1/10 W; MIL-R-55182/3 81349 RNC55H5760FS R20 C Same as R1 R21 c Same as R3 R22 c Same as R4 R23 c Same as R4 R24 c Same as R7 R25 c Same as R7 R26 c Same as R8 T1 c TRANSFORMER, ISOLATED OUTPUT 10236 7160044-1 T2 c TRANSFORMER, ISOLATED DRIVER 10236 7160045-1 T3 c TRANSFORMER, CURRENT SAMPLER 10236 7160046-1 T4 c TRANSFORMER, DE DRIVER, QUAD SECONDARY: 10236 7160047-1 T5 c Same as T3 T6 c TRANSFORMER, DE DRIVER, DUAL SECONDARY 10236 7160048-1 T7 c TRANSFORMER, LOW POWER: 115 V Primary, 20 V Secondary; V.C.T. 10236 7160049-1 U1 c IC, REGULATING PULSE WIDTH MODULATOR (Electrodynamics 7100373-1) 34333 SG1526 U2 c Same as U1 U3 c IC, VOLTAGE REGULATOR: -12 V, 0.5A (Electrodynamics 7100452-1) 27014 LM320H-12 8-12 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c ■D C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U4 XU1 XU2 XU3 XU4 IC, VOLTAGE REGULATOR: 12 V, 0.5A (Electrodynamics 7100371-1) CONNECTOR, IC SOCKET: 18 pins; low profile (Electrodynamics 7180132-4) SameasXlM SOCKET, TRANSISTOR, TO-5 Same as XU1 07263 00779 10236 UA7812H 641263-1 829009-1 8-13 Table 8-1. Parts List (Continued) PARTS LIST Ref Des ■*■> c 0) TJ C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A2A3/ A4 B DIGITAL SYNCHRO CONVERTER CCA 10236 4260061 A 1 C1 Not Used C2 Not Used C3 C CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 |UF ±10%; 50 V;MIL-C-39014/1 81349 M39014/01-1473 C4 C Same as C3 C5 C Same as C3 C6 C Same as C3 C7 Not Used C8 Not Used C9 C Same as C3 C10 Not Used C11 C Same as C3 C12 C Same as C3 C13 Not Used C14 C Same as C3 C15 Not Used C16 C Same as C3 C17 Not Used C18 C Same as C3 C19 C Same as C3 C20 Not Used C21 c Same as C3 C22 Not Used C23 c Same as C3 C24 Not Used C25 c Same as C3 C26 c Same as C3 C27 c Same as C3 C28 c Same as C3 C29 c Same as C3 C30 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.01 juF ±10%; 100 V; MIL-C-39014/5 81349 M39014/01-1455 C31 c Same as C3 C32 c Same as C3 C33 c CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 2.2 juF ±10%;20V;MIL-C-39003/1 81349 M39003/01-2283 8-14 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c ■o Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes C34 C Same as C33 C35 C Same as C3 C36 c Same as C33 C37 c Same as C33 C38 c Same as C3 C39 c Same as C3 C40 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: 2700 pF ±10%; 100 V; MIL-C-39014/1 81349 M39014/01-1445 C41 c CAPACITOR, FIXED, ELECTROLYTIC: tantalum; non-polarizing; 6 /iF ±10%; 20 V; MIL-C-39003/4 81349 M 39003/4-0271 C42 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: 1.0/xF ±10%; 50 V; MIL-C-39014/2 81349 M3901 4/02-1 407 CR1 c SEMICONDUCTOR DEVICE, DIODE: Switching, Ml L-S- 19500/1 16 81349 JAN1N4148 CR2 c SEMICONDUCTOR DEVICE, DIODE: Zener, 7.5 V; 1 .5 W; M I L-S-1 9500/406 81349 JAN1N4462 CR3 c SameasCR2 CR4 c SameasCRl CR5 c Same as CR1 CR6 c Same as CR1 MP1 c PRINTED WIRING BOARD 10236 6260061-1 MP2 c INJECTOR/EJECTOR (Electrodynamics 8501044) 22589 NE-3001-W Q1 c TRANSISTOR: FET (Electrodynamics 7040050-1) 27014 2N5434 Q2 c Same as Q1 Q3 Not Used Q4 c TRANSISTOR: FET; Ml L-S-1 95001/385 81349 JAN2N4857 Q5 c Same as Q4 R1 c RESISTOR, FIXED, COMPOSITION: 220,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G224JS R2 c RESISTOR, FIXED, FILM: 16,000 ohms ±0.01%; 0.3W;MIL-R-55182/9 81349 RNC90Y1602TR R3 c Same as R2 R4 c RESISTOR, FIXED, CARBON: 33,000,000 ohms ±5%; 1/4W; (Electrodynamics 7010044-1) 01121 CB3365 R5 c RESISTOR, FIXED, COMPOSITION: 16,000,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G166JS R6 c RESISTOR, FIXED, FILM: 1,600,000 ohms ±1%; 1/8 W; MIL-R-55182/3 81349 RNC60H1604FS 8-15 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c a> ■o Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R7 R8 C C RESISTOR, FIXED, FILM: 3,200,000 ohms ±1%; 1/8W;MIL-R-55182/3 RESISTOR, FIXED, FILM: 6,420,000 ohms ±1%; 1/4W;MIL-R-55182/5 81349 81349 RNC60H3204FS RNC65H6424FS R9 c RESISTOR, FIXED, FILM: 12,700,000 ohms ±1%; 1/2W;MIL-R-55182/6 81349 RNC70H1275FS R10 c RESISTOR, FIXED, FILM: 1,280,000 ohms ±0.1%; 1/8W;MIL-R-55182/3 81349 RNC60H1284BS R11 c RESISTOR, FIXED, FILM: 640,000 ohms ±0.1 %; 1/8W;MIL-R-55182/3 81349 RNC60H6403BS R12 c RESISTOR, FIXED, FILM: 320,000 ohms ±0.1%; 1/8W;MIL-R-55182/3 81349 RNC60H3203BS R13 c RESISTOR, FIXED, FILM: 160,000 ohms ±0.1%; 1/8W;MIL-R-55182/3 81349 RNC60H1603BS R14 c RESISTOR, FIXED, FILM: 128,000 ohms ±0.01%; 0.3 W; (Electrodynamics 7010043-1) 18612 E102C128K000T R15 c RESISTOR, FIXED, FILM: 64,000 ohms ±0.01%; 0.3W;MIL-R-55182/9 81349 RNC90Y6402TP R16 c RESISTOR, FIXED, FILM: 32,000 ohms ±0.01%; 0.3W;MIL-R-55182/9 81349 RNC90Y3202TR R17 c RESISTOR, FIXED, COMPOSITION: 120 ohms ±5%;1/2W;MIL-R-39008/1 81349 RCR20G12US R18 c Same as R17 R19 c Same as R1 R20 c Same as R2 R21 c Same as R2 R22 c Same as R4 R23 c Same as R5 R24 c Same as R9 R25 c Same as R8 R26 c Same as R7 R27 c Same as R6 R28 c Same as R10 R29 c Same as R1 1 R30 c Same as R12 R31 c Same as R13 R32 c Same as R14 R33 c Same as R15 R34 c Same as R16 R35 c Same as R2 R36 c Same as R16 8-16 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R37 c Same as R2 R38 C Same as R16 R39 C RESISTOR, FIXED, COMPOSITION: 10,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G103JS R40 C RESISTOR, FIXED, COMPOSITION: 22,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G223JS R41 C RESISTOR, FIXED, FILM: 1,500 ohms ±1%; 1/8W;MIL-R-55182/3 81349 RNC60H1502FS R42 C RESISTOR, FIXED, COMPOSITION: 68,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G683JS R43 C RESISTOR, FIXED, FILM: 20,000 ohms ±1%; 1/8W;MIL-R-55l82/3 81349 RNC60H2002FS R44 C Same as R39 R45 C RESISTOR, FIXED, COMPOSITION: 100 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G101JS R46 C Same as R45 R47 C Same as R39 R48 C RESISTOR, FIXED, COMPOSITION: 75,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G753JS R49 c RESISTOR, FIXED, COMPOSITION: 2,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G202JS R50 c RESISTOR, FIXED, FILM: 200,000 ohms ±1 %; 1/8W;MIL-R-55182/3 81349 RNC60H2003FS R51 c RESISTOR, FIXED, FILM: 100,000 ohms ±1%; 1/8W;MIL-R-55182/3 81349 RNC60H1003FS R52 c RESISTOR, FIXED, COMPOSITION: 1,000,000 ohms±1%; 1/8 W; MIL-R-39008/1 81349 RCR07G105JS R53 c Same as R39 R54 c Same as R39 R55 c Same as R43 R56 c Same as R1 R57 c Same as R39 R58 c Same as R39 R59 c RESISTOR, FIXED, COMPOSITION: 5,100 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G512JS R60 c Same as R59 R61 c Same as R39 R62 c Same as R39 R63 c Same as R39 8-17 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c a> C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R64 C RESISTOR, FIXED, COMPOSITION: 33,000 ohms ±5%; 1/4 W; M I L-R -39008/1 81349 RCR07G333JS R65 c Same as R52 R66 c RESISTOR, FIXED, COMPOSITION: 3,300 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G332JS R67 c Same as R45 R68 c Same as R48 R69 c RESISTOR, FIXED, COMPOSITION: 3,000 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G302JS R70 c Same as R50 R71 c Same as R51 R72 c Same as R52 R73 c RESISTOR, VARIABLE, NON-WIRE-WOUND: 100,000 ohms; MIL-R-39035B 81349 RJR24FX104P T1 c TRANSFORMER, MAGNETIC 10236 7160042-1 TP1 c TEST POINT: White; MIL-C-39024/1 1 81349 M39024/11-01 TP2 c Same as TP1 TP3 c Same as TP1 TP4 c Same as TP1 TP5 c Same as TP1 TP6 c Same as TP1 TP7 c Same as TP1 TP8 c Same as TP1 TP9 c Same as TP1 TP10 c TEST POINT: Red; MIL-C-39024/1 1 81349 M39024/11-02 TP11 c TEST POINT: Purple; MIL-C-39024/1 1 81349 M39024/1M0 TP12 c TEST POINT: Black; MIL-C-39024/1 1 81349 M39024/11-03 U1 c IC, CMOS DUAL 4-INPUT NOR GATE (Electrodynamics 7100336-1) 27014 CD4002B U2 c IC, CMOS QUAD BILATERAL SWITCH (Electrodynamics 7100320-1) 27014 CD4062B U3 c Same as U2 U4 c Same as U2 U5 c Same as U2 U6 c IC, SYNC, 4-BIT UP/DOWN CONVERTER (Electrodynamics 7100344-1) 27014 CD4019B U7 c Same as U6 U8 c Same as U6 8-18 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c o ■o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U9 C Same as U6 LMO C IC, HEX INVERTER (Electrodynamics 7100202-1) 27014 CD4069UBMJ/883 U11 C Same as U10 U12 C Same as U10 U13 C IC, 4-BIT FULL ADDER (Electrodynamics 7100343-1) 27014 CD4008B U14 C Same as U13 U15 C Same as U13 U16 C Same as U13 U17 C Same as U2 U18 C Same as U2 U19 C Same as U2 U20 C Same as U2 U21 c IC, DUAL 4-CHANNEL MULTIPLEXER/ DEMULTIPLEXER (Electrodynamics 7100348-1) 27014 CD4052 U22 c Same as U21 U23 c IC, QUAD 2-INPUT NOR GATE (Electrodynamics 7100345-1) 27014 CD4001B U24 c IC, CMOS QUAD 2-INPUT NAND GATE (Electrodynamics 7100250-1) 04713 MC14011BBCBS U25 c IC, SYNC, 4-BIT UP/DOWN DECADE COUNTER (Electrodynamics 7100372-1) 02735 CD40193BF/3 U26 c Same as U24 U27 c IC, DUAL J-K MASTER/SLAVE FLIP-FLOP WITH SET AND RESET (Electrodynamics 7100341-1) 27014 CD4027B U28 c IC, QUAD 741 OPERATIONAL AMPLIFIER (Electrodynamics 7100291-1) 27014 LM148J/883 U29 c IC, QUAD OPERATIONAL AMPLIFIER (Electrodynamics 7100351-1) 27014 LM124 U30 c IC, TIMER (Electrodynamics 7100292-1) 27014 LM555J U31 c Same as U10 U32 c Same as U24 U33 c IC, OPERATIONAL AMPLIFIER, 8 PIN, TO-92 (Electrodynamics 7100342-1) 00665 OP05-883-J XQ1 c TRANSISTOR PAD: TO-5 10236 8290009-1 8-19 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) "O Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes XQ2 C Same as XQ1 XQ3 Not Used XQ4 C Same as XQ1 XQ5 C Same as XQ1 XU1 C CONNECTOR, IC SOCKET: 14 pins; low profile (Electrodynamics 7180132-2) 00779 641261-1 XU2 C Same as XU1 XU3 XU4 C C Same as XU1 Same as XU1 XU5 C Same as XU1 XU6 C CONNECTOR, IC SOCKET: 16 pins; low profile (Electrodynamics 7180132-3) 00779 641262-1 XU7 C Same as XU6 XU8 C Same as XU6 XU9 C Same as XU6 XU10 c Same as XU1 XU11 c Same as XU1 XU12 c Same as XU1 XU13 c Same as XU6 XU14 c Same as XU6 XU15 c Same as XU6 XU16 c Same as XU6 XU17 c Same as XU1 XU18 c Same as XU1 XU19 c Same as XU1 XU20 c Same as XU1 XU21 c Same as XU6 XU22 c Same as XU6 XU23 c Same as XU1 XU24 c Same as XU1 XU25 c Same as XU6 XU26 c Same as XU1 XU27 c Same as XU6 XU28 c Same as XU1 XU29 c Same as XU1 XU30 c CONNECTOR, IC SOCKET: 8 pins; low profile (Electrodynamics 7180132-1) 00779 641260-1 8-20 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c -a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes XU31 C SameasXUl C SPREADER, IC SOCKET: 8 pins, 0.400 inch centers (Electrodynamics 829001 3-1 ) 32559 700-130 8-21 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A2A5 B SYNCHRO OUTPUT BOARD CCA 10236 4260062 A 1 C1 C CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 /nF ±10%; 50 V; MIL-C-39014/1 81349 M39014/01-1473 C2 Not Used C3 C Same as C1 C4 Not Used C5 C Same as C1 C6 C Same as C1 C7 Not Used C8 c Same as C1 C9 c Same as C1 C10 c Same as C1 C11 c Same as C1 C12 Not Used C13 c Same as C1 C14 Not Used C15 c Same as C1 C16 Not Used C17 c Same as C1 C18 c Same as C1 C19 Not Used C20 c Same as C1 C21 Not Used C22 c Same as C1 C23 Not Used C24 c Same as C1 C25 Not Used C26 c CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 2.2/xF±10%; 15 V; MIL-C-39003/1 81349 M39003/01-2283 C27 c Same as C26 C28 c Same as C26 CR1 c SEMICONDUCTOR DEVICE, DIODE: Zener; 7.5 V; 1 W; M I L-S- 19500/406 81349 JAN1N4462 CR2 c Same as CR1 CR3 c SEMICONDUCTOR DEVICE, DIODE: Transient voltage suppressor; 5 V minimum breakdown voltage; 23.8 A maximum peak pulse current (Electrodynamics 7030040-1) 12969 TVS505 8-22 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes MP1 C PRINTED WIRING BOARD 10236 6260062-1 MP2 c INJECTOR/EJECTOR (Electrodynamics 8501044-1) 22589 NE-3001-W R1 c RESISTOR, FIXED, COMPOSITION: 4,700 ohms ±5%; 1/4 W; Ml L-R -39008/1 81349 RCR07G472JS R2 c Same as R1 R3 c Same as R1 R4 c Same as R1 R5 c Same as R 1 R6 c Same as R1 R7 c Same as R1 R8 c Same as R1 R9 c Same as R1 R10 c Same as R1 R11 c Same as R1 R12 c RESISTOR, FIXED, COMPOSITION: 6,800 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G682JS R13 c Same as R 1 R14 c Same as R1 R15 c Same as R1 R16 c Same as R 1 R17 c Same as R 1 R18 c Same as R 1 R19 c Same as R1 R20 c Same as R1 R21 c Same as R 1 R22 c Same as R 1 R23 c Same as R 1 R24 c Same as R 1 R25 c RESISTOR, FIXED, COMPOSITION: 8,200 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G822JS R26 c Same as R25 R27 c Same as R25 R28 c Same as R25 R29 c Same as R25 R30 c Same as R12 R31 c Same as R12 R32 c Same as R12 8-23 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c Q) ■D C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R33 c Same as R12 R34 c Same as R12 R35 c Same as R 1 R36 c Same as R1 R37 c Same as R1 R38 c Same as R1 R39 c Same as R1 R40 c Same as R1 R41 c Same as R1 R42 c Same as R1 R43 c Same as R1 R44 c Same as R1 R45 c Same as R1 R46 c Same as R1 R47 c Same as R1 R48 c Same as R1 R49 c Same as R1 R50 c Same as R1 R51 c Same as R12 R52 c Same as R12 R53 c Same as R12 R54 c Same as R1 R55 c Same as R1 R56 c Same as R1 R57 c Same as R12 R58 c Same as R12 R59 c Same as R1 R60 c Same as R1 R61 c Same as R1 R62 c Same as R1 R63 c Same as R1 R64 c Same as R1 R65 c Same as R1 R66 c Same as R1 R67 c Same as R12 R68 c Same as R1 R69 c Same as R1 8-24 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) "D C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R70 C Same as R1 R71 c Same as R1 R72 c RESISTOR, FIXED, COMPOSITION: 120 ohms ±5%; 1/2 W; Ml L-R -39008/2 81349 RCR20G121JS R73 c Same as R72 T1 c TRANSFORMER: 10236 7160043-1 TP1 c TEST POINT: Red; Ml L-S-1 5900/385 81349 M39024/11-02 TP2 c TEST POINT: Black; MIL-S-19500/291 81349 M39024/11-03 TP3 c TEST POINT: Purple; Ml L-S-1 9500/251 81349 M39024/11-10 TP4 c Same as TP1 U1 c IC, CMOS QUADRUPLE Bl LATERAL SWITCH (Electrodynamics 7100320) 27014 CD4062B U2 c Same as U1 U3 c Same as U1 U4 c Same as U1 U5 c IC, HEX INVERTER (Electrodynamics 7100202-1) 27014 CD4069UBMJ/ 883B U6 c IC, BIPOLAR 32x8 PROM (Electrodynamics 7100350-1) 34371 HM1-7602B-8 U7 c Same as U6 U8 c Same as U6 U9 c Same as U6 U10 c Same as U6 U11 c IC, CMOS ADDER (Electrodynamics 7100352-1) 04713 MC14560BBEBS U12 c Same as U11 U13 c Same as U11 U14 c Same as U11 U15 c IC, LOW POWER SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) (Electrodynamics 7100273-1) 18324 S54LS240F/883B U16 c Same as U15 U17 c IC, OCTAL D-TYPE TRANSPARENT LATCH AND EDGE TRIGGERED FLIP-FLOP (Electrodynamics 7100360-1) 18324 S54LS373F/883B U18 c Same as U6 U19 c Same as U6 U20 c Same as U17 U21 c Same as U5 U22 c Same as U1 8-25 Table 8-1. Parts List (Continued) PARTS LIST Ref Des •4-> c c 0) -a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R3 C RESISTOR, FIXED, COMPOSITION: 100,000 ohms ±5%; 1/4 W; Ml L-R -39008/3 81349 RCR07G104JS R4 C RESISTOR, FIXED, FILM: 1,100 ohms ±1%; 1/8W;MIL-R-55182/3 81349 RNC60H1101FS R5 c RESISTOR, FIXED, FILM: 2,200 ohms ±1%; 1/8W;MIL-R-55182/3 81349 RNC60H2211FS R6 c Same as R3 R7 c Same as R3 R8 c RESISTOR, FIXED, COMPOSITION: 22,000,000 ohms ±5%; 1 /4 W; Ml L-R -39008/3 81349 RCR07G226JS R9 c Same as R3 R10 c Same as R3 R11 c RESISTOR, FIXED, COMPOSITION: 3,300 ohms ±5%; 1/4 W; MIL-R-39008/3 81349 RCR07G332JS R12 c Same as R1 1 R13 c RESISTOR, FIXED, COMPOSITION: 1,000 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G102JS R14 c Same as R3 R15 c RESISTOR, FIXED, COMPOSITION: 47,000 ohms ±5%; 1/4 W; MIL-R-39008/3 81349 RCR07G473JS R16 c Same as R3 R17 c Same as R3 R18 c Same as R3 R19 c Same as R3 R20 c Same as R3 R21 c Same as R3 R22 c Same as R3 R23 c Same as R3 R24 c Same as R3 R25 c Same as R3 R26 c Same as R3 R27 c Same as R3 R28 c Same as R3 R29 c Same as R3 R30 c Same as R3 R31 c Same as R3 R32 c Same as R3 R33 c Same as R3 R34 c Same as R3 8-32 Table 8-1. Parts List (Continued) % PARTS LIST Ref Des c -a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R35 C Same as R3 R36 c Same as R3 R37 c Same as R3 R38 c Same as R3 R39 c Same as R3 R40 c Same as R3 R41 c Same as R3 R42 c RESISTOR, FIXED, COMPOSITION: 4,300 ohms ±5%, 1/4 W; Ml L-R -39008/1 81349 RCR07G432JS R43 c RESISTOR, FIXED, COMPOSITION: 39,000 ohms ±5%; 1/4 W, MIL-R-39008/3 81349 RCR07G393JS R44 c Same as R11 R45 c Same as R1 1 R46 c Same as R1 1 R47 c Same as R11 R48 c Same as R11 R49 c Same as R13 R50 c RESISTOR, FIXED, COMPOSITION: 75 ohms ±5%; 1/4 W; Ml L-R -39008/1 81349 RCR07G750JS TP1 c TEST POINT: Black; Ml L-C-39024/1 1 81349 M39024/11-03 TP2 c TEST POINT: Red; Ml L-C-39024/1 1 81349 M39024/1 1 -02 TP3 c TEST POINT: Purple; M I L-C-39024/1 1 81349 M39024/11-10 TP4 c Same as TP2 TP5 c Same as TP2 U1 c IC, OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE TRIGGERED FLIP-FLOP (Electrodynamics 7100360-1) 18324 S54LS373F/883B U2 c Same as U1 U3 c IC, LOW POWER SCHOTTKY HEX D FLIP-FLOP 18324 S54LS174F/883B U4 c Same as U3 U5 c IC, 8-BIT, HIGH SPEED, MULTIPLE DIGITAL- TO-ANALOG CONVERTER ( Electrodynamics 7 1 00355-1 ) 34335 DAC-08AQB U6 c IC, DATA SELECTOR/MULTIPLEXER (Electrodynamics 7100358-1) 18324 S54LS251F/883B U7 c Same as U6 U8 c IC, CMOS DUAL D-TYPE FLIP-FLOP (Electrodynamics 7100251-1) 27014 CD4013BF/3 U9 c IC, OSCILLATOR PRESCALER, 3.58 MHz to 60 Hz (FlfirtrnHynamir.: 710091 R-1) 27014 MM5369AA/N 8-33 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c •a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U10 C IC, CMOS BCD-TO-DECIMAL DECODER (Electrodynamics 7100339-1) 27014 CD4028B U11 C IC, QUADRUPLE 2-INPUT NOR GATE (Electrodynamics 7100345-1) 27014 CD4001B U12 c IC, QUADRUPLE 2-INPUT NOR GATE (Electrodynamics 7100443-1 ) 27014 CD4071B U13 c IC, ALARM CLOCK CALCULATOR (Electrodynamics 7100445-1 ) 27014 MM73178N U14 c IC, 7-SEGMENT TO BCD CONVERTER (Electrodynamics 7100446-1) 27014 MM54C915 U15 c Same as U14 U16 c Same as U14 U17 c IC, TIMER (Electrodynamics 7100292-1 ) 27014 LM555J U18 c Same as U14 U19 c IC, LOW POWER SCHOTTKY QUADRUPLE 2-INPUT EXCLUSIVE OR GATE (Electrodynamics 7100147-1) 27014 DM54LS86J/883E U20 c IC, DUAL 4-INPUT POSITIVE AND GATE (Electrodynamics 7100225-1) 18324 S54LS21F/883B U21 c Same as U19 U22 c IC, LOW POWER SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) (Electrodynamics 7100273-1) 18324 S54LS240F/883B U23 c Same as U20 U24 c Same as U1 U25 c Same as U1 U26 c Same as U1 U27 c Same as U1 U28 c IC, OPERATIONAL AMPLIFIER (Electrodynamics 7100169-2) 27014 LM741 U29 c IC, VOLTAGE COMPARATOR (Electrodynamics 7100159-1 ) 27014 LM1 11 J/883 XQ1 c TRANSISTOR PAD: TO-5 10236 8290009-1 XU1 c CONNECTOR, IC SOCKET: 20 pins; low profile (Electrodynamics 7180132-5) 00779 641264-1 XU2 c Same as XU1 XU3 c CONNECTOR, IC-SOCKET: 16 pins; low profile (Electrodynamics 7180132-3) 00779 641262-1 XU4 c Same as XU3 XU5 c Same as XU3 XU6 c Same as XU3 8-34 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 9 Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes XU7 C Same as XU3 XU8 C CONNECTOR, IC SOCKET: 14 pins; low profile (Electrodynamics 7180132-2) 00779 641261-1 XU9 C CONNECTOR, IC SOCKET: 8 pins; low profile (Electrodynamics 7180132-1) 00779 641260-1 XU10 C Same as XU3 XU11 C Same as XU8 XU12 C Same as XU8 XU13 C CONNECTOR, IC SOCKET: 40 pins; low profile (Electrodynamics 7180132-9) 00779 641268-1 XU14 C CONNECTOR, IC SOCKET: 18 pins; low profile (Electrodynamics 7180132-4) 00779 641263-1 XU15 C Same as XU14 XU16 C Same as XU14 XU17 c Same as XU9 XU18 c Same as XU14 XU19 c Same as XU8 XU20 c Same as XU8 XU21 c Same as XU8 XU22 c Same as XU1 XU23 c Same as XU8 XU24 c Same as XU1 XU25 c Same as XU1 XU26 c Same as XU1 XU27 c Same as XU1 XU28 XU29 c c SPREADER, IC: 8 pins; 0.400 inch centers (Electrodynamics 829001 3-1 ) SameasXU29 32559 700-130 Y1 c CRYSTAL: 3.579545 MHz; 10 PPM MIL-C-3098/47 81349 CR69A/U3.579- MHz 8-35 Table 8-1. Parts List (Continued) PARTS LIST Ref Des *•> c 0) T3 Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A2A8 B TRANSMITTER CCA 10236 4260064A1 C1 C CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 22 juF ± 10%; 15 V; MIL-C-39014/1 81349 M39003/01-2271 C2 C CAPACITOR, FIXED, MICA DIELECTRIC: 10 pF ± 10%; 300 V; MIL-C-39001/5 81349 M39014/01-1473 C3 C Same as C2 C4 C Same as C2 C5 C Same as C2 C6 C Same as C2 C7 C Same as C2 C8A C Same as C2 C8B C Same as C2 C9 Not Used C10 C Same as C2 C11 C Same as C2 C12 c Same as C2 C13 c Same as C2 C14 c Same as C2 C15 c Same as C2 C16 c Same as C2 C17 c Same as C2 C18 c Same as C2 C19 c Same as C2 C20 c Same as C2 C21 c Same as C2 C22 c Same as C2 C23 c Same as C2 C24 c Same as C1 C25 c Same as C1 C26 c Same as C1 C27 c Same as C2 C28 c Same as C2 C29 c Same as C2 C30 c Same as C2 C31 c CAPACITOR, FIXED, MICA DIELECTRIC: 10 pF ± 10%; 300 V; Ml L-C-39001/5 81349 CMR03C100- DOCM 8-36 Table 8-1. Parts List (Continued) PARTS LIST Ref Des *•> c 9 "O c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes C32 C CAPACITOR, FIXED, CERAMIC DIELECTRIC: 470 pF ±10%; 200 V; MIL-C-39014/1 81349 M39014/01-1231 C33 C CAPACITOR, FIXED, MICA DIELECTRIC: 27 pF ±5%; 50 V; MIL-C-39001/5 81349 CMR03E270- JOYM CR1 C SEMICONDUCTOR DEVICE, DIODE: Transient voltage suppressor, 12 V minimum breakdown voltage, 53.7 A maximum peak pulse current (Electrodynamics 7030040-2) 12969 TVS512 CR2 C Same as CR1 CR3 C SEMICONDUCTOR DEVICE, DIODE: Transient voltage suppressor, 5 V minimum breakdown voltage, 23.8 A maximum peak pulse current (Electrodynamics 7030040-1) 12969 TVS505 CR4 C SEMICONDUCTOR DEVICE, DIODE: Zener; 5.1 V; 400 MW; MIL-S-19500/127F 81349 JAN1N757A MP1 c PRINTED WIRING BOARD 10236 6260064-1 MP2 c INJECTOR/EJECTOR (Electrodynamics 8501044-1) 22589 NE-3001-W Q1 c TRANSISTOR: MILS- 19500/3 17 81349 JAN2N2369A Q2 c Same as Q1 R1 c RESISTOR, FIXED, COMPOSITION: 10 ohms ±5%; 1/4 W;M I L-R -39008/1 81349 RCR07G100JS R2 c Same as R1 R3 c Same as R1 R4 c Same as R1 R5 c Same as R1 R6 c Same as R1 R7 c Same as R1 R8 c Same as R1 R9 c Same as R1 R10 c Same as R1 R11 c Same as R 1 R12 c Same as R1 R13 c Same as R1 R14 c Same as R1 R15 c Same as R1 R16 c Same as R1 R17 c RESISTOR, FIXED, COMPOSITION: 220 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G221JS R18 c Same as R17 8-37 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R19 c RESISTOR, FIXED, COMPOSITION: 1,000 ohms ±5%; 1/4 W; Ml L-R -39008/1 81349 RCR07G102JS R20 C Same as R17 R21 C Same as R17 R22 C RESISTOR, FIXED, COMPOSITION: 750 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G751JS R23 C Same as R17 R24 c Same as R17 R25 c Same as R22 R26 c Same as R19 R27 c Same as R17 R28 c Same as R17 R29 c RESISTOR, FIXED, COMPOSITION: 110ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G111JS R30 c Same as R22 R31 c RESISTOR, FIXED, COMPOSITION: 3,900 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G392JS R32 c Same as R29 R33 c RESISTOR, FIXED, COMPOSITION: 10,000 ohms ±5%; 1 /4 W; Ml L-R-39008/1 81349 RCR07G103JS R34 c Same as R 19 R35 c RESISTOR, FIXED, COMPOSITION: 680 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G681JS R36 c RESISTOR, FIXED, COMPOSITION: 8,200 ohms ±5%; 1/4W; Ml L-R-39008/1 81349 RCR07G822JS R37 c Same as R36 R38 c RESISTOR, FIXED, COMPOSITION: 5,100 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G512JS R39 c Same as R36 R40 c RESISTOR, FIXED, COMPOSITION: 62,000 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G623JS R41 c RESISTOR, FIXED, COMPOSITION: 150 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G151JS R42 c RESISTOR, FIXED, COMPOSITION: 470 ohms ±5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G471JS TP1 c TEST POINT: Black; Ml L-C-39024/1 1 81349 M39024/11-03 TP2 c TEST POINT: Purple; Ml L-C-39024/1 1 81349 M39024/11-10 TP3 c TEST POINT: Red; Ml L-C-39024/1 1 81349 M39024/11-02 TP4 c TEST POINT: White; Ml L-C-39024/1 1 81349 M39024/11-01 TP5 c Same as TP4 8-38 Table 8-1. Parts List (Continued) PARTS LIST Ref Des «-> c 5 ■o Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes TP6 C Same as TP4 TP7 C Same as TP4 TP8 C Same as TP4 TP9 C Same as TP3 TP10 C Same as TP4 TP11 C Same as TP4 U1 C IC, QUADRUPLE DUAL IN-LINE (Electrodynamics 7100456-1) 04713 MHQ6001 U2 c Same as U1 U3 c Same as U1 U4 c Same as U1 U5 c IC, 9-BIT ODD/EVEN PARITY GENERATOR/ CHECKER (Electrodynamics 7100356-1) 18324 S54LS280F/883B U6 c IC, PARALLEL LOAD 8-BIT SHIFT REGISTER (Electrodynamics 7100346-1) 18324 S54LS165F/883B U7 c Same as U6 U8 c IC, CMOS ANALOG MULTIPLEXER (Electrodynamics 7100455-1) 34371 HI-1818A-8 U9 c IC, HIGH SPEED VOLTAGE COMPARATOR (Electrodynamics 7100454-1) 07263 jiiA760HMQB U10 c IC, LOW POWER SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) (Electrodynamics 7100273-1) 18324 S54LS240F/883B U11 c IC, LOW POWER SCHOTTKY OCTAL BUFFER (3-STATE) (Electrodynamics 7100268-1) 27014 DM54LS244J/883E ! U12 c Same as U10 U13 c IC, LOW POWER SCHOTTKY 4-BIT BINARY COUNTER (Electrodynamics 7100155-1) 18324 S54LS161F/883B U14 c IC, LOW POWER SCHOTTKY DUAL 4-INPUT POSITIVE NAND GATE (Electrodynamics 71 001 41-1) 18324 S54LS20F/883B U15 c Same as U13 U16 c IC, BCD DECODER (Electrodynamics 7100363-1) 01295 SNC5445J U17 c IC, LOW POWER SCHOTTKY TRIPLE 3-INPUT POSITIVE NAND GATE (Electrodynamics 7100139-1) 18324 S54LS10F/883B U18 c IC, QUADRUPLE 2-INPUT POSITIVE - NAND SCHMITT TRIGGER (Electrodvnamics 7100364-1) 27014 DM54LS132J/883B 8-39 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c ■o Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U19 C IC, LOW POWER SCHOTTKY HEX INVERTER (Electrodynamics 7100137-1) 18324 S54LS04F/883B U20 C IC, MONOSTABLE MULTIVIBRATOR (Electrodynamics 7100453-1) 01295 SNJ54123J U21 C IC, LOW POWER SCHOTTKY DUAL D-TYPE TRIGGERED FLIP-FLOP (Electrodynamics 7100145-1) 18324 S54LS74F/883B U22 C Same as U13 U23 C IC, SCHOTTKY HEX INVERTER (Electrodynamics 7100120-1) 18324 S54S04F/883B XQ1 C TRANSISTOR PAD: TO-5 10236 8290009-1 XQ2 C Same as XQ1 XU1 C CONNECTOR, IC SOCKET: 14 pins; low profile (Electrodynamics 7180132-2) 00779 641261-1 XU2 C Same as XU1 XU3 C Same as XU1 XU4 C Same as XU1 XU5 c Same as XU1 XU6 c CONNECTOR, IC SOCKET: 16 pins; low profile (Electrodynamics 7180132-3) 00779 641262-1 XU7 c Same as XU6 XU8 c Same as XU6 XU9 c SPREADER, IC SOCKET: 8 pins; 0.400 inch centers (Electrodynamics 8290013-1 ) 32559 700-130 XU10 c CONNECTOR, IC SOCKET: 20 pins; low profile (Electrodynamics 7180132-5) 00779 641264-1 XU11 c SameasXUlO XU12 c Same as XU10 XU13 c Same as XU6 XU14 c Same as XU1 XU15 c Same as XU6 XU16 c Same as XU6 XU17 c Same as XU1 XU18 c Same as XU1 XU19 c Same as XU1 XU20 c Same as XU6 XU21 c Same as XU1 XU22 c Same as XU6 8-40 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) ■D C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes XU23 C SameasXUI C CRYSTAL: 14.318180 MHz; Ml L-C-39098/42 81349 CR64/U14.31818MHz 8-41 Table 8-1. Parts List (Continued] PARTS LIST Ref Des c 0) C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A2-A9 C INPUT BUFFER WSR-74 CCA 10236 4260063A1 C1 Not Used C2 Not Used C3 Not Used C4 c CAPACITOR, FIXED, MICA DIELECTRIC: 400 pF ± 5%; 50 V; MIL-C-39001/1 81349 CMR03F401- JOYM C5 c CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 idF ± 10%; 50 V; Ml L-C-39014/01 81349 M39014/01-1473 C6 Not Used C7 c Same as C5 C8 c Same as C5 C9 Not Used C10 c Same as C5 C11 Not Used C12 c Same as C5 C13 Not Used C14 c Same as C5 C15 Not Used C16 c Same as C5 C17 Not Used C18A c Same as C5 C18B c Same as C5 C19 Not Used C20A c Same as C5 C20B c Same as C5 C21 Not Used C22A c Same as C5 C22B c Same as C5 C23 Not Used C24A c Same as C5 C24B c Same as C5 C25 Not Used C26A c Same as C5 C26B c Same as C5 C27A c Same as C5 C27B c Same as C5 8-42 ^ Table 8-1. Parts List (Continued) PARTS LIST Ref Des *■> c 5 ■o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes C28A C Same as C5 C28B C Same as C5 C29 Not Used C30A C Same as C5 C30B C Same as C5 C31 Not Used C32A C Same as C5 C32B C Same as C5 C33 Not Used C34A C Same as C5 C34B c Same as C5 C35 Not Used C36A c Same as C5 C36B c Same as C5 C37A c Same as C5 C37B c Same as C5 C38 c CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 1.2juF ± 10%; 20 V; MIL-C-39003/01 81349 M39003/01-2279 C39 c Same as C38 CR1 c SEMICONDUCTOR DEVICE, DIODE: Transient voltage suppressor, 5 V minimum breakdown voltage, 23.8 A maximum peak pulse current (Electrodynamics 7030040-1) 12969 TVS505 CR2 c Same as CR1 MP1 c PRINTED WIRING BOARD (Electrodynamics 6260063) 10236 6260063-1 MP2 c INJECTOR/EJECTOR (Electrodynamics 8501044-1) 22589 NE-3001-W Q1 c TRANSISTOR, NPN: T05; MIL-S-195001/255E 81349 JAN2N2222A R1 c RESISTOR, FIXED, COMPOSITION: 8,200 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G822JS R2 c RESISTOR, FIXED, COMPOSITION: 5,600 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G562JS R3 c RESISTOR, FIXED, COMPOSITION: 1,600 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G162JS R4 c RESISTOR, FIXED, COMPOSITION: 75 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G750JS R5 c RESISTOR, FIXED, COMPOSITION: 12,000 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G123JS 8-43 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R6 C RESISTOR, FIXED, COMPOSITION: 56,000 ohms ± 5%; 1/4 W; MIL-R-39008/11 81349 RCR07G563JS R7 C Same as R2 R8 c Same as R5 R9 Not Used R10 c Same as R2 R11 c Same as R2 R12 c Same as R2 R13 c RESISTOR, FIXED, COMPOSITION: 430 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G431JS R14 c RESISTOR, FIXED, FILM: 21,500 ohms ± 1%; 1/8W;MIL-R-55182/3 81349 RNC60H2152FS R15 c RESISTOR, FIXED, COMPOSITION: 3,600 ohms ±5%; 1/4 W; MIL-R-39008/11 81349 RCR07G362JS R16 c RESISTOR, VARIABLE, NON-WIRE-WOUND: 20,000 ohms; 1/2 W; MIL-R-39935/2 81349 RJR24FX203P R17 c Same as R1 R18 c Same as R1 R19 c RESISTOR, FIXED, COMPOSITION: 240 ohms ± 5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G241JS R20 c Same as R19 R21 c Same as R1 R22 c RESISTOR, FIXED, COMPOSITION: 330 ohms ± 5%; 1/4 W; Ml L-R-39008/1 81349 RCR07G331JS R23 Not Used R24 c Same as R 1 R25 c Same as R2 R26 c Same as R2 R27 c Same as R2 R28 c Same as R2 R29 c Same as R2 R30 c Same as R2 R31 c Same as R2 R32 c Same as R2 R33 c Same as R2 R34 c Same as R2 R35 c Same as R22 R36 c Same as R22 8-44 ^ Table 8-1. Parts List (Continued) PARTS LIST Ref Des *•> c 6 •o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R37 C Same as R22 R38 C Same as R22 R39 C Same as R22 R40 C Same as R22 R41 C Same as R22 R42 C Same as R22 R43 C Same as R22 R44 C Same as R22 R45 C Same as R2 R46 C Same as R2 R47 c Same as R2 R48 c RESISTOR, FIXED, COMPOSITION: 2,200 ohms ± 5%; 1/4 W; Ml L-R -39008/1 81349 RCR07G222JS R49 c Same as R2 R50 c Same as R2 R51 c Same as R2 R52 c Same as R2 R53 c Same as R2 R54 c Same as R2 R55 c Same as R22 R56 c Same as R22 R57 c Same as R19 R58 c Same as R22 R59 c Same as R22 R60 c Same as R22 R61 c Same as R22 R62 c Same as R22 R63 c Same as R22 R64 c Same as R22 R65 c Same as R2 R66 c Same as R2 R67 c Same as R2 R68 c Same as R2 R69 c Same as R2 R70 c Same as R2 R71 c Same as R2 R72 c Same as R2 8-45 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c •a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R73 C Same as R2 R74 C Same as R2 R75 c Same as R22 R76 c Same as R22 R77 c Same as R22 R78 c Same as R22 R79 c Same as R22 R80 c Same as R22 R81 c Same as R22 R82 c Same as R22 R83 c Same as R22 R84 c Same as R22 R85 c Same as R2 R86 c Same as R2 R87 c Same as R2 R88 c Same as R2 R89 c Same as R2 R90 c Same as R2 R91 c Same as R2 R92 c Same as R2 R93 c Same as R2 R94 c Same as R2 R95 c Same as R22 R96 c Same as R22 R97 c Same as R22 R98 c Same as R22 R99 c Same as R22 R100 c Same as R22 R101 c Same as R22 R102 c Same as R22 R103 c Same as R22 R104 c Same as R22 R105 c RESISTOR, FIXED, COMPOSITION: 1,000,000 ohms ± 5%; 1/4 W; M I L-R -39008/1 81349 RCR07G105JS TP1 c TEST POI NT: White; M I L-C-39024/1 1 81349 M39024/11-01 TP2 c Same as TP1 8-46 k Table 8-1. Parts List (Continued) PARTS LIST Ret Des *-> c fi •o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes TP3 C Same as TP1 TP4 C TEST POINT: Red; Ml L-C-39024/1 1 81349 M39024/11-02 TP5 C TEST POINT: Orange; Ml L-C-39024/1 1 81349 M39024/11-06 TP6 C TEST POINT: Black; MfL-C-39024/1 1 81349 M39024/11-03 TP7 C TEST POINT: Brown; Ml L-C-39024/1 1 81349 M39024/11-04 U1 c IC, DUAL OPTO COUPLER (Electrodynamics 7040045-1) 50434 HCPL-2531 U2 c Same as U1 U3 c IC, HEX BUFFER DRIVE (Electrodynamics 7100357-1) 01295 SNC5407J U4 c IC, MONOSTABLE MULTIVIBRATOR (Electrodynamics 7100318-1) 01295 SNC54121J U5 c IC, LOW POWER SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) (Electrodynamics 7100273-1) 18324 S54LS240F/883B U6 c IC, OCTAL D-TYPE TRANSPARENT LATCH AND EDGE TRIGGERED FLIP-FLOP (Electrodynamics 7100360-1) 18324 S54LS373F/883B U7 c Same as U6 U8 c IC, LOW POWER SCHOTTKY NON-INVERTING OCTAL BUFFER (3-STATE) (Electrodynamics 7100268-1) 27014 DM54LS244J/883E I U9 c Same as U6 U10 c Same as U6 U11 c IC, LOW POWER SCHOTTKY HEX SCHMITT TRIGGER INVERTER (Electrodynamics 7100140-1) 18324 S54LS14F/883B U12 c Same as U11 U13 c Same as U11 U14 c Same as U11 U15 c Same as U1 1 U16 c Same as U11 U17 c Same as U11 U18 c Same as U1 U19 c Same as U1 U20 c Same as U1 U21 c Same as U1 U22 c Same as U1 U23 c Same as U1 8-47 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c a> ■a c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U24 C Same as U1 U25 C Same as U1 U26 c Same as U1 U27 c Same as U1 U28 c Same as U1 U29 c Same as U1 U30 c Same as U1 U31 c Same as U1 U32 c Same as U1 U33 c Same as U1 U34 c Same as U1 U35 c Same as U1 U36 c Same as U1 U37 c Same as U1 U38 c IC, VOLTAGE COMPARATOR (Electrodynamics 7100159-1) 27014 LM111J/883B XQ1 c TRANSISTOR PAD: TO-5 10236 8290009-1 XU1 c CONNECTOR, IC SOCKET: 8 pins; low profile (Electrodynamics 7180132-1) 00779 641260-1 XU2 c Same as XU1 XU3 c CONNECTOR, IC SOCKET: 14 pins; low profile (Electrodynamics 7180132-2) 00779 641261-1 XU4 c Same as XU3 XU5 c CONNECTOR, IC SOCKET: 20 pins; low profile (Electrodynamics 7180132-5) 00779 641264-1 XU6 c Same as XU5 XU7 c Same as XU5 XU8 c Same as XU5 XU9 c Same as XU5 XU10 c Same as XU5 XU11 c Same as XU3 XU12 c Same as XU3 XU13 c Same as XU3 XU14 c Same as XU3 XU15 c Same as XU3 XU16 c Same as XU3 XU17 c Same as XU3 8-48 Table 8-1. Parts List (Continued) PARTS LIST Ref Des *-> c S ■o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes XU18 C Same as XU1 XU19 C Same as XU1 XU20 C Same as XU1 XU21 C Same as XU1 XU22 C Same as XU1 XU23 C Same as XU1 XU24 C Same as XU1 XU25 C Same as XU1 XU26 C Same as XU1 XU27 C Same as XU1 XU28 c Same as XU1 XU29 c Same as XU1 XU30 c Same as XU1 XU31 c Same as XU1 XU32 c Same as XU1 XU33 c Same as XU1 XU34 c Same as XU1 XU35 c Same as XU1 XU36 c SameasXUI XU37 c Same as XU1 XU38 c SPREADER, IC SOCKET: 8 pins; 0.400 inch centers; TO-92 32559 700-130 (Electrodynamics 829001 3-1 ) 8-49 Table 8-1. Parts List (Continued) PARTS LIST Ref Des E 0) "O Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1A2- A10 B INPUT BOARD WSR57 CCA 10236 42 60063 A2 C1 Not Used C2 Not Used C3 Not Used C4 C CAPACITOR, FIXED, MICA DIELECTRIC: 400 pF ± 5%; 50 V; MIL-C-39001/1 81349 CMR03F401- JOYM C5 C CAPACITOR, FIXED, CERAMIC DIELECTRIC: 0.1 mF ± 10%; 50 V; MIL-C-39014/01 81349 M39014/01-1473 C6 Not Used C7 Not Used C8 C Same as C5 C9 Not Used C10 Not Used C11 Not Used C12 C Same as C5 C13 Not Used C14 C Same as C5 C15 Not Used C16 Not Used C17 Not Used C18A C Same as C5 C18B C Same as C5 C19 Not Used C20 Not Used C21 Not Used C22 Not Used C23 Not Used C24A C Same as C5 C24B C Same as C5 C25 Not Used C26 Not Used C27 Not Used C28A C Same as C5 C28B C Same as C5 C29 Not Used C30 Not Used 8-50 Table 8 1. Parts List (Continued) PARTS LIST Ref Des *-> c 8 "O c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes C31 Not Used C32 Not Used C33 Not Used C34 Not Used C35 Not Used C36 Not Used C37 Not Used C38 C CAPACITOR, FIXED, ELECTROLYTIC: tantalum; 1.2/xF ± 10%; 20 V; MIL-C-39003/01 81349 M39003/01-2279 C39 C Same as C38 CR1 CR2 C C SEMICONDUCTOR DEVICE, DIODE: transient voltage suppressor, 5V minimum breakdown voltage, 23.8 A maximum peak pulse current (Electrodynamics 7030040-1) Same as CR1 12969 TVS505 MP1 C PRINTED WIRING BOARD 10236 6260063-1 MP2 C INJECTOR/EJECTOR (Electrodynamics 8501044-1) 22589 NE-3001-W Q1 C TRANSISTOR: NPN; TO-5; MIL-S-195001/255E 81349 JAN2N2222A R1 c RESISTOR, FIXED, COMPOSITION: 8,200 ohms ± 5%; 1 /4 W; Ml L-R-39008/1 1 81349 RCR07G822JS R2 c RESISTOR, FIXED, COMPOSITION: 5,600 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G562JS R3 c RESISTOR, FIXED, COMPOSITION: 1,600 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G162JS R4 c RESISTOR, FIXED, COMPOSITION: 75 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G750JS R5 c RESISTOR, FIXED, COMPOSITION: 12,000 ohms ± 5%; 1/4 W; Ml L-R-39008/1 1 81349 RCR07G123JS R6 c RESISTOR, FIXED, COMPOSITION: 56,000 ohms ± 5%; 1/4W; Ml L-R-39008/1 1 81349 RCR07G563JS R7 c Same as R2 R8 c Same as R5 R9 Not Used R10 Not Used R11 Not Used R12 Not Used 8-51 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) ■D Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R13 C RESISTOR, FIXED, COMPOSITION: 430 ohms ± 5%; 1 /4 W; M I L-R -39008/1 1 81349 RCR07G431JS R14 c RESISTOR, FIXED, FILM: 21,500 ohms ± 1%; 1/8W;MIL-R-55182/3 81349 RNC60H2152FS R15 c RESISTOR, FIXED, COMPOSITION: 3,600 ohms ± 5%; 1/4 W; MIL-R-39008/1 81349 RCR07G362JS R16 c RESISTOR, VARIABLE, NON-WIRE-WOUND: 20,000 ohms; 1/2 W; MIL-R-39035/2 81349 RJR24FX203P R17 c Same as R1 R18 c Same as R1 R19 c RESISTOR, FIXED, COMPOSITION: 240 ohms ± 5%; 1/4 W; MIL-R-39008/1 1 81349 RCR07G241JS R20 c Same as R19 R21 c Same as R1 R22 c RESISTOR, FIXED, COMPOSITION: 330 ohms ±5%; 1/4 W; MIL-R-39008/1 81349 RCR07G331JS R23 Not Used R24 c Same as R1 R25 c Same as R2 R26 c Same as R2 R27 c Same as R2 R28 c Same as R2 R29 Not Used R30 Not Used R31 Not Used R32 Not Used R33 Not Used R34 Not Used R35 c Same as R22 R36 c Same as R22 R37 c Same as R22 R38 c Same as R22 R39 Not Used R40 Not Used R41 Not Used R42 Not Used R43 Not Used R44 Not Used 8-52 Table 8-1. Parts List (Continued) ) PARTS LIST Ref Des *-< c •D C Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R45 C Same as R2 R46 c Same as R2 R47 c Same as R2 R48 c RESISTOR, FIXED, COMPOSITION: 2,200 ohms ± 5%; 1/4 W; Ml L-R -39008/1 81349 RCR07G222JS R49 Not Used R50 Not Used R51 Not Used R52 Not Used R53 Not Used R54 Not Used R55 c Same as R22 R56 c Same as R22 R57 c Same as R19 R58 c Same as R22 R59 Not Used R60 Not Used R61 Not Used R62 Not Used R63 Not Used R64 Not Used R65 c Same as R2 R66 c Same as R2 R67 Not Used R68 Not Used R69 Not Used R70 Not Used R71 Not Used R72 Not Used R73 Not Used R74 Not Used R75 c Same as R22 R76 c Same as R22 R77 Not Used R78 Not Used R79 Not Used R80 Not Used 8-53 Table 8-1. Parts List (Continued) PARTS LIST Ref Des +■» c 03 ■o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes R81 Not Used R82 Not Used R83 Not Used R84 Not Used R85 c Same as R2 R86 C Same as R2 R87 Not Used R88 Not Used R89 Not Used R90 Not Used R91 Not Used R92 Not Used R93 Not Used R94 Not Used R95 C Same as R22 R96 C Same as R22 R97 Not Used R98 Not Used R99 Not Used R100 Not Used R101 Not Used R102 Not Used R103 Not Used R104 Not Used R105 C RESISTOR, FIXED, COMPOSITION: 1,000,000 ohms ± 5%; 1/4 W; MIL-R-39008/1 81349 RCR07G105JS TP1 C TEST POINT: White; Ml L-C-39024/1 1 81349 M39024/11-01 TP2 C Same as TP1 TP3 C Same as TP1 TP4 C TEST POINT Red; Ml L-C-39024/1 1 81349 M39024/11-02 TP5 C TEST POINT Orange; M I L-C-39024/1 1 81349 M39024/11-06 TP6 c TEST POINT Black; M I L-C-39024/1 1 81349 M39024/11-03 TP7 c TEST POINT Brown; M I L-C-39024/1 1 81349 M39024/11-04 U1 c IC, DUAL OPTO COUPLER (Electrodynamics 7040045-1) 50434 HCPL-2531 U2 c Same as U1 U3 Not Used 8-54 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 6 ■o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U4 Not Used U5 C IC, LOW POWER SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) (Electrodynamics 7100273-1) 18324 S54LS240F/883B U6 Not Used U7 Not Used U8 C Same as U5 U9 Not Used U10 Not Used U11 Not Used U12 C IC, LOW POWER SCHOTTKY HEX SCHMITT TRIGGER INVERTER (Electrodynamics 7100140-1) 18324 S54LS14F/883B U13 C Same as U12 U14 C Same as U12 U15 Not Used U16 Not Used U17 Not Used U18 C Same as U1 U19 C Same as U1 U20 Not Used U21 Not Used U22 Not Used U23 c Same as U1 U24 c Same as U1 U25 Not Used U26 Not Used U27 Not Used U28 c Same as U1 U29 Not Used U30 Not Used U31 Not Used U32 Not Used U33 c Same as U1 U34 Not Used / U35 Not Used U36 Not Used 8-55 Table 8-1. Parts List (Continued] PARTS LIST Ref Des T3 Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes U37 Not Used U38 C IC, VOLTAGE COMPARATOR, TO-92 (Electrodynamics 7100159-1) 07236 MAF111HMQB XQ1 c TRANSISTOR PAD: TO-5 10236 8290009-1 XU1 c CONNECTOR, IC SOCKET: 8 pins; low profile (Electrodynamics 7180132-1 ) 00779 641260-1 XU2 c Same as XU1 XU3 Not Used XU4 Not Used XU5 c CONNECTOR, IC SOCKET: 20 pins; low profile (Electrodynamics 7180132-5) 00779 641264-1 XU6 Not Used XU7 Not Used XU8 c Same as XU5 XU9 Not Used XU10 Not Used XU11 Not Used XU12 c CONNECTOR, IC SOCKET: 14 pins; low profile (Electrodynamics 7180132-2) 00779 641261-1 XU13 c Same as XU12 XU14 c Same as XU12 XU15 Not Used XU16 Not Used XU17 Not Used XU18 c Same as XU1 XU19 c Same as XU1 XU20 Not Used XU21 Not Used XU22 Not Used XU23 c Same as XU1 XU24 c Same as XU1 XU25 Not Used XU26 Not Used XU27 Not Used XU28 c Same as XU1 XU29 Not Used XU30 Not Used 8-56 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) ■o c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes XU31 XU32 XU33 XU34 XU35 XU36 XU37 XU38 Not Used Not Used Same as XU1 Not Used Not Used Not Used Not Used SPREADER, IC SOCKET: 8 pins; 0.400 inch centers; TO-92 (Electrodynamics 8290013) 32559 700-130 8-57 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1N2- A11 J1 J2 MP1 EXTENDER CARD CCA CONNECTOR, ELECTRICAL (Electrodynamics 7180127-1) Same as J1 PRINTED WIRING BOARD 10236 05574 10236 42 60080 A 1 3VH36-1JN015- 083 6260080-1 8-58 Table 8-1. Parts List (Continued) PARTS LIST Ref Des c 0) c Name of Part/Description Mfr Code JAN/MIL Mfr Part No. Notes N1N2 C BACKPLANE ASSEMBLY 10236 4260068A1 A12 E1 D STUD, TERMINAL 96906 MS17121-6 E2 D Same as E1 E3 D Same as E1 E4 D Same as E1 E5 D Same as E1 E6 D Same as E1 E7 D Same as E1 E8 D Same as E1 E9 D Same as E1 E10 D Same as E1 E11 D Same as E1 E12 D Same as E1 E13 D Same as E1 E14 D Same as E1 E15 D Same as E1 E16 D Same as E1 MP1 D PRINTED WIRING BOARD 10236 6260068-1 MP2 D GUIDE, CARD (Electrodynamics 8501042-2) 32559 DC-450 S1 D SWITCH, MICRO (Electrodynamics 7152055-1) 91929 BZ-2RW80-D5 S2 D Same as S1 TB1 D TERMINAL BLOCK (Electrodynamics 8240059-2) 33333 4PCV-04-002 XU1 D CONNECTOR, IC SOCKET: 72 pins, low profile (Electrodynamics 7180125-1) 00779 3-583715-4 XU2 D CONNECTOR, IC SOCKET: 50 pins, low profile (Electrodynamics 7180146-02) 71787 DD-50PV 8-59 Table 8-2. List of Manufactu rers Mfr Manufacturer Mfr Manufacturer Code Code 00779 Amp Inc. 24229 Geo. Risk Industries P.O. Box 3608 802 S. Elm Harrisburg, PA 17105 Kimball, NE 69145 02735 RCA Corp. 27014 National Solid State Division 2900 Semiconductor Drive Route 202 Santa Clara, CA 95051 Somerville, NJ 08876 28480 Hewlett-Packard Co. 04713 Motorola Corporate Headquarters 5005 E. McDowell Road 1501 Page Mill Road Phoenix, AZ 85008 Palo Alto, CA 94304 06383 Panduit Corp. 30161 Aavid Engineering Inc. 17301 Ridgeland 30 Cook Court Tinley Park, IL 60477 Laconia, NH 03246 07263 Fairchild 34333 Silicon General Inc. Mountain View, CA 94042 7382 Bolsa Avenue Westminister, CA 92683 07933 Raytheon Co. Semiconductor Div. Hq. 34355 AMD 350 Ellis Street Sunnyvale, CA Mountain View, CA 94042 34649 Intel 10236 Electrodynamics Inc. 1200 Hicks Road Santa Clara, CA 95051 Rolling Meadows, IL 60008 46384 Penn Engineering & Manufacturing Corp. 11982 TRW P.O. Box 311 Redondo Beach, CA Doylestown, PA 18901 12969 Unitrode Corp. 56289 Spraque Electric Co. 580 Pleasant Street North Adams, MA 01247 Watertown, MA 02172 70674 ADC Products Div. 18324 Signetics Magnetic Controls Co. 811 E. Arques 4900 West 78th Street Sunnyvale, CA 94086 Minneapolis, MN 55435 22589 Electro-Space Fabricators, Inc. 71400 Bussman Manufacturing Div. Centrel Avenue McGraw-Edison Co. Topton, PA 19562 502 Earth City Plaza P.O. Box 14460 St. Louis, MO 63178 8-60 Table 8-2. List of Manufacturers (Continued) Mfr Code Manufacturer Mfr Code Manufacturer 71590 Centralab Electronics Division of Globe-Union Inc. P.O. Box 858 Hwy 20 W Fort Dodge, IA 50501 81349 Military Specifications Promulgated by Military Departments/Agencies under Authority of Defense Standardization Manual 4120 3-M Rotron Inc. 7-9 Hasbrouck Lane Woodstock, NY 12498 86928 94222 95146 95263 Seastrom Manufacturing Co., Inc. 701 Sonora Avenue Glendale, CA 91201 Southco Inc. Lester, PA 19113 Alco Electronic Products Inc. P.O. Box 1348 Lawrence, MA 01842 Leecraft Manufacturing Co., Inc. 21-16 44th Road Long Island City, NY 11101 8-61/8-62 « SECTION 9. INSTALLATION, INTEGRATION. AND CHECKOUT 9.1 INTRODUCTION. This section contains information pertinent to the installation of the Isolation Distribution Equipment (IDE). 9.2 UNPACKING AND HANDLING. -- Each IDE is packaged separately to provide maximum protection and ease of shipping by rail, truck, or ship. Precautionary procedures for the normal handling of delicate (fragile) electronic equipment are applicable. After unloading and removing the equipment from its shipping containers, examine it for shipping damage, particularly if a container shows such signs. If a unit is found to be damaged, do not attempt to operate it. The packing case containing the IDE unit should be handled and opened with care. Inspect these units for shipping damage, and check packing slip to ensure complete shipment. The IDE is shipped with cables and spare cards. After receiving the unit, carefully unpack it and inspect the unit for visible signs of damage. Do not open the front panel at this point. The unit should be mounted on the wall before opening. This is to insure that no cards will fall out. How the unit will be mounted to the wall will be determined at the site. The unit should be located within ten feet of a standard three wire, 120 volt, electric outlet. The cabling for the IDE is fifty feet long. This will also be a factor as to where the IDE will be mounted. Inventory of Installation Kit, Part Number 1 130065 and a list of spare parts are listed in table 1-2. 9.3 POWER REQUIREMENTS. - The IDE requires a power source of 105-125 Vac, 60 ± 2 Hz, single phase. 9.4 ISOLATION. The IDE is electrically isolated from all other equipment by the use of isolation transformers or optical isolators on all inputs and outputs. User's equipment has to be isolated optically. 9.5 INSTALLATION PROCEDURES. 9.5.1 Wall Mounting. — Figure 9-1 shows a typical wall-mount installation. Use the appropriate sup- plied hardware depending on whether the IDE is to be mounted on a mason, wood, plaster, or wallboard surface. 1. Locate four holes on a wall on which the IDE is to be mounted. To do this, select one locator hole, then measure center-to-center for the remaining three holes, making sure the equipment will be level when mounted. Recommended height is to locate the top holes 72 inches from the floor. 2. Using appropriate hardware, mount the unit on the wall. Appropriate hardware is supplied with each IDE. 9.5.2 Installation Check.— Once the unit is mounted on the wall in an upright position, the front panel can be opened. This is done by turning the 5 screws on the right one-quarter turn to the left (counterclockwise). Carefully open the door and remove the packing material used to support the cards during shipment. Examine the inside of the unit (also the cards) for any visual damage. 9.5.3 Special Instructions. 9.5.3.1 WSR-57. 1. On the Input Buffer CCA N1A2A9, verify the following jumper positions: E3 and E4 - in; E2 - out E7 and D8 - in; E1 1 and E12 - out 9-1 /^ © © © © © © © ^ o o o ^ ® ® J o Figure 9-1. Typical Wall-Mount Installation 9-2 E9 and E10 in; E5 and E6 out E13 and E14 in; E15 and E16 - out 2. Verify that IC A9U8 is a 54LS240, not a 54LS44. 9.5.3.2 WSR-74C. 1. On the Input Buffer CCA N1A2A9, verify the following jumper position: E1 and E2 - in; E3 and E4 - out E9 and E10 -in; E5 and E6 - out E1 1 and E1 2 - in; E7 and E8 - out E13 and E14 - in; E15 and E16 - out 2. Verify that IC A9U8 is a 54LS244, not a 54LS240. 3. Check the installation cable (9.5.5). Connect pin CC at the IDE end of the cable to pin FF at the radar end; and vice versa (pin FF to pin CC). 4. Perform modifications 10 and 16 of NWS Engineering Handbook No. 6 for WSR-74C. 9.5.3.3 WSR-74S. 1. Same as step 1 of 9.5.3.2. 2. Same as step 2 of 9.5.3.2. 3. Same as step 3 of 9.5.3.2. 4. Check the installation cable (9.5.5). Connect pin j at the IDE end of the cable to pin DD at the radar end; and vice versa (pin DD to pin j). 5. Perform modifications 13 and 17 of NWS Engineering Handbook No. 6 for WSR-74S. 9.5.4 IDE Wiring. - Refer to 9.5.4.1 for WSR-74 and to 9.5.4.2 for WSR-57. 9.5.4.1 WSR-74 Installation Wiring. — Provided in the installation kit are two 50-foot cables with connectors in place at the IDE end. The coaxial cable is for trigger input, and the shielded multi- conductor cable is for data. Connect both cables to the IDE, and route the cables from this point to the bottom rear of the radar console. Leave appropriate slack for connection 1J2 and 1J12. See figures 9-2 and 9-3 for connector assembly and table 9-1 for pinout and color code. After soldering the connectors, disconnect cables at the IDE, and using an ohmmeter, verify correct pinout. Turn radar power off and connect trigger cable to 1 J 1 2 and data cable to 1J2. Connect IDE end of the cables and return power to the radar. 9.5.4.2 WSR-57 Installation Wiring. — Provided in the installation kit are two 50-foot cables with the connectors in place of the IDE end. The larger of the two multi-conductor cables is for data input, and the smaller cable is for synchro input. Connect both cables to the IDE. Turn radar power off. Route the synchro cable to the rear of the console and through to the front center of the radar console between TB207 and TB209. Lace to existing harness, leaving appropriate slack for connection to TB207 and TB209. See figure 9-4 for connector assembly and table 9-2 for pinout and color code. Route the data cable to the bottom rear of the radar console and up through the interior into the DVIP cabinet via one of the two access holes (see DVIP installation). Leave appropriate slack so that the DVIP drawer may be pulled out to the service position. See figure 9-5 for connector assembly and 9-3 CABLE 8030060 CONNECTOR UG-260C/U ? Figure 9-2. Connector Assembly, WSR-74 System Trigger Cable CABLE 8030059 \~s CONNECTOR MS3II6J-22-55P Figure 9-3. Connector Assembly, WSR-74 Data Cable 9-4 £ TERMINAL, RING LUGS 8240053-1 Figure 9-4. Connector Assembly, WSR-57 Synchro Cable CABLE 8030057 CLAMP AN3057-20 CONNECTOR MS3I06A32-4I4S SEE DETAIL A BUSHING MS3420-8 BUSHING MS3420-I0 BUSHING MS3420-I2 BUSHING MS3420-I6 BUSHING MS3420-20 DETAIL A Figure 9-5. Connector Assembly, WSR-57 Data Cable 9-5 Table 9-1. WSR-74 Connections J2 PIN (Radar Console) SIGNAL J2 PIN (Radar Console) SIGNAL FUNCTION NO. NAME FUNCTION NO. NAME ~A Shield w VOL 6 WHT] B 0.1 BRN] V RTN 6 BLU J C 0.2 GRNj u VOL 5 GRN ] D 0.4 BRN] t RTN 5 WHT j E 0.5 BLUJ s VOL 4 YEL ] F 1.0 BRN] Monitor r RTN 4 WHT j G 2.0 VIO J Computer q VOL 3 ORG ] H 4.0 BRN"] Reg Out p RTN 3 WHT j Antenna J 8.0 GRAJ (8-bit) n VOL 2 RED ] Azimuth K 10.0 RED] m RTN 2 WHT ] Angle L 20.0 ORGj k VOL 1 WHT] M 40.0 RED] (LSB) > N 80.0 YEL J _j RTN 1 BRN j P 100.0 RED] R GG _S 200.0 GRNj h g f 1 BRN] INHIBIT WHT] 0.2 YEL j RETURN BLK J 0.4 BRN] i FF Antenna e d c 0.8 ORG j IFATBPM BLK ] 1.0 BRN] Time Sample BRN j 2.0 RED j Monitor DD Range Coverage BLK ] Elevation b 4.0 BLK ] CC Test Level RED J Angle a 8.0 GRA ] EE Not Used Z Y 10.0 BLK ] 20.0 VIO j N.C. ORG] X 40.0 BLK ] Monitor BB DATA READY BLK j W 80.0 BLU j Computer z VOL 8 (MSB) WHT] V 100.0 BLK ] Reg Out AA y RTN 8 GRA j VOL 7 WHT] U HH 200.0 GRN J (8-bit) INHIBIT BLK ] X RTN 7 VIO J T RETURN YEL j System J12 Trig. V Indicates T wisted Pa r Trigger (Radar Console) 9-6 Table 9-2. WSR-57 Connections J11 PIN (DVIP Cabinet) SIGNAL J11 (DVIP Cabinet) PIN SIGNAL \ FUNCTION NO. NAME FUNCTION NO. NAME J A C7 (MSB) YEL 1 ~p~ C1 RED ] B C7 rtn BLK ] r C1 rtn BRN ] w CO (LSB) RED ] E C6 BLU ] x CO rtn GRN j F K C6 rtn C5 BLK ] BLU | 2 TEST LVL BRN | 3 DATA RDY BLK j L C5 rtn RED v TIME "") R C4 J GRN ~) SAMPLE RED u TIME SAMP. ) Computer S C4 rtn BLK j Monitor rtn YEL 4 DATA RDY J Reg Out Y C3 WHT ] rtn WHT 1 (8-bit) Z g C3 rtn C2 BLK ] RED "I z TEST \ LEVEL RED J rtn h C2 rtn BLK J 6 RANGE -v COVERAGE ORG [ 5 RANGE COVERAGE } J Indicates Twisted Pai — rtn BLK J r ►> RADAR WIRE IDE TERMINAL SIGNAL COLOR/ J11 FUNCTION BLOCK NAME NUMBER PIN ~B207-1 AZ S1 BLK ] A #1 RED j B TB207-2 AZ S2 Synchro TB207-3 TB209-5 EL AZ S3 S1 BLK] C #2 WHT J D Data TB209-6 EL S2 BLK ] E #3 GRN j F TB209-7 EL S3 TB207-6 R1 BLK } G #4 BLU j H TB207-8 R2 TB209-8 SYS TRIG BLK ] I #5 YEL J J _GROUND ] Indicates Twisted Pair CUT OFF BLACK WITHOUT NUMBER AND BROWN - NOT USED 9 9-7 table 9-2 for pinout and color code. After soldering the connectors, disconnect cables at the IDE; and, using an ohmmeter, verify correct point. Connect synchro cable to TB207 and TB209 and the data cable J1 1. Connect IDE end of the cables, and return power to the radar. 9.5.5 Connections. — All cable and mating connectors shall be provided for connection of the distribution equipment to either type radar. Cable distance shall be 50-feet. The system trigger is available at the bottom of the console on both radars. For WSR-74 radars, the remainder of informa- tion is located at the bottom rear of the console on J2 (MS31 16F-22-55P). For WSR-57 the synchro information is in the bottom front of the console on #6 barrier strips. The DVIP information is on top of the console directly out of the DVIP J1 1 (MS3106A-32-414S). Pinout for all signals is located in tables 9-1 and 9-2. 9.6 FINAL CHECKOUT. — Locate the power cord and plug it into the IDE ac power input. Insure that the IDE power switch is off and plug the cord into an ac outlet. The battery charger light should now be on. Turn the main IDE power switch. Verify that all front panel power supply lights are on. 9.6.1 Equipment Turn-On. a. Note that the battery charger lamp is on.* b. Set the power switch ON. 1. Power indication lamp is on.* 2. Two indicating fuse lamps are off. (System will operate with one lamp on. Maintenance is required). 3. All eight power supply voltage status indicator lamps are on. (System will operate if one of each type (i.e., +11V) indicator lamp is on. Maintenance is required.) 4. Status Display — all four characters light with any digit. System may be functional without. Maintenance is required. 9.6.2 Radar Trigger Adjustment. — Open the unut and locate the Input Buffer CCA N1A2A9. Using an oscilloscope, connect the probe (X10) to TP2 signal and TP7 isolated ground. Adjust R16 on the Input Buffer CCA while looking at the scope for a stable trigger pulse waveform. When the trigger pulse waveform is stable, add one turn. This is the only internal ajdustment. Adjustment of the time/date is described in Section 3, Paragraph 3.3.3. 9.6.3 Status Check. — To verify the IDE status, perform the following procedure: a. Set DVIP test/normal switch to TEST. b. Set DVIP time sample switch to 15. c. Set transmitter pulse width to SHORT and IF attenuator (WSR-74) to OFF. d. Set IDE status select switch to SYNC STATUS. Position display on IDE should read FFOO (WSR-74C should indicate FF04 instead of FFOO). e. Set transmitter pulse width to LONG. Position display on IDE should read FF04 for all types of radar. f. Set DVIP test/normal switch to NORM. Observe FF05 on IDE readout. g. Return DVIP test/normal switch to TEST. 9-8 h. Set DVIP time sample switch to 31. Observe FF06 on IDE readout. i. Return DVIP time sample switch to 15. j. For WSR-74 only, turn on IF attenuator and observe FFOC on IDE readout. Set IF attenuator to OFF. k. Verify correct azimuth and elevation. Compare reading. I. Verify DVIP data by injecting internal DVIP test ramp and comparing to the IDE front panel jack with an oscilloscope. Use the IDE front panel trigger jack for triggering. 9-9 O o o B Ul 1- O ut-< <->£ 1- Q < O o< < + 5V ISOL INOI IA II o 3 a 3 o o ■D > m T3 o 0) > c o a O) £ u I c/i CO w 3 D5 9-10 INSTRUCTION BOOK ISOLATION DISTRIBUTION EQUIPMENT VOLUME 2 CONTRACT DOT FA78WA-4211 CONTRACTOR ELECTRODYNAMICS, INC. 1200 HICKS ROAD ROLLING MEADOWS, ILLINOIS 60008 MADE FOR U.S. DEPARTMENT OF COMMERCE NATIONAL WEATHER SERVICE 4 i SECTION 10. TROUBLESHOOTING SUPPORT DATA 10.1 INTRODUCTION. — This section contains parts location illustrations, schematic diagrams, inter connection diagrams, power distribution diagram, and signal flow diagram for the Isolation Distribution Equipment (IDE). FIGURE TITLE PAGE 10-1 IDE Front View with Access Cover in Place (photo) 10-3 10-2 IDE Front View with Access Cover Removed (photo) 10-4 10-3 Control Panel Assembly — Front View, Parts Location 10-5 10-4 Front Panel Assembly — Rear View, Parts Location (Cards Removed) 10-6 10-5 Front Panel Assembly — Rear View, Parts Location (Cards in Place) 10-7 10-6 Connector Panel Assembly, Parts Location 10-8 10-7 Battery Charger CCA N1A1A1 - Component and Wiring Sides 10-9 10-8 Display Mounting Board Assembly, Parts Location (photo) 10-10 10-9 Display Mounting Board No. 2 N1A1A2 - Component and Wiring Side 10-11 10-10 Display Mounting Board No. 1 N1A1A3 - Component and Wiring Side 10-12 10-11 Power Supply CCA N1A2A1/A2 - Component and Wiring Side 10-13 10-12 Synchro Converter CCA N1A2A3/A4 - Component and Wiring Side (photo) 10-14 10-13 Synchro Output CCA N1A2A5 - Component and Wiring Side (photo) 10-15 10-14 DE Receiver CCA N1A2A6 - Component and Wiring Side (photo) 10-16 10-15 Clock/Display CCA N1A2A7 - Component and Wiring Side (photo) 10-17 10-16 DE Transmitter CCA N1A2A8 - Component and Wiring Side (photo) 10-18 10-17 Input Buffer CCA N1A2A9 (4260063A1) - Component and Wiring Side 10-19 10-18 Input Buffer CCA N1A2A9 (4260063A2) - Component and Wiring Side 10-20 10-1 FIGURE TITLE PAGE 10 19 IDE Signal Flow Diagram 10-21 10-20 Battery Charger CCA N1A1A1, Schematic Diagram 10-23 10-21 Display Mounting Board No. 2 N1A1A2, Schematic Diagram 10-25 10-22 Display Mounting Board No. 1 N1A1A3, Schematic Diagram 10-27 10-23 DE Power Assembly and Power Supply CCA N1A2A1/A2, Schematic 10-29 Diagram 10-24 Synchro Converter CCA N1A2A3/A4, Schematic Diagram (3 Sheets) 10-31 10-25 Synchro Output CCA N1A2A5, Schematic Diagram 10-37 10-26 DE Receiver CCA N1A2A6, Schematic Diagram 10-39 10-27 Clock/Display CCA N1A2A7, Schematic Diagram (2 Sheets) 10-41 10-28 DE Transmitter CCA N1A2A8, Schematic Diagram (2 Sheets) 10-45 10-29 Input Buffer CCA N1A2A9, Schematic Diagram (2 Sheets) 10-49 10-30 Backplane Assembly N1A2A12, Interconnect Diagram (5 Sheets) 10-53 10-31 Control Panel to Chassis Interconnecting Wiring List (6 Sheets) 10-63 10-32 Connector Panel to Chassis Interconnecting Wiring List (7 Sheets) 10-69 10-33 Integrated Circuit Data (9 Sheets) 10-77 10-2 c c G C v» Figure 10-1. IDE Front View with Access Cover in Place 10-3 Figure 10-2. IDE Front View with Access Cover Removed 10-4 c o co u o re O- £ CD i> +■« c o >• .a E a> (/> 0) < "55 c re Q. c o o CO 6 3 10-5 s> - - Figure 10-4. Front Panel Assembly - Rear View, Parts Location (Cards Removed) - BATTERY CHARGER ASSY DISPLAY MOUNTING ARD ASSY POWER SUPPLY NO I CCA N1A2A1 SUPPLY NO , N1A2 SLOi OE TRANSMITTER IA2A8 Figure 10-5. Front Panel Assembly — Rear View, Parts Location (Cards in Place) 10-7 c Figure 10-6. Connector Panel Assembly, Parts Location " 10-8 Figure 10-7. Battery Charger CCA N1A1A1 - Component and Wiring Sides 10-9 **->* J> Figure 10-8. Display Mounting Board Assembly, Parts Location (photo) " 10-10 10236 ASSY 426007BA R540 *m R5 IS **5 Figure 10-9. Display Mounting Board No. 2 N1A1A2 - Component and Wiring Side 10-11 10236 ASSY. 4260077AW R540 Atfo R541 r" ris at ri mj R1« < ICII R2 i 9» < R17 - atft / R3 iqii * *1t t iBi R4 * \1B9 ' Rlt («» R5 r*t R20 «» Re : mWr* R21 B» R7 • E*t R22 ! !■■ > R8 ' HI : R23 ■)*;' R * : **• r Rt4 f*» RIO [Bt MM TUB . R\1 IBS * Rt« (01 RW Of fit? m ? R13 mi Rit m RM rvt i ■ OSI«»MO0i(T>^)OO " Figure 10-10. Display Mounting Board No. 1 N1A1A3 — Component and Wiring Side 10-12 Figure 10-11. Power Supply CCA IM1A2A1/A2 - Component and Wiring Side 10-13 t\ - Figure 10-12. Synchro Converter CCA N1A2A3/A4 - Component and Wiring Side (photo) ' 10-14 lit tiii i I f 1 1 ! i f ! « 1 1 i |i i i !!'=!»♦ l|l||l|Ml|l fill *Cjhb8c ^^^^^*^^^^^ 1 1 1 lii!!iili Itilfiiii T I ■ •r + ■ • : • 3 :-• = m jSD XT n ClO HG < « TPi U1* CO C « TP4 u „ A m ^^ *■* TP5 \i ' C II i mm2 C'9 fct urn SB *fc H ^! Figure 10-14. DE Receiver CCA N1A2A6 — Component and Wiring Side (photo) 10-16 aafaaaaaaaaiaaaaaaaaaaia Figure 10-15. Clock/Display CCA N1A2A7 - Component and Wiring Side (photo) 10-17 10236 ASSY. ^S 4260064A1 cJ|w »3 . « t J/0FA9901 °"'v , '•' U , 5w\ wJSBKM^M^^Sii'l 1 II I • * as • * n ._«■■! ■ L ■__. 5 V U? U3M?a 04 "n,| I >isas 1 ^■Ik ^*H ftaUlaT ***m " * *■- *M'-ttJ (|pT~ »j ^ 8bte*4 3S| V- • •■. tMJ I m* ' MM d WmmJLft .... (..... I'tMXWt ■:?.| a " * ■* 'tVnaV * *lr» a^*^^H sUmm • .* --'*. !^W C «K. .*.*.«.! JI2 U1I » "i*|| ■ » ■ **=$9 \ h. : 3f^inJ LL 1 1 • I * • • ""1 UI4 013 »» < tvfi *i . MM uia Pii* *"^ 1 nSnT ? fl ■ ■ win "no ar ........ £> W U20 • • uia uia • 1 • *C?3 "*\ 1 "-- c "1 U17 • IB'. E = ' 1 ■ 1 a. u»i aV_ ^ ^H - Figure 10-16. DE Transmitter CCA N1A2A8 - Component and Wiring Side (photo) ' 10-18 •CHI C38 *»7 R19 H.'l HJO iCI s R4 I» 'B7 Rio FM1 • fKi R8 A12 gjft jggll ES f B f ' £8 F )0 -*i> TPI I>»3 til lit U6. v 1 ■if* • — .. 9BD ntV it ill ^HKHM r <8KmMhI ,-1 t f ML. '•->.-•. «B< * * XST, » • RJ9 Mu < aEu*-R3< act »B 3 « 3 MD' ' R<0 B39 ~WKP'' R* ) » *8Br J "33 '134 143 H4J £ V MB- H44 «46 *> R4? H53 *■' P fl Q I B**°P S IB * '%, 10236 ASSY 4260063A1 § P O R540 & R54 1 oa 03 IS Figure 10-17. Input Buffer CCA IM1A2A9 (4620063A1) — Component and Wiring Side 10-19 T D M vA ' ' hj. ii« ' >. V. < r 9*1 m 10236 ASSY 4260063A A P O R540 & RS4 1 oS 1 »* 7 «*> «»» i Figure 10-18. Input Buffer CCA N1A2A9 (4260063A2) - Component and Wiring Side ~ 10-20 k INTEGRATED CIRCUIT ELEMENT DATA Figure 10-34 provides integrated circuit charts for covering all unique integrated circuits (ICs) used by the RRWDS. These diagrams show the logical function performed by the IC and relate the function to the physical terminals. The following list provides cross-reference between Electrodynamics part numbers to IC type and gives a description of the IC. The number in parentheses in the "IC Type" column is the commonly recognizable number. For example, 8086 is functionally the same as S4151. This IC was assigned the number S4151 because of more rigid testing requirements. ► 10-75/10/76 A ELECTRODYNAMICS IC PART NO. TYPE DESCRIPTION 7040045 HCPL-2531 DUAL OPTOCOUPLER 7100100 SA129 (8085A) 8-BIT CHANNEL MICROPROCESSOR 7100101 SA151 (8086) 16-BIT MICROPROCESSOR 7100103 8212 8-BIT INPUT/OUTPUT PORT 7100104 S4127 (8226) 4-BIT PARALLEL BIDIRECTIONAL BUS DRIVER 7100105 8251A PROGRAMMABLE COMMUNICATION INTERFACE 7100106 S4130 (8255A) PROGRAMMABLE PERIPHERAL INTERFACE 7100107 S4146 (8257-5) PROGRAMMABLE DMA CONTROLLER 7100108 S4153 (8273) PROGRAMMABLE HDLC/SDLC PROTOCOL CONTROLLER 7100109 S4119 (8279-5) PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE 710011 1 S4121 (8284) CLOCK GENERATOR AND DRIVER FOR S4151 CPU 7100112 S4122 (8286) OCTAL BUS TRANSCEIVER 7100113 S4120 (8755A) 16,384-BIT EPROM WITH I/O PORTS 7100114 AM9016DDCB (2117-5) 16-BIT DYNAMIC RAM 7100115 AM9114DDCB 1024 X 4-BIT STATIC RAM (450 NSEC) 7100116 S6553 (2708) 8K, WIRE NO. WIRE AWG COLOR APPROX. LENGTH FROM TERM ITEM TO TERM ITEM REMARKS 122 COAX. CABLE BK 42" N1A3 J9(2)(CTR) N1N2 E13 — 123 COAX. CABLE BK N1A3 J9(1)(GND) — N1N2 E14 — 124 COAX. CABLE 42" N1A3 J10(2)(CTR) — N1N2 E11 — 125 COAX. CABLE BK N1A3 J10(1)(GND) — N1N2 E12 — 126 16 G 2-1/2" N1A3 JK2) — N1N3 GND.LUG — Figure 10-32. Connector Panel to Chassis Interconnecting Wiring List (Sheet 7 of 7) 10-75/10-76 &IU.S. GOVERNMENT PRINTING OFFICE : 1985 - 480-173 : QL 3 ► > > 100139 - S54LS10F (883B) ;CHOTTKY TRIPLE INPUT POSITIVE NAND GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT I 2 3 4 I I I I I I I I I I I I 7100140 - S54LS14F (883B) SCHOTTKY HEX SCHMITT TRIGGER INVERTER LOGIC DIAGRAM This element is a Schottky hex Schmitt-trigger positive- NAND gate and inverter with totem-pole outputs. 7100141 - S54LS20F (883B) SCHOTTKY DUAL 4-INPUT POSITIVE NAND GATE LOGIC DIAGRAM This element is a Schottky dual 4-input positive-NAND gate with totem-pole outputs. Each gate pro- duces a logical "0" output when both inputs are "1" and a "1" output if any of the inputs are "0". 7100142 - S54LS27F (883B) SCHOTTKY TRIPLE 3-INPUT NOR GATE LOG.CD.AGRAM TRUTH TABLE INPUT '/J r f'UT I 2 3 4 I I I I I I I I I I I I I This element is a Schottky triple 3-input NAND gate with totem-pole outputs. Each gate pro- duces a logic "0" output when all inputs are "1" and a "1" output if any of the inputs are "0". 7100143 - S54LS30F (883B) SCHOTTKY 8-INPUT POSITIVE NAND GATE BpT F |jT GND [jT LOGIC DIAGRAM JJ>cc r ? H "|2~| h ~h"~] g To] H ~8~[ j This element is a Schottky 8-input NAND gate. It pro- duces a logical "0" output when all inputs are "1" and a "1" output if any of the inputs are "0". J=AB-C-DE-F-G-H 7100144 - S54LS32F (883B) SCHOTTKY QUAD 2-INPUT POSITIVE OR GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT I 2 3 I I I I I I I This element is a Schottky quad 2-input positive OR gate with totem-pole outputs. It produces a logical "1" output when one of its inputs is logical "1" and a logical "0" output when both of its inputs are "0". Figure 10-33. Integrated Circuit Data (Sheet 1 of 9) 10-77/10-78 7040045 - HCPL-2531 DUAL OPTOCOUPLER LOGIC DIAGRAM CATHODE 2 \T ANODE 2 [T ~5~| GND This element is a dual, high-speed optocoupler in an 8-pin dual in-line package. 7100120 - S54S04F (833B) SCHOTTKY HEX INVERTER LOGIC DIAGRAM IAp~ IY[T 5 £ £ "J4]Vcc "|3]6A 2A[T 2Y[T 3 J2J6Y TTJ5A 3A[T 5 lo]5Y 3Y[^ GND[~7~ c ]T]4A T|4Y POSITIVE LOGIC Y = 5 This element is a Schottky inverter with totem-pole outputs. 7100135 - S54LS00F (883B) SCHOTTKY QUAD 2-INPUT POSITIVE NAND GATE LOGIC DIAGRAM GNDpT This element is a Schottky quad 2-input NAND gate. Each gate produces a logical "0" output when both inputs are "1" and a "1" output if any of the inputs are "0". TRUTH TABLE INPUT OUTPUT 1 2 3 1 1 O 1 O 1 O 1 1 1 7100136 - S54LS02F (883B) SCHOTTKY QUAD 2-INPUT POSITIVE NOR GATE LOGIC DIAGRAM This element is a quad 2-input NOR gate with totem-pole outputs. Each gate produces a logical "0" output when one or more of its inputs are "1" and a "1" output when both inputs are "0". TRUTH TABLE INPUT OUTPUT I 2 3 1 1 1 1 1 O 7100137 - S54LS04F (883B) SCHOTTKY HEX INVERTER LOGIC DIAGRAM ia n~ ^7^ EKc IY |"T JW H]6A 2A[T \p/__c=-| 751 6Y 2Y [T nY^ 1 U]5A 3A|~5" r- — i ? 5V 7b"]5Y 3Y[~6" 9l4A GNPfT i_j y_ T]4Y POSITIVE LOGIC C = A This element is a Schottky /nverter with totem-pole outputs. 7100138 - S54LS08F (883B) SCHOTTKY QUAD 2-INPUT POSITIVE AND GATE LOGIC DIAGRAM GNDpT TRUTH TABLE This element is a Schottky quad 2-input AND gate with totem-pole outputs. On any one gate, when either input is "0", the output is "0". When both inputs are "1", the output is "1". INPUT OUTPUT 1 2 3 O 1 O 1 1 O 1 1 7100139 - S54LS10F (883B) SCHOTTKY TRIPLE 3-INPUT POSITIVE NAND GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT I 2 3 4 I I I I I I O I I I I I I 7100140 - S54LS14F (883B) SCHOTTKY HEX SCHMITT TRIGGER INVERTER LOGIC DIAGRAM .[HKc gndIT I3J IB To] a This element is a Schottky hex Schmitt-trigger positive- NAND gate and inverter with totem-pole outputs. 7100141 - S54LS20F (883B) SCHOTTKY DUAL 4-INPUT POSITIVE NAND GATE LOGIC DIAGRAM GND ["7" This element is a Schottky dual 4-input positive-NAND gate with totem-pole outputs. Each gate pro- duces a logical "0" output when both inputs are "1" and a "1" output if any of the inputs are "0". 7100142 - S54LS27F (883B) SCHOTTKY TRIPLE 3-INPUT NOR GATE TRUTH TABLE GNDl LOGIC DIAGRAM LZ Hl v cc LX m r^ \T ^r m E HIGH VOLTAGE LEVEL This element is a Schottky quad 2-input exclusive OR gate. On any one gate, when one, but not both, inputs are high, the output is high. When both inputs are high or both inputs are low, the out- put is low. LOGIC DIAGRAM J3 v cc -m 7100155 - S54LS161F (883B) SCHOTTKY 4-BIT BINARY COUNTER LOGIC DIAGRAM CEP V cc -- PIN 16 GND = PIN8 ( )=PIN NUMBER This element is a Schottky high speed 4-bit binary counter. The counters are positive edge-triggered, synchronously presettable and are easily cascaded to n-bit synchronous applications. A terminal count output is provided which detects a count of HHHH. The master reset asynchronously clears all flip-flops. MODE SELECT - FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS RESET (CLEAR) MR CP CEP CET PE °Ji On TC L X X X X X L L PARALLEL LOAD H H X X X X 1 1 1 h L H L (B) COUNT H h h h(D) X COUNT (B) HOLD (DO NOTHING) H H X X no X X 1(C) h(D) h(D) X X On On (B) L H * HIGH VOLTAGE LEVEL STEADY STATE L = LOW VOLTAGE LEVEL STEADY STATE h = HIGH VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE LOW-TO-HIGH CLOCK TRANSITION I = LOW VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE LOW-TO-HIGH CLOCK TRANSITION X= DON'T CARE q = LOWER CASE LETTERS INDICATE THE STATE OF THE REFERENCED OUTPUT PRIOR TO THE LOW-TO-HIGH CLOCK TRANSITION = LOW-TO-HIGH CLOCK TRANSITION NOTES (B) THE TC OUTPUT IS HIGH WHEN CET IS HIGH AND THE COUNTER IS AT TERMINAL COUNT (HHHH F0R"l6l") (C) THE HIGH-TO-LOW TRANSITION OF CEP OR CET ON THE 54/74161 SHOULD ONLY OCCUR WHILE CP IS HIGH FOR CONVENTIONAL OPERATION (D) THE LOW-TO-HIGH TRANSITION OF PE ON THE 54/74161 SHOULD ONLY OCCUR WHILE CP IS HIGH FOR CONVENTIONAL OPERATION LOGIC SYMBOL 9 3 4 5 6 PIN CONFIGURATION 14 13 12 M V cc = Pin 16 GND= Pln8 Figure 10-33. Integrated Circuit Data (Sheet 2 of 9) 10-79/10-80 7100218 - S54LS164F (883B) SCHOTTKY 8 BIT SERIAL-IN PARALLEL-OUT SHIFT REGISTER LOGIC SYMBOL PIN CONFIGURATION sod Q 2 (5) °3 (6) V high speed 8-bit serial-in, parallel-out shift register featur- i an asynchronous master reset. Serial data is entered through hronously with the low to high clock transition. An asyn- hich clears the register, setting all outputs low independent V CC = PIN 14 GND = PIN 7 MODE SELECT TRUTH TABLE OPERATING MODE INPUTS OUTPUTS MR CP n SA n SB Qo 0,-Q 7 RESET (CLEAR) L H X X I X i L L L " L 90-96 SHIFT H I h L 9 -9 6 H h I L 90'9 6 H h h H 9 -96 7100223 - DM54S373J (883B) OCTAL D TYPE LATCH LOGIC DIAGRAM DO d> (3) E III) (4) E D D 2 (7) E D 5 n 3 (8) E D O D 4 (1 3) E D D 5 (14) E D OE ->- rY rY rY rY in V cc = PIN 20 GND = PIN 10 (2) 00 (5) 0| (6) 2 3 D6 (17) o E D (9) 03 r? rY (I 2) 04 05) (16) 6 FIGURATION 20] V CC UK I8]D 7 T7]D 6 HJoe H]Q5 J±]D5 TTJD4 TJ]q 4 TTJcp LOGIC SYMBOL 3 4 7 8 13 14 17 18 MODE SELECT-FUNCTION TABLE n 7 (18) E D rY 09) 7 l-C OE CP QO Q| Q2 Q3 Q4 Q5 Q6 Q7 1 r 6 9 12 15 16 19 5 Q6 Q7 f I I OPERATING MODES INPUTS OUTPUTS OE E D INTERNAL REGISTER °0-°7 ENABLE 8 READ REGISTER L H L L H H L H L H LATCH ft READ REGISTER L L 1 L L h L H L H LATCH REGISTER 8 DISABLE OUTPUTS H L 1 H L h L H (Z) (Z) This element is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled indepen- dently by latch enable G and output control gates. V cc = PIN 20 GND= PIN 10 H = HIGH VOLTAGE LEVEL h = HIGH VOLTAGE ONE SETUP TIME PRIOR TO THE HIGH TO LOW ENABLE TRANSITION L = LOW VOLTAGE LEVEL I = LOW VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE HIGH TO LOW ENABLE TRANSITION (Z)= HIGH IMPEDANCE "OFF" STATE Figure 10-33. Integrated Circuit Data (Sheet 3 of 9) 10-81/10-82 7100159 - A AF111HMQB VOLTAGE COMPARATOR BALANCE This element is designed to operate over a wide range of supply voltages, ranging from standard ±15V op-amp supplies down to a single 5V supply used for I.C. logic. The out- put is compatible with TTL as well as MOS circuits. The 111 can drive lamps, relays or switching voltages up to 50 volts at currents as high as 50mA. 7100202 - CD4069UBMJ (883B) HEX INVERTER LOGIC DIAGRAM I 2 3 4 5 6 " 14 This element consists of six inverter cir- cuits and is manufactured using com- plementary CMOS to achieve wide power supply operating range, low power consumption, high noise immuni- ty and symmetric controlled rise and fall times. 7100169 -//A741DMQB OPERATIONAL AMPLIFIER LOGIC DIAGRAM nc[T l4~| NC Ncfir l3~| NC OFFSET NULL [IT \2_\ NC INVERT IN [a~ iN- TT| v + NON-INVERT IN Hf" -p^- lb~| OUTPUT v- nr T] OFFSET NULL NC [T "j~| NC This element is a general purpose operational amplifier which features improved performance over many industry stan- dards. These features include overload protection on the input and output, no latch-up when the common mode range is exceeded, and freedom from oscillations. 7100215 - MM5369AA/N OSCILLATOR PRESCALER, 3.58 MHz TO 60 Hz OSC. IN - TUNER_ OUTPUT" DSC SI, UU [ X r 4 I7 STAGE DIVIDER 0)0 (2) (8) 6 CJ H> (9l!50o. v cc = nn ' GND = PIN 7 jtj fjjJ £ o rC> 7100218 - S54LS164F (883B) SCHOTTKY 8-BIT SERIAL-IN PARALLEL-OUT SHIFT REGISTER LOGIC SYMBOL PIN CONFIGURATION (3) (4) Q 2 (5) 03 (6) °4 (IO) This element is a Schottky high speed 8-bit serial-in, parallel-out shift register featur- ing grated serial inputs and an asynchronous master reset. Serial data is entered through a 2-input AND gate synchronously with the low to high clock transition. An asyn- chronous master reset which clears the register, setting all outputs low independent of the clock, is featured. MODE SELECT - TRUTH TABLE 05 (in OPERATING MODE INPUTS OUTPUTS MR CP n SA °SB Qo 0|-0 7 RESET (CLEAR) L H X X 1 X 1 L L L- L 90-16 SHIFT H 1 h L "0-«»6 H h 1 L Ve H h h H "o^e RESET PULSE GENERATOR -•-» BUFFER 3 1 t DIVIDER "OUTPUT I ! v ss v dd CONNECTION DIAGRAM DUAL IN LINE PACKAGE TURNER OSC. OSC. V dd OUTPUT OUT IN 8 7 6 5 — ■ 1 2 3 4 This element is a CMOS integrated circuit with 17 binary divider stages that can be used to generate a precise 60 Hz reference from commonly available high frequency quartz crystals. An internal pulse is generated by mask programming the combinations of stages 1 through 4, 16 and 17 to set or reset the individual stages. DIVIDER V« N, 64 Mz " C OUTPUT TOP VIEW 7100223 - DM54S373J (883B) OCTAL D TYPE LATCH LOGIC DIAGRAM DO (3) E-{>V uir (4) E D D 2 (7) rY 0E-[>O— (I) V cc = PIN 20 GND = PIN IO S E D (2) 00 (5) 0| D5 (14) E D 3 (IS) PIN CONFIGURATION LOGIC SYMBOL MODE SELECT-FUNCTION TABLE l-C OE 8 13 14 17 18 I I I I I QO Ql Q3 Q4 Q5 Q6 Q7 1 — I I I I 9 12 15 16 19 OPERATING MODES INPUTS OUTPUTS OE E D INTERNAL REGISTER Q -Q 7 ENABLE a READ REGISTER L H L L H H L H L H LATCH a READ REGISTER L L 1 L L h L H L H LATCH REGISTER a DISABLE OUTPUTS H L 1 H L h L H (Z) (Z) This element is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled indepen- dently by latch enable G and output control gates. GND ■ PIN IO H = HIGH VOLTAGE LEVEL h = HIGH VOLTAGE ONE SETUP TIME PRIOR TO THE HIGH TO LOW ENABLE TRANSITION L = LOW VOLTAGE LEVEL I • LOW VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE HIGH TO LOW ENABLE TRANSITION (Z)= HIGH IMPEDANCE "OFF" STATE Figure 10-33. Integrated Circuit Data (Sheet 3 of 9) 10-81/10-82 00231 - S54LS174F(883B) IOTTKY HEX D FLIP-FLOP PIN CONFIGURATION 04) -|D CP 02) D flip-flop used storage register. 'the register during clock pulse. The lears all flip-flops. (15) 5 LOGIC SYMBOL 4 6 II 13 14 TS Y b L H [Z) TAT E MODE SELECT-FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS MR CP D N Qn Q N RESET (CLEAR) LOAD " I " LOAD"0" L H H X t t X h I L H L H L H 7100273 - S54LS240F (883B) SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) LOGIC DIAGRAM TRUTH TABLE INPUTS OUTPUTS OE a 'a °E b lb Yq *b L L H L H X L L H L H X L H (Z) L H (Z) H=HIGH VOLTAGE LEVEL L=LOW VOLTAGE LEVEL X= DON'T CARE (Z) = HIGH IMPEDANCE (OFF) STATE This element is a Schottky octal in- verter buffer packaged in a 20 pin dual in-line package. 7100250 - MC14011BBCBS CMOS QUAD 2 INPUT NAND GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT I 2 3 I I O O I O I I I I This element is a CMOS quad 2-input NAND gate having buffered inputs and outputs. Each gate pro- duces a logical "0" output when both inputs are "1" and a "1" output if any of the inputs are "0". 7100291 - F A A148DMQB QUAD 741 OPERATIONAL AMPLIFIER LOGIC DIAGRAM IN4 IN4* V- IN 3* IN3 |I3 12 |ll IO |9 OUT I 00 T 2 |3 IT IN r V* IN 2* TOP VIEW This element is a quad operational amplifier consisting of four independent, high gain, internally compensated, low power operational amplifiers which has been designed to provide func- tional characteristics identical to the 741 operational amplifier. 7100292 - ZM555DE (883B) TIMER LOGIC SYMBOL tzt GND TRIGGER OUTPUT RESET DISCHARGE THRESHOLD 5 CONTROL VOLTAGE TOP VIEW This element is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting. Figure 10-33. Integrated Circuit Data (Sheet 4 of 9) 10-83/10-84 7100225 - S54LS21F (883B) DUAL 4-INPUT POSITIVE AND GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT B c D Y I I I I I I I I I I I I I This element is a dual positive AND gate with totem-pole output. Each gate produces a logic "1 " output when all inputs are "1 " and a "0" output if any of the in- puts are "0". 7100251 - MC14013BBCBS CMOS DUAL D-TYPE FLIP-FLOP LOGIC DIAGRAM (1/2 OF DEVICE SHOWN) so- o-Oci^ 4-1 BLOCK DIAGRAM TRUTH TABLE INPUTS OUTPUTS CLOCK* DATA RESET SET Q _j- 1 -T 1 O 1 O -\_ X Q Q X X 1 1 X X 1 1 X X 1 1 1 1 This element con- sists of two iden- tical, independent data type flip- flops. Each flip- flop has indepen- dent data, set, reset, clock inputs and Q, Q outputs. C R 9- NO X * DON'T CARE • LEVEL CHANGE C Q R V D0 = PIN 14 V SS =PIN 7 7100231 - S54LS174F (883B) SCHOTTKY HEX D FLIP-FLOP LOGIC DIAGRAM CP- (9) ^ V CC Pin 20 (3) GND* Pin 6 ( ) ■ Pin numbin D Qh >CP *D _ (I) MR ^H> (4) Q ► CP (2) (6) °3 (II) PIN CONFIGURATION L|D Qh CP "D (5) D >CP "D (7) 4 (13) D Qh >CP R D (10) 3 (14) LOGIC SYMBOL 4 6 II 13 D Q >CP "D (12) (15) 5 H = HIGH VOLTAGE LEVEL STEADY STATE h»HIGH VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE LOW-TO-HIGH CLOCK TRANSITION L = L0W VOLTAGE LEVEL STEADY STATE I =LOW VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE LOW-TO-HIGH CLOCK TRANSITION X = DON'T CARE | = LOW-TO-HIGH CLOCK TRANSITION MODE SELECT-FUNCTION TABLE This element is a Schottky hex D flip-flop used primarily as a 6-bit edge-triggered storage register. Data on the D inputs is loaded into the register during the low-to-high transition of the clock pulse. The master reset input asynchronously clears all flip-flops. 7100268 - DM54LS244J (883B) SCHOTTKY OCTAL BUFFER (3-STATE) PIN CONFIGURATION I°l v cc TRUTH TABLE INPUTS OUTPUTS OE >fl OE„ lb Y o Y b L L L L L L L H L H H H H X H X (Z) (Z) H= HIGH VOLTAGE LEVEL L=LOW VOLTAGE LEVEL X = DON'T CARE (Z)=HIGH IMPEDANCE (OFF) STATE This element is a Schottky ocal buffer with tri-state outputs. OPERATING MODE INPUTS OUTPUTS MR CP D N On °N RESET (CLEAR) LOAD " I " LOAD"0" L H H X t t X h I L H L H L H 7100273 - S54LS240F (883B) SCHOTTKY OCTAL INVERTER BUFFER (3-STATE) LOGIC DIAGRAM TRUTH TABLE °Eq LZ 'aoLX 1°] v cc H]0E b Y b0 LX '■iLX |£^^ JiJ Y aO ID 'bO JH Y ol 1] 'bl Y bi LS. 'azLX Y b2LZ '03 LH Y b 3 E GND [To" ^\3^- J3 Y a2 JE 'b2 m Y o 3 ID '» INPUTS OUTPUTS OEa 'a °E b lb Y a Y b L L H L H X L L H L H X L H (Z) L H (Z) H= HIGH VOLTAGE LEVEL L=L0W VOLTAGE LEVEL X= DON'T CARE (Z) = HIGH IMPEDANCE (OFF) STATE This element is a Schottky octal in- verter buffer packaged in a 20 pin dual in-line package. 7100250 - MC14011BBCBS CMOS QUAD 2-INPUT NAND GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT I 2 3 I I O I I O I I I This element is a CMOS quad 2-input NAND gate having buffered inputs and outputs. Each gate pro- duces a logical "0" output when both inputs are "1" and a "1" output if any of the inputs are "0". 7100291 - F/HXr1> t F >-h, BOj^-l^o^K^ r^o s> tt> (H>^ri> t v y> O °(H>- ^£^-^ p P° 7100343 - CD4008 4-BIT ADDER PIN ASSIGNMENT A 4 [j B 3LX a 3 LT B 2 [T A 2 [jL B, \T A, [T v SsLH 16J V DD "is] B 4 !1]cout 1T[ s 4 H]S3 77] s 2 i°] s i j]C|N This element is a CMOS 4-bit full-adder IC in a hermetically sealed 1 6-pin dual in-line package. TRUTH TABLE A| B| C| c SUM I 1 I I I 1 1 I 1 1 1 1 I I I 1 1 1 1 1 0>- -£>-(D"°" -—^0 o(>— @".» ^y— ^>— ©"2- Q° — 4>— ®" 3 " O c(>-©-4- :^d — c[>^©" 5 " 0> — o-©" 6 " :Zy — °f>— ®" 7 " PIN CONFIGURATION 4LT jH v ( 2 \T_ T5~| 3 o \T "iT| i r[£ T3~| B 9 (T TT| c 5 \T Ti~| o «LL To] A .sLT T] 8 TOP VIEW cc i=0- H>--®" 8 " :3> — o[>— ®"9- 7100344 - CD40192BF/3 CMOS SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER PIN CONFIGURATION I6 OUTPUTS This element is a synchronous 4-bit up/down (COUNT _± decade counter IC DOWN hermetically sealed INPUTS< in a 16-pin dual in-line package. OUTPUTS DATA A i INPUTS CLEAR (JJP RR0W~1 > OUTPUTS CARRY LOAD DATA C > INPUTS DATA D Figure 10-33. Integrated Circuit Data (Sheet 5 of 9) 10-85/10-86 7100318 - S54121F (883B) MONOSTABLE MULTIVIBRATOR PIN CONFIGURATION MODE FUNCTION TRUTH TABLE INPUTS OUTPUTS vcc A| A 2 B Q L X H L H X L H L H X X L L H R ext /C ext H H X L H H * H J~L "LT Cext 4 H H n u i t H -TL T_T L X t n is X L ♦ n i_r H = HIGH VOLTAGE LEVEL L = LOW VOLTAGE LEVEL X = DON'T CARE ♦ = LOW-TO-HIGH TRANSITION * = HIGH-TO-LOW TRANSITION This element is a monostable multivibrator with an active HIGH going Schmitt trigger input and two gated active LOW going trigger inputs. The device is non-retriggerable and will not react to input transitions while timing out. In response to a trigger, the Q output goes high and the 5 output goes low, staying there for a predetermined time and then returning to the initial state. 7100341 - CD4027B DUAL J-K MASTER/SLAVE FLIP-FLOP WITH SET AND RESET LOGIC DIAGRAM Q2 CLOCK 2 RESET 2 SET 2 I !§_ 2 ^_ I5 3 F/F | 14 4 13 b Vi 6 "tj F/F2 II 7 IO 8 9 RESET I Kl This element is a J-K flip flop hermetically sealed in a 1 6-pin dual in-line package. J I SET 7100320 - CD4062B QUAD BILATERAL SWITCH LOGIC DIAGRAM OUT OUT CONTROL B CONTROL C 'ss I 14 2 SW A — I 13 3 |_ 12 4 SW D -1 II 1 «-| 5 IO ■ SW B 7 I | I - SW C r 8 1 'DO CONTROL A CONTROL D OUT OUT IN This element consists of four independent switches capable of controlling either digital or analog signals. This quad bi-lateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS Logic Implementation. 7100342 - OP-05-883J OPERATIONAL AMPLIFIER This element is a Type OP-05 in- strumentation operational amplifier IC hermetically sealed in a metal can package. B4 I5 0- A4 I O- B3 2 CI- AS 3 O- B2 4 0- A2 5 0- 7100336 - CD002BF (3) CMOS DUAL 4-INPUT NOR GATE LOGIC DIAGRAM 'DD NC HNRHH^IH TRUTH TABLE [^ H 111 NC V ss INPUT OUTPUT 1 2 3 1 1 1 1 1 This element is a dual 4-input NOR gate. Each gate produces a logical "0" output when one or more of its inputs are "1" and a "1" output when both inputs are "0". FUNCTIONAL DIAGRAM HIGH SPEED PARALLEL CARRY -OUT ADDER 4 C4 ADDER 3 C3 ADDER 2 C2 ADDER HO SI V DD ■ PIN 16 'SS = PIN 8 7100339 - CD4028BF (3) CMOS BCD-TO-DECIMAL DECODER LOGIC DIAGRAM A®— £>0-J-c[> ■@->-rt> r=o 3> to ©-Or ^ t r >> £> '(HXrC^ ?> ~y — $>— ® v ~y — o>— ©"*" Q> c(>-— ©•*• ~y — c> — CD" 5 " ;3> c[>— ©v ;^> — o[>— ©"7- PIN CONFIGURATION 4[T jUv r 2[T "l5~| 3 o [T W\ i 7[T If] B 9 [T TF| c 5 [F TT"| D 6 [T lol A is[I 9~| 8 TOP VIEW ;^0 — c(>-®-8» z|3 — «>-©*■ 7100343 - CD4008 4-BIT ADDER PIN ASSIGNMENT A4LI B3U A3U B 2 [4 A 2 |X B, (T A, \T v ss[Z 16J V DD IF] B 4 !l]C0UT Til S4 il]S3 TT]s 2 10] s, 1]C|N This element is a CMOS 4-bit full-adder IC in a hermetically sealed 1 6-pin dual in-line package. TRUTH TABLE A| B| C| Co SUM O I I I I I I I I I I I I ! I I I I I 7100344 - CD40192BF/3 CMOS SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTER PIN CONFIGURATION DATA B I INPUT OUTPUTS ("count _± DOWN This element is a synchronous 4-bit up/down decade counter IC hermetically sealed INPUTS^ in a 16-pin dual [COUN" in-line package. *■ OUTPUTS INPUTS borrow"! > OUTPUTS DATA C > INPUTS Figure 10-33. Integrated Circuit Data (Sheet 5 of 9) 10-85/10-86 JTPUT Oh h Qho QGn QGn Qho shift cage. PIN CONFIGURATION 7100348 - CD4052B/F3 DUAL 4-CHANNEL MULTIPLEXER/ DEMULTIPLEXER FUNCTIONAL DIAGRAM reo — INHIBIT CONTROLS L9o — rizo— A B XO X —oiT SWITCHES , IN /OUT "S liE XI X2 X3 YO < COMMONS > OUT/ IN 2^ Yl Y2 Y 03 -J ^_40 Y3 ©VD0_ "DD 'SS 'EE = PIN 16 ;PIN8 B®^ INHig^— = PIN7 LOGIC LEVEL CONVERSION This element is a CMOS differential 6-channel analog multiplexer/demultiplexer IC in a hermetically sealed 16-pin dual in-line package. BINARY TO I OF 4 DECODER WITH INHIBIT SjVss S V E E X CHANNELS IN/OU T ^ 2 i 0^- ©©©(S TG COMMON X OUT/IN TG 6©© COMMON Y OUT/IN Y CHANNELS IN/OUT ER :ically sealed 7100352 - MC14560-BBEBS CMOS ADDER TRUTH TABLE * INPUT OUTPUT A4 A3 A2 Al B4 B3 B2 Bl C IN c OUT S4 S3 S2 SI I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I ^PARTIAL TRUTH TABLE TO SHOW LOGIC OPERATION FOR REPRESENTATIVE INPUT VALUES. BLOCK DIAGRAM 70 C IN SI O 13 l5o Al l4o Bl A2 S2 OI2 20 B2 S3 Oil 30 A3 4 63 S4 OIO 5o A4 60 B4 c OUT 09 'DD 'ss = PIN 16 = PIN 8 This element is a CMOS Natural Binary Coded Decimal (NBCD) adder IC hermetically sealed in a 16-pin dual in-line package. Figure 10-33. Integrated Circuit Data (Sheet 6 of 9) 10-87/10-88 7100345 - CD4001BF/3 QUAD 2-INPUT NOR GATE LOGIC DIAGRAM TRUTH TABLE INPUT OUTPUT I 2 3 I I I I I I I This element is a quad 2-input NOR gate. Each gate provides a logic "0" output when all inputs are "1 " and a "1 " output if any of the inputs are "0." OUTPUT | Qh PARALLEL INPUTS 10 r . A| II B |~J2 c|~J3 |~i4 7100346 - SNC54LS165J PARALLEL-LOAD 8-BIT SHIFT REGISTER PIN CONFIGURATION SERIAL IN CLOCK INHIBIT SHIFT/ LOAD FUNTION TABLE OUTPUT Qh _8 | GND 7 6J H T]g T]e 2~| CLOCK SHIFT/ PARALLEL INPUTS INPUTS INTERNAL OUTPUTS OUTPUT Oh SHIFT/ LOAD CLOCK INHIBIT CLOCK SERIAL PARALLEL A . . . H Qa Qb L X X X o ... h a b h H L L X X Q AO °BO Qho H L t H X H °An QGn H L t L X L Q An Ocn H H X X X Qao Q BO Qho I LOAD This element is a low power Schottky parallel load 8-bit shift register IC hermetically sealed in a 16-pin dual in-line package. PIN CONFIGURATION 7100348 - CD4052B/F3 DUAL 4-CHANNEL MULTIPLEXER/ DEMULTIPLEXER FUNCTIONAL DIAGRAM reo— INHIBIT CONTROLS-j IOO L90 A B X ^13^ ' I20— X0 I4 0— XI mo- X2 SWITCHES J IN /OUT * no— X3 Y0 5 ° — Yl Y2 Y 03 -J L 4 °— Y3 .COMMONS r OUT/ IN _§)< V DD = PINI6 V SS = PIN8 V EE = PIN 7 This element is a CMOS differential 6-channel analog multiplexer/demultiplexer IC in a hermetically sealed 16-pin dual in-line package. INHd)*— LOGIC LEVEL CONVERSION L ejv ss DD BINARY TO I OF 4 DECODER WITH INHIBIT S VEE X CHANNELS IN/OUT ©©© I© -QD-d ■ ■ — | UU I / 1 -nfryi— eg) :ommon X OUT/IN Slhr— ® COMMON Y OUT/IN 6@© >© 2 3 Y CHANNELS IN/OUT N CONFIGURATION 3, \Z I 3 5 E 5 36 E 6 3 7 C^ *0 [2 8 iKc ^| cs H*4 "0*3 I2 ~J A 2 II Z] A| IO^A O B 7100350 - HM17602B-8 BIPOLAR 32 X 8 PROM FUNCTIONAL DIAGRAM , do) — in) — (I2) - I (13) — . (14) - CS ( vcc GND. ADDRESS BUFFERS — » 1 OF 32 ROW DECODER 32 X 8 MEMORY ARRAY 5) ol "N r .T w w W J s/v j vvvvvv (16) (8) (9) (7) (6) (5) (4) (3) (2) (I) J 8 This element is a bipolar 32 x 8 PROM (open collector) IC hermetically sealed in a 16-pin dual in-line package. 7100351 - LM124 QUAD OPERATIONAL AMPLIFIER LOGIC DIAGRAM This element is a low power quad operational amplifier IC hermetically sealed in a 14-pin dual in-line package. 7100352 - MC14560-BBEBS CMOS ADDER TRUTH TABLE * INPUT OUTPUT A4 A3 A2 Al B4 B3 B2 Bl C IN c OUT S4 S3 S2 SI I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I • PARTIAL TRUTH TABLE TO SHOW LOGIC OPERATION FOR REPRESENTATIVE INPUT VALUES. BLOCK DIAGRAM 7o C IN SI OI3 I50 Al I4 Bl A2 S2 0I2 20 B2 S3 on 30 A3 40 B3 S4 OIO 5o A4 60 B4 c OUT 09 V DD =PIN 16 V SS -■ PIN 8 This element is a CMOS Natural Binary Coded Decimal (NBCD) adder IC hermetically sealed in a 16-pin dual in-line package. Figure 10-33. Integrated Circuit Data (Sheet 6 of 9) 10-87/10-88 NC5407 DRIVER OGIC DIAGRAM 6Y 5A 5Y 4A 4Y 12 II 10 9 8 >" ->- 4> -On -o^ 3 4 5 6 7 2A 2Y 3A 3Y GND : Y = A 4LS251F MULTIPLEXER TRUTH TABLE INPUTS OUTPUTS ) 'l '2 '3 '4 '5 "6 '7 Y Y X X X X X X X X X X X X X X X X X X X X X L X X X X X X H X X X X X X X L X X X X X X H X X X X X X X L X X X X X X H X X X X X X X L X X X X X X H X X X X X X X L X X X X X X H X X X X X X X L X X X X X X H X X X X X X X L X X X X X X H (Z) (Z) H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H GE LEVEL ;e level ANCE (OFF) LOGIC DIAGRAM 3 2 1 15 14 I 12 _l 1 I I I L_L i "3 "4 >5 '6 '7 7100360-1 - 4260016 (54LS373) OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE TRIGGERED FLIP-FLOPS LOGIC DIAGRAM ENABLE V C c 80 80 70 70 60 60 50 50 G 12 TRUTH TABLE 20 19 I8 17 I6 15 14 13 00 D G|» OE ^ HD OF Ho Dp Hd oh 4 D i G OE X OE n r 1 r D °|g OE ZL D G OE X OE D G OE OUTPUT CONTROL ENABLE G U OUTPUT L L L H H H H L L X X X H L Qo z OUTPUT 10 10 20 20 30 30 CONTROL 40 40 GND This element is an octal, D-type transparent latch and edge triggered flip-flop. It is an 8-bit register with totem-pole three-state outputs. The eight latches are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was setup. 7100363 - SNC5445J BCD DECODER FUNCTION TABLE LOGIC DIAGRAM NO INPUTS OUTPUTS D C 8 A I 2 3 4 5 6 7 8 9 L L L L L H H H H H H H H H I L L L H H L H H H H H H H H 2 L L H L H H L H H H H H H H 3 L L H H H H H L H H H H H H 4 L H L L H H H H L H H H H H 5 L H L H H H H H H L H H H H 6 L H H L H H H H H H L H H H 7 L H H H H H H H H H H L H H 8 H L L L H H H H H H H H L H 9 H L L H H H H H H H H H H L H L H L H H H H H H H H H H H L H H H H H H H H H H H H < > H H H L H L L H H H H H H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H INPUTS OUTPUTS v_cc f I6 12 10 C D BCD-TO-DECIMAL 3 4 5 6 GND OUTPUTS H= HIGH LEVEL (OFF) L= LOW LEVEL (ON) This element is a BCD-to-decimal decoder/driver integrated circuit hermetically sealed in a 16-pin dual in-line package. Figure 10-33. Integrated Circuit Data (Sheet 7 of 9) 10-89/10-90 V REF ( + )o- v REF (-)o! 7100355 - DAC-08A08 8-BIT, HIGH-SPEED MULTIPLE DIGITAL-TO-ANALOG CONVERTER FUNCTIONAL DIAGRAM MSB LSB V+ V LC B, B 2 B 3 B 4 B 5 B 6 B 7 B 8 fl °5 |6 °7 °8 |9 TlO °H °I2 I— i— T5^L THRESHOLDI L >— PIN CONFIGURATION 3 — 1 ■ I COMPENSATION NETWORK CURRENT SWITCHES Ir^^lx It It^Iti ] NOTE; PIN I IS MARKED FOR ORIENTATION C0MP6 This element is an 8-bit, high-speed multiplying D/A converter IC hermetically sealed in a 16-pin in-line package. CONTRO 'out [2 2 'out Q MSB B, Q B 2 Q '5 3 W"' 14 -J V REF (+) 13 ^J V + 12 ^\ B 8 LSB 10 Z\ B 6 -Db 5 7100356-1 - 4260015 (54LS280) 9-BIT ODD/EVEN PARITY GENERATOR/CHECKER LOGIC DIAGRAM ^Ch BLOCK DIAGRAM INPUTS V CC F E D C B A I EVEN ODO LjTiniTi3iininzr NC I z 1 INPUT .EVEN ODD, OUTPUTS NC=N0 INTERNAL CONNECTION GND TRUTH TABLE ODD H= HIGH LEVEL, L= LOW LEVEL This element is a universal, monolithic, nine-bit parity generator/checker. It utilizes Schottky-clamped TTL high-performance circuitry and features odd/even outputs to facilitate operation of either odd or even parity application. NUMBER OF INPUTS A THRU 1 THAT ARE HIGH OUTPUTS 2 EVEN r ODD 0,2,4,6,8 1,3,5,7,9 H L L H 7100357 - SNC5407 HEX BUFFER DRIVER LOGIC DIAGRAM 6A 6Y 5A 5Y 4A i3| nil Mil I 1 1 This element is a hex buffer/driver with open collector and high voltage outputs IC hermetically sealed in a 14-pin dual in-line package. I 2 3 I I 4 IA IY 2A 2Y POSITIVE logic: Y = A 7100358 - 54LS251F DATA SELECTOR/MULTIPLEXER TRUTH TABLE This element is a low power Schottky data selector/multi- plexer with 3-state outputs IC hermetically sealed in a 1 6 pin dual in-line package. INPUTS OUTPUTS OE s 2 S| s k> 'I l2 l3 '4 '5 '6 I? Y Y H X X X X X X X X X X X (Z) (Z) L L L L L X X X X X X X H L L L L L H X X X X X X X L H L L L H X L X X X X X X H L L L L H X H X X X X X X L H L L H L X X L X X X X X H L L L H L X X H X X X X X L H L L H H X X X L X X X X H L L L H H X X X H X X X X L H L H L L X X X X L X X X H L L H L L X X X X H X X X L H L H L H X X X X X L X X H L L H L H X X X X X H X X L H L H H L X X X X X X L X H L L H H L X X X X X X H X L H L H H H X X X X X X X L H L L H H H X X X X X X X H L H H = HIGH VOLTAGE LEVEL L = LOW VOLTAGE LEVEL X = DON'T CARE (Z) = HIGH IMPEDANCE (OFF) LOGIC DIAGRAM 7 4 3 2 I 15 14 I 12 b I I I | | | | | OE "0 I iz '3 U l5 l6 17 1 1 — so 10 S| 9 s 2 Y Y = PIN 16 V I y cc GND= PIN 8 7100360-1 - 4260016 (54LS373) OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE TRIGGERED FLIP-FLOPS LOGIC DIAGRAM ENABLE V c c 80 80 70 70 60 60 50 50 G L fob — Dp Ho op Ho op 4d oh Wl7 TRUTH TABLE A OD-i G> OE H—a J iJLUll D § OE OUTPUT CONTROL ENABLE G U OUTPUT L L L H H H H L L X X X H L 00 OUTPUT 10 10 20 20 30 30 40 40 GND CONTROL This element is an octal, D-type transparent latch and edge triggered flip-flop. It is an 8-bit register with totem-pole three-state outputs. The eight latches are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the data (Dl inputs. When the enable is taken low the output will be latched at the level of the data that was setup. 7100363 - SNC5445J BCD DECODER FUNCTION TABLE LOGIC DIAGRAM NO. INPUTS OUTPUTS D C B A I 2 3 4 5 6 7 8 9 L L L L L H H H H H H H H H I L L L H H L H H H H H H H H 2 L L H L H H L H H H H H H H 3 L L H H H H H L H H H H H H 4 L H L L H H H H L H H H H H 5 L H L H H H H H H L H H H H 6 L H H L H H H H H H L H H H 7 L H H H H H H H H H H L H H 8 H L L L H H H H H H H H L H 9 H L L H H H H H H H H H H L H L H L H H H H H H H H H H H L H H H H H H H H H H H H < > H H H L H L L H H H H H H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H H H H H H v cc '"a b ^U^U^IMJ^RJ^ 8 C D BCD-TO-DECIMAL I 2 3 4 3 5 7 5 6 7 75 5 5 5 7 r^j T3T3Tin3TLrWTin±I 6, GND H= HIGH LEVEL (OFF) L= LOW LEVEL (ON) This element is a BCD-to-decimal decoder/driver integrated circuit hermetically sealed in a 16-pin dual in-line package. Figure 10-33. Integrated Circuit Data (Sheet 7 of 9) 10-89/10-90 7100442 - S5442F (883B) 4-LINE TO 10-LINE DECODER FUNCTION TABLE LS42 UT '43A EXCESS- 'L43 3-INPUT '44A, 'L44 EXCESS-3-GRAY INPUT ALL TYPES DECIMAL OUTPUT A D C B A D C B A I 2 3 4 5 6 7 8 9 L L L H H L L H L L H H H H H H H H H H L H L L L H H L H L H H H H H H H H L L H L H L H H H H H L H H H H H H H H L H H L L H L H H H H L H H H H H H L L H H H L H L L H H H H L H H H H H H H L L L H H L L H H H H H L H H H H L H L L H H H L H H H H H H H L H H H H H L H L H H H H H H H H H H H L H H L H L H H H H H L H H H H H H H H L H H H H L L H L H L H H H H H H H H H L L H H L H H L H H H H H H H H H H H H H H H H L H L L H H H H H H H H H H H L H H H H H L L L H H H H H H H H H H H L L L L L L L L H H H H H H H H H H L L L L H L L L H H H H H H H H H H H H L L H L L L H H H H H H H H H H H H ivel LOGIC DIAGRAM ITS OUTPUTS 8 : 1 3 1 2 I IO = > C D 3 4 5 6 7 8 9 — t; > < p } c > C [ 1 T_ i \ : > t •1- r< 3 This element is a 4-line to 10-line decoder IC in a 16-pin dual in-line package. These monolithic decimal decoders consist of eight inverters and ten four-input NAND gates. The inverters are con- nected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic ensures that all outputs remain off for all invalid input conditions. _6, GNO JTPUTS 7100443 - CD4071B QUAD 2-INPUT OR GATE LOGIC DIAGRAM V 0D |l4 13 I? II IO 9 8 I 2 3 4 5 '^SS This element is a quad 2-input OR buffered gate. It produces a logical "1 " output when one of its inputs is logical "1 " and a logical "0" output when both of its inputs are "0". 7100444 - 9370 7-SEGMENT DECODER/DRIVER lllllfl! 13 10 14 V CC = PIN 16 GND = PIN 8 PIN CONFIGURATION A, \T jIKc A 2 [Z 75] 7 LE [T "14] g RB0 [jT "75] a RBI [~5~ "Ti] B A3HE TT| 5 A [T "To] d GND [IT Hi This element is a 7-segment decoder/driver/latch IC hermetically sealed in a 1 6-pin dual in-line cermanic package. Figure 10-33. Integrated Circuit Data (Sheet 8 of 9) 10-91/10-92 7100364-1 - 4260016 (54LS132) QUADRUPLE 2-INPUT POSITIVE-NAND SCHMITT TRIGGER LOGIC DIAGRAM POSITIVE LOGIC ■■ Y = AB 7100370- LM117K ADJUSTABLE VOLTAGE REGULATOR Ol CASE IS OUTPUT This element is a 3-terminal adjustable regulator hermetically sealed in a metal can package (TO-3). 7100372 - CD40193BF/3 SYNC, 4-BIT UP/DOWN DECADE COUNTER LOGIC DIAGRAM INPUTS OUTPUTS INPUTS V D D DATA A CLEAR BORROW CARRY LOAD DATA C DATA X D |l6 15 14 13 12 II IO 9 o o ° I 2 3 4 5 6 7 8 DATA B A COUNT COUNT O c On V ss B v ~ ' ^DOWN UP . v ~ ' INPUT OUTPUTS ~ OUTPUTS INPUTS This element is a synchronous 4-bit up/down decode counter IC hermetically sealed in a 16-pin dual in-line package. 7100371 - A A7812H VOLTAGE REGULATOR, +12V, 0.5A •^-IN OUT COMM^ I 2 3 This element is a 2-terminal positive voltage regulator in a hermetically sealed metal can package (TO-39). 7100373 - 34333 (SG 1526) MM 5369 REGULATING PULSE WIDTH MODULATOR m OSC OUT OSC IN 0IV OUT This element is a pulse width modulator hermetically sealed in an 18-pin dual in-line package. 7100442 - S5442F (883B) 4-LINE TO 10-LINE DECODER FUNCTION TABLE NO. '42A, 'L42, 'LS42 BCD INPUT '43A, EXCESS- 'L43 3-INPUT '44A, 'L44 EXCESS-3-GRAY INPUT ALL TYPES DECIMAL OUTPUT C B A D C B A D C B A O 1 2 3 4 5 6 7 e 9 O L L L L L L H H L L H L L H H H H H H H H H I L L L H L H L L L H H L H L H H H H H H H H 2 L L H L L H L H L H H H H H L H H H H H H H 3 L L H H L H H L L H L H H H H L H H H H H H 4 L H L L L H H H L H L L H H H H L H H H H H 5 L H L H H L L L H H L L H H H H H L H H H H 6 L H H L H L L H H H L H H H H H H H L H H H 7 L H H H H L H L H H H H H H H H H H H L H H 8 H L L L H L H H H H H L H H H H H H H H L H 9 H L L H H H L L H L H L H H H H H H H H H L H L H L H H L H H L H H H H H H H H H H H H a -i H L H H H H H L H L L H H H H H H H H H H H H H L L H H H H H L L L H H H H H H H H H H z H H L H L L L L L L L L H H H H H H H H H H H H H L L L L H L L L H H H H H H H H H H H H H H H L L H L L L H H H H H H H H H H H H 7100443 - CD4071B QUAD 2-INPUT OR GATE LOGIC DIAGRAM V DD 14 7 S > 'v S s This element is a quad 2-input OR buffered gate. It produces a logical "1" output when one of its inputs is logical "1 " and a logical "O" output when both of its inputs are "0". H'hlgh level, L=low level LOGIC DIAGRAM V CC / ~A B C 0^ "^9 8 7^ BCD O I 2 3 4 5 6 7 8 9 B n s b s n n o B - .0 1 2 3 4 5 6. GND This element is a 4-line to 10-line decoder IC in a 16-pin dual in-line package. These monolithic decimal decoders consist of eight inverters and ten four-input NAND gates. The inverters are con- nected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic ensures that all outputs remain off for all invalid input conditions. OUTPUTS 7100444 - 9370 7-SEGMENT DECODER/DRIVER LOGIC SYMBOL 7 I 2 6 3 5 I I I I i I A A, A 2 A 3 LE RBI RBO a b c d e f g TTTTTTTT 4 13 12 II IO 9 15 14 V CC = PIN 16 GND = PIN 8 PIN CONFIGURATION A, \T Ji] v cc a z \T ~J5~| f LE [T RBO [~4~ RBI [~5~ ~l4~lcj This element is a 7-segment T3] a decoder/driver/latch IC hermetically sealed in a 1 6 pin dual in-line cermanic -jji - package. A 3 [E Ti~l c AolZ To] d GND [IT 3 1 Figure 10-33. Integrated Circuit Data (Sheet 8 of 9) 10-91/10-92 noiM LE D2 3 C2 2 10 SEGMENT IDENTIFICATION 1 1 1 g i 1^ e i i A2 L 8 |9 B2 1 GND This element is a CMOS 7-segment to BCD converter IC in a hermetically sealed 18-pin ceramic dual in-line package. 7100452 - LM320H-12 VOLTAGE REGULATOR, -12V f 0.5A GND OUTPUT INPUT This element is a -1 2-volt regulator hermetically sealed in a TO-5 metal can. The regulator has a cur- rent capability of 0.5A. 7100453 - SNJ54123J MONOSTABLE MULTIVIBRATOR LOGIC DIAGRAM LT J Bo 10 ) r D2 [77 02 UK oi [7? c ext I \\4 Rext^Cextl ill This element is a retriggerable monostable multivibrator, featuring dc trig- gering from gated active LOW inputs (A) and active HIGH inputs (B) and also provide overriding direct reset inputs. Complementary outputs are provid ed. The retrigger capability simplifies the generation of output pulses of ex- tremely long duration. By triggering the input before the output pulse is ter- minated, the output pulse may be extended. The overriding reset capability permits any output pulse to be terminated at a predetermined time in- dependently of the timing components R and C. 7100459 - SNJ54S280J PARITY GENERATOR PIN CONFIGURATION INPUTS INPUTS FUNCTION TABLE c n 'F 13 E I? D II C in B q r^ F E D C B G A H I EVEN ODD I 2 3 4 b 6 7 J NUMBER OF INPUTS A THRU I THAT ARE HIGH OUTPUTS l EVEN IODD 0,2,4,6,8 1 , 3, 5, 7, 9 H L L H H^ NC I £ £ INPUT ^EVEN ODD , OUTPUTS GND H = HIGH LEVEL L = LOW LEVEL This element is a Schottky 9-bit odd/even parity generator/checker IC in a hermetical- ly sealed 14-pin dual in-line package. 7230023 - HDSP-3531 SEVEN-SEGMENT DISPLAY LOGIC DIAGRAM This element is a common anode, 7-segment display hermetically sealed in a 14-pin dual in-line package. Figure 10-33. Integrated Circuit Data (Sheet 9 of 9) 10-93/10-94 7100445 - MM73178N ALARM CLOCK CALCULATOR PIN AM OUTPUT 10 HRS BSC HRS F HRS G HRS A HRS B HRS D HRS C HRS E IOMINS F 10 MINS G IOMINS AS D 10 MINS 10 MINS 10 MINS MINS MINS MINS MINS MINS CONFIGURATION 40 39 38 37 36 35 34 33 32 31 30 29 PM OUTPUT I Hz OUTPUT 12/24 HR SELECT BLANKING OUTPUT 50/60 Hz SELECT 50/60 Hz INPUT FAST SET INPUT SLOW SET INPUT SECOND DISPLAY INPUT ALARM DISPLAY INPUT SLEEP DISPLAY INPUT VDD i 28 ,, SLEEP OUTPUT — ALARM OFF INPUT ALARM OUTPUT — SNOOZE/CALENDAR MODE INPUT — OUTPUT COMMON SOURCE 22 MINS C — MINS D This element is an alarm clock calendar IC encapsulated in a high reliability 40-pin dual in-line epoxy package. 7100446 - MM54C915 7-SEGMENT TO BCD CONVERTER TRUTH TABLE PIN CONFIGURATION MINUS SEGMENT INPUTS OUT SEGMENT IDENTIFICATION CHARACTER AT SEGMENT INPUTS BCD OUTPUTS NON-BCD OUTPUTS D 2 3 c 2 2 B 2 1 A 2° , * . INVERT V CC a b c CONTROL LE D2 3 C2 2 t e I l b c ERROR MINUS g I I 2 3 4 5 6 6 7 8 9 9 All other input combinations I I I I X X X I X X X 1 1 1 1 1 1 X X X 1 1 1 1 1 1 1 1 X X X I I I | IB ir lb 13 14 13 Yd I IU V T I I d o This element is a CMOS 7-segment to BCD converter IC in a hermetically sealed 18-pin ceramic dual in-line package. vL_ I 2 e 3 4 5 6 7 g, ERROR DE A2° B2 3 9 1 GND X = TRI -STATE CONDITION Y SEGMENT INPUTS TOP VIEW 7100452 - LM320H-12 VOLTAGE REGULATOR, -12V, 0.5A GND OUTPUT INPUT This element is a -1 2-volt regulator hermetically sealed in a TO-5 metal can. The regulator has a cur- rent capability of 0.5A. 7100453 - SNJ54123J MONOSTABLE MULTIVIBRATOR LOGIC DIAGRAM This element is a retriggerable monostable multivibrator, featuring dc trig- gering from gated active LOW inputs (Al and active HIGH inputs (B) and also provide overriding direct reset inputs. Complementary outputs are provid- ed. The retrigger capability simplifies the generation of output pulses of ex- tremely long duration. By triggering the input before the output pulse is ter- minated, the output pulse may be extended. The overriding reset capability permits any output pulse to be terminated at a predetermined time in- dependently of the timing components R and C. 7100454 - A A760HMQB VOLTAGE COMPARATOR PIN 4 CONNECTED TO CASE This element is a high-speed differen- tial comparator in an 8-pin metal package. 7100455 - H1-1818A-2 CMOS ANALOG MULTIPLEXER PIN CONFIGURATION ADDRESS A| + 5.0V SUPPLY ENABLE ADDRESS A 2 IN 8 IN 7 IN 6 IN 5 1 2 3 4 5 6 7 8 16 ADDRESS Arj 15 -I5V SUPPLY ■ 14 +I5V SUPPLY 13 IN I 12 OUT II IN 2 IO IN 3 9 IN 4 This element is an 8-channel CMOS analog multiplexer in a hermetical- ly sealed 16-pin dual in-line package. 7100456 - MHQ6001 QUAD DUAL INPUT TRANSISTOR CONNECTION DIAGRAM E B C n n 8n D U 7U E B C This element is quad dual in-line silicon annular complementary transistor pair in a hermetically sealed 14-pin dual in-line package. 7100459 - SNJ54S280J PARITY GENERATOR PIN CONFIGURATION INPUTS FUNCTION TABLE B r> V CC r f e d c -< ?i — r^i — nyi — n — ryi — \ji~ . EVEN ODD NUMBER OF INPUTS A THRU 1 THAT ARE HIGH OUTPUTS I EVEN I ODD 0,2,4,6,8 1 , 3, 5, 7, 9 H L L H nirnirnirnirnij— h— lit H , NC H = HIGH LEVEL L = LOW LEVEL This element is a Schottky 9-bit odd/even parity generator/checker IC in a hermetical- ly sealed 14-pin dual in-line package. INPUT ^EVEN ODD , OUTPUTS 7230023 - HDSP-3531 SEVEN-SEGMENT DISPLAY LOGIC DIAGRAM This element is a common anode, 7-segment display hermetically sealed in a 14-pin dual in-line package. Figure 10-33. Integrated Circuit Data (Sheet 9 of 9) 10-93/10-94 )AR ^SOLE ji TB 207 AZ si AZ S2 AZ S3 Rl R2 TB 209 EL SI EL S2 EL S3 SYS TRIG SYS TRIG RTN PI I ! 1 2 -I z 1 3 -i V PI I IDE Nl ji i R7 fiS_ -"s/\/W rzi P3 CARD RACK ASSEMBLY J3 P2 J2 37 21 36 20 40 24 39 23 38 22 I 2 19 P3i J3 2 14 48 10 12 I I ze, 17 XA7 22 21 20 19 28 27 26 25 24 23 16 18 17 P2 XA4 XA5 PI £_L XA1 XA9 P2 INPUT BUFFER CO CO SHLD cl CI SHLD C3 C3 SHLD C2 C2 SHLD C4 C4 SHLD C5 C5 SHLD C6 C6 SHLD C7 C7 SHLD TEST LEVEL TEST LEVEL SHLD 3ATA RDY TIME SAMPLE TIME SAMPLE SHLD DATA RDY SHLD RANGE COVER RANGE COVER SHLD AZ SI AZ S2 AZ S3 SYNCHRO. CONVERTER At SYNCHRO OUTPUT Rl A5 EL SI EL S2 EL S3 SYNCHRO CONVERTER A3 INPUT BUFFER A9 SYS TRIG SYS TRIG RTN J WIRING DIAGRAM-WR57 RADAR TO R540 IDE R450-WR57 DVIP R6I I XA7 CO (LSB) X CO RTN 20 CI Y CI RTN 21 C2 C2 RTN C4 RTN C5 C7 C7 RTN z 22 a 23 b 24 c 25 d 26 e 27 XA5 TEST LEVEL TEST LEVEL RTN DATA RDY TIME SAMPLE TIME SAMPLE RTN DATA RDY RTN XA8 PRF RATE RTN 43 y NOTES: 1 A9-2 INPUT FOR RADAR RANGE C0VER:HIGH=450, L0W=230 TEST LEVEL: HIGH=NORM, LOW=TEST TIME SAMPLE:L0W=I5, HIGH=3 I DATA RDY:LOW=TRUE 2 CONNECTIONS NOT SHOWN J3-39 TO J3-23 J3-37 TO J3-2I J2-34 TO J2-42 J3-35 TO J3-I9 J2-37 TO J2-4 J2-36 TO J2-3 J2-40 TO J2-7 J2-39 TO J2-6 J2-38 TO J2-5 J2-I TO J3-I J2-2 TO J3-40 J3-I4 TO J3-I5 J3-26 TO J3-33 J3-rr TO J7- (I) 3 SYNCHRO TRANSIENT PROTECTION ASSY. CRI AND CR2 RADAR CONSOLE ji i pi i TB 207 AZ SI 1 AZ S2 2 AZ S3 3 Rl 6 R2 8 TB 209 EL SI EL S2 EL S3 SYS TRIG SYS TRIG RTN PI I IDE Nl BZ — AAA— -B5--WV-- R7 R8 ,.,/w- rs P3 CARD RACK ! ASSEMBLY J3 P2 J2 P3, J 3 XA7 P2 XA4 6 2 4 XA5 35 33 PI £J_ XAi XA9 CO CO SHLD 51 C_l SHLD C3 C3 SHLD C2 C2 SHLD C4 C4 SHLD C5 C5 SHLD C6 C6 SHLD TEST LEVEL TEST LEVEL SHLC 3ATA RDY TIME SAMPLE TIME SAMPLE SHLD DATA RDY SHLD RANGE COVER RANGE COVER SHLD AZ SI AZ S2 AZ S3 SYNCHRO OUTPUT Rl AS PI EL SI EL S2 EL S3 SYNCHRO CONVERTER , A3 P2_ INPUT BUFFER A9 SYS TRIG SYS TRIG RTN J WIRING DIAGRAM-WR57 RADAR TO R540 IDE R450-WR57 I. RISM=RANGE INTERVAL SELECT =RANGE COVERAGE 2. TSSM=TIME SAMPLE SELECT 3. TEST SIG MON=TEST LEVEL 4. IFATBPM=IF AT TENUATOR.BYPASS MODE 9. A9-P2 INPUT FOR 74C RADAR RANGE COVERAGE:HIGH=450KM TEST LEVEL:HIGH=NORM,LOW=TEST TIME SAMPLE:HIGH=I5,L0W 3 1 IFATBPM:HIGH=ON LOW=NORMAL DATA RDY:LOW=TRUE WIRING DIAGRAM WSR74 TO R54I IDE R45 i-WSR7^ RADAR CONSOLE DVIP I A4 INPUT BUFFER AI2 FT~ RlsiF 130 lWflWW'34 32 35 28 STCM' DATA RDY TSSM' VOL I VOL 2 VOL 3 VOL 4 VOL G VOL 7 VOL 8 XAI2 VOL 2 RTN VOLS RTN VOL 7 RTN VOL 6 RTN VOL 5 RTN VOL 4 RTN VOL I RTN VOL 3 RTN TEST SI6 - MON S22B X J M P R- T Z V F B E H G D Y W U S Q N L K RHI I A3 INPUT BUFFER AI2 EL .1 EL .2 EL .4 EL .8 EL .1 EL .2 EL 4 EL 8 EL 10 EL 20 EL 40 EL 80 EL 100 EL 200 EL INH EL INH RTN PPI I A2 INPUT BUFFER Al 2 1=1 AZ .1 AZ .2 AZ .4 AZ .8 AZ I' AZ 2 AZ 4 AZ 8 AZ 10 AZ 20 AZ 40 AZ 80 AZ 100 AZ 200 AZ INH XAI AZ INH RTN RTN [. P3 SYSTEM TRIGGER NOTES: i . RISM-RANGE INTERVAL SELECT =RANGE COVERAGE 2. TSSM-TIME SAMPLE SELECT 3. TEST SIG MON-TEST LEVEL A. IFATBPM=IF AT TENUATOR.BYPASS MODE 5. A9-P2 INPUT FOR 74C RADAR RANGE COVERAGE:HIGH-450KM TEST LEVEL.HIGH-NORM.LOW-TEST TIME SAMPLE:HIGH-15,L0* 3 1 IFATBPM.HIGH-ON LOW-NORMAL DATA RDY'LOW-TRUE WIRING DIAGRAM WSR74 TO R54I IDE R45!-WSR7^ TIME EL SYNC S4 MO/DAY (STATUS SELECT) NOTES: S3 ICIOCK CONTROL) 5 < 6 3 {CHANNEL MONITOR) I PART OF N I A I A I (BATTERY CHARGERI 2. EVEN PINS N/C EXCEPT 72 3. PART OF BACK PLANE ASSY. IN I N2A I 21 4. SWITCHES VIEWED FROM REAR 5. JUMPERS FROM PIN TO PIN ARE BARE WIRE OR CLEAR INSULATION UNLESS OTHERWISE NOTED 6. EXCEPT WHERE NOTED. ALL REFERENCES TO "PI "ON THIS PAGE ARE TO NIN2 PI 7. ALL SWITCHES AND FUNCTIONS VIEWED f ROM REAR. . WIPER PINS ON S2 AND S4 ARE ON OPPOSITE SIDE OF WAFER. S2 S3- I 8 WHT/BLK S5 J-A 2 I (FAST SET) WHT/BLK — •— YEL/GRN > « 1> P26 I 2 (SLOW SET) (NIAIAI) TBI, TU, Ul OTHERWISE SPECIFIED: IONS ARE IN INCHES NCES: ANGLES ± 5» E DECIMALS 1 005 E DECIMALS 1 .02 r totm of c ENGINEERING DIVISION SILVER SPRING, MD. 20910 PREPARED Qeflg^ CHECKED DESIGN fl£ APPROVEO BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE R540-54 I FRONT PANEL N I A I ■5I7T _c_ SCALE DATE DRAWING NO. R450-NI Al-I SHEET FILE viQUT/HMiTt/irnPi ii S»£EN XAl-7 NIN2 PI NIAI CONTROL PANEL ROTARY SWITCHES (NOTE 5) NIN2 PI ♦ 5V »5V ISOLATED 2 J BLACK jg^j ^otcu XDS2 Qj - i2v y ) OFF TBI -4 (NOTE 31 S4 MO/DAY (STATUS SELECT) NOTES: a S3 (CLOCK CONTROL) : c^: (CHANNEL MONITOR) 1. PART OF NIAI A I (BATTERY CHARGER) 2. EVEN PINS N/C EXCEPT 72 3. PART OF BACK PLANE ASSY. INI N2A 1 2) 4. SWITCHES VIEWED FROM REAR 5. JUMPERS FROM PIN TO PIN ARE BARE WIRE OR CLEAR INSULATION UNLESS OTHERWISE NOTED 6. EXCEPT WHERE NOTED, ALL REFERENCES TO "PI "ON THIS PAGE ARE TO NIM2 PI T. ALL SWITCHES AND FUNCTIONS VIEWED FROM REAR. _ WIPER PINS ON S2 AND S4 ARE ON OPPOSITE SIDE OF WAFER. S2 S3- I 8 WHT/BLK 3 CO _L J _L — '- -^** WHT/BLK — <— YEL/SRN^ 2 I (FAST SET) I 2 (SLOW SET) TBI-21NOTE 31 DARK BLUE S3 - 1 LIGHT BLUE TBI-21H0TE II ORANGE TBI-3IN0TE II (NIAI All TBI, TU, Ul SI , WHITE/ORAY TBI -3 INOTE 3) NIAI CONTROL PANEL-REAR VIEW (PARTIAL) UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES TOLERANCES: ANCLES ± .5' 3 PLACE DECIMALS * 005 2 PLACE DECIMALS t .02 ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SILVER SPRING, MD. 20910 R540-54 1 FRONT PANEL NIAI -^■MB bV PREPARED Q,£C£liJJ CHECKED QP DESIGN APPROVED BY SIZE C DATE DRAWING NO. R450-NIAI-I 1 ^B^ APPROVED BY 1 "*»ENT Of «• SCALE SHEET | FILE CRI IN4I48 -W P/0 TBI P/0 ASSY 8501287 r IN ADJ OUT BATT IN Ul LMII7K OUT AOJ r CHG. ON (FRONT PANEL) — Bl I \ TO CLK/DISP BD L J SS OTHERWISE SPECIFIED: NSIONS ARE IN INCHES RANCES: ANGLES ± .5' ACE DECIMALS ±005 ACE DECIMALS ± .02 »a£j£22£* ?r *«FNT Of ENGINEERING DIVISION SILVER SPRING, MD. 20910 PREPARED frefc)^ ^Q [& CHECKED DESIGN JSP APPROVED BY APPROVED BY U. S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE BATTERY CHARGER CCA ■sTZT _c_ SCALE DATE 12/17/84 DRAWING FEE R450-CH0R- SHEET FILE 115 VAC 470 30V R3 I00K C2 0.1 T R2 -WV- 10 Rl 121 1% CRI IN4I48 -W P/0 TBI u P/0 ASSY 8501287 ADJ OUT Q«" Ul LMII7K |ADJ OUT r i CHG. ON (FRONT PANEL) -=■ Bl TO CLK/DISP BO L S NOTE: UNLESS OTHERWISE SPECIFIED: I. PARTIAL REFERENCE DESIGNATION ARE SHOWN. FOR COMPLETE DESIGNATIONS PREFIX WITH NIAIAI. 2. RESISTANCE VALUES ARE IN OHMS. 3. RESISTORS ARE I /4 WATT, 5% TOL . 4. CAPACITANCE VALUES ARE IN MICROFARADS. FIGURE 10-20 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES t .9" 3 PLACE DECIMALS ± 005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING, MD. 20910 PREPARED frafcUyy ^Olff* CHECKED DESIGN APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE BATTERY CHARGER CCA tizt _C_ SCALE DATE 12/17/84 BftAWINfl NO. R450-CH0R- SHEET FILE F O E3I E29 E8 E5 E6 E3 E4 E I E2 o t2l E24 E23 E26 E25 E28 F?7 o O tlb EI5 EI8 EI7 E20 EI9 F?? O O O EIO O E9 — EI2 Ell EI4 EI3 E30 E32 F33 o FIND NO. ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REQO PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES I 5* 3 PLACE DECIMALS t .005 2 PLACE DECIMALS i .02 ENGINEERING DIVISION SILVER SPRING, MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DISPLAY MOUNTINNG BOARD NO. 1 NIAIA3 SCHEMATIC DIAGRAM ^ W PREPARED '\)2MU^ CHECKED sQ$ DESIGN APPROVED BY SIZE D DATE 12/17/84 DRAWING NO. R450-A 1 A3- 1 APPROVED BY ^*t *NT Of ^ SCALE SHEET | FILE NOTES'. UNLESS OTHERWISE SPECIFIED: I. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN. FOR COMPLETE DESIGNATION PREFIX WITH NIAIA3. 2 RESISTANCE VALUES ARE IN OHMS. 3. RESISTORS ARE 1/4 WATT, 5% TOL. HIGHEST REFERENCE DESIGNATION Ml 1 U4 1 C2 | | | | | REFERENCE DESIGNATIONS NOT USED REF DESIG DEVICE CONN +5V GND Ui.ua, U3.U4 9370 16 8 FIGURE 10-22 UST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±.5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ±.02 mm ENGINEERING DIVISION SILVER SPRING. MD. 20910 SjiiE xP APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DISPLAY MOUNTINNG BOARD NO. I NIAIA3 SCHEMATIC DIAGRAM SIZE DATE D 12/17/84 DRAWING NO. R450-AI A3- | FILE DS4 n — I E *° B fL DP +5V« 14 DS5 + 5V« 5 OTHERWISE SPECIFIED >IONS ARE IN INCHES ANCES ANGLES ± .5' :E DECIMALS ± 005 :E DECIMALS ± .02 ^O WMOSq^ '''Hent of c ENGINEERING DIVISION SILVER SPRING, MD. 20910 PREPARED CHECKED DESIGN ££. APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DISPLAY MOUNTING BOARD NO. 2 NIAIA2 SCHEMATIC DIAGRAM -5I7T ^_ SCALE DATE .12/17/84 DRAWING NO. R450-A I A2- I SHEET FILE NOTES' UNLESS OTHERWISE SPECIFIED I. PARTIAL REFERENCE DESIGNATIONS SHOWN. FOR COMPLETE DESIGNATIONS PREFIX WITH NIAIA2. FIGURE 10-2 1 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± .5' 3 PLACE DECIMALS I .005 2 PLACE DECIMALS * .02 ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SILVER SPRING, MD. 20910 DISPLAY MOUNTING BOARD NO. 2 NIAIA2 SCHEMATIC DIAGRAM PREPARED CHECKED fP DESIGN APPROVED BY SIZE C DATE .12/17/84 DRAWING NO. R450-AI A2-I APPROVED BY SCALE SHEET [FILE R38 32 K 03W, 01% -Wv- R37 I6K 2|2 £*£ 3wroi i| 4| el ill < CO O O ? ? 2 U2 CD U Q .' £ V £ R69 3K R7I I00K -vw — •- R70 200K _wv — I/8W, l%j I/8W, 1% LMI24 LMI24 R5I I00K I/8W, 1% + 7V I/8W, 1% C30 4 .01 r -7V 8 RST U30 DISCHOUT THD TRIG LM555H CONTV 5 C391 .01 R53 I0K 1 C40 2700PF -7V A U32D 13 R46 00 R47 I0K -7V 2JU23A, CD400I 3 II CD40II CD40I I 12 U32C V 10 CD4069 U3I TP6 U32A CD40II TP9»>-^ F/ U31 7 CD4069 12 U32B V o \ CD40II (•TP7 J UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES ANGLES ± .5' 3 PLACE DECIMALS ± 005 2 PLACE DECIMALS * .02 j.oMMOS- '"'Went of c ENGINEERING DIVISION SILVER SPRING, MD. 20910 PREPARED CHECKED DESIGN D.Sclt-U>v u/o/'gH J£. APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SYNCHRO CONVERTER CCA Nl A I A3/A4 SCHEMATIC DIAGRAM "sTTF c SCALE DATE 12/17/84 DRAWING NO. R450-A I A3/AA-2 SHEET 2 OF 3 I FILE +7V R40 22K -vw IZ2D REF FIGURE 10-24 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± .5* 3 PLACE DECIMALS t .005 2 PLACE DECIMALS * .02 ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SILVER SPRING, MD. 20910 SYNCHRO CONVERTER CCA NIAI A3/A4 SCHEMATIC DIAGRAM ^Hent of ctr PREPARED D.ScUJU*v izhKH CHECKED |BP DESIGN APPROVED BY SIZE C OATE 1 2/ 1 7/84 DRAWING NO. R450-AI A3/AA-2 APPROVED BY SCALE SHEET 2 OF 3 |FILE ♦7V < as o o o o o o U7 CD40I92 -=o ► 7V < CD o Q.-.2 _J < < < < i-o. CC < < < < -I CD Q O Q Q U 15? 9 |I0| 1 1 IS .) 14 Q U27A J2T" £5 RST2 Q2 CLK2 +7V SET2 -7V III CD4027 12 K| oi RST| J, CLK| ** U27B - SET| ' -7V 13 ^ U8 CD40I92 OQ too" < _: <<<< jo o o a a u -i 9 ll0| I|l5|l4 ll1f U7 CD40I92 OQ _l < < < £h APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL. OCEANIC 8t ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SYNCHRO C0NNVERTER CCA Nl A I A3/A4 SCHEMATIC DIAGRAM. SIZE DATE D 12/17/84 DRAWING NO. R450-A2A3/A4-3 SHEET 3 QF 3 066 3UT-D ONTO OUT-C iONTC XIT-B 3NT-B )UT-A 5NT-A 366 DUT-A ONT-A Dur-B- :dnt-b- IIUT-C DNT-C OUT-D ONT-D 9 _b .10 AZSII AZSIO AZS9 AZS8 AZSI2 AZSI3 I t ♦ ^H ^ ! 'CR3 TP4 CD4069 U2IA |R7 IR4 |R3 |R2 + |C26 P 'i TP3 L — VVVf- 120 [ l/2W^ CRI IN4462 lee 68K HM7602 01 CS 02 A4 03 U7 A3 04 A A2 05 06 AO HM7602 Ql AO 02 Al 03 U6 A2 04 C A3 05 A4 06 CS 1 T 27 2 2 120 I/2W 1 - CR2 JN446? CD4066 CONT-D IN-D OUT-D IN-CCONT-C IN-B OUT-C IN-ACONT-B OUT-B CONT-A U2 OUT-A CD4066 ]47K I47K47K OUT-A IN-A CONT-A IN-B OUT-B IN-C CONT-B IN-D OUT-C CONT-C OUT-D CONT P=| CD4069 U2IB 3 Tl 2 I-5V 3. RIO 47K R8 4 7K ■JW. CD4066 OUT-A CONT-A U3 OUT-B CONT-B IN-A OUT-C IN-B CONT-C IN-C OUT-D IN-D CONT-D jr 14 PI RI3"7K -vw RI4 " 7 K I — wv CD4066 3 U8 U9 UIO UN 113 UI5 fC3 TC8 TC9 Tcio Ten TCI3 TCI5 r T X T T T T OUT-A CONT-A U4 OUT CONT-B IN-A OUT-C IN-B CONT-C IN-C OUT-D IN-D CONT-D UI7 UI8 DECOUPLING CAPACITORS 1- 50V, TYP TCI7 TCie TC20 TC22 T T T T ~Tc24 )- >-• )-• ELSII ELSIO ELS9 ELS8 ELSI2 ELSI3 REFERENCE OUTPUT HIS II5VAC 60 HZ ELS4 ELS5 ELS6 ELS7 ELSO ELSI FIND ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REOD SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± V 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS * .02 A ^JJEgfej, ENGINEERING DIVISION SILVER SPRING. MD. 20910 PREPARED tSeD=CBtf< CHECKED ££. «.(n|gR27 >82K 19 1615 8Q7Q6Q5Q4Q3Q2QIQ OC 54LS373 EG UI7 8D7D6D5D4D3D2DID DECOUPLING CAPACITORS 0.1- 50V, TYP _l£l8 JC20_IC22 J_ T T T ~Ta* REFERENCE OUTPUT Rl II5VAC60HZ R2, ELSO ELSI ELS2 ELS3 FIGURE 10-25 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±.5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS 1 .02 VHP LIST OF MATERIAL ENGINEERING DIVISION SILVER SPRING. MD. 20910 PRE PARED & gDgccp< CHECKED [ g^) a.|n|g/ U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SYNCHRO OUTPUT CCA Nl A2A5 SCHEMATIC DIAGRAM SIZE I n«Tf D |I2/ 17/84 DRAWING NO. R450-A2A5-I ECIFIED IATIONS ARE SHOWN sIS PREFIX WITH % TOL. OHMS. MICROFARADS. c 3 V I I U2 U3 US U6 U7 U8 U9 UIC U 1 1 1111111111 /tn ^T^ 'T^ 'T'* , T N 'T* 'T^ ^T^* 'T* 'T^ JCI JC2 |c3 |c5 |C6 JC7 JcB |c9 }ciO | (l DECOUPLING CAPACITORS I-50V TYP t UI2 UI3 UI4 UI5 UI6 UI7 UI8 UI9 U20 J2I 1111111111 X ••TV /TN /*Ts /TN <^TN ^T^ •*TN /"TN ST** ^ CI2 C13 CI4 CIS CI6 I CI 7 CI8 CI9 |C20 C2 I W 2 U 3 13 SI6I CET CEP 10 o m > O l/» X CD z o t> > m 1 mi h -^ uJnM APPROVED BY APPR0VE0 BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DE RECEIVER CCA NIA2A6 SCHEMATIC DIAGRAM SIZE D DATE 12/17/84 DRAWING NO R450-A2A6- I SERIAL INPUT «t 54LSI64 B CLR QA QBQC QDQEQFQG QH 3 4 5 6 10 II 12 13 4 2 I 13 12 I H G F E D C 54LS280 UI4 B A ODD EVEN NOTES ^ UNLESS OTHERWISE SPECIFIED I. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN. FOR COMPLETE DESIGNATIONS PREFIX WITH NIA2A6. 2.DI0DES ARE TVS505. 3.RESIST0RS ARE 1/4 WATT, 5% TOL. 4.RESISTANCE VALUES ARE IN OHMS. 5. CAPACITANCE VALUES ARE IN MICROFARADS. I U2 U3 US U6 U7 U8 U9 UIC Ull 1111111111 •-T-N •"T*^ ^T"N ST~* ^TN ^T^. ^TN 'T^ ^T^ *T> |ci [C2 [C3 |c5 [C6 |C7 Ic8 Ic9 IciO |cil + |_2 2 3-Tv'SV -Xl£2 54LSI64 A UI6 B OA QB OC QO QE QFQGQH CLR -2-1 CLK 3 4 5 6 10 II 12 13 IQ 2Q 3Q4Q5Q6Q 7Q 80 EG UM _ 54S373 07; ID 2D 3D4D5D6D7D8D 3 4 7 8 13 14 17 18 DECOUPLING CAPACITORS I-50V TYP t UI2 UI3 UI4 UI5 UI6 UI7 UI8 UI9 U20 J2I llllllllll •tn /r\ •fx /T\ •-r* /tn ^T^ ^T^ T* ^p CI2 C13 CI4 Ici5 Ici6 Ici7 Ici8 Ici9 |C20 C2 54LSI U20C T ET D0"|D2D 3 _ _7J CE p U2 TC Q Q| 02 Q3 I2l 773 Q 0°I°2 Q 3 UI3 54LSI6I D 0, D 2 D 3 33. IT ~1 ) 6 ' 7 59 51 43 45 4749 15 13 3" II 9 £| 51 > > 3D £ > §51 > X > O Z xH x d m i| -jo| -I o| T O * c x| O J> HIGHEST REFERENCE DESIGNATION U2I | C24| CRI | R3 | TP5 | REFERENCE DESIGNATIONS NOT USED C4 FIGURE 10-26 U20B 54LS0 U7D ^4S04 r-^ju^xA- UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± V 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS * .02 LIST OF MATERIAL ENGINEERING DIVISION SILVER SPRING, MD. 20910 prepared D.eoei£N aiilvf CHECKED &> U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DE RECEIVER CCA N I A2A6 SCHEMATIC DIAGRAM SIZE DATE D 12/17/84 DRAWING NO. R450-A2A6-I CR3 -H — BATT CR2 -M— CRIO -H '_[, (V, E l D CLK CD403B FIND NO. ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REQD PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MA TERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± 5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS t .02 ENGINEERING DIVISION SILVER SPRING. MD 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE CLOCK/DISPLAY CCA NIA2A7 SCHEMATIC DIAGRAM PREPARED OeoBusM ^->\tH CHECKED & DESIGN APPROVED BY SIZE D DATE 12/17/84 DRAWING NO R450-A2A7-I APPROVED BY ■*n *ENT Of ^ SCALE SHEET | OF 2 | FILE NOTES: UNLESS OTHERWISE SPECIFIED: 1. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN. FOR COMPLETE DESIGNATIONS PREFIX WITH NIA2A7. 2. RESISTANCE VALUES ARE IN OHMS. 3. RESISTORS ARE 1/4 WATT, 5% TOL. 4. CAPACITANCE VALUES ARE IN MICROFARADS. 5. ALL DIODES IN4I48 CR2 THROUGH CRIO. HIGHEST REFERENCE DESIGNATION U29 C46 CRII Yl R54 TP4 Ql REFERENCE DESIGNATIONS NOT USED C5 C9 CI2 CI3 C|7 C34 69,70. 71,72 tT — 1— » + ;; TP3 Li: T T * » 47 TP2 T4>" TP « »+5 P/ol~ PI (_ D7jdTd;d3P4B551d7 17 19 21 23 25 27 29 31 R44 >P45 BOH B2 B3B4 BSB6 B7 AO Al A2 A3 A4 A5 A6 A7 SWI SW2 X UIO Jrs; >3.3 CD407 IB UI2D 1"T Q7 D7 Q6 D6 Q5 D5 04 U25 Q3 D4 D3 Q2 D2 Ql Dl 00 DO 54LS86 k2C <3J_ it <3f. SEE' <^ui9Bt7 54LS86 it AM BLANKING UI5 g MM54C9I5 D ^ *^L UI4 MM54C915 £ s?° OUTPUT COMMON SOURCE 50/60 HZ SELECT MM73I7B UI3 ALARM DSP INPUT 5 a» CR2 -r»— BATT J2l C35. , B2pf 3.579 ;iCR8 i;CR7 " CLK CD40I3B FIGURE 10-27 FIND NO. ELEC REF DES NOMENCLATURE OR DESCRIPTION QTY REQD PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL UST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±.5* 3 PLACE DECIMALS ± .003 2 PLACE DECIMALS * .02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE CLOCK/DISPLAY CCA. NIA2A7 SCHEMATIC DIAGRAM warn PREPARED beoBusM «ji->r«4 CHECKED & DESIGN APPROVED BY SIZE D DATE 12/17/84 DRAWING NO. R450-A2A7-I APPROVED BY ■*H »fTCf °* SCALE SHEET | OF 2 1 FILE 1 !9 I ' 1 51 1 ' 1 17 r R2 2 K I % CRI 'JMN754 10V R5 2 2 IK 1% R48 ■M\ — J UNUSED GATE REF DESIG DEVICE PWR a GND CONNECTION + 5V GND + I2V -I2V Ul 54LS373 20 10 U2 54LS373 20 10 U3 54LSI74 16 8 U4 54LSI74 16 8 U5 DA0-08A 1.2 13 3 U6 54LS25I 16 8 U7 54LS25I 16 8 U8 CD40I3B 14 7 U9 MM5369 8 2 UIO CD4028B 16 8 Ull CD400IB 14 7 UI2 CD407IB 16 8 UI3 MM73I78N 29 30 UI4 MM54C9I5 18 9 UI5 MM54C9I5 18 9 UI6 MM54C9I5 18 9 UI7 LM555 8 2 UI8 MM54C9I5 18 9 UI9 54LS86 14 7 U20 54LS2I 14 7 U2I 54LS86 14 7 U22 54LS240 20 10 U23 54LS2I 14 7 U24 54LS373 20 10 U25 54LS373 20 10 U26 54LS373 20 10 U27 54LS373 20 10 FIND NO. NOMENCLATURE OR DESCRIPTION DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± .5° 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS I .02 ATMOSjfc. 'VIENT Of C ENGINEERING DIVISION SILVER SPRING, MD. 20910 prepared b.z&tk*- oJ'~>W ~m APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE CLOCK/DISPLAY CCA N I A2A7 SCHEMATIC DIAGRAM SIZE D DATE 12/17/84 DRAWING NO. R450-A2A7-2 SHEET Z Ul- Z I F«-E I5V » U »' u » 2 u » 3 " t 4 U t 6 V U t 8 U J ° " » ' U li 4 u » 5 u ', 6 le i |C 2 |c 3 |c 4 |c 6 |c 7 |c8 |ciO Ic I I Jci4 Jci5 Jcie 4 TTTTTTTTTTTT + 5V < U I 8 U I 9 U20 U2I U22 U23 U24 U25 U26 U2 7 |c i8 |c i9 |c20 |C 2I |C22 _|c23 _|c_24 |c25 [c26 |c27 X TTTTTTTTTT JT D6 30 D5 28 D4 26 D3 24 D2 22 Dl 20 00 18 DAY STATUS TIME L0 EL l_0 AZ LO M ONTH SYNC TIME HI EL HI AZ HI DECOUPLING CAPACITORS O.IUF. 50V, TYR -L-C44 ■^r-o.i -C42 ^po.i 1-0.1 D4 Q5 D3 04 02 U4 Q3 01 02 DO CLK DO CLK II 54LS373 or 54LS373 2 C38 22/(f C29 HI— C3 TT 2.2/(f |C32 DAC&0/e 6 } iCRI '|N754 10V :■ 2.2IK UNUSED GATE 54LS2I H^ REF DESIG DEVICE PWR a GND CONNECTION + 5V GND + I2V -I2V Ul 54LS373 20 10 U2 54LS373 20 10 U3 54LSI74 16 8 U4 54LSI74 16 8 U5 DA0-O8A 1,2 13 3 U6 54LS25I 16 8 U7 54LS25I 16 8 U8 CD40I3B 14 7 U9 MM5369 8 2 UIO CD4028B 16 8 Ull CD400IB 14 7 UI2 CD407IB 16 8 UI3 MM73I78N 29 30 UI4 MM54C9I5 18 9 UI5 MM54C9I5 18 9 UI6 MM54C9I5 18 9 UI7 LM555 8 2 UI8 MM54C9I5 18 9 UI9 54LS86 14 7 U20 54LS2I 14 7 U2I 54LS86 14 7 U22 54LS240 20 10 U23 54LS2I 14 7 U24 54LS373 20 10 U25 54LS373 20 10 U26 54LS373 20 10 U27 54LS373 20 10 FIGURE 10-27 FIND NO. ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REQD PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL UST OF MATERIAL UNLESS OTHERWISE SPECIFIED; DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±.5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ±.02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE CLOCK/DISPLAY CCA N 1 A2A7 SCHEMATIC DIAGRAM m H6P PREPARED b-ZM&t*. «.!'-> W CHECKED £p DESIGN APPROVED BY SIZE D DATE 12/17/84 DRAWING NO. R4GO-A2A7-2 APPROVED BY «NTOf^ SCALE SHEET Z . 10 UI4B \£ 1 ^ 54LS20 4 TTTXs 2 1 54LS20 54LS244 NOTES UNLESS OTHERWISE SPECIFIED I- PARTIAL REFERENCE DESIGNATIONS ARE SHOWN FOR COMPLETE DESIGNATIONS PREFIX WITH 2-RESISTANCE VALUES ARE IN OHMS. 3- RESISTORS ARE 1/4 WATT, 5% TOLERANCE 4- CAPACITANCE VALUES ARE IN MICROFARADS P/0 --PI 9 DAY 7 OATS 43 AH 45 AL 47 EH 49 EL 1 5 TH 1 3 TL 37 1 1 STATUS MO HIGHEST REFERENCE DESIGNATION C33 CR4 02 R42 TPII U23 PI Yl REFERENCE DESIGNATIONS NOT USED C9 DESIG PWR BGND CONN DEVICE ♦5V ♦12V -I2V GND Ul MHQ600I 187 8SI4 U2 U3 U4 MHQ600I 187 8814 U5 54LS240 14 7 U6 54LSI65 16 8 U7 54LSI65 16 8 U8 HI-I8I8A-2 2 14 15 U9 «A760 B 5 UIO 54LS240 20 10 Ull 54LS244 20 10 UI2 54LS240 20 10 UI3 54LSI6I 16 8 UI4 54LS20 14 7 UI5 54LSI6I 16 8 UI6 5445 16 8 UI7 54LSI0 14 7 uie 54LSI32 14 7 UI9 54LS04 14 7 U20 54123 16 8 U2I 54LS74 14 7 U22 54LSI6I 16 8 U23 54S04 14 7 FIND ELEC REF NO DES NOMENCLATURE OR DESCRIPTION OTY REOD PART OR IDENTIFYING NO CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES 1 5* 3 PLACE DECIMALS ± 005 2 PLACE DECIMALS ± .02 '^SG&f ENGINEERING DIVISION SILVER SPRING. MD. 209)0 PREPARED btfpgcgKf >a-ji~>/^- <»-^-U2 54LS04 JI96 -ii&X>^ 54LSI32 UI8B 13 UI8D Wl 54LSIO 4 _L 13 III UI7A UI7C U6 U7 UIO UN UI2 UI3 UI4 UI5 UI6 UI7 UI8 UI9 U20 U2I U22 U23 rrxTrmrTXTrm /T*n ^T^ ^T*^ ^T^ ^T^ / ""T* N ^T^ / 'T S / 'T S / "T S ^T^ / *T" N ^V^ 'T^ x 'T Nv ' > |C6 |C7 ICIO jCII |CI2 |CI3 Ici4 JCI5 ]CI6 JCI7 JCI8 JCI9 |C20 Ic2l ]C22 C23 DECOUPLING CAPACITOR 0.1,50V U8 TL C8A -I2V OTHERWISE SPECIFIED: IONS ARE IN INCHES NCES ANGLES ± .5' ENGINEERING DIVISION U. S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE E DECIMALS ± 005 E DECIMALS ± .02 SILVER SPRING, MD. 20910 DE TRANSMITTER CCA Nl A2A8 SCHEMATIC DIAGRAM jg WMOg^ •?/„ PREPARED A NOflfl A. CHECKED PP ■^k. DESIGN H " *J^^4 m APPROVED BY SIZE C DATE 12/17/84 DRAWING NO. R450-A2A8-2 ^S APPROVED BY 'MENT Of v SCALE SHEET 2 OF 2 [file SPECIFICATION OR MATERIAL COMMERCE ;RIC ADMINISTRATION SERVICE \ NIA2A9 HAGRAM i- 1 I FILE C30 IZ5B IZ5& I.C. SECTIONS NOT USED MONITOR OUTPUT TO RCVR BOARD A B C OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 54LS244 54LSI32 U5 U6 U7 UIO UN UI2 UI3 UI4 UI5 UI6 UI7 UI8 UI9 U20 U2I U22 U23 sssems iiiiililliiimii 0.1,50V TYP 'Pg n^ 6 / "P 7 'jao'Tcil ^12^13 ^14 ^15^16 ^17^1 8 ^Tci9^|c20'^'2l / 7c22'lc23 DECOUPLING- CAPACITOR 0.1,50V I JO DECOUPLING ^ csb capaciJO.R -r^ 8A 0.1,50V ZL 54LS74 J3L 2PR 2CK 20 U2IB 2D 25 2CLR -I2V FIGURE 10-28 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± .5' 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SILVER SPRING, MD. 20910 DE TRANSMITTER CCA Nl A2A8 SCHEMATIC DIAGRAM PREPARED CHECKED tf DESIGN APPROVED BY SIZE C DATE 12/17/84 DRAWING NO. R450-A2A8-2 APPROVED BY SCALE SHEET 2 OF 2 |file A C39 1.2 -©- <. TP6 N BLK CR2 TVS505 "=" MSR-57 0RWISR-74C JUMPER E5 TO E6 E9 TO EIO OPEN SR-745 JUMPER E9 TO E I E5 TO E6 OPEN HIGHEST REFERENCE DESIGNATION UI6 |U38 I TP7 |RI04|C40[ Ql |CR2 REFERENCE DESIGNATIONS NOT USED C40 JUMPER SEQUENCE WSR 57 A2 A3 A5 A8 WSR 74C Al A4 A5 A8 WSR 74S Al A4 A8 NOTES : UNLESS OTHERWISE SPECIFIED : I. PARTIAL REFERENCE DESIGNATION ARE SHOWN. FOR COMPLETE DESIGNATION PREFIX WITH NIA2A9 10. 2. RESISTANCE VALUES ARE IN OHMS. 3. RESISTORS ARE 1/4 WATT, 5% TOLERANCE. 4. CAPACITANCE VALUES ARE IN MICROFARADS. NOTED COMPONENTS ARE USED ON Al ASS'Y. ONLY , AND ARE OMITTED FOR THE A2 ASS'Y. &> "TEI2 Je6 lEIO lEI6 Al A2 Al NOT Al 3NLY ONLY ONLY USED A2 !J9_E59_E99 EI59 EI3 1 8 I ~1 2 G> A2 ASSY WSR-57 Al ASSY WSR-74 PWR 8 GND CONNECTION + 5V GND I- +5v| I- GND ill Ul HCPL-2531 SEE SCHEMATIC / U2 U2 HCPL-2531 | < U3 U3 5407 1 I U4 U4 54122 SEE SCHEMATIC U5 U5 54LS240 20 10 - U6 54LS373 i> ii — U7 54LS373 — U8 54LS244 U8 - 54LS240 — U9 54LS373 i i' - UIO 54LS373 20 10 - Ul 1 54LSI4 1 4 7 UI2 UI2 il i ii UI3 UI3 UI4 UI4 - UI5 - UI6 •> 'i ' i - UI7 54LSI4 14 7 UI8 UI8 HCPL-2531 UI9 UI9 i SEE SCHEMATIC — U20 i — U2I — U22 U23 U23 U24 U24 — U25 — U26 — U27 U28 U28 — U29 — U30 - U3I - U32 U33 U33 — U34 — U35 - U36 1 — U57 HCPL-2531 i U38 U38 LMII 1 SEE SCHEMATIC FIND NO ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REOD PART OR IDENTIFYING NO. DWG SIZE CODE 1DENT SPECIFICATION OR MATERIAL LIST OF MA TERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES ANGLES 1.5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING, MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE INPUT BUFFER CCA N 1 A2A9 SCHEMATIC DIAGRAM 33P W PREPARED fcEyelo-, ia/»/w/ CHECKED / DESIGN APPROVED BY SIZE D DATE 12/18/84 DRAWING NO R450-A2A9- 1 APPROVED BY ^^ lENTOf 1 -" SCALE SHEET | OF 2 | Fll - E HIGHEST REFERENCE DESIGNATION UI6 |U38 1 TP7|RI04|C40| Ql ICR2 REFERENCE DESIGNATIONS NOT USED C40 JUMPER SEQUENCE WSR 57 A2 A3 A5 A8 WSR 74C Al A4 AS AS WSR 74S Al A4 AS \p NOTES : UNLESS OTHERWISE SPECIFIED : I. PARTIAL REFERENCE DESIGNATION ARE SHOWN. FOR COMPLETE DESIGNATION PREFIX WITH NIA2A9 10. 2. RESISTANCE VALUES ARE IN OHMS. 1 RESISTORS ARE 1/4 WATT, 5% TOLERANCE. 4. CAPACITANCE VALUES ARE IN MICROFARADS. NOTED COMPONENTS ARE USED ON Al ASS'Y. ONLY , AND ARE OMITTED FOR THE A2 ASS'Y. \P> A2 ASSY WSR-57 Al ASSY WSR-74 PWR 8 GNO CONNECTION + 5V GND I-+5v|l-GND Jl Ul HCPL-2531 SEE SCHEMATIC U2 U2 HCPL-2531 t U3 U3 5407 1 U4 U4 54122 SEE SCHEMATIC U5 U5 54LS240 20 10 - U6 54LS373 i - U7 54LS373 _ US 54LS244 U8 - 54LS240 — U9 54LS373 - UIO 54LS373 20 10 - UN 54LSI4 1 4 7 UI2 UI2 i . 1 1 UI3 UI3 UI4 UI4 - UI5 - UI6 1 " - UI7 54LSI4 14 7 UI8 UI8 HCPL-2531 UI9 UI9 SEE SCHEMATIC _ U20 - U2I — U22 U23 U23 U24 U24 — U25 — U26 — U27 U28 U28 — U29 - U30 - U3I — U32 U33 U33 - U34 — U35 — U36 — U37 HCPL-2531 ' U38 U38 LMIII SEE SCHEMATIC FIGURE 10-29 LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±.5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ±.02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 PBEPARED P-e^dlo-, B/«)g/ APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE INPUT BUFFER CCA N I A2A9 SCHEMATIC DIAGRAM SIZE DATE [3 12/18/8- DRAWING NO. R450-A2A9-I SHEET | OF 2 01 02 0304 05 0607 OC 54LS373 U7 EC 10 01 D203D40506D7 7 8 13 14 17 18 RI8 8.2K 2| 5| 6| 9|I2|I5|I6|I9 0001 020304Q5 0607 OC 54LS373 UIO EC 0001 02 0304 05 06 07 ^u 6 2 I 12 UI7DX zz_\ui7C /zz\ I 1 13 UI7E/ ZZ^UIIB /zz' 9 |5 UIIC, ZZ_\UI7F /zz' 9 |3 .10 16 UI6E A. ZZ_\UIID /zz^ II UIIE ZZ\UI6F /ZZ JjrTjriJTTJTTIJTID ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REOD PART OR IDENTIFYING NO DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES ANGLES ±5* 3 PLACE DECIMALS t 005 2 PLACE DECIMALS ± .02 XIMOSPu, ENGINEERING DIVISION SILVER SPRING. MD. 20910 D edtitvi ££. R|f>fg/ APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC 81 ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE INPUT BUFFER CCA N I A2A9 SCHEMATIC DIAGRAM SIZE D DATE 12/1 8/84 DRAWING NO R450-A2A9-2 sheet 2 OF 2 rjjTijriiriJTiirJiriiTiJrjjrjjrjjrjirijrjD SEE DET SHEET I AIL "A" OF 2- R70 5.6K C30A 0.1 Tout C2 e ci HCPL253I U25 OUT C2 E CI HCPL253I U30 OUT CI E C2 HCPL253I U35 R87 5.6 K C34A 01 OUT CI E C2 HCPL253I U2I OUT CI E C2 HCPL253I U34 OUT CI E C2 HCPL253I U29 R29 5.GK C20A Her 0.1 OUT CI E C2 HCPL253I U20 R74 5.6K C32A He 0.1 OUT CI E CI HCPL253I U32 J- R34 5.6 K C22A He 0.1 ZL OUT C2 E CI HCPL253I U22 T R53 5.6K C27B OUT CI E C2 HCPL253I U27 J,C27B T - 1 R94 5.6K C37A ne 0.1 OUT CI E C2 HCPL253I U37 RI032 330 I Xc37B T - 1 R 4 ! 2 104? 3301 R92 5.6K C36A ne 0.1 a OUT C2 E CI HCPL253I U36 T R52 5.6 K C26A ne 0.1 ~1 OUT C2 E CI HCPL253I U26 1 OUT CI E C2 HCPL253I U3I C34B 0.1 C20B 0.1 C22B C36B C26B • > FIGURE 10-29 LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES * .5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 prepared sedcltm Rl'~7fy/ JSE- APPROVED by U. S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE INPUT BUFFER CCA NIA2A9 SCHEMATIC DIAGRAM SIZE DATE Q 12/18/84 DRAWING NO. R450-A2A9-2 SHEET 2 OF 2 P/0 PI -CI 7 " 2000//F 10 V CI6 4.7/iF' 10V m T r 5802 CRI3 U4 412V REG .CIO " IOO//F 20 V T CR3 -P> — C4 -I-22//F 15V n C2 2 2//F 20 V U3 -I2V REG ,C3 ■ 22//F 15 V T CI : 2 2i/F 20 V ^Z iz xi ±C6 - 470// F 10 V ^ ;C5 ' 4 7//F 10 V JZ ISO GNO + 5VDC 5A • 5V INDICATOR + I2VDC INDICATOR -I2VDC I A -I2VDC INDICATOR + 5VDC ISOLATED INDICATOR ■F5VDC ISOLATED I A GND ISOLATED FIND ELEC Hit NO. DES DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES ANGLES ±5* 3 PLACE DECIMALS t 005 2 PLACE DECIMALS 1 .02 SSraf*' ENGINEERING DIVISION SILVER SPRING. MD. 20910 prepared p. eogua a|n|gn SlZ APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DE POWER SUPPLY ASSEMBLY AND POWER SUPPLY CCA N I A2A I /A2, SCHEMATIC DIAGRAM . D DATE 12/17/84 DRAWING NO R450-A2A I/A2-I L0II3VAC 60HZHI GND ISOLATED FIGURE 10-23 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±.5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ±.02 UST OF MATERIAL ENGINEERING DIVISION SILVER SPRING, MD. 20910 JET APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE DE POWER SUPPLY ASSEMBLY AND POWER SUPPLY CCA N I A2A I /A2, SCHEMATIC DIAGRAM . DATE 12/17/84 DRAWING NO. R450-A2AI II SPLAY lATA(BCD) MULTIPLEXED DATA BUS DATA STROBES SERIAL INPUT 4260065AI (NIA2A7) SERIAL RECEIVER (DAY^ MONTH, S TATUS , TIME LP, TIME HI. EL LO, EL HI, AZ LO, AZ HI, SYNC, DATA) FIND NO ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REOD PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES ANGLES ±5° 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING, MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE IDE SIGNAL FLOW DIARAM 1 ¥ PREPARED VSW-i CHECKED Tl RANGE COVERAGE TIME SAMPLE c> ANT ELEV. INHIBIT FRONT PANEL DVIP DATA Ctht 42600G3AI/A2 (NIA2A9) INPUT BUFFER AZ200.AZIOO. AZ90,AZ40,AZ20,AZI0. AZ8,AZ4,AZ2,AZI, AZ.8,AZ.4.AZ.2.AZ.I EL200.ELIOO, EL80,EL40,EL20,ELI0, EL8.EL4.EL2.ELI, EL.8.EL4.EL.2.EL.I c DATA STROBES 426006IAI (NIA2A4) SYNCHRO CONVERTER ^ SYNCHRO REF OUTPUT 426006IAI (NIA2A3) SYNCHRO CONVERTER ^> guild A AZSI2 AZSI3 SYNCHRO OUTPUT ELSO -ELSII \ QUADRANT BITS IS IS A 4260066AI (NIA2A6) CLOCK /DISPLAY r 4260077, 4260078 DISPLAY MOUNTING NO. I a NO. 2 AAAA s ■ 7-SEGMENT OUTPUT BUSES x„ i> DISPLAY SECTION c MULTIPLEXED DATA BUS •st- mt* STROBES CHANNEL SELECT SWITCH 42600 64AI (NIA2A8) TRANSMITTER SERIAL OUTPUT CHANNELS CHANNEL I 2 4260065AI (NIA2A7) SERIAL RECEIVER ( DAY, MONTH, S TATUS , TIME L P, TIME HI, EL LO, EL HI, AZ LO, AZ HI, SYNC, DATA) "1 55 co 33 ** IL co to CO FRONT PANEL FRONT PANEL FUNCTION SELECT SWITCH §§yt uu. tnvt FIGURE 10-19 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±5" 3 PLACE DECIMALS ±.005 2 PLACE DECIMALS ±.02 UST OF MATERIAL ENGINEERING DIVISION SILVER SPRING. MD. 20910 ij-afrku M^ U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE IDE SIGNAL FLOW DIARAM SIZE DATE D 12/17/84 DRAWING NO. R450-A-I *5V BUS 2,3,4 2,3,4 ,2 2,3,4 ,2,3,4 ,2,3,4 ,2,3,4 59,70,71,72 ,2,3,4 TABLE POWER AND GROUND CONNECTIONS +5V ISOL 51, 52 51, 52 + I2V BUS 59,60 59,60 59,60 59,60 63,64 4.30,31,39,40 67,68 67,68 65,66 67,68 63,64 41 59,60 16 -I2V BUS 55, 56 55, 56 55, 56 55,56 65,66 65,66 61,62 55,56 GND BUS 69,70, 71,72 69,70, 71,72 69,70, 71,72 69,70,71,72 69,70,71,72 GND ISOL 47,48 47,48 69,70,71,72 69,70,71,72 69, 70,71,72 69,70,71,72 1,2,3,4 69,70,71,72 67,68 7,9,11,13,15, 17,19,21,23, 25,27, 59,61, 63, 65, 67 67,68 32 47,48,49,501 35,41, 18 THRU 24 2 THRU 8, 17,18 20,22,32, 34,36,38,45, 47, 48, 50 E2,E4,E6,E8, EIO, EI2.EI4, EI6 DWG SIZE SPECIFICATION OR MATERIAL IED: S 5» ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SILVER SPRING, NID. 20910 BACKPLANE ASSEMBLY Nl A2AI2 INTERCONNECT DIAGRAM PREPARED \ CHECKED Pf> DESIGN I APPROVED BY r SIZE c DATE 12/17/84 DRAWING NO. R450-A2A 1 2- 1 APPROVED BY SCALE SHEET | OF 5 Ifile I. DEPARTMENT OF COMMERCE OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE lACKPLANE ASSEMBLY Nl A2AI 2 TERCONNECT DIAGRAM V84 DRAWING NO. H450-A2A I 2-2 SHEET 2 OF 5 o o o o U XA1-I XA2-I XA3-I XA4-I XA5-I XA6-I XA7-I XA8-I XA9-I XAIO-I 72lnl7l 7217171 72PI7I 7217171 721^71721^717211117172 n 7172| 7172 71 TBI jg]l 313 3®]4II5VAC NC II5VAC COM lU 10 ceo UJO OCJ Q-* l_ 10 ceo UJO *<0 a* I 2[UJl S2 o °5 I| oO Z<0 >C\J ILJ i °:-w col- M l< u I- 3 °< ON iro uio O<0 UJCVJ U'«IL 0-_ co< 5^ CD *o 00 010 I 2 UJ_ coo ZO ffl/ APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC 8t ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE BACKPLANE ASSEMBLY Nl A2AI2 INTERCONNECT DIAGRAM SIZE D DATE 12/17/84 DRAWING NO. R450-A2A I 2 SHEET 2 OF 5 XAI-I INIA2AI) GND BUS GND 72 7 GND GND BUS GND 70 69 GND 68 67 66 65 64 63 62 61 + I2V BUS + I2V 60 59 + I2V + I2V IND JI-35 + I2VIND 58 57 + I2V IND -\2\l BUS -I2V 56 55 -I2V -I2V IND JI36 -I2V IND 54 53 -I2V IND + 5V ISOL BUS 1 + 5V 5? 51 1 +5V I + 5V IND JI-37 1 + 5V IND 50 49 I + 5V IND GND ISOL BUS l-GND 48 47 l-GND 46 45 44 43 AC XA2-4I-42, TBI-3 II5V ACLO 42 41 1 15V ACLO 40 39 1 15V AC S 1 - 1 II5V ACHI 38 37 1 15V AC HI 36 35 34 33 32 3 30 29 28 27 26 25 24 23 22 21 20 9 18 17 6 5 4 13 12 10 9 + 5V IND JI-36 + 5VIND 8 7 + 5V IND 6 5 + 5V BUS + 5V 4 3 +5V + 5V BUS + 5V 2| 1 +5V XA2-I (NIA2A2) XA3-I INIA2A3) XA4-I INIA2A4) GND BUS GND BUS GND BUS GND BUS + I2V BUS + I2V BUS + I2V IND + I2V IND JI3< -I2V BUS -I2V BUS -I2V IND -I2V IND Jl-| +5V ISOL 3US + 5V ISOL BUS I+5V IND I+5V IND JI-18 GND ISOL BUS GND ISOL BUS 1 15V AC II5VAC XAI-41-42, TBI-3 II5VAC TB -2 1 15V AC S2-I +5V BUS + 5V BUS + 5V IND JI-35 + 5V BUS +5V BUS GND 7 2 71 GND GND 70 69 GND 68 67 66 65 64 63 62 61 + I2V 60 59 +I2V + 12V IND 58 57 +I2V IND -I2V 56 55 -I2V -I2V 54 53 -I2VIND 1 +5V 52 51 1 +5V I + 5V IND 50 49 I+5V IND l-GND 48 47 l-GND 46 45 44 43 II5V ACLO 42 4 1 15V ACLO 40 39 1 15V ACHI 38 37 1 15V ACHI, 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 2 20 19 18 17 16 15 14 13 12 II 10 9 +5VIND 8 7 +5V IND 6 5 + 5V 4 3 + 5V + 5V 2 +5V GND BUS GND BUS -H2V BUS + I2V INDXA2-I-58 -I2V BUS -I2V IND XA2-I-54 +5V ISOL BUS +5VIND XA2-I-50 GND ISOL BUS II5V ACXA2- T8I-3 1 15V AC XA2-I-38 GND BUS GNO BUS +5V IND XA2-I-8 +5V BUS +5V BUS -8.XA5-I-34 J3-I0 J3-I I J3-I2 GND 72 71 GND GNO 70 69 GND 68 67 66 65 64 63 62 61 + I2V 60 59 + I2V 58 57 -I2V 56 55 -I2V 54 53 52 5 50 49 EL S 13 48 47 EL SI2 46 45 EL Sll 44 43 EL SIO 42 41 EL S9 40 39 EL S8 38 37 EL S7 36 35 EL S6 34 33 EL S5 32 31 EL S4 30 29 EL S3 28 27 EL S2 26 25 EL SI 24 23 EL SO 22 21 20 9 18 17 16 15 14 13 12 1 1 10 9 REF 8 7 EL SI 6 5 ELS2 4 3 EL S3 2 1 GND BUS GND BUS XA5-I-52 XA5-I-5I XA5 -I- 54 XA5-I-53 XA5 -1-56 XA5 -1-55 XA5-I-58 XA5-I-57 XA5 -1-60 XA5 -1-59 XA5 -1-62 XA5 -1-61 XA5 -1-64 XA5 -1-63 GND BUS GND BUS + I2V BUS -I2V BUS XA3-I-8.XA5-I-34 03- 13 J3 -44 J3-4 3 GND 72 71 GND GND 70 69 GND 68 67 66 65 64 63 62 61 + I2V 60 59 +I2V 58 57 -I2V 56 55 -I2V 54 53 52 5 50 49 AZ SI3 48 47 AZ SI2 46 45 AZ Sll 44 43 AZ SIO 42 41 AZ S9 40 39 AZ S8 38 37 AZ S7 36 35 AZS6 34 33 AZ S5 32 31 AZ S4 30 29 AZ S3 28 27 AZ S2 26 25 AZ SI 24 23 AZ SO 22 21 20 19 18 17 16 15 14 13 12 11 10 9 REF 8 7 AZ SI 6 5 AZ S2 4 3 AZS3 2 1 GND BUS GND BUS XA5-I-4 XA5-I-3 XA5-I-6 XA5-I-5 XA5-I-8 XA5-I-7 XA5-I-I0 XA5-I-9 XA5-I-I2 XA5-I-II XA5-I-I4 XA5-I-I3 XA5-I-I6 XA5-I-I5 FIGURE 10-30 FIND NO. ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REOD PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± V 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC ft ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE BACKPLANE ASSEMBLY Nl A2AI2 INTERCONNECT DIAGRAM PREPARED D-eddw ttlnftff CHECKED /. ' DESIGN APPROVED BY SIZE D DATE I 2/ I 7/84 DRAWING NO. C1450-A2A I 2-2 APPROVED BY ^VtNTC* SCALE SHEET 2 OF 5 | FILE XA (NIA 7-1 2A7) XA8-I (NIA2A8) 72 71 GNO TO 69 GND 68 G7 BATT 66 65 + I2V 64 63 62 61 -I2V 60 59 A3, Dl 58 57 A2, Dl 56 55 Al, Dl 54 53 AO, Dl 52 51 SYNC 50 49 eTTo 48 47 EL HI 46 45 AZ LO 44 43 AZ HI 42 41 DVIP DATA 40 39 Z2 38 37 STATUS 36 35 Zl 34 33 ZO 32 31 D? 30 29 06 28 27 05 26 25 D4 24 23 03 22 21 D2 20 19 Dl 18 17 DO 16 15 TIME HI 14 13 TIME 10 12 l 1 MONTH 10 9 DAY 8 7 DATA STR ET 6 5 SLOW SET 4 3 + 5V 2 l + 5V GNO BUS GNO BUS XA7- 1-68 + I2V BUS -I2V BUS Jl- 13 JI-29 Jl- 12 Jl - 28 XA6 -1-51 XA6-I-49 XA6- 1-47 XA6-I-45 XA6- 1- 43 Jl- 15 Jl- l | XA6-I- 37 Jl - 27 Jl" 10 XA5-I-3I, XA8- -31, XA9- -31 XA5-I-29, XA8- -29, XA9- -29 XA5-I-27, XA8- -27, XA9- -27 XA5-I-25, XA8- -25, XA9- -25 XA5-I-23, XA8- -23, XA9- -23 XA5-I-2I, XA8- -21. XA9- -21 XA5-I-I9, XA8- -19, XA9- - 19 XA5-I-I7, XA8- -17, XA9- -17 XA6-I-I5 XA6-I-I3 XA6- l-ll XA6- 1-9 XA6-I-7 JI-26 +5V BUS + 5V BUS GND BUS GND BUS -I2V BUS Jl 46 J I -45 J I -44 . XA6-I-63 + 5V BUS + 5V BUS GND 72 71 GND GND 70 i,') GND -I2V 68 6/ + I2V A 66 65 OUT 8 B 64 6", OUT 7 C 62 61 OUT 6 MOT OUT 60 ! OUT 5 58 5 7 OUT 4 56 65 OUT 3 54 55 OUT 2 52 51 OUT 1 50 49 EL 48 47 T»" 46 4 6 AT 44 4} AH" 42 41 SYST. TRIG 40 39 DA T A READY 38 37 STATUS 36 36 34 53 32 31 6~7 30 29 06 28 2 7 D5 26 25 D4 24 2 3 D3 22 21 D2 20 19 Dl 18 1 7 DO 16 5 TH 14 13 TL 12 1 MO 10 9 oTTy 8 7 DATA 6 5 +5V 4 3 + 5V -I-5V 2 + 5V GNO BUS GND BUS + I2VBUS El E3 E5 E7 E9 Ell EI3 EI5 XA5-I-49, XA9- -49 XA5-I-47, XA9- -47 XA5-I-45, XA9- -45 XA5- 1-43, XA9- -43 XA9 -1-41 XA9- 1-39 XA9- 1-37 XA5- 1-31, XA7- 31, XA9- -31 XA5- 1-29, XA7- -29. XA9- -29 XA5 1-27, XA7- -27, XA9 -27 XA5- 1-25, XA7- - 25. XA9- -25 XA5- 1-23, XA7- -23. XA9- -23 XA5- 1-21, XA7- -21, XA9- -21 XA5- 1 - 19, XA7- - 19, XA9 19 XA5- 117, XA7- - 17, XA9- - 17 XA7- 1- 16 XA7- 1- 14 XA7- 1-12 XA7- 1 - 10 XA9- 1 - 7 +5V BUS + 5V BUS FIND ELEC REF OES NOMENCLATURE OR DESCRIPTION PART OR IDENTIFYING NO. DWG SIZE CODE I DENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ± 5° 3 PLACE DECIMALS ± 005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 PREPARED D.£dt/«r> win ^ AP APPROVED BY APPROVED BY U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE BACKPLANE ASSEMBLY Nl A2AI2 INTERCONNECT DIAGRAM SIZE D DATE 12/17/84 DRAWING NO R450-A2AI2-3 SHEET 3 OF 5 XA5 - I (NIA2A5) GNU BUS GND BUS + I2V BUS -I2V BUS XA3-I-25 XA3-I-29 XA3-I-33 XA3-I-37 XA3-I-4I XA3-I-45 XA3-I-49 XA3-I-8.XA4-I- XA4-I-25 XA4-I-I9 XA4-I-33 XA4-I-37 XA4-I-4I XA4-I-45 XA4-I-49 + 5V BUS GND 72 n GND GND 70 69 GND + I2V 68 67 + I2V -I2V 66 65 -I2V EL SI 64 63 EL SO EL S3 62 61 EL S2 EL S5 60 59 EL S4 EL S7 58 57 EL S6 EL S9 56 55 EL SB EL Sll 54 53 EL SIO EL SI3 52 5 EL SI2 50 49 TT 18 47 EH 46 45 TZ 44 43 AH 42 4 40 39 STB 38 37 36 35 RIIII5VACI REF 34 33 R21II5VAC) 3? 31 D7 30 29 06 28 ?r D5 26 25 D4 24 23 03 ?? 21 52 20 19 Dl 18 7 DO AZ SI 16 5 AZ SO AZ S3 14 13 AZ S2 AZ S5 12 AZ S4 AZ S7 10 9 AZ S6 AZ S9 8 7 AZ SB AZ Sll 6 5 AZ SIO AZSI3 4 3 AZ SI2 + 5V 2 1 +5V GND BUS GND BUS + I2V BUS -I2V BUS XA3-I-23 XA3-I-27 XA3-I-3I XA3-I-35 XA3-I-39 XA3-I-43 XA3-I-47 XA8-I-49, XA9-I-49 XA8-I-47, XA9-I-47 XA8-I-45, XA9-I-45 XA8-I-43, XA9-I-43 GND BUS GND BUS +I2V BUS -I2V BUS XA7 .-31, XA8- -31, XA9 1-31 KA7- XA7 1-29, XA8- -». XA9 29 XA7- XA7 1-27, XA8- -27, XA9 -27 XA7- XA7 1-25, XA8- -25, XA9 1-25 XA7- XA7 1-23, XA8- -23, XA9 -23 XA7- XA7 1-21, XA8- -21, XA9 1-21 XA7- XA7 1-19, XA8- -19, XA9 1-19 XA7 XA7 1- 17, XA8- -17, XA9 1-17 XA7- XA4 -1-23 XA4 1 27 XA4 -1-31 XA4 1-35 XA4 1-39 XA4 -1-43 XA4 1-47 + 5V + 5V BUS + 5V GND 72 71 GND GND 70 69 GND + I2V 68 67 + I2V -I2V 66 65 -I2V 64 63 SERIAL IN 62 61 AUX DATA 60 59 ERROR 58 57 56 55 54 53 5? 5 SYNCH 50 49 ELLO 48 4 7 EL HI 46 45 ATTS 44 43 AZ HI 4? 41 40 39 38 37 STATUS 36 35 34 33 D7 3? 31 D7 06 30 29 06 05 28 27 D5 D4 26 25 D4 D3 24 23 D3 D2 2? 21 D2 Dl 20 19 Dl DO 18 1 7 DO 16 15 TIME HI 14 13 TIME LO \? 1 MONTH 10 9 DAY 8 7 DATA STB 6 5 ■F5V 4 3 + 5V + 5V 2 I + 5V GND BUS GND BUS + I2V BUS -I2V BUS XA8 NC NC 60 XA7 1- 51 XA? 1- 49 XA7 1- 47 XA7 1- 45 XA7 1- 43 XA7 1- 37 XA6 1-32 XA6 1-29 XA6 1-27 XA6 1-25 XA6 1-23 XA6 1-2 1 XA6 1-19 XA6- 1-17 XA7 1- 15 XA7 1- 13 XA7 -1 - II XA7 1 - 9 XA7 1 - 7 + 5V BUS + 5V BUS GND BUS GND BUS Jl -33 +I2V BUS -I2V BUS JI-43 Jl- 19 JI-3 JI-20 JI-4 Jl - 21 JI-5 JI-22 JI-6 JI-23 JI-7 Jl 24 JI-8 XA6-I -31-32 XA6-I-29-30 XA6-I- 27-28 XA6-I-25-26 XA6-I-23-24 XA5-I-2I-22 XA6-I-I9-20 XA6-I-I7-IB XA8-I-I5 XA8-I- 13 XA8-I - I I XA8-I - 9 Jl -25 Jl - g + 5V BUS +5V BUS GND 72 71 GND GND 70 69 GND BATT 68 67 BATT + I2V 66 65 + I2V 64 63 -I2V 6? 61 -I2V 60 59 A3, 01 SW 58 57 A2, Dl A3.D2 56 55 Al, Dl A2.D2 54 53 AO.OI Al. 02 52 51 SYNC A0.D2 50 49 ETT6 A3.D3 48 47 EL HI A2, D3 46 45 AZ LO Al. 03 44 43 AZ HI A0.D3 4? 41 DVIP DATA A3, 04 40 39 Z2 A2, 04 38 37 STATUS Al. D4 36 35 Zl AO, D4 34 33 ZO D7 32 31 07 D6 30 29 06 D5 28 27 155 04 26 25 04 D3 24 ?3 53 02 22 21 02 Dl 20 19 Dl DO 18 17 DO TH 16 15 TIME HI TL 14 13 TIME LO MO 12 1 1 MONTH DAY 10 9 DAY SW2 8 7 DATA STR FAST SET 6 5 SLOW SET + 5V 4 3 + 5V +5V 2 1 F5V GNO BUS GND BUS XA7-I-68 + I2V BUS -I2V BUS JI-13 JI-29 Jl- | 2 Jl - 28 XA6-I-5I XA6-I-49 XA6-I-47 XA6-I-45 XA6-I-43 Jl- 15 GND BUS GND BUS -I2V BUS J I -46 J I -45 J I -44 XA6-I-63 Jl- I I XA6-I-37 Jl- 27 Jl- 10 XA5-I-3I, XA8-I-3I, XA9 XA5-I-29, XA8-I-29, XA9 XA5-I-27, XA8-I-27, XA9 XA5-I-25, XA8- 1-25, XA9 XA5 - 1 - 23, XA8 XA5-I-2I, XA8 XA5-I-I9, XA8 XA5-I-I7, XA8 XA6-I-I5 XA6-I-I3 XA6-I-H XA6- 1-9 XA6 - 1 - 7 JI-26 -I-5V BUS +5V BUS -23, XA9 -21, XA9 -19, XA9 -17, XA9 + 5V BUS + 5V BUS GND 72 71 GNO GND 70 69 GND -I2V 68 67 f 12V A 66 65 OUT 8 B 64 63 OUT 7 C 62 61 OUT 6 MOT OUT 60 59 OUT 5 58 57 OUT 4 56 55 OUT 3 54 53 OUT 2 52 51 OUT 1 50 49 EL 48 47 EH 46 45 AL 44 43 AH 42 41 SYST. TRIG 40 39 DATA READY 38 37 STATUS 36 35 34 33 32 31 FJ7 30 29 06 28 27 D5 26 25 D4 24 23 D3 22 21 D2 20 19 Bl 8 17 50 6 15 TH [4 13 TL 12 1 1 MO 10 9 DAY 8 7 CATS 6 5 + 5V 4 3 + 5V F5V 2 1 + 5V GND BUS GND BUS + I2VBUS El E3 E5 E7 E9 FN EI3 EI5 XA5-I-49, XA9 1-49 XA5-I-47, XA9 1-47 XA5-I-45, XA9 1-45 XA5-I-43, XA9 1-43 XA9-I-4I XA9-I-39 XA9-I-37 XA5-I-3I, XA7 1-31. XA9 XA5-I-29, XA7 1-29, XA9 XA5-I-27, XA7 1-27, XA9 XA5-I-25, XA7 125. XA9 XA5-I-23, XA7 1-23, XA9 XA5-I-2I, XA7 1- 21, XA9 XA5-I-I9, XA7 1-19, XA9 XA5-I-I7, XA7 1-17. XA9 XA7-I-I6 XA7-I-I4 XA7-I-I2 XA7-I-I0 XA9-I-7 + 5V BUS + 5V BUS FIGURE 10-30 FIND NO. ELEC REF DES NOMENCLATURE OR DESCRIPTION OTY REOD PART OR IDENTIFYING NO. DWG SIZE CODE IDENT SPECIFICATION OR MATERIAL LIST OF MATERIAL UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES ±5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS ± .02 ENGINEERING DIVISION SILVER SPRING. MD. 20910 U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE BACKPLANE ASSEMBLY Nl A2AI2 INTERCONNECT DIAGRAM n w PREPARED D.£oW«" KinW CHECKED /PP DESIGN APPROVED BY SIZE D DATE 12/17/84 DRAWING NO. R450-A2AI2-3 APPROVED BY ^*n *M&°^ SCALE SHEET 3 OF 5 | FILE XA9-2 NIA2A9) XAIO-I 1NIA2AIO) BUS BUS 3-46 3-49 5-33 5- 16 »-l5 2-43 2-45 2-47 2-50 1- 17 2-16 215 2- 14 213 2-12 2-1 I 2-10 2-9 2-8 '-40 5-39 >-38 >-37 5-36 10 -I :-34 -19 -2 1 -23 BUS BUS + 5V 72 71 + 5V + 5V 70 69 + 5V EL INH 68 67 l-GND AZ INH 66 65 1- GND SYS TRIG 64 63 1- GND 1 FAT BPM 62 61 1- GND RANGE COV 60 59 1- GND 58 57 AZ 100 c .6 55 EL .8 AZ 200 54 53 EL .4 AZ 8 52 51 EL 80 AZ 2 50 49 EL 40 AZ .2 48 47 EL. 2 a: . i 46 45 EL 1 AZ 40 44 43 EL 20 AZ 20 42 41 EL 200 AZ .8 40 39 EL 8 AZ .4 38 37 EL J AZ 10 36 35 EL 100 AZ 80 34 33 EL 10 AZ 1 32 31 EL 4 AZ 4 30 29 EL 2 C6 28 27 1 - GND C7 26 25 1- GND TEST LEVEL 24 23 l-GND C4 22 21 1 -GND C5 20 19 1 - GND TIME SAMPLE 18 17 1- GND DATA RDY 16 15 1- GND C2 14 13 1- GND C3 12 1 1 1 - GND CI 10 9 1 GND CO 8 7 1- GND 6 5 GND 4 3 GND GND 2 1 GND +5V BUS +5V BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS J3-3I J2-44 J2-46 J2-48 J2-49 J2-33 J2-32 J2-3I J2-30 J2-29 J2-28 J2-27 J2-26 J2-25, J3-9 GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GNO ISOL BUS GND ISOL BUS GND BUS GND BUS GND BUS GND BUS GND ISOL BUS +5V ISOL BUS + 12V BUS +I2V BUS +5V BUS + 5V BUS GND 72 71 GND GND 70 69 GND l-GND 68 67 1 CND 66 65 1 + 5V 64 63 1 +5V 62 61 + I2V 60 59 + I2V 58 57 -I2V 56 55 -12V 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 1 10 9 8 7 6 5 + 5V 4 3 + 5V + 5V 2 1 + 5V GND BUS GND BUS GND ISOL BUS +5V ISOL BUS -H2V BUS -I2V BUS +5V BUS -I-5V BUS UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES ANGLES ± .5' ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE 3 PLACE DECIMALS ± 005 2 PLACE DECIMALS ± .02 SILVER SPRING, MD. 20910 BACKPLANE ASSEMBLY NIA2AI2 INTERCONNET DIAGRAM ^OMMOS^. PREPARED &.£&!en KUl7/«4 A JIOAP IK f A% CHECKED ■3P DESIGN "«_ . ^^^^ ^^H :■ APPROVED BY m W $9 SIZE C DATE 12/17/84 DRAWING NO. R450-A2AI2-I APPROVED BY 'MENT Of *" SCALE SHEET 4 OF 5 |FILE XA9-I (NIA2A9) XA9-2 (NIA2A9) XAIO-I INIA2AIO) GND BUS GND BUS GND ISOL BUS +5V ISOL BUS + 5V BUS + 5V BUS GND 72 71 GND GND 70 69 GND 1 -GND 68 67 l-GND 66 65 + 5V 64 63 1 +5V 62 61 60 59 58 57 56 55 54 53 52 51 SYST TRIG 50 49 E" 7 . 48 47 EH 46 45 AL 44 43 AH 42 41 SYS TRIG 40 39 DATA READY 38 37 STATUS 36 35 34 33 32 31 D7 30 29 D6 28 27 05 26 25 D4 24 23 03 22 21 D2" 20 19 Dl 18 17 DO 16 15 14 13 12 1 1 10 9 8 7 DATA 6 5 + 5V 4 3 + 5V +5V 2 1 + 5V GND BUS GND BUS GND ISOL BUS +5 ISOL BUS Jl- 17 XA5-I-49, XA8-I-49 XA5-I-47, XA8-I-47 XA5-I-45, XA8-I-45 XA5-I-43, XA8-I-43 XA8-I-4I XA8-I-39 XA8-I-37 XA5-I-3I, XA7-I-3I, XA8-I-3I XA5-I-29, XA7-I-29, XA8-I-29 XA5-I-27, XA7-I-27, XA8-I-27 XA5-I-25, XA7-I-25, XA8-I-25 XA5-I-23, XA7-I-23, XA8-I-23 XA5-I-2I, XA7- 1-21, XA8-I-2I XA5-I-I9, XA7-I-I9, XA8-I-I9 XA5-I-I7, XA7-I-I7, XA8-I-I7 + 5V BUS +5V BUS + 5V BUS + 5V BUS J3-46 J3-49 J3-26-33 J3- 16 J3- U-15 J2-43 J2-45 J2-47 J2-50 J2- I 7 J2-I6 J2-I5 J2-I4 J2-I3 J2-I2 J2-I I J2-I0 J2-9 J2-8 J2-7-40 J2-6-39 J2-5-38 J2-4-37 J2-3-36 J2-2, J-3-40 J2-I, J3-I J2-42, J2-34 J3-35-I9 J3-37-2I J3-39-23 GND BUS GND BUS + 5V 72 71 + 5V + 5V 70 69 + 5V EL INH 68 67 l-GND AZ INH 66 65 1- GND SYS TRIG 64 63 1- GND 1 FAT BPM 62 61 1- GND RANGE COV 60 59 1- GND 58 57 AZ 100 56 55 EL .8 AZ 200 54 53 EL .4 AZ 8 52 51 EL 80 AZ 2 50 49 EL 40 AZ .2 48 47 EL. 2 AZ .1 46 45 EL 1 AZ 40 44 43 EL 20 AZ 20 42 41 EL 200 AZ .8 40 39 EL 8 AZ .4 38 37 EL.I AZ 10 36 35 EL 100 AZ 80 34 33 EL 10 AZ 1 32 31 EL 4 AZ 4 30 29 EL 2 C6 28 27 l-GND C7 26 25 l-GND TEST LEVEL 24 23 1- GND C4 22 21 1 -GND C5 20 19 1 -GND TIMESAMPLE 18 17 1- GND DATA RDY 16 15 1- GND C2 14 13 1- GND C3 12 II 1 - GND CI 10 9 1 GND CO 8 7 1- GND 6 5 GND 4 3 GND GND 2 1 GND + 5V BUS + 5V BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS J3-3I J2-44 J2-46 J2-48 J2-49 J2-33 J2-32 J2-3I J2-30 J2-29 J2-28 J2-27 J2-26 J2-25, J3-9 GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND ISOL BUS GND BUS GND BUS GND BUS GND BUS GND ISOL BUS +5V ISOL BUS + I2V BUS + I2V BUS + 5V BUS + 5V BUS GND 72 71 GND GND 70 69 GND l-GND 68 67 l-GND 66 65 1 +5V 64 63 1 +5V 62 61 + I2V 60 59 + I2V 58 57 -I2V 56 55 -I2V 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 10 9 8 7 6 5 + 5V 4 3 + 5V + 5V 2 1 + 5V GND BUS GND BUS GND ISOL BUS +5V ISOL BUS +I2V BUS -I2VBUS + 5V BUS +5V BUS FIGURE 10-30 UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE IN INCHES TOLERANCES: ANGLES * .5* 3 PLACE DECIMALS ± .005 2 PLACE DECIMALS * .02 ENGINEERING DIVISION U.S. DEPARTMENT OF COMMERCE NATIONAL OCEANIC & ATMOSPHERIC ADMINISTRATION NATIONAL WEATHER SERVICE SILVER SPRING, MD. 20910 BACKPLANE ASSEMBLY NIA2AI2 INTERCONNET DIAGRAM iB IF PREPARED tedelen i^nlM CHECKED ^P DESIGN APPROVED BY SIZE C DATE 12/17/84 DRAWING NO. R450-A2AI2-I 1 ^* r