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LIBRARY OF THE 
 
 UNIVERSITY OF ILLINOIS 
 
 AT URBANA-CHAMPAIGN 
 
 wno.45i-45lo 
 cop. 7. 
 
JAN 2 7 
 
 L161 — O-1096 
 
Report No. 
 
 7^*^ 
 
 U55 
 
 7U 
 
 tf&S 
 
 COMPARISON OF THE IMPLICIT ENUMERATION METHOD 
 AND THE BRANCH-AND -BOUND METHOD 
 FOR LOGICAL DESIGN 
 
 by 
 
 Tomoyasu Nakagawa. 
 Saburo Muroga 
 
 June 1971 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/comparisonofimpl455naka 
 
Report No. 1+5 5 
 
 COMPARISON OF THE IMPLICIT ENUMERATION METHOD 
 
 AND THE BRANCH- AND- BOUND METHOD 
 
 FOR LOGICAL DESIGN* 
 
 Tomoyasu NAKAGAWA 
 Saburo MUROGA 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 618OI 
 
 This work was supported in part by the National Science Foundation under 
 Grant No. NSF GJ-503. 
 
INTRODUCTION 
 
 1. Optimal network design using NOR gates by the implicit enumeration method. 
 
 1.1 Formulation of the problem with basic inequalities. 
 
 1.2 Algorithum of the implicit enumeration method. 
 
 1.3 Improvement of the computational efficiency. 
 1.3*1 Preclusion of non-optimal solutions. 
 
 1.3.2 The NOR-gate oriented scheme of fixing a free variable at IE-step 3- 
 
 2. Optimal network design using NOR gates by the branch-and-bound method. 
 
 2.1 Definitions. 
 
 2.2 Algorithm of the branch-and-bound method. 
 
 2.3.1 The concepts necessary for the SCUC and the IPPC. 
 
 2.3.2 Uncovered components of type 1-COV. 
 
 2.3.3 A scheme to cover type NWG components. 
 
 2.3.4 The SCUC and IPPC. 
 
 2.3.5 Modification of backtrack at BB-step h. 
 
 3. Comparison of the two methods. 
 
 3.1 The concept of isolated gates. 
 
 3.2 Generation of feasible networks. 
 
 3.3 Exhaustion of feasible networks. 
 
 3.4 Exclusion of unnecessary networks. 
 
 3.5 Programming and computation time. 
 
 h. Comparison of the two methods for logical design with AND-OR gates. 
 
 k.l Formulation of the problem by the implicit enumeration method. 
 
 k.2 Formulation of the problem by the branch-and-bound method. 
 
 4.3 Programming and computation time. 
 
INTRODUCTION 
 
 The synthesis problem of optimal logic design is studied as an integer 
 programming problem by Muroga et al. , [18,19]. The integer programming 
 formulation with inequalities is a unified formulation for design problems 
 involving different types of gates. By assigning appropriate values to the 
 coefficients of the inequalities, and/or changing the inequalities slightly, 
 we have the optimization problem with a particular gate type or with a 
 mixture of particular gate types. So far, the optimal NOR networks, the 
 optimal NOR- AND networks, the optimal NOR-OR networks, and the optimal 
 NOR-NAND networks, for all representative functions of three or less vari- 
 ables are obtained [2,4,13,17]* a s well as the optimal NOR networks of 
 many functions of four variables [5]. 
 
 On the other hand, the branch-and-bound algorithm is applied by 
 Davidson to the synthesis problem of NAND networks [6]. By this algorithm, 
 the optimal NAND networks for some single and multiple output function 
 problems are obtained. 
 
 In spite of their different approaches to the optimal logic design, 
 the implicit enumeration method (inequalities are used) and the branch- 
 and-bound method (no inequalities are used) share several common pro- 
 perties. This report discusses the similarity and differences of the 
 algorithmic structure of these two methods. 
 
 In the first two chapters, we describe the two methods as applied to 
 the synthesis problem of optimal NOR networks. (Although the branch-and- 
 bound method was applied to NAND networks, we present this method as 
 applied to NOR networks, for the purpose of comparison.) In chapter 3* 
 we compare the two methods, summarizing the similarities and differences. 
 
We also discuss the programming aspect and the computation speed of the two 
 methods in this chapter. 
 
 The branch- and-bound method can be applied to the problems of other 
 gate types or of a mixture of different gate types. For example, this 
 method is applied to optimal AND-OR networks [23]. In the last chapter, 
 we compare the implicit enumeration and branch -and -bound methods as 
 applied to AM)-OR networks. 
 
1. OPTIMUM NETWORK DESIGN USING NOR GATES BY INTEGER PROGRAMMING [2] 
 1.1 Formulation of the Problem With Basic Inequalities * 
 
 Given a switching function of n external variables,, the problem is to 
 obtain optimum loop-free networks of NOR gates, where an optimum network is 
 defined as a network which has the least number of connections and inter- 
 connections among those having the least number of gates. 
 
 Let us express external variables x. and the given function f with 
 the corresponding column vectors of the truth table as follows: 
 
 2 n -l 
 external variable x «= (x «,..., x « ), for I = 1, . .., n, and 
 
 ^-1 
 the given switching function f(x) = (f t . . . , f ). 
 
 Corresponding to the above representation for the x 's and f(x), 
 
 n ^ 
 we represent the output of gate i by: (P., . .., P. " ), where P., j = 0, 
 
 . . . , 2 -1, are variables which assume the values or 1. 
 
 Let us introduce 0-1 variables a. and w. which denote the following: 
 
 a., : gate i is connected to gate k if a., = 1, and is not if a., = 0. 
 lk to lk ' lk 
 
 w • x. is connected to gate k if v. = 1, and is not if w = 0. 
 
 The output of NOR gate k is 0, if at least one input is 1, or the 
 
 output of gate k is 1, if all inputs are 0. Therefore, we have the following 
 
 two sets of inequalities with respect to gate k. 
 
 * The following basic inequalities for the NOR network can be obtained 
 directly as a special case of the general expression based on the 
 threshold gate, if we choose the coefficients in the general ex- 
 pression appropriately. For details, see[i8]. 
 
Z w* x] + Z a F? > l-u pj (#-1) 
 
 t I I 1+k ik i - k 
 
 Z w* x J " + Z a.. P"? < 0+ U(l-P«j) (#-2) 
 ^ I I .^ ik i- k 
 
 for j =0, ..., 2 n -l, 
 
 ■where U is a sufficiently large positive number. These inequalities will 
 be called th e gate inequalities . 
 
 Assume the network under consideration consists of R gates, where gate 
 1 is the output gate of the network. For gate 1, the following inequalities 
 hold. 
 
 ' n i i R d J 
 
 (Gate 1) Z w, x 3 g + Z a P^ > 1, if f J = 
 i=l l l i=2 1X x 
 
 n , . R , i 
 
 z w: x J + z a p? < o, if f =1 
 
 &=1 ^ ^ i=2 lX X 
 
 n 
 
 for j =o, . . . , 2 -1. 
 
 And for gate k, k=2, ..., R, the gate inequalities (#-l) and (#-2) hold. 
 
 Notice that the above inequalities contain the non- linear terms 
 a.,P?. By linearizing them with new variables p. J = a P , the above 
 
 xk k l-K- l-K K 
 
 inequalities become the following: 
 
(Gate 1) 
 
 n 1 . R . , 
 
 z w, A + z b :J >i, if r = o 
 
 i=l ^ X i=2 
 
 n 1 . R . 
 
 Z wT x J , + Z p.ij < 0, if f J = 1, 
 1=1 l l 1=2 1J " 
 
 (1.1) 
 
 n 
 
 for j=0, . .., 2-1, 
 
 (Gate k, for k=2, . . . , R) 
 
 iik 
 
 n . . R 
 
 Z w, x J , + Z p J < 0+ U (l-F?) 
 
 i=1 1 1 i=1 ik- k 
 
 ^ 
 
 (1.2) 
 
 for j=0, 
 
 2 n-l 
 
 where the new variables 8., are related to P. and a., through the following 
 
 lk 11k 
 
 linear inequalities: 
 
 J., 1 > P^ + a.. - 1 
 
 lk — 1 lk 
 
 26.? < P? + a., 
 ik — 1 1k 
 
 (1.3) 
 
 The inequalities (l.l) ~ (1.3) represent the input-output relation of 
 gates in the network of R gates. 
 
Now, recall that the network must be loop- free. This is expressed 
 by the following set of inequalities which prohibit the interconnection 
 from forming a loop. 
 
 Breaking loops containing 
 two gates: 
 
 Breaking loops containing 
 three gates: 
 
 Breaking loops containing 
 R eates: 
 
 a. . + a 
 
 :. . < 1, for i, I 
 Vl " 1 
 
 a. . + a . + a. . . _ 
 V 2 ^3 Vl - 2 > 
 
 which are 
 different from each other. 
 
 for i l' V V 
 
 a. . + a. . + . . . + a. . < R-l 
 1 1 1 2 1 2 1 3 ^1 
 
 for i , . . . , i , which are 
 J. R 
 
 different from each other. 
 
 ) (i.h) 
 
 The sets of linear inequalities (l.l) through (1.4) are the mathe- 
 matical expression of a NOR network of R gates to realize the given 
 switching function f (x). Let us call them the basic inequalities . 
 
 Our objective is to find the networks which have the least number of 
 connections and interconnections among those having the least number of 
 gates. Let us define the objective function z as the sum of the connections 
 and interconnections in a network of R gates: 
 
 z = 
 
 R 
 
 Z 
 
 k=l 
 
 n 
 
 Z 
 
 k 
 
 £=1 l i=l 
 
 R 
 Z 
 
 a 
 
 ik 
 
 i+k 
 
The following is the Design Procedure . 
 The Design Procedure 
 
 (1) Set R=l. Go to (2). 
 
 (2) Solve the following integer programming problem with the R-gate 
 formulation: 
 
 Minimize the R n , R 
 
 objective function: z = Z ( Z w.+Z a -T, ^ 
 
 k=l i=l & i=l xK 
 ik 
 
 Subject to the basic inequalities (l.l) through (l.h). 
 (3) If the problem has optimum solutions, then go to (h); 
 
 If the problem is infeasible, then increase R by 1 and go to (2). 
 (k) The networks of these optimum solutions are the optimum networks 
 of our problem. 
 1.2 Algorithm pf The Implicit Enumeration Method 
 
 In the Design Procedure presented in Section 1.1, we need an algorithm 
 for solving the integer programming problems. In this section, let us 
 discuss an algorithm known as the implicit enumeration method for zero-one 
 integer programming problems [5]. 
 
 A zero-one integer programming problem is written as follows: 
 
 N 
 
 minimize z = Z c.y., where c. >0 for j=l, ..., N (1-5) 
 
 • _1 J J J 
 
 N 
 subject to Z a. .y . + b. > 0, for i = 1, . . . , M (1.6) 
 
 j=l 1J J J ~ 
 
 and y.=0 or 1 for j=l, ..., N (1.7) 
 
 Let us define some concepts. There are 2 different ways of assigning 
 1 or to the set of {y , ..., y }. Each of these 2 assignments is called 
 
a solution . If a solution satisfies (1.6), then the solution is said to 
 be feasible ; otherwise, the solution is said to be infeasible . A feasible 
 
 solution which minimizes (1.5) is said to be optimal . The implicit enu- 
 
 N 
 meration method is a method which enumerates the 2 solutions implicitly 
 
 and obtains the optimal solutions, if any, in the following way. 
 
 Variables which are assigned or 1 are said to be fixed ; variables 
 
 which are not assigned are said to be free (and are denoted by *) . An 
 
 ordered assignment, S, of binary values to a subset of N variables is 
 
 called a partial solution . A solution which contains a partial solution 
 
 S is said to be a completion of this S. The best feasible solution (the 
 
 best feasible completion) found up until a certain time is called the 
 
 incumbent at that time. The value of the objective function, z, of the 
 
 incumbent is called the incumbent cost . During the computation, however, 
 
 the following situation may occur: Given an assignment y.=0 (or l), we 
 
 J 
 
 may find that we need not investigate the complementary assignment y.=l 
 
 J 
 
 (or 0) relative to the partial solution. Then we underline the assignment 
 y.=0 or y.=l as y.=0 (or y.=l) in order to indicate the skipping of 
 
 d J J J 
 
 the future investigation of the opposite assignment. Now, we are ready 
 to state the implicit enumeration method. 
 
 The Implicit Enumeration Method 
 
 IE-step (initialization): The method starts with the empty partial 
 solution S_= <f>. 
 
 Set z to a sufficiently large number. 
 IE-step 1 (Check inequalities): Scanning through the inequalities 
 
 (1.6) with the current partial solution, we examine whether 
 or not any free variables are forced to assume the value 
 
10 
 
 or 1 in order to satisfy the inequalities. If we find 
 such variables, then we fix these variables. Repeat the 
 above process until we cannot find any more free variables 
 which can be forced to assume the value or 1. Write down 
 all newly fixed variables on the right of the current 
 partial solution, forming an augmented partial solution. 
 We need not investigate the opposite assignments to these 
 variables. Thus, we underline them. 
 IE-step 2 (Check feasibility): For the current partial solution, one 
 of the following conditions holds: 
 
 1-1: All variables are fixed, and the value of the 
 objective function is less than or equal to z. 
 1-2: The value z of the objective function corre- 
 sponding to the partial solution, i. e., 
 
 z = I c.y. , is greater than z. 
 J J 
 
 (fixed variables) 
 
 1-3: There is at least one free variable y. such that 
 
 J 
 
 each of the two assignments, y.=0 or y.=l, violates 
 
 J J 
 
 some of the inequalities (1.6). 
 1-k: There are free variables and neither 1-2 nor 
 1-3 holds. 
 
 If 1-1 holds, then go to IE-step k; 
 
 If 1-2 or 1-3 holds, then go to IE-step 5; 
 
 If I-k holds, then go to IE-step3. 
 
 (Note that if we incorporate the inequality 
 N 
 
 Z c. x. z, into the set of the problem 
 =1 3 3 
 
 inequalities (1.6), we can check the condition 1-2 
 as a part of 1-3. ) 
 
11 
 
 IE-step 3 (Fix a free variable): Select a free variable y. and fix 
 
 J 
 
 it to (or l). Write down the new assignment y. = 
 
 J 
 
 (or y. = l) on the right of the partial solution, forming an 
 
 j 
 
 augmented partial solution. In order to indicate that we 
 must investigate the opposite assignment in the future, we 
 do not underline the current assignment. Go to IE- step 1. 
 
 IE-step k (Feasible solution): This is a feasible solution. Print the 
 solution. Replace the incumbent cost z by the value of the 
 objective function of this solution. 
 
 IE-step 5 (Backtrack): From the current partial solution S, generate 
 a partial solution which has not yet been investigated, by 
 the following procedure. 
 
 (i) Examine whether or not the current partial solution 
 has non-underlined variables. If the current partial 
 solution has non- underlined variables, then go to (ii) 
 below; otherwise go to IE-step 6. 
 
 (ii) Select the non-underlined variable y.* that has been 
 introduced most recently. That is, the non- under- 
 lined variable which occupies the right most 
 position among all non- underlined variables in S. 
 Remove from the partial solution all variables which 
 were introduced after y.*. (That is, all variables 
 
 which are located on the right of y.* in S. ) Change 
 
 J 
 
 the value of the y.* to its complementary value. 
 
 J 
 
 (That is, if the previous assignment was y.* = 
 
 o 
 
12 
 
 (or l), then the new assignment is y.*=l 
 (or 0).) Since we have implicitly explored 
 the completions of the previous assignment, 
 we underline the new assignment. Go to 
 IP-step 1. 
 IE-step 6 (Termination): The present partial solution has no non- 
 underlined variables; this means we have investigated im- 
 plicitly all partial solutions, hence all completions. 
 The algorithm terminates. 
 From the computational view point, the efficiency of the algorithm 
 depens on: 
 
 (i) The procedure of checking inequalities at IE- step 1, 
 (ii) The choice of inequalities, and 
 
 (iii) The heuristics of choosing a free variable to fix at 
 IE-step 3- 
 
 On the first point, Muroga et al. introduced a set of programming 
 gimmicks to perform IE-step 1 quickly, a part of which is independently 
 known in the literature [1, 'J, 15, 28, 29] . 
 
 On the second point, they introduced additional inequalities to 
 preclude some non-optimal solutions. 
 
 On the third point, they applied Davidson's idea of desirability 
 order and related gimmicks, tailoring those to logical design with NOR 
 gates by integer programming. 
 1.3 Improvement of the Computational Efficiency 
 
 The optimum NOR network for a given function f (x) can be obtained 
 by applying the implicit enumeration algorithm in the Design Procedure. 
 
13 
 
 However, a straightforward application of the implicit enumeration 
 algorithm to the basic inequalities is not necessarily feasible com- 
 putationally. In the following two sections, we explain the second and 
 third gimmicks. 
 
 1. 3.1 Preclusion of Non - Optimal Solutions By Additional Inequalities , 
 Due to the properties of NOR gates, partial solutions which contain 
 the following configurations are redundant: 
 
 Redundant Configurations 
 
 (l) (Triangular configuration l) A triangular configuration among 
 three gates i, j, and k as shown in Fig. 1.2. 
 
 gate i 
 
 "N no other outputs 
 gate j f^. 1.2 
 
 In this configuration, one of the three interconnections a.. , Of. . and 
 
 a., is redundant. 
 
 (2) (Triangular configuration 2) A triangular configuration among 
 external variable x» and gates j, k as shown in Fig. 1.3* 
 
 j no other outputs 
 
 gate j 
 
 Fig. 1.3 
 
 i k 
 In this configuration one of the two connections w *, w g , or the 
 
 interconnection Q5„ is redundant. 
 Jk 
 
Ik 
 
 (3) (A gate which connects to gate l): If gate k is connected to 
 gate 1 (the gate whose output is the given switching function) , 
 then all interconnections of gate k to other gates are redundant, 
 
 gate k gate 1 
 
 UD O 
 
 *-*\ gate t- gate t_ > 
 v ± d y 
 
 Fie. 1.^ 
 
 In this configuration, either the connection ol = 1 or all 
 OL = 1, t = t_ f t p , . .., are redundant. 
 
 (k) (A gate which has a single input where the input is an output 
 from another gate): If gate k (except gate l) has a single in- 
 put where the input is an output from another gate, then gate k 
 is redundant, assuming no fan- in constraint is imposed. In an 
 optimal network, gate k must have at least either one input w, 
 or two inputs. 
 
 7 5 
 
 
 ->. 
 
 'gate i gate k gate m ? -*/« gate m 
 
 (a) (b) 
 
 Fig. 1.5 
 
 In Fig. 1.5 (a), gate k and the preceding gate i are redundant, 
 because Fig. 1.5 (a) can be reduced to Fig. 1.5 (b). 
 
 In order to preclude partial solutions which contain the above con- 
 figurations, we provide the following additional inequalities which pro- 
 hibit such configurations. 
 
The inequality 
 
 a. . + a.. + a.. < 2 + u z a.. 
 iJ ik jk - t k jt 
 
 15 
 
 (1.8) 
 
 prohibits the configuration shown in Fig. 1.2. 
 
 The inequality 
 
 prohibits the configuration shown in Fig. 1.3* 
 
 The inequality 
 
 The inequality 
 
 4 *" - u ^ 
 
 t+1 
 
 (1.10) 
 
 prohibits the configuration shown in Fig. l.k. 
 
 2 Z, nH + Z, a, . > 2 
 i l t*k tk " 
 
 (1.11) 
 
 prohibits the configuration shown in Fig. 1.5. 
 In addition to the inequalities (1.8) ~ (l.ll), we introduce two more 
 restrictions: 
 
 (5) each gate except gate 1 has at least one output interconnection, 
 and 
 
 (6) each external variable must be connected to at least one gate, 
 these two restrictions are represented by: 
 
 The inequality 
 
 and 
 
 The inequality 
 
 1 ^ z °Vb 
 t*k Ktl 
 
 (1.12) 
 
 1 < Z w, 
 
 (1.13) 
 
 respectively. 
 
16 
 
 By adding the additional inequalities (1.8) ~ (1.13 ) to the basic 
 inequalities, we modify our entire integer programming problem as: 
 
 R n R 
 minimize z = Z { Z w« + Z a } 
 
 k=l i=l Z i=l 1K 
 
 i#k 
 
 subject to the basic inequalities (l.l) ~ (l.^-), and 
 the additional inequalities (1.8) ~ (1.13). 
 
 This modified integer programming problem contains more inequalities 
 than the one presented in (2) of the Design Procedure, yet can be solved 
 in less computation time. 
 
 1.3.2 The NOR - gate Oriented Scheme of Fixing a Free Variable at IE - step 3. 
 
 At IE-step 3, we choose a free variable to fix. In this section, we 
 explain the detailed scheme of IE-step 3 which is tailored to the logical 
 design problem with NOR gates. The scheme consists of four phases: selec- 
 ting a free variable, fixing a selected free variable, calculating the lower 
 bound of the objective function, and exiting from the procedure. 
 
 Phase I: selecting a free variable 
 
 Recall the gate inequalities (#-l) and (#-2). Let us take an inequality 
 
 n . R . 
 
 Z w- x] + Z p.? > 1-U P J 
 £=1 II . =1 ik - k 
 
 i#k 
 
 from (#-l), where P!r is already fixed to 0, and each of the variables (note 
 
 that the x^ are not variables) in the left hand side are either or free, 
 
 but not 1. The physical meaning of such a P is that either gate k has no 
 
17 
 
 input connection yet, or gate k has only those inputs such that their j-th 
 components are or unas signed. We call such a P£ an output component 
 which is not yet covered, or an uncovered component. Suppose we assign 1 
 to one of the free variables of this inequality. The inequality becomes 
 satisfied regardless of what the values of other free variables in the 
 lefthand side will be. The physical meaning of this procedure is: 
 
 to supply gate k with an input (from an external variable or 
 
 from another gate) whose j-th component is 1. 
 
 k 
 covered. 
 
 A P =0 whose corresponding inequality {#-!.) is satisfied is said to be 
 
 Our selection strategy of a free variable is to cover at least one 
 
 i k i 
 
 uncovered component Pr,, by fixing a selected free variable w* or p.r. 
 
 to the value 1. Notice that we need not consider explicitly the in- 
 equalities (#-2), i.e., 
 
 l ± w i 4 + .| hi < ° + u <«£> > 
 
 i#k 
 
 because IE-step 1 of the algorithm checks these inequalities, and assigns 
 to all of the free variables w, for such £'s that x^=l, and B.jl if P^.=l. 
 
 Let us define some concepts. 
 
 An isolated gate is a gate which has no output interconnections. 
 
 i k 
 
 Associated with an output component P r.=0, the types of variables w „ and 
 
 B., are defined as follows: 
 lk 
 
18 
 
 Types Variables Which Are Assigned Types 
 
 i k 
 
 COV: p which is already fixed to 1, or w, which is 
 
 2.K. So 
 
 already fixed to 1, where x~,=l. 
 
 (COV denotes a variable which COVers P?=0.) 
 v k 
 
 G*: B J which is * (i.e., free), where a.,=l and pl=*. 
 
 IK IK. 1 
 
 (G* denotes a Gate i with P^= *. 
 
 k 
 Variable with x =1 and Connection being *. ) 
 
 k i 
 
 VC*: w, which is *, where x^=l. (VC* denotes an external 
 
 GC*: 8.? which is *, where a , =*, P?=l, and gate i is 
 
 ik ik i 
 
 not isolated. (GC* denotes Gate i with P.=l and 
 
 — i 
 
 Connection being *. ) 
 
 G*C*: 8.? which is * where a =*. P?=*. and gate i is 
 ik ik i 
 
 not isolated. (G*C* denotes Gate i with P^=r* and 
 
 — l — 
 
 Connection being *. ) 
 
 NWG: 8-? which is *, where a., =*, P?=*. and gate i is 
 
 ik ' ik ' i ' to 
 
 isolated. (NWG stands for NeW Gate. ) 
 
 Note that every variable appearing in the above definition is assigned 
 one and only one type. 
 
19 
 
 Since an output component Pt_ may be associated with variables of 
 different types, let us order these types by the desirability : 
 
 COV, G*, VC*, GC*, G*G*, and NWG, 
 Where COV is the most desirable, 
 And NWG is the least desirable. 
 
 With the use of the desirability order, the types of output components 
 Pr.=0, the types of gates, and the type of the partial network are defined 
 as follows: 
 
 The Type of P = is defined as the most desirable type of variable 
 
 i£ 
 
 k i 
 among all variables w* and p.;. which are assigned types with respect 
 
 to P? = 0. 
 
 The Type of gate k is defined as: 
 
 ISL: If gate k is isolated. (ISL is a mnemonic abbreviation 
 
 of isolated gate k. ) 
 
 LTG: If gate k is not of ISL type, has no input connections/ 
 
 interconnections, and P^=0 or * for all j. (LaTently 
 useful Gate in the sense that a covering of 0-components 
 is postponed until the gate k has at least one 
 1- component. ) 
 
 If gate k satisfies neither of the above conditions, then the type of 
 
20 
 
 gate k is defined as the least desirable type of output component 
 among all output components Pr. = of gate k. 
 
 Let The Desirability of Types of Gates be defined by: 
 
 ISL, COV, LTG, G*, VC*, GC*, G*C*, NWG, 
 Where ISL is the most desirable, 
 And NWG is the least desirable. 
 
 The Type of the Partial Network is defined as the least desirable type of 
 gate among all the gates of the network. 
 
 Now we are ready to explain the rule of selecting a free variable. 
 Notice that with the Design Procedure given in section 1.1, a network 
 realizes the given switching function only when the type of the network 
 is COV. Therefore, we skip to Phase IV below if the type of the current 
 network is COV. Otherwise, we select a free variable according to the 
 following rule, called the Selection Rule . 
 
 The Selection Rule: 
 
 (i) Choose a gate which defines the type of the partial network. If 
 there are two or more such gates, choose the one which has the 
 smallest gate label k. ) 
 
 (ii) Choose an output component which defines the type of the gate 
 
 d 
 chosen in (i). Let P. denote this component. If there are 
 
 two or more such components, and the type is VC*, then choose 
 
 a free variable w, which covers the most uncovered components 
 
21 
 
 of type VC*. If there are two or more such components, and the 
 
 Jo 
 
 type is other than VC*, first choose P with the smallest jO. 
 
 J o 
 
 Then, choose a free variable 8 which defines the type of the 
 P, . If there are two or more such free variables, then choose 
 the one which has the smallest gate label i. 
 
 Phase II: Fixing The Selected Free Variable 
 
 In this phase, we fix the free variable selected in phase I. If the 
 
 selected free variable is |3. whose type is one of G*, GC*, or G*C*, 
 
 k 
 
 then we fix it as 8.. =1. If the selected free variable is w„ (that is, 
 
 lk si ' 
 
 the type of the free variable is VC*), we fix it as w, = 1. 
 
 i 
 If the selected free variable is 6 whose type is NWG, we fix it as 
 
 ^ lie 
 
 J o 
 
 8 = 1. However, notice the following in the case of type NWG. Suppose 
 lk j 
 
 J 
 that 8 is selected among two or more isolated gates i, p, q, . . . 
 
 i 
 
 Since covering the same P with different isolated gates i, p, q, ... , 
 
 results in augmented partial solutions which are equivalent to each other 
 
 (by permuting gate labels), it is sufficient to cover the P. with only 
 
 one of the isolated gates, say, gate i. Therefore, we underline the 
 
 D 'o 
 
 assignment B. n =1. 
 lk 
 
 Phase III : Calculation of the Lower Bound of the Objective Function 
 
 In the third phase, we calculate the lower bound of the objective 
 function by using the following properties of the problem. (We assume 
 that no fan- in or fan-out limit is imposed. ) 
 
 Properties 
 
 1. A feasible solution is realized with exactly R gates. In other 
 
22 
 
 words, every gate has at least one input connection, and every 
 gate, except gate 1, has at least one output connection. 
 
 2. According to the inequality (l.ll), each gate has either ( 2a. ) 
 at least one input connection from an external variable or 
 ( 2b. ) at least two input interconnections from other gates. 
 
 3- The number of gates, each of which is solely devoted to ex- 
 pressing x., that is, the number of gates each of which has 
 a single input from an external variable and no inputs from 
 other gates, is at most n , where n is the number of ex- 
 ternal variables of the given switching function. 
 
 k. If the type of gate is one of GC*, G*C*, and NWG, then the 
 
 gate requires at least one more interconnection from another 
 gate. 
 
 5. If the type of the gate is VC*, then the gate requires at least 
 one more connection from an external variable. 
 
 6. If the type of the gate which is chosen by the Selection Rule 
 is VC*, and the selected external variable does not cover all 
 O-components whose types are VC*, then the gate requires at 
 least one more external variable in addition to the one in 5- 
 
 Combining the above properties of the network, we count the number of 
 additional connections and interconnections by steps 1, 2 and 3 of the 
 following procedure. Finally we obtain the lower bound z at step k. 
 
 Step 1. Classify the gates according to their attributes, as follows: 
 (Not all gates are classified into the following classes, and 
 
23 
 
 some gates may be classified sinumtaneously into two classes 
 X and S, S and L, or T and L. 
 
 Class X: Gates which are required to have additional inputs from 
 external variables due to properties 5 and 6. Let C be 
 the total number of additional inputs to these gates. 
 
 Class C: Gates which are required to have additional inputs from 
 other gates due to k and 2b. Let C be the total number 
 of additional inputs to these gates. 
 
 Class T: Gates whose types are LTG or ISL, and which have no in- 
 puts yet. Whether these gates must have inputs from ex- 
 ternal variables or from the outputs of other gates, will 
 be determined based on the configuration of the entire 
 network. Let t be the number of these gates. 
 
 Class S: Gates which have no inputs from other gates, and are 
 
 required to have a single input from an external veri- 
 able; and gates whose types are COV, LTG or ISL, and 
 which have a single input from an external variable but 
 no inputs from other gates. Let s be the total number 
 of these gates. 
 
 Class L: Isolated gates. Let & be the number of these gates. 
 
 Step 2. Attempt to obtain the additional interconnections which 
 
 are required by the gates of Class C and Class T from the 
 isolated gates (one output connection per isolated gate), 
 
2k 
 
 in the following procedure. First, use the output connec- 
 tions of the isolated gates as the additional interconnec- 
 tions to the gates of Class C. Then, use the output con- 
 nections of excess isolated gates, if any, as the additional 
 interconnections to the gates of Class T, connecting two 
 isolated gates to each gate of Class T . This procedure is 
 completed by the following iterative steps. 
 
 (i) Set y = i-c 2 
 
 If y < 1, then stop. 
 
 (ii) If y > 2 and t > 1, then replace the values y, 
 c and t according to the formulas: 
 
 y *■ y 
 
 c 2 «- c 2 +2 
 t «- t - 1 
 
 (iii) Go to (ii) if the condition y > 2 and t > 1 holds. 
 Otherwise, stop. Let c ' and t' be the final values 
 of c Q and t by the above procedure. Let T' denote 
 the class of gates of Class T which do not have the 
 additional interconnections from two isolated gates 
 by the above procedure (the number of gates in class 
 T f is t')« 
 
 Step 3« Calculate the lower bound e of the number of connections and 
 interconnections which must be introduced into the current 
 partial solution. Clearly, the maximum number of gates each 
 
25 
 
 of which has an external variable as its only input is n. 
 Each of the excess gates with a single input x . must have 
 one more input. Let us examine this in the following three 
 cases. 
 
 (a) The case where s > n. 
 
 Each of (s-n) gates of class X must have one more input, 
 and each of the gates of class T f must have two inputs. 
 Let us count the number of excess output interconnec- 
 tions, v, from isolated gates, if any, after we connect 
 as many isolated gates as possible to the inputs of gates 
 of classes C and T, and to the inputs of (s-n) gates of 
 class X. The v is given by 
 
 v = max { 0, t - ( c ' + 2t' + s - n ) }. 
 
 Therefore, the lower bound e is given by 
 
 e = ( c +c ' ) + (s-n) + 2t' + v. 
 
 (b) The case where n-t' < s < n. Among t' gates, (n-s) 
 gates of class T' may have external variables as their 
 single inputs. And f t' - (n-s) } gates must have 
 two inputs. Therefore the lower bound e is given by 
 
 e = (c +c 2 ') + (n-s) + 2 (f + s - n). 
 
 (c) The case where s< n-t'. All gates of class T' have 
 external variables as their single inputs. Let us 
 count the number of excess output interconnections v 
 
26 
 
 from isolated gates, if any, after we connect as many 
 isolated gates as possible to the inputs of gates of 
 classes C and T. The v is calculated by 
 
 v = max { 0, I -c ' } . 
 
 Therefore the lower bound e is given by 
 
 e = (c + c * ) + t f + v. 
 
 Step k. By adding e to the value z of the objective function cor- 
 responding to the current partial solution, we obtain the 
 lower bound z of the objective function, as z = z + e. 
 
 Phase IV: The Exit From IE- step 3 
 
 If the type of the partial network is COV, then transfer to IE-step k 
 (Feasible Solution); If the z exceeds z, then transfer to IE-step 5 
 (Backtrack); Otherwise, transfer to IE-step 1 (Check Inequalities). 
 
27 
 
 2. OPTIMUM NETWORK DESIGN USING NOR GATES BY THE BRANCH- AND- BOUND METHOD [6]*. 
 
 2.1 Definitions 
 
 Given a switching function f(x) of n variables, the problem is to 
 obtain the optimal loop- free networks of NOR gates which realize this func- 
 tion. An optimal network is defined as a network which has the least cost, 
 
 where the cost, C, of the network is a weighted sum of the number of gates 
 and the number of connections and interconnections, i.e., C = AX ( number 
 of gates } + BX { number of connections and interconnections}, where A and 
 B are arbitrary non-negative constants. Let us assume A » B > which im- 
 plies the problem of minimizing the number of gates primarily, then mini- 
 mizing the number of connections and interconnections secondarily. 
 
 Let us express external variables and the given function in the same 
 
 ( ° 2 ' 
 
 2 n -l 
 way as before: external variable x, = (x,, . . . , x „ ), for 1=1., ..., n, 
 
 ~* 2 n -l 
 and the given switching function f(x) = (f , ..., f ). Let us denote 
 
 n 
 the output of a gate by: Output of gate i= (p., ..., p " ), where Y- 
 
 j=0, ..., 2 -1, are variables which assume values of or 1. (An un- 
 specified output component is denoted by *. ) 
 
 The Initial Solution is defined as a NOR gate which is assigned the given 
 switching function f(x), but which has no inputs initially; this gate is 
 labeled 'gate 1' . 
 
 As we mentioned in the Introduction, we explain Davidson's branch- 
 and-bound algorithm, replacing NAND gates by NOR gates. 
 
28 
 
 An Intermediate Solution S is defined as a NOR network which consists of 
 R gates (R > l) with external variables, and which satisfies the following. 
 
 Condition 1 The network has neither isolated gates nor loops; R gates 
 are labeled with consecutive integers 1 through R. 
 
 Condition 2-1 Gate 1 is assigned the given switching function f(x). 
 
 Condition 2-2 The output of each gate other than gate 1 is completely 
 or incompletely specified such that for every j, if at 
 least one of the j-th components in the immediately 
 preceding or succeeding gates, or in the connected external 
 variables is 1 (one), then the j-th component of the gate 
 is (zero). Notice that the initial solution is a special 
 case of the intermediate solution. An output component 
 Pr =0 of gate k is said to be covered , if gate k has an in- 
 put (external variable x, or gate i) whose j-th component 
 is 1. Otherwise, it is said to be uncovered . 
 
 A Feasible Solution is an intermediate solution in which all output com- 
 ponents of the value in all gates are covered. A feasible solution 
 realizes the given switching function. 
 
 The Cost Ceiling C (or incumbent cost) is the cost of the best feasible 
 solution found thus far. 
 
 *50_ 
 
 k 
 intermediate solution, external variable x ff or gate i is called a possible 
 
 "k 
 
 Associated with an uncovered component P^ =0 of gate k in the current 
 
 cover of Pr , if it satisfies one of the following conditions: 
 
29 
 
 I. External variable x. for which 
 
 x J '2l, and x°' = for all j such that p£ = 1 hold. 
 
 II. Gate i for which 
 
 either 
 
 1. Gate i is connected to gate k, and P . =* 
 
 or 
 
 2. Gate i is not yet connected to gate k, the connection 
 
 of gate i to gate k would not form loops, P . =1 or *, 
 
 and P^Oor * for all j such that E? =0 holds . 
 l k 
 
 III. A gate which does not exist in the current intermediate solution. 
 
 All components in this gate are unspecified. This 
 gate is called a new gate , and labeled R+l when the 
 number of gates in the current intermediate solution 
 is R. 
 
 An uncovered component P r. of gate k can be covered with its possible cover 
 by the following procedure, called the implementation of a possible cover 
 forP . (i) if the possible cover is not yet connected to gate k, then 
 connect it to gate k. (2) If the possible cover is gate i for which 
 P. =*, then set P . =1. (3) Assign the value to unassigned components 
 whenever such an assignment is necessary to make the resulting network an 
 intermediate solution. The resulting intermediate solution is called the 
 augmented intermediate solution of the intermediate solution S. Note that 
 the word 'augmentation' does not always mean the addition of a connection/ 
 interconnection or the addition of a gate with an interconnection, but 
 
30 
 
 may only mean the change of an unassigned component to 1. By applying the 
 above procedure to uncovered components of intermediate solutions, we may 
 eventually obtain a feasible solution. 
 
 In order to enumerate feasible solutions systematically, we introduce 
 two rules, namely, the selection criterion of uncovered components (CCUC) 
 and the implementation priority of possible covers (IPPC) as defined below: 
 
 The selection criterion of uncovered components (SCUC) is the criterion 
 under which an uncovered component is selected from the current intermediate 
 solution. 
 
 The implementation priority of possible covers is the priority under 
 which the order of implementation of possible covers for the selected 
 uncovered component is determined. 
 
 2.2 Algorithm of the Branch- And- Bound Method 
 
 By using the concepts defined in section 2.1, the algorithm is de- 
 acribed as follows. 
 
 The Branch- And- Bound Algorithm 
 
 BB-Step (Initialization): Start with the initial partial solution S . 
 Set the cost ceiling c to a sufficiently large number. 
 Set K=l. 
 
 BB-Step 1 (Check Feasibility): For the current intermediate solution S„, 
 
 IV 
 
 one of the following three conditions holds: 
 
 B-l (Feasible): The cost of S v does not exceed C, and there 
 
 K 
 
 are no uncovered components in S. 
 
 B-2 (Cost Too Large): The cost of S exceeds C. 
 
 K 
 
31 
 
 B-3 (Continue): The cost of S does not exceed C, and there 
 are uncovered components in S . 
 
 A. 
 
 If B-l holds, then go to BB-Step 3; 
 
 If B-2 holds, then go to BB-Step k; 
 If B-3 holds, then go to BB-Step 2. 
 
 BB-Step 2 (implement the First Possible Cover): Select an uncovered com- 
 ponent according to the SCUC. 
 Let P be the selected component. 
 List all possible covers of P. 
 
 Store the P and the possible covers in a working space. Give 
 the label K to this portion of the working space. We call 
 the working space the possible cover list (PC-list), and we 
 
 refer to the P and the list of its possible covers as the 
 
 /\ 
 
 K-th P and K-th block of the PC-list, respectively. 
 
 Take a possible cover from the K-th PC-block, according 
 to the IPPC. 
 Increase K by 1. 
 
 Implement the possible cover taken above, generating the 
 augmented intermediate solution, S^. 
 Go to BB-Step 1. 
 BB-Step 3 (Feasible Solution): S^ is a feasible solution. Print the solution. 
 Replace the incumbent cost C by the value of the objective 
 function of this solution. 
 
 BB-Step k (Backtrack): Generate an intermediate solution which is not yet 
 investigated, by the following procedure. 
 
32 
 
 Take the PC-block of the largest label K among those 
 
 which contain unimplemented possible covers. If there 
 
 is no such PC-block, then go to BB-Step 5. 
 
 Otherwise set K=K_ . 
 
 Reconstruct the intermediate solution S . 
 
 Take one of the unimplemented possible covers from the 
 
 K-th block, according to the IPPC. 
 
 Increase K by 1. 
 
 Implement the possible cover taken above, generating the 
 
 augmented intermediate solution, S . 
 
 K 
 
 Go to BB-Step 1. 
 
 BB-Step 5 (Termination): All intermediate solutions are enumerated. 
 
 Stop. 
 
 As is easily seen, the efficiency of the algorithm entirely depends on 
 
 the order of generating intermediate solutions, namely the SCUC and the 
 IPPC. In the next section, we explain the details of the SCUC and IPPC 
 along with the related gimmicks employed in the best version among those 
 which Davidson programmed. 
 
 2. 3 Details of the Algorithm 
 
 In order to state the gimmicks of Davidson's program, we start with 
 more definitions of concepts based on the properties of the NOR network. 
 
 2.3.1 The concepts necessary for the SCUC and the IPPC 
 
 A component which is already covered is called type COV (COV 
 stands for a component which is already COV ered). Associated 
 with an uncovered component Pr =0 in gate k, a possible cover 
 is assigned one and only one type in the following. (Refer 
 to the definition of possible covers, in section 2.1) 
 
33 
 
 Type 
 
 + 
 
 Possible Cover 
 
 G*: 
 
 Gate i which satisfies the condition 
 
 II-l. (G* denotes a Gate i with 
 
 P<?°=* .) 
 1 — 
 
 VC*: 
 
 External variable x „ which satisfies 
 
 the condition I. (VC* denotes an 
 external Variable and Connection being 
 
 * •) 
 
 Gate i which satisfies the condition II-2 is assigned one of the following 
 four types: 
 
 GC*0: 
 
 GC*0*: 
 
 If F? =1. and P? =C for all j such 
 
 that P?=l. (GC*0 denotes Gate i with 
 
 F; =1, Connection being *, and F:=0 , 
 for all j such that F? =1. ) 
 
 If F: =1, and there is at least one 
 
 n such that P? = * for P? = 1. 
 i k 
 
 iO 
 
 (GC*0* denotes Gate i with F? =1, 
 — l 
 
 Connection being *, and P;=0 or * 
 
 for all f\ such that Pr=l. ) 
 
 k 
 
 + The types G*, VC*, GC*0, GC*0*, G*C*0*. G*C*0* and NWG are the re- 
 named types of EXP, VAR, FCN, MCF, EXF, EXMCF and W in Davidson's 
 definitions respectively. 
 
3^ 
 
 Types Cont'd 
 G*C*0: 
 
 G*C*0*: 
 
 NWG: 
 
 Possible Cover Cont'd 
 
 If F?°=* and F?=0 for all j such that 
 1 ' 1 u 
 
 P?=l. (G*C*0 denotes Gate i with 
 k — 
 
 Pr = * , Connection being *, and Pt^O_ 
 for all j such that F?=l. ) 
 
 iO 
 
 If Pr =* j and there is at least 
 
 one 
 
 j such that F?=* for P?=l. (G*C*0* 
 denotes Gate i with Ft =* , Connec- 
 tion being * , and Pr=0 or * for all 
 
 i — 
 
 j such that pj=l. ) 
 
 A new gate (of the condition III) is 
 assigned a type NWG. (NWG stands for 
 a NeW Gate. ) 
 
 The Desirability Order of Types is Defined By: 
 
 COV-G* - VC* - GC*0 - GC*0* - G*C*0 - G*C*0* - NWG, where COV is the 
 most desirable, and NWG is the least desirable. 
 
 The Type of an Uncovered Component is Defined By: 
 
 The most desirable type among its possible covers. (When an output 
 component has possible covers of type G*, this component will be reas- 
 signed either type 1-COV or type G*, by the use of an additional concept. 
 See 2.3.2 below. ) 
 
 The Type of Gate k is Defined By: 
 
35 
 
 The least desirable type among all components Pr = of gate k. 
 
 2.3.2 Uncovered Components of Type 1-COV 
 
 Suppose we have a type G* component Pr in gate k such that Pr 
 satisfies the following condition: 
 
 For at least one type G* possible cover gate i, the 
 jO-th components of all immediately preceding gates 
 of gate i are already assigned the value 
 (Fig. 2.1). 
 
 gate i Q ( * ) 
 
 Fig. 2.1 F^ of type G* has a type G* possible 
 
 cover gate i where the jO-th com- 
 ponents of all preceding gates m , 
 nip, . . . , are 0. ■*■ 
 
 If we cover Pjj. with such a gate i, no uncovered components are newly 
 introduced in the augmented intermediate solution. Therefore, such a 
 E£ of type G* is more desirable than other uncovered components of 
 
36 
 
 type G* which do not satisfy the above condition. As seen easily, if the 
 uncovered components of the current intermediate solution are all of type 
 G* and satisfy the above condition, we can obtain a feasible solution from 
 the current intermediate solution simply by changing appropriate unassigned 
 output components to the value 1. Due to the above observation on uncov- 
 ered components of type G*, we classify the original type G* into two types, 
 type 1-COV, and type G* of revised definition, as follows. 
 
 Type 1-COV 
 
 An uncovered component Pr is said to be type 1-COV , if 
 
 (1) Pr has at least one type G* possible cover gate i such 
 that the jO-th components of all preceding gates m , m , 
 
 . . . , of the gate i are already assigned the value 0, and 
 
 (2) If the above gate i is not of type COV or of the original 
 type G*, then the jO-th component of any external vari- 
 able that is able to cover uncovered components of the 
 gate i is 0. 
 
 Type G* of Revised Definition 
 
 An uncovered component P~ is said to be type G*~ of revised definition , 
 if it has possible covers of type G*, and it is not of type 1-COV. 
 
 + This condition assures that an uncovered component of type 1-COV will 
 not change its type to less desirable ones as long as the intermediate 
 solution has only uncovered components of types G* or VC*. This prop- 
 erty reduces the work of determining type 1-COV components « 
 
37 
 
 In accordance with the further classification of type G*, we modify the 
 conditions B-l and B-3 of BB-Step 1 as follows. This modification improves 
 the algorithm by reducing unnecessary covering steps. 
 
 B-l (Feasible Solution): The cost of the intermediate solution S 
 
 K 
 
 does not exceed G. And S has no uncovered components or 
 only uncovered components of type 1-COV. 
 
 B-2 (Cost Too Large): The cost of the S^ exceeds C. 
 
 IV 
 
 B-3 (Continue): The cost of S T _. does not exceed C and there is at least 
 one uncovered component whose type is not 1-COV. 
 
 2.3.3 A Scheme of Covering Type NWG Components 
 
 Suppose an intermediate solution at BB-Step 2 has uncovered com- 
 ponents of type NWG. We introduce new gates to cover some of them according 
 to the following scheme (case 1 or case 2). The augmented intermediate 
 solution resulting from this procedure will not have any type NWG components. 
 (The motivation will be discussed in section 3«^-«) 
 
 Case 1: (The current intermediate solution S has type NWG components in 
 only one gate k.) Let Pr , j=g_ , j t ..., be the type NWG com- 
 ponents. We select one of Fr, 3=3-,, j Q j •••* according to the 
 following procedure. 
 
 (i) For each component position j, j=j,, j p , ..., count the 
 number of external variables and/or gates whose j-th 
 components are 1. 
 (ii) Among $ , j , ..., select a j which has the largest total. 
 
38 
 
 (iii) Cover this j-th component with a new gate. (This gate 
 is assigned a gate label R+l, when S has R gates.) 
 
 By step (iii) the selected component (i.e., the component with 
 the selected j ) becomes type COV, and the rest of uncovered 
 components in gate k become type G*. In the augmented inter- 
 mediate solution, if gate R+l has no type NWG components, then 
 this intermediate solution has no type NWG components at all. 
 If gate R+l has type NWG components, then apply the steps (i) 
 through (iii) to the type NWG components of gate R+l. After 
 this, no gate i, i=l, ..., R+2 in the resulting intermediate 
 solution has type NWG components. 
 
 Case 2: ( The current intermediate solution S has type NWG components in 
 two or more gates k , k , . . . .) Let us illustrate first with an 
 example where two gates, gate 1 and gate 2, have type NWG com- 
 ponents. For k=l and 2, let T* be the set of indices j such 
 
 that P;=l, let F* be the set of indices j such that Pr=0 where 
 k k k 
 
 Er is type NWG, and let F be a non-empty subset of F* i.e., 
 
 F n c: F* and F n ± <3> . Clearly we need at least one new gate 
 k — k k 
 
 in order to cover one type NWG component. Suppose we cover 
 one type NWG component in gate 1. Then the rest of them (in 
 gate l) become type G*. At the same time, however, uncovered 
 components of the original type NWG in gate 2 may become more 
 desirable types because of the gate newly introduced into the 
 network. If all uncovered components originally of type NWG 
 in gate 2 become a more desirable type, then we do not need 
 
39 
 
 a second new gate; otherwise we must connect a second new 
 gate to gate 2. The following property is easily observed: 
 If we cover a type NWG component belonging to F c T* 
 (F c Tt) with a new gate, then we need another new gate for 
 gate 2 (gate l). If we cover a type NWG component not be- 
 longing to any F c t* (any F ^j T* ) with a new gate, then 
 this new gate becomes a possible cover for each uncovered 
 component belonging to F (F ) . Therefore, no additional 
 new gates are required. 
 
 Extending the above argument to the case where S has 
 three or more gates k , k , . . . , k which have type NWG 
 components, we have the following scheme for covering type 
 NWG components. Let K be the set of k , k , ..., k , i.e., 
 
 K= { k_ , k,_, . . . , k , ) , where k < k <: . . . < k < R . Let 
 l 7 2 7 7 r 7 12 r — 
 
 T*, F*, and F , for k e K be defined similarly as above. 
 A Scheme of Covering Type NWG Components 
 
 (i) u +- 1. Set F k = F* , and set G ■■■■ { k n } . 
 
 (ii) u +- u + 1 . If u > r, then go to (iv). 
 
 Set F 1 = F* . 
 k k 
 
 (iii) Check if F, c T* or F c rn* holds for all 
 k. — k k — k. 
 1 |i u 1 
 
 i < u . If this condition holds, then store k into 
 G, and go to (ii); 
 
 If this condition does not hold, but if F n c T,* or 
 
 7 k. — k 
 
1+0 
 
 F' 5 T* holds for a non-empty subset F' of F 
 
 U 1 11 
 
 (i.e., F' c F and F' £ 0) and for a non-empty 
 
 K. . r. . K . 
 
 11 l 
 subset F' of F for all i < n, then rename F' as 
 
 K K K. 
 
 U U 1 
 
 F n , and store k into G. 
 k. u 
 
 l 
 
 Go to (ii). 
 
 (iv) The set G is the set of the gates -which require new 
 gates. Let r denote the number of elements in G. 
 Select a type NWG component from each F , keG. If 
 
 K. 
 
 F , keG contains a single index j then the selected 
 component is Er ; if F , k£G contains two or more 
 
 K. K. 
 
 indices j, then select one Pr by applying (i) ~ (ii) 
 
 ri 
 
 of Case 1. 
 
 (v) Cover each of the selected components of type NWG by 
 a separate new gate. The r new gates are assigned 
 gate labels R+l through R+r . 
 
 (vi) If the resulting intermediate solution of R+r n gates 
 has again type NWG components, then apply Case 1 or 
 Case 2 to this olution. After that, the resulting 
 intermediate solution of R + r + r' gates where 
 r' > 1, will have no type NWG components at all. 
 
kl 
 
 2.3.U The SCUC and the IPPC 
 
 First we explain the selection criterion of uncovered components 
 (SCUC). We assume that the given intermediate solution has no uncovered 
 components of type NWG, and has at least one uncovered component whose 
 type is different from 1-COV. 
 
 Let us define the selection order of types . The selection order 
 consists of parts I and II. Part I is defined by the order G*C*0* - 
 G*C*0 - GC*0* - GC*0. Part II is defined by the order G*/D - VC*G*/ B ' " 
 G*/C - VC*G*/A T - G*/A* - G*/B' _ VC*/A , where these types are the 
 finely classified types of uncovered components of the original types 
 VC* and G* (of revised definition), as defined in the following: 
 
 Classification of Uncovered Components in Type VC* Gates' 
 
 VC*/A: A type VC* component which has only "bad" VC* possible 
 covers. (For the definition of "bad" and "good" pos- 
 sible covers, see Note 1 below. ) 
 
 G*/A' : A type G* component which has no "good" VC* possible 
 covers and is selected by a special procedure G* PICK. 
 (For the procedure G* PICK, see Note 2 below. ) 
 
 VC*G*/A': A type VC* or type G* component (different from VC*/A 
 or G*/A' ) of a type VC* gate which cannot be covered 
 with a single external variable. 
 
 f The mnemonic names VC*A, G*/A' , VC*G*/A' and VC*B*/B' correspond to 
 Davidson's VARD, EXPA' , VARB' and VARC f , respectively. 
 The definition of the finely classified types here is based on the 
 authors' interpretation of Davidson's paper, since Davidson did not 
 define explicitly. 
 
U2 
 
 VC*G*/B' : A type VC* or type G* component (different from VC*/A 
 or G*/A' ) of a type VC* gate which can be covered with 
 a single external variable. 
 
 Classification of Uncovered Components in Type G* Gates 
 
 t 
 
 G*/B' : A type G* component which is selected by the procedure 
 
 G* PICK, 
 
 G*/C: A type G* component which has VC* possible covers and is 
 different from type G*/B' . 
 
 G*/D: A type G* component which has no VC* possible covers and 
 is different from type G*/B' . 
 
 Note 1 An external variable x« is called a "bad" VC* possible 
 cover for an uncovered component Pr of gate k, if the 
 following condition holds: 
 
 Covering Pr by x» (i.e., a connection of x* to 
 gate k) causes a change of the type of uncovered com- 
 ponents in an immediately succeeding gate m of gate k 
 from G* to a less desirable type (Fig. 2.5)« 
 
 + The mnemonic names G*/B' , G*/C, and G*/D correspond to Davidson's 
 EXPB' , EXPC, and EXP respectively. 
 
 The definition of the finely classified types here is based on the 
 author's interpretation of Davidson's paper. 
 
^3 
 
 gate m Qj ( 00 ) 
 (J(0 ** ) 
 
 gate k 
 
 T 
 
 x £ ( 1 10 ) 
 
 Fig. 2.5 Example of the "bad" possible cover x. 
 
 J *0 
 for P . Assume that gate m has only one 
 
 input connection which comes from gate k. 
 
 J J l 
 
 By covering P. with x„, P " no longer has 
 
 a possible cover of type G* (gate k), there- 
 to 
 fore the type of P becomes less desirable. 
 
 An external variable x* which does not satisfy this 
 condition is called a "good" possible cover. 
 
 Note 2 The procedure G* PICK is given in the following. Given 
 gate k, this procedure attempts to select one component 
 among the uncovered components of type G* in gate k. 
 Let gate m denote a possible cover of type G* for some 
 or all uncovered components of gate k, let H denote 
 the set of all possible covers of types other than G* 
 for the uncovered components of gate m. The procedure 
 is: Search for a type G* component P~ such that by 
 covering it with gate m (of type G*), the number of 
 
 elements in H is reduced by at least one. If there is 
 
 m 
 
 such a type G* component for some gate m, then select 
 that component. 
 
kk 
 
 By combining Parts I and II, we have the following SCUC. 
 
 SCUC The Selection Order is Given By: 
 
 G*/D-VC*G*/ BI -G*/C* -VC*G*/ a ' -G*/A' -G*/B' -VCVA/-fi*C*0*-G*C*0-GC*0*-GC*0^ 
 
 Part II Part I 
 
 where G*/V is the most desirable, and GC*0 is the least desirable. Ac- 
 cording to this selection order, first we choose a gate which contains 
 uncovered components of the least desirable type. When there are two or 
 more such gates, if there is a tie in Part I, choose the one whose gate 
 label is the smallest or , if there is a tie in Part II, choose the one 
 whose gate label is the largest. Then, select an uncovered component 
 from the gate chosen above, but, if the gate contains two or more such 
 uncovered components (except type G*/A' or Gr*/B f , since G* PICK chooses 
 one in these cases), choose one which has the fewest possible covers. 
 
 After we select an uncovered component, we determine the imple- 
 mentation order of its possible covers. The implementation priority 
 of possible covers (IPPC) is as follows. 
 
 First, calculate the cost lower bound C for each possible cover 
 by the following procedure. 
 
 (i ) Implement the possible cover, generating the augmented inter- 
 mediate solution, S'. If S' does not contain any type NWG 
 
 + Notice that the definition of desirability in Part I is the reverse 
 of the one defined in section 2.3.1. 
 
^5 
 
 components, then go to (iii). 
 
 (ii) Apply 'A scheme of covering type NWG components' to S', gener- 
 ating another intermediate solution -which contains no type NWG 
 components. Rename this intermediate solution as S'. 
 
 (iii) Calculate C by the formula 
 L 
 
 C = AX { the number of gates in S'} 
 L 
 
 + BX { the number of connections/ interconnections 
 in S'} 
 
 + BX { the number of gates whose types are other 
 than G* or COV. } 
 
 (iv) If the possible cover under consideration is of type VC*, 
 
 modify C by the formula 
 Jj 
 
 modified C = original C T - (A + B) 
 L Ju 
 
 By using C ' s, the IPPC is given by the following. 
 
 Li 
 
 IPPC 
 
 Order the possible covers in ascending order of their respective C's. 
 If a tie occurs by this rule, order them according to VC* - G* - GC*0 - GC*0*- 
 G*C*0 - G^C^O* - NWG. 
 
 2.3.^ Modification of Backtrack at BB-Step k 
 
 The algorithm given in section 2.2 may enumerate the same intermediate 
 solutions more than once, for the following reason. Suppose we return to 
 an intermediate solution S by backtracking. ( S is reconstructed at BB-Step k. ) 
 
U6 
 
 J 
 Let P denote the output component chosen from S, and let pc , pc , 
 
 ..., denote the possible cover which we are about to implement. By im- 
 
 (1) 
 
 plementingpc , we had an augmented intermediate solution, S . By 
 
 implementing pc p , we will have another intermediate solution, S 
 
 Assume that there is an uncovered component P of gate k in S, different 
 
 from P , for which pc is a possible cover but pc is not. Since the 
 
 J l . (2) J l (2) 
 
 P remains uncovered inS v , the P must be covered by pc 1 in S , or 
 
 (2) 
 in a certain intermediate solution following S . But this is a redundant 
 
 process because we have enumerated the case where P is covered by pc 
 
 in S . The following procedure excludes this redundant process. 
 
 °0 
 (i) If pc. is gate i of type G*, then set P . =0 before we 
 
 implement pc2« 
 
 (ii) If pc is external variable x ., or gate i of type GC*0* or GC*0*, 
 
 (2) 
 then prohibit x, or gate i from being connected to gate k in S 
 
 and all succeeding intermediate solutions. 
 
 (iii) If pc is gate i of type G*0*O or type G*C*0*, then prohibit gate 
 
 i from being connected to gate k, if P. becomes 1, or set P. =0 
 
 (2) 
 if gate i becomes connected to gate k, in S v and in all suc- 
 ceeding intermediate solutions . 
 
 (iv) If pc is gate i of type NWG, then prohibit every gate m which is 
 
 (2) 
 introduced in S , or in any succeeding intermediate solution, 
 
 from being connected to gate k if P becomes 1, or set P_ =0 if 
 ^ mm 
 
 gate m becomes connected to gate k. 
 
^7 
 
 In a similar way, when we return again to S, we impose the restriction 
 corresponding to pc in addition to the one corresponding to pc_ , before we 
 implement the next possible cover, pc . By taking this procedure each time 
 we return to S, we exclude redundant enumerations. 
 
 From the programming view point, the above (i) and (ii) can be implemented 
 easily, whereas the (iii) and (iv) are more difficult. Thus, Davidson in- 
 corporated only (i) and (ii) into his program, but not (iii) and (iv). 
 
kS 
 
 3. COMPARISON OF THE TWO METHODS 
 
 In the last two sections, we explained the implicit enumeration 
 method and the branch- and-bound method* for the synthesis problem of optimal 
 NOR networks. For the sake of simplicity, we refer to the two methods as the 
 IE Method and The BB- Method, in the following. 
 
 Both methods enumerate the feasible networks implicity by covering the 
 O-components of the gate outputs. The basic ideas of the two methods are 
 essentially identical except for the difference that the IE-method is based 
 on inequalities while the BB-method is not. However, if we go into a de- 
 tailed discussion of the two methods, there are some differences in the 
 intrinsic properties which are incorporated in each program. 
 
 In this section, we summarize the differences in the following aspects, 
 namely 1. the concept of isolated gates, 2. generation of feasible net- 
 works, 3. exhaustion of feasible networks, and k. exclusion of unnec- 
 essary networks. Finally, we compare the programming aspect and the com- 
 putation speed of both methods. 
 
 3.1 The Concept of Isolated Gates 
 
 The most distinctive feature of the IE-method is that the number of 
 gates is fixed in the problem formulation. Because of this, we need the 
 concept of "isolated gates' as defined in section 1.3.2, whose counter- 
 part does not exist in the BB-method. Let us call a network which con- 
 sists of external variables and gates other than isolated gates a partial 
 network. 
 
 * The improved branch- and-bound method with redundancy check and other 
 gimmicks (Nakagawa and Muroga) are not discussed here. 
 
h9 
 
 Suppose the current partial network S requires an additional gate i to cover 
 an uncovered component of gate k in S. Clearly we only have to consider 
 covering the uncovered component under consideration, with an arbitrary- 
 isolated gate, because covering with other isolates gates simply results 
 in networks which are equivalent to the first one with gate labels per- 
 mitted. In order to preclude such equivalent networks, we underline the 
 assignment p., = 1 as we explained in Phase II of section 1.3.2, where 
 p., is the corresponding free variable. 
 
 The counterpart of a partial network is an intermediate solution in 
 the BB-method. In the BB-method, every uncovered component is assumed to 
 have one and only one possible cover of type NWG, besides having external 
 variables and/or existing gates as possible covers. Therefore, only the 
 free variable of type NWG, in the IE-method, which is chosen among all 
 isolated gates corresponds algorithmically to the possible cover of type 
 NWG, in the BB-method, for an uncovered component. 
 
 3.2 Generation of Feasible Networks 
 
 (Detection of whether or not a partial solution represents a feasible 
 network ) 
 
 In terms of the implicit enumeration method, a feasible solution is 
 defined by a complete assignment of N binary variables which satisfy the 
 given set of inequalities (1.6). Strictly speaking, the two expressions 
 "a feasible solution" and "a feasible network" have a subtle difference. 
 A feasible solution represents a feasible network, i.e., a network which 
 realizes the given function, but the converse is not necessarily true. 
 During the computation of the implicit enumeration method for the logical 
 design problem, we check whether or not all 0- components in the current 
 
50 
 
 partial network are covered at Phase III of IE- Step 3> as explained in 
 section I.3.2. If all O-components become covered (i.e., the type of the 
 network becomes COV), we call this partial solution a feasible network 
 even if some output components remain unassigned in this partial solution. 
 In the BB-method on the other hand, we check whether or not all O-com- 
 ponents are of type COV or 1-COV in the current intermediate solution. 
 If all O-components are of type COV or 1-COV, we call this intermediate 
 solution a feasible solution. As explained in section 2.3.2, output 
 components of type 1-COV are not yet covered. Therefore, this inter- 
 mediate solution may contain more unassigned components than the corres- 
 ponding partial solution of the IE-method, when they are considered as 
 feasible networks. Fig. 3*1 illustrates the difference. 
 
51 
 
 'a) A network for f = x (x v x ) v x x x with NOR gates, 
 
 1) (01111000) 
 
 (*O00011l) 
 
 5 ) (*0001000) 
 
 i;( oniiooo) 
 
 type 1-COV 
 £7(10000000) >T\ (^oi*l) 
 
 (b) An assignment of output com- 
 ponents when the partial net- 
 work is found to be feasible 
 in the IE-method. 
 
 f type 1-C0V 
 I 
 
 5)(*oooiooo) 
 
 (c) An intermediate solution which is 
 
 found to be feasible in the BB-method. 
 
 Fig. 3.1 A feasible solution to a function x (x ss x ) v x x x 
 
 by the two methods. 
 
52 
 
 Generation of an Augmented Partial Solution 
 
 Next, let us discuss the method of covering an uncovered component. 
 In order to select an uncovered component to cover, the IE-method em- 
 ploys the Selection Rule as explained in Phase II of section 1.3.2, while 
 the BB-metnod employs the Selection Criterion of Uncovered Components 
 (SCUC). The two rules are conceptually the same, though the SCUC is more 
 sophisticated than the Selection Rule. By covering an uncovered component 
 with a free variable (IE-method), or with a possible cover (BB-method), 
 we have an augmented partial solution, or an augmented intermediate 
 solution, respectively. We illustrate, with the following example, how 
 one iteration of the covering process in the BB-method corresponds to one 
 iteration in the IE-method. Suppose we are going to cover an output com- 
 ponent P of gate k by a possible cover gate i of type G*C*0* as shown 
 in Fig. 3' 2 (gate i which is not yet connected to gate k, has P = * and 
 
 has F?=* for some j such that R D = 1. Thus, it is of type G*C*0*) . 
 
 (a) 
 
 *1 
 
 1 ) 
 
 h 
 H 
 
 ll 
 
 i> 
 
 i i 
 
 1 1 t x Xj — ) 
 
 (h) 
 
 Fig. 3.2 Subnetwork of an intermediate solution where gate i is a possible 
 
 cover of type G*C*0* for P 
 
 '0 
 
53 
 
 One iteration of the covering process in the BB-metnod consists of the 
 following : 
 
 h 
 
 Change 1: Connect gate i to gate k, and assign 1 to P. 
 
 ^0 3 
 Change 2: Assign 0's to P and P , . 
 
 mm 1 
 
 Assign 0's to the output components denoted by (a) in 
 
 gate k. 
 
 Assign 0's to the output components denoted by (b) in 
 gate i. 
 
 Change 3: Update all necessary information for determining the types 
 of possible covers in the augmented intermediate solution. 
 
 The corresponding steps in the IE-method are as follows. First we fix 
 
 p. =1 at Phase II of IE- step 3- Then we transfer to IE- step 1. In 
 
 J 
 IE-step 1, this assignment p =1 induces the following changes due to 
 
 ik 
 
 the inequalities. 
 
 Zw? x- 5 + Z ^ > 1-U F 5 (#1) 
 
 i i q p Pq_ q 
 
 Z w^ x J + Z p£ < O^J (1-pJ) (#2) 
 
 I l l p Pq q 
 
 a + P^ > 2 $ , ^ > a + P 3 - 1 (#3 ) 
 
 Pq P - Pq' Pq - Pq P 
 
 and, inequalities expressing loop-free conditions (#4) 
 
 3 J 
 
 Change 1': The assignment B. n =1 forces a =1 and P. =1 through 
 
 ik ik i 
 
 the inequalities (#3)« 
 
 Change 2': The assignment P. =1, in turn, forces 6 . =0 and P =0 
 
 . l ' > ' mi m 
 
 3 «3n 
 
 as well as P im - = 1 and P m V = , 
 
fr 
 
 through the inequalities (#2) and (#3). The assignment 
 a =1 forces P*? k =l and then p£=0 for all j denoted (a). 
 
 And a. =1 forces P?=0 for all j denoted by (b), through 
 
 IK. 1 
 
 the inequalities (#2) and (#3). 
 
 Change 3'-l: The assignment a., =1 forces also some interconnection 
 variables a to through the inequalities (#0; for 
 example 0, .=0 due to a + a . < 1, ql =0 due to 
 
 a ik + %a + a mi ^ 2 > and S ° ° n ' 
 
 Change 3' -2: The assignment P. =1 forces all w p to where w^=* and 
 i 1 i * 
 
 x, s= 1, and forces all B . to where B =*, through 
 
 the inequalities (#2); then, the assignment B =0, in- 
 
 turn, forces a to if P =1 and <X .=*, through the 
 
 TUX "C "CX 
 
 inequalities (#3). The assignment P. =1 forces all 
 OL., to where B.. =0 and OL'.. = *, through the in- 
 
 equalities (#3). 
 
 Change 3* -3: The assignment P = at change 2' forces 6 , to 
 
 m mt . 
 
 for all 8 . = *. and so does the assignment P . = 0, 
 
 K mt ' m' 
 
 through the inequalities (#3). The assignment QL .=0 
 
 at change 3'-l forces pj. to for all B^. = * through 
 
 the inequalities (#3)> an -d so does the assignment 
 
 a. =0. 
 Km 
 
 We should notice that all of the above assignments must be underlined. 
 
 By the above changes 1', 2' and 3', IE- step 1 forms an augmented 
 
 partial solution S". S" = (S, B._° = 1, a., = 1, P.°= 1, P °=0, P 9=0,...) 
 
 , ^ik ' ik i ' m ' m 
 
55 
 
 The augmented partial solution S" is identical to the augmented inter- 
 mediate solution generated by an infc eration of the covering process in 
 
 the BB-method. 
 
 3«3 Exhaustion of Feasible Networks 
 
 In the BB-method, suppose we are given an intermediate solution S 
 
 /\ 
 
 from which an uncovered component P is selected by using the SCUC. Assume 
 
 /\ /\ 
 
 that the P has v possible covers, pc , •••) pc . First, we cover the P 
 
 with one of its possible covers, say pc , generating the augmented inter- 
 mediate solution S . When we come back to S by backtracking, we cover 
 
 the P with another possible cover, say pc , generating another augmented 
 
 (2) 
 intermediate solution, S . In this way, each time we come back to S, 
 
 /\ . 
 
 we cover the P with one of its unimplemented possible covers, thus we 
 
 /\ 
 
 exhaust all possible covers of the P. 
 
 The corresponding process of covering in the IE-method is as follows. 
 
 k (i ) 
 Let us rewrite the free variables w, and P-r. which correspond to the 
 
 possible covers pc, , . .., pc , as y.. , ..., y . First we fix one of y , 
 
 ..., y , say y , to 1, i.e., y = 1. Then write down the assignment y-, =1 
 
 on the right of the current partial solution S. Therefore, the augmented 
 
 partial solution becomes S' = ( S, y = l). In S' , the P is covered by 
 
 y . When we return to S by backtracking, we fix y , to the opposite value, 
 
 i.e., y = 0, and underline it. The new partial solution S" is 
 
 s " = (S, y, = 0). In s", the P is uncovered. Since y is fixed to 0, the 
 
 -*- JL 
 
 free variables that can cover P are y , . . . , y . Therefore, in S" (or in 
 succeeding partial solutions of S" ), when the P is chosen by the Selection 
 Rule, a free variable is taken among y p , . . . , y , to cover the P. In this 
 
56 
 
 way, each of the free variables y , . . . , y is enumerated to cover the P, 
 only once, except the free variables of type NWG. (For these free variables, 
 see the discussion in section 3«1« ) 
 
 The three major differences between the two methods are as follows: 
 
 The first difference is the selection of P. In the BB-method, when 
 we come back to the S, we cover the same P by the second possible cover. 
 In the IE-method, however, when when we come back to the S, we select, by 
 the Selection Rule, an uncovered component which is not necessarily the 
 old P. This strategy of the IE-method is better, because by this strategy 
 we always cover an uncovered component of the least desirable type, while 
 by the strategy of the BB-method we cover the same P which is no longer 
 necessarily of the least desirable type after the first possible cover 
 has been enumerated. 
 
 The second difference is the covering of P. In the BB-method, we 
 cover the P with a possible cover which raises the cost of the augmented 
 intermediate solution by the least amount among all unimplemented possible 
 covers. In the IE-method, we simply choose a free variable which deter- 
 mines the type of the P, but do not discriminate among the free variables 
 (corresponding to the P) with respect to the cost increase in the augmented 
 partial solution. The former strategy is better, because by this strategy 
 we may obtain an augmented intermediate solution having the least cost, 
 while by the later strategy, this is not necessarily true. 
 
 The third difference is the exhaustion of partial solutions. In the 
 IE-method, we do not generate the same partial solution twice or more. In 
 the BB-method, we do not generate the intermediate solution twice or more, 
 if we implement the entire scheme of section 2.3-5 in the program. As we 
 
57 
 
 mentioned there, however, Davidson's program includes the cases (i) and 
 (ii), but not (iii) and (iv). Therefore, his program may generate some 
 intermediate solutions twice or more. 
 
 3.6 Exclusion of Unnecessary Networks 
 
 (Unnecessary networks due to an excessive cost) 
 
 Between the two methods, there is a slight difference in the pruning 
 of the search tree by the use of z (or c), the cost of the best feasible 
 network found thus far, as shown in the following. 
 
 In the BB-method, the lower bound of cost of the given intermediate 
 solution is calculated from a consideration of its current configuration 
 along with the types of gates. In the IE-method, however, the lower 
 bound of cost of the given partial solution is calculated not only from 
 its current partial network along with the types of its gates but also 
 from the consideration of additional properties of the NOR network, as 
 explained in Phase III of section 1.3.2. Therefore, the cost lower 
 bound in the IE-method is more accurate than the one in the BB-method. 
 This means that more partial solutions are discarded in the IE-method 
 than in the BB-method. 
 
 (Unnecessary Networks Due to an Equivalent Configuration With Gate 
 Labels Permuted.) 
 
 We explained in section 3«1 that the treatment of isolated gates 
 in the IE-method (i.e., underlining the assignment p., = 1 when B. is a 
 free variable of type NWG) is equivalent to the treatment in the BB-method 
 where the number of type NWG possible covers is only one for each selected 
 
58 
 
 uncovered component. Notice, however, that this treatment (i.e., the 
 treatment that for each uncovered component we have only one free variable 
 of type NWG in the IE-method, or only one possible cover of type NWG in the 
 BB-method) still cannot eliminate all equivalent networks with gate labels 
 permuted, as the following example illustrates. This example is for the 
 IE-method. But it is also applicable to the BB-method. Suppose the given 
 
 output function is x x . We start with the partial solution S^ = (P =0, 
 
 12^ 01 2 
 
 p =o, P =0, Pl=l), where P , P , and P are of type NWG. The corresponding 
 
 partial network is shown in Fig. 3*3 (a). If we want to cover P =0 with 
 
 a new gate (gate 2), then we fix the free variable p to 1 and underline 
 
 it as Ppn = 1. The augmented partial solution S p is: S = (S_, 3 _=l). 
 
 The assignment 3p-,=l forces some free variables to ones through the basic 
 
 inequalities. After going through IE-step 1, S is changed to S , 
 
 S, 
 
 = ( S 1 , p^ = 1. a =1, P° = 1, P^ = 0). Fig. 3.3 (b) is the net- 
 
 work representing S„. From S , we will obtain two feasible solutions, 
 Figs. 3-3 (c) and (d). Thus the same network is repeated. 
 
59 
 
 gate 2 Q 
 
 O* 
 
 irate 1 
 
 (a) Initial partial solution, S_ . 
 
 (b) Augmented partial solution S . Both 
 x and x can be connected to gate 2, 
 
 (V ) Augmented partial solution 
 
 S . x can be connected to 
 gate 2, but x cannot. 
 
 gate 3 
 
 (c) A feasible solution of f=x x . 
 
 cate 2 
 
 gate 3 
 (d) Another feasible solution of 
 
 f = X l X 2* 
 
 (c') A feasible solution of 
 
 X l V 
 
 Fig. 3.3 Illustration of the process 
 of generating a feasible 
 solution for the function 
 
 X l X 2* 
 
6o 
 
 Alternatively, if we cover FT = in S.. with a new gate (gate 2) 
 we fix (3..p to 1 and underline it as 3 pi = 1. The augmented partial solution 
 S is : Sp = ( S 1 , Pp, = l). The assignment p p - = 1 forces some free 
 variables to ones through the basic inequalities. After going through IE- 
 step 1, S^ is changed to S* S^ = (S^ ppj=l, Ot 21 =l, P^l, P^=0, W^=0). 
 
 Fig. 3*3 (h 1 ) is the network representing S . Note in this case that the 
 
 t 
 
 external variable x p is prohibited from being connected to gate 2 in S._, 
 
 1 1 • 
 
 because of P p =l and x =1. From S we will obtain only one feasible solution 
 
 as in Fig. 3.3 (c f )« This is simply Fig. 3.3 (c). It is interesting to see 
 that, depending on which uncovered component of type NWG we cover with a new 
 gate, the number of networks equivalent with gate labels permuted varies. 
 Clearly the number p of external variables and existing gates which can be 
 connected to the new gate under consideration depends on the position of the 
 1- component of the new gate, and so does the number q of existing gates to 
 which the new gate can be connected. (Note that when a new gate is introduced 
 to cover an uncovered component, the new gate has only a single 1-component 
 which corresponds to the uncovered component. ) As the above example illustrates, 
 reducing the number p (or p+q) for the new gate upon its introduction seems 
 to be a good method for the reduction of the number of equivalent networks. 
 
 The BB-method has this feature which is applied not only to the out- 
 put gate but also to any other gates which have type NWG components, as 
 explained in section 2.3.3. The IE-method lacks the corresponding feature, 
 but it employs a gimmick which has an effect similar to the above feature. 
 Assuming that gate 1 has at least two inputs from other gates in the 
 optimel network, we lexicographically order the output of the two imme- 
 diately preceding gates, say, gate 2 and gate 3 of the output gate 1 as 
 follows : 
 
61 
 
 2 n -l 2 n ~l 
 Let ( P , . . . , Fl ) and ( P , ..., P ) denote the outputs of gates 
 
 2 and 3 respectively. The ordering is given by the inequality 
 
 2 -1 n .. . . 2 -1 „n ., . 
 
 Z 2 2 - 1 " 1 x ?l > 2 2 2 - 1 " 1 x P* 
 
 i=0 d i=0 J 
 
 (Unnecessary networks due to having redundant connections.) 
 
 In the IE-method, some kinds of redundant connections can be pre- 
 cluded by the use of inequalities. Figs. 1.2 ~ 1.5 show the redundant 
 connections which are precluded by the inequalities (1.8) ~ (l.ll). 
 
 These constraints are suitable to incorporate into the problem for- 
 mulation of the IE-method, but not into the BB-method. The BB-method 
 lacks a corresponding feature. * 
 
 3.5 The Programming Aspect and the Computation Time 
 
 Ibaraki et al. developed a code for general 0-1 integer programming 
 by the implicit enumeration method. The code, called ILLIP (iLLinois 
 Integer Programming code [12,l6]), is written in FORTRAN for the IBM 360/75. 
 By modifying ILLIP with the gimmick of 'A NOR-gate oriented scheme of 
 fixing a free variable', Baugh et al. prepared the implicit enumeration pro- 
 gram for the logical design problem with NOR gates [2], The latter program 
 consists of about 2000 FORTRAN statements, which are translated into kO K 
 bytes of machine instructions. (The subroutines corresponding to the above 
 gimmick consist of about 300 FORTRAN statements, or 6 K bytes of machine 
 
 * The improvement of the BB-method incorporating new gimmicks corres- 
 ponding to these constraints of the IE-method is reported in [2^]. 
 
62 
 
 instructions.) On the other hand, Davidson implemented a computer program 
 for the branch- and bound algorithm for the CDC l604. The program consists 
 of over 5500 records of instructions in the CDC l60*+ Assembler. In order 
 to compare the computational efficiency of the BB-method and the IE-method, 
 using the same computer, we implemented the BB-method in FORTRAN. The pro- 
 gram consists of 2200 FORTRAN statements, which are translated into 52 K 
 bytes of machine instructions. 
 
 Although this program may differ from Davidson's program in some of 
 the detailed aspects of the gimmicks, it may be worth while to compare this 
 program with the IE-method. 
 
 The program with the CDC Assembler was compactly prepared because of 
 the memory space limitation of the CDC l6ok computer, while the above two 
 programs with FORTRAN were not because of the abundant memory space of the 
 IBM 360/75 !• In this sense, a comparison of the number of program state- 
 ments between programs implemented on the different computers is not 
 meaningful. 
 
 Table 3*1 shows the computational results for the functions of three 
 variables which require 6 and 7 NOR gates in their optimal networks. Since 
 the IE-method solves the problems with a fixed number, R, of gates, the 
 FORTRAN program of the BB-method was run for the same problems by imposing 
 R < 6, or R < 7*, depending on the problem. According to the results in 
 Table 3«1> the computation speed by the BB-method is two to three times 
 faster than the IE-method. 
 
 For a fair comparison with the IE-method, we imposed this restriction. 
 Although this restriction may slightly reduce the computation time from 
 the case without a restriction of the number R of gates (probably in 
 only a few percent of the cases). 
 
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 This difference may arise from the following: 
 
 (i) The heuristics of the SCUC and the IPPC of the BB-method are much 
 more sophisticated than those of the Selection Rule in the IE- 
 method. Therefore the BB-method will generate the optimal solu- 
 tions more efficiently than the IE-method. The difference of 
 the total number of feasible solutions (including the optimal ones) 
 generated by the two methods proves that the heuristics of the 
 BB-method are better than the one of the IE-method. 
 
 (ii) One iteration of the covering process in the BB-method is com- 
 pleted by a subroutine specifically tailored to the problem of 
 NOR gates, while the corresponding operation in the IE-method is 
 completed through the inequalities at IE- step 1, as is explained 
 in section 3*2. The use of inequalities seems to be more time- 
 consuming than the specifically designed subroutine of the BB- 
 method in two aspects: First, a variable which must be fixed 
 in the IE-method is detected only after checking of values of 
 
 certain m.'s, where each m. = Z c.y.+b, 
 
 (y.: fixed variables) 
 
 is the left-hand side of (1.6). Second, m. for all i=l, . .., 
 M must be updated each time a variable is fixed. 
 Although the program ILLIP has a programming gimmick which improves 
 the computational procedure by reducing as much unnecessary computational 
 work as possible, still the computation time required for the above two 
 aspects are intrinsic to the inequality approach. 
 
 Going to problems of functions of more variables which require more 
 gates, the difference in the computation times of the two methods becomes 
 greater. Table 3.2 shows the average computation times for some 6, 7, and 
 
65 
 
 8-gate functions of four variables. These figures are plotted in Fig.3»^» 
 The storage requirements for the IE-method becomes critical, as Table 
 3.3 shows. Notice that most of the information the programs handle are in 
 binary form. In the program of the IE-method, one bit of information oc- 
 cupies two bytes, while in the program of the BB-method, it occupies four 
 bytes (the use of different numbers of bytes has no very significant reason). 
 Therefore, the absolute sizes of those figures are not important, but the 
 relative sizes are worthwhile to compare. One more point about memory space 
 is that in the IE-method, the memory space for one problem remains fixed 
 while in the BB-method it does not because the latter contains the PC-list 
 (Possible Cover list) whose length varies during the computation. However, 
 for most of the experimental problems, the maximum length of the PC-list 
 rarely exceeded 100 items. Therefore, the storage requirement for the 
 BB-method will not become critical. 
 
66 
 
 1 J 
 
 1 — __ — « 
 
 COMPUTER PROGRAM (IBM 360/75) 
 
 The Implicit Enumeration 
 Method (the IE-method ) * 1 ' 
 
 The Branch- And- Bound 
 Method (the BB-method ) v 
 
 83 6-gate 
 functions of 
 four variables 
 
 6.36 sec. 
 
 4.56 sec. 
 
 k6 7- gate 
 functions of 
 four variables 
 
 92.25 
 
 31.65 (3) 
 
 2 8-gate 
 functions of 
 four variables 
 
 125^.5^ 
 
 U.7.8U 
 
 TABLE 3*2 The average computation times for some functions of four vari- 
 ables by the IE and the BB methods. 
 
 Note 1 The computation time by the IE-method is due to CuLliney [5]. 
 
 2 The computation by the BB-method is done without imposing a 
 restriction on the maximum number R of gates such as R < 6, 
 R < 7, or R < 8. So restricting the maximum number of gates 
 could generally reduce the computation time slightly except 
 for a few extraordinary cases as mentioned in Note 3 below. 
 
 3 Among k-6 functions there is one 7-gate function for which the 
 computation did not terminate in 700 seconds by the BB-method. 
 The best network found within 700 seconds has 9 gates/l8 con- 
 nections, while the optimal one has 7 gates/l8 connections. 
 For this reason, we excluded this function from the statistics . 
 (That is, the figure 31.65 seconds is the average for U5 7-g a te 
 functions, instead of k6 functions.) By imposing R < 7, the com- 
 putation terminated in 2k.k2 seconds for this function. 
 
67 
 
 time in seconds 
 10000" 
 
 1000" 
 
 100 
 
 io-- 
 
 w 
 
 gates 
 
 Fig. J,.h The average computation time for 6, 7 and 8-gate functions 
 of four variables by the two methods. 
 
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69 
 
 To summarize the above points, the logic design by the IE-method 
 confronts a tighter barrier on the problem size than does the BB-method. 
 
 However, an advantage of the IE-method exists in the ease of pro- 
 gramming effort. For logic design by the IE-method, we need to write 
 only the inequalities along with a program for the fixing scheme of free 
 variables, the scheme explained in section 1.3.2, when a code for the 
 implicit enumeration algorithm is available, while for the logic design 
 by the BB-method we must write the entire program. This difference in 
 programming effort is especially important when we want to develop com- 
 puter programs for the design problems with different type of gates. As 
 will be seen in the next section about the AND/OR problem formulation, 
 in the case of the IE-method, the programming effort required to convert 
 the program to handle another logical design problem with a different 
 type of gate is simply a change of some inequalities and a replacement 
 of the subprogram which fixes free variables according to the heuristics; 
 but in the case of the BB-method, an entirely new program must be written. 
 In other words, the development of a computer program for another design 
 problem with different types of gates by the BB-method, involves almost a 
 complete rewriting of the integer programming code. 
 
 Table 3'^- shows the approximate amount of time in weeks* needed for 
 developing the programs of the IE-method and the BB-method, according to 
 our experience. Writing the programs from scratch, the IE-method required 
 about 11 weeks while the BB-method required about l6 weeks as seen in 
 Table 3.k (a), time required to understand the algorithms and debugging 
 time is included. It is much harder to understand the details of the 
 
 * ' Weeks ' mean man- weeks . 
 
TO 
 
 BB-method. If a ready-made code of the implicit enumeration method were 
 available, then 6 weeks would be required instead of U weeks. 
 
 When programs for different types of gates were to be prepared, the 
 IE-method required only 2 weeks while the BB-method required 16 weeks as 
 shown in Table 3.k (b) (note that the subroutine SELECT in Table 3.U (b) 
 is a simpler one than that used in (a)). Since the BB-method is much 
 more complicated than FIXJ of the IE-method, debugging the program of the 
 BB-method was much harder. And if a programmer is not completely familiar 
 with the BB-method or if his programming procedure is not appropriate, 
 then changing the BB-method program for new types of gates would take 
 longer. Certainly, the IE-method has a greater advantage in programming 
 effort requirements than the BB-method. 
 
 In this comparison, however, the programs for the two methods were 
 prepared by different people, though their capabilities appeared to be 
 comparable. In this sense the above comparison is only intended to show 
 a rough comparison. 
 
71 
 
 The IE-method 
 
 The program ILLIP 
 
 (A code of general 0-1 integer pro- 
 gramming by the Implicit enumeration 
 method. ) 5 weeks 
 
 Two subroutines, FIXJ and BNDCHK, 
 
 which is a particular fixing scheme 
 
 for the NOR problem as explained 
 
 in section 1.3.2. k weeks 
 
 The program which generates the 
 
 inequalities of the NOR problem. 2 weeks 
 
 The BB-method 
 
 The entire program except the subroutine 
 SELECT which chooses an uncovered com- 
 ponent according to the SCUC as explained 
 in section 2.3.k. 8 weeks 
 
 The subroutine SELECT 8 weeks 
 
 TABLE 3.U (a) The approximate amount of time needed for 
 
 developing the programs for the NOR problem 
 by the IE and BB methods. 
 
72 
 
 The IE-method^ 
 
 
 Change of a subroutine, F3XJ, for 
 
 
 the NOR case to the one for the 
 
 
 AND-OR problem as will be ex- 
 
 
 plained in section 4.1.2. 
 
 1 week 
 
 The program which generates the 
 
 
 inequalities of the AND-OR problem. 
 
 1 week 
 
 (2) 
 The BB-method v J 
 
 
 The entire program 
 
 8 weeks 
 
 TABLE 3.k (b) 
 
 The approximate amount of time needed for developing the 
 program for the AND-OR problem by the IE and BB methods, 
 after the program for the NOR problem was completed. 
 
 Note 1 Since we do not need to rewrite the code for the implicit 
 enumeration method, the programming work is only the 
 writing of a new FIXJ and a new program for generating 
 the inequalities. 
 
 Note 2 We must rewrite the entire program. In this AND-OR problem, 
 the scheme of the SCUC is much simpler than Davidson's SCUC 
 for the NOR problem. Hence we do not list it separately 
 from the rest of the code. 
 
73 
 
 k OPTIMAL NETWORK DESIGN USING AMD and OR GATES 
 
 The concepts and gimmicks used in the formulation of the AND-OR problem 
 have their counterparts in the NOR problem formulation, except for the new 
 concept that each gate may assume either of two gate modes*, i.e., AND or 
 OR. Therefore, we present the two methods for the AND-OR problem only 
 briefly in sections k.l and k.2. At the end of section k. 2, we compare the 
 heuristics of assigning the modes to gates in the two methods. A com- 
 parison of the programs for the two methods is given in section k.3» 
 
 k.l Formulation of the AND-OR Problem by the Implicit Enumeration Method [17] 
 U.l.l The Inequalities 
 
 The inequalities for the AND-OR network of R gates is as follows. 
 
 Assuming that complemented variables x. ' s are also available as 
 
 — k — k 
 inputs to a network, we introduce new variables, w. , where w- represents 
 
 a connection of x^ to gate k if w^ = 1, or no connection of x^ to gate 
 
 k if w^ = 0. 
 
 (i) Basic inequalities 
 
 Suppose gate k is OR. The output component R* = 1 if there is at least 
 one input whose j-th component is 1, or if = if all of the j-th components 
 of its inputs are 0. Thus, we have the inequalities: 
 
 Types of gates, i.e., AND and OR, are called modes in this text, 
 because the phrase "type of gate" is reserved for a different 
 meaning. 
 
7* 
 
 (OR gate k) 
 
 C n , . n _, 
 
 Z w, x] + Z Vg (1 
 
 £=i * * i=a * 
 
 n . . n 
 
 Z w. x J . 4- Z w* (1 
 
 R 
 x J J + Z 6.J > 1-U (1-pJ) 
 
 i=l 
 i+k 
 
 R 
 
 ik 
 
 - x 
 
 ) + E P .J < U Pj , 
 
 i=l 
 i^k 
 
 ik 
 
 where p.? = a.. F? . 
 
 ik ik i 
 
 On the other hand, suppose gate k is AND. The output component Pr = 
 if there is at least one input whose j-th component is 0, or k = 1 if 
 all of the j-th components of its inputs are 1. Thus, we have the in- 
 equalities: 
 
 (AND gate k) 
 
 n _ . n 
 
 E w x\ + Z w (1 
 
 £=l * l £=1 l 
 
 n - k * n k 
 Z w, x 3 + Z w, (1 
 
 £=1 * & i=l * 
 
 R 
 x 3 ) + L 7.? > 1-U P? 
 £ L=l 
 
 ifk 
 
 R 
 
 - x 
 
 ) + 2 7,£ < U(l-Pj) , 
 
 i=l 
 
 i+k 
 
 ik 
 
 k' 
 
 where 7 ±k = a ±k - p^. Notice that the ? £ are new variables which do 
 not exist in the NOR problem. 
 
75 
 
 In an actual AND-OR network, each gate k must represent either the 
 function AND or OR. Hence, we combine the above two sets of inequalities 
 using another variable \ in the following: 
 
 (gate k) 
 
 Z w k A + Z w k (l-x J ") + Z p J > 1-U (l-pj) - U(l-V) 
 £=1 Z Z £=1 l l i=l 1K k 
 
 n , n 
 
 i*k 
 R 
 
 i+k 
 
 A ^ ^ + A *5 (i_x ^ + A r ^ - i_uPk 
 
 i*k 
 
 n 
 
 + U (l-\) 
 
 -U \ 
 
 k 
 
 A w l 4 + A w i ^ + .*, 7 ik 5 u(i-FJ) + u ^ 
 
 £=1 £-1 1=1 
 
 i^k 
 
 for j=0, . . . , 2 -1. 
 
 > (^.D 
 
 When K = 1, then obviously the last two inequalities of (^.l) become non- 
 restrictive and the first two are the inequalities representing an OR gate. 
 When K = 0, then the first two inequalities become non- restrictive and the 
 last two are the inequalities representing an AND gate. 
 
 The non- linear equations 3 
 
 ik 
 
 a„ ri and y.j 1 = a., 
 
 xk i ik ik 
 
 (3. r_ can be expressed 
 
 by: 
 
76 
 
 *£ - 2 a xk + i + 2 hi * ° 
 
 • 3 p ik + 3 a ik + 4 - k7 ii * x 
 
 R 
 - Z p.? + U K > 
 t=l Xt X " 
 
 t=i 
 
 Ji 
 
 ) (k.2) 
 
 for j=0, . .., 2 -1, and 
 
 i=l, . . . , R, i=j=k. 
 
 J 
 
 In order that the network be loop-free, we must prohibit the inter- 
 connections from forming loops. Different from the formulation of the 
 NOR problem, however, we do this not by 'loop-free' inequalities, but by 
 a subroutine. This saves the memory space otherwise needed for these 
 
 inequalities. 
 
 2 n -l 
 Suppose we are given a switching function f(x) = (f , . . . , f ). 3y 
 
 setting rf = f 3 , for j=0, ..., 2 n_1 , in (k.l) for k=l , the set of in- 
 equalities (k.l) and (^.2) for k=l, ..., R becomes the corresponding 
 mathematical expression of the AND-OR network with R gates for the f(x). 
 
 (ii) Additional Inequalities 
 
 In order to preclude unnecessary solutions, we incorporate the fol- 
 lowing 'additional inequalities' into the problem formulation. The idea 
 is similar to that explained in section 1.3-1 for the NOR problem. 
 
 (l) Each gate, except the output gate, has at least one output 
 connection to another gate. 
 
 Z a > 1 for k = 2, . . . , R. 
 
 t+k kt 
 
77 
 
 (2) If three gates, i, k, and p, are connected as shown in Fig. ^-.1, 
 then the network is not optimal. Therefore we have the following 
 
 inequalities. 
 
 a. + a., + a , < 2 for i, k, p = 1, . . . , R, where i, p, k 
 lp xk pk — ' ' ' ' ' ' 
 
 are different from each other. Even if we replace gate i by 
 
 an external variable x* or x*, the above property holds, i.e., 
 
 \rl + w. + a < 2, and w^ + w, + a < 2. But we did not 
 
 include these inequalities into the problem formulation, because 
 they did not seem to be very effective in reducing the com- 
 putation time. 
 
 (may have other connections) 
 
 (gates i, p, k can be either AND gates or OR gates) 
 
 Fig. k.l Triangular condition 
 
 (3) Each gate has at least two inputs. 
 
 n k n _ R 
 S w. + Z w. + 2 a > 2 
 1=1 * i=l l i=l lJs " 
 
 i+k 
 
 for k=l, . . . , R. 
 
 (h) Suppose two gates i and k are of the same mode (both are AND 
 gates or OR gates), where gate i is connected to gate k. Gate 
 i must have at least one more output connection, assuming that 
 
78 
 
 no fan- in constraint is imposed on the gates. (Fig. k.2) 
 
 A si 
 
 i. ^ equivalent \^ M 
 
 no other output inputs 
 
 connections from to gate i 
 
 gate i 
 
 This restriction is given by 
 
 //it 2 x -\ - \ - & - V 
 
 t=l 
 t*i 
 
 ttk 
 
 t ^it > ^i - \) - (i - V - (i - « ik ) 
 tjd 
 
 tfk 
 
 for i, k=l, . .., R, where i±k. 
 
 (5) At least one AND gate and one OR gate must exist in the optimal 
 
 network. 
 
 R R 
 
 Z *.. > 1. and S \. < R-l . 
 
 1=1 i=l 
 
 4.1.2 The AJTO-OR Oriented Scheme of Fixing a Free Variable at IE-step 3 
 
 In Phase I of IE-step 3 of the implicit enumeration algorithm, we 
 choose a free variable to fix, using the Selection Rule . In order to state 
 the rule for the AND-OR case, we start with some definitions. Corresponding 
 to Er.=l in an OR gate, the types of the variables f3.£ , w* and w, are 
 
 defined as follows: 
 
79 
 
 Types 
 
 Variables Which Are Assigned Types 
 
 GOV 
 
 r 
 
 (3.£ which is already fixed to 1. 
 
 w, which is already fixed to 1, and for which 
 
 < 
 
 I 
 
 - k 
 
 x u , = 1. 
 
 w* which is already fixed to 1, and for which 
 
 4 ■ °- 
 
 G* 
 
 P.? which is * (free), where a., =1 and F? = *. 
 
 lk ' lk i 
 
 VC* 
 
 k k 
 
 w, which is *, where x,=l . 
 
 — k — i 
 
 w. which is *, where x =0. 
 
 GC* 
 
 B.^ which is *, where a =* f F?=l, and gate 
 
 IK. IK. X 
 
 i is not isolated. 
 
 G*C* 
 
 6., which is *, where a., =*, F:=*, and gate 
 lk ' lk ' i ' 
 
 i is not isolated. 
 
 NWG 
 
 3.^ which is *, where gate i is isolated. 
 
 Corresponding to Pr = in an AND gate k, the types of the variables 7.^, 
 
 k — k 
 \r g, and w, are defined as follows: 
 
 Types 
 
 Variables Which Are Assigned Types 
 
 r 
 
 cov 
 
 ^. 
 
 7.r. which is already fixed to 1. 
 
 k 1 
 
 w, which is already fixed to 1, and for which x^=0. 
 
 - k i 
 
 w* which is already fixed to 1, and for which x «=1. 
 
 '£ 
 
 r 
 
8o 
 
 Types Variables Which are Assigned Types 
 
 7.? which is *, where a =1 and P: = *. 
 
 ik ' ik i 
 
 G* 
 
 VC* 
 
 G*C* 
 
 NWG 
 
 Wp which is *, where x^ = 0. 
 
 — k j 
 
 Wp which is *, where x r, = 1. 
 
 7.? which is *, where a.. = *, P. = * and 
 ik ' ik ' i 
 
 sate i is not isolated. 
 
 7 , which is *, where gate i is isolated, 
 ik 
 
 The desirability order of types is defined by COV, G*, VC*, GC*, G*C*, NWG 
 where COV is the most desirable, and NWG is the least desirable. 
 
 The type of Pr = 1 in an OR gate k is defined by the most desirable type 
 
 rL 
 
 among the variables corresponding to Pr , and so is the type of Pr = in 
 an AND gate k. 
 
 The type of gate k is defined as: ISL, if gate k is isolated. 
 
 Otherwise the type of gate k is defined as the least desirable type of 
 output component among all output components Pr = 1 of gate k if gate k 
 is OR, or among all output components P~ = of gate k if gate k is AND. 
 
 K. 
 
 Let the desirability of types of gates be defined by ISL, COV, G*, VC*, 
 G*C*, NWG, where ISL is the most desirable, and NWG is the least desirable. 
 
 The type of the partial network is defined by the least desirable type of 
 gate among all gates. With the use of the above concept, the Selection 
 
81 
 
 Rule is given as follows: 
 
 Step 1 Chosse a gate which defines the type of the partial network. In 
 
 the case where there are two or more such gates, choose one having 
 
 the smallest gate label k. 
 
 J 
 Step 2 Choose an output component P which defines the type of the gate. 
 
 K. 
 
 In the case where there are two or more such output components, 
 
 choose a P, having the fewest free variables which cover it. Then 
 k 
 
 • , , k - k 3 3 /n 
 
 choose a free variable w*, w, , g or y., (depending on the 
 
 mode of gate kj which defines the type of the P . In the case where 
 
 k 
 
 there are two or more such free variables, then choose one which 
 has the smallest label & of external variable x, or the smallest 
 label i of gate i. 
 
 In Phase II, we fix the selected free variable to 1. This procedure is 
 the same as for the NOR problem, except that we also fix the free variable 
 "K. according to the following rule, when the selected free variable corre- 
 sponds to the new gate i, assuming no fan- in restriction. 
 
 r 
 
 \. = (gate i to represent AND) 
 
 if gate k is OR, 
 
 V =1 (gate i to represent OR) 
 ^ if gate k is AND. 
 
 The motivation behind this rule is: An optimal network more likely has those 
 interconnections between different gate modes (i.e., AND to OR, or OR to AND) 
 than those between the same gate types (i.e., AND to AND, or OR to OR). Thus, 
 
82 
 
 we want to enumerate the former case first, letting gate i be AND when 
 gate k is OR, or gate i be OR when gate k is AND. 
 
 In Phase III, in the case of the NOR problem, we calculated the cost 
 lower bound of the partial network. However, the IE-method for the AND- 
 OR problem lacks the corresponding procedure. The reason is that the use 
 of the cost lower bound would not be very effective in discarding non- 
 optimal solutions for the AND-OR problem, judging from our experience in 
 the case of the NOR problem, (this observation was made on only functions 
 of three variables ) . 
 
 k.2 Formulation of the AND-OR Problem by the Branch- And- Bound Method [23] 
 
 1+.2.1 Definitions 
 
 The initial solution is a gate which is assigned the given switching function 
 f (x), but has no inputs yet; the gate is labeled "gate 1". Since the gate 
 may assume either the function AND or OR, we must try two initial solutions, 
 namely the AND gate 1, and the OR gate 1. 
 
 An intermediate solution S is an AND-OR network of R gates (R > l) with 
 both uncomplemented and complemented external variables, satisfying the 
 following : 
 
 Condition 1 The network has neither isolated gates nor loops; R gates are 
 labeled with consecutive integers 1 through R. 
 
 Condition 2-1 Gate 1 is assigned the given switching function f(x). 
 
 Condition 2-2 The output of each gate k other than gate 1 is specified as; 
 
83 
 
 (1) Pr = 1, if there is at least one immediately succeeding AND 
 gate whose j-th component is 1, 
 
 (2) R; = 0, if there is at least one immediately succeeding OR 
 gate whose j-th component is 0, 
 
 (3) FT = 0, if gate k is AND, and if there is at least one im- 
 
 K. 
 
 mediately preceding gate or connected external variable 
 (x., x .) whose j-th component is 0, 
 
 (h) Pr = 1, if gate k is OR, and if there is at least one im- 
 
 mediately preceding gate or connected external variable 
 (x*, x.) whose j-th component is 1. 
 
 Some of the Pr's may be unspecified. These are denoted by an asterisk(*), 
 
 ri 
 
 An output component Pr = (Pr = l) of an AND gate k (OR gate k) is 
 said to be covered , if gate k has one input (external variable x,, x . or 
 gate i) whose j-th component is (l). 
 
 An output component P = (Pr = l) of an AND gate (OR gate) is un- 
 covered, if it is not yet covered. 
 
 A feasible solution is defined as an intermediate solution in which all 
 0-components in all AND gates, and all 1-components in all OR gates are 
 
 covered. 
 
 j 
 The possible covers of an uncovered component P = in AND gate k, 
 
 are defined as follows. 
 
 Type Possible cover (gate i or external variable x ., x») 
 
 G*A OR gate i which is connected to gate k, and has 
 
 ^0 
 P. = *. 
 
 l 
 
84 
 
 Type 
 
 Possible cover (gate i or external variable x*, x.) 
 
 VC* 
 
 GC*A 
 
 x, (or xJ which is not yet connected to gate k ; 
 
 J Q J Q -j J 
 
 has x = (or x. = 0), and has yr =l (or x^ =l) 
 
 'I 
 
 -i J 
 
 for all j such that Pr = 1. 
 
 k 
 
 OR gate i which is not yet connected to gate k, 
 
 J i 
 
 has P. = 0, and has Pr = 1 or * for all j such 
 
 that Pr = 1, where a connection of gate i to 
 
 .K. 
 
 gate k will not form any loops in the network. 
 
 G*C*A 
 
 OR gate i which is not yet connected to gate k, 
 
 J 'o J 
 
 has P. = * and has K = 1 or * for all j such 
 that Pr =1, where a connection of gate i to gate 
 k will not form any loops in the network. 
 
 NWGA 
 
 -\ 
 
 G*B 
 
 GC*B 
 
 G*C*B 
 
 NWGB 
 
 J 
 
 OR new gate. All output components are *. This 
 gate is labeled R + 1, when the current inter- 
 mediate solution has R gates. 
 
 For AND gate i, these types are defined by re- 
 placing OR by AND in the above definitions. 
 
 The definitions of possible covers for an uncovered component P, = 1 in an 
 OR gate are given in the same way as above, except that 1 and are inter- 
 changed, and that OR gate i and AND gate i are interchanged. 
 
85 
 
 The Desirability order of these types is defined by G*A, VC*, GC*A, G*C*A, 
 G*B, GC*B, G*C*B, NWGA, NWGB, where G*A is the most desirable, and NWGB is 
 the least desirable. 
 
 The type of an uncovered component P is defined as the most desirable type 
 
 
 
 among 
 
 those of all the possible covers of the P v (= 1 or 0) 
 
 The type of gate k is defined as follows: 
 
 COV If gate k has no uncovered components (gate k may have unassigned 
 components *) . 
 
 G*X 
 
 If every uncovered component is of type G*A or G*B. 
 
 VC* 
 
 If every uncovered component is one of types G*A, VC* or G*B, 
 and there is at least one uncovered component of type VC*. 
 
 GC*X 
 
 If every uncovered component is one of types G*A, VC*, GC*A, 
 G*B or GC*B, and there is at least one uncovered component of 
 type GC*A or GC*B. 
 
 G*C*X 
 
 If every uncovered component is one of types G*A, VC*, GC*A, 
 G*C*A, G*B, GC*B or G*C*B, and there is at least one uncovered 
 component of type G*C*A or G*C*B. 
 
 NWGX If there is at least one uncovered component of type NWGA or 
 NWGB. 
 
 4.2.2 
 
 Algorithm 
 
 Since we have two initial solutions (AND gate 1 and OR gate l), we 
 apply the branch- and-bound algorithm twice to enumerate all feasible 
 
86 
 
 solutions. The algorithm is the same as that explained in section 2.2, 
 except that we start with the best known C at BB-step for the second 
 initial solution. 
 
 (i) The heuristics for the selection criterion of uncovered components 
 (SCUC) and the implementation priority of possible covers (IPPC) 
 are as follows; 
 
 The SCUC 
 
 Select an uncovered component which has the fewest possible covers. 
 In the case where there are two or more such uncovered components, 
 select one of the least desirable type. 
 
 The IPPC 
 
 Implement the possible covers of the selected uncovered component 
 
 according to the desirability order 
 
 G*A - VC* - GC*A - G*G*A - G*B - GC*B - G*C*B - NWGA - NWGB. 
 (The possible covers of type G*A are assigned the highest priority. ) 
 
 (ii) The cost lower bound, C , for a possible cover is calculated by the 
 following formula. (The C is compared with the cost ceiling C, and 
 only those possible covers whose C's are less than or equal to the 
 C are accepted at BB-step 2. ) 
 
 Let gate k denote a gate one of whose uncovered components we 
 are going to cover with a possible cover pc. First we calculate 
 c , c , c , d and e as follows; 
 
 c = the number of gates (excluding gate k) whose types are 
 COV or G*X, and which have only one input connection. 
 
87 
 
 c = the number of gates (excluding gate k) whose types are 
 VC*, GC*X, G*C*X or NWGX, and which have no input con- 
 nections yet. 
 
 c = the number of gates (excluding gate k) whose types are 
 VC*, GC*X, G*C*X or NWGX, and which have only one input 
 connection. 
 
 r 
 
 * = < 
 
 ^ 
 
 0, if the type of the pc is G*X, and gate k has two or more 
 input connections. 
 
 1, if either the type of the pc is G*X, and gate k has only- 
 one input connection, or the type of the pc is one of 
 VC*, GC*X or G*C*S , and gate k has one or more input 
 connections. 
 
 2, if the type of the pc is one of VC*, GC*X or G*C*X , and 
 gate k has no input connection yet, 
 
 3, if the type of the pc is NWGX , and gate k has input con- 
 nections, 
 
 k, if the type of the pc is NWGX , and gate k has no input 
 connection yet. 
 
 e = 
 
 1, if type of the pc is NWGX 
 0, otherwise. 
 
 By using the above values c,, c , c , d and e, C is given by 
 C = C + AC, where C is the cost of the given intermediate solution S, 
 and AC = A x e + B x (c + 2c + c + d). (A and B are the weights 
 of the cost function. ) 
 
88 
 
 (iii) By backtracking, we reconstruct an intermediate solution S K at BB- 
 
 step k. Before we implement the next possible cover for the un- 
 covered component P corresponding to S„, we impose the following 
 
 restriction on S and on all succeeding intermediate solutions. The 
 K 
 
 idea is a modification of that explained in section 2.3.5* 
 
 Let pc denote the possible cover which was implemented last. 
 
 a) if the pc is gate i of type G*A or G*B, then set P. =0 if 
 gate k is OR, or set P. =1 if gate is AND. 
 
 b) if the pc is an external variable x, or x*, or gate i of 
 type GC*A, GC*B, then prohibit the pc from being connected 
 to gate k. 
 
 Comparison of the Heuristics of Assigning Modes to New Gates in 
 The Two Methods 
 
 In the IE-method, the variables K represent the modes of gates. 
 
 JK 
 
 We set K to (representing AND), or to 1 (representing OR), using the 
 
 rule explained in Phase II of section U.1.2, when we first connect gate 
 k to the partial network S as a new gate. At the time of backtracking, 
 we set the K to the opposite value, thus we enumerate the network in 
 which gate k is either AND or OR. 
 
 In the BB-method, we assume every uncovered component has two new 
 gate possible covers, type NWGA and type NWGB. The type NWGA possible 
 cover is a new gate whose mode is different from the mode of the gate k 
 to which the new gate is going to be connected, and the type NWGB pos- 
 sible cover has the same mode as the gate k. 
 
89 
 
 Since type NWGA possible covers are implemented prior to type NWGB 
 according to the IPPC, the schemes of assigning modes to new gates by 
 the IE-method and the BB-method are identical. 
 
 ^-.3 The Programming Aspect and the Computation Time 
 
 Liu et al. , obtained the optimal AND-OR network for a one-bit adder 
 by the IE-method [17]. The size of the program is about the same as the 
 one for the NOR problem, since they rewrote only the subroutine which con- 
 tains the fixing scheme of free variables according to the heuristics for 
 the AND-OR problem. This subroutine consists of about 160 FORTRAN state- 
 ments, which are translated into 2.k K bytes of machine instructions. 
 
 Nakagawa coded a FORTRAN program of the branch-and-bound method for 
 the AND-OR problem [23, 26]. The program consists of about 27OO FORTRAN 
 statements which are translated into 62 K bytes of machine instructions. 
 
 The memory requirements and the computation time for the problem of 
 the optimal AND-OR network for a one-bit adder are shown in Tables k.l 
 and k.2. 
 
 
 ( 
 
 COMPUTER PROGRAM (IBM 360/75) 
 
 The Implicit Enumeration 
 Method (the IE-method) 
 
 The Branch-And- Bound 
 Method ( the BB-method) 
 
 Size of machine 
 instructions 
 
 ^0 K bytes 
 
 62 K bytes 
 
 Working Storage 
 for one-bit adder 
 (a 9-gate network 
 of 3 variables) 
 
 105 K bytes 
 
 8 K bytes 
 
 TABLE k.l The memory requirements for the computer programs of the 
 two methods. 
 
90 
 
 
 > - " ' ■ ■- ■ '■ - ■ ■ .. ■ i-.- .i . ■ M .. .... .... . i — .. 
 
 COMPUTER PROGRAM (IBM 360/75) 
 
 the IE-method 
 
 the BB-method 
 
 Computation 
 time for a 
 one-bit adder 
 
 102 minutes 
 
 6 minutes 15 seconds 
 
 TABLE k.2 The computation time for the optimal AND-OR network by 
 the two methods. 
 
 The amount of programming effort required to adapt to a problem of 
 different types of gates (i.e., AND and OR gates) is shown in Table 3«^ (b) 
 for the two methods, after the programmers have already experienced pro- 
 gramming the problem of another type of gate (NOR gates). As was ex- 
 plained there, the programming effort required for the IE-method is only 
 the rewriting of two small programs, namely a subroutine FIX J for fixing 
 free variables, and a program which generates the inequalities; but the 
 programming effort for the BB-method is almost a complete rewriting of 
 the NOR program. The major part of rewriting the program of the BB- 
 method consists of the subroutine which generates augmented intermediate 
 solutions by implementing possible covers, and the subroutine which selects 
 uncovered components according to the SCUC. Besides those, many additional 
 changes are required throughout the entire program due to the AND-OR prob- 
 lem having two different modes AND and OR, instead a single mode, NOR. 
 
 In the IE-method, the memory space for machine instructions remains the 
 same. In the BB-method, the increase in the memory space for the AND-OR pro- 
 blem over the NOR problem is slight. 
 
91 
 
 REFERENCES 
 
 1. E. Balas, "An additive algorithm for solving linear problems with 
 zero-one variables," Operations Research , vol. 13, no. k, pp. 517- 
 5^9, July-August 1965. 
 
 2. C. R. Baugh, T. Ibaraki, T. K. Liu and S. Muroga, "Optimum network 
 design using NOR and NOR-AND gates by integer programming," Report 
 No. 293, Department of Computer Science, University of Illinois, 
 January 19&9* 
 
 3. M. L. Balinski, "Integer Programming: Methods, Uses, Computation," 
 Management Science , vol. 12, no. 3, PP« 253-313, November I965. 
 
 k. C. S. Chandersekaran, "Synthesis of optimal double- rail logic net- 
 works using NOR-OR gates by integer programming," Report no. 38^-, 
 Department of Computer Science, University of Illinois, February 
 1970. 
 
 5. J. N. Culliney, "On the synthesis by integer programming of optimal 
 NOR gate networks for four variable switching functions," Master 
 thesis, Department of Computer Science, University of Illinois 1971* 
 
 6. E. S. Davidson, "An algorithm for NAND decomposition of combinational 
 systems," Ph.D dissertation, Department of Electrical Engineering 
 and Coordinated Science Laboratory, University of Illinois, I968. 
 
 7. B. Fleischman, "Computational experience with the algorithm of Balas," 
 Operations Research , vol. 15, no. 1, pp. 153-155, January-February 
 1967. 
 
 8. A. M. Geoffrion, "Integer programming by implicit enumeration and 
 Balas' method," SIAM Review , vol. 9, no. 2, pp. I78-I9O, April I967. 
 
92 
 
 REFERENCES 
 
 9. F. Glover, "A multiphase -dual algorithm for the zero-one integer 
 
 programming problem," Operations Research , vol. 13, no. 6, pp. 879- 
 919, November- Dec ember 1965. 
 
 10. S. W. Golomb and L. D. Baumert, "Backtrack programming," Journal of 
 the Association for Computer Machinery , vol. 12, no. k, pp. 516-52^, 
 October 1965. 
 
 11. L. Hellerman, "A catalog of three-variable OR- invert AND- invert 
 logical circuits," IEEETEC , vol. EC-12, no. 3, pp. 198-223, June 1963. 
 
 12. T. Ibaraki, T. K. Liu, C. R. Baugh and S. Muroga, "Implicit enumeration 
 program for zero-one integer programming," Report No. 305, Department 
 of Computer Science, University of Illinois, January I969. 
 
 13. T. Ibaraki, T. K. Liu, D. Djachan and S. Muroga, "Synthesis of optimal 
 Networks with NOR and NAND gates by integer programming, " Report No. 
 ^27, Department of Computer Science, University of Illinois, January 
 1971. 
 
 Ik. N. Lkeno, A Hashimoto and K. Naito, "A table of four- variable minimal 
 NAND circuits, Extra Issue No. 26, 1968, Electrical Communication 
 Laboratory Techinical Journal, Nippon Telegraph and Telephone Public 
 Corporation, Tokyo, Japan. 
 
 15. P. L. Ivanescu and S. Rudeanu, "Psendo- Boolean methods for bivalent 
 programming," Lecture Notes in Mathematics, Vol. 23, Springer- Verlag, 
 Berlin-Heidelliey - N.Y. , 1966. Also, Operations Research, March- 
 April, I969, pp. 233-261. 
 
 16. T. K. Liu, "A code for zero-one integer linear programming by impli- 
 cit enumeration," Report No. 302, Master thesis, Department of Com- 
 puter Science, University of Illinois, 1968. 
 
93 
 
 REFERENCES 
 
 17. T. K. Liu, L. H. Shiau and S. Muroga, "Optimal networks with different 
 types of gates for a one-bit full adder/' Report to appear, Department 
 of Computer Science, University of Illinois. 
 
 18. S. Muroga and R. Ibaraki, "Logical design of an optimum network by 
 integer linear programming - Part I," Report No. 26k, Department 
 of Computer Science, University of Illinois, July 1968. 
 
 19. S. Muroga and T. Ibaraki, "Logical design of an optimum network by 
 integer linear programming - Part II," Report No. 289, Department 
 of Computer Science, University of Illinois, December 1968. 
 
 20. S. Muroga, "Logical design of optimal digital networks by integer 
 programming," in book Advances in Information Systems Science, Vol. 3 
 edited by J. T. Tou, Plenum Press, 1970, pp. 283-3^8. 
 
 21. T. Nakagawa and S. Muroga, "Exposition of Davidson's Thesis 'An 
 algorithm for NAND decomposition of combinational switching systems'," 
 Department of Computer Science, University of Illinois. 
 
 22. T. Nakagawa and H. C. Lai, "A branch- and-bound algorithm for optimal 
 NOR networks (the algorithm description)", Report No. ^38, Department 
 of Computer Science, University of Illinois. 
 
 23. T. Nakagawa, "A branch- and-bound algorithm for optimal AND-OR networks 
 (the algorithm description)," Report to appear, Department of Computer 
 Science, University of Illinois. 
 
 2k. T. Nakagawa, H. C. Lai and S. Muroga, "Pruning and branching methods 
 
 for designing optimal networks by the branch- and-bound method," Report 
 to appear, Department of Computer Science, University of Illinois. 
 
9U 
 
 REFERENCES 
 
 25. T. Nakagawa and H. C. Lai, "Reference manual of FORTRAN program 
 ILLOD-(NOR-B) for optimal NOR networks," Report to appear, Department 
 of Computer Science, University of Illinois. 
 
 26. T. Nakagawa, "Reference manual of FORTRAN program ILLOD-(AND-OR-B) 
 for optimal AND-OR networks," Report to appear, Department of 
 Computer Science, University of Illinois. 
 
 27. R. S. Swee, "Optimum network design using NOR-OR gates by integer 
 programming," Report No. 375* Department of Computer Science, 
 University of Illinois, February 1970* 
 
 28. S. Woiler, "Implicit enumeration algorithm for discrete optimization 
 problem," Report No. k, Department of Industrial Engineering, 
 Stanford University, May I967. 
 
 29. S. Zionts, "Implicit enumeration using bounds on variables: A 
 generalization of Balas' additive algorithm for solving linear pro- 
 grams with zero-one variables," Working Paper No. "J, School of 
 Business Administration, State University of New York at Buffalo, 
 Buffalo, N. Y. , June 1968. 
 
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