Hi "4d! iff HH 1 1 I Mm m H&i mm am m HI Wi A illil HrM'i"' Wa : ■ ■Hi waif Hh H &? ■L LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 nc.734-739 cop 2 m*** Y «*.*. NOR NETWORK TRANSDUCTION BASED ON ERROR -COMPENSATION (Principles of NOR Network Transduction Programs NETTRA-E1, NETTRA-E2 and NETTRA-E3) by Y. Kambayashi H. C. Lai J. N. Culliney S . Muroga June 1975 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS Digitized by the Internet Archive in 2013 http://archive.org/details/nornetworktransd737kamb UIUCDCS-R-75-737 NOR NETWORK TRANSDUCTION BASED ON ERROR-COMPENSATION (Principles of NOR Network Transduction Programs NETTRA-E1, NETTRA-E2 and NETTRA-E3) by Y. Kambayashi H. C. Lai J. N. Culliney S. Muroga June 1975 Department of Computer Science University of Illinois at Urb ana- Champaign Urbana, Illinois 6l801 This work was supported in part by the National Science Foundation under Grant No. GJ-1;0221. Ill ABSTRACT As an extension of the concept of Compatible Sets of Permissible Functions (CSPF's) proposed in an earlier paper, the concept of Compatible Sets of Permissible Functions with Errors (CSPFE's) is introduced. CSPFE's are defined for gates and connections in a loop- free NOR-gate network whose actual (set of) output function(s) differs from the desired (set of) output function(s). Based on this concept, an "error-compensation" process is proposed which attempts to reconfigure the network, without employing additional gates, to realize the desired function(s). This process "compensates for" [i.e., corrects] "errors" [i.e., individual components of the (set of) actual output function(s) which differ from those desired] in the network's output (s) by "compensating for" error components in the CSPFE's of gates in the network, considered one at a time. Error- compensation is performed at each gate by removing redundant input connections of the gate, adding desirable connections to the gate, and/or replacing existing input connections of the gate with more desirable connections. In the latter two cases, functions which might be connected as new inputs are not restricted to external variables and those functions realized by gates in the network's current configuration. Also, new functions for this purpose can be created by adding new connections elsewhere in the network [in such a way as to cause no further errors to occur in components of the output function(s)] to constructively alter the function (s) produced by a certain (group of) gate(s). XV To utilize this err or- compensation process in reducing the number of gates in a given, non-optimal, loop-free NOR network, a gate is first removed from the network. The resultant network will either still realize the required function (s), in which case the number of gates in the network will have been successfully reduced, or errors will have been introduced into the realized function (s), in which case error- compensation will be attempted. If either the former case occurs or the latter case occurs and the error-compensation is successful, a second gate is removed and the process is repeated. This combination of gate removal and attempted error- compensation forms one type of transduction ( trans formation and re duction ) procedure for simplifying NOR networks. This particular type of transduction procedure is the most sophisticated of those developed in a series of reports of the authors' research group. NOR network transduction procedures based on error- compensation were implemented in the computer programs, NETTRA-E1, NETTRA-E2, and NETTRA-E3, whose principles are described in this report. V TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. ERROR- COMPENSATION AND CALCULATION OF COMPATIBLE SETS OF PERMISSIBLE FUNCTIONS WITH ERRORS 6 2.1 Basic Determination of CSPFE's 7 2.2 Error- Compensation During CSPFE Determination lk 2.2.1 Addition of a Connection 15 2.2.2 Removal of a Connection 21 2.3 Basic Transduction Procedure Using CSPFE's and Example 25 3. POTENTIAL OUTFJT TABLE 36 k. NETWORK TRANSDUCTION PROCEDURE USING CSPFE ' S ^9 k. 1 Selection of Gates to be Removed k-9 k.2 Selection of Gates for Error-Compensation 52 ^-.3 Error- Compensation Using a Potential Output Table 53 U.3.1 Classification and Compensation of Error- Components ^k 1+.3.2 Ordering of the Compensations for Different Types of Error- Components 56 ^-.3.3 A Procedure to Replace Inputs 60 k.k Addition of Functions Realized at Input Terminals 63 h. 5 The Calculation of CSPFE* s 63 h. 6 Recalculation 67 VI Page 5. COMPUTER PROGRAM IMPLEMENTATIONS AND EXPERIMENTS 69 5.1 Program Realizing Network Transduction Procedure Using Modified Error- Compensation (MEC ) 70 5.1.1 Selection of a Gate for Removal 70 5.1.2 Calculation of CSPFE's and Error-Compensation 71 5.2 Single- and Multi-Path Applications of Transduction Procedure 76 5.3 Network Transduction Examples 80 6. CONCLUSIONS 99 LIST OF REFERENCES 101 1. INTRODUCTION As an attractive alternative to time-consuming exhaustive or implicitly exhaustive computer programmed approaches to synthesizing optimal multiple -level, multiple- output, loop-free NOR networks, methods have been developed by the authors' research group at the University of Illinois which attempt to produce near- optimal networks in reasonable computation times. These methods involve, basically, synthesizing an initial network (which need not be close to optimal) and then trying to reduce the "cost" (defined in terms of numbers of gates and connections) of this network by altering its configuration. Several procedures, called "transduction procedures" (for trans formation and re duction ) have been developed and documented for the latter purpose. A succeeding report will discuss a NOR network design system which incorporates these transduction procedures with an option of several different procedures to synthesize the initial networks. The term "optimal, " when used to refer to NOR gate networks, can have several different meanings. Three of the more common meanings are: (l) the minimization of the number of gates; (2) the minimization of the number of gates as a primary objective and the minimization of the number of connections as a secondary objective; (3) the minimization of the number of connections as a primary objective and the minimization of the number of gates as a secondary objective. The design system' based on transduction procedures tries to achieve near-optimal networks in the sense of (2) [however, among the individual procedures there are differences in their emphases in gate versus connection removal] . Of course, achieving near- optimal! ty in this sense also satisfies (l); and, furthermore, a near-optimal network of this type would perhaps be found to be a near- optimal network under the criteria of (3) as well. Of this collection of transduction procedures which has been developed, the procedures based on "error- compensation" are the most sophisticated and, in general, the most powerful for the purpose of reducing the number of gates in a network. It is the purpose of this report to explain error- compensation and to describe the principles of the computer program implementations, NETTFA-El, NETTRA-E2, and NETTPA-E3, of the resultant transduction procedures. A full description of the process of error-compensation requires, first of all, a knowledge of the concept of Compatible Sets of Permissible Functions with Errors (CSPFE's), defined with respect to the actual and desired (set of) output function(s), for gates and connections in a NOR-gate network. The concept of CSPFE's, which will be introduced in Section 2, is an extension of the concept of Compatible Sets of Permissible Functions (CSPF's) proposed in [6]. Error-compensation is a process which attempts to reconfigure a network in which the actual (set of) function(s) realized differs from a desired (set of) output function(s). If successful, the reconfigured network, having no more gates than the original, will realize the desired function(s). This process "compensates for" (i.e., corrects) "errors" [i.e., individual components of the (set of) actual output function(s) which differ from those desired] in the network's output (s) by "compensating for" error-components in the CSPFE's of gates in the network, considered one at a time. Error- compensation is performed at each gate by removing redundant input connections of the gate, adding desirable connections to the gate, and/or replacing existing input connections of the gate with more desirable connections. In the latter two cases, functions which might be connected as new inputs are not restricted to external variables and those functions realized by gates in the network's current configuration. Also, new functions for this purpose can be created by adding new connections elsewhere in the network [in such a way as to cause no further errors to occur in components of the output function(s)] to constructively alter the function(s) produced by a certain (group of) gate(s). In order to expedite the search through such currently nonexistent, but employable, functions to find those useful as new inputs, an updated table is kept which lists both potential functions and the network configuration changes required to produce them. The structure and maintenance of this table, called "POT" (for Potential Output Table), will be discussed in Section 3. To utilize error- compensation in reducing the number of gates in a given, non-optimal NOR network, a gate is first removed from the network. The resultant network will either still realize the required function(s), in which case the number of gates in the network will have been successfully reduced, or errors will have been introduced into the realized function(s), in which case error-compensation will be attempted. If either the former case occurs or the latter case occurs and the error-compensation is successful, a second gate is removed and the process is repeated. Section k will detail the basic transduction procedure formed by this combination of gate removal and attempted error-compensation, while the three actual program implementations (NETTRA-E1, -E2, and -E3) will be discussed in Section 5. The difference between network transduction based on error-compensation and the transduction procedures based on other principles, detailed previously i- n [^],[5]> an d [1-0] can 1 ° e explained intuitively as follows. In moving from an initial network to a final, reduced network (i.e., a network of less cost; a network of fewer gates or of the same number of gates with fewer connections) the previous transduction procedures must follow a "chain" of "correct" networks [i.e., networks realizing the correct function(s)] — each network differing only slightly from the preceding one in the "chain" (and not necessarily being of less cost). From one network to the next in the chain, only a relatively small number of connections are added, deleted, or exchanged in relatively localized portions of the network. In contrast to this, transduction using error-compensation is not restricted to following such chains of closely related "correct" networks. In fact, in going from one "correct" network to the next reduced correct network, this type of transduction can be thought of as normally following a "chain" of "networks with errors" (i.e., networks which do not realize the correct functions). It should also be noted that transduction based on error-compensation need not even start from a "correct" network. So the "leap" (in terms of the magnitude of change in the network configuration) from one correct network to the next may include much more complex changes affecting a much greater portion of the network than the (relatively) "small step" taken from one correct network to the next by transduction procedures not based on error- compensation. The obvious advantage for procedures based on error- compensation Is in cases where no chain of closely related correct networks can be found leading from a particular correct network to any corresponding correct network of fewer gates. Naturally, since different types of transduction procedures consider different types of network reconfiguration, a generally weaker, less sophisticated transduction procedure may he more successful than a generally stronger, more sophisticated procedure in reducing certain given networks. While no transduction procedure which has been developed can always give better results than the other procedures (starting from the same initial networks), experiments have shown network transduction based on error- compensation to be, generally, significantly superior to the other types of network transduction in producing networks of fewer numbers of gates. However, just as the transduction methods offer fast alternatives to the more powerful, but more time consuming, exhaustive or implicitly exhaustive methods, the transduction procedures not based on error-compensation offer a faster, though generally less powerful, alternative to transduction based on error-compensation. Thus the NOR network designer is presented with a full range of network design programs from which to choose based on his own particular requirements (expenditures vs. degree of network cost reduction). A familiarity with the definitions, concepts, and procedures presented in [6] will be assumed in the following sections. 6 2. ERROR- COMPENSATION AND CALCULATION OF COMPATIBLE SETS OF PERMISSIBLE FUNCTIONS WITH ERRORS In this section, the concept of CSPFE's (Compatible Sets of Permissible Functions with Errors) is introduced, and its function in error- compensation is demonstrated. Although the concept is an extension of the concept of CSPF's, there are important differences in the manner of employment of CSPFE's and CSPF's. CSPFE's and CSPF's are both defined for gates and connections in a network, but, while CSPF's [defined only with respect to the actual (set of) output function(s) of a network] are defined for any network, CSPFE's are defined only for networks in which the (set of) actual output function(s) differs from a desired (set of) output function(s). Also, while for some transduction procedures employing CSPF's it was found useful to calculate the CSPF's for the entire network before attempting to transform and reduce the network, transduction based on error- compensation works intimately with the calculation of CSPFE's--both processes being carried on simultaneously. It is due to this practical inseparability of the calculation of CSPFE's from the error- compensation process that the calculation of CSPFE's is described in this section in its role as an integral part of error-compensation. Following the development of error-compensation and CSPFE calculation, a basic transduction procedure based on CSPFE's is given. An example (Example 2.3.1) is then presented to illustrate the operation of the fundamental procedure in preparation for the more advanced procedure explained in Section k. 2.1 Basic Determination of CSPFE's Each CSPFE is represented by a 2-dimensional vector whose components may be O's, l's, *'s, O's, or l's. While O's, l's, and *'s have the same meanings as defined for CSPF's, and 1 are newly introduced for CSPFE's. The underline in the and 1 symbol indicates that the value of this component is perferably changed to a 1 or 0, respectively. Such a component is said to he an "error" component. The vector representing the CSPFE for a gate, input terminal, or output terminal, v., is denoted by G_(v. ). 1 El G_(c. .) denotes the vector representing the CSPFE for a connection c. . (i.e., the connection from v. to v.). For simplicity, G_(v. ) and G„(c. .) i 3 E l E ij are sometimes referred to as "CSPFE vectors." Let z , z p , ..., z denote the set of output functions required of a network. Let z', z', ..., z' be the set of actual outputs of a given network which incorrectly realizes at least one of the required functions (z. is assumed to correspond to z!). (The derivation of such a network for the purpose of transduction by error-compensation is explained as part of the basic procedure. ) Before the CSPFE's are calculated for the gates and connections of the given network, the components of the CSPFE vectors for the output terminals are determined by a comparison of the actual outputs of the network z', z', ..., z f with the required outputs z , z , ..., z . (Note that the z. 1 , determined by the network's configuration, are always completely specified with respect to the external variables, while the z., determined by the designer, may be either completely or incompletely specified. ) More specifically, the components of the vectors representing CSPFE's for the output terminals are determined as follows. th For the d input combination to the network (i.e., (x.., Xp, ..., x ) where 2 x, + 2 "'" x~ + . .. + X +1 = d), the corresponding d component, G^ '(v. ), of the CSPFE vector for output terminal v., i = n + R + 1, n + R + 2, ..., n t- R + m, is: i if z< d > . z: (d ) - i 1 1 1 if zf d ) = and z!^ = 1 — l i o if z. (d) = z: (d) = o i i if z.( d ) = 1 and z.'^ = — i i * if z. (d) = *. i After this initialization is complete, the CSPFE's are determined for the c. . and remaining v. (i = 1, 2, ..., n+R; j = n+1, n+2, ..., n+R+m) as follows. (A), (b), and (C) explain the determination of G (c), for E Ji every j such that v. e IP(v. ), given G {v.); and (D) explains the 3 l Ei determination of G„(v. ) given G_(c. .) for every j such that v. e IS(v. ). E 1 E 1J J ' 1 (A) For G.1 (v.) = 1. In this case, the d components ill 1 — of all of the inputs to v. are currently (since f^ (v.) = 1, this must he true). If at least one of them could be changed to a 1, then f(v.) would change As in [6], external variables are assumed to be available in uncomplemented form only, in order to simplify the discussion. Hence p=n (see [6]). IP(v. ) and IS (v. ), as defined in [6], represent the set of immediate predecessors and the set of immediate successors, respectively, of the gate or terminal v. . l to 0, and the "error" (G^ (v.) = l) would be compensated. Since it is not known at this point which particular th input is easier to change to a 1, the d components of the CSPFE vectors for all the input connections, c... to v. are considered to be errors which are propagated through v., i.e., Gj, (c) = is specified for every v. e IP(v. ). JL Jl — ■ J 1 This is shown in Figure 2.1.1(a) (note the possibility that certain v. may be input terminals or v. may be an output terminal). (B) For G-i (v.) = 0. In this case, the d component of Jii i — at least one input to v. is 1 (since f (v. ) = 0, there must exist a v. such that v. e IP(v. ) and f^ (v.) = l). 3 3 i J If all the inputs which are l's could be changed to 0's, the output of v. would change to 1, and the error would be compensated. Thus, these inputs are regarded as errors which are propagated through gate v. . As it is desirable to compensate for the error of the output of v., other inputs th should remain for the d component. Thus, G.A (c) =1 is specified for every v. e IP(v. ) such that f^( v .) = 1, J G), (c . . ) = is specified for every v. e IP(v. ) such that f^(v.) = 0. J This relation is shown in Figure 2.1.1(b). 10 v c . . v. (a) (b) Figure 2.1.1 Propagation of Errors in CSPFE Vector Components 11 (C) For G^, (v.) = 0, 1, or *. For these three cases, the same calculation method as discussed in [6] for the calculation of CSPF's is used: for G^(v. ) = 0, one G^^v.), such that v. e IP(v. ) and fW(v.)-l,l. selected and required to be lj for Gi d ^(v. ) = 1, all G; d ^(v.) such that v. e IP(v. ) Jjj i E j j i are required to he 0; for Gj, (v. ) = *, no requirements are made of the immediate predecessors of v. . (D) After CSPFE's for all the output connections of gate or input terminal v. have been calculated, the CSPFE for v. itself is obtained by the relation: v.elSlv. ) ° J i which is developed in the following. First let the operation A be defined between two components of two respective CSPFE's. Definition 2.1.1 The binary operation A is defined by Table 2.1.1. Note that the operation A is both commutative and associative. The CSPFE vector for a gate or input terminal v. , i.e., G_(v. ), is calculated based on the operation A and E 1 the CSPFE vectors for all the output connections of v. , i.e., G Tn (c. . ) *s for every v. e IS (v. ). E v ij J j i' Table 2.1.1 The Operation L. Second Element 12 First Element A -x- 1 1 * 1 1 * 1 1 1 1 1 - 1 - - - 1 1 1 - 1 - - - ("-" indicates -undefined) 13 Definition 2.1.2 The CSPFE vector for a gate or input terminal v. is calculated by taking A operations among the CSPFE vectors of all the output connections of v., i.e., G E ( V " A G E (C ), v eIS(v i ) where the A operation between two vectors results in a vector obtained by taking A operations between the corresponding components, and the A operation among more than two vectors can be taken in any order. The meaning of these definitions can be demonstrated more clearly by a discussion of the following example. Consider a case where c. . and c. are the only output connections from v., i.e., IS (v.) = {v., v. 1 . There are i i l y k J the following possible combinations of G^, (c. .) and GJ; (c. ): iii ij hi iK (a) Either ^(c^) or G^ d) (c. k ) is *. For example, suppose G^ ( c ± i) = * and G g ( C ±]J = 2" In this case, Gj, (v. ) should be since * means that 7 E l — either or 1 is permissible with respect to c. . and means that f (v. ) =1 is preferred with respect to c ik . Therefore, when <4 ( c ij) = * > ^^V = G E (c W' The A operation gives this result. (b) G^(c. .) and G^lc, ) are equal. E ij E lk fd ) Obviously, Gj, (v.) should have the same value as hi l i GJ; (c. .) and Gj, (c, ) in this case. The A operation E i j E ik is consistent with this observation. 14 Only two combinations are possible, i.e., (1>1) and (c) G; } (c. .) / G; ^(c. ) and neither is *. E i,i ' E lk (0,0). All other combinations cannot exist. For example, the combination Gj, (c. .) = and G„ (c. ) = 1 * ' E lj E ik y — cannot occur since G_ (c .) = implies f (v.) = 0, E ij' * i' ' and Gj, (c., ) = 1 implies f (v.) = 1 which cannot be E lk — * v i' simultaneously satisfied. When G^ d) (c ±j ) = and G^^ik' = 2» ^ (\) COuld be either or 0. However, if were chosen and later compensated to 1 (implying a change in f (v.) from the value to the value l), then a new error would have been introduced in c. ., since Gj, (c. . ) = 0. In order ij E ij to avoid the introduction of such new error components, G-A (v.) =0 is chosen. Similarly, for the combination & i (l, l), GJ, (v.) =1 is chosen. Again, the A operation is consistent with these choices. Following the initialization consisting of the determination of CSPFE vectors for the output terminals, CSPFE' s can be calculated for all gates, input terminals, and connections throughout the network by repeated applications of (A)-(D). During this calculation, let errors be compensated by the means described in the following section. 2.2 Error-Compensation During CSPFE Determination The following two subsections, 2.2.1 and 2.2.2, introduce two basic methods of error- compensation, respectively, simple addition and removal 15 of connections (more sophisticated methods will be discussed in Section k). The calculation of CSPFE's ((A)-(D) of the previous section) and the compensation of errors (Sections 2.2.1 and 2.2.2) provide the basis for the basic transduction procedure in Section 2.3. 2.2.1 Addition of a Connection If the d component of G„(v. ) is 1, as shown in Figure 2.2.1.1(a), ii 1 — this error can be compensated by adding one input connection from a gate (or input terminal), v., realizing a function whose d component is 1 j (see Figure 2.2.1.1(b)). Whenever an error component G.1 (v.) = 1 of a it, x — CSPFE vector is compensated in this manner, it immediately changes value to Gj, (v.) =0 as the new input is connected. This function, however, must be "E-connectable" (defined in the following) in order not to change the "correct components" of the output of v. (i.e., components of f (v. ) for which the corresponding components of G_(v. ) are 0, 1, or *). iii i Definition 2.2.1.1 Function f is said to be E-connectable to gate v. with respect to G„(v. ) if and only if the function realized by v. is in set G after connecting f as an input to v. , where G is the set of functions represented by substituting * for every and 1 component in G E (v i>- Definition 2.2.1.1 only gives a necessary condition under which a function can be connected to a gate as an input without increasing the number of error- components in the CSPFE vector of that gate. Adding such a connection to a gate may or may not compensate for errors in the CSPFE vector' of the gate. For a network obtained as stated in Definition 2.2.1.1, components which are *'s in the vector representation of G may be or 1 Si^ S M '"i' = 1 (a) v „(d)/ v , newly added j i^-^ connection f (d) (v.) 1 w c new values (b) Figure 2.2.1.1 Addition of a Connection L6 17 in the new f (v. ). If there is such a f (v. ) = for which the corresponding component in G- C ,(v. ) is originally 1, the error for this component is h i — compensated. If there is a 1 instead, it is still -uncorrected. A Gj, (v.) which is originally cannot be compensated by the addition of input connections, although it can possibly be compensated by removing input connections (see Figure 2.2.1.3). Theorem 2.2.1.1 Function f is E-connectable to v. with respect to G„(v. ) if and only if E l f< d > - ( d ) for every d such that G~ (v.) = 1. Let K(v. ) be the set of all functions defined by lO d '(v. ) = for all d such that Gi, d ^(v. ) = 1, i E i K^(v. ) = * for all other d (i.e., G^ d ^(v. ) = 0, 0, 1, or *). Then K(v. ) is the set of all functions E-connectable to v. with i l respect to G„(v. ). The function which is constantly is always E-connectable to any gate. To avoid this trivial situation, the following concept is introduced. Definition 2.2.1.2 A function f is effectively E-connectable to v. with respect to G (v . ) if and only if: (1) it is E-connectable to v. with respect to G T? (v. ), and (2) there exists at least one d for which: (2-1) f (d) = 1 and G^ d) (v. ) = or ili 1 (2-2) f(d) =1 and G ( d )( v .) = !. ili 1 — lfl If there exists a function f and a d satisfying condition (2-2), the 1 error in v. can be compensated by adding the effectively E-connectable function f as an input to v. . Definition 2.2.1.3 A gate or input terminal v. is E-connectable J (or effectively E-connectable) to gate v with respect to G„(v. ) if and i ^ i only if : (1) f(v.) is E-connectable (or effectively E-connectable) to v. with respect to G„(v.) and (2) the network obtained after connecting v. to v. is loop-free. In choosing connections to be added to compensate for errors, there is a special case which should be noted. When IS(v.) 3 IS(v. ), even if v. is effectively E-connectable to v., the connection of v. to v. does not i j i reduce errors of the network. This is exemplified by the following. Assume that there exist v. and v. satisfying: (a) IS (v.) 3 IS(v ), J -*- (b) G^O = 1, and f (d) (v.) = 1. Then there exists a gate v. in IS (v. ) such that: k i (c) 4 d)(c ik } = h i- e - G E d)(v k } = 2> aja6L (d) v k e IS (v..), as shown in Figure 2.2.1.2(a). Since f (v.) = 1, the addition of a connection from v. to v. 3 J i causes the output of v. to become 0. At the same time, this causes l Gj, (v.) to become 0. This, in turn, can force GJ; (c . . ) = 1. resulting, hi l iii j l through the A operation, in G^ (v.) =1 (see Fig. 2.2.1.2(b)). Thus f^ '(v.) & J 3 (d) would remain unchanged, f ( v t,) would still be 0, and the error component 19 f (d) (v.) = 1 3 -^ v. -U_J> G ( d ) (v .) = i E ^ Gi d) (v ) = v. (a) 1 v. v f (d) (v.) = 1 f (d) (v k ) = V. ' f (d) (v.) =0 l 00 Figure 2.2.1.2 Prohibited Connection Addition for Error- Compensation 20 Gi (v, ) = would not only remain unchanged but also would have become iii K. ~~ uncompensable (due to G.1 (v.) = f (v.) = l). E 3 3 Therefore, even if v. is effectively E-connectable to v., such a J i connection must be avoided. The following definition is introduced for this purpose. Definition 2.2.1.U Gate or input terminal v. is strongly effectively E-connectable to gate v . with respect to G-(v . ) if and only if: (1) v. is effectively E-connectable to v. with respect to G_(v. ) and E i (2) is(v ) £ IS(v ). It should be observed that condition (a) above is only a sufficient condition for the connection of v. to v. to be useless in reducing the number of errors in the network even though v. is effectively E-connectable J to v.. Note that when condition (a) above is replaced by IS(v.) D IS(v. ) fi f) J. J X (a necessary condition for the situation shown in Figure 2.2.1.2 to occur), although it is still possible that there exists such a gate v in IS (v. ) satisfying (c) and (d) above (in which case, connecting v. to v. would create at least one uncompensable error), it is also possible that there exist one or more gates, v., in IS (v. ) - IS(v.) for which there are one or Jo l j more values of d such that the following are satisfied: (e) G^ d) (v.) = 1 and f (d) (v.) = 1 hi i — j (f) GJj, d) ( Cii ) = 1, i.e., G^v^) =0. In such a case, it is possible that the addition of a connection from v. to v. could eliminate more errors than it would make uncompensable. So such cases are not excluded in the definition of strong effective E-connectability. 21 2.2.2 Removal of a Connection If the d component of GL(v. ) is 0, there are one or more inputs to v. whose d components are 1. This error- component could be compensated by removing all such inputs from gate v. (see Figure 2.2.2.1). Whenever an error- component Gj, (v. ) = of a CSPFE vector is compensated for in this Xj 1 — ( d ) manner, it immediately changes value to Gj, '(v. ) = 1 as the appropriate inputs are disconnected. These disconnected functions, however, must satisfy the condition stated in the following definition in order that their removal does not change correct components in the output of v. . Definition 2.2.2-1 A gate or input terminal v. is said to be E-disconnectable from gate v . with respect to G„(v . ) if and only if the output function, f (v. ), of v. is in set G after removing input v. from v., where G is the set of functions represented by substituting *'s for l's and 0's in G„(v. ). — — Ei Theorem 2.2.2.1 A gate or input terminal v. is E-disconnectable J from gate v. with respect to G„(v. ) if and only if there exists no d such i xLi i that: V f(v) (d) = 0, veIP(v. ) v/v. r f(v.) (d) - 1, and f (d) (v. ) : J i f (d) (v k ) f (d) K ) = 1 1 = (a) ^(v.) =0 f (d) (v k ) f (d) ^) new values) <4 d) (v,) - 1 Y i'>'(v.) 1 (b) Figure 2.2.2.1 Removal of Connections 23 The proof is obvious from Table 2.2.2J. which shows all possible combinations of G^^v. ), f^(v,), and V f '(v) for which v. is E- E x j veIP(v.) J disconnect able from v.. Note that the combinations of Table 2.2.2.1 together with that combination excluded in Theorem 2.2.2.1 exhaust all possibilities. If there exists a d satisfying combination (f), then a disconnection of v. would result in compensation for the error of G_(v.). Combination (g) is a case where the disconnection of input function f(v. ) from v. would reduce the num- ber of l's covering the and, therefore, make compensation for this easier in later steps. For all other combinations, the removal of connection c.. would not affect the d component of the output, f (v. ), of v.. While two or more inputs to v may be individually E-disconnectable, their simultaneous removal could result in the creation of errors in previously correct components of f (v. ). As an example, consider a case in which two gates, v. and v , are both E-disconnectable from v. with J K 1 respect to G„(v. ) and where, for some d: G< d) (v.) = 0, f(v.) (d) = f(v, ) (d) = 1, and v f(v) (d) = 0. E x 3 k veIP(v.) v/v. ( d ) If both connections c. and c. . were simultaneously removed, f (v.) ji ki l ( ci ) would become 1 (and, hence, Gj, (v.) would become l). Thus, connections from E-disconnectable functions should be removed singly with E-disconnectability being reevaluated after each such removal. In this example, had either c. or c,. been removed, alone, the gate ji kx corresponding to the remaining connection, v or v., respectively, would k j no longer satisfy the definition of E-disconnectability from v. . 2k Table 2.2.2.1 E-Disconnectable Conditions 4%> . f (d) (v.) 3 V f (d) (v) veIP(v. ) i i v/v. , (a) * or 1 or 1 (b) 1 (c) 1 i (d) or 1 1 (e) 1 (f) 1 (g) 1 1 25 2.3 Basic Transduction Procedure Using CSPFE's and Example A basic network transduction procedure using CSPFE's may now be given as follows. Procedure BEG : (Basic Error-Compensation). (1) Derive a network N' by removing one gate, other than an output gate, from a given network N Q . (2) Calculate the output functions of N 1 . If some output functions are different from those of N ,"*" calculate all the CSPFE's for gates, input and output terminals, and connections (see (A)-(D) of Section 2.1). During this calculation, compensate for errors as possible by adding or removing connections using the strongly effectively E-connectable For simplicity, in the programming of the transduction procedures in this report, each z. realized at a particular output terminal of N Q is assumed to correspond with the output function z.' realized at the same terminal in N'. It should be noticed though that there is some advantage in not making this assumption (if one is willing to sacrifice the additional computation time involved). For example, it is possible that z. (of N ) = z! (of N' ) and z. = z.' while z = z' for all k / i or j. Although this would mean N 1 realizes the same functions as N_, the procedures, as programmed, would not recognize this fact and would perceive z.' and z! as output functions with errors. 1 J To take advantage of not assuming correspondence between each pair of z. and zf, it is not even necessary to have a case in which the output gates of N' realize z , z_, ..., z in a permutation of the order in which they were realized in N„. A full treatment would be a method of creating a correspondence (z. to z' , i = 1, 2, ..., m) which in same sense minimizes 1 K. 1 the "distance" between the z. and the z! . However, this would involve x 1 the testing of many correspondence combinations under a weighting scheme created to define the relative importance of minimi zing the number of "error-positions" (to be defined in Section h) vs. minimizing the actual number of error-components in the CSPFE vectors of the output terminals. condition and E-disconnectable condition. (3) A modified network N may be obtained after the calculation of step (2). If all output functions of U are the same as those of N n , terminate the procedure; otherwise, return to step (l) to attempt the removal of different gate from N n . In Step (2), suppose a CSPFE for v. has been already calculated. Then, even if v. is strongly effectively E-connectable to v., it is not J connected because the addition of such a connection would require a recalculation of CSPFE' s for v. and gates in P(v. ). 1 1 Procedure BEC is illustrated in the following example. Example 2.3.1 The network in Figure 2.3.1(a) realizes function *(= f(v 5 )) z = (1001 0111 1010 1100)/ and it consists of 10 gates and 22 connections (excluding the output connection from v ). If gate Vo is removed from this network, the network shown in Figure 2.3.1(b) results. The functions realized at input terminals and gates in this network (Figure 2.3.1(b)) are as follows: x = f(v ) = (0000 0000 1111 1111), x 2 = f(v 2 ) = (0000 1111 0000 1111), x = f(v ) = (0011 0011 0011 0011), x^ = f(v^) = (0101 0101 0101 0101), f(v^) = (1100 1100 1100 1100), f(v ) = (0011 0011 0000 0000), The d component of function z, z , is the d from the left in this representation of the function. Spaces are included for readability. 27 f( V;i2 ) = (nil oooo 1111 oooo), f(v ) = (1010 0000 1010 0000), f(v Q ) = (0000 1100 0000 1100), f(v ) = (0000 1000 0000 0000), f(v 6 ) = (0100 0000 0101 0011), z' = f( v _) = (1011 0111 1010 1100). 5 Only the 3 r component of f (v_) differs from that of z. The 3 r 5 components of functions realized at gates and input terminals are shown in Figure 2.3.1(b) beside the corresponding connections. Underlined values are regarded as errors. Let an attempt be made to compensate for the output error by adding or removing connections. As G £ (v ) = (1011 0111 1010 1100), f(vg) - (0100 0000 0101 0011), and f(v ) = (0000 1000 0000 0000), the set of E-connectable functions to v.. is represented by K(v ) = (0**0 *000 0*0* 00**). If a function f could be found such that f e K(v ) and f^ - 1, (3) then the error, Gj, j (v ) = 1, could be compensated for by adding such an input to v . However, there is no such function realized at other gates or input terminals of the network in Figure 2.3.1(b). Thus the error is allowed to propagate to the two inputs of v,_. The use of rules (A), (C), and (D) of Section 2.1 results in: G £ (v 6 ) = (0100 *000 0101 0011), G„(v r7 ) = (0*00 1000 0*0* 00**). & ( — 28 First consider Vs. Presently, v Q , v. n , and v_ are connected as inputs to v 6 . Since r 3 '(v ) = 0, r 3 )(v 10 ) = 1, and f' 3 '(v ) = 1, it is desirable to replace the two connections from v, n and v by new connections (3) in order to compensate for the error signified by G), {v/) = 0. The set of E-connectable functions to v,- is represented by K(v^) = (*0** **** *0*0 **00). In order to compensate for the error, a function f is required such that f e K(v 6 ) and f^ = 0. If it were possible to remove both connections c, n s and c,~ ^ by connecting functions satisfying this condition, the error would be compensated. Even if it were possible to remove only one of the two connections by this means, it would be desirable to do so since this might generally reduce the number of errors propagated in later steps. The functions realized by gates v„ and v satisfy the above condition. However, v cannot be used since it is already an input of v^-, and v cannot be used since it is neither strongly effectably E-connectable nor can it permit the removal of either c n ^ or c /-. Therefore, no additions or removals of connections are made, and the error is allowed to propagate further as follows (according to rules (B), (C), and (D) of Section 2.1): G E (v 9 ) = G E (c^ 6 ) = (*00* *1** *O*0 1100), G E (v 1Q ) = G E (c 1( ^ 6 ) = (101* **-** 1010 **00), and G^(c 10 ,) = (*011 **11 *0*0 **00). E 13^o — Next consider v . In this case it is found desirable to replace the two connections from v, p and v _„ by new connections in order to (3) compensate for the error indicated by Gj, (v„) = 0. The set of E-connectable ih f — functions to v is represented by K(v v ) = ( xxxx o**-* -x-x-x-x- -x-x-x-x-). 29 'Ik X 2-g> *l- 13 £> x. Xi.-/ 10 E> x i x k X 11 V, xl f(v 5 ) = z (a) Original network realizing function z. x 3-^ 5^1- V ^y^ 3H v *2 ^ - oi v io 13 v ^ V, V (b) Network after removal of gate Vn. Figure 2.3.1 Networks in Example 2.3.1 (c) Network after compensation of errors during first application of Procedure BEC. i htb v, >:.- V. 10 X 1 I r >»■ V x l 3 V (d) Network after removal of gate v,i in beginning of second application of Procedure BEC. Figure 2.3.1 (continued) Networks in Example 2.3.1 31 K3J 1 V Q N V< V V l_y^ G A^ I 1 . X X > 1 v io\ ( — / **z/ f (v 5 ) X 2- s — *\ ] ~> 1 )^o>- ' xji^> 1 5 > — ! i =KV- t3^ = z (e) Optimal, final network obtained after compensation of errors during second application of Procedure BEC. Figure 2.3.1 (continued) Networks in Example 2.3.1 As in the case for V/-, a function f is required such that f e K(v ) and t^' = 0. In the network, only f (v. ), f(v>), and f (v,-) satisfy this condition. Of these three, v, and v. are already inputs of v , and v^- is not strongly effectively E-connectable to v . Once again, the error in f(v ) is allowed to propagate to its input connections : G„(c n _) - (**0* O*** 1*1* 11**), E l, ( G (c. ) = (**01 01*1 **** ****), G^(c, _) = (1*1* 0*** **** ****), and E id, ( — G £ (c ) - (**1* 0*1* **** ****). Now consider v Q with its single output connection. As previously found, Gfv ) = (*00* *1** *0*0 1100). E 9 Since there are no error- components in G (v ), the CSPFE's for the input connections to v are simply determined to be: G T? (c _) = (**1* *0** ***1 0011) and E 5, y G^(c no _) = (*1** *0** *1** 00**). e id>y Next consider v, n --also with just a single output connection. As determined earlier, G^(v n J = (101* **** 1010 **00). E 10 - The corresponding set of E-connectable functions is represented by K(v ) = (0*** xxx x 0*0* ■**-**). It is found that f(v ~) is the only function f satisfying f e K(v ) and f ^ - i # However, since IS(v_„) 3 IS(v _), v, _ is not strongly effectively E-connectable to v, „, and no new input connections are added to v, n . 33 Before considering v^, G e^ v 12^ mus ' t be fir st calculated from G E ( °12,7 ) *** G E (C 12,9 ): G E (C 12, 7 ) AG E (C 12,9 } = GL(v, ) - (111* 00** *1** 00**). The set of E-connectable functions to v, ? is represented by K(v ) = (00** xxxx -x-o** **-x-x-) # (3) To compensate for the error indicated by Gj, (v, ) = 1, a function f satisfying f € KCv^) and f^ 3 ' = 1 is required. Both f(v~) and f(v ..-) are found to satisfy this condition, and both are further found to be strongly effectively E-connectable to v, p . As f(v_) > f(v,_) (i.e., every component of f(v„) is not smaller than the corresponding one of f(v,_), and at least one component of f(v_) is greater) f(v_) is selected to compensate for the error at v. p , and x is connected as an input to v-.p. Another reason to prefer v_ over v, ^ in compensating for this error (3) is that f (v __) - 1 is considered to be an error. Connecting v__ to v ~ (o) (o) (o) would mean changing the value of GJr'(v 10 ) (= G), (c, c) A G^ (c, _)) a -1-3 a -L3j D a -0> I (o) from 1 to 1, insuring f v y (v 1 „) = 1, and making both the error-components Gj, (v/0 = and G^ ' (v ) = uncompensable. Such considerations can be made in general. Since v_ is an input terminal and, therefore, contains no components considered to be errors, no such problem could arise from its connection. The addition of the new connection, c_ 12 , corrects the error- component Gp '(v-jp), but it cannot correct the error at v_ (G £ (v„) = 0) (3) since v, ^ is still connected to v„ and f (v,J = 1. 3h Immediately upon connection of the new input, the value of (3) Gp (v p ) is changed from 1 to 0. The new f(v,p) and G (v ~) are determined as : f(v ) = (1100 0000 1100 0000) and G T7 (v no ) = (110* 00** *1** 00**). E 12 The CSPFE's for the two input connections to v..p could be determined, hut since in this case both of the connections are from input terminals, this determination can be omitted. Gate v.. „ is next considered. From G„(c, A and G_(c no „), G T ,(v,„) 13 E' 13, 6' E v 13,7 E v \y is determined by the A operation to be: Gjv 10 ) = (*011 0*11 *0*0 **00). ij 13 ~~ The corresponding set of E-connectable functions is represented by K(v ) = (***0 **00 -x-*** •x-x-x-x). Only f(v ) satisfies both the requirements for a function f to be (3) used in error- compensation for v, ~, f(v ) e K(v ) and f (v ) = 1. Gate v,_ is determined to be strongly effectively E-connectable to v ; and the new connection from v, _ to v_„ is added, resulting in Figure 2.3.1(c), The new f(v, _) and G„(v,„) are: -1-3 & ±3 f(v ) = (0001 0011 0000 0000) and G^(v no ) = (*001 0*11 *O*0 **00). E v 13 rd In Figure 2.3.1(c), the 3 components of functions realized at the gates and input terminals are shown. It can be seen that the error in the function realized at the output terminal of the original network has been compensated, and a new network consisting of 8 gates and 19 connections has been created which realizes the output function z. Applying Procedure BCE again to this new network, gate v,> is first removed to create N' (shown in Figure 2.3.1(d)). Figure 2.3.1(e) 35 shows the final result of this 2nd application of the procedure. This last network, consisting of 7 gates and 18 connections, is known to be an optimal network for the function z. (Its optimal! ty has been proved by a program [13] based on the branch-and-bound method described in [12] and [Ik].) 3. POTENTIAL OUTPUT TABLE In order to compensate for errors at one gate, functions currently realized at other gates and input terminals are used in Procedure BEC. In order to make the error- compensation more flexible, a function f (v. ) realized at gate v. may be changed to a permissible function f ' e G (v. ) by connecting additional inputs to v. and f ' may be used in error-compensation. The addition of inputs to a gate other than the one under consideration for error-compensation may enhance the capability of error-compensation. However, if we add too many connections in compensating for one error- component at a particular gate, other error- components may become difficult to be compensated as we experienced in our computational experiments. Let us call this an over- compensation . Because of this over- compensation problem we always try to add minimum possible changes to a network in compensating for errors. In the previous paper [10], the "possibly connectable" condition is introduced for a similar purpose. If this condition is satisfied with gates v. and v., a connection from v. to v. is added after modifying 1 y l j the output function of v. . This network change based on the possibly- connectable condition has the following advantages and disadvantages; (l) CSPF's are used in the possibly-connectable condition. As a CSPF for each gate is represented by only one vector, the memory space required in a computer is proportional to the number of gates and input terminals. Thus we can save memory space. 37 (2) After the modification of the output function of gate v., the recalculation of all the outputs and CSPF's of gates in the set S(v. ) of all the successors of v. is required. (3) Since the calculation of CSPF's depends on ordering, the result of a network transduction may be different if we use a different ordering. (k) For the compensation of an error-component in the CSPFE of v., sometimes outputs of several gates may be modified, J and it may cause an over-compensation. In order to avoid the problem of over-compensation and to save computation time for updating as mentioned in (2), we introduce the concept of the Potential Output Table (POT) which stores a special subset of functions that may be obtained by adding inputs to gates in the network. The subset is carefully selected so that the addition of connections does not require the recalculation. The following lemma gives a condition under which the recalculation of output functions realized at gates other than the one with newly added connections is not required. Lemma 3.1 : Assume that there exist two gates or a gate and an input terminal, v. and v., respectively, satisfying IS(v.) 3 IS(v. ). When the output of v. is connected to v., only the output function of v. may change while the output functions of all other gates stay the same. Proof : It is known as the triangular condition and generalized triangular condition [1,11] that the addition of a connection from v. to v. does not change output functions of gates in IS (v. ). Go only output function of gate v. may change by this addition. Figure 3.1 shows an example of Lemma 3.1 where originally (Figure 3»l(a) IS(v k ) D IS(v ) 3 IS( Vi ). So we can modify the output of v. by any of the following three changes without changing the output functions of other gates. (a) Addition of a connection from v. to v. (Figure 3.1(b)). (b) Addition of a connection from v to v. (Figure 3.1(c)). K 1 (c) Addition of the above two connections (Figure 3.1(d)). If we allow changes of two outputs, the network shown in Figure 3.1(e) can be formed. But we do not use such function (i.e., the function realized by v. in Figure 3.1(e)) in potential output table for the sake of simplicity. Based on Lemma 3.1> potential output table is defined as follows: Definition 3.1 . The i-th row of a potential output table consists of v , f, and V. which are defined as follows: v is a gate or an a. b. d. a. ill l input terminal; f is the function realized at v by adding inputs from all i i the gates and/or input terminals in V, to v . If v is an input terminal, ii i V is an empty set; otherwise V, is an arbitrary subset (including the empty i i set) of set U defined by a . l U = fvllS(v) 3 is(v )}. a. ' - a. i l A potential output table is a collection of rows defined above. Suppose that V\, and V, are two subsets of U and that the d. d. a. In lp 1 addition of inputs from V, to v and the addition of inputs from V, d. a. * d. (a) 39 (b) (c) (a) (e) Figure 3.1 Modification of Gate Outputs UO to v produce the same function f . Then we select one of them (say V, ) along a i i with v and f, as the i-th row of the potential output table. If o n 4 lv I < Iv I , we select V, because the same f can be realized with 1 d. ' ' ' d. " d b *1 x 2 X l less additional connections, where |v denotes the number of gates or i input terminals in V . i In the error-compensation procedure presented in Section k, only- functions listed in POT may be connected to the gate currently under consideration for the purpose of compensating for error- components in the CSPFE of that gate. This restriction can avoid the problem of over- compensations since a minimum possible connection change is attempted. One important point should be noted in using the potential output table, namely not all entries in the potential output table can be used simultaneously. In other words, if we select one entry from the potential output table, several other entries may be required to be prohibited from selection because of possible loops or other reasons. The following lemma describes the conditions for prohibitions. Lemma 3.2 : If the i-th row consisting of v & , f and V d in the i i i potential output table is used for network changes, the j-tfa row (v & , 3 f , V ) satisfying one of the following conditions must be prohibited 3 3 from use : (1) v = v , v ' a. a. 3 i (2) v e V^ and V, £ fi, ^ a . d . d . 3 i 3 (3) v a 6 V d and V d i p. i 3 i 1+1 Proof: (1) is prohibited because only one function realized at each gate can be used. In other words, f and f cannot be realized i J simultaneously. (2) is prohibited because the selection of the j-th row would change the function realized at v and therefore cause possible changes in f . a. b. In other words, the situation similar to the one shown in Figure 3.1(e) is prohibited. Condition (3) is equivalent to (2) if i and J are interchanged. Q.E.D. The conditions in Lemma 3.2 also prevent possible loops in the network. If conditions (2) and (3) are both satisfied for some i and j, the use of both the i-th and j-th entries would produce a loop since v would a . 1 be connected to v and v would be connected to v . For the sake of EL . ci . cl . convenience, these conditions will be referred to as prohibition conditions. The advantages and disadvantages of the transduction procedure based on the potential output table are as follows : (1) Functions are selected such that the necessity of the recalculation of output functions of other gates is avoided. (2) Since all the functions obtained by input modifications are stored in a table form, functions to be used, at each network change can be chosen by a simple table look-up. (3) There is less dependency on ordering. (k) Memory space is required for the table. (5) There will be less problems of over-compensation if a POT is used. Example 3.1 shows a POT for a given network. h2 Example 3.1 : For the network shown in Figure 3.2, the potential output table is shown in Table 3.1. Both v, ~ and v are connectable to v Q ; but neither of the connections changes the output function of v . Based on Definition 3.1> 7 such a row is not listed as an entry of the potential output table. The same discussion is applied to the possible connections from v,-, v , and v..- to v , V/-, and v, n , respectively. Neither of the three connections changes the respective outputs, so they are not listed as potential outputs. In this table, we cannot use the functions in the 9-th row and 10-th row simultaneously since condition 1 of lemma 3.2 prohibits such a usage. More specifically, both functions are realized at the same gate v, , so they cannot be realized simultaneously. The same prohibition applies to the pairs of rows the 11-th and 12-th, 13-th and lU-th, and 15-th and l6-th. The 10-th row and lU-th row cannot be used simultaneously because of the condition 3 of Lemma 3.2. More specifically, the simultaneous usage of the 10-th and lU-th rows would cause a loop in the network since v,~ would be connected to v in making the 10th row and v,_ would be connected to v, „ in making the lU-th row. The following definition gives a condition for an entry in the potential output table (a potential output) to the E-connectable or effectively E-connectable. Definition 3.2: Consider the i-th row (v , f , V, ) in a potential a. b. d. ill output table. Then v is E-connectable (effectively E-connectable) to v a « i if the following conditions are satisfied: (1) f is E-connectable (effectively E-connectable) to v, i and (2) [{v a } u v d ] ns(v) = fi. i i k3 ^ m Table 3.1 Potential Output Table for Network in Figure 3.2 kk i V a. i i 1 1 v i 0000000011111111 t 2 V 2 0000111100001111 p 3 V 3 0011001100110011 p k v k 0101010101010101 5 V 5 1011011110101100 fi 6 v 6 0100000001010011 t 7 V 7 0000100000000000 p 8 v 9 0000110000000000 p 9 *» 1010000010100000 10 V 10 1000000010100000 V 13 11 v 12 1111000011110000 t 12 v 12 1100000011000000 V" X3) 1 13 V 13 0011001100000000 ! * T 13 0001001100000000 V 10 15 V lU 1100110011001100 fi ! * i ! v iu ! i i 1100110000000000 i i v,( = X,) ^ The second condition is required in order to guarantee that the network after modification has no feed-back loop. Definitio n 3.3 : Consider the i-th row (v , f, , V, ) in a potential a. b. d. * 111 output table. Then v is strongly effectively E-connectable to v if the l following conditions are satisfied: (1) v is effectively E-connectable to v, and i (2) none of the following conditions are satisfied: (2-1) IS(v ) 3 lS(v) a . l (2-2) v e IS (v.) for same v. et . J J d i Both the conditions (2-1) and (2-2) are required because of the strongly effectively connectable condition introduced in Definition 2.2.1.4 of Section 2.2.1. The condition (2-1) is the same as condition (2) in Definition 2.2.1.4. If condition (2-2) is satisfied and we use f, to b i compensate for some error-components in v, then the resulting network will contain the subnetwork shown in Figure 3»3> where the dotted lines show the added connections. This subnetwork should be avoided based on the discussion in Section 2.2.1. In this case, there must exist a k such that v = v , \ a i and V, = V, - fv.). It is easy to prove that the k-th entry f, is also \ d i ^ \ a strongly effectively E-connectable to v, and should be used instead of f . b. l v. / / s £> Figure 3.3 Condition (2-2) in Definition 3.3 k6 The usage of a potential output table in an error-compensation procedure is shown in the following example. Example 3.2 : Consider the network shown in Figure 3. Ma), which realizes the same function realized by the network in Figure 2.3.1(a). After removing gate Vn and accordingly gate v, . (v, , is connected to Vn only), we obtain the network in Figure 3. Mb) which is the same as Figure 3.2. The third component in G„(v ) is the only error- component in the output. Values shown in Figure 3. Mb) correspond to the third components of CSPFE's for connections and gates. Procedure EEC fails to compensate for the error in the network output. However, if the potential output table for the network of Figure 3. Mb) (Table 3.1) is used during the procedure, we can compensate for the error caused by the removal of gate Vn and V--. First, for the error-compensation at v_, we use the function realized at v, ? by adding input x (the 12-th entry in Table 3.1) and disconnect the connection from v, n to v . The procedure then continues to compensate for error-components in other gates and finally obtains a network as shown in Figure 2.3.1(c). LTN ^7 t- c^ 00 U3 d 0) -p < 0) a d 6 A) 5h O SB -P a) g h9 k. NETWORK TRANSDUCTION PROCEDURE USING CSPFE'S In this section, several modifications will be added to Procedure BCE to improve the effectiveness of the procedure. U.l Selection of Gates to he Removed In Procedure BCE if we remove an improper gate, the errors caused by this removal may not be compensated. In such cases, Procedure BCE need be reapplied to a network obtained by removing another gate. In order to shorten the calculation time a proper ordering for removing gates is desired. A gate for which error- compensation seems easier should be removed first. In other words, if the removal of one gate causes many errors in the output functions, it may be difficult to compensate for all these errors, and therefore the removal of such a gate should not be tried at first. Definition U.l.l : If a given network N' realizing output functions z', ..., z' is to be converted to a network realizing z., .... z , the 1' m 1' m number of error positions (abbreviated as NEP) in the network N' with respect to z n , .... z is defined to be the number of l's in the following 1 m vector : v (z i e zi), i=l, . . .,m where z. © z.' is a binary vector whose d-th component has the value if z: d ) = *, or z: d ) © zV d ) otherwise. i'ii For example, assume that a given network N' which realizes two functions z! and z', z , 1 = (01010110), z^ = (01100101), is to be converted into a network realizing two functions z and z , Z = (0011011*), z 2 - (00101*01). Then the number of error positions (NEP) is calculated by the following: z © z' = (01100000), z 2 © z^ = (01001000), (z e z|V(z 2 ® z^) = (onoiooo). The NEP for network N' with respect to z and z is the number of l's in this vector which is three. The concept of NEP can be used to determine the ordering of gates to be removed. The calculation of NEP, however, is time-consuming. Lemma U.l.l : If a CSPF for gate v. in a network N contains k l's, the NEP of network N. with respect to the outputs of N is at most k, where N. is the network obtained from N by removing gate v. . Proof: If the MSPF for v. in network N contains k l's, the NEP l of network N. with respect to the outputs of N is also k (recall that a 1 in the MSPF is such a component that the corresponding component of at least one of the output functions of N will change if this 1 is changed). Since a CSPF for v. is a subset of the MSPF for v., the former contains at least i i the same number of l's as the latter. Q.E.D. MSPF stands for Maximum Set of Permissible Functions which was introduced in [k] and [6], 51 Corollary U.l.l ; If function f (v. ) of v. in a network N contains k l's, the NEP of the network N. with respect to N is at most k, where N. is the same as in Lemma U.l.l. Proof: Since f (v. ) e G (v.), f (v. ) contains no less l's than 1 c 2. 1 G (v.). Using Lemma U.l.l the result is obvious. CI Q.E.D. Corollary U. 1.1 or Lemma ^.1.1 can be used to determine an ordering of the removal of gates. Definition U.1.2 : P is an ordering of all the gates which satisfies the following condition: If f (v. ) contains more l's than f(v.), W >P o ( V An ordering based on Lemma U.l.l may give a better result than P in selecting the gate to be removed, but the calculation of CSPF's is required. However, some redundant connections may be removed during the calculation of CSPF's. Definition k.1.3 : P is an ordering of all the gates which satisfies the following condition: If the CSPF for v. contains more l's than the CSPF for v., P l (v i } > P 1 ( V* If ordering P n or P. is used in determining the order of gates to be removed, a gate v. such that P_(v. ) or P, (v. ) is the smallest among l i 1 l all P (v)'s or P (v)'s for all unselected v's is selected next. 52 4.2 Selection of Gates for Error-Compensation During the calculation of CSPFE's, there may be more than one gate for which CSPFE's have been already calculated. Any of these gates can be selected for error-compensation by changing input connections. The selection of a gate whose CSPFE contains the minimum number of error- components is expected to give a better result for the following reasons: (1) Error-compensation for a gate whose CSPFE contains a smaller number of error-components is likely to be easier. So by an ordering based on the number of error-components, the calculation time may be shortened. (2 ) If we select a gate whose CSPFE contains many error-components, many network changes would be required and yet only a few or no error- components could be compensated. As a result of many network changes, it may become difficult to compensate for err or- components in other gates (over-compensation, see Section 3). Definition 4.2. 1 : P is an ordering of gates which satisfies the following conditions : (1) P is defined on a subset of gates V, for which (a) error- compensation has not yet been applied, and (b) CSPFE's have been already calculated. (2) Let E (v) and E (v) be the numbers of 1-error- and 0- error- components in the CSPFE for gate v, respectively, P p satisfies the following condition: For two gates v. and v. in V, if W l E l^ v i^ + W E 0^ V i^ > W l E l^ v i^ + w o *W' 53 then P p (v. ) > P„(v.), where w and w p are appropriately determined weights for 1-error and O-error-components, respectively. If we use ordering P p in selecting a gate from the gates whose CSPFE's have been calculated, a gate v with the minimum P p (v) will be selected first. Different combinations of w and w» may produce different results. Typical combinations of w and w are as follows : (1) w x < w Q . As discussed later, the error-compensation for 1-error- components seems easier than the error- compensation for 0- error- components. Since ordering P usually assigns a smaller number to a gate whose errors are easier to be compensated, a condition w < w is set up. (2) w 1 = w = 0. The selection of the gate to be considered next depends only on the labels of gates. ^.3 Error- Compensation Using a Potential Output Table After selecting gate v., new inputs may be added and some inputs may be removed from v. in order to compensate for error-components in the CSPFE of gate v. . The input set to be added and the input set to be removed should be carefully determined so that the number of error- components compensated is maximized. This is a combinatorial problem and it may be difficult to obtain the best result without lengthy calculation. In order to keep the calculation time within a reasonable range, an efficient procedure to determine 54 such input sets without exhaustion is desired. For this purpose, error- components will be classified in Section 4.3.1 along with the possible ways to compensate for each type of them. Section 4.3.2 will then propose a proper ordering for the compensation of different types of errors. A common sub- procedure to be used in these compensations will be given in Section 4. 3. 3« 4.3.1 Classification and Compensation of Error-Components Err or- components in the CSPFE of a function are classified as follows : (l) 1-error-components in the CSPFE of a gate (see Figure 2.1.1(a)) If a component of the CSPFE for a gate v. is 1, e.g., G^, (v.) = 1, 3. — El — it means f (v. ) = 1 and it is regarded as an error. There are two ways to compensate for this error: (l-l) The error will be compensated if at least one of the inputs of v. changes to 1. This is actually done by propagating this error to the inputs of v. (Figure 2.1.1(a)). For example, when an immediate predecessor of v., e.g., v. e IP(v. ), is taken into consideration at a later stage fri ) of the error-compensation procedure, f (v.) will become j ( ci) 1 if the error- component G^ (v.) = is compensated. (1-2) Add a new input to v. which is selected from the potential output table (see Figure 2.2.1.1). If the j-th ( d ) entry of the POT is selected, f/ should have the value 1 (d) ^ in order to compensate for G), (v. ) = 1. 55 (2) O-error-camponents in the CSPFE of a gate (see Figure 2.1.1(b)) If a component of the CSPFE for a gate v. is 0, e.g., G^ '(v.) = 0, it means f (v. ) = and it is regarded as an err or -component. In this case, there must exist at least one input of v. whose d-th component is 1 (Figure 2.1.1(b)). There are three ways for the error- compensation of this case : (2-1) The error will be compensated if all of the 1 inputs of v. change to 0's. This can be actually performed by propagating this error to the CSPFE 's of all immediate predecessors of v. whose d-th components are l's. When all these error-components are compensated at a later stage of the error-compensation procedure, f (v.) becomes and thus G-A (v.) is compensated. (2-2) Replace all 1 inputs by other functions in the potential output table which are E-connectable to v. and whose d-th components are 0's. In order not to change the O-components in G„(v. ), the added inputs should cover all ±Li 1 O-components which were originally covered only by removed inputs. (2-3) Combination of (2-1) and (2-2). In other words, replace some of the 1-inputs and propagate the error to the CSPFE 's of the remaining 1-inputs. (3) Error- components in the CSPFE of a function realized at an input terminal. If the CSPFE for a function realized at an input terminal has error- components, these error-components cannot be compensated. There are two such cases: E 6 (3-1) A 0- error- component in the CSPFE of a gate v is propagated to a function realized at an input terminal. (3-2) A 1- error- component in the CSPFE of a gate v. is propagated to all the inputs of v. which all originated at input terminals. Even if there is an input connection from a gate v., sometimes it is impossible to propagate J the error to the CSPFE of gate v. due to the requirement by J other immediate successors of v. that v. realize 0. In the error-compensation procedure, input terminals are never selected for error-compensation since an error in an input terminal can never be compensated. Therefore, in order to compensate for all errors in the network output gates, we should try to not propagate errors to input terminals. Based on this consideration, error-components covered by input terminals should be taken into consideration first as to be explained in the next section. 1+.3.2 Ordering of the Compensations for Different Types of Error- Components In order to maximize the number of errors compensated in the CSPFE of v., we first try to compensate for error- components which are likely the most difficult to compensate. Based on the discussion in Section U.3.1, the degrees of difficulty of error- compensations are ordered as follows: (l) Error-compensation for a function realized at an input terminal is impossible because the error cannot be further propagated. Therefore, we should try to remove inputs of v. originating from input terminals 57 whenever their retention would allow errors to be propagated to the terminals themselves. (2) Compensation for a 0- err or- component in the CSPFE of v. may be the next most difficult. i (3) Compensation for a 1- err or- component in the CSPFE of v. may be the easiest. We try to compensate for error- components according to the above order. After each step, IP(v. ) and G (v. ) should be updated so that an error- component in G (v. ) once compensated will never become an error again. The following is a more detailed description of these steps: (1) Replacement of functions realized at input terminals. Let set Q consist of input terminals satisfying (a) Q cz IP(v. ) and (b) for every v. e Q, there exists at least one d such that J f (d) (v.) = 1, G^ d) (v.) = 0, or f (d) (vJ =0, G< d >(v.)= 1. Let Q^ be the set of rows of the potential output table which are strongly effectively E-connectable to v. . If we select a subset Q~ of Qu such that (a) no two functions of £L satisfy any of the prohibition conditions of Lemma 3.2, and (b) a subset Q_ of Q becomes E-disconnectable with respect to G F (v.) if Q_ is connected to v., then we say connections from input terminals in Q, can be replaced by functions contained in Q,_. A procedure to calculate Q and Q_ from Q and Q^ will be discussed later. (2) Compensation of 0- error components in the CSPFE of gate v. The compensation of this type of error components is divided into two substeps according to the importance of the error-components classified as follows. Definition k. 3.2.1 : The number of 1-errors (NOOE) of a function f which is strongly effectively E-connectable to gate v. is defined to be the number of d's such that f (d) = 1 and G^ d) (v.) = 0. Definition 1+.3.2.2 : P is an ordering of functions satisfying the following condition: P (f ) > P..( f 2 ) if the N00E of f i is grater than the NOOE of f Ordering P is used in determining the order of functions in the set Qp of v. (rows of a potential output table representing the functions which are strongly effectively E-connectable to v.). It is also used in determining the order of functions which are inputs of v. . When ordering P is used, the function f with the lowest P~(f) has the highest priority to be selected. Definition ^-.3.2.3 : An input terminal or gate v. in IP(v. ) is said J -L to have a primary 1- err or if for f(v.) there exists a d such that f (d) (v.) . 1, J V f (d) (v. ) = 0, v k sIP(v.) k First we try to replace connections from gates or input terminals which have primary 1-errors. 59 (2-1) Select one v. e IP(v. ) which has a primary 1-error. Let Q, be [v.], and Q^ the set of rows in the potential output table which are strongly effectively E-connectable to v. and whose d-th components are O's. Calculate a Q, c Q( = {v.} ) and a subset Q^c^ such that no two functions of Q_ satisfy any of the prohibition conditions in Lemma 3*2. This calculation procedure will be given in Section ^.3«3« (2-2) Replacement by functions whose NOOE's are zero. Let Q, be the set of gates in IP(v. ) which realize functions whose NOOE's are not zero. Let Q_ be the set of rows in the potential output table whose corresponding functions are strongly effectively E-connectable to v. and whose NOOE's are zero. Let Q,_ be a subset of Q^ such that Q_ can replace a subset Q, of Q and no two functions of Q_ satisfy any of the prohibition conditions in Lemma 3.2. The procedure for the calculation of Q_ and Qu from Q, and Q^ is given in the next section. (3) Compensation of 1-error- components in the CSPFE of gate v. . l The compensation of 1-error components in the CSPFE of gate v. can be done by adding proper inputs to v. . Let Q~ be the set of rows in the potential output table which do not correspond to gates or input terminals in IP(v. ) and each of which is either of the following two: (a) A row corresponding to an input terminal v. which is strongly effectively E-connectable to v. and for which the NOOE of f(v.) is zero. J (b) A row corresponding to a gate which is strongly effectively E-connectable to v. . 60 Qp is the set of candidates to be connected to v. for the compensation of 1-error-components. The reason for (a) is that a function realized at an input terminal which causes an error is not desired. The following procedure can be used for the compensation of this type of err or- components. Step 1 . Set Q = 0. Step 2 . Select a row j in Q according to the ordering P~. If all rows in Q, have been considered, the procedure terminates. Step 3 . If there exists any d satisfying n* ' = 1 and G^, (v. ) = 1, D . Li X — then set Gj, (v. ) =0 for all such d's; otherwise go to step 2. Step k . Delete all the rows from Q, each of which and the j-th rows satisfy at least one of the prohibition conditions of Lemma 3.2. Set C^ = ^ U (j). If a nonempty set Q_ is obtained at the end of this procedure, some 1-error-components in the CSPFE of v. can be compensated by adding connections to v. from the gates and input terminals corresponding to the rows in Q,„. U.3.3 A Procedure to Replace Inputs In the previous section, a procedure for the calculation of Q c Q and Q„ c Q^ is required, where Q is a subset of IP(v. ) and Q^ is a subset of functions contained in the potential output table which are strongly effectively E-connectable to v. . In other words, Q, contains the inputs to be replaced and Qu the functions which can possibly replace some or all of these inputs. The objective is to find a subset Q, of Q, and a subset Q of Q^ such that Q_ can actually replace Q . In other words, if 61 the functions in (^ are connected to gate v., the inputs in Q will become E-disconnectable. This relation is illustrated in Figure ^.3.3-1. Q IP(v i )-Q ,^ v i IP(v. )-Q Q 1 c Q (a) Before replacement (b) After replacement Figure U.3.3.1 Input Replacement The procedure is as follows: Step 1 . Set & = fi, and Q = 0. Step 2 . Vector T is defined as follows: T^ d ^ = 1, if G^'O. ) = and V E X v.€lP(v.)-Q f (d) (v.) - 0; ,(d) 0, otherwise. Vector T_ is defined as follows T n (d) = 1, if V f^ d) ■ 1 and T„ (d) JeQg J "0 = i; [d) T x-/ = 0, otherwise. Set T 2 = T Q - T . 62 Step 3 . (3-1) Select an input terminal or gate v. from Q, J according to the ordering P„ (an ordering based on the number of NOOE's). (3-2) Calculate T^ as follows: '^ (d) = 1, if f (d) (v.) = 1 and T^ d) = 1; „(d) 0, otherwise. v If T' contains only O's, go to Step (3-1) . (3-3) Calculate T' as follows: T' (d) = 1, if f (d) (v.) = land T | d) = 1; "1 ,(d) _ 0, otherwise. v. Set T ± = T ± - T£, T 2 = T 2 - T^ t and ^ = ^ - (v }. If T still contains some 1, go to Step (3-1). Step k . (k-1) Set Q = p. {h-2) Select a row j in Q^ according to ordering P_, If all rows in Q_ have been selected, the procedure terminates. (k-3) Calculate T' as follows: ' T ; (d )=l, if f' d » = 1 and T ,d » = l; I" ^ ' = 0, otherwise. If T| consists of all 0's go to Step (k-l). 63 (k-k) Set T = T - T». (U-5) Let U(j) be a subset of Qi such that the j-th row and each row in U(j) satisfy the one of the prohibition conditions in Lemma 3.2. set ^ = ^ - U(j), and Q 3 = Q3 U (J). (U-6) If there exists a d such that t| =1 and V f> / = then set Q^ = - u( j ) and go to Step 1: otherwise set Q = Q u{j) and go to Step (4-1). ^.^ Addition of Functions Realized at Input Terminals In general, the proper addition of functions realized at input terminals to gate v ± can produce more *'s in the CSPFE's of other gates connected to v. . This may make it easier to compensate for error-components in these gates. A function f realized at an input terminal will be connected to v. if the following conditions are satisfied: (1) f is strongly effectively E-connectable to v . 1 (2) For any d such that G^ (v. ) =0 and only one input v satisfies f v ; (v.) - 1 (primary 1- error), ( \ f =0. This guarantees that the addition of function f to gate v. will not reduce the number of primary 1-errors which are very likely the easiest to be compensated. f .5 The Calculation of CSPFE's . Upon the completion of the steps for the compensation of error- cmponents in the CSPFE of v. mentioned in Sections 4.3 and k.k, the 6k new input set for v. results. The CSPFE's for these inputs must be calculated based on the discussion in Section 2.1. As mentioned in Section 2.1, the CSPFE for a gate v. can be calculated based on the following relation: G (v ) = A G (c ) E * v k£ IS(v.) E Jk Let IS(v.) . (v^, v^, ..., v^ } and P^v^) < P^) < ... < P^) (P is an ordering for the selection of gates for error- compensation and is defined in Definition ^-.2.1). Then the above relation can be rewritten as: In the actual program, the CSPFE's for connections, i.e., G,_,(c, )'s are not E jk stored individually. Instead, G (c ) is stored first, and then it is E K -|_ replaced by G_(c ., ) A G„(c. 1 ) after v. is considered. ^SkJ A G E (c jk 2 ) iS thSn replECed by G E (G dk 1 ) A G E (c Jk 2 ) A G E (c jk 3 ) after v is considered and so on. This process continues until k 3 all immediate successors of v. have been considered, and G_(v.) results upon the completion of the consideration of v . For convenience of later k i discussions, let us define G £ (v. ) a = G E ( c -j k ) A G E^°jk ) A ••• ^ G E^ C :ik ^ and call G„(v.V an intermediate CSPFE for v.. Storing one intermediate E j J a j CSPFE for each gate has the following advantages : (1) Saving of memory space. (2) Intermediate CSPFE's can be used for the proper assignment of CSPFE's for input connections. 65 The calculation of CSPFE's for the input connections of v. is performed based on the discussion in Section 2.1. However, special consideration is given for the case when Gj, (v. ) = holds and more than one Hi 1 v. e IP(v. ) satisfies f^ (v.) = 1. In such a case, onlv one G^ (c.) j 1 3 ' J E v ji y should be assigned to 1, and all others to *. The following definition gives an ordering on how to select such an input connection (the connection / ■, \ c. such that G^, (c.) is assigned 1). ji E ji y Definition 4.5.1 : P, denotes an ordering for the inpats of a gate v. satisfying the following conditions: (1) If v. is an input terminal and v is a gate, and both 3 K v. and v n e IP(v. ), then 3 k l" P, (c. ) > P, (c, . ) 4 V ji y 4 V ki y (2) If both v. and v are gates, P, satisfies the following: (2-1) P, (c . . ) > P, (c ) if f(v.) has more primary 1-errors than f(y ). k (2-2) When f(v.) and f(v ) has the same number of 3 k primary 1-errors, then P, (c..) > Pj,(c, . ) if the NOOE of f(v, ) is greater than that of f(v.)« K 3 (2-3) When f(v.) and f(v ) have the same number of 3 K primary 1-errors and NOOE's, then P, (c. ) > P. (c, . ) 4 ji 4 ki if ||lS(v.)|| > ||lS(v )||. According to ordering P, the connection c. which has the highest P, (c.) will be selected first. (c\ \ Suppose GZ, (v.) = and Q is a subset of IP{v. ), Jii i i satisfying f^ (v.) = 1 for every v. e Q. In this case, only one G^ (c..) Table U.5.1 Propagation of CSPFE 56 ^(V J G E ( Va G E (v jW * or 1 * * 1 l 1 1 1 *, 0, or 1 1 * or 1 *, 0, or 1 * or 1 1 1 1 i 1 i i ! o * *■ i i i 1 1 1 i i ■* * or 1 ! ! i 1 1 or 1 67 for v. e Q, should be assigned 1 and all other G (c ) for v e Q, - {v.} are assigned *. The ordering P. are used in selecting such c.. as follows: (1) If there exists a v. e Q such that G; d/) (v.L = 1 where G^^v.L is the partial CSPFE for v. obtained prior to considering c.., we select J J - 1 - one such v . . 3 (2) If there exists no v. satisfying the condition (l) but exists J ( d ) one or more v e Q, satisfying Gj, (v) = *, we select one v. among v's according to ordering P. . (3) If there exists no v. satisfying the above two conditions, J i.e., for every v e Q, Gl (v) = 1, we select one v. from Q according to n, a — j ordering P, . After v. is selected, we set J G^(c. ) = 1, and / -j \ Gj, (c ) = *, for every k such that v e IP(v.) - {v.}. i Kl K 'J J In the actual program, the two steps of calculating G_(c.) for E J 1 v. e IP(v. ) and G_(v.)_, , = G_(v.)_ A G_(c..) are combined into one step, and thus Table U.5.1 results. An exception should be noticed. Suppose v. is an output gate and / \ E ^ j ; a respectively. G i (v.L has been assigned or 1. Then we will never assign G (c. ) = or 1, K -\ OL — — XL J 1 h.6 Recalculation In Procedure BEC, CSPFE' s for gates are calculated in such an order that no recalculation of CSPFE 's would be required. Furthermore, during this process in order to compensate for error-components some connections may be removed or added in such a way that no recalculation would be required. However, in the more effective network transduction procedure discussed in this section, recalculation of CSPFE's is sometimes required for the following reasons: (1) In Procedure BEC the use of a gate whose CSPFE has been calculated is prohibited. In the procedure discussed in this section, the use of such a gate is allowed in order to increase the effectiveness of the procedure. This requires the recalculation of some CSPFE's. (2) Consider the case shown in Figure 2.1.1(a). A 1-error of gate v. is propagated to all its inputs as errors. However, if we can compensate for one of them, the 1-error in the CSPFE of v. will be compensated, In Procedure BEC, even if we have compensated for one of them, we still try- to compensate for O-errors in other inputs. Such compensation is unnecessary and sometimes causes over-compensation. We can avoid this situation by the recalculation of CSPFE's. (3) In Section h.k, only primary 1-errors are preserved. However, if some nonprimary 1-errors are compensated and an uncompensated 1-error becomes a primary 1-error, the recalculation process will recognize this new primary 1-error, and concentrate on the compendsation for this error. One problem with the recalculation is a possible infinite loop in a procedure. In other words, a network may be converted back into the original network after several recalculations. Careful consideration in compensating for errors is required in order to avoid such a loop. If one of the following conditions is satisfied, we recalculate CSPFE's. (1) At least one error of gate v. is compensated. (2) A row j in the potential output table is used as an input to v. and {v ] U V, contains at least one gate whose CSPFE i c a. d. 3 has already been calculated. 69 5. COMPUTER PROGRAM IMPLEMENTATIONS AND EXPERIMENTS A "basic error- compensation procedure, EEC, was discussed in Section 2.3. Later, modifications to this basic procedure were discussed in Section 3 and k, which lead to a more powerful error-compensation procedure. Let this procedure, consisting of the BEC with these modifications, be referred to as the MEC (Modified Error -Camp ens at ion) procedure. A network transduction procedure using this MEC has been programmed, and Section 5.1 will discuss the details of the implementation. Although this network transduction procedure is often quite successful in removing a single gate from a redundant network, a redundant network has, in general, more than just one unnecessary gate. The obvious solution, of course, is to repeatedly apply the procedure to a network until it is impossible to remove any further gates (at least, by the use of the transduction procedure). Section 5.2 will discuss two methods of doing this which have been programmed. Some of the results obtained by these two methods of repeatedly applying the network transduction procedure using MEC will be presented in Section 5.3. For some 5 -variable functions, optimal (in terms of number of gates and number of connections) networks were actually found by the transduction procedure, beginning with very redundant initial networks . 5.1 Program Realizing Network Transduction yr id u ■ Using Modified Error-Compensation (MEC ) The suggested modifications of the basic error- comijensati procedure were added to it along with means of selecting a v. to form N! from N', and the resulting network transduction procedure was implemented as part of the program NETTRA-E1. This program reads in a given initial network, applies once the network transduction procedure using MEC, and prints out the resultant network. The details necessary to use NETTRA-E1 (and also NETTRA-E2 and -E3, discussed in Section 5.2) are given in [9]. Sections 5.1.1 and 5.1.2 will describe the program NETTRA-E1 in greater detail. 5.1.1 Selection of a Gate for Removal In the program NETTRA-El there is a subroutine named PROCCE (transformation PROCedure by the Compensation of Errors) which, although simple in itself, directs the overall execution of the network transduction procedure. After the main subroutine reads in an initial network, N 1 , subroutine PROCCE assumes control, choosing the order of removal of the v. 's to form the N.''s, causing the computations of the possible output table, and, generally, controlling the execution of the modified error- compensation procedure (MEC) for each N.' . What happens after a particular v. is selected and removed from the given network N' will be discussed in Section 5.1.2. Two alternative methods (mentioned previously in Section k) for determining the order of removal of and attempted error-compensation for the gates v. have been programmed. 71 The first of these is quite simple and straightforward. This ordering of removal of gates, for the purpose of applying MEC, is exactly the same as the ordering P defined in Definition 4.1.2. The subroutine PROCCE itself counts the number of 1-components in f (v. ) for each gate v. in N 1 and determines P„. However, the second alternative, based on Lemma 4.1.1, goes a little beyond the ordering P, of Definition 4.1.3. During the calculation of a set of CSPF's for N', some redundant gates may be removed from the network, by a pruning procedure discussed in [h] which also calculates CSPF's simultaneously, resulting in a new network N" (actually, a subnetwork of N' ) which still realizes the correct output functions. Then, subroutine PROCCE makes an ordering P of the gates in N" (rather than N') later forming networks N" , N!' , ... by the removal of gates i... i„, ... . i, i p 1 2' This second alternative may allow several gates to be removed in just a single application of the network transformation procedure realized by PROCCE. 5.1.2 Calculation of CSPFE's and Error-Compensation As discussed in 5.1.1, a network N' which does not realize the desired outputs is obtained by removing a gate from the original network N according to a proper ordering. The network N' is then modified by subroutine RCEC (Replacement of Connections by Error- Compensation) in order to realize the desired outputs by means of error- compensation discussed in Sections 2 and k. In subroutine RCEC, error- compensation is concentrated on one gate (v. ) at a time. If some of the error-components in G (v. ) can be compensated, subroutine RCEC will return to the calling 72 subroutine PROCCE to check whether or not the new network realizes the desired output functions. Depending on the result of the checking, subroutine RCEC is entered again to continue the error-compensation procedure; otherwise a new network which realizes the desired output functions has been obtained. If no error-compensation occurs during the consideration of a gate v., G„(v. ) is propagated to its immediate 1 hi predecessors, and RCEC continues err or- compensation on other gates. RCEC fails to obtain a new network realizing z. 's after all the gates in the 1 network have been considered without any compensation. Subroutine RCEC is well in line with the procedure described in Section k. Before it is called, the initial values of CSPFE's for all gates must be calculated. A complete CSPFE for a gate will be calculated when all its successors are considered. Procedure realized by subroutine RCEC : Step 1 Select a gate v. according to ordering P p of Definition U.1.3 with w = w = 0. If all gates are considered, return, unsuccessful, to the calling subroutine. Step 2 Remove E-disonnectable input connections with respect to G (v.) defined by Definition 2.2.2.1. If no error- component exists in Ei G„(v. ), go to Step 9. Jii l Step 3 From the potential output table, select a set Q containing all strongly effectively E-connectable functions to gate v. according to Definition 2.2.1.1+. If Q = f), go to Step ^. Step k Classify Q into the following four subsets: B^ contains f, € Q_ such that v is a gate and b . p a. NOOE (Definition 1+.2.1) of f, is 0. b . 73 D^ contains f, e Q._ such that v is an input b. 5 a. terminal and NOOE of f, is 0. b . B- L contains f^ _ such that v is a gate and NOOE off is greater than 0. b . 3 D., contains f, e Q,_ such that v is a gate and NOOE of f, is greater than 0. b . Sort B. according to P of Definition U. 3.2.1. Step 5 Replace functions realized at input terminals according to the following. Let Q = fv.lv. e IP(v. ), v. e V_, N00E(v.) ^ 0}, [ ^2 = D U B U B l Q 1 = 0, T x = Call subroutines CALS1 and RPLCF to substitute Q e CL for Q, e Q if possible, Step 6 Replace functions with primary 1-errors (Definition 4.3.2.2) according to the following substeps: (6-1) Set Q = p, T = fi, and Q = {v.|v. e IP(v. )} (6-2) Select a gate v. e IP (v. ) such that f(v.) has a J — ■ J / -j \ primary 1-error. Let f (v.) be that error. J (6-3) Calculate Q, c Q^ such that for every f, e Q,_ f/ = 0, and no two functions in G^ satisfy any k prohibition conditions described in Lemma 3.2. (6-h) If Q, can replace v., set Q, = Q U {v.} and T n = T.. U [d|G^ d) (v. ) = 0, V f (d) (v) = 0} ^ 1 V€IP(V. )-{v.) 7h (6-5) Repeat substeps (6-2) through (6-k) until all possible v's J have been considered in substep (6-2). (6-6) Call CALS1 and RPLCF to substitute ict^ for Q c Q. Step 7 Replace functions with O-errors by functions without errors according to the following steps. Let Q^ = D U B , and Q = {v.lv. € IP(v. ), f' d '(v.) - 1 for some G; d '(v. ) = 0}. Call CALS1 and RPLCF to substitute Q, C Q for Q, C Q. Step 8 Let Qp = D U B U B . Compensate for 1- error-components according to the following step. Calculate Q = {f | f b €0^, f^ d) = 1 for some G^ d) = 1} . 3 3 3 If Q~ f 0, connect functions in G^ to v. . Step 9 Adding redundant connections realized at input terminals satisfying the following conditions : (a) V €D Q U3 3 (b) Connect f to v. will not reduce the number of primary 1-errors 3 in IP(v. ). i Step 10 If any error-component in G (v. ) has been compensated during Steps 2, 5, 6, 7, or 8, return, successful, to the calling subroutine. Step 11 Propagate G (v. ) to v. e IP(v. ) according to Table ^.5.1. Go to Step 1. Two subroutines are called by subroutine RCEC in Steps 5> 6, and 7. Subroutines CALS1 and RPLCF are programmed based on the procedure described in Section ^-.3. CALS1 is the procedure which calculates a Q, c Q that 75 can be replaced by functions in set Q. RPLCF then calculates a set Q c G^ which is sufficient for replacing Q . Since Q^ may contain such pairs of functions that satisfy one of the prohibition conditions of Lemma 3.2, and since Q_ is calculated before actual replacement (Q~) is taken into account, subroutine RPLCF may not always find a set Qq E Op sucn that no two functions of Qo satisfy any prohibition condition and that Q~ can actually replace G>, . In such a case, the last selected function in Q- is removed from set Qp and CALS1 is called again from RPLCF to calculate a set %. based on the new set of Qp. Ey returning to subroutine RPLCF, a replacement for Q_ is recalculated. If the calculation is possible, a replacement has been found; otherwise this process is repeated. When CALS1 is called, Q, Q^ and initial values of Q and T are given. Q x and T ± may not be empty when CALS1 is called from RCEC in Substep (6-6), Procedure realized by subroutine CALS1 Step 1 Select v e Q, according to the inverse order of ordering P, (v with the highest P (v ) is selected first). If all v 's have o y d p p been considered, return to the calling subroutine. Step 2 Let D = {d|f (d) (v.) = 1, v f (d) (v) = 0, J veIP(v.)-{v J } ( d ) V f = 1 for all d e D, go to Step 3; otherwise go to Step 1. feQg ste P 3 T ± = T 1 U D, Q 1 = Q 1 U v . Update IP(v. ) and go to Step 1. Subroutine RPLCF is always called immediately after CALS1. The procedure realized by subroutine RPLCF is as follows: Step 1 Q^ = , T = 0, and call CALS1 J to recalculate a new Q and associated T, . Go to Step 1. Step 8 Connect all f e ^ to v. and corresponding gates or input k terminals in V. to v . Disconnect the connections from v. e Q n to v. . \ \ k 1 i Return to the calling subroutine. There are variations of the above subroutines with different orderings. The complete evaluation of the effectiveness of each variation, however, requires considerable effort. 5.2 Single- and Multi-Path Applications of Transduction Procedure Section 5.1 discussed the program NETTRA-E1 which reads in a given network, attempts to remove and compensate for errors for a single gate of + Notice that if initially Q^ f and T. f ft, RPLCF is being called from Substep (6-6) in RCEC. In such cases, the functions in Q_, already satisfy that no pair of functions of Q^ satisfy any prohibition conditions, so Step 7 will never be reached. 77 the network, and terminates upon the successful removal of such a gate (although, in the process, more than just that single gate may have been removed) or upon the failure to locate such a gate. A new network resulting from NETTRA-E1 could still contain many gates which are removable by further applications of the network transduction procedure using MEC . The programs NETTRA-E2 and NETTRA-E3 offer two different approaches to the repetitive application of the network transduction procedure. NETTM-E2 is identical to NETTRA-E1 except that it calls the subroutine PROCCE repeatedly until no further gates can be removed from the network transduction procedure. The program moves through only one sequence of intermediate networks in going from the given network to the final result. It might be mentioned that, generally, comparing the network transduction procedure using the ordering P and the network transduction procedure using P and CSPF calculation (as described in Section 5.1.l)> one finds that the latter moves through a shorter sequence of intermediate networks (i.e., the transduction procedure is applied a fewer number of times in arriving at a final result) than the former. This is due to the fact that the latter transduction procedure generally removes more gates during a single application. However, it is not possible to say that either of these two variations (i.e., using P or P plus CSPF calculation) is stronger than the other. Since the order of successful gate removals is likely to be different in both cases, one will achieve a better final solution for certain given networks while the second will achieve the better solution for others. Except when otherwise specified, NETTRA-E2 and -E3 will be assumed to employ P along with the corresponding procedure [k] with CSPF calculation. 78 The program NETTRA-E3 represents what is called a multi-path application of the network transduction procedure using MEC. It is only slightly more complicated than NETTRA-E2, employing only one additional subroutine (although a few others are slightly modified versions of their counterparts in NETTRA-E2). To illustrate the difference between NETTEA.-E3 and NETTBA-E2, let 1 ,2 3 h E N be the given network (specified by input cards) and let IT, N , N , . .., N be the sequence of networks produced by NETTEA-E2 in arriving at the final solution In (a network from which NETTRA-E2 cannot extract further gates successfully). Each IT" is obtained from the preceding N by a single application of the network transduction procedure. In other words, NETTRA-E2 finds a gate v. for which the errors resulting from its removal from N J can be compensated by MEC, resulting in IT". However, in general, there are several different networks, N , which can be obtained from each IT"' by the removal of and successful compensation for several different gates, v.. While NETTRA-E2 accepts only the first network In that it discovers d can be obtained from KT , NETTRA-E3 searches for all networks N which can be obtained from N by the successful removal of (possibly) several different individual gates. Upon the discovery of each IF which can be obtained from N ~ , the new network IT is stored in a stack. After obtaining every possible W~ from W~ , NETTRA-E3 returns to the stack and selects the top network (generally a N , but possibly not--if for instance no N were obtainable from N ) and precedes just as it had for N , placing new networks in the stack as they are obtained. Thus NETTRA-E3 will produce a whole "tree" of solutions while NETTKA-E2 only produces a single "path" of solutions in this tree, 79 beginning at the root of the tree (i.e., the given network) and ending at a terminal node. Before attempting to further transform each network selected from the top of the stack, NETTRA-E3 prints out a description of its configuration (along with an identifying number and the identifying number of its "parent" network). When NETTRA.-E3 discovers the stack to be empty, it stops. The terminal nodes of the "solution tree" must be searched for in the printed output and the number of gates in their corresponding networks compared. In this way, the best solution (i.e., the network with the fewest number of gates) can be determined. Obviously, NETTRA-E3 will produce a solution as good as the best solution produced by NETTRA-E2, and it is quite possible that NETTRA-E3 may even produce a better solution. However, NETTRA-E3 generally requires much more computation time. (Apparently, without degradation of the results, the size of the tree could be reduced, and the computation time shortened, by terminating a branch whenever it is about to produce a network duplicating one already in the tree; but testing such a condition requires considerable computation time in itself. ) The size of the solution tree for a given initial network could be varied by several methods from the size of the particular tree obtained by the normal NETTRA-E3. All of these methods though, with the exception of one, require actual programming changes to NETTRA-E3. The one exception requires only a modification of the input cards. There is a parameter NEBV1AX on the input cards which specifies the maximum allowable number of "error-positions." In other words, when a gate v. is removed from a network N' producing a network N.' with a larger number of error-positions than NEPMAX, then MEC will not even attempt to compensate for the removal of v. . Normally, in NETTRA-E3 (and -E2, too), NEPMAX is set very high (to 2^ for a network with n external variables); however, setting NEPMAX to a low value (NEPMAX = 1 or 2 ) will limit the number of branches from each node of the normal (NEIMAX =2^ ') solution tree, resulting in a smaller tree (which, in this case, will be a subtree of the normal- sized tree). Another simple way to change the normal tree size (in this case, usually to increase it) would be to use the ordering P and thus omit the pruning procedure (associated with P, ) preceding the applications of MEC This would usually produce a much larger tree than the normal NETTRA-E3. (in this case, the smaller tree is usually not a subtree of the larger.) Of course, there are obviously many other ways to produce different trees, but it should be remarked that a larger tree does not guarantee a better solution, although it almost always guarantees a much longer computation time. In fact, it is easily possible that some smaller tree for a given network may produce a better solution than some larger tree. 5.3 Network Transduction Examples Example 5.3.1 . Table 5.3.1 and Figure 5.3.l(a-f) illustrate the initial, intermediate, and final configurations of a network at various stages during the execution of NETTRA-E2. The initial given network, obtained by a simple method for synthesizing 3- level networks realizing a desired function, consists of 25 gates and 100 connections. This is transformed, by NETTRA-E2 through a series of intermediate networks, finally arriving at a network of 11 gates and 37 connections which realizes the same function as the original network. 81 Table 3.3.1 Given Network for Example 5.3.1 Consisting of 25 Gates and 100 Connections Sate Level Gates or External Variables v. of v. Feeding v. 1 1 1 1 1 2 3 5 7 8 10 12 13 16 17 18 21 2 2 2 xl x2 x3 xk x5 3 2 xl x2 x3 x5 k 3 xl x2 x3 xU 5 2 xl x2 x3 1+ 6 3 xl x2 xk x5 7 2 xl x2 xk k 6 8 2 xl x2 . x5 6 9 3 xl x3 xk x5 10 2 xl xk x5 6 9 11 3 xl x3 xk 12 2 xl xk 6 11 13 2 x2 x3 xk x5 Ik 3 x2 x3 xk 15 3 x2 x3 x5 16 2 x2 x3 lH 15 17 2 x2 xk x5 6 18 2 x2 xk k 6 Ik 19 3 xl x3 20 3 x3 xk 21 2 x3 15 19 20 22 3 xl x5 23 3 x2 x5 24 3 x^ x5 25 2 x5 22 23 2k f(x jX^x ,x. ,x ) = 01001001111100110110001111001101 (a) Network after first application of network transduction procedure (an intermediate result of NETTRA-E2). Network consists of l6 gates and ^5 connections. Figure 3-3.1 Results by NETTRA-E2 for Example 5.3.1 83 ■p •H n . £ o ■H CD a o 0) [>- I" 8 * ft 0) g "S •H +3 O Pi "3 ^ w bO LA H p ^J Jh O Ss •p O o •H -P • ft <* ft ffi EH o O d 36 X X X \ X X [I \ £ £ T3 0) d c •H O O no fe 87 H en LT\ (L> H §■ as X K o CVJ m s w 4 >>Ph ,Q CO 10 -P H w CD K CM U Si P •H Ph co LTN 1] ho 3 •H H U & ° i ^ on 0) EH T3f M 1) T3 H t~- ON CO ro ro ro o VO ON -=r LTN OJ VO CO LTN W (U CJ CO C\) t- ro CO ro CO VO CO LfN H o t- H H ft a o VO Jt H rH OJ vo O VO CO CO O _=h CO OA OA H EH CD H H W W CO fl H O d -H d -P •ri ^ O o sg VO co! ON OJ on Ol ON OJ o ro ro LTN -3- ir\ OJ 3 LTN 0J O CO CO CO ITN CO £ O O +5 o CD o H H o H CO CO CO CO H H CO H ON LTN H ON ON 9 H H CO H H H -p s •• j CO CO 1 O CD 1 o -p i d 1 bO 1 1 1 i j 1 bO H Ph X X ! i i X X X X X X ! -H-C fn a 0) CC ; -dp : o o Ph X X X X X X X X w H pj d O •H -H Init ork nect LTN o J- CO c- & H H o O o t- H 00 ro H H CO ON H Ch -P O • • • • • • * • • • • • • • • • OJ CO ro LTN VO co CO t- O CD O OJ H ro OJ 0J CO OJ OJ S •• -p w CO CD O -p o d hD a o u •H 0) H OJ CO -=t LTN VO § s - 92 and attempted error- compensation) with the accompanying CSPF calculation including possible pruning of the network; (b) a modified NETTPA-E2 employing the ordering P which never alters the network prior to gate removal for MEC. The cost of the networks (number of gates and connections) and the times required to obtain these networks appear in the last columns. The functions labeled 1, 2, 3, h, 5, and 6 are all functions of exactly 5 variables. These functions are explicitly: f^ - ( 10011110011000 111011111001111111), f - (00001010100010001000000100000011), f = (0100100 1111100110110001111001101), f, = (10000101100011101100000111001011), f = (11010101100010101001111100010001), fg = (11011010000110000010111001010001). There are several interesting remarks and observations to be made about Table 5.3.2 The four results for function #2 all achieve a minimum number of gates, and three of the four achieve networks of optimal cost (optimality proved by a branch-and-bound program [12,13]). (An optimal network is defined as one having a minimum number of connections among those networks with a minimum number of gates. ) For function #h, three of the four results have a minimum number of gates, and two of them are optimal (optimality proved by program described in [13]). For the other four functions, optimal costs and minimum numbers of gate are unknown, so the results cannot be compared with them. However, for each of the functions #1, #3, and #6, NETTFA-E2 achieves (in the better case of each pair) a solution whose cost is (currently) the least among solutions by other methods tried (i.e., certain other transduction methods and a branch-and-bound program [13] limited to 20 minutes of computation). For 93 function #5, though, there is a known solution consisting of 9 gates and 28 connections (best solution by a branch-and-bound program [13] after 20 minutes of computation ) , but the best result by NETTRA-E2 consists of 11 gates. Also, in an earlier section, it was mentioned that neither the use of the ordering P in PROCCE nor the use of P (with its associated pruning) could be said to be better than the other. This is evidenced in Table 5.3.2 where, for functions #1, #5, and #6, NETTRA-E2 with P achieves a better result, and where, for functions #3 and #k, NETTRA-E2 with P proves better. The result for function #h by NETTRA-E2 with P is especially bad. Example 5.3.3 . This third example will illustrate the power of NETTRA-E3 (multi-path) over NETTRA-E2 (single-path). The initial network, realizing a U-variable function f = ( 1001011110101100 ), is pictured in Figure 5-3.2 along with an optimal network realizing the same function (optimal network from [2]). Beginning with that initial network of 12 gates, NETTRA-E3 produces, in 20.5^- seconds, the "tree" of solutions shown in Figure 5.3.3(a). In this case, NEFMAX has been set to 2 to limit the tree to a reasonable size (setting NEPMAX = 8 would give a tree of 8l networks). The notation r— used in Figure 5.3-3 means network number "a", consisting of 'V gates and "c" connections, and a line connecting a larger network with a smaller means the smaller is derived from the larger by PROCCE. In Figure 5.3- 3> it is important to notice that while some paths (i.e., sequences of networks obtained by repeated uses of PROCCE) lead to terminal nodes representing optimal networks, others lead to terminal nodes representing networks not very near to the optimal. o ubt It le NETWORK TRANSDUCTION BASED ON ERROR-COMPENSATION nciples of NOR Network Transduction Programs ■RA-E1, NETTRA-E2 and NETTRA-E3) 3. Recipient's Accession No. 5. Report Date June 1975 iof(s) ambayashi, H. C. Lai, J. N. Culliney, and S. Muroga 8. Performing Organization Rept. No. .irming Organization Name and Address rtment of Computer Science ersity of Illinois at Urbana-Champaign na, Illinois 6l801 10. Project/Task/Work Unit No. 11. Contract /Grant No. NSF-GJ-^0221 c design ;c circuits [cal elements : rans ( computers ) ntifiers/Open-Ended Terms nter- aided- design brk transduction brk transformation rr-compensation a-optimal networks rlssible functions |«AT1 F.e Id/Group permissible functions with errors NOR NAND CSPFE CSPF ^lability Statement Release Unlimited 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 108 22. Price ' S-JS I 10-70) USCOMM-DC 40329-P71 tf£ \«fl% . I,