— ■HiiiiiiiiiiHiaa gsarai iHi gig Hm IHH Bragg HI mmm I BlH HP*™ M SH* ysss ■HE LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 510.84 no. 480-489 cop. 3. &3 UITJCDCS-R-71-U83 coo 1*169-019^ A SYNCHRONIZATION SYSTEM FOR A TELEVISION BANDWIDTH COMPRESSION SCHEME by EDWARD ELLIS CARR October, I97I NOV 9 19T2 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS UIUCDCS-R-71-^83 A SYNCHRONIZATION SYSTEM FOR A TELEVISION BANDWIDTH COMPRESSION SCHEME by EDWARD ELLIS CARR October, 1971 Department of Computer Science University of Illinois Urbana, Illinois 61801 This work was supported in part by Contract No. Atomic Energy Commission AT(ll-l)l469 and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science, October, 1971* Digitized by the Internet Archive in 2013 http://archive.org/details/coefficientgener484chen Ill ACKNOWLEDGEMENT The author wishes to thank Dr. M. Faiman for his advice and council on preparing this thesis and Barbara Weeks for typing it. iv TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. THE NATURE OF THE SYNCHRONIZATION PROBLEM U 3. A SOLUTION TO THE SYNCHRONIZATION PROBLEM 7 k. CONCLUSION 19 LIST OF REFERENCES 2 LIST OF FIGURES Figure Page 1. TV Camera Scanning a Line Drawing 2 2. Video Signal for Line A 2 3. Analog Equivalent of the Video Line A 2 h. Transmitted Signal. • • 2 5. Block Diagram of the Orbit Synchronizing System 5 6. Orbit Receiver Clock 8 7. Orbit Receiver Clock Theoretical Timing Diagram 9 8. Orbit Sync Waveforms 10 9. Orbit Sync Waveform Generator 11 10. Field Code Waveforms ik 11. Orbit Sync Waveform Generator 15 1. INTRODUCTION This paper describes a synchronization system for a real time television bandwidth compression scheme called ORBIT (ONLINE REDUCED BANDWIDTH INFORMATION TRANSFER) . The ORBIT system is designed to transmit black-on-white drawings with an average bandwidth compression of twenty-five to one. It consists of a transmitting section, fed by a standard TV camera, and a receiving section, coupled to a conventional monitor. The system was proposed by Professor W. J. Poppelbaum and designed by Peter Oberbeck. The transmitting section contains a standard TV camera and encoding circuitry. Its operation is as follows. Assume the TV camera is scanning a line drawing, as shown in Figure 1. Then the video signal for the horizontal line labeled A will be as shown in Figure 2. The ORBIT transmitter circuitry encodes the times from the beginning of the line of video to each of the video pulses on the line and places the results in digital storage registers. Then, as the next line is being scanned, the transmitter circuitry retrieves, at equal time intervals , the information about the previously scanned line and converts it to an analog signal: the times t , t , t and t> of Figure 2 being converted proportionately into the voltages v , v , v and v, of Figure 3. Bandwidth compression is obtained because the transmitter redistri- butes the video information equally spaced in time during the scanning of the next line, since a lower bandwidth signal is required to resolve points spread out than points which occur at closely spaced intervals. The last step in the transmitter circuitry is filtering the analog voltage to remove the high frequency components. The resultant signal, as shown in Figure h t is transmitted via a wire to the receiver. r / Line Drawing C^ 71 Camera Figure 1 TV Camera Scanning A Line Drawing N * 1 2 ^ Horizontal Blanking Interval * Figure 2 Video Signal For Line A T" 1 r v 2 V. V, Horizontal Blanking Interval Figure 3 ■ Analog Equivalent Of The Video Line A Figure k Transmitted Signal The ORBIT receiver consists of decoding circuitry and a standard TV monitor for displaying the picture. The decoding circuitry contains an A/D converter, storage registers and a comparator circuit which drives the monitor. The incoming video signal is sampled at the correct intervals and converted to digital information. This information, which represents the time intervals for the video pulses on a line, is stored in registers. As the next line is received, the digital counts for the first line are compared sequentially "by a digital comparator with a counter which is being driven by the receiver clock. When a comparison between the contents of a register and the counter is detected, the comparator drives the moni- tor which displays a point of the line. Trie ORBIT system, as presently designed, can handle line drawings with up to 32 intersections per horizontal line. 2. THE NATURE OF THE SYNCHRONIZATION PROBLEM As mentioned in the Introduction, the average video signal bandwidth for ORBIT is compressed about twenty-five to one. However, until this project was completed the receiver monitor was driven by using the RETMA sync waveform output of the transmitter camera, and the receiver cir- cuitry was driven by the transmitter 9-^5MHz clock, which is used to sample and digitize the camera video. Obviously, it does no good to reduce video signal bandwidth in the information channel if the 9A5MHz synchronization signal bandwidth cannot also be reduced. One can see that the sync problem has two parts. One is the pro- blem of driving the receiver monitor in synchronization with the television camera in the transmitter section. The second is the establishment of the correct interrelation between the information encoded in the transmitter and decoded in the receiver. In order to synchronize the receiver monitor, the incoming line frequency must be detected. In addition information indicating the end of an even and odd field is necessary. The incoming video line frequency is obtained from the fundamental period of Figure k by circuitry diagramatically illustrated in the top left corner of Figure 5. The output of the VIDEO TO SQUARE WAVE CONVERTER is used to generate a pulse which indicates the start of each line. A detailed description of this operation will be given later. The information indicating the end of an odd or even field, which is necessary for interlacing, is encoded in the video signal. The scheme used is for the transmitter to hold the last line of an odd field and the last line o> H c 3 N 0. c o> o c JC JC u c c o >> if) E 03 k. .t: •" o o ^ 5 5 > O 4) T> O *— O 0> in ■^ 0) 01 cr n- 01 ■o k. o 01 o c D "O o 01 o Li. I T _ c * us at ha UJ K o •o c 4; o o La o> o < 1 c ■o T3 0> O 01 il 01 k. ■o o o *- u o ^ s 0) 0> il ^ I >N O i_ c a> a> — r> -Q ?J u. J § -p ca !>> bO fl •H N •H O o >> -P ■B o o u bjj •H Q pq 01 bD •H if and a half of an even field at ground. This code is detected by the cir- cuitry of the central regions of Figure 5, The circuitry remaining in the lower right corner of the figure serves to generate the required monitor signals. The transmitting section of ORBIT uses a 9-^5MHz clock which pro- duces a 600 count line (9- U5MHz/600 = 15.75kHz - the line frequency). The first 512 counts are used to digitize the video, i.e. to determine the posi- tions of the intersections in the line being transmitted, and the remaining counts are used to define the horizontal synchronization interval. Since the receiver must determine the positions of the intersections from the encoded signal, it was initially thought that there should be a 9«^5MHz clock to digitize this encoded signal. Thus, considerable effort was initially directed in this area. However, the sampling frequency for digitizing the video signal only needs to be approximately the same as the corresponding frequency in the transmitter, owing to the relative flatness of the video signal at the sampling points. Therefore, a clock which has an accuracy of about 1% but is quite stable and capable of being restarted in the same phase at the beginning of each line, is all that is necessary. 3. A SOLUTION TO THE SYNCHRONIZATION PROBLEM The understanding of the requirements for the receiver led to the design of the clock circuit shown in Figure 6. The circuit comprises an SN7^122 retriggerable monostable multivibrator with clear and four inverters, The inverters, together with the internal delays of the monostable, pro- vide for the logical "0" state of the clock. The theoretical timing diagram for the clock circuit is shown in Figure 7- Clear is initiated by the negative edge of the Clear and Trigger signal from the VIDEO TO SQUARE WAVE CONVERTER. The first clock pulse of a line is generated by the positive edge of the Clear and Trigger signal. Subsequent clock pulses are formed by Retrigger which is merely Q delayed by UOns. The delay times shown in Figure 7 are the average delay times for the devices found in integrated circuit data sheets. In actual operation this clock has a period of 106ns and provides the receiver with a 600 count line. The solution to the problem of synchronizing the receiver monitor was accomplished by designing a sync waveform generator; its components occupy two printed circuit boards. The first board contains a circuit which produces a 15,750Hz reference square wave for controlling the receiver clock and, in addition, detects the odd or even field code for the monitor sync system. This circuit is shown in Figure 8. Its operation is best described by referring to the waveforms in Figure 9- Waveform 2 in Figure 9 shows the last five lines of video of an even field from the ORBIT transmitter. Consider this waveform to be applied to the input pin 3 on the circuit In Figure 8. The Clear and Trigger 2pf 5.1K Hr— rAAAri SN7404 Figure 6. Orbit Receiver Clock t=0 Clear And Trigger Q Retrigger 1_ r i_ Start of a Horizontal Line Figure 7. Orbit Receiver Clock Theoretical Timing Diagram 10 o s o a >> CQ -p •H O CO •H A . Igsi 2 ^ oz L 32 v UJ 5d J 11 CO .§ u o I (0 ■J "O0_ C o rr, <_> c u. >o T3 M 0) X 0) c s T3 a> N >i3 m as CO ^2 -J .2 o c a> oj "O > to Q. c CTc UJ c= C CO x cr cz e o CO En UJO a) u. a> ■o -o •o o OO o O N I in *— i ro £t> >• o co ii: Sir C i. >- o cou. TJ i) 0) u Li_ u 0) c c h >» c >> CO CO "O > T) n UJ o o o ^_ o ^„ 1^ a> *_ 0> h» in a> a> a> a> > a: > 12 uATlOC comparator outputs a "l" or "0" according as the video input is above or below ground. This logic signal is inverted and level-shifted to conform to the ORBIT receiver logic levels (ground = "l", -5V = "0") by the 2N3905 transistor. The inverted logic triggers an SN7^121 monos table multivibrator which produces a 15,750Hz square wave (Figure 9, waveform 3). This, in turn, is used to produce the Clear and Trigger pulse for the receiver clock and to generate the odd or even field code pulse. Odd or even field information is necessary for interlacing, as mentioned previously. The logic level output, from the collector of the 2N3905, result- ing from the application of waveform 2 to the comparator is shown by waveform k. This signal, called Video Logic, is applied to a NMD gate together with alps pulse which is triggered from the rising edge of wave- form 3. The resultant output is Even Field Code for input waveform 2. In a similiar manner the resultant output is Odd Field Code for input waveform 1. Even field code and odd field code waveforms are shown by waveforms 5 and 6 respectively. After the field code is generated, it drives a counter and a reset circuit. The counter is composed of an SNT^T3 dual J-K flip-flop; its clock input is driven by Field Code. A reS et pulse, when the field code indicates the end of an even field, is produced by using two SN7^121 monostables in series followed by a NAND gate. The latter has as its output Field Code Reset, The way the reset circuit works is by causing the first pulse of the even field pulse code to be delayed by exactly one horizontal line time plus 1 ys. Due to a property of the monostable, this delay causes the second pulse to be ignored by the first monostable. After the first monostable has timed out, 13 it fires a second monostable which reaches its logical "l" state before the first monostable times out, the two inputs to the NAND gate are both "l" , and the resultant signal is the desired counter reset pulse. The time at which reset occurs and the resulting states of the counter are shown in Figure 10, waveforms 2 and 3. The positive edges of the counter outputs ;£, and Qo > are used to S enerate the appropriately timed sync reset pulses shown as outputs in Figure 8. The timing and distribution of the reset pulses are best explained by first understanding the operation of the second circuit board of the sync waveform generator. Figure 11 shows the circuits on the second circuit board. These generate the EETMA standard sync signal. The signals shown in Figure 9 (waveforms 8 and 9) detail the sync waveform for odd and even fields respec- tively. The sync waveform is divided into four intervals, as labeled on Figure 9, waveform 8. It is formed by generating signals which define the four intervals and using them to gate the required signals from the appropriate monostable multivibrator. Since the equalizing and vertical sync pulses are required to occur at a 31.5kHz rate, a clock having this frequency was needed to trigger these monostables. The simplest way to do this was to use the 15,750Hz reference signal to trigger tvo SN7^121 monostables and gate their outputs. One monostable is triggered on the positive edge, and the other is triggered on the negative edge of the 15,750Hz reference square wave. The 31.5kHz clock signal is shown in Figure 9> waveform J. The sync intervals are determined by modulo 6 and modulo h counters comprising negative edge triggered SN7^73 and SN7H76 J-K flip-flops. The sync waveform J Ik 32 a> c a> > LU (7). 5 a> ■a •o O o 00 J CO 0) 3 0) CO O k- a> o a> £ o o 0) "D o o o O a*) T3 o waveforms 10 and 11 respectively. Observe that the positive edges of the two waveforms occur between two edges of a clock pulse. The task of interlacing the odd and even fields is accomplished by controlling the clear and preset inputs to the SNT^T^ flip-flop which triggers the horizontal sync monostable. If the flip-flop is preset at the start of the vertical sync interval, the negative edge of the signal from the flip-flop will trigger the horizontal sync monostable one full line after the end of the vertical sync interval. If the flip-flop is cleared, triggering will occur one half line after the end of the vertical sync interval. This control of the horizontal blanking monostable causes the correct interlace. 18 Vertical blanking is provided by a monostable which is triggered by the positive edge of Vertical Sync Reset. 19 CONCLUSION A synchronizing system has been designed to provide the ORBIT system with its full capability for bandwidth compression unimpaired by any high frequency synchronization channel. The understanding of the clock synchronizing circuitry, in particular, led to the design of a very simple circuit to provide the ORBIT receiver with a proper time base. The system described in this thesis has been built and is functioning correctly. 20 LIST OF REFERENCES 1. Oberbeck, P. E. R., "ORBIT: ONLINE REDUCED BANDWIDTH INFORMATION TRANSMISSION", Report No. ^30, Department of Computer Science, University of Illinois, Urbana, Illinois, February, 1971. 2. Integrated-Circuit Sync Generators , Technical Manual 6x-^39, Cohu Electronics, Inc., 19^6. 3. TTL Integrated Circuits Catalog , Dallas, Texas, Texas Instruments, 196^ : orm AEC— 427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) I, AEC REPORT NO. coo 1^9-0194 2. TITLE A SYNCHRONIZATION SYSTEM FOR A TELEVISION BANDWIDTH COMPRESSION SCHEME 3. TYPE OF DOCUMENT (Check one): [5] a. Scientific and technical report I I b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): fc~l a. AEC's normal announcement and distribution procedures may be followed. ~2 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. "2 c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 5. SUBMITTED BY: NAME AND POSITION (Please print or type) Edward Ellis Carr Research Assistant Department of Computer Science University of Illinois Urbana, Illinois 61801 Signature Edward Ellis Carr Date October, 1971 FOR AEC USE ONLY . AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: I I a. AEC patent clearance has been granted by responsible AEC patent group. I I b. Report has been sent to responsible AEC patent group for clearance. I I c. Patent clearance not required. I = Hi UNIVERSITY OF ILLINOIS-URBANA UN.'VEHS.TYOF.UL.NO.S-URBANA *M 1 2 088400061 ■ l l"^s ■ H 1 ■ ? I ^r ■■#' ■ ■ i ■ ■• i I * iM. I I I ^^^1 I I ?^t Jl 3 J