12 (,» J7]M umcDcs-R-7^-623 OPTIMAL NETWORKS WITH NOR-OR GATES AND WIRED-OR LOGIC by Tsuneo Kawasaki January I97U DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS UR8 W CHAMPAfGN Digitized by the Internet Archive in 2013 http://archive.org/details/optimalnetworksw623kawa UIUC DC S-R- 7^-623 OPTIMAL NETWORKS WITH NOR-OR GATES AND WIRED-OR LOGIC by Tsuneo Kawasaki January I97U Department of Computer Science University of Illinois at Urbana- Champaign Urbana, Illinois 6l801 This work was supported in part by the National Science Foundation under Grant No. GJ-^0221 and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science, May 197^. Ill ACKNOWLEDGEMENT The author would like to express his deep gratitude to his advisor, Professor Saburo Muroga, for his enthusiastic guidance and encouragement during the preparation of this thesis, and also for his careful reading and valuable suggestions for the improvement of the original manuscript. The author wishes to thank Dr. Y. Kambayashi for his many suggestions. He also thanks his colleague, J. N. Culliney, H. C. Lai and K. R. Hohulin for their variable suggestions. This work was supported in part by the National Science Foundation under Grant No. NSF-GJ-40221. ABSTRACT Generally, Emitter Coupled Logic (ECL) gates have dual outputs (i.e., NOR-OR) and the outputs of two or more ECL gates can be tied together to realize OR functions without extra gates. This is called Wired-OR. Using gates with dual outputs and Wired-ORs, an algorithm to get the optimal networks, i.e., those which have a minimum number of NOR-OR gates and, as the secondary objective, a minimum number of connections, for a given arbitrary function, is discussed in this paper, under the assumption that only non-complimented variables are available as the network inputs. Only NOR-OR gates are used in these net- works, but this algorithm can also be applied to networks with NAND-AND gates and Wired-ANDs. First, the algorithm derives all networks which have a minimum number of NOR gates, using NOR gates only, and next it obtains all possible OR outputs of gates in the NOR network such that OR output can be connected to a successor gate with- out changing its output valve but with replacing its inputs by this connection. Finally, it forms Wired-ORs in the resultant network with NOR-OR gates. Thus the optimal network for the given function has been obtained. Based on this algorithm, optimal networks for all func- tions of three variables and also some functions of four vari- bles are found. 1 IV TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. BASIC PROPERTIES AND PROCEDURE OUTLINE 4 3. LOGICAL DESIGN PROBLEMS BASED ON INTEGER PROGRAMMING FORMULATION 21 4. ALGORITHM FOR THE DERIVATION OF OPTIMAL NETWORKS WITH NOR-OR GATES AND WIRED-OR LOGIC 26 5. COMPUTATIONAL RESULTS BY THE ALGORITHM 34 6. CONCLUSION 43 LIST OF REFERENCES 45 APPENDICES 4 7 1. INTRODUCTION One of the major objectives in logical design of dig- ital networks is the derivation of optimal networks. The optimality of a network is usually defined as the minimization of the number of gates, connections, levels, the chip area for an integrated circuit (IC) , or others. In this paper, using Emitter Coupled Logic (ECL) gates in ICs which have NOR-OR functions as their dual outputs and assuming that all external variables are non- complemented, logical design problem of optimal network is discussed, permit- ting the use of Wired-OR logic defining the optimality as the minimization of the number of gates first, and the number of connections next. Also optimal networks with ECL gates are derived for all switching functions of three variables and also functions of four variables which can be implemented with five or less NOR gates. The algorithm for this logical design prob- lem consists of three phases as follows: Phase 1 : All the networks consisting of only NOR gates in which the number of NOR gates is minimized without necessarily minimizing the number of connections are derived by Y. Kambayashi using the logical de- sign procedure based on Integer Programming (IP) (2M5) (8H12) formulation developed by Muroga et. al. In this phase, all the NOR networks for each function are synthesized. The basic nature of the IP formula- tion is to model the network using linear inequal- ities where the unknowns in these inequalities as- sume the value or 1 , which represent the absence or presence of a connection, respectively. Each solution of these inequalities corresponds to a network. This is a 0-1 IP problem. Phase 2 : All the OR output of gates such that the OR out- put of each gate can be connected to a successor gate without changing its output value but with re- placing its inputs corresponding to that OR output are exhausted by checking every pair of the OR out- put of a gate and a successor gate in each NOR net- work obtained in phase 1. Then the connections from those OR outputs actually replace the corresponding input connections in the successor gate in the orig- inal network in order to reduce the number of con- nections in the network. (See Figure 2.1 where the connections to gate k from the inputs to gate j in (a) are replaced by the OR output of gates j , as shown in (b) ) . Phase 3 ; Wired-ORs which are formed by tying down some con- nections without changing the output values of gates to which these connections go are exhausted by checking every set of connections in each network obtained in Phase 2. Then the optimal networks for each function has been exhausted. Wired-ORs are formed as follows: If output of some gates and/or some external variables are connected to only the same set of gates, (Figure 1.1 (a)), we can form a Wired-OR as shown in Figure 1.1 (b) . 3 <>-' (a) Figure 1.1 — A Wired-OR A Wired-OR (b) Compared with the design approach which derives the optimal network of NOR-OR gates with Wired-ORs by the IP formulation only, this approach reduces greatly computer time. It took 200 seconds (IBM 360/75) for all switching functions (77 representative functions by P-equi valence excluding triv- ial functions) of three variables, and 130 seconds for func- tions (312 representative function by P-equi valence) of four variables which can be implemented with five or less NOR-OR gates. 2. BASIC PROPERTIES AND PROCEDURE OUTLINE Let us describe basic properties in each phase in more details. 2.1 Phase 1 ; Solution of the logical design problems based on the IP formulation. In Phase 1, all networks which have the minimum number of NOR gates but where a number of connections is not necessar- ily minimized (i.e., all networks with a minimum number of gates no matter whether they have a minimum number of connec- tions as the secondary objective) are obtained for each function by solving the logical design problem based on the IP formula- tion which is discussed in the next chapter. 2.2 Phase 2 : Derivation of OR-output-to-gate connections. (A) In each of the networks derived in Phase 1, gates generally have inputs from NOR outputs of the other gates and/or ex- ternal variables. If gates j and k share the same inputs like Figure 2.1(a), the three inputs to gate k may be (a) (b) Figure 2.1 — OR-output-to-gate connection replaced by a single connection from the OR output of gate j like Figure 2.1(b). Generally i-1 connections are elim- inated if two gates j and k share i inputs in Figure 2.1. If gate j has only one input (i.e., 1=1), the number of connections does not change. But this connection is still a candidate of OR-output-to-gate connection by the follow- ing reason. When we consider Wired-ORs, the OR output corresponding to this input can be an input to a Wired- OR which is to be considered in Phase 3. (See Figure 2.2), x A Wired OR 3^; xvy Figure 2.2 — The OR output from a single input gate (B) A gate k can have inputs from the OR outputs of other gates under the following three restrictions. Restriction 1 : (i) Gate k must have two or more inputs. If gate k has only one input, in other words, the OR output of another gate j is connected to gate k like Figure 2.1(b) to replace the connection from the input of gate j to gate k, these two gates have the same output functions, (i.e., NOR and OR outputs) and one gate is redundant. (See Figure 2.3). Figure 2.3 — A redundant gate (ii) Inputs of gate k must not be connected from the OR outputs of its successor gates or itself to avoid a loop (See Figure 2.4) . ■* Figure 2.4 — Loop-free networks (iii) Inputs of gate k must not be connected from other gates whose NOR outputs are already connected to gate k. This is because the output of gate k becomes always "0" (Figure 2.5) . A * Figure 2.5 — The Output of gate k is always "0" (C) All the possible OR-output-to-gate connections are derived by checking every pair of the OR output of a gate and a successor gate such as gates j and k in Figure 2.1(b). Some gates have a possibility to have only one input from an OR output, and some other gates have possibilities to have two or more inputs from OR outputs. But in all of these cases we do not necessarily replace the input connections to the successor gate by the corresponding OR-output-to-gate con- nections to reduce the number of connections. The reason for this is as follows: If a gate k has a possibility to have only one input from the OR output of gate j s , and if this OR output is inputs to other gates as shown in Figure 2.6(a), we w x (a) 14 connections (b) 13 connections Figure 2.6 — Some gate should keep original inputs can derive a Wired-OR for the inputs to the other three succes- sor gates unless we replace the inputs to gate k s by OR-output- to-gate connection from gate j as shown in Figure 2.6(b). The number of connections in the network in Figure 2.6(b) is smal- ler than that in (a) . So gate k should not have an input from OR output but have original inputs. Consequently, we have to further check every OR-output-to-gate connection later in sec- tion 2.3 (B) to find out whether a Wired-OR instead of the OR- output-to-gate connections can reduce the number of connections. If a gate has possibilities to have two or more inputs from OR outputs , these OR-output-to-gate connections have the same problem, as illustrated in Figure 2.7. If gate k has two A Wired OR (a) Connections in class i 18 connections (b) Connections in class i < 17 connections Figure 2.7 — The set in class is should be chosen inputs from OR outputs of gates j _ and j _ , a Wired-OR can not be formed for inputs of the other three gates (See Figure 2.7(a)). But if gate k has only one input from the OR output 9 of gate j . , a Wired-OR can be formed for inputs of the other ml three gates as shown in Figure 2.7(b). This reduces the number of connections in the entire network, though the number of in- puts of gate k increases . Therefore we divide all the gates in the network into three sets of gates S, M, and the remainder in order to facil- itate our checking OR-output-to-gate connections to find out whether Wired-ORs can reduce the number of connections. Set S consists of gates each of which has a possibility to have only one input from an OR output like gate k s in Figure 2.6 (a) , and set M consists of gates each of which has possibilities to have two or more inputs from OR outputs like gate k in Figure 2.7. If a gate has a possibility to have Ro inputs from OR Ro outputs, then there are 2 -1 possible ways to replace the cor- responding inputs of the gate by the OR-output-to-gate connec- tions, where Ro is the number of the OR outputs. Examples are 2 shown in Figure 2.8 for Ro =2, and there are 2-1=3 possible (a) class 1 (b) class 2 (c) class 3 Figure 2.8 — All possible ways to replace by two OR-output-to-gate connections 10 ways to replace the corresponding inputs by OR-output-to-gate connections like (a) , (b) , and (c) . If we do not consider Wired-ORs, the connection configuration in (a) should be chosen because the number of connections is the minimum among these three connection configurations, (a), (b) and (c) . But when we consider Wired-ORs as we will in the next section, some OR-output-to-gate connections must not replace the cor- responding inputs like the case of the OR output of gate j ^ in Figure 2.7 (b) , even though the number of inputs of gate k increases. Since the above trade off between Wired-ORs and OR-output-to-gate connections differs with different connection RO configurations, we classify these 2 -1 connection configur- ations according to the number of all the input connections to gate k , as follows; class 1 is the configurations in each of which gate k has the minimum number of connections (i.e., the 3 m minimum compared with the numbers of connections of other con- nection configurations of the gate k ) , class 2 is the config- uration in each of which gate k has the second minimum of 3 m connections, and so on. Thus in Figure 2.7 a set of connections in class i_ should be chosen rather than a set of connections in class i, though i < i_. Thus we have to consider which class of connections has the minimum number of connections in the Ro entire network, by taking into account Wired-ORs. 2 -1 is a fairly large number even if Ro is small, and it is tedious to derive Wired-ORs. 11 Suppose gate k has different configurations of con- nections from OR outputs and these configurations are differ- ent classes. Then if we keep only connection configurations satisfying the next restriction discarding other connection configurations, we can decrease the number of connection con- figurations to be considered such that the scope of later search for optimal networks is narrowed down. Restriction 2 ; (i) Choose a connection configuration in class 1 if every connection configuration has no OR outputs connected to any Wired-OR. This is because we do not need to take into account Wired-ORs in this case, and class 1 is a configuration in which gate k has the minimum number of connections. (ii) Otherwise, choose every connection configuration which has OR outputs connected to any Wired-OR and also satisfy d > discussed in the following. This is be- cause if a connection configuration in class i (i > 1) has OR outputs connected to any Wired-OR, there is a possibility that the number of connections in the con- nection configuration in class i becomes smaller with Wired-ORs than the number of connections in the connection configuration in class 1. The number of connections for a Wired-OR with k. inputs and k 2 outputs is counted as k, + k, - 1. (We will discuss in 12 the next section why the number of connections for a Wired- OR is counted as k. + k. - 1.) If we do not use this Wired- OR, k. x "k connections are required. So we can reduce the number of connections by at most k, x k - (k + k_ - 1) using this Wired-OR. But the number of connections to gate k in- r m creases by using this connection configuration in class i in- stead of the connection configuration in class 1. Let us as- sume this increase to be k . Let us define d as: c d = k 1 x k - (k. + k_ - 1) - k 12 12 c d is the maximum number by which we can reduce the number of connections in the network by using this connection configur- ation in class i instead of the connection configuration in class 1. Thus, if the number of connections is reduced by Wired-ORs, d > must hold. 2.3 Phase 3 : Derivation of Wired-ORs Let us discuss basic properties in (A) and (B) first. (A) The following properties about the effects of use of Wired-ORs are known. The networks obtained by Phase 1 consist of only NOR gates and Phase 2 was applied to all NOR gates except the network output gate (gate 1) . First notice that Phase 2 obviously does not change the number of gates, though the number of connections may be reduced. Theorem 1 shows that the number of gates is still not reduced even when Wired-ORs are considered to all NOR-OR gates except the network output NOR gate. 13 Theorem 2 shows a basic property when a Wired-OR is con- sidered to only the network output NOR gate, if the net- work output gate has the NOR output only. Theorem 1 The number of NOR-OR gates in any network con- sisting of NOR-OR gates only without Wired-ORs which has a minimum number of NOR-OR gates can not be reduced by using Wired-ORs whose outputs are connected to NOR-OR gates, but not using Wired-ORs whose outputs are connected to the network output terminal. The number of connections in the network may be reduced. Proof Assume that there exists a network which has fewer NOR-OR gates by mixing with Wired-ORs whose outputs are connected to NOR-OR gates than a network without Wired- ORs which has a minimum number of gates. Change all the Wired-ORs such as (a) in Figure 2.9 to ordinary input con- nections in (b) . In this conversion, no NOR-OR gate is add- ed but some connections are added, so the new network without t> i (a) (b) Figure 2.9 — Conversion of a NOR-OR network 14 Wired-ORs have fewer NOR-OR gates than the network with a minimum number of NOR-OR gates without Wired-ORs. This contradicts the assumption that the network with a mini- mum number of NOR-OR gates without Wired-ORs has the min- imal number of gates. The number of connections may be reduced by going from (b) to (a) . Q.E.D. Because of Theorem 1, the number of gates is not changed by Part 1 of Phase 3 . But since the reduction of the number of connections is different for a different function in Phase 2 or 3, we considered all networks with a minimum number of NOR gates but without minimizing the number of connections in Phase 1. Theorem 2 If an optimal NOR-OR network without Wired-ORs realizing function f consists of R - 1 NOR-OR gates and if the network output gate has the NOR output only, an optimal network realizing the same function using NOR-OR gates and only a Wired-OR connected to the network output No Wired-ORs connected to any other gate) may have at most two less gates, the number of connections may also be reduced, and there exist functions which consist of exactly R - 2 NOR-OR gates in their optimal networks. Proof If optimal networks without Wired-ORs for f and 1" require R , and R _ NOR-OR gates (including the network output gate which has the NOR output only) , respectively then |r n - R -I < j holds, because a network realizing nl n2 — ' 15 f or 1 can be obtained by connecting one extra NOR gate to the network output gate of an optimal network without Wired-ORs realizing 7 or f, respectively. Suppose the network for f without Wired-ORs has R _ = R _ + 1 NOR-OR nl n2 gates (including the network output gate which has the NOR output only) . The network realizing f is obtained by replacing the network output gate of an optimal network for f taking into account a Wired-OR, and this network requires R - 1 NOR-OR gates. This means that the net- work for f requires R . - 2 NOR-OR gates. Since Wired- ORs other than the Wired-OR whose output is connected to the network output do not reduce the number of NOR-OR gates as stated in Theorem 1, this number R . - 2 is the ^ nl least possible result. Q.E.D. Theorem 1 is still true even if "NOR-OR" in the state- ment is replaced by "NOR. " Since Wired-ORs are not ordinary gates physically, Wired- ORs shown in Figure 1.1 should satisfy the following re- strictions. Restriction 3 ; (i) If an input of a NOR-OR gate is connected to a Wired- OR, that input cannot be connected to other gate, other Wired-ORs or the output terminal. (ii) If an external variable is connected to a Wired-OR, it cannot be connected to any gates, any other Wired-ORs or the output terminal. 16 (iii) A Wired-OR can not be connected to any other Wired- ORs. (B) Next, we define how to count the number of connections for a Wired-OR. Suppose we have a network shown in Figure 2.10 (a). Out of this connection configuration, we can form Wired- ORs as shown in Figure 2.10 (b) and (c) . Each Wired-OR in these examples has three inputs and goes to three gates, From the original network (a) which requires nine connec- tions, we get network (b) consisting of six connections. ■o- (b) (a) N (c) Figure 2.10 — Examples of a Wired-OR 17 Generalizing this conversion, we can form a Wired-OR consisting of k. + V connections generally for a set of connections from k.. inputs going to k ? outputs which require k.. x k connections. Network (c) which consists of five connections is also feasible. For this connec- tion configuration, we get a Wired-OR consisting of k 1 + k 2 - 1 generally. If we assume that this network (c) is located on a single IC chip, this counting method of the number of connections may be reasonable. It is very dif- ficult to define the way of counting the number of con- nections for a general case . But counting as shown in the case (c) would be one of reasonable definitions, and this counting is used in this paper. Therefore, the num- ber of connections required by a Wired-OR which has k. inputs and k. outputs is k + k - 1. Next, let us discuss the algorithm in detail. (C) At first in phase 3, Wired-ORs whose outputs are connected to only NOR-OR gates but are not used as network outputs are derived using networks obtained by Phase 2. If R k denotes the number of gates which have a possibility to have at least one input from OR output in each network obtained by Phase 1, 2 R k - 1 possible new networks can be derived by Phase 2 from each original network obtained by Phase 1 by replacing or not replacing by OR-output-to- gate connections. Thus we have to check whether the total number of connections can be reduced by considering Wired- 18 ORs in each of all 2 k possible networks, i.e., 2**k - 1 new networks and one original network. So we have to check R, gates in each network to exhaust all Wired-ORs, and totally 2k x R, gates in each original network ob- tained by Phase 1. But we can reduce this number of The- orem 3. Theorem 3 If R, denotes the number of gates which have a possibility to have at least one input from OR output in each original network obtained by Phase 1, we need to check only 2 jc - 1 + R, gates for each original network to exhaust all Wired-ORs (instead of 2Hc x R, ) , by intro- ducing a K bit down-counter . This K bit down-counter is used for deriving all 2 Hk possible networks in the following manner: Each count shows the status of each of 2Hc networks such that each bit shows the status of each of all R gates; bit value "1" means that some inputs of the gate corresponding to the bit position are replaced by OR-output-to-gate connections and bit value "0" means that the inputs are not replaced by OR-output-to-gate connections but connected from the inputs of the gates as obtained by Phase 1; the count (0, 0, . . ., 0) denotes the original network. Proof An example of this down-counter is shown in Figure 2.11. Initially all bits are set to "1." This means that some inputs of each gate of all R, gates in the network corresponding to this count (1, 1, . . ., 1) are replaced by OR-ouput-to-gate connections. We need to check R, 19 Gate #. R R -1 ... 54321 1 ... 01101 When we have a count as shown above , for example, some inputs of gates 1, 3, 4 . . . and R, are re- placed by the respective OR-output-to-gate con- nections , and any inputs of gates 2,5, . . . and R - 1 are not replaced by OR-output-to-gate con- nections but connected from the inputs of these gates as obtained by Phase 1. Figure 2.11 — A R, bit down-counter gates for this network to exhaust the possible Wired-ORs. The remaining 2 Tc - 1 possible networks are derived by the counts of the counter by counting down one by one . The down-count has the basic property that exactly one bit is changed from "1" to "0" in each down-count, even though more than one bit may be changed from "0" to "1." For each of these 2k - 1 possible networks , we need to check only one gate whose corresponding bit of the R, bit counter is changed from "1" to "0," to find whether a Wired-OR can reduce the number of connections when the inputs of the gate is not replaced by the corresponding OR-output-to-gate connection. But we do not need to check the gates whose corresponding bits are changed from "0" to "1." This is becuase we want to check whether Wired-ORs 20 can reduce the number of connections in each network of 2 k - 1 possible networks and because since gates whose corresponding bits are changed from "0" to "1" (this means that the original inputs to each of these gates will be replaced by OR-output-to-gate connections) were already checked in the initial network corresponding to the count (1, 1, . . ., 1) to find whether Wired-ORs can reduce the number of connections, there is no possibility to derive any new Wired-ORs which reduce the number of connections. Therefore corresponding to each count-down, we need to check only one gate for each network of the remaining 2 k - 1 possible networks. This means checking 2Hc - 1 x R gates totally, i.e., R gates for the initial network and 2k - 1 gate for the succeeding 2k - 1 net- works. Q.E.D. An up-counter can also be used for this purpose. (D) Secondarily, a Wired-OR whose output is used as the net- work output is derived by Theorem 2. (E) Finally, networks which have the minimum number of NOR- OR gates first and the minimum number of connections sec- ond are derived among all networks for a given function, simply by counting the numbers of gates and connections in each network and comparing them. 21 3. LOGICAL DESIGN PROBLEMS BASED ON INTEGER PROGRAMMING FORMULATION The Integer Programming (IP) problems dealt with in this paper are so-called - 1 IP problems and formu- lated to calculate all networks with the minimum number (R ) n of NOR gates for a given function f. No fan-in and fan-out restrictions are assumed in this paper. 3.1 Representation of a NOR network with inequalities^ Assuming that the network synthesis problem has n ex- ternal variables X., X_ , . . . , X , all of the 2 possible in- put vectors must be considered. For convenience each of the •» . -*(i) input vectors X = (X-,, X~ , . . . , X ) is numbered as X J (j = 1, 2, 3, . . . , r = 2 n ) from X (1) - (0, 0, . . . , 0) through -*(r} k X (1, 1, . . ., 1). Let W. represent the connection from k external variable X. to gate k. If W. = 1, the connection exists. If W. =0, the connection does not exist. Let the connection from gate i to gate k (i ^ k) be denoted by a.. . The connection exists if a., =1 and does not exist if a.. = 0. lk ik Let P. ^ denote the output value of gate i for input vector X (d) . Finally, let 3-i J) = a., P. (j) (3.1) ik ik l (i) Inequalities for a network Using the preceeding definitions, inequalities char- acterizing a network with R NOR gates are as follows: 22 n R Z W* x{ j) + Z B. ( ^ > 1 - UP^ j) (3.2) 1=1 L L i=l 1K ~ K n R -Z W* X. (j) - Z U ^iV - U (1 - P^ j) ) (3.3) 1=1 L 1 i=l 1K * where j = 1, 2, 3, . . ., 4=2 n and k = 1, 2, 3, . . . , R Here U is a positive number large enough so that inequal- ity (3.2) is non-restrictive if P^ = 1 and inequality (3.3) is non-restrictive if P^ = 0. We assume that gate 1 is the network output gate, so P^ j) = f R (X (j) ) (3.4) Inequalities for possible combinations among all the gates are necessary for the entire network. Thus all connec- tions but inequalities for preventing loops are included. (15) This is called "all-interconnection formulation." (ii) Inequalities for B-, = ol.,P. 3 ' ^ lk lk l As can be easily seen, the non-linear equality (3.1) can be replaced by the following linear inequalities: -P. (j) - a,, + B. f , j) > 1 (3.5) i lk lk — P i j) + a ik - 23 ik ) - ° (3,6) where i = 1, 2, . . .,R,k=l, 2, . . . , R (i^k) and n n (iii) Restrictions on inputs and outputs 23 Each gate except the network output gate must have at least one input from the external variables or from other gates, becuase we do not need any gates which have no inputs. Thus I wj +? a. > 1 (3.7) 1=1 - 1 i=l 1K where k=2, 3, ...,R. n All gates except the network output gate connect to at least one other gate. Thus _, K n Z a, . > 1 (3.8) j=l k ^ " where k=2, 3, 4 , . . ., R n The following three inequalities are powerful for speeding up the computation, (iv) Triangular condition. Theorem 4 ' Suppose three gates are connected as shown in Figure 3.1 where the only output from gate j is a.,. If a. =ot., =a., =1, the network shown in Figure 3k 13 jk lk 3.1 is not optimal. gate Figure 3.1 — Triangular connections 24 By this theorem, at least one of a. ., a., and a., is ij jk ik 0. Thus K n a. . + a ... + a.. < 2 + Z a., (3.9) ID Dk ik - 1=1 :1 9 » l?*i, j, k where i , j , k = 1 , 2 , . . . , R and i ^ j / k ^ i. This property is still true even if gate i is replaced by external variable X. . Thus ' ir n W?+W. + a., > 2 + E a.., (3.10) i i Dk - 1=1 3I where j , k = 1, 2, . . . , R , i = 1, 2, . . .,n and kj* j . (v) Restrictions on the inputs of the network output gate . (2) (3) (13) Theorem 5 All gates which are connected to the network output gate (gate 1) are not connected to any other gate. The property stated in this theorem is expressed -£ a., > U ( a. n - 1) (3.11) k=2 lk " xl k^i U is a positive integer large enough so that the inequal- ity becomes non-restrictive if a... = 0. 3.2 Procedure A synthesis approach for all networks which have a minimum number of NOR gates without minimizing the number of (6 ) connections is as follows ' : 25 (i) The initial value of R is set to 1; R =1. n n (ii) Formulate an IP problem described in section 3.1 to obtain the networks for f using R NOR gates. The ob- jective function is not required. (iii) If there exists no solution, set R + 1 + R and n n repeat (ii) and (iii) until solutions are obtained. By this step, all networks which have the minimum num- ber of NOR gates but where the number of connections is not necessarily minimized are obtained for a given function f. 3.3 Notations R : A number of NOR gates assumed in a network, n 3 f: A function to be realized. X. , X_, . . ., X : n external variables. X (:,) = (Xj 3 ] X^ 3 ] . . . , 3L- ): j-th input vector, where X^ 3 ^ = or 1 and i = 1, 2, . . . , n, j = 1, 2, . . .,r=2 n . a., : The connection from gate i to gate k exists if a., = 1 and does not exist if a.. =0. lk Wv: The connection from external variable X. to gate k exists if WV = 1 and does not exist if Wv = 0. P^ 3 : The output value of gate k for the j-th input vector X 3 , ^ik = p i a, v : Tne value of tne input to gate k from gate i for the j-th input vector X 3 . U: A sufficiently large positive number. Table 3.1 — Notation table 26 4 . ALGORITHM FOR THE DERIVATION OF OPTIMAL NETWORKS WITH NOR-OR GATES AND WIRED-OR LOGIC The algorithm consists of three phases—solution of the logical design problems based on the IP formulation, deri- vation of OR-output-to-gate connections and derivation of Wired-ORs. The flow chart is shown in Figure 4.1. 4.1 Phase 1 : Solution of the logical design problems based on the IP formulation. Since the algorithm for this is described in section 3.2, it is omitted here. 4.2 Phase 2 : Derivation of OR-output-to-gate connections. Step 1. Choose a network among those derived by Phase 1. Step 2. Pick up a gate k which satisfied (i) of restriction 1, where 1 < k < R . — — n Step 3. Get all seccessor gates of gate k. Step 4. Choose a gate as gate j which satisfies (ii) and (iii) of restriction 1 and where the set of all in- puts of gate j is identical to a subset of inputs of gate k, where 2 _< j _< R . Check whether each gate in the network can be a candidate for gate j . Step 5. Classify a gate k into set S if this gate has a pos- sibility to have only one input from OR output, and 27 f START J Phase 1. ± By solving the logical design problems based on the IP formulation, get all networks which has the minimum number of NOR gates but where a num- ber of connections is not necessary minimized. Phase 2. Steps l.to 6. Step 7. Step 8. ±. Get all candidates for OR-output-to-gate connections. ±. Form Wired-ORs by Part 1 of Phase 3 in a network replaced by all OR-output-to-gate connections . ±. Are there any gates which have possibilities to have two or more inputs from OR outputs? NO Step 11. Repeat Step 9 through Step 10 for all 2 - 1 pos- sible subnetworks by counting down a Ro bit down- counter by one. Classify the connection configur- ation to a gate in set M by the number of input con- nections. Step 12. Choose connection configurations which satisfy re- striction 2. Step 13. Repeat Step 9 through Step 12 for every gate in set M. Step 14. If 1^ = 0, go to Part 2 of Phase 3. (If WG = 0, the network by Step 1 can not be minimized by Part 1 and if WG ^ 0, the network by Step 7 can not be minimized any more by Part 1, where WG is defined in Step 7.) If R ? 0, go to Part 1 of Phase 3. 4.3 Phase 3 ; Derivation of Wired-ORs (i) Part 1. Derivation of Wired-ORs whose outputs are con- nected to gates. Step 15. Make a IL bit down-counter in which each bit repre- sents each of all the IL gates. Set all bits to "1." Step 16. Make a network by replacing the original connections by OR-output-to-gate connections to inputs of gates in set S and by OR-output-to-gate connections in Class 1 to inputs of gates in set M. Let the current count N of a R bit down-counter represent a network N. Step 17. For each input 1. of gate 1, find all gates to which 31 this input is connected. Denote these gates with (1 il' l i2' * * " ^mi*" Step 18. Thus we have n gate sets (1-iw 1, 2 » » * • t ^-\ m i ) * (1 21' 1 22' ' * " 1 2m2 ) ' ' • " (1 n l' ^2' " ' " 1 ) corresponding to inputs 1, , 1„, . . .. 1 of nmn c 1 2' ' n gate 1. Check whether there are identical sets among these gate sets applying Restriction 3. If there are any, store (i) those inputs as candidates for inputs of Wired- ORs, (ii) the corresponding gate sets as candidates for outputs of Wired-ORs , (iii) the number of connections as R after replac- mc ing the original connections by all Wired-ORs, where this R is initialized to be large mc 3 positive number, (iv) the network number N, (v) and the network itself. Repeat Steps 17 and 18 for all 1, where 2 < 1 <_ R . Step 19. Count down the R. bit counter by one, and generate a network corresponding to the new count. Step 20. Check the possibility to form Wired-ORs for only the gate whose corresponding bit of the counter changes from "1" to "0", by Steps 17 and 18. If there are any new Wired-ORs , compare the number of connections in the entire network with R . Store (i) through mc 32 (v) of Step 18 only when the number of connections of the new network is smaller than R mc Repeat Steps 19 and 20 until each bit of the counter becomes "0". Step 21. Set N into the R, bit counter. Corresponding to N, pick up a gate m which is in set M, and whose corre- sponding bit of the R, bit counter is "1." If there is none, go to Part 2. Step 22. Change OR-output-to-gate connections for inputs of gate m from class i to class i + 1, where i = 1, 2, 3, . . ., and check the possibility to form Wired- Ors by the procedure described in Steps 17 and 18 for gate m. If a network which has a fewer connections than R is obtained, store the number of connections, mc Repeat for all classes of connection configurations of gate m, and repeat for each gate as gate m. (ii) Part 2. Derivation of a Wired-OR whose output is used as the network output. Step 23. Repeat Step 2 through Step 22 for all original net- works for a function f, and pick up the network which has the minimum number of connections. Step 24. Repeat Step 2 through Step 23 for all original net- works for a given function obtained by Phase 1. Step 25. Let R and R be the minimum numbers of NOR-OR gates ^ n en in the networks among the networks obtained by Step 33 24 for f and f" ', respectively. If R < R , (this en — n means R=R +lorR=R by Theorem 2) change n en n en ^ gate 1 of the network for f to a Wired-OR. Then this network has become an optimal network for f. If R c en > R , go to the next step. Step 26. If the number of connections in the network for f is larger than that for f, this network for f is opti- mal. Otherwise, change gate 1 of the network for f to a Wired-OR. Then this has become an optimal net- work for f . When we repeat all steps from 1 to 26 for all func- tions to be solved, we will have a catalog. 34 5. COMPUTATIONAL RESULTS BY THE ALGORITHM 5.1 Program package This program package is an implementation of Phase 2 and Part 1 of Phase 3 of the algorithm, and can treat up through four variable functions which require 15 NOR-OR gates. Phase 1 is accomplished by the integer program package im- plemented in the past (Developed by Muroga et. al. , and modu- lated by Y. Kembayashi) , and Part 2 of Phase 3 is accomplished by hands. This program package consists of one main program and seven subroutines written in FORTRAN IV. The number of statements for each program is shown in Table 5.1, and the details of flow charts and programs are shown in Appendix C and D, respectively. Number of Name Function Statements MAIN Main program 338 CHKWRD Check whether a new Wired-OR satisfies Restriction 3 73 CONCT Count connections in the entire network 15 DOWNCT Count down a counter by one 13 MAKECT Generate or change networks 16 SEQNS Sort by the number of gates 17 SECSSR Obtain all successor gates of a gate 23 WRDOR Derive all Wired-ORs in the network 94 Table 5.1 — Main program and seven subroutines in the program package 5 . 2 Optimal networks 35 The algorithm was applied to all networks for all three variable functions and to all networks for all four variable functions which can be implemented with five or less NOR gates, where all these networks were obtained by Phase 1. All func- tions are classified into equivalence classes with respect to permutation of variables. According to this classification, there are 77 representative functions for functions of three or less variables except trivial functions (i.e., 0, 1, and X.) and 312 representative functions for functions of exactly four variables which can be implemented with five or less NOR (14) gates (it was proved by Ikeno et. al. ' that 312 representa- tive functions can be implemented with five or less NOR gates) . For original networks obtained by Phase 1, the numbers of rep- resentative functions and numbers of networks are shown in Table 5.2 according to the number of NOR gates in a network. Number of NOR gates in each network 1 2 3 4 5 6 7 Number of representative functions Number of networks by Phase 1 Number of OR-output-to-gate connections by Phase 2 Number of Wired-ORs by Part 1 of Phase 3 Number of Wired-ORs by Part 2 of Phase 3 3 3 5 5 2 8 12 4 17 35 2 11 23 94 1 9 21 15 235 10 19 14 6 189 15 52 6 Table 5.2 (a) — Statistics on functions of three variables at each phase of the algorithm 36 Numbers of all OR-output-to-gate connections and numbers of all Wired-ORs in networks obtained by Phase 2 and by Part 1 of Phase 3 (by the program package) , and numbers of Wired-ORs in optimal networks obtained by Part 2 of Phase 3 are also shown in the same table, (e.g., 52 Wired-ORs are found through- out 189 networks of 7 gates.) The number of Wired-ORs used as the network output of networks which can be implemented with five NOR gates and also the number of representative functions are not found in the cases labeled with * in Tables 5.2 (b) and 5.3 (b) for the fol- lowing reason. For functions of four variables, no network Number of NOR gates in each network 1 2 3 4 5 Number of representative functions Number of networks by Phase 1 Number of OR output-to-gate connections by Phase 2 Number of Wired-Ors by Part 1 of Phase 3 Number of Wired-ORs by Part 2 of Phase 3 1 1 4 4 1 13 20 2 5 60 135 1 27 37 234 892 23 221 * Table 5.2 (b) — Statistics on functions of four variables at each phase of the algorithm which can be implemented with six NOR gates was obtained by Phase 1. If they were obtained, the number of NOR gates in a network could be reduced by Theorem 2 . 37 For optimal networks with NOR-OR gates and Wired-ORs which are derived by the algorithm, numbers of representative functions are shown in Table 5.3 classified according to the number of NOR-OR gates in each optimal network. For functions Number of NOR-OR gates in each network 1 2 3 4 5 6 7 Total Number of representative functions 6 7 17 24 15 7 75 Table 5.3 (a) — Optimal networks with NOR-OR gates and Wired-ORs for functions of three or less variables. Number of NOR-OR gates in each network 1 2 3 4 5 Number of representative function 4 13 60 234 * Table 5.3 (b) — Optimal networks with NOR-OR gates and Wired-ORs for functions of four variables of three or less variables, the numbers of NOR gates of two func- tions (i.e., X 2 V X 3 and X., V X 2 V X.) are reduced to zero. 38 This means that networks for these functions are implemented without NOR-OR gate but with single Wired-ORs . For functions of four variables, the number of NOR gates of one function (i.e., X.. V X v X_ V X.) is reduced from two to zero. Thus these functions are not counted in Table 5.3. 5.3 Major conputational results By combining exhaustive methods with the IP-formula- tion, computer time is reduced greatly compared with the ap- proach based on only the IP-formulation. Phase 2 and Part 1 of Phase 3, however, are exhaustive methods, taking only 200 seconds for all switching functions of three or less variables and 130 seconds for all switching functions of four variables which can be implemented with five or less NOR gates. Compared with Hellerman's catalog (The results by (15) integer programming approach are identical to Hellerman's in the case of three variable functions) and with the results (12) of the IP- formulation for all switching functions of three or less variables and for all switching functions for four variables and for all switching functions for four variables which can be implemented with four or less NOR gates , this algorithm reduced 88 connections (by Theorem 1) and 74 NOR gates (by Theorem 2) throughout 59 functions of 77 representa- tive functions of three or less variables and 74 connections and 28 NOR gates throughout 45 functions of 78 representative functions of four variables. About 16% of connections and 26% of NOR gates on the average for 77 representative functions of three or less variables, and 11% of connections and 10% of 39 NOR gates on the average of 78 representative functions of four variables are reduced by replacing by OR output-to-gate connections and by Wired-ORs. The numbers of representative functions which are im- proved by the algorithm are shown in Table 5.4. Whenever an optimal NOR network is improved by the algorithm, OR outputs and Wired-ORs are simultaneously incorporated or Wired-ORs without OR outputs are incorporated. No im- Improved Improved Improved provement by OR alone by Wired- ORs alone by both Number of representa- tive functions of three variables 18 53 6 Number of representa- tive functions of four variables 33 44 1 Table 5.4 — The numbers of representative functions im- proved by the algorithm 5.4 Examples of optimal networks Three examples of optimal networks are shown here com- paring with optimal networks of NOR gates only derived by Hel- lerman's catalog. (1) (i) x 1 v x 2 v x 3 Hellerman's catalog x l x 2 x 3 » - s i — ^ V \ Y \ j ' L * 2 NOR gates, 4 connections This algorithm Xl X. 2 connections Two NOR gates and two connections are reduced. 40 (ii) x 1 x 2 x 3 v Xl x 2 x 3 v Xl x 2 x 3 Hellerman's catalog This algorithm X. X, X X. r-O^O 7 NOR gates, 14 connections 5 NOR gates, 12 con- nections Two NOR gates and two connections are reduced. (iii) Parity function X-.X-X- V X,X X V X,X n x\, V X,X X J 123 123 123 123 Hellerman's catalog X. X. x; T X. X. 7 NOR gates, 20 connections This algorithm 41 X. x! X. X. 6 NOR gates, 14 connections One NOR gate and six connections are reduced. All optimal networks whose numbers of NOR gates or numbers of connections are reduced by Phases 2 and 3 of this algorithm are shown in Appendix A-l and B-l for all switching functions of three or less variables. Hellerman's catalog has no network for functions of four variables , but networks which consists of only NOR gates have been obtained by the logical design based on the IP-for- (12) mulation. Let us show examples of optimal networks for functions of four variables comparing with the networks de- rived by the logical design based on the IP-formulation. (i) Xl x 2 x 3 v x lX2 x 4 v x^^ v x 2 x 3 x 4 IP- formulation X X ::=C^i 5 NOR gates and 12 connections 42 This algorithm X ] X. r v 3 NOR gates and 9 connections 7 S Two NOR gates and three connections are reduced (ii) X X X 3 V X 2 X 3 V X X X 2 X 4 IP- formulation x: x l r^\ b> — 1 %— X2 1 X 4 5 NOR gates and \ 1 J • -A 10 connections 1 -Ly This algorithm X. X, 3 NOR gates and 7 connections Two NOR gates and three connections are reduced. All optimal networks whose numbers of NOR gates or numbers of connections are reduced by Phases 2 and 3, and which can be implemented with three or less NOR-OR gates are shown in Appendix A-2 , and B-2 . 43 6. CONCLUSION Optimal networks consisting of NOR-OR gates and Wired- ORs under the assumption that only non-complemented variables are available as the network inputs have been found for all switching functions of three or less variables and for all switching functions Of four variables which can be implemented with three or less NOR-OR gates, defining the optimality as the minimization of the number of gates first, and the number of connections next. The reason why we defined the optimality in this manner is that the cost of connections is considered to be very small compared with the cost of implementation of NOR-OR gates. But if the cost of connections becomes compara- ble to or is sometimes higher than that of NOR-OR gates, we have to consider a different definition of the optimality. Also a Wired-OR is defined to have k- + k 2 - 1 connec- tions. If we define it to be k. + k 2 as in the case (b) in Figure 2.10 (this also may be a fiarly reasonable definition), all optimal networks which have at least one Wired-OR derived by this algorithm are still optimal networks. And then the original networks which we had before replacing the original connections by these Wired-ORs are also optimal networks for all the functions except only two functions X,X 2 X 3 X. V X,X 2 X~X 4 and (X., V X 2 V X.) X. V X^xJx^. for the following reason: 44 Each of all the Wired-ORs in these networks except those for the above two functions has exactly two inputs and two outputs , in other words k.. = k_ = 2, and these Wired-ORs do not reduce the number of connections, because if we do not use this Wired- OR, k, x k„ = 4 connections are required (notice that the num- ber of connections for the Wired-OR is k. + k ? = 4) . Conse- quently, each function except the above two functions has lat- ter networks in each of which the number of connections is equal to that of the former networks. Thus each function ex- cept the above two functions has one extra optimal network with- out Wired-ORs, corresponding to each optimal network with Wired- ORs for the function. However each of the two functions X, X-X-X, V X,X X-X\ 1234 1234 and (X, V X 2 V X-) X. V X,X 2 X 3 X 4 has one optimal network which contains one Wired-OR with two inputs and three outputs, under the counting of k + k. - 1. The Wired-OR reduces the number of connections . Thus the corresponding network without the Wired-OR is not an optimal network under the counting of k, + V The networks for functions of three or less variables which are obtained by Phase 1 are also derived by the branch- and-bound method to make sure whether all networks are correct- ly derived by Phase 1. 45 LIST OF REFERENCES (1) L. Hellerman, "A catalog of three Variable OR-Invert and AND-Invert Logical Circuits," IEEE Trans. Electron. Comput., Vol. EC-12, pp. 198-223, June 1963. (2) S. Muroga, "Logical design of optimal digital networks by integer programming , " in Advances in Information Systems Science, J.T. Ton Ed. New York Plenum, 1970, Vol, 3, Ch. 5, pp. 283-348. (3) , "Threshold Logic and its Applications," New York Wiley-Interscience , 1971, Ch. 14. (4) & T. Ibaraki, "Design of optimal switching network by integer programming, " IEEE Trans. Comput., Vol C-21, No. 6, pp. 573-582, June 1972. (5) C.R. Bough, C. S. Chandersekaram, R.S. Swee & S. Muroga, "Optimal network of NOR-OR gates for functions of three variables," IEEE Trans. Comput., Vol. C-21, No. 2, PP. 153-160, Feb. 1972. (6) Y. Kambayashi & S. Muroga, "Properties of Wired Logic," To be published. (7) S.F. Gimpel, "The minimization of TANT networks," IEEE Trans. Electron, Comput. Vol. EC-16, pp. 18-38, Feb. 1967. (8) S. Muroga & T. Ibaraki, "Logical Design of an optimum net- work by integer linear programming — Part I," Dept. Comput. Sci., Univ. Illinois, Urbana, Rep. 264, July 1968. (9) , " — Part II," Dept. Comput. Sci., Univ. Illi- nois, Urbana, Rep. 289, Dec. 1968. (10) T. Ibaraki, T.K. Liu, C. R. Baugh and S. Muroga, "Implicit enumeration program for zero-one integer programming," Int. J. of Comp. and Inf. Sci., Vol. 1, No. 1, pp. 75- 92, March, 1972. (11) T.K. Liu, "A code for zero-one integer linear programming by implicit enumeration," M.S. thesis, Dept. Comput. Sci., Univ. Illinois, Rep. 302, 1968. 46 (12) J.N. Culliney, "On the synthesis by integer programming of optimal NOR gate networks for four variable switching functions," M.S. thesis, Dept. Comput. Sci., Univ. 111., Rep. 480, 1971. (13) K.R. Holhulin, "A code for designing optimal networks by implicit enumeration using the all-interconnection in- equality formulation." To be published. (14) N. Ikeno, A. Hashimoto & K. Naito, "A Table of Four- Variable Minimal NAND Circuits," Electrical Communica- tion Lab. Tech. J., Extra Issue No. 26, Electrical Communication Laboratory, Nippon Telegraph and Tele- phone Public Corporation, Tokyo, Japan, 196 8 (in Japanese) . (15) C.R. Baugh, T. Ibaraki , T.K. Liu & S. Muroga, "Optimum network design using NOR and NOR-AND gates by integer programming," Dept. Comput, Sci., Univ. Illinois, Report No. 293, Jan. 10, 1969. 47 APPENDIX A Optimal Networks With NOR-OR Gates And Wired-ORs 48 All optimal networks whose numbers of NOR gates or numbers of connections are reduced by the algorithm are shown here. The networks for functions of three or less variables are shown in A-l, and the networks for functions of four variables are shown in A-2. Function number FCT is defined as follows: (i) Functions of three or less variables. External Variables X. X. X. 00001111 00110011 01010101 f f l f 2 f 3 f 4 f 5 f 6 f 7 FCT f_f^ f.f.f- f_f.f n in octal. 76 543 210 e.g., for X, V X-X.; f_, f., f_, f, and f- =1 FCT = (11111000) 2 = (270) (ii) Functions of four variables. External x i 1 1 1 1 1 1 1 1 Variables x 2 1 1 1 1 1 1 1 1 X 3 1 1 1 1 1 1 1 1 X 4 1 1 1 1 1 1 1 1 f f l f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f io f n f 12 f 13 f 14 f 15 FCT = t Q t x t 2 l 3 f 4 f 5 f 6 f, f 8 f 9 f 10 f n f 12 f 13 f 14 f 15 in hexa " decimal. 49 Notations used in this paper are as follows : A Wired-OR NOR output OR output These tables show all networks with NOR-OR gates and Wired-ORs. From these tables, optimal networks with NAND-AND gates and Wired-AND can be easily obtained by finding the func- tion number FCT for NAND for a given function f in the tables and then by changing NOR-OR gates and Wired-ORs to NAND-AND gates and Wired-ANDs, respectively . (e.g., the network with NOR-OR gates and Wired-ORs for function X,x" 2 X 3 V X^X-j V X,X 2 X 3 (No. 42) is changed to the network with NAND-AND gates and Wired-ANDs for function X 3T V X^X.. V X~ 2 X 3 V X^X^ as shown in this figure.) Wired-AND 50 o H CO CO Pn EH o |M l>r OJ OJ o "1 a- m IK^ IX* F, « "K. IK ► in" ► •c IH Rr o M CO CO Ph Eh U Ph IM CM K O IK CM LTN IM .M H IK >■ is if iT M l>r IK > ^O cn CM I-* "P O H CO CO Ph EH O [in O o CM g o H CO CO Ph EH Ph VD •Vi o H CM IM >• IM~ IK > D- C- 6 CM C\J •*i IM ► CM Ph 1 g M > IK H I J, CVJ on IM CM 51 o H CO CO O. EH O Pn ,* '5* ,f 1m o OJ "k '* IM_, OJ 1$. IK OH LP, ITS M LP H i $ a o H CO CO EH O > Q no O on OJ LP o LP LP O" IM I" Lf\ c- oo o H o H CO CO Pm EH O IM ► IM* & o i* oo H IK VD C 4 - OJ IK ► IK- Ik <\j H oi K IK LTN LTN OO H OJ o H CO CO PL, EH O K tv. IM LTN K oo H OJ & H •V. O oo IK Ik -d" LT\ OO OO 52 :-■ o M CO CO Oh EH O In |M . H IN oo H CVI o VO g nT IN on LP H IM ► N <\) M H LP cvl o H CO co PL, X EH O IN In In CVI K O _5_ VO LP H IK N N N iiT* IN N ru N ► N N CVI LP H H in CVJ IN 0- o CVJ VO cm 125 O H CO co EH O • n X N VO r- H K O H O CVI IN IN H no CM LP LP H IN IN In OO O CVI vo o H CO CO Ph X EH O IN IN In LTV H i H H J. IN H CO on LP on N > N I.T o LP lx In VO 53 o H CO I EH O En Ir- on OJ s ••r IM vo H LT\ H H 00 CM Ik o H CO CO I Pn EH O En IK IK OO oo OJ o IK g IM o Lf\ H H LP oj o M co CO I EH O En IK ru K wt IK * ! X i«r vo oo o H CO co Cm Eh O En IK I* IK rvj IK rH K o on OJ O vO on IK LP OJ o vo oo OJ 54 o H CO GO I EH O Fn CM O r M 6 O OO 00 OO K o IM H IM w w w fin Ik iiT 6 IM X o H CO CO Ph X w Eh O In (VI F^ CO O IM. IM IM -7*r CO o CO co 3 IK IK 55 o H CQ CO g Ph 8 EH o IM IT Ik IM IM o CO IM IM H IM M ph t IM IM IM ► |K~ I if ► t- M I if* IM* EH O P-h IJ« .**! IM M * M H |M o CO CO K o IM IM rH IM P-4 w p-4 00 CO M i\j M IM CO is; o M CO CO g Ph X H Eh O P-H M M S IK 3 co CO o H CO CO g Cm 8 EH O IM K OJ o .11 Ik O Ik fa H < M . "^ IM IM CO 00 CO OJ Ik IM M •r 56 o H CO CO !:! PH i;i O In* |M o OJ K O pq o & o < ■t M *\ I* Ik CO "V. IM H IM IM •r IM IM |H ~cT CO K O o P>h o H W CO PL. X w EH O Pn l*~ M IM OJ M o H O CM O IM pq o CO o lx. IM IK ON CO CO CO IM. IM I J" IM IM IM H M 5 CO CO o H w d |25 O H CO CO PLj EH O IM IM o o o CM O IM irf* IM pq o o o n ; I* l»t Ik |x o> IM . w IM M k IM IM IM too IM IM o H CO CO I CM 8 EH O En IM IN* M- 00 Ik Ik Im 30 30 CO r p o H CO CO CM IM Ik IM Ik M- 00 En 00 CO Q o g |K CO CO (W) CO w 58 O H CO CO g fa X fa EH O fa o H CO CO P-i EH O fa IM IT Ik IM IK o co fa O Ik IT IK IK IK" w w w fa g Ik IK .** Ik o CO CO CO 6 i 59 APPENDIX B Statistics on Optimal Networks 60 Statistics on optimal networks for each of all repre- sentative functions of three or less variables except trivial functions (i.e., 0, 1 and X.) are shown in B-l. Statistics on optimal networks for each of all representative functions of four variables which can be implemented with four or less NOR gates in the original network derived by Phase 1 and for each of all representative functions of four variables whose numbers of NOR gates are reduced from 5 to 3 by the algorithm are shown in B-2. Original networks are those obtained by Phase 1 of the algorithm and optimal networks are those obtained by Phases 2 and 3. Optimal networks shown with "-" sign in the optimal network column are identical to original networks . (These networks do not have network numbers in tables) . Because we do not have gates which have only OR out- puts, the numbers of NOR outputs in the optimal network column also express the total numbers of gates in the networks. 61 B-l Functions of three or less variables Original netw- orks derived Optimal ne ■tworks derived by phase 1 by entire algorithm No. of No. of No. of No. of No. of No. Of Network NOR conne- NOR OR Wired- conne- number FCT gates ctions outputs outputs ORs ctions 1 1 3 - 2 2 4 - 3 1 2 - 11 6 5 9 3 2 8 7 4 6 - 10 > 5 - 11 4 9 - 12 2 ■* _> - 13 3 5 - 16 2 4 - 17 1 1 - 24 26 6 14 4 1 14 12 27 5 10 3 1 8 25 30 6 11 4 1 10 26 31 6 10 4 1 8 13 32 5 9 7 J 1 8 14 33 5 8 3 1 6 15 36 5 10 3 2 8 7 37 4 6 2 1 4 27 50 6 10 4 2 9 42 51 7 14 5 1 2 12 16 52 5 7 3 1 6 28 53 6 10 4 1 9 29 54 6 10 4 1 9 30 55 6 • 11 4 2 9 17 56 5 8 3 1 7 18 57 5 7 3 1 5 19 74 5 8 3 1 7 31 75 6 10 4 1 9 20 76 5 9 3 1 8 8 77 4 5 2 1 3 55 150 7 15 6 1 14 56 151 7 16 6 1 19 43 152 6 12 5 1 13 44 153 7 15 5 1 14 32 156 6 10 4 1 10 33 157 6 11 4 1 9 34 176 6 11 4 1 11 21 177 5 7 3 1 5 200 4 6 - 45 201 5 12 5 1 10 202 5 10 - 46 203 5 11 5 1 9 37 206 6 15 6 1 1 13 47 207 6 14 5 2 10 62 Original netw- orks derived Optimal networks derived by phase 1 by entire a lgorithm No. of No. of No. of No. of No. of NO. Of Network NOP conne- NOR OR Wired- conne- number FCT gates ctions outputs out nuts ORs ctions 210 7 ^ 4 _ 35 211 4 9 4 1 8 212 4 6 — 36 213 4 8 4 1 7 48 216 5 10 5 1 9 37 217 4 7 4 1 6 58 ?2e 7 20 6 2 14 59 227 7 15 6 2 13 49 230 5 10 5 1 9 38 231 4 8 4 1 7 50 232 5 11 5 1 1 9 51 233 5 10 5 1 9 60 236 6 15 6 1 1 13 52 237 5 11 5 1 9 250 3 5 - 39 251 4 10 4 1 1 8 3 2 53 -z. 3 5 1 1 3 254 4 7 - 40 255 4 9 4 1 8 9 256 4 6 2 1 4 4 257 3 4 1 1 2 274 5 9 - 53 275 5 11 5 1 10 22 276 5 10 3 1 8 10 277 4 6 2 1 4 350 4 9 - 54 351 5 15 5 1 1 12 23 352 3 6 3 1 5 41 353 4 10 4 1 g 1 356 2 3 1 1 5 357 5 5 1 1 3 2 376 2 4 1 2 63 B-2 Functions of four variables which reauire four or less NOR-OR gates in each optimal network Original netw- orks derived Optimal networks derived by phase 1 by entire algorithm No. of No. of No. of No. of No. of No. of Network NOR conne- NOR OR Wired- conne- number FCT gates ctions outputs outputs ORs ctions 2 k 7 _ 7 k 7 - 8 3 6 - IF k 8 - 2A 3 6 - 7F 3 6 - 80 2 5 - 8A k 7 — 8F k. 7 - 15 AS 5 8 3 2 7 BF k 7 - 16 FA 5 8 3 1 7 IFF k 9 4 1 7 22 A k 10 — 28A k 8 - 2AA 3 7 - 17 2FF 5 s 8 3 1 6 35F h Q - ?7F k 10 - 38 F k p, - 777 x 6 - 77F k 11 h 2 10 78 F k 9 4 1 8 7F7 h ' 8 - 18 7FF "Z 7 3 1 6 19 880 5 10 ■* 3 9 888 2 5 — 20 8A0 5 10 3 2 9 21 8A8 5 o x 2 8 8AA 4 7 - 22 8F0 5 10 3 1 9 23 8F8 5 9 3 1 8 5 8ff 4 7 2 1 5 24 ACO 5 10 "^ 1 9 25 AEA 5 9 3 1 8 TPPD 4 7 - BFF 4 8 4 1 7 26 FEE 5 8 3 1 7 27 EFF 5 9 3 1 7 17FF h 12 4 1 10 1RBB k 8 — 1BFF k 9 4 1 8 28 1FFF 3 8 •? 1 6 64 Original netw- orks derived Optimal networkr, der ived by phare 1 by entire al. gorithm Mo. of No. of Mo. of No. of No . o f Ko . of Network . ,; 0R conne- NOR OR V'/ired- conne- number |i CT gat ess ctions out pu ts outputs OPs ct ■ o n s 29 2888 5 11 3 "7 9 30 ?8a8 5 10 3 2 o 7 1 28 FF R s 12 "Z 2 9 2 AAA 2 5 - 32 2AC0 11 3 2 q 53 2AFA 5 10 3 2 8 6 2AFF 4 7 2 1 34 2CCC r s 11 3 2 9 35 2CEC 5 10 3 1 9 ~^6 2CFF 5 11 "^ 1 9 37 2EEE 5 o z 1 p 38 2EFF 5 10 ■^ 1 8 7 2FFF 4 7 2 1 5 39 6 AAA 5 11 3 2 o 40 6 AGO 12 3 3 9 41 6AFA c; 11 •z p 9 42 6AFF 5 12 i. 2 o 43 6EFE 10 T. o 1 o 44 6EFF 11 X 1 Q 45 6F:^F 5 11 X ^ 1 Q 1 7FFF 2 5 1 1 Q QOQ 1 4 - R008 4 10 - 8 00 A 4 10 - 8 OOF ^ 10 4 1 9 80? A 4 11 4 1 10 P f) "z. jT 4 ■ 11 4 1 1 9 807? 4 12 4 1 1 Q 8088 3 6 - 808 a 4 9 - 808F 4 9 4 1 8 °0AA 3 6 - 80BF 4 10 4 1 1 8 2 <°-OFF 3 6 1 1 4 828A 4 10 - P ?AA 4 n 4 1 10 8?8F 4 10 4 1 9 °3FF 4 11 4 1 10 8777 4 12 4 1 1 o 878F 4 11 4 2 9 87F7 4 11 L 1 1 9 87FF 2x 12 4 1 1 9 o I.) Q Q Q Q 4 7 2 2 6 88 8 A Zi o - 8 8 8 F 4 8 4 1 7 ,' , f . 8 Q A0 9 •z 1 p 47 88A8 c: 8 3 1 7 65 Original netw- orks derived Optimal networks derived by phase 1 fey entire algorithm No. of No. of No. of No. of No. of No. of lietwork NOR conne- NOR OR Wired- conne- number FCT gates ctions outputs outputs ORs ctions 88BF 4 9 4 1 8 48 S8F0 c 9 3 1 7 49 38F8 5 8 3 1 6 8 AAA 6 - 50 8AFF 8 3 1 6 8 BBB 4 9 4 1 8 8 BFF 4 10 4 1 9 3 8FFF 3 6 1 1 4 9BBB 4 10 4 1 9 9BDF 4 10 4 1 9 9 BFF 4 11 4 1 9 9FFF 4 12 4 1 9 51 A880 5 11 3 1 11 9 A888 4 7 2 1 6 A8AA 4 7 - 10 A8FF 4 8 2 1 6 52 AAA8 5 a 3 1 8 AABF 4 8 4 1 7 53 ■ AACO 5 9 3 1 7 54 AAFA 5 8 5 1 6 ABFF 4 9 4 1 7 55 ACCC 5 10 3 1 1 7 56 ACEC 5 9 3 1 7 57 A OF 1 ' 1 5 Q 3 1 7 58 AEEF 5 8 3 1 6 59 AEFE 5 8 3 1 6 4 BFFF 3 ' 6 1 1 4 60 E888 5 12 3 2 9 61 E8A8 5 11 3 1 9 62 E8FF 11 3 1 9 11 EAAA 4 7 2 1 5 12 EACO 4 7 2 1 5 63 EAC8 5 10 3 1 8 13 FAFF 4 7 2 1 5 64 EEEA 5 9 3 1 7 14 EFFF 4 7 2 1 5 65 FE^F 5 8 3 1 6 66 FEFF 8 3 1 6 C6 APPENDIX C Flow Charts 67 The detailed flow charts for the programs in the pro- gram package which consists of one main program and seven subroutines as shown in Table 5.1 are shown here. The step numbers of the algorithm are also shown in the flow charts. 68 Read data cards. NOVR = no. of variables. NONR = no. of NOR gates. Read NO, FCT, COM? * Step 1, Count the no. of connections from, external variables. J+1-*J 7FT START Read $W, $WW _^L Read $A, $AW ± O^NC(I), GATEIN(I.J) ] t I J± ^ l-> J O D,"^OVR D y LOD +D J NONR I+l+I V J- f 15+J ■*■ GATEIN(I,NC(I)) I: NONR GATEIN = inputs of gates 69 Count the no. of connections from NOR gates. J+l+J Print out, NOCN: no. of connections _^ 1+1 2t ^ 1+J ±. NC(J)+1+NC(J) Jsk GATEIN(J,N(J)) Print out NO, FCT, COMP, NOVR, NONR, NOCN I+l+I 7R Original Table Initialization. JL MS(I),ORIN(I,J),$0(I,J), $OW(I,J), Ro Print out Message 70 Find OR-output. Step 2. KC: K counter. Step 3. JC: J counter. Step 4. Find Subset. INK+1+INJ 1-KLNJ 1+INK INK+1+INK 71 If MS=1, KC in S If MS«2, KC in M Step 5. ORIN: Inputs to KC from OR outputs. Step 6. MS(KC)+1-*MS(KC) CALL MAKECT.O+JD JC-*ORIN(KC,MS(KC)) 0+M(KC) Step 7. Step 8. CALL WRDOR 1+KC Ro+L+Ro KC+KSP(Ro) Gate in Group M. Step 9. |_l_BC(l>,BC(2),...,BC(MSCkC), 2**MS(KC)-1-»BCD. BCDM 2+M(KC) NCNW(I) !+!-»■ I J+l+J 4l O^NCN(JM) JttMMM(I) 1+IWG IWG+1+IWG } IWC+1+IWC v, IMS+1+IMS "* 1-»"M(KC) 1+IWC -> I* IMS 1-*J J+l+J 74 Step 12. I+IT BCDM-1+BCDM NCNW(IT+1) +NCNW(IT) K1(IWG)*K2(IWG)-K1(IWG)-K2(IW6)+1 -(NCNW(1)-NCNW(I))+D JCM: name of imputs (or outputs) at LVL JMM(I). Step. 13 NGM: no of inputs at LVL JMM (2) JCM ( JMM ( i ) , j )+JCMG (Ro , LVL , ING ) NGM(JMM(i)) -*NGNG(Ro,LVL) BCDM -+MNG(Ro) 75 tep 14. tep 15. ake a network: ;ep 16. 1* BC(l),BC(2), ...,BC(Ro) 1* ALL, FIRST, TBC 0+ IWGP 2L £- KSP(IBC)-> KC.l-» ING £ JCMG(IBC,1,ING)+JC JL CALL MAKECT, Print out Message ING+1*. IMG 7R ± N0CN-K1*K2+ K1+K2-1*RMC IBC+1* IBC 7R CALL CONC 7 6 IWGM-* I vVG KSP(IONF)*LOV/,LAST Step 19. XL CALL DOWNC r [/_ -> ALL / IPC s£- KSP(IBC)->KC, 1-»ING _fc JCMG(IBC,1,IMG)->JC Jl CALL MAKECT ING+1-»ING — ft IPC+1-*?C A 77 1»BC(1),BC(2) BC(Ro) a CALL DOWNCT $AW+$A , $WW-*$W , $OW->-$0 , 1->IBC IBC+1+IBC Print Out $AW,$WW,$OW WIR,WOR,RMC 3L 2+LVL ±k Change level ± IWGP+IWG ±. CALL WRDOR LVL+1+LVL 7R CALL CHKWRD LVL+LVL(IBC) 73 SUBROUTINE CHWKRD CHECK WIRD-ORe SUBROUTINE CONCT No. of Connections f START J _^ 0*RC MoMft NoVfc NONR Z [ £ $W(I,J) + Z ($A(I,J) + $0(l,j))] 1=1 J=l J=l IW3P + Z (K1(I)+K2(I)-1-K1(I)K2(I))-».RC 1-1 f RETURN J CALL CONCT RC+RMC 0*FIRST f RETURN 1 79 IBROUTINE DOWNCT rWN-COUNTER O+BCCIBC), BCD-1-KBCI JL RETURN JBROUTINE *XE NETWORK MAKECT START TEM= > / — S. GATEH KJC.J) > 15 yS ^ JD+$AW(TEM,KC) v^ JD+$WW(KC,TEM-15) 80 SUBROUTINE SEQNS SEQUENCE START 1+IJ ARRAY ( I T , IJ ) +WORK1 IJ+1->JJ ARRAY ( 1 1 , J J ) -+WORK2 WORK1+ARRAY ( I I , J J ) WORK2+WORK1 IJ+l+IJ JJ+l-MJ WORK1+ARRAY ( II , IJ ) ( RETURN J 81 MtOUTINE SUCSSR IlCESSOR GATES 1)1: the gate which we want to get its successors. ): successors llC: number of successors. NC+l+NC START O+NSUC NSUC-1+NSUC 02 SUBROUTINE WRDOR Step 17. NI: no. of inputs to IL IY+l+IY ~* CHECK(I,J) LOW+IL NI+l+NI 1 +IX +NG(NI) IX+l+IX IF XILrLAST S~ CALL SEQNS >/ CALL SEQNS >/ ^ RETURN J NG: no. of gates from IY NG(NI)+1+NG(NI) 1+CHECK(IX,IY+15) IX+GSET(NI,NG(NI)) IY+13*INT(NI) 83 O 1 -»- IY NI+1 ■* NI 1 -* IX ■* NG(NI) IX+1 ■> IX A NG(NI)+l->-NG(NI) i-k:heck(ix,iy) ix+gset(ni,ng) iy-kln p(ni) 84 1 ■+ IY SG(NI)+l->-NG(NI) l-k:heck(ix,iy+20) ex-+gset(ni,ng) IY+20-*INP(NI) 85 NS+1 -*■ NS NST+1 -». NST JNI •» NSAME(NS) «m*NSAMT(NST) INP(INI),INP(NSA- ME) *WIR(i;VG,i) 86 APPENDIX D The Program Package 87 The complete program package which consists of one main program and seven subroutines as shown in Table 5.1 are shown here. All programs are written in FORTRAN IV. 88 IMPLICIT INTEGERS =0 323 GO TO 1278 324 1276 SOP (WIR (I , JJ-20t I 1*1 325 DO 1277 J0=1,ILS 326 1277 SOWIWIRI I,J)-20,W0R( I,JO))=0 327 1278 CONTINUE 328 DO 1280 J=1,ILS 329 1280 SRAU ,WOR(I,J) 1=1 330 GO TO 1290 331 1282 00 1286 1=1, RO 332 IF(MU).GE.l) GO TO 1284 333 CALL MAKECTUA,$W,SO,ORIN(KSP( I ) , 1 > , KSP< I ) ,0 ) 334 GO TO 1286 335 1284 ILR=NGMG( 1,11 336 DO 1285 ING=1,ILR 337 1285 CALL MAKECT($A,SW,SO,JCMG( 1,1, ING ) , KSP ( I ) , 01 338 1286 CONTINUE 339 RMC=ROR 340 IWGM=0 341 DO 1288 I=1,N0NR 342 DO 1287 J=1,N0VR 343 1287 sww< I , J) = $w< 1 ,J) 344 DO 1288 J=1,N0NR 345 $AW( I , J)=SAI I, J) 346 1288 $OW(I,J)=$0( I, J) 347 1290 PRINT 8 348 PRINT 5.SWW 349 PRINT 6, SAW 350 IF(RO.EQ.O) GO TO 1291 351 PRINT 9, SOW 352 IF( IWGM.EO.O) GO TO 1295 353 1291 PRINT iO.SWR 354 PRINT ll,$AR 355 IF(RO.EO.O) GO TO 1292 356 PRINT 12.S0R 357 1292 PRINT 13, SPA 358 1295 PKINT 14.RMC 359 GO TO 100 360 END 361 SUBROUTINE CHKWRD( SA ,SW, SO,WIR,WOR, IWG, IWGP,RPC,F ,* ) CH 1 IMPLICIT INTEGER*2 (A-Z,S) CH 2 COMMON NONP,NOVR,KK 10),K2(10) , NC < 1 5 ) .GATE IN ( 15,5 ) CH 3 DIMENSION SA(15,15),SW( I 5 , 4 ) , SO ( 15, 15 ) , WIR ( 10 , 10) ,WOR(10,10) CH 4 IF(F.EO.l) GO TO 90 CH 5 94 I - I WG *1 5 DO 40 J"lilWG IF(Kl< I I.NE.KK Jt ) GO Tb 40 I L T =K 1 ( I ) DO 10 IW=1,ILT IF (W|R( I , 1W J.NE.WIRI J, IW) ) GO TO 40 10 CONTINUE [WGP«IWGP-1 K2( J|xK2(J)4l ILT=K2( J|-l DO 15 IW=1,ILT IF(WO«( JtIWI.-NE.WORC IiIWll GO TO 20 15 CONTINUE WOP( J,K2( J) )=WOR( I tK2( J) ) GO TO 25 20 WJR< J.K2I J) )=WOR(I,IW) 25 CALL SECNS(W0R,J,K2( J)l DO 35 LC*I,IWGP Kl (LC)=K1(LC*1) K2(LC)=K2(LC*1) ILT=K1(LC) DO 30 LD=1.ILT 30 WIR(LCtLD)*WlRILC+l»LDI. ILT=K2(LCJ DO 35 LD=1, ILT 35 WOR(LC,LD)=WOR(LC«-l»LD) GO TO 62 40 CONTINUE DO 80 J=1,IWG IF(K2( I J.NE.K2U) I GO TO 80 ILT = K2( I) DO 45 IW=1,ILT IF(WOR( I , IWJ.NE.WORl J,IWJ J GO TO 80 45 CONTINUE IWGP=IKGP-1 Kl( J)=K1(J)+1 ILT=K1( J)-l DO 50. IW = 1,ILT IF(WIR( J, IW) .NE.WIRJ I.IWI) GO TO 55 50 CONTINUE WIR( J,K2(J) I = WIR( I,K2( Jl ) GO TO 60 55 WIR(J,K2( J))-WIR(It IW) 60 CALL SE0NS(WIR,J,K2( J) ) DO 65 LC=I iIWGP KKLCI-KKLC4-1) K2(LC)=K2(LC+ll ILT=K1(LC) DO 65 LD*U1LT 65 WlR(LC,LD)=WlRtLCM,LD) ILT=K2(LC) 00 70 LD=1, ILT 70 WOR(LC tLD)=WOR(LC+liLD) GO TO 82 80 CONTINUE IF< I.GE.IWGP) GO TO 85 1 = 1+1 GO TO 5 82 IF( I.GT.IWGP) GO TO 85 GO TO 5 85 CALL CONCT(>A,SW,$Ot IWGPtRC) CH 6 CH 7 CH 8 CH 9 CH 10 CH 11 CH 12 CH 13 CH U CH 15 CH 16 CH 17 CH 18 CH 19 CH 20 CH 21 CH 22 CH 23 CH 24 CH 25 CH 26 CH 27 CH 28 CH 29 CH 30 CH 31 CH 32 CH 33 CH 34 CH 35 CH 36 CH 37 CH 38 CH 39 CH 40 CH 41 CH 42 CH 43 CH 44 CH 45 CH 46 CH 47 CH 48 CH 49 CH 50 CH 51 CH 52 CH 53 CH 54 CH 55 CH 56 CH 57 CH 58 CH 59 CH 60 CH 61 CH 62 CH 63 CH 64 CH 65 CH 66 95 IPIRMC.LE.PC) GO TO 95 90 CALL CONCTUA 95 R>1C = RC c = RETURN END SUBROUTINE C^ IMPLICIT INTE COMMON 1 NONR.N DI M ENSIPN JA( RC=0 CJ 10 1=1, NCN 03 5 J=1,N0V 5 RC=RC+*W< I ,J) 00 10 J=1,N0N 10 RC=PC*JA( I , J) IF( IWGP.EQ.O) OH 15 I=lfIWG 15 RC=RC-K1( I)*K RETURN END SUBROUTINE DO IMPLICIT INTE COMMON NONP.N DIMENSION BC( IBOl 10 IF( PC( I BC 1 .EO BC( IBC ) =1 IBOIRC+1 GO TO 10 20 BC(IBC)=0 RCD=BCD-1 RETURN END SUBROUTINE "A IMPLICIT INTE COMMON NONP.N DI M ENSION $A( NCJ=NC(JC) DO 20 J=1,NCJ IF(GATEIN( JC, SAIGATEINUC, GO TO 20 10 $W(KCtGATEIN( 20 CONTINUE IF(JO.EO.O) J IF(JD.EQ.l) J $0IJ+l DO 5 JJ*IJ1» IF(ARRAY(II, J RETURN 1 ,$W,$0, IWGP.PC) NCT($A,$W,iO,lWGP,RC) GCR*2 (A-l,l) OVR.Kll 10 1 ,K2< 10), NCI 15), GATE IN I 15,5) 15,15), 1W(15,4) ,10(15,15) ♦ SOU, J) RETURN P 2II)+K1U )+K2(I)-l WNCTIBCBCDflBC) GER*2 IA-Z,$) OVR,Kl(10),K2llO),NCI15),GATEINI15,5) 10) .1) GO TO 20 KECTI$A,$W,$0,JCfKCf JDI GER*2 IA-Z,$) OVR.KK 10 ),K2 1 10), NCI 15), GATE IN 1 15, 5) 15, 15), SWl 15, 4), $0115, 15) J1.GT.15) GO TO 10 J),KC)»JD JC,J)-15)»JD DC=«1 DC=0 ONSIARRAYfl I,IJMI GER*2 IA-Z,$) 0VR,KII10),K2I10),NCI15),GATEINI15»5) AYI10.10) Ml IflJI IJM JI.GE.W0RK1) GO TO 5 CH 67 CH 68 CH 69 CH 70 CH 71 CH 72 CH 73 CO 1 CO 2 CO 3 CO ** CO 5 CO 6 CO 7 CO 8 CO 9 CO 10 CO 11 CO 12 CO 13 CO 14 CO 15 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7 DO 8 DO 9 DO 10 DO 11 DO 12 DO 13 MA 1 MA 2 MA 3 HA 4 MA 5 MA 6 MA 7 MA 8 MA 9 MA 10 MA 11 MA 12 MA 13 MA 14 MA 15 MA 16 SE 1 SE 2 SE 3 SE 4 SE 5 SE 6 SE 1 6 SE 7 SE 8 SE 9 96 wnBK2 = APPAY( I It JJ » ARRAY! I I i J J)=WCRK1 WJRKl=W0PK2 5 CONTINUE 10 ARRAY! I I , I J)=WCRKl RETURN END SUBROUTINE SUCSSP ( $A iTOP tSUCtNSUCI IMPLICIT INTEGER*2 (A-Z,$) CJ"MQN NONP,NOVR,KK 10 1 1 K2( 101 1 NC t 15 ) , GATE INI 15, 51 DIMENSION 1A< 15,15I,SUC( Ul NSUC=0 NI=0 INI=TOP 3 DO 20 IDES=l,NONR IF( $A( INI , IDES). EO. 01 GO TO 20 NSUC = NSUOl SUC(NSUC)=IDES NN=1 5 IFINN.GE.NSUCI GO TO 20 IF(SUC(NN).EQ.SUC(NSUC») GO TO 10 NN=NN+l GO TO 5 10 NSUC=NSUC-1 20 CONTINUE IF(NI .GE.NSUCI RETURN NI=NI*1 INI=SUC«NI I GO TO 3 END SUBROUTINE WRDOR ( $A , $W , *0, LOW, LAST, WI R ,WOR , I WGI IMPLICIT INTEGER*2 (A-Z,$) COMMON N0NP,N0VR,K1( 10), K2( 10), NCI 15) , GATE INI 15,5) DIMENSION $A(15,15),$W(15,4),$0(15,15),WIR(10,10),KOP(10,10), 1 CHECK ( 15,35),GSET(10,10),NG(10I,INP(10) ,NSAME(101 f 2 NSAMTI10) DO 10 I=1,N0NR DO 10 J=l,35 10 CHECK( I,J)=0 DO 400 IL=LOW,LAST IF(NC( ID.LT.2) GO TO 400 NI=0 DO 100 IY=1,N0VR IF(4W( IL.IYJ.NE.l) GO TO 100 IF(CHECK(IL, IY+15), >EQ. .1) GO TO NI=NI*1 NGINI )=0 DO 90 IX=1,N0NR IF( IX.EO.IL) GO TO 90 IF( *W( IXfIYl.NE.ll GO TO 90 NG(NI )=NG(NI )♦! CHECK! IX,IY*151»1 GSET(NI,NG(NI))=IX INP(NI )=IY*15 90 CONTINUE 100 CONTINUE DO 200 IY=1,N0NR IF( tA( IYtILl.NE.il GO TO 200 IF(CHECK« ILf IYI.EO, .11 GO TO 200 NI=NI*l NG(NI )«0 100 SE 10 SE 11 SE 12 SE 13 SE 14 SE 15 SE 16 SU 1 SU 2 SU 3 SU 4 SU 5 SU 6 SU 7 SU 8 SU 9 SU 10 SU 11 SU 12 SU 13 SU 14 SU 15 SU 16 SU 17 SU 18 SU 19 SU 20 SU 21 SU 22 SU 23 WR 1 HR 2 WR 3 WR 4 WR 5 WR 6 WR 7 WR 8 WR 9 WR 10 WR 11 WR 12 WR 13 WR 14 WR 15 WR 16 WR 17 WR 18 WR 19 WR 20 WR 21 WR 22 WR 23 WR 24 WR 25 WR 26 WR 27 WR 28 WR 29 WR 30 WR 31 97 190 200 290 300 305 310 320 330 350 360 370 DO 190 IX» IF( IX.EO.I IF($A< IY, I NG(NI ) = NG( CHFCK( IX, I GSFT(NI,NG INP(NI )=IY CONTINUE CONTINUE 00 100 IY= 1 F ( $ 1 i I Y , I IF(CHECK( I NI=NI*1 NT, (NI > = DO 290 IX= IF( IX.cO.I IF($0( IY, I NG(NI l=NG( CHECK( IX, I GSmNI.NG INPINI ) = IY CONTINUE CONTINUE IFINI.LE.1 00 305 NST NSAMT(NST) NST = NIl=NI-l DO 390 INI IFJNST.EQ. DO 310 INS IF(NSAMT( I CONTINUE NS = IP(NGdNI) INIl=INI«-l DO 350 JM 1F(NG( INI ) NG1=NG(INI DO 330 ING IF(GSET( IN CONTINUE NS=NS*1 NST=NST+i NSAMEINS1= NSAMT(NST) CONTINUE IFINS.EO.O IWG=IWG«-1 Kl( IWG)=NS K2(IWG)=NG WOR(IWG,l) ILT=K2(IWG DO 360 J=2 WOR( I WG, J) WIP(IWG,1» ILT=KKIWG DO 370 J=2 WIR( IWG, J) CALL SECNS CALL SECNS l.NONR L) GO TO 190 X).NE.l) GO TO 190 NI )«-l Y) = l (NI) )*IX l.NONR D.NE.l) GO TO 300 L, IY+20).E0.1I GO TO 300 1,N0NR LI GO TO 290 XJ.NE.l) GO TO 290 NI )*1 Y*20)*l (NI J )*IX ♦ 20 ) GO TO 400 = 1,10 = ■ltNIi 0) GO TO 320 T»l,NST NSTI.EQ.INI) GO TO 390 .EO.O) GO TO 390 =INI1,NI • NE.NGIJNin GO TO 350 ) =1,NG1 I, ING).NE.GSET< JNI.INGH GO TO 350 JNI *JNI ) GO TO 390 ♦ 1 ( INI)*l = IL I tILT *GSET( INI.J-l) -INP(INI) ) »ILT *INP(NSAME(J-i)) ( WIR.IWG.KK IWG) I ( WOR ,IWG,K2( IWG) ) WR 32 WR 33 WR 34 WR 35 WR 36 WR 37 WR 38 WR 39 WR 40 WR 41 WR 42 WR 43 WR 44 WR 45 WR 46 WR 47 WR 48 WR 49 WR 50 WR 51 WR 52 WR 53 WR 54 WR 1 54 WR 55 WR 56 WR 57 WR 58 WR 59 WR 60 WR 61 WR 62 WR 63 WR 64 WR 65 WR 66 WR 67 WR 68 WR 69 WR 70 WR 71 WR 72 WR 73 WR 74 WR 75 WR 76 WR 77 WR 78 WR 79 WR 60 WR 81 WR 82 WR 83 WR 84 WR 85 WR 86 WR 87 WR 88 WR 89 WR 90 WR 91 98 390 CONTINUE K giBflBa mfflWOTi i ■9 llllili KnMBDSuDGuflOi IS llllHIi