LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 I£6t t\p. 541-546 cop 2- Digitized by the Internet Archive in 2013 http://archive.org/details/studyofeffectofa543mora , UIUCDCS-R-72-5^3 yjiaH c&b a. A STUDY OF THE EFFECT OF ADDITIONAL INEQUALITIES IN INTEGER PROGRAMMING FOR LOGICAL DESIGN by Jose Joaquin Mora-Tovar October, 1972 THE uaRAftr OF THE NOV* b 1972 ^V^SITYOFimNOIS ATiyr. &e&mNm UIUCDCS-R-72-5^3 A STUDY OF THE EFFECT OF ADDITIONAL INEQUALITIES IN INTEGER PROGRAMMING FOR LOGICAL DESIGN by JOSE JOAQUIN MORA-TOVAR October, 1972 Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois, October, 1972, and supported partially by the National Science Foundation under Grant No. NSF GJ-503A #1. Ill ACKNOWLEDGEMENT The author would like to thank Professor Saburo Muroga and his logical design group at the University of Illinois. Special thanks should be expressed to those whose ideas, comments and indispensable help made this work possible: Tso-kai Liu, Keith R. Hohulin and Jay N. Culliney. The author is also grateful to Mrs. Margaret L. Gidel for her help with the English grammar and for typing this paper. This work is dedicated to my wife and son. IV TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. PROBLEM STATEMENT 2 3. COMPUTATIONAL RESULTS AND CONCLUSIONS 15 3-1 NOR design 15 3.2 NOR -AND design with all-interconnection formulation 32 3*3 NOR-NAND design with all-interconnection formulation 36 3'h AND-OR design with all-interconnection formulation 38 3.5 Overall Conclusion kl LIST OF REFERENCES i+3 APPENDIX A 1+5 APPENDIX B 82 1. INTRODUCTION Logical design by integer programming has proved to be an efficient approach to finding optimal networks .[10, 11, 12]. Several computer programs for the logical design of optimal networks by integer programming techniques have been prepared at the University of Illinois. This work is concerned with computer programs based on the Implicit enumeration method, and inequalities added to the integer programming problem, in order to speed-up the execution time. These additional in- equalities, based on intrinsic properties of the networks, are incorporated in the inequalities for the integer programming logical design. The objective of the present work is to establish how effective these additional inequalities are in reducing the execution time of the mentioned programs for several cases of network design. 2. PROBLEM STATEMENT It is assumed that the reader is familiar with integer linear programming or that he can easily refer to available publications in that field [10, 11, 12, 13]. Integer linear programming techniques have been implemented by computer programs to solve the optimal design problem for logical networks. The implicit enumeration method based on inequalities is used at the University of Illinois after computational experiences with logical design. Description of the algorithm used is available in the literature [1, 6, 11, 12, 13]. As previously stated, the inclusion of additional inequalities based on some features of gates and networks is found to speed-up the execution time of the computer programs [1, 10, 11]. In what follows, it will be determined to what extent each type of additional inequality effects the computation time for the following cases of logical design: (i) - Networks with three input variables and five NOR gates. (ii) - Networks with three input variables and six NOR gates, (iii) - Networks with three input variables and seven NOR gates, (iv) - Networks with four input variables and five NOR gates. (v) - Networks with four input variables and six NOR gates, (vi) - Networks with four input variables and seven NOR gates, (vii) - Networks with three input variables and five NOR or NAND gates(i.e., each network consists of a mixture of NOR and NAND gates), (viii) - Networks with four input variables and. five AND or OR gates(i.e., each network consists ef a mixture ef AND or OR gates).. 3 (ix) - One-bit adder networks with three input variables and eight NOR gates. For all cases the all-interconnection formulation was used. In addition, the feed-forward formulation was used for cases (i) and (ii) under several combinations of types of additional inequalities. The following assumptions are made in the present work: (1) Complemented input variables are not available, i.e., the so-called "single rail logic" is assumed for NOR, NOR-AND and NOR-NAND design cases. But both complemented and non -complemented input variables are available in the AND-OR design case. (2) No fan-in or fan-out restrictions are considered (although they can be included in the programs used) . (3) The number of levels for the implementation of the networks is not restricted (though the programs permit this restriction to be included). (h) Except for the one-bit adder design case, the number of outputs of the networks is limited to one (although the programs, again, permit multiple outputs) . Let us show the additional inequalities for the logical design cases of interest in this paper. First we need some notation conventions in order to understand the formulas which appear below. Variables are needed to represent : a) the external variables which are inputs to the network gate; b) whether or not an external variable connects to a gate (G); c) whether or not a gate (G ) connects to another gate (G ), and 1 3 d) the type of the gate when more than one type is involved. In the given order, these variables are: a) x , x p , ..., x represent n uncomplemented variables (or simply variables) which can be external input variables. Also, x. , x p , ..., x represent the corresponding complemented variables. k b) v. . is a connection from the i-th external variable, x . , to the ;i-th gate, G . ; v. . can take on the values given by: J •*- J J 1 if the connection exists v. . = < " | if the connection does not exist. v. . will represent in similar way connections from complemented variables to gates. c) ex.. . represents the interconnection from gate G. to gate G., and its value will be: J 1 if the interconnection exists a. . = / J if the interconnection does not exist. d) As we are concerned with at most two different types of gates in the logical design of networks with a mixture of types of gates, \. will J represent the type of gate j. \. will take values as given by: J i - in the case of networks with a mixture of NOR and NAM) gates J 1 if the gate is NOR J | if the gate is NAND ii - in the case of networks with a mixture of OR and AND gates and if the gate is AND iii - in the case of a network with a mixture or NOR and AND gates J 1 if the gate is NOR J I if the gate is AND In what follows, formulas are given without deduction, which can be found elsewhere [1, 12, 13]. For logical networks using NOR gates we can establish five types of additional inequalities (from now on let us refer to them simply as "inequalities") : ■it- Type 1 - Each gate must have at least two input interconnections or at least one input connection. This condition can be expressed by the inequalities: Z a; . + 2 Z v. . > 2 j = 1,2,..., R-l for f.f.f. i=l ID i=l 1 <3 - R n and Z a. . + 2 Z v., • > 2 j = 1,2,..., R-l for a. i.f. i=l iJ i=l 1 J — Type 2 - Every gate (except for the output gate) must have at least one output interconnection to another gate in the network. This is an obvious condition in order to have the gate within the network, and can be expressed by the inequalities: R Z a. . > 1 i = 1,2,..., R-l for f.f.f. j=i+l ia R and Z a > 1 i = 1,2,..., R-l for a. i.f. * For the sake of simplicity, let an input be defined as a connection from an external variable to a gate or an interconnection from one gate to another; the words connection or interconnection will be added, as qualifiers, to the word input when the distinction between the two types inputs is necessary. ** For the formulas about inequalities, f.f.f. stands for feed-forward for- mulation and a. i.f. for all-interconnection formulation. The gates are numbered from 1 to R; G being the output gate. For details about f.f.f. and a. i.f. see [1, 10]. As a convention, summations Z are assumed to be set to zero, if the upper limit takes values less than the lower limit. 6 Type 3 - A gate which is interconnected to the output gate is not interconnectec to any other gate. The corresponding inequalities are: R-l U (1 - a._) > S .. a. . i = 1,2,..., R-2 for f.f.f. iR - j=i+i ij R-l and U (l - a._) > Z a . . i = 1,2,..., R-l for a. i.f. IK — j=l 1J where U is a positive number, large enough so that the inequalities ■become non-restrictive if 0^ - 0. Type h - For the structure shown in fig. 1 the network is not optimal if ^ii = a ik = a ik = ^-t an( ^- ^ S & ^ e G. has no other output inter- connection. This condition, usually referred to as the triangular condition, is expressed by: + a + a i = 1,2,..., R-2 lk jk j = i + 1, 2,..., R-l k = j + 1, 2,..., R for f.f.f. R Z a + 2 > a ^=d+i j£ id #k Z a u +2 > a.. +a. k+ a. k i = 1,2,..., R lH J = 1*2,..., R i^k k = 1,2,..., R i t 3 f k for a. i.f. no other outputs Type 5 - This inequality type is the triangular condition with gate G i in fig. 1, replaced by an external variable x.. Then we have: It k 3 = 1,2,..., R-l k = j+1,2,..., R i = 1,2, . . ., n for f.f.f. 8 | =1 a U +2 ^ v io + v ik + a ,-k J = 1 > 2 '"" R i# k = 1,2,..., R i^k i = 1,2, . . ., n for a. i.f. All inequalities described in the following refer to the all' inter- connection formulation only. For the NOR-AND design case the following inequalities apply: Type 6 - This inequality is a replacement for inequality type 1 of the NOR design case, and it takes into account the two different types of gates we now have. The inequality establishes the condition that every AND gate must have at least two inputs, while a NOR gate must have at least one. Then: n R J 1 for a NOR gate where X . = ( to J ] for an AND gate The NOR-AND design case includes two more sets of triangular conditions similar to those for inequalities types K and 5 of the NOR design case; these inequalities are: Type 7 - If either gate G. or gate G, in the triangular condition (see fig. l) J is an AND gate, the triangular condition still holds, even if G. J interconnects to other gates different from G . In terms of inequalities: \, + 2 > a. . + a., + a., i = 1,2,..., R k — 13 ik 3k J — -L,2, • • • , K and \ + 2 > 0^ + a ik + a k = 1,2,..., R for i ^ 3 ^ k and X as previously defined. Type 8 - In inequality type 7 gate G. can be replaced "by a connection from an external variable and the triangular condition still holds; the inequalities expressing this are: X k + 2 > v.. + v. k+ a. k 3 =1,2,..., R k = 1,2,..., R X. + 2 > v. . + v., + a . j —13 ik jk l = 1,2,..., n J ^ k Besides inequality types 6, 7 and 8, for NOR-AND design case inequality types 2 through 5 of the NOR design case still hold. The same is true for the NOR-NAND design case but the presence of a new type of gate, NAND, brings in the following four new types of inequalities; Type 9 - Each gate has at least one input connection or interconnection. The corresponding inequality is: Ev+Ea > i 3' = 1,2, ..., R i=l 13 1*1 13 ~ * See Appendix B for programming details. ** See Appendix B. 10 There is another type of triangular condition for NOR-NAND design case as follows: Type 10 - This inequality implies that if gates G. and G, in the triangular condition are of different type , then the triangular condition (see fig. l) holds even if gate G. interconnects to gates other than G , J k i.e. : 2 + (l - \ ) + \> a ± + a ik + a i = 1,2,..., R* J = 1,2, . . ., R 2 + (1 - \) + V. > u ± j + a ik + a k = 1,2,..., R 1 for a NOR gate now X. = 1 I for a NAND gate Type 11 - In inequality type 10 gate G. can he replaced by an external input. Then : -X--X- 2 + (1 - Vj) + X k > v.. + v. k + C. k J = 1,2,..., R k = 1,2,..., R 2 + (1 - x. ) + \. > v. . + v., + a.. . _ _ k j — 13 lk jk 1 = 1,2,..., n 3 ^ k Type 12 - If a gate has only one input, it can he set to a NOR gate: R n X. + Z a. . + Z v.. > 2 j = 1,2,..., R J i=1 13 i=1 13 - Md * See Appendix B. ** See Appendix B. 11 In the case of AND-OR design, inequality types 2 and 3 about input and output conditions for NOR design are still valid, but the other conditions modify to the five following new types of inequalities: Type 13 - This is again a modification to inequality type 1 according to the types of gates, AND and OR. It states that each gate must have at least two inputs. In terms of inequalities: Z v + Z a . + Z v, . > 2 j = 1,2,..., R (13) i=l J i=l J i=l J i a where v. . stands for the connection from a complemented variable X. to the gate G. f as previously defined. This is necessary in AND-OR -*- J design since we need a complete set of logical functions to realize a general boolean function [13] • Type lU-The triangular condition holds even if gate G. interconnects to one J or more gates different from G, . This is formalized with the k expression: 2 > a. . + ex.. + a., i = 1,2,..., R - 13 lk jk > > > j = 1,2, . . . , R k = 1,2,..., R Type 15 - In the triangular condition of inequality type lU gate G. can be replaced by an external variable input, complemented or not, then: 2 > v. . + v. n + en., , . _ - ij lk jk j = 1,2,..., R or 2 > v. . + v., + a ., " 1J lk Jk i- 1,2,..., n J i k 12 Type l6 -If gate G. interconnects to gate G. and the gates are of the same type( both are AND gates or OR gates), then G. must have at least one more output interconnection: R E a. . + X. + \. > a. . i = 1,2,..., R tfl 3 = 1,2,..., R 1 /■j R S a. „ + 2 > \. + \. + a. . £ =1 li 1 10 Jl for an OR gate For AND-OR design \. = / 1 |0 for an AND gate Type 17 - In the network there must be at least one AMD gate and at least one OR gate: R E X. > 1 i=l 1 - ; R and R - 1 > Z X. - i=l 1 The above types of inequalities, type 1 to type 17, are not the only ones that can be established for the logical design cases since some kinds of geometrical symetries and ordering between the gates can be exploited, in order to preclude certain network configurations from being generated during computation. However, only those seventeen types were used in the logical design by integer programming, in order to limit the number of additional inequalities to a reasonable size [1, 7, 8]. See table 1 for the inequalities tested in each design case in this work. 13 H X H X LP\ rH o H X on X 3 X H rH X o rH X Oa X CO X! t- X VD X \T\ XI X X J- X X X m X X X o OJ X X X X H X inequality type design case * 6 is i 8 1 1 6 g 1 CD W CO O • a nd •H CD W M CD o •V CD 43 CD O 43 -P -P o O id -P ra >. CD H £ Ph • ft ■d -p cO • CD 3 S3 X p -P Eu u O •H CD W S3 W XI CD CD O -H w Td H CD w Ph O ?H cO ft ^3 CD JS CO ■-r, >> -c CD CD +3 CO ££ •H H -!-' -P +3 CO •H 3 43 >> >> o 1 1 -P "P CD CD •H -H S3 d rH rH •H co cO 2 3 QJ C1J O 1 D<43 .'■: CD -P ! s3 d •H -H -P 4n CO 1 1 CD CD 43 43 43 -P CD -P -P m w CO ■P +3 CD O CO CO •H 43 43 tH CD -P -P •H .'• : w ra S i CD CD •H w •H -rl w cu £h «h t» -i •H -H ^) a S) S) CO •H -H H q W W 42 •H X O < * ■H 03 CD 13 CO CJ •H bu o rH CD 43 -P U o Ch T3 CD ^ O CD 43 O CD fn CD £ S3 CO >? H R* ft CO O •H ■g w CD •H -P •H H CO a 1 CD S3 •H H co o •H +3 •H T3 t3 < CD H ■s Ik For computational purposes two different programs were used: ILLIP (standing for ILL inois Integer Program) for the feed-forward formulation and ILLODIE-AIF (standing for Illinois LOgical Design Implicit Enumeration using the All-interconnection Inequality Formulation) for the all inter- connection formulation. Descriptions of the programs and programming manuals for them are available [5,9l> and we will not discuss these programs here. Computation was arranged in such a way that for every design case and almost all tested functions, the programs were run first with all additional inequalities included, and then with some types of additional inequalities removed. The types of inequalities which were eliminated varied with the different design cases. For some cases (see tables 8 and 9), additional inequalities were all removed for one of the runs, then the different types of inequalities were included individually or in different combinations on subsequent runs. This was done in those cases in which the results removing inequalities were not very conclusive and an additional test appeared to be necessary. 15 3. COMPUTATIONAL RESULTS AMD CONCLUSIONS literature as indicated in Appendix A. The number of functions used in each case was determined from the consideration of computer time cost, though the greater number of functions the more reliable the statistics would be. 3.1 NOR design 3.1.1 NOR design with all-interconnection formulation a) Table 2., which is a summary of tables A 12., A 13^> and A ik. in Appendix A shows the average computation times for five functions in each of the three tested design cases: with five, six, and seven NOR gates. The all-inter- connection program was run first with all additional inequalities included, and then all combinations of additional inequalities were removed, one-by-one and in pairs. The main purpose of these runs was to determine for the NOR design case if the effect of the additional inequalities when removed in pairs is additive or not. As can be seen in table 2, the effect of removing in- equalities is not additive; it can be observed, however, that the effect of a specific type of inequality when removed alone is in the same direction as when it is removed in combination with some other type of inequality. For example, inequality types 1 and 3 produce the largest execution time figures when individually removed and then, when they are both simultaneously 16 case 5 gates 6 gates 7 gates t I F0 t I FO t I FO All inequalities included 1.12 29 111 1+.61 132 ll+ 3k.60 869 122 All except type 1 1.29 1+0 16 ^•77 128 Ik 37.72 982 119 All except type 2 1.12 29 ik k-31 132 Ik 33.9^ 869 122 All except type 3 1.25 36 19 5.20 163 15 1+1.50 1120 ll+9 All except type k 1.11 29 11+ 1+.52 ll+8 11+ 30.28 1081 122 ; All except type 5 1.06 29 11+ 1+.21+ 132 11+ 32.60 869 122 ! All except types 1,2 1.39 1+0 16 ^•75 128 11+ 37.69 982 119 ; All except types 1,3 1.5U ki 19 5.1+2 172 15 1+1+.1+5 1201+ 152 ; All except types 1,1+ 1.22 ko 16 If. 70 170 lU 39.23 1211+ 119 All except types 1,5 1.22 1+0 16 k. 1+1 128 ill 3^.69 982 119 Table 2. Three variable NOR design. (All-interconnection formulation) . (Summary of Tables A 12., A 13., A ik. in Appendix A). (continued) 17 case 5 gates | 6 gates 7 gates T I F0 t I F0 t I FO All except types 2,3 1.27 36 19 5.13 163 15 1+1.01 1120 ll+9 All except types 2,k 1.10 29 Ik !+.32 ll+8 11+ 36.28 1081 122 All except types 2,5 1.08 29 Ik 1+.22 132 ik 32.55 869 122 All except types 3,k 1.20 37 19 5.10 181 15 1+1.88 1376 150 All except types 3,5 1.22 37 19 ^•93 163 15 38.1+9 1122 ll+9 All except types l+,5 O.98 29 lU 3.97 1U8 ik 32.25 1081 122 Maximum of the Averages 1.5** hi 19 5.U2 181 15 1+1+.1+5 1376 152 Minimum of the Averages 0.98 29 lU 3-97 128 Ik 32.25 869 119 Number of Functions , Tested 5 5 5 (continued from the previous page) Table 2. T hree variable NOR design. "(All-interconnection formulation) . (Summary of Tables A 12., A 13., A Ik. in Appendix A) 18 removed, they produce the largest execution time of all tested combinations. In a similar analysis, it can he observed that in- equality types h and 5 show the smallest figures for execution time in table 2, when they are individually removed, and again their combination, when removed, produces the smallest of all execution times, even smaller than that of the case in which all inequality types were included. b) Table 3«> which is a summary of tables A 1., A 2., A 3« in Appendix A, shows the average computation time for almost al] possible functions with three input variables in NOR designs with five gates, and for all the functions with three input variables in NOR design with six and seven gates. After the non-additivity of the effect of the removal of different inequality types on the computation time was established, as shown in part a), only the removal of individual types of inequalities was considered. In table 3«> it is observed that the largest figures for the average of the execution time in the cases of five, six seven gates are given by the removal of inequality types 1, 3 and 3 respectively. The second to the largest time is produced by the removal of inequality types 3, 1 and 1, corresponding to the five, six and seven NOR gates design. This implies that inequality types 1 and 3 are very effecth in reducing execution time when they are present in the program. 19 case 5 gates 6 gates 7 gates t I F0 t I F0 t 1 F0 All inequalities included 0.97 29 12 5.30 157 32 32.92 821 100 All except type 1 1.20 39 Ik 5.96 182 1+1 35.52 920 106 All except type 2 0.98 29 12 5-12 157 32 32. ik 821 100 All except type 3 1.05 33 Ik 6. 2k 199 k2 39-22 1052 131 All except type k 0.93 29 12 5.20 179 35 3^.52 1027 100 All except type 5 O.96 30 13 U.96 158 32 30.93 821 100 Maximum of the Averages 1.20 39 Ik 6.2k 199 k2 39.22 1052 131 Minimum of the Averages 0.93 29 12 k.96 157 32 30.93 821 100. Number of Functions Tested 22 15 6 t I F0~: average computation time in seconds. average of total number of Iterations for the solution. average of number of iterations to obtain First Optimal solution, Table 3. Three variable NOR design. (All-interconnection formulation) . (summary of Tables AL, A2., and A3. ). 20 It is also noticed in table 3 that "both inequality types 1 and 3 appear to be more effective when the number of gates increases since the differences from the figures for the run in which all inequality types are included become larger as the number of gates is increased. Inequality types k and 5 when removed from the program produce execution time figures which are the smallest for the 5 gate case while inequality type 2 produces almost no effect in computation time. It is observed, however, that when the number of gates increases inequality type k becomes more effective in reducing execution time, inequality type 5 instead produces an adverse effect when the number of gates increases but inequality type 2 remains ineffective. These analyses lead us to conclude that inequality types 1 and 3 should always be included in the program if we want to obtain the minimum execution time. Inequality type k should be included for designs with more than 6 gates and inequality types 2 and 5 should be removed since they do not affect execution time (type 2) or affect the execution time adversely (type 5). Let us check the NOR design with four input variables. In observing table k it is noticed that inequality type 3 produces the largest time figures for all number of gates; inequality type 1 is now less effective in reducing execution time than in the case of three variables; and inequality types 2 and 5 have almost no affect on execution time especially for 21 case 5 gates 6 gates 7 gates t I F0 t I F0 t I F0 All inequalities, included 2.22 1+2 13 31o32 636 1+2 117.17 2071 1+1+8 All except type 1 2.66 5h 16 39.88 8lk 1+2 119.1+2 2091 1+56 All except type 2 2.39 1+2 13 32.95 636 1+2 119.1+9 £071 1+1+8 All except type 3 2.68 53 16 1+1+.5 972 81 159.38 2932 681+ All except type k 2.17 1+2 13 31+.16 73^ 1+2 133.16 2587 1+1+8 All except type 5 2.28 1+2 13 29.66 636 1+2 120.70 2327 1+88 Maximum of the Averages 2.68 51+ 16 1+1+.5 972 81 159.38 2587 681+ Minimum of the Averages 2.17 1+2 13 29.66 636 1+2 117.17 2071 1+1+8 Number of Functions Tested 10 5 1 t I_ FO average computation time in seconds, average of total number of Iteration for the solution. average number of iterations to obtain First Optimal solution. Table k. Four variable NOR design. (All-interconnection formulation) . (Summary of Tables Al+., A 5-, A 6. ) 22 the case of seven gates. Inequality type k shews a similar behavior to the three variable design. It should be noticed that for seven gates all inequality types are effective in reducing execution time. This tendency appears to show that when the number of gates and the number of variables increases the additional inequalities become more effective regarding execution time. It can be concluded that inequality types 3 and k should, always be included in the program if we want to obtain the minimum execution time, and inequality type 5 should be re- moved, from the NOR design case with five and six gates, but probably should be included for designs with more than six gates. Unfortunately, fund, limitations for computation time impeded testing of designs with eight or more gates (see [2] ) to obtain reliable statistics to confirm the last assertion. Further research in this direction is desirable. c) In table 5, results are shown for the design of a one-bit full adder with eight NOR gates. It can be observed here that removal of any type of additional inequalities decreases execution time with respect to the case in which all inequality types are included. This appears to show that additional in- equalities, in this case, can be removed without increasing execution time. In fact, the name table shows the execution time drastically reduced for the case in which all additional inequalities were removed, in comparison to the case in which all the additional inequalities were included. In addition, 23 case t 1 FO All inequalities included 55.7*+ 1029 16 All except type 1 52.59 10U9 16 All except type 2 51.76 1029 16 All except type 3 53.67 1029 16 All except type k 1+1.58 1073 16 All except type 5 ^7.1+0 1029 16 All inequalities removed 36.61* 1081 16 With type 1 onlv 37-20 1073 16 With type 2 only 35.65 1081 16 With type 3 only 36.16 1081 16 With type It only 1+9.31 10U9 16 With type 5 only to. 32 1081 16 Maximum values 55-7^ 1081 16 Minimum values 35.65 1029 16 t FO time in seconds total number of iterations to obtain all solutions number of iterations to obtain First Optimal Solution Table 5. Three variable, eight NOR gate, one-bit Full Adder design. (All-interconnection formulation) . 2k it should be noticed, that when inequality types 1, 2, and 3 were individually added to the program, the difference with the case of all inequalities removed is very small (addition of inequality type 2 slightly reduces time but judging from the number of iterations, it could be due to timing accuracy of the computer), and that inequality types k and 5 produce the worst effect in execution time when included in the program. 3.1.1.1 Summary of conclusions for the NOR design with all interconnection formulation (i) - It can be said, in general, and according to the results i the previous section, that the inequality type which has the best effect in reducing execution time for single output NOR networks with the all-interconnection formulation is "type 3 j in both three and four variables cases. It would also be desirable to include types 1 and k, though they are ; not always as effective as type 3* (ii) - Inequality types 2 and 5 could be left out of the program, since they have adverse effect or marginal speed improvement. They might be, however, effective for five or more variables, or for eight or more gates. Inequalities related to the triangular condition (i.e., types k and 5) probably because of the great number of additional inequalities generated, actually increase executior time in some cases. Then additional inequality types h and 5 should be removed, for the case of' five or less NOR gate design but apparently they should be included for cases 25 of six or more NOR gate designs according to the numerical results discussed above. Table 6 summarizes the effect of additional inequalities for the NOR design with the all-interconnection formulation program. case most effective types marginally effective types adversely effective types CD H & CD >H U CD > CO 5 gates 1,3 2 ^5 6 gates 3,1 2 M 7 gates 3,1^ 2 5 QJ H CD ■H in CD > 5 gates 3,1,2 5 k 6 gates 3,1,* 2 5 7 gates 3,U 1,2,5 one -bit Full adder »*, 5, 1,3,2 Table 6. Comparison of the effect of additional inequalities on NOR design with all-interconnection formulation. 26 3.1.2 NOR design with feed-forward formulation a) - In the case of using the feed-forward formulation program for the NOR design case, table 7> which is a summary of tables AT* and A 8* in Appendix A, shows that inequality types 5 and 1 in this order produce the largest execution times when removed from the program, while inequality types 3, h and 2, again in the given order, produce the smallest execution times when removed from the design program for five NOR gates. Similarly, in designs with 6 gates, inequality types 1 and 3 give the largest execution times and inequality types h, 5 and 2 give the smallest ones. Unlike the NOR case with the all-interconnection formulations, all types are effective. b) - In order to compare the effect on execution time from a different angle, a separate test for ten functions and five gate NOR design, with the feed-forward formulation program, was run (table A 9» ) • For this test, all additional inequalities were initially removed and then each inequality type was added. Results for this test, (see table 8), which is a summary of table A9» in Appendix A, proved the reduction of execution time given by inequality type 1, followed by inequalit; types 2,' 5 and 3* decreasing in this order.. Inequality type k appears to have little effect on the computation time. c) The results above were confirmed by an additional test, made on two of the functions, one for five NOR gates and one for six NOR gates, as shown in table 9. For this test, the 27 case 5 gates 6 gates t I FO t I FO All inequalities included k.26 118 35 62.16 1813 157 All except type 1 5.16 168 53 122.20 1+2 71+ 293 All except type 2 If. 58 137 38 77. 1+2 2158 191 All except type 3 1+.U8 131 1+1 78.96 2397 26l All except type 1+ k.56 137 37 70.07 2007 222 All except type 5 5.80 171 kk 73.01+ 1992 69 Maximum of the Averages 5.80 171 53 122.20 ^27^ 293 Minimum of the Averages k.26 118 35 62.16 1813 69 Number of functions tested 22 5 t I FO average computation time in seconds. average Total number of iterations for the solution. average of number of iterations to obtain First Optimal Solution* Table 7« Three variable NOR design. (Feed-forward formulation). (Summary of Tables A 7. and A 8 . ) 28 case t I FO All inequalities lk.2h ^39 67 removed With type 1 l.kk 2^9 h9 only With type 2 11.28 397 58 only With type 3 13.69 >+57 113 only With type k Ik. 62 kQh 69 only With type 5 11.61 399 15U only Maximum of the 1U.62 1+8U 15U Averages Minimum of the l.kk 2U9 58 Averages Table 8. Three variable, five NOR gate design. (Feed-forward formulation). Adding inequalities one -by-one (Summary of Table A 9. ) 29 case 5 gate NOR fun. 37 [4] 6 gate NOR fun. 60 [1+] All inequalities removed 14.73 219.84 With type k only 14.48 348.75 With types k,l only 7-83 - With types 4,1,2 only 7.18 - With types 4,1,2,3 only 5.80 - With type 1 only 8.39 102 . 16 All inequalities included 3.72 54.67 Maximum time 14.73 348-75 Minimum time 3.72 5U.67 case not tested. Table 9- Three variable, NOR design. (Test cases for feed-forward formulation) 30 program was run with all additional inequalities removed first, then adding the other additional inequalities one- by-one in successive runs. In the case of the function for five gates, the weak effect of inequality type h on the execution time, and the strong effect of inequality type h when added to the program, can be observed. Notice that all inequalities proved to be effective in reducing execution time for that particular function. For the six-gate function, in the same table (8) it can be observed that inequality type k had an adverse effect in execution time (more than 5&"$ time increase). While inequality 1 type 1 showed an improvement slightly above 53$ in execution time over the case of all inequality types removed from the program. Observing table A9«, in Appendix A, it can be noticed, however, that inequality type h showed a weak effect on the computation time for all the functions tested. Inequality "type 5> instead, produced a greater effect on the execution time, but this effect appears to depend mainly on the particular function tested. For most of the functions, however, the tendency was to decrease execution time. We can conclude then, that for the NOR design using the feed-forward formulation all inequalities, except the triangular condition (type k) appear to have an effect in reducing execution time. Since inequality type k showed a weak effect most of the time, and in some instances a strongly 31 adverse effect we are tempted to conclude that this inequality- type should he removed from the feed-forward formulation program hut again further research, especially for designs with more than five gates, is desirable to establish firmer conclusions in this respect. Table 10 shows the effect the different inequality types have on execution time for the feed-forward formulation. case most effective marginally effective adversely effective 5 gates removing inequalities 5,1 2,M 6 gates removing inequalities 1,3,2 5,U 5 gates adding- inequalities 1,2,5,3 k 6 gates adding * inequalities 1 h * This was incompletely tested and only one function was used. Table 10. Comparison of the effect of additional inequalities on the NOR design with feed-forward formulation for three variable functions. 32 In observing Tables 6 and 10 for the NOR design with the all-interconnection and the feed-forward formulations, respectively, it is observed that inequality types 2 and 3 are always effective in reducing execution time, inequality type h has weak or adverse influence, in general, for both formulations, and, in contrast, inequality types 2, and. 5 which showed almost no effect and a slightly adverse effect, respectively, for the all-interconnection formulation become more effective in the case of the feed-forward formulation. Then, and as a general rule, for NOR designs with all- interconnection formulation inequality types 1 and 3 should always appear in the program, inequality type 2 may or may not be removed without affecting execution time while inequality types k and 5 should be removed in designs. with five or six gates but should probably be included in designs with seven or more gates. For the feed-forward formulation, instead, all inequality types should be included in the program but more attention should be given to the inclusion of inequality types h and 5 in designs with more than five gates since their influence appears to be determined, to a great extent by the individual functions. 3-2 NOR-AND design. with all-interconnection. formulation For this design case, results shown in table 11, which is a summary of tables A 15 and A l6, demonstrated that removal of additional inequalities from the program does not produce additive effects on 33 case 5 gates 6 gates t I F0 t I FO All inequalities included 8.1+ 171 1+6 1+5.62 81+7 195 All except type 6* lit. 1+8 353 86 77.92 1530 270 All except type 2 8.05 171 1+6 1+J+.55 8I+7 195 All except type 3 10.02 202 52 57.80 103^ 217 All except type U 7.83 172 1+6 1+5.58 886 196 All except type 5 7-59 172 hG 1+1.61+ 853 197 All except type 7 ** 7-73 177 1+8 1+2.98 897 210 All except type 8 -** 8.06 177 U8 I+I+.70 870 201 All except types 2,6 lU.05 353 86 77.52 1530 270 All except types 3,6 15. 7U 383 97 90.1+0 1712 311 All except types k,6 13-66 355 86 75.90 l6ok 271 Table 11. Three variable, NOR-AND design. (All-interconnection formulation) . (Summary of Tables A 15. and A 16. ) (continued) 3^ case 5 gates 6 gates t 1 F0 t I FO All except types 5,6 13-51 35^ 86 7^.52 1550 272 All except types 7,6 13.76 357 87 76.60 1571 275 All except types 8,6 13.56 355 87 73-78 1550 271 All except types 2,3 10.80 202 52 58.8 1031+ 217 All except types 2,1+ 7.60 172 1+6 1+2. kQ 886 196 All except types 2,5 7-55 172 1+6 I+I.56 853 197 All except types 2,7 7.77 177 kQ 1+3.12 897 210 All except types 2,8 8.0^ 177 1+8 1+2. 8U 870 201 All except types 3,k 9.7^ 205 52 55.52 1085 219 All except types 3,5 9.63 203 52 56.68 101+3 220 All except types 3,7 9.85 219 60 57.92 1152 250 (continued from previous page) Table lie Three variable, NOR-AM) design. (All-interconnection formulation) . (Summary of Tables A 15. and A 16. ) (continued' 35 case 5 gates 6 gates t I F0 t I FO All except types 3,8 9-76 210 5h 5^.82 1072 223 All except types k,5 7.57 173 kG ^3.30 892 198 All except types U,7 8.03 190 53 1+3.95 1000 221 All except types k,8 7.66 178 kQ 1+2.22 909 202 All except types 5,7 7.50 177 kQ kl.^k 903 212 All except types 5,8 7.58 179 kQ UO.96 882 20l+ All except types 7,8 7.50 183 51 in. 58 93^ 221 Maximum of the Averages 15.7^ 383 97 90.1+0 1712 311 Minimum of the Averages 7.50 171 k6 U1.5U 81*7 195 Number of Functions Tested 5 k (continued from the previous page) * corresponds to type 1 in NOR design ** other triangular conditions t T FT) average computation time in seconds. average of total number of Iterations for the solution. average of number of iterations to obtain First Optimal solution. Table 11. Three variable, NOR-AND design. (All-interconnection formulation) . (Summary of Tables A 15. and A 16. ) 36 the execution time, but the effect of removing inequality types in pairs reinforces the results of removing inequality types individually in the same sense as in the NOR case. It can be observed in table 11 that inequalities type 6 and type 3 produced the largest execution times when individually removed from the program, and that inequality types 5, 7 and 8 reduce the execution times when removed individually. Conclusions for this case follow the same tendency as in the NOR design case with all-interconnection formulation, i.e. additional inequalities which restrict in some way the number of inputs or outputs to the gates (inequalities type 6 and type 3) > have the greatest effect in reducing execution tune when included in the program to solve the optimal design problem. Also additional inequalities related to the triangular condition (inequality types 5 and 7) produce the effect of increasing execution time when included in the program. Then inequality type 6 and 3 should always be included in the program and inequality types 5 and 7 should be removed from the program without an adverse effect in execution time. As inequality types 2, h, and 8 do not produce a significant effect on executions time, they may or may not be removed from the program, without affecting the execution time in a significant way. 3*3 NOR-NAND design with all-interconnection formulation For the ten functions tested in the NOR-NAND design case we observe in table 12 (see table A 10 for details), that the largest figure for average computation time is given by inequality type 12 followed by those figures given by inequality types 3 and k. Adverse effects case t 1 F0 All inequalities included 7.38 168 62 All except type 9 * 7.15 168 62 All except type 2 7.26 168 62 All except type 3 10.00 228 88 All except type k ■ 7.96 183 76 All except type 5 7.20 169 66 All except type 10 ** 7.12 168 62 All except type 11 *"* 6.86 168 62 All except type 12 *** 12.68 292 125 Maximum of the Averages 12.68 292 125 Minimum of the Averages 6.86 168 62 Number of Functions Tested 10 37 * corresponds to type 1 of NOR design. ** other type of triangular condition. *** unique for NOR-NAND design. t : average computation time in seconds. T : average of total number of iterations for the solution. FT) : average of number of iterations to obtain First Optimal Solution. Table 12. Three variable, five gate NOR-NAND design. (All-interconnection formulation). (Summary of table A 10} 38 are produced by inequalities type 11, type 10 and. type 9> while inequalities type 2 and type 5 have little effect on the computation time. We can conclude that inequalities type 12, type 3 and type k should not be removed from the program while inequalities type 11, type 10 and type 9 should be removed from the program if speed-up in execution time is desired. The rest of the additional inequalities, inequality types 2 and 5 may be left in or taken out from the program without affecting the execution time. 3.^ AND-OB design with all-interconnection formulation As it was shown in table 1 for this design case inequality types 3 and 15 were not tested and actually they were not included in the program at any time since storage requirements were too large to be justified at the moment the program was written and tested. In addition, the authors of the program thought that these two types of inequalities were not very effective in reducing execution time. In all tested cases inequalities type 3 and type 15 are removed, from the program. It should be noticed, observing table 13> that what happened in the NOR design case with the all-interconnection form- ulation appears to be reversed in the present case since now the elimination of the additional inequality related to the triangular condition, inequality type Ik, produces the largest figure in execution time. This inequality, in turn, is followed by the execution time figures produced, when inequalities type l6 and type 13 are removed. Almost no effect is produced when inequalities type 17 and type 2 are removed, from the program. 39 case •* t I F0 All inequalities included 37-90 589 57 All except type 13* 57.77 893 62 All except type 2 37.58 5.91 57 All except type lU** 85.8O 1663 108 All except type l6*** 61.89 1091 78 All except type 17*** 38.02 589 57 Maximum of the Averages 85.80 1663 108 Minimum of the Averages 37.58 589 57 Number of Functions Tested 10 * corresponds to type 1. ** another triangular condition. *** unique for AND-OR design. t I_ FO average computation time in seconds. average of total number of iterations for the solution. average of number of iterations to obtain First Optimal solution. Table 13 . Four variable, five AND-OR gate design. (All-interconnection formulation) (Summary of table Alio) 1+0 All of this implies that inequality types ik, ±6 and 13 should be included in the program in order to obtain the shortest execution times, and inequality types 2 and 17 may mor may not be removed from the program without significantly affecting the execution time for the design of" five AND or OR gate networks with the all- interconnection formulation program. Since, in this case, and the NOR -NAM) case, only five gate functions were used, it is suggested that more research should be done using functions which are implemented with a larger number of gates to obtain enough information that would permit more general and fundamented conclusions. Table ik. shows the effect of additional inequalities for the last three design cases discussed. case most effective marginally effective adversely effective NOR -AND 6,3 2-A8 5,7 NOR-NAND 12,3,^ 2,5 11,10,9 AND-OR Ik, 16,13 17,2 Table ik. Comparison of the effect of additional inequalities on NOR-AND; NOR-NAND, and AND-OR, designs with the all-interconnection formulation for three variable functions. hi 3.5 Overall Conclusion Tables 6, 10 and ik show the effects of additional inequalities on the execution time for the design cases of interest in this paper. Observation of those tables lead us to conclude that in general: l) The most effective types of inequalities in terms of reduction of execution time are: a) those which are concerned with the number of connections and interconnections permitted to the gates, such as type 1 for NOR design and its corresponding types in other design cases: type 6 for NOR-AND design, type 13 for AND-OR (but notice the exception of type 9 for N0R_NAND design), and b) those inequalities which prohibit certain types of output interconnections as inequality type 3 in the cases in which this type was tested. In this group can also be classified inequality type 12, applicable to the NOR-NAND design. 2) Inequalities which consistently show weak or almost negligible effect on the computation time are those corresponding to type 2 with the exception of the feed-forward formulation for NOR design; 3) The most adverse effect on execution time is presented by inequalities related to the triangular condition with the exceptions of some cases in the feed-forward formulation for NOR design and for the AND-OR design with the all-interconnection formulation. k2 These conclusions show only the apparent tendency of the effect of the inequality types on the computation time for different cases of logical design. In a specific case it is recommended to refer to tables 6, 10 or Ik, whichever corresponds, and to the adjoining conclusions to establish in a more proper way which inequality types should be included, or which should be excluded from the programs to obtain improvement of execution time. >+3 LIST OF REFERENCES Baugh, C. R., T. Ibaraki, T. K. Liu, and S. Muroga, "Optimum Network Design Using NOR and NOR-AND Gates by Integer Programming," Report No. 293> Department of Computer Science, University of Illinois, January, 19&9' Culliney, J. N. , "On the Synthesis by Integer Programming of Optimal NOR Gate Networks for Four Variable Switching Functions, " Report No. I+80, Department of Computer Science, University of Illinois, September, 1971. Culliney, J. N. , personal communication. Hellerman, L., "A Catalog of Three-Variable OR-Invert and AND-Invert Logical Circuits," IEEETEC, Vol. EC-12, No. 3, pp. 198-223, June, 1963. Hohulin, K. , "A Code for Solving Network Synthesis Problems by Implicit Enumeration Using the All-Interconnection Inequality Formulation, " Master Thesis, to be published as a report of the Department of Computer Science, University of Illinois. Ibaraki, T., T. K. Liu, C. R. Baugh, and S. Muroga, "Implicit Enumeration Program for Zero-One Integer Programming, " Report No. 305, Department of Computer Science, University of Illinois, January, 1969. Also in International Journal of Computer and Information Sciences , March, 1972, PP. 75-92. Ibaraki, T., T. K. Liu, D. Djachan, and S. Muroga, "Optimal Networks by NOR-NAND Gates," Department of Computer Science, University of Illinois, Report No. k2 r [, January, 1971. Liu, T. K. , K. Hohulin, L. E. Shiau, S. Muroga, "Optimal One-bit Full Adders with Different Types of Gates," to be published in IEEETC. Liu, T. K. , "A Code for Zero-One Integer Linear Programming by Implicit Enumeration, " Master Thesis, Department of Computer Science, University of Illinois, 1968. Printed as report, No. 302, Department of Computer Science, University of Illinois, December, 1968. Muroga, S., "Logical Design of Optimal Digital Networks by Integer Programming," in Advances in Information Systems Science, Vol. 3, J. T. Tou, Ed. Plenum Press, New York, 1970, pp. 283-3I+8. Muroga, S. and T. Ibaraki, "Design of Optimal Switching Networks by Integer Programming," IEEETC , June, 1972, pp. 573-582. Muroga, S. and T. Ibaraki, "Logical Design of an Optimum Network by Integer Linear Programming, Part I, " Report No. 26k, Department of Computer Science, University of Illinois, July, 1968. 1* [13] Muroga, S. and T. Ibaraki, "Logical Design of an Optimum Network by Integer Programming, Part II, " Report No. 289, Department of Computer Science, University of Illinois, December, 1968. [lU] Muroga, S., CS 391 Course Notes. University of Illinois, Fall, 1970. [15] Muroga, S., Threshold Logic and its Applications , .John Wiley and Sons, 1971. ^5 APPENDIX A TABLES OF DETAILED COMPUTATIONAL RESULTS The following tables show the results for each function used in the different design cases, the tables include: an identification number for the function, taken from the literature as given below; execution time in seconds (t) , total number of iterations to exhaust all possible optimal networks (i), and the number of iterations until the first optimal solution is generated (FO) , for each of the computer runs made. At the end of each table the averages for the three numerical values for each run are presented, but for the number of iterations (I and FO) we took the smallest integer greater or equal to the corresponding average. The functions were taken from the literature as follows: For NOR design, three variable case from [k], For NOR-NAND design from [7], For AND-OR design case and four variable NOR design case from [2 and 3] For NOR-AND design from [l] ,and For the one-bit full adder design case from [8] . o [X, VC 3 tA- H £1 H vo rH ! H H CA CA CA H A- H A- -p ft CD LT\ O X 1— 1 CO o co -3- OJ vo -J- OJ CO O VO CO CD CD H J- vc rH CO CO H CO CO CO 0J H B H -P H no co CO CA H CA H J" VC CO oo OA H H H H H H H H CA OA OJ H • ( O X CD CD s h- 1 J- o CO OJ A- A- co 0J D— -=r VC co OJ -=f vc OJ co CO H CO CO CO 0J H ( H -P q CA -3- CA VO CO J- -=t- OA CO -3- CA co < [A- OJ CO A- H H vo OA H H co CO < -p O H H O H H o O H H d d ^ o V_i CM t— 0J UA VO H CA CA OA a- A- < i ( < -p ft CD OJ O h H H H H H H H H ( ! < 4 X s CD CD H CO VC CO _-t 0J VO -=J- OJ CO O vc 00 H -P H CO VO H CO CO H CO CO CO 0J H r i-l ' sJ 0) -H -=f- H H VO CO -=r H VO VO CA CO VO (I a A- H CA VO O o VO OA o O CO VO <1 •H -P f. o H H o H H o O H H o o i— i 1 s -=J- i i -p s &H VO OJ A- OA O H CO CO O O A- 0O <3 u -2 CD CO OJ cvj OJ CO CO 0J CO UA J- -J- -J- -P cci a I — a All except type 5 o l>- o H CO CO 3 OO co LT\ OJ CO CA H oo H H VD OJ O OJ VO oo CO OJ -3" OJ OJ OJ OO OJ o oo oo OJ O OO -P CA I— O -4- o CA o H OO CO o oo o H OO O -=J- H H oo o H VD CO o H VD CA O All except type h O O- o H CO CO H H OO 00 LT\ OJ 00 CA H 21 M VD OJ O OJ o oo CO OJ -=J- OJ OJ OJ CO OJ O OO oo OJ H CA OJ -P H oo o CA o CA CO o H oo o OO VO o oo OO o OJ H OO o H H CA O H H OO CA O All except type 3 O P°H 0- o CO CO 3 00 CO H -3- OO OO OJ H H VO OJ OJ o oo OO OJ CO OJ OJ OJ CO OJ OO -4" OJ LT\ LTN oo -P o CO l>- o H H H H CA O oo o 00 oo o VO H H CO LTN H OO CA o CA VO H LT\ O H All except type 2 O c— o H CO CO d CO CO LT\ OJ co CA H 21 H VD OJ o OJ o oo CO OJ -3- OJ OJ OJ CO OJ o oo oo OJ H CA OJ -P OO CO o oo O oo CA O oo oo o CO o CA o H OJ H 8 O i CO o OO VD H 00 CA O All except type 1 O l>- O H CO CO 3 CO CO oo oo CA H J- H M vo J- O OJ -3- vo o OJ o J- OO oo O LTN oo OJ H LT\ CA OO -P VD H VO o VO VO H CA o H oo l>- o CA H H OJ H CA OO H co CO o VD t- H O OJ H All inequalities included O P-H l>- o H CO CO 3 co CO OJ CO CA H 21 M vo OJ O OJ O OO CO OJ J" OJ 0J OJ CO OJ o oo oo OJ H CA OJ -P oo CO d oo • O oo CA 6 CA 00 6 oo l>- 6 CA CO • o CO OJ H CA o H VO 00 d CO H CA 6 Functions numbered after Ik 1 J- IfA OO Q OJ H H LT\ 0O VD OJ OJ CA J- CA OO w OJ bO cd Ph cd ■ ^7 bfl CD ft to O •H > OJ Ph ft •H <4H CD Ph i CD H CO All except type 5 o O oo o OJ OA OJ OO LTN OO H vo OJ 0- H H CVI LTN H CM o vo H OO H OO -=t- H co H OJ 'UA OO o H OJ o OJ ! OJ OJ CVI -P co O OJ o LT\ o LTV OJ oo • -3- o OJ H OJ OA OJ OO OJ co vo o CA • VO' All except type h O F"H o m o OJ ON 0J OO LT\ OO IA- H vo OJ H UA H OJ LTN H 0A OJ co vo H LIA CO H t- i LTN H OJ vo OJ UA o H OJ CO OJ CO OJ -P o vo OJ OA -=t- LT\ OJ o 0- VO o OJ H OO oo OO H CO oo H All except type 3 O Fn o CO OJ OJ H H CO , OO H vo OJ OO CO H V£ 1— 1 oo ca OJ CO UA OJ LTN H OJ OA H CO vo OJ vo o H i VO OJ OJ VO OJ -P LTN vo CO LiA UA co H D— O CO UA LT\ vo CO vo OJ VO LTN OO LTN CO LTN OJ CO All except type 2 o Fq o OO o OJ oa OJ OO LTN OO H VO OJ H H CVI LTN 1— 1 OO LT\ OJ o vo H OO t- H OO H co H OJ UA OO o H OJ o OJ OJ OJ I CVI -P OJ OJ t- LPv OO LT\ LTN vo LTN oo 0- OJ H OO OJ OJ OO CO vo o H All except type 1 o F>h o OO o OJ O H OJ oo CO OO o- H VO OJ LTN OA H oo OO H H vo OJ o H oa CO H ON CA H o vo OJ OO vo H H H 00 OJ CO vo OJ ■P co OO t— 00 OA OA UA UA H vo H CO -3- OJ OA VO OO LT\ oo OA UA UA CO All inequalities included o o OO o OJ oa OJ OO LT\ OO o- H VO OJ H H OJ LT\ H OO ua OJ o vo H OO [— H oo H CO H OJ UA oo o H OJ o OJ OJ OJ CVI -P oo OO OJ CO LIA O O UA oo OJ OA LTN OO CO OA VO* o H IA- Functions numbered after OT co UA OA LTN H vo UA LTN 1 o VO J- VO UA CO vo vo o •H -P cd O «h S3 O •H -P O QJ a S3 O CJ Sh CD CD Sh .e! EH OJ < ^9 O •H •P O +3 •H < W »H GO 0) TJ CD -P CO b£> a! o ft & 2 3 O CO •H « !> 0) a> H *h rQ ft a) •H 0) ^ & a) -P !> S 01 O cd h fc - o ON oo Fq OJ H CO oo H ON c~- vo H H -p Pi o X CO oo OJ _3- -=f -=f CO LTN vo -d- o -d- OJ - vo o H ON oo H Pi (1) CM CJ X a> a) H co OJ -d- «* OO LT\ vo -d- o -=r OJ Pj oo -=f LfN vo OO OJ oo oo J- -=!■ if rj -P d c— -d- vo ON VO vo OJ $ vo ON P H CO o LfN ITN oo OJ vo oo OJ OJ OJ oo OJ H OJ OJ OJ OJ OJ O oo H H CO vo oo ON f- vo o H ON vo H ■P Pi H a $ oo VO J- ON vo vo OO ON vo OJ •H o vo o oo J3F On ON H LT\ OJ P OJ OJ OJ oo OJ H H H OJ OJ OJ C3 rr-j i— i w a! OO CO < o oo [*1 pq &h Pt) cu M «3 s 1 a) sa o 5j OO H ON 00 S § 3 PQ CO (1) ^ 3 OJ OJ OJ vo CO CO o o o o > G 5 cd cd 51 o •H P CO O Ch SH O •H P CJ 0) a. o o ^1 CD P •H I CO cu 0) P CO bo (L) > •H cp ^1 co •H CO !> O CO H 52 Functions numbered after [3] 011F 0255 0BD1 0FF1 6bff averages All inequalities included t 37 -Ok 37-98 20.10 22.13 39.38 31.32 I 658 757 385 1+51+ 926 636 FO 13 136 ik 12 31+ 1+2 All except type 1 t 56.32 53-23 22.09 25.09 1+2.68 39-88 I 1011+ 1077 1+1+7 520 1008 8ll+ FO 13 136 Ik 12 31+ 1+2 All except type 2 t 1+0-35 1+0.68 20.1+3 23.07 1+0.23 32.95 I 658 757 385 U5I+ 926 | 636 FO 13 136 ll+ 12 3^ 1+2 All except type 3 t 6k. kQ 57-15 22.1+6 25.00 53-!+3 1+1+.50 I lkl2 1181 !+53 528 1282 972 FO 15 318 18 12 38 81 All except type k t i+o.oi 1+0. 8l 20.81 2k. 96 kk.2k 31+.16 I 718 881 1+33 5l+0 109I+ 731+ FO 13 136 ll+ 12 31+ 1+2 All except type 5 t 37-05 36.02 17.85 20.93 36.1+7 29.66 I 658 757 385 k$k 926 636 FO 13 136 1* 12 31+ 1+2 Table A5. Four variable, six NOR gate design. (All-interconnection (formulation). 53 Function numbered after [3] 8228 All inequalities included t 117.17 I 2O7I FO kkQ All except type 1 t 119.^2 I 2091 FO I+56 All except type 2 t 119.49 I 2071 FO 1+1+8 All except type 3 t 159.38 I 2932 FO 68U All except type k t 133.16 I 2587 FO 1+48 All except type 5 t 120.70 I 2327 FO 1+88 Table A6. Four variable, seven NOR gate design. (All-interconnection formulation) . o on rH LfA LfA H LfA o\ c~- _=J- o7 oo CO p F-4 cv _=]- H rH vo oo OJ UA OJ -3- ft CD LT\ O C— rH oo H t- OA LfA H LfA LfA H H X H _=J- D— CON VO o\ H -=f PO H OA H H CD CD H H OO H H H H H H K rH -P < LfA 00 oo CO OO ON LTN CO o OO LfA CO LfA -P oo VO H t- CON VjO H H OO OJ H LfA CM • -Hf OJ VO o rH "* • LTn • • • • -=1" O VO oo o t- CjA LTn O VO VO CO co 00 -P ft CD _=t- fo H -=t rH OJ J- H o H H H 9 o l>- c— D- oo t- oa C— t- H LfA H i>- X O LfA On CON H oo VO O OO o rH LfA CD CD H H H H rH H H H H H H H -P < p CO O oo OJ oo OO VO H LfA oo o ^ CO LfA O VO o CO OO -3" -3- oo oo LfA LfA _=!- oo -=t- oo oo tt O 00 H oo t- rH CO 00 o CO oo OJ co -p P-H H VO H H OO VO OJ CO OJ OJ OO ft cd on o OO oo d— t- On t- o\ oo OA 1>- LfA oo X O oo OA oa H -=t 3 o o o H rH CD CD H rH H H H H H H H H H -P *u LfA H OJ o CO VO 00 CO CO LfA 8a OO p H VO CO LfA OO _^- OJ o H O oo J" oo oo OO LfA LT\ -=J- -=t- -=t- -=r oo -d- O LfA tr- H VO o CO o LfA -d- L^ o- CO p P>h rH vo H H OJ t— H t- H H c— ft CD OJ O X H H oo H OO C— oo t~- oo H LfA t— CD CD H OA CO CO D— OO LT\ oo OO OA CA OA ON H S H H H H rH -P - r- OA 00 H t- VO t- o vo c- OJ OO oo oo oo LTA -=J- _H- oo -^ oo 00 J- C T3 i — , O CD J- •H rH i i -P CD Sh c— VO OJ a\ oa OJ c— VO OA o H 00 CJ ,0 CD -P oo OJ J- .=*■ oo OO OJ oo OJ oo OO OJ fin S3 03 1 o •H -P CD rH 2 o CD o I CD g) •H W CD ■a CD +3 CO g CD > •H H ■§ •H u cd !> 0) CD U Xi En <: CD H ■§ Eh LfN o LfN o O tfA 00 CO ON H LfN H _4 piH OJ H t- H H -3- OJ -=r H J" -p OJ ft CU LTN V On on H t- H CO ON ON co t- 1 H X w H CO co CO 00 -3- vo H H O 1 t- - All e type H OJ H CO H VO H OJ H LTN C— OJ CO o OO CO H ON H s o P 1 t- ON ir\ OJ H o H VO -4 CO • • • • • • R • 1 • -4- OJ 00 _=r CO H VO -=r VO 1 ^ o CO a t- o t- H H H OO CO t^ -p ft CU -3- fa H 3 LTN co CO OJ CO H H CO O LTN r~ H t- ON L^ LTN t— H H t— M H ■H H CO o CO o J" CO ?l LfN CO ON CO 1XN OJ C*- CO VO L^ LfN CO J- CO CO vo CO co VO J- VO J" -3- -4 O f- H On OJ OJ £ ON J- L^ 9 OO fa H H H rH t~- LTN H -3- H CO ■P ft 0) OJ o ON LTN fr- t- H CO ON co LfN rH c— x H On ON -=r o CO LTN -=r vo ON o CO All e type H H H OJ H -4- OJ H LfN C"- OO LfN CO ON CO ON OO o CO -P co OJ CO -d- ON o rH r-| OJ rH LfN • • • • • • • H % • v CO CO vo CO CO t- LTN CO VO J" O o vo ^p H C- LTN ON LfN o s co -p ft fi* OJ iH H H C- LfN co CO CO OJ LfN o X D— ltn H H LTN H H H ON t- OO cu a; H CO ON CO CO H H t«- ■H CO J- VO H 6 H H H H OJ OJ H CO H H H H -P CO O o fr- o o LTN _J CO rH VO -P LfN J- vo 00 CO .sf ON 3 VO J- r^ «tf LfN LPs CO LTN LTN -J- c— -=T -4- LfN O fa VO H ^ H VO LfN o CO OJ OO OJ ^ r^ LfN CO cu •H T3 ■P d) H H LTN ON ON H co CO LfN t- 00 •H T3 H H ^ M o H K 9 ON H H CO H CO H H OJ H H SI H H < 3 O a; -h O U"\ H CO OJ O co o OJ CO vo * -P 00 ON OJ OJ CO CO LTN ON t- ON OJ • • • • • • • • • • 1 CO CO VO CO CO LO J- LfN CO CO -3- CO i — i co O 0) -3" cu •H fn t i p M -P CP U co o O t*- CO -4" J" LfN a H CO O ,Q 0) -P CO LfN J* -3- -=r co -=)" CO LfN d) fa a CD > 55 o •H -P CO O •H W f3 D +3 CO bO @ QJ > CU •H bO o CO •0 •H rH cu CO fn > ft cu g cu o rH rH & CH H tS cu • S r— C < •H -P cu fl H o r" O CO LH 56 Functions numbered afte rUl 58 59 61 55 60 averages All inequalities included t 63-17 66.60 63.23 ' 63.12 54.67 62.16 I I8U7 1783 1951 1823 1661 1813 FO 99 162 152 208 162 157 All except type 1 t 99.16 113.91 165.84 122.1+3 IO9.7O 122.20 I 3285 3671 6403 1+261 37^9 ! 4274 FO 199 265 351 1+1+6 304 293 All except type 2 t 76.80 75-48 77-^5 91.31 66.10 77.42 I 2269 1939 2101 2569 1911 2158 FO 105 168 265 2 1+1 172 191 All except type 3 t 71.44 8U. 95 95-95 70.86 71.62 1 78.96 I 2121 2425 3017 211+1 2281 2397 FO 126 339 230 267 339 261 All except type 4 t 74.80 72.34 69.53 69.36 64.34 70.07 I 2247 1937 2055 1885 1907 j 2007 FO 61 196 170 1+72 210 222 All except type 5 t 97.25 83. 42 64.55 43.15 76.83 73-04 I 2777 2267 1517 1205 2193 1992 FO 43 46 44 51 160 69 Table A8. Three variable , six NOR gate design. (Feed-forward formulation). 57 Functions numbered after [4] 48 43 47 40 28 All inequalities removed t 14.33 10.42 14.32 25.90 13-40 I 479 349 499 1015 44l FO 12 14 21 165 158 With type 1 only t 4.31 5.4l 6.93 17.99 4.85 I 123 155 249 735 137 FO 12 14 17 159 62 With type 2 only t 10.24 8.32 10.90 21.19 9.99 I 345 269 389 875 321 FO 12 14 21 114 134 With type 3 only t 14.02 10.65 14.37 21.89 13.20 I ^75 345 493 779 44l FO 8 10 19 87 158 With type 4 only t 13-92 11.57 14.15 29.03 12.75 I 473 . 34l 477 1151 4ll FO 8 10 19 217 150 With type 5 only t 16. 4l 10.95 7-11 11.00 15.31 I 669 403 265 327 555 FO 176 43 93 279 349 Table A9. Three variable five NOR gate design. (Feed -forward formulation). (Adding inequalities one-by-one). (continued) 58 Functions numbered after [4] 29 27 39 42 37 averages All inequalities removed t 10.06 10.31 ! 17.74 11.05 14.90 14.24 I 317 345 609 339 491 489 FO 125 95 11 24 45 67 With type 1 only ! t 5.18 ; 5.28 10.24 5.85 8.39 7.41+ I 151 i 169 1 151 161 255 249 FO 76 45 n 19 33 49 With type 2 only t 8.l4 8.19 14.30 9.01 12.50 11.28 I 261 273 497 275 4l3 397 FO 117 87 n 24 45 58 With type 3 only t 9-57 10.22 17.03 10.97 15.01 13.69 I 309 34l 569 333 483 457 FO 119 95 10 20 39 113 With type 4 only t 9.69 10.37 18.29 11.74 14.70 14.62 I 297 319 561 333 469 484 FO 115 96 n 20 37 69 With type 5 only t 11.67 17.14 8.99 8.61 8.91 11.61 I 399 555 291 249 269 399 FO 227 286 17 35 35 154 (continued fromm the previous page) Table A9. Three variable, five .NOR gate design. ( Feed-forward formulation J. (Adding inequalities one-by-one). 59 rH on £ en on t- LfN H LfN j- VO VO -p Pi a) ir\ OJ ON LTN on H r-l on H vc LfN vc o ro -* ON NO LfN J" H CVJ H O ON X J- on on LTN on -d- ON NO H t— VD cn H H H H H H CVJ H H CO on vc J" VO CO VD « VO d J- ON 0- C— -3- O H ON CU SI LfN VO NO vo NO LfN t— CO VO t- on -3" ?1 on ON LfN on on H LfN C— VC VO VO -p Pi (1) -3- fe CVJ LfN LfN H on H co t— O X ON co ON CVJ LfN NO H VO ON ^t on a) a) M Lf\ LfN on co cn NO ON CO CVJ 00 CO K m H H H H H H CJ H H •i ^ d C- on j- on ON VC NO on \ ~ J- V j J- co 1— 1 H J- LfN on -if H VC V. VL 3 * J- on rn H H H H ON H cvj H H CO § NO on H ON CO on H CO O co -J- 0" LPi H •P SI NO NO NO NO vo _* r- r- VO f— O on on I s - LfN ON LfN H VO CV) fa CVJ Cn LfN m H cn J- vc LfN VO •H tl H H •H Ti ^ 2* 71 H -^- ON vc IfN CVJ H O l~N J- CO H J- on on LfN cn ON VC' O vc Vl 0< C on H H H H H H CVJ H H C LTN CO on ON on CO CO , J- CO •H -p ON H LfN ON ON r- H _r ON fT\ on SI vc NO NO NO VC LfN O f«- -' [*- r- to (1) 60 > O 0) t— •H *h -P ~ CVJ -H- CO CVJ on CC cn 1 CVJ fa (3 d 1 •p a o •rH ■g :-! c •H •P O H B ■p UN OJ OJ OJ OJ OJ H CO OO OJ OJ IA IA -=r t- o -=1" 0- co CO UN CO s! H • un • • -=r- • OJ CO -=!" UN VD • -P H H H Pi a Si 3 cd CO H ?3 H H CM H ON LT\ H o VD OJ O oo O CO h- LTN o CO -=J- VD UN VD -p 0) o Pi P°H OJ ON UN CO H H H X H -=t ON VD UN OJ H O ON J- CO (1) - LTN ON UN H o- VD OJ pq OJ ON LT\ co H o CO -=f VD UN VD -p H H Pi «u o o H O VD H ON -=f CO X H -=f ON VD ITS OJ H o VD UN 0) 0) H -=|- CO CO LTN CO -=t- ON OJ H H B +3 oo H H H H H H 8 O ON ON -=1- VD co ON -=f H SI H J* OO UN H c- ON VD VD _p • • • • • • • • • • • CO H VD VD VD VD VD -4- VD t- VD t- ra G -d O 0) h- w •H 5-1 +3 217 All except types 2,1+ t 26.22 57.25 *+3-59 1+2.81+ 1+2.1+8 I 517 12 1+1 921 863 886 FO 26 520 193 1+1+ 196 All except types 2,5 t 26.02 56.17 1+1.05 1+3.03 1+1.56 I 517 1199 81+1 855 853 FO 26 521+ 197 l+l 197 All except types 2,7 t 26.97 60.02 Ul.73 ^3.76 1+3.12 I 5*+3 1279 863 903 897 FO 26 578 195 1+1 210 (continued from the previous page) Table Al6. Three variable, six NOR- AND gate design. (All-interconnection formulation. ) (continued) 8o Functions numbered after [l] 101 100 105 99 averages All except types 2,8 t 27.13 57-19 1+2,29 I+I+.7I+ 1+2.81+ I 523 1215 ! 837 905 87O F0 26 538 195 h3 201 All except types 3, it- t 3^.1^ 77.52 56.1+2 53-99 55.52 I 619 1599 1095 1027 IO85 FO 26 609 195 k6 219 All except types 3? 5 t 35.75 80.88 55.99 5I+.09 56.68 I 619 1523 1015 1013 101+3 FO 26 610 199 1+3 220 All except types 3,7 t 35.90 83.21 56. 51+ 56.0I+ 57.92 I 693 1699 1117 1099 1152 FO 28 71^ 215 1+3 250 All except vypes 3,8 t 3^.92 77. 0*+ 52.98 51+.31 51+.82 I 637 1559 1027 IO63 1072 FO 28 622 197 1+5 223 All except types l+,5 t 25.5^ 56. 81+ 1+6.81+ 1+3-97 1+3.30 I 517 1251 935 863 892 FO 26 52 U 197 1+1+ 198 (continued from the previous page) Table Al6. Three variable, six NOR-AND gate design. (All-interconnection formulation. ) (continued) 81 Functions numbered after [ l] 101 100 105 99 averages All except types k,7 t 26.65 60.25 1+5.02 1+3.89 1+3.95 I 587 1399 1021 993 1000 FO 26 602 209 1+6 221 All except types l+,8 t 26.24 56. 9k 1+2.61 1+3.08 1+2.22 I 523 2267 931 913 909 FO 26 538 195 1+6 202 All except types 5,7 t 26.1k 57-39 1+0.28 1+2.36 1+1. 5k I 5^3 1289 877 903 903 FO 26 582 199 i+l 212 All except types 5,8 t 26.62 55.07 39.71 1+2.1+1+ I+O.96 I 533 1231 853 911 882 FO 26 5M+ 199 45 201+ All except types 7,8 t 26.02 58.15 39-98 1+2.19 1+1.58 I 567 1329 885 953 93*+ FO 28 610 199 45 221 (continued from the previous page) Table Al6. Three variable. six NOR-AND gate design. (All-interconnection formulation. ) 82 APPENDIX B VARIATION OF SUBSCRIPTS IN ACTUAL IMPLEMENTATION OF THE TRIANGULAR INEQUALITIES In the all-interconnection program, TLLODIE-ALF, when used for NOR-AND and NOR-NAND design cases, the actual range of the subscripts is as follows: i = 1,2,..., R-l j = 1,2,..., R-l J£ = J-j d. y • • • j X\ while for the NOR and AND -OR designs they are i = 1, 2 , • • • , R j = 1^2, o . . , R k - 1,2,..., R The reasons for choosing different ranges for the NOR-AND and NOR-NAND designs is that only single output networks have been considered for these designs and the additional inequalities generated for the cases where G. or G. is the output gate were assumed to be not too effective in reducing the execution time. HBLIOGRAPHIC DATA HEET 1. Report No. UIUCDCS-R~72-5^? 3. Recipient's Accession No. Title and Subtitle A STUDY OF THE EFFECT OF ADDITIONAL INEQUALITIES IN INTEGER PROGRAMMING FOR LOGICAL DESIGN 5- Report Date October, 1972 Author(s) Jose Joaquin Mora-Tovar 8. Performing Organization Rept. No. Performing Organization Name and Address Department of Computer Science University of Illinois Urbana, Illinois 6l801 10. Project/Task/Work Unit No. 11. Contract/Grant No. NSF GJ-503A #1 2. Sponsoring Organization Name and Address National Science Foundation Washington, D.C. 13. Type of Report & Period Covered Master Thesis 14. i. Supplementary Notes i. Abstracts In logical design of optimal networks by integer programming, additional inequalities are added in order to speed-up the computations time. The effects of different types of these additional inequalities for several logical design cases is studied. . Key Words and Document Analysis. 17a. Descriptors Integer Programming, Implicit Enumeration Method, Additional Inequalities, All-interconnection formulation, Feed-forward formulation, NOR, NOR -AND, NOR-NAND and AND-OR designs. t>. Identifiers/Open-Ended Terms ):• COSATI Field/Group 1 Availability Statement Release unlimited H=» M NTIS-3B (10-70) 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 82 22. Price USCOMM-DC 40329-P7I