LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 ho.£|-8>0 >3 CO Digitized by the Internet Archive in 2013 http://archive.org/details/coaxialcablememo76leic UNIVERSITY OF ILLINOIS GRADUATE COLLEGE DIGITAL COMPUTER LABORATORY REPORT NO. 76 COAXIAL CABLE MEMORY by Gene H. Leichner January 10, 1957 This work was supported by the Atomic Energy Commission and the Office of Naval Research under AEC Contract AT(ll-l)-4l5 Introduction In the design of high speed computers it is sometimes necessary to have a very fast memory of small capacity. For example such a memory could replace many of the registers of the arithmetic unit provided that the access time is short enough. It is possible to make a memory with a very short access time using an ordinary coaxial cable as a delay line if fast enough switching elements are available for the regeneration logic. The new diffused base transistors currently being developed are particularly well suited for this application. Design Considerations Figure 1 is a logical diagram of this type of memory. The regener- ation is accomplished by using a flipflop, at the input to the cable, which is set on each clock cycle to agree with the state of the output end of the cable. ,l i" for CLOCK' I CLOCK "0" FOR CLOCK- 1 ^ 6ATFS TO" I "WHEN/ nput isv e) 3ATES To "CV'WWEsJ y IMPUT IS ^0" COAX CONTAINS 74PJQ/ TS Figure 1. Logical Diagram of Delay Line Memory The relative timing of the clock, cable input, and cable output signals are shown in Figure 2. The drawing represents the situation at a safe speed of operation, for which a clock period is just equal to twice the time required to change the state of the flipflop. With such a choice of clock period the -1- CLOCK SICaKJAL I INPUT TO CABLE- OUTPUT OFCAb Figure 2. Timing Diagram output end of the cable remains in a constant state throughout the length of the flipflop gate signal (1/2 clock cycle). However the length of the cable must he chosen properly relative to the clock period. The system shown in Figures 1 and 2 requires that the delay of the cable be equal to some (n - l/2) clock periods where n is the number of digits to be circulated. The other l/2 clock period is the time required to set the flipflop in the regeneration logic. By using direct-coupled regeneration logic a non-return- to- zero system of storage within the cable is possible, thus permitting a larger number of digits to be stored in the same interval of time than would be possible with a return- to-zero system. If it is assumed in either system that the output end of the cable should remain constant throughout the time it takes to gate the flipflop, then a non- return- to- zero system can store in two units of time what would take three units in a return- to- zero system. Test Circuit An eight-digit memory using 212 feet of RG-62/U cable was con- structed in which diffused base transistors were used in the regeneration logic. The delay of the cable is 1.3 mi-is per foot so the total delay is 276 mu.s -2- In order to store eight digits, this 276 mu.s must contain 7 - l/2 clock periods so one clock period is 36.8 mu.s or f = 27-2 mc . Since the cahle delay is only 1.3 mu.s per foot, the length of the cable is not very critical. An error of a foot or two probably would not be noticed in the circuit operation. Figure 3 is a circuit diagram of the original test circuit. The two transistors which make up the difference amplifier to provide push-pull clock signals would only be required once for a large-scale memory, but the rest of the circuitry shown would be required once for each line used. The write-in circuit which was used in this test circuit was made as simple as possible to minimize the number of transistors required. It therefore merely sets the flipflop at some random time and is used only to produce typical storage patterns. Since the system is non- return- to- zero, the cable will be at some constant potential for all eight digits equal to one and at another potential for all eight digits equal to zero. However since all the regener- ation logic is direct- coupled, and no amplifiers are used, there are none of the usual difficulties associated with the dc shift. A typical waveform at the input end of the cable, point A of Figure 3> I s shown in Figure h. The clock frequency is only 17 mc in this Figure k- . Oscilloscope Tracing figure rather than 27.2 mc, but it shows the typical waveform near the upper limit of speed of operation. The lower frequency of this waveform was necessary -3- Ill a M d— |h 'ihNrM*-r*r-»^ o UN ♦^-^1 \r o O Eh H t3 £ s 09 w ^H a> o Tl +3 o CO •H ■H Q ca a a) -4. because one of the original transistors drifted in its characteristics enough to be unusable and a replacement was not available because of the shortage of these transistors. When a transistor of lower alpha (below the design limit of the circuit elements) was substituted, the maximum speed of operation was less. The fact that the trailing edges of the pulses extend into the adjacent digit positions is an effect of this same change, but also occurred somewhat with the original transistor at the maximum speed of 27.2 mc . More careful design of future circuits will /correct this tendency. Use as a Fast Access Memory Figure 5 shows one read and write logic that could be used for a memory but which was not included in the first test circuit. The READ and TF0R.(cL0C^I "AMD WRITE) ®*A '~F|| V'FOV? j" I ' ®' ®-y 0" FOf?(C LOCK'" f "AND >MRlTE) Figure 5. Memory with Read and Write Logic -5- WRITE signals are selected clock pulses which coincide with the digit position required. The control of the computer must provide these signals as well as keep track of the digit currently "being regenerated. The memory is intended to be used in a parallel fashion. That is, each digit of a computer word would be stored in a separate cable and all cables would be regenerated in synchronism. Figure 6 is a diagram of such an arrange- ment and Figure 7 is its register equivalent. CONTROL VJE^TE REA£> *NE *©■ *EAD -06 1 C N WRITE LOGIC RE* I RE AD I XJVSKrf ^ L06IC ^LOSI '^M ■N DIGITS "© 103) C i *> 1NR.IT6 U?<5IC REG FN LOGIC Figure 6. Block Diagram of a Parallel Memory <3ATES TO tFl?OM E ACH R.EO* \S TC&. OPERATE*? BYGD«4TROl_ rani Figure 7- Register Equivalent of Parallel Memory -6-