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1o i?7 Report No. h2TJ 
 
 SYNTHESIS OF OPTIMAL NETWORKS 
 WITH NOR AND NAND GATES 
 BY INTEGER PROGRAMMING 
 
 January 1971 
 
 by 
 
 T. Ibaraki 
 T. K. Liu 
 
 D . D j achan 
 S. Muroga 
 
 NOV 9 1972 
 
 Y OF ILLINOIS 
 AT URBANA-CHAMPAIGN 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, ILLINOIS 
 
Report No. k-2'J 
 
 SYNTHESIS OF OPTIMAL NETWORKS 
 
 WITH NOR AND NAND GATES 
 
 BY INTEGER PROGRAMMING* 
 
 T. Ibaraki 
 
 T. K. Liu 
 D . D j achan 
 
 S. Muroga 
 
 January 18, 1971 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 This work was supported in part by the National Science Foundation under 
 Grant No. NSF GJ-503- 
 
57 W 
 
 SYNTHESIS OF OPTIMAL NETWORKS WITH NOR AND NAND GATES BY INTEGER PROGRAMMING 
 T. Ibaraki, T. K. Liu, D. Djachan and S. Muroga 
 
 Summary: All optimal networks of a mixture of NOR and NAND gates are designed 
 by integer programming approach for all functions of three or fewer variables. 
 
 1. Introduction 
 
 An algorithm for designing optimal networks with prespecified types of 
 gates was formulated in the earlier papers [l] [2] by using the integer pro- 
 gramming approach. An algorithm of an integer program by the implicit enu- 
 meration was given in [k]. All the optimal networks using NOR gates only, 
 and also those using NOR and AND gates were exhausted and listed in [3] for 
 every function of three or fewer variables [7]. 
 
 In this paper, all the optimal networks of a mixture of NOR and NAND 
 gates are tabulated for all functions of three or fewer variables. 
 
 By an optimal network we mean a feed- forward network which realizes a 
 given function with the minimum number of interconnections (among gates) and 
 connections (of external variables to gates), among those with the minimum 
 number of NOR and/ or NAND gates. This optimality criterion does not always 
 yield a unique optimal network. In case of multiple optimal solutions, 
 all the optimal networks are listed. 
 
 The integer programming formulation for up through six gate networks is 
 the same as that presented in [2] and [3]. However, two classes of functions 
 which require seven gates are solved by the all- interconnection formulation 
 and a tailored algorithm of the implicit enumeration approach to the network 
 design problems [3]. 
 
2. Formulation 
 
 We will present the inequalities used for representing the feed-forward 
 networks of a mixture of NOR and NAND gates. The formulation can be derived 
 from the general approach given in [2] by restricting the types of gates to 
 NOR and NAND. Notations are the same as those in the papers [2] and [3]. 
 
 Let us consider a feed- forward network with R gates. Let us introduce 
 selection variables , k = 1, 2, . . . , R, which assume the value or 1, where 
 0=1 indicates the k-th gate being a NOR gate and 0=0 indicates a NAND 
 gate. Variable v* represents the connection to the k-th gate from the ex- 
 
 ternal variable x „, £ = 1, 2, 3, where v, = 1 means the existence of the 
 
 ]$_ 
 
 connection and v„ = means the non-existence, cp stands for the intercon- 
 £ ik 
 
 nection from the i-th gate to the k-th gate, cp = 1 and means the exist- 
 
 ik 
 
 ence and non-existence, respectively, of the interconnection, x , x , . . . 
 
 x are the eight different combinations of the three external variables, 
 
 x , x , x . (The superscripts are numbered in an arbitrary order.) P is 
 12 3 -K 
 
 the output value of the k-th gate for x^ . Finally p.£ stands for 
 
 1 ik 
 
 The basic set of inequalities describing a feed-forward network is 
 
 as follows : 
 
 £=1 1=1 
 
 y 
 
 Z v*x ( , j) + Z P^ } > 1 - UPp } - 11(1-0.) 
 n ., £ £ . n ik — k k 
 
 £=1 i=l 
 
^ 3 ]r (•) k- 1 /.\ 3 v k-1 ,.s 
 
 Z v n xY } + Z P., > Z v* + Z cp - U P lJj - U 0, 
 i!=l i=l i/=l i=l 
 
 2 k JJ) 
 
 - Z v x . 
 i=l ^ * 
 
 k-1 / .\ 3 k k-1 / . \ 
 
 z p)^ > - z v, - z q> + i - u(i-r u; ) - u e 1 
 
 . -. lk - /, , i . _ lk ^ k ' k 
 
 i=l £=1 i=l 
 
 V 
 
 k = 1, 2, ... , R - 1 
 j = 1, 2, ..., 8 
 
 As easily seen, the first two inequalities are for a NOR gate and the last two 
 
 are for a NAND gate. 
 
 For the last gate, for j = 1, 2, ..., 8, 
 
 r 
 
 i 
 
 \ v R x (;i) 
 
 i=l ^ ^ 
 
 R-l , x 3 R R-l 
 
 = P iR >" * v i" = *iR + 1 - U0 R 
 
 i=l i!=l i=l 
 
 ? R (j) ^ ,(J) 
 
 i=i ^ * 
 
 Z P^ ; > - U(l-0 ), 
 i=l 
 
 V. 
 
 if f(x (j) ) = 1, 
 
 or 
 
 r 
 
 I R (j) *'} M) . I 
 
 R 
 
 R-l 
 
 * V J X J + . Z n P iR * A T J + . Z - ^R'^R 
 i;=l i=l i!=l i=l 
 
 < 
 
 Z v*x^ } + Z P^ } > 1 - U(l 
 £=1 i=l 
 
 R" 
 
 ^. 
 
 if f(x^) = 0. 
 
The non- linear relation P^jj/ = pj 3 ' cp i s expressed by the following 
 
 linear inequalities: 
 
 ,(i) 
 
 f?>>-i 
 
 - p: 0/ - cp + p 
 
 Pp } + cp. v - 2 pjj^ > 0, 
 
 r ik 
 
 ik - 
 
 k o 2, 3, ..., R 
 
 i = 1, 2, . .., k - 1 
 
 <D = -*-j ^j • • • j 0« 
 
 Besides these basic inequalities, the following additional inequalities 
 are incorporated to reduce the computation time. Most of them are the same 
 as those explained in [l] and [3]. 
 
 (l) Each gate has at least one input connection or interconnection, and 
 at least one output interconnection. 
 
 Thus, 
 
 3 k k-1 
 
 Z v + Z cd > 1 k = 1, 2, .... R 
 
 i=l l i=l 1K 
 
 R 
 
 Z 
 
 j=k+l 
 
 % * X ' 
 
 K. — J., C. y . . . « K ~ J. 
 
 (2) Assume three gates are connected as shown in Fig. 1. 
 
 Fig. 1 Triangular interconnections 
 
If the j-th gate does not have any output interconnection except cp , then 
 
 Jk 
 
 it can be proved that the subnetwork should be discarded. 
 
 R 
 
 p=j+i 
 
 ij jk lk - ^ op 
 
 i<j<k<R-l. 
 
 The above property is true even if the i-th gate is replaced by an external 
 variable. Thus 
 
 R 
 v] + v + cp < 2 + Z cp.. , 
 
 pfc 
 
 P=J+1 
 
 j < k < R 
 I = 1, 2, 3 . 
 
 Also, if one of the j-th and k-th gates is NOR and the other is NAND, the 
 subnetwork should be discarded regardless of the existence of output inter- 
 connections from the j-th gate to gates other than k. 
 
 '« + v + cp i^ 2 + (1 -V +e k 
 
 cp. . + cp + cp < 2 + 9 . +(1-0, ), 
 ij jk lk - j k 
 
 i<j<k<R-l, 
 
Replacing the i-th gate by an external variable, 
 
 v i +v '« + v^ 2 + (1 - e d ) + e k 
 
 v i + v i + v s * + ^ + d-\). 
 
 j < k < R 
 i = 1, 2, 3- 
 
 Finally, the above property still holds even if the j-th gate is replaced by 
 subnetwork without output interconnection except to the k-th gate. This prop- 
 erty is partially incorporated using the next set of inequalities. 
 
 k-1 k-i-1 R 
 
 Z cp < + U( Z Z cp s + (1-cp )), 
 
 d=l+l 1J p=l j=k+l U+PJJ lk 
 
 k = k, 5, ..-, R 
 
 1 = 1, cL f • « • , K — 3 • 
 
 k-1 . k-i-1 R 
 
 E V> <0+U( S Z » (1 }J + (l-v)), 
 
 j=i+l p=l j=k+l 
 
 k = If, 5, ..., R 
 
 i = 1, ^-, • • • , k - 3 
 i = 1, 2, 3. 
 
(3) If a gate has the output interconnection connected to the last gate, 
 the gate can have no other output interconnections. 
 
 ?., ♦u^»a ) . 
 
 J=i+1 
 
 i — J-j e- y ■ • • a R — 2« 
 
 (k) Interconnections to the last gate can be ordered as follows 
 
 CD < CD 
 
 ^1R - y 2R 
 
 CP (R-2)R * *(R-1)R 
 
 1 5 VDh- 
 
 (5) The condition stated in (*0 can be extended to a subnetwork in which only 
 the k-th gate has an output interconnection to those gates outside the subnetwork. 
 
 Fig. 2 Ordering of interconnections 
 
 This is illustrated in Fig. 2. Only subnetworks consisting of gates 1, 2, . . . , k 
 are taken into account. 
 
k-1 R 
 
 (p-i)k- Pk i=1 . =k+1 ±y 
 
 k = 3, ^, ..., R 
 
 p = 2, 3, ..., k-1. 
 
 (6) A gate which has exactly one input connection can be specified as a NOR 
 gate (9 k = 1). 
 
 k-1 3 k 
 e >1 - ( 2 cp + z v - 1), 
 
 k i=l lk i=l * 
 
 (7) Although the detail is omitted, some inequalities are added to preclude 
 some of the networks which can be obtained from others by relabeling the 
 gates in the network. They are similar to those explained in [3] for NOR 
 networks . 
 
 With those basic and additional inequalities, all the optimal NOR-NAND 
 networks of up through six gates were obtained by using the general purpose 
 implicit enumeration code ILLIP [h] [5]. Two classes of functions, however, 
 need seven gates and the computation time for these by the above approach 
 appears excessive. Therefore, the all- interconnect ion formulation was used 
 for these two seven gate functions. The detailed discussion on this approach 
 is not given in this paper, since the modification from the above feed-forward 
 network can be done straightforward along the line given in [3]. 
 
3. Computation 
 
 Based on the integer programming formulations discussed in Section 2, 
 all the optimal networks for functions of three variables are exhausted by- 
 using the IBM 360/751 computer. The size of each problem and computation 
 time are listed in Tables 1 and 2„ 
 
 All the functions of three variables are realized within seven gates. 
 All 80 representative functions can be realized by networks of NOR and NAND 
 gates which have totally 58 fewer gates than the total number of NOR gates 
 in the case of [6]. The total number of interconnections and connections 
 contained in all the networks is also reduced by ^h. 
 
 Total computation time is 69. 07 minutes including both feed- forward 
 and all- interconnection network formulations. Of course, if all the net- 
 works are solved by all- interconnection network formulation the computation 
 time could be reduced further. 
 

 
 
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12 
 
 h. List of all the optimal networks 
 
 In tables k and 5, all the optimal networks of NOR and NAND gates for 
 all functions of up through three variables are listed. 
 
 The procedure for obtaining the optimal network diagram for a given 
 function follows that of Hellerman's [6]. A function can be represented by a 
 truth table as shown below, by specifying the values of L, f , . . . , f Q 
 
 1 c. O 
 
 where f , . . . , fn show the values of the given f for input vectors in the 
 same rows. a. b and c denote the variables of f. 
 
 
 a 
 
 b 
 
 c 
 
 f l 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 f 3 
 
 
 
 1 
 
 
 
 % 
 
 
 
 1 
 
 1 
 
 f 5 
 
 1 
 
 
 
 
 
 f 6 
 
 1 
 
 
 
 1 
 
 f 7 
 
 1 
 
 1 
 
 
 
 f 8 
 
 1 
 
 1 
 
 1 
 
 Let us write eight binary digits f , ..., fn as follows, 
 
 fo f. 
 
 
 f f f 
 3 2 1 
 
 ' v 
 
 0. 
 
13 
 
 Grouping the f.'s as shown, we obtain three octal digits to 
 identify a function. 
 
 In Tables k and 5 only representatives of equivalence class obtained 
 by permutation of variables and dualization of the function are listed, 
 reducing 256 functions into hG representatives. The dualization is intro- 
 duced because NOR is the dual of NAND, and vice versa. The representative 
 of a given function f can be easily derived by using Table 3- The procedure 
 is illustrated by an example. 
 
 Suppose that the function f has the octal number 321. The entry for 
 this number in Table 3 is 5*056d. This means that f is equivalent to function 
 O56 by applying permutation 5, which is (ac) as also shown in Table 3» a nd 
 then taking the dual of the resultant function. Table k shows that function 
 O56 has the optimal network with network number 13. Then Table 5 gives us 
 the actual optimal networks of function O56. To obtain optimal networks 
 for the function 321, we apply the dualization operation (change NOR 
 to NAND, and NAND to NOR) and then the permutation 5, which is (ac), to 
 the network in Table 5. 
 
 Seven out of the k6 three-variable functions listed are degenerate 
 in the sense that they are independent of at least one variable. The 
 network diagram numbers for the degenerate functions have the suffix D. 
 They are grouped together at the beginning of Table h. 
 
 Note that if a given function is symmetric in some variables, 
 say a and b. among all the optimal networks obtainable by permuting these 
 symetric variables, a and b, only one network is listed in Table h and 
 Table 5. The rest of networks can be obtained by simply interchanging 
 the connection from the external variables according to the permutation 
 
Ik 
 
 of variables. Also in Table 5* if & gate has only one input, the gate is 
 specified as NOR gate. Obviously the network with such gate replaced by 
 NAND gate is also an optimal network. 
 
 If a function is self-dual, the network with NOR gates and NAND gates 
 interchanged also realizes the same function. In Table 5? only one of these 
 two networks is tabulated. For these self-dual functions the letter "S" is 
 attached after the octal number expression of functions in Tables k and 5- 
 
 Some classes of functions have a property such that the dual of a 
 function in the class belongs to the same class by permuting variables. For 
 these functions, two optimal networks can be paired in the sense that one can 
 be obtained from the other by applying the dualization f interchange of NOR 
 and NAND) and also an appropriate permutation of variables. In Table 5? 
 however, both optimal networks are listed for easy manipulation. Such 
 classes are 033, 055, 232 and 2^k. 
 
15 
 
 
 
 
 1 
 
 2 
 
 3 
 
 1+ 
 
 5 
 
 6 
 
 7 
 
 
 
 -1*000 
 
 1*001 
 
 1*002 
 
 -1*003 
 
 3*002 
 
 -3*003- 
 
 1*006 
 
 1*007 
 
 10 
 
 1*010 
 
 1*011 
 
 -1*012 
 
 1*013 
 
 -4*012 
 
 4*013 
 
 1*016 
 
 -1*017 
 
 20 
 
 2*002 
 
 -2*003 
 
 2*006 
 
 2*007 
 
 3*006 
 
 3*007 
 
 1*026 
 
 1*027 
 
 30 
 
 1*030 
 
 1*031 
 
 1*032 
 
 1*033 
 
 l+*032 
 
 4*033 
 
 1*036 
 
 l*007d 
 
 4o 
 
 2*010 
 
 2*011 
 
 -6*012 
 
 6*013 
 
 2*030 
 
 2*031 
 
 6*032 
 
 6*033 
 
 50 
 
 1*050 
 
 1*051 
 
 1*052 
 
 1*053 
 
 1*054 
 
 1*055 
 
 1*056 
 
 l*013d 
 
 6o 
 
 -2*012 
 
 2*013 
 
 2*016 
 
 -2*017 
 
 2*032 
 
 2*033 
 
 2*036 
 
 2*007d 
 
 70 
 
 6*05l+ 
 
 6*055 
 
 6*056 
 
 6*013d 
 
 -l*07l+ 
 
 3*031d 
 
 1*076 
 
 -l*003d 
 
 100 
 
 3*010 
 
 3*011 
 
 3*030 
 
 3*031 
 
 -3*012 
 
 3*013 
 
 3*032 
 
 3*033 
 
 110 
 
 3*050 
 
 3*051 
 
 l+*05l+ 
 
 l+*055 
 
 3*052 
 
 3*053 
 
 4*056 
 
 4*013d 
 
 120 
 
 -5*012 
 
 5*013 
 
 5*032 
 
 5*033 
 
 3*016 
 
 -3*017 
 
 3*036 
 
 3*007d 
 
 130 
 
 3*054 
 
 3*055 
 
 -3*071+ 
 
 2*031d 
 
 3*056 
 
 3*013d 
 
 3*076 
 
 -3*003d 
 
 140 
 
 2*050 
 
 2*051 
 
 2*05l+ 
 
 2*055 
 
 5*05l+ 
 
 5*055 
 
 -2*074 
 
 l*031d 
 
 150 
 
 1*150 
 
 1*151 
 
 1*152 
 
 l*051d 
 
 3*152 
 
 3*051d 
 
 1*156 
 
 l*011d 
 
 160 
 
 2*052 
 
 2*053 
 
 2*056 
 
 2*013d 
 
 5*056 
 
 5*013d 
 
 2*076 
 
 -2*003d 
 
 170 
 
 2*152 
 
 2*051d 
 
 2*156 
 
 2*011d 
 
 3*156 
 
 3*011d 
 
 1*176 
 
 l*001d 
 
 200 
 
 1*200 
 
 l*176d 
 
 1*202 
 
 l*076d 
 
 3*202 
 
 3*076d 
 
 1*206 
 
 l*036d 
 
 210 
 
 -1*210 
 
 l*156d 
 
 1*212 
 
 l*056d 
 
 1+*212 
 
 4*05 6d 
 
 1*216 
 
 l*0l6d 
 
 220 
 
 2*202 
 
 2*076d 
 
 2*206 
 
 2*036d 
 
 3*206 
 
 3*036d 
 
 1*226 
 
 l*026d 
 
 230 
 
 5*27^d 
 
 -2*074d 
 
 1*232 
 
 6*032d 
 
 l+*232 
 
 3*03 2d 
 
 l*206d 
 
 l*006d 
 
 240 
 
 -2*210 
 
 2*156d 
 
 6*212 
 
 6*056d 
 
 6*27l+d 
 
 3*074d 
 
 6*232 
 
 l*032d 
 
 250 
 
 1*250 
 
 l*152d 
 
 -1*252 
 
 1*0 5 2d 
 
 1*25U 
 
 4*054d 
 
 l*212d 
 
 - l*012d 
 
 260 
 
 2*212 
 
 2*056d 
 
 2*216 
 
 2*0l6d 
 
 2*232 
 
 5*032d 
 
 2*206d 
 
 2*006d 
 
 270 
 
 6*25^ 
 
 2*05l+d 
 
 6*212d 
 
 -6*012d 
 
 l*27l+ 
 
 3*030d 
 
 l*202d 
 
 l*002d 
 
 300 
 
 -3*210 
 
 3*156d 
 
 4*274d 
 
 -l*07l+d 
 
 3*212 
 
 3*056d 
 
 3*232 
 
 4*03 2d 
 
 310 
 
 3*250 
 
 3*152d 
 
 l+*25l+ 
 
 l*05l+d 
 
 -3*252 
 
 3*052d 
 
 4*212d 
 
 -4*012d 
 
 320 
 
 5*212 
 
 5*056d 
 
 5*232 
 
 2*032d 
 
 3*216 
 
 3*Ol6d 
 
 3*206d 
 
 3*006d 
 
 330 
 
 3*254 
 
 5*05l+d 
 
 3*27l+ 
 
 2*03 Od 
 
 3*212d 
 
 -3*012d 
 
 3*202d 
 
 3*002d 
 
 340 
 
 2*250 
 
 2*15 2d 
 
 2*25l+ 
 
 6*05l+d 
 
 5*25U 
 
 3*054d 
 
 2*274 
 
 l*030d 
 
 350 
 
 1*350 
 
 l*150d 
 
 l*250d 
 
 l*050d 
 
 3*250d 
 
 3*050d 
 
 -l*210d 
 
 l*010d 
 
 360 
 
 -2*252 
 
 2*052d 
 
 2*212d 
 
 -2*012d 
 
 5*212d 
 
 -5*012d 
 
 2*202d 
 
 2*002d 
 
 370 
 
 2*250d 
 
 2*050d 
 
 -2*210d 
 
 2*010d 
 
 -3*210d 
 
 3*010d 
 
 l*200d 
 
 -l*000d 
 
 Explanatory Example 
 
 Class of 321 is given by word at intersection of row 320 and column 1, 5*056d. 
 
 This says 321 is in class of O56 by permutation 5 and dualization. 
 
 Negative permutation means the function is degenerate. 
 
 d means dualization 
 
 Permutation 1 is the identity 
 
 Permutation 2 is f'abc) 
 
 Permutation 3 is (acb) 
 
 Permutation 4 is (be) 
 
 Permutation 5 is (ac) 
 
 Permutation 6 is (ab) 
 
 Table 3 Conversion of octal numbers by 
 equivalence of functions 
 
16 
 
 Table k Optimal network number 
 
 corresponding to an octal number 
 
17 
 
 Function 
 
 Functional expression 
 
 Network 
 
 No. of gates 
 
 No. of 
 interconnections 
 
 No. of 
 
 
 
 
 
 
 
 (octal) 
 
 
 number 
 
 NOR 
 
 NAND 
 
 and connections 
 
 levels 
 
 000 
 
 
 
 ID 
 
 
 
 
 
 
 
 
 
 003 
 
 a'b' 
 
 1+D 
 
 1 
 
 
 
 2 
 
 1 
 
 012 
 
 a'c 
 
 5D 
 
 2 
 
 
 
 3 
 
 2 
 
 017S 
 
 a' 
 
 3D 
 
 1 
 
 
 
 1 
 
 1 
 
 07*+ 
 
 a'b + ab' 
 
 7D 
 
 3 
 
 1 
 
 7 
 
 3 
 
 210 
 
 be 
 
 6D 
 
 l 
 
 1 
 
 3 
 
 2 
 
 252S 
 
 c 
 
 2D 
 
 
 
 
 
 1 
 
 
 
 001 
 
 a'b'c* 
 
 1 
 
 1 
 
 
 
 3 
 
 1 
 
 002 
 
 a'b'c 
 
 2 
 
 2 
 
 
 
 1+ 
 
 2 
 
 006 
 
 a'b'c + a'bc' 
 
 11+ 
 
 3 
 
 1 
 
 8 
 
 3 
 
 007 
 
 a'b' + a'c' 
 
 8 
 
 2 
 
 1 
 
 5 
 
 3 
 
 010 
 
 a'bc 
 
 5 
 
 l 
 
 1 
 
 1+ 
 
 2 
 
 Oil 
 
 a'b'c' + a'bc 
 
 22 
 
 1+ 
 
 
 
 9 
 
 3 
 
 013 
 
 a'b' + a'c 
 
 7 
 
 3 
 
 
 
 5 
 
 3 
 
 016 
 
 a'b + a' c 
 
 3 
 
 2 
 
 
 
 1+ 
 
 2 
 
 026 
 
 a'b'c + a'bc' + ab'c' 
 
 1+6 
 
 2 
 
 h 
 
 12 
 
 1+ 
 
 027S 
 
 a'b' + a'c' + b'c' 
 
 26 
 
 5 
 
 
 
 10 
 
 3 
 
 030 
 
 ab'c' + a'bc 
 
 32 
 
 2 
 
 3 
 
 10 
 
 3 
 
 
 
 1+1 
 
 3 
 
 2 
 
 10 
 
 1+ 
 
 ' 031 
 
 a'bc + b'c' 
 
 30 
 
 3 
 
 2 
 
 9 
 
 3 
 
 
 
 36 
 
 1+ 
 
 1 
 
 9 
 
 1+ 
 
 032 
 
 a'c + ab'c' 
 
 31 
 
 2 
 
 3 
 
 9 
 
 3 
 
 
 
 33 
 
 5 
 
 
 
 9 
 
 3 
 
 
 
 39 
 
 3 
 
 2 
 
 9 
 
 1+ 
 
 ■ *■■■! 
 
18 
 
 unction 
 
 Functional expression 
 
 Network 
 
 No. of gates 
 
 No. of 
 interconnections 
 
 No. of 
 
 
 
 
 (octal) 
 
 
 number 
 
 NOR 
 
 NAND 
 
 and connections 
 
 levels 
 
 033 
 
 a'c + b'c' 
 
 27 
 
 k 
 
 1 
 
 8 
 
 3 
 
 
 
 29 
 
 3 
 
 2 
 
 8 
 
 3 
 
 
 
 35 
 
 5 
 
 
 
 8 
 
 k 
 
 
 
 37 
 
 2 
 
 3 
 
 8 
 
 h 
 
 036 
 
 a'b + a'c + ab'c' 
 
 ko 
 
 3 
 
 2 
 
 9 
 
 k 
 
 050 
 
 a' be + ab'c 
 
 19 
 
 2 
 
 2 
 
 8 
 
 3 
 
 051 
 
 a'b'c' + a'bc + ab'c 
 
 k5 
 
 3 
 
 3 
 
 12 
 
 h 
 
 052 
 
 a'c + b' c 
 
 9 
 
 1 
 
 2 
 
 5 
 
 3 
 
 053S 
 
 a'c + b'c + a'b' 
 
 28 
 
 k 
 
 1 
 
 9 
 
 3 
 
 054 
 
 a'b + ab ' c 
 
 23 
 
 
 
 k 
 
 9 
 
 3 
 
 055 
 
 a'b + a'c' + ab'c 
 
 ^7 
 
 k 
 
 2 
 
 10 
 
 5 
 
 
 
 1+8 
 
 k 
 
 2 
 
 10 
 
 5 
 
 056 
 
 a'b + b'c 
 
 13 
 
 3 
 
 1 
 
 7 
 
 3 
 
 076 
 
 a'b + ab' + a'c 
 
 16 
 
 3 
 
 1 
 
 8 
 
 3 
 
 150 
 
 a'bc + ab' c + abc' 
 
 3^- 
 
 
 
 5 
 
 15 
 
 3 
 
 151S 
 
 a'bc + ab'c + abc' +a'b'c' 
 
 h9 
 
 7 
 
 
 
 16 
 
 5 
 
 152 
 
 a'c + b'c + abc' 
 
 2k • 
 
 
 
 k 
 
 10 
 
 3 
 
 156 
 
 a'b + a'c + b'c + be' 
 
 17 
 
 3 
 
 1 
 
 8 
 
 3 
 
 176 
 
 ab' + be' + a'c 
 
 18 
 
 3 
 
 1 
 
 9 
 
 3 
 
 200 
 
 abc 
 
 h 
 
 1 
 
 1 
 
 1+ 
 
 2 
 
 202 
 
 abc + a'b'c 
 
 21 
 
 1 
 
 3 
 
 9 
 
 3 
 
 206 
 
 abc + a'b'c + a'bc' 
 
 hk 
 
 k 
 
 2 
 
 12 
 
 h 
 
 212 
 
 a'c + be 
 
 11 
 
 h 
 
 
 
 6 
 
 3 
 
 
 
 25 
 
 2 
 
 2 
 
 6 
 
 k 
 
19 
 
 Function 
 
 Functional expression 
 
 Network 
 
 No. of gates 
 
 No. of 
 interconnections 
 
 No. of 
 
 
 
 
 
 
 
 (octal) 
 
 
 number 
 
 NOR 
 
 NAND 
 
 and connections 
 
 levels 
 
 216s 
 
 a'b + a'c + be 
 
 38 
 
 3 
 
 2 
 
 9 
 
 k 
 
 226S 
 
 abc v ab ' c ' ^ a'bc' ^a'b'c 
 
 50 
 
 6 
 
 1 
 
 15 
 
 5 
 
 232 
 
 a'c + be + ab'c' 
 
 >+2 
 
 5 
 
 
 
 11 
 
 k 
 
 
 
 ^3 
 
 1 
 
 k 
 
 11 
 
 k 
 
 250 
 
 ac + be 
 
 6 
 
 3 
 
 
 
 5 
 
 2 
 
 25U 
 
 a'b + ac 
 
 12 
 
 h 
 
 
 
 7 
 
 3 
 
 
 
 20 
 
 l 
 
 3 
 
 7 
 
 3 
 
 27U 
 
 ab' + ac + a'b 
 
 15 
 
 3 
 
 l 
 
 8 
 
 3 
 
 350S 
 
 ■ -.. , 
 
 ab + ac + be 
 
 10 
 
 h 
 
 
 
 9 
 
 2 
 
20 
 
 Table 5 List of all the optimal 
 
 networks of NOR and NMD gates 
 for functions of three or fewer variables 
 
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 REFERENCES 
 
 1. Muroga, S., and T. Ibaraki, "Logical design of an optimum network by 
 integer linear programming - Part 1, " Report no. 26^-, Department of 
 Computer Science, University of Illinois, July 1968. 
 
 2. Muroga, S. , and T. Ibaraki, "Logical design of an optimum network by 
 integer linear programming - Part 2," Report no. 289, Department of 
 Computer Science, University of Illinois, December 1968. 
 
 3. Baugh, C. R. , T. Ibaraki, T. K. Liu and S. Muroga, "Optimum network 
 design using NOR and NOR-AND gates by integer programming," Report 
 no. 293 > Department of Computer Science, University of Illinois, 
 January I969. 
 
 h. Ibaraki, T. , T. K. Liu, C. R. Baugh and S. Muroga, "Implicit enumer- 
 ation program for zero-one integer programming," Report no. 305, 
 Department of Computer Science, University of Illinois, January 1969- 
 
 5. Liu, T. K. , "A code for zero-one integer linear programming by implicit 
 enumeration," Report no. 302, Department of Computer Science, Univer- 
 sity of Illinois, December I968. 
 
 6. Hellerman, L. , "A catalog of three-variable or-invert logical circuits," 
 IEEE Transactions of Electronic Computers, June 1963* 
 
 7. Muroga, S. , "Logical design of optimal digital networks by integer 
 programming, " in book Advances in Information Systems Science, Vol. 3 
 edited by J. T. Tou, Plenum Press, 1970, pp. 283-3^8. 
 
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