LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 1^6r nOoiaO-170 cop. 4 The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN NOV tS m L161 — O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/novelfamilyofdig169coll ' |6 r coo-i+15-1028 10 169 '^ a DIGITAL COMPUTER LABORATORY UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT NO. 169 A NOVEL FAMILY OF DIGITAL CIRCUITS by Donnell Michael Collins, Jr. September 22, 196^^- (This work was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering, September, 19^^, and was supported in part by the Atomic Energy Commission under contract No. AT-(11-1)-1018.) COO-J+15-1028 DIGITAL COMPUTER LABORATORY UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT NO. 169 A NOVEL FAMILY OF DIGITAL CIRCUITS by Donnell Michael Collins, Jr. September 22, 196^ (This work was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering, September, 19^^, and was supported in part by the Atomic Energy Commission under contract No, AT-(ll-l)-10l8. ) ACKNOWLEDGEMENT The author wishes to express his gratutude to Dr. K. G. Smith for the original idea, encoioragement and guidance in pursuing this vork, and for vaJ-uahle counsel that he gave the author during this study. The author is also indebted to his fiancee, Miss Linda Liikas. for her help in proofreading and typing the final draft of this report. Thanks are extended to K. C. Law and the drafting department for their assistance in providing the final drawings and illustrations for this report. TABLE OF CONTENTS Page REVIEW OF PROPERTIES OF A DIGITAL LOGIC CIRCUIT. l.I 1.2 1.3 l.k 1.5 1.6 1.7 1.8 Introduction, ... .,o.. o.., o = <,........... o ,..,.. . Power Requirements . ..,.., o . ...o ..... , . . 1.2.1 The Number of Supply Voltages Required. 1.2.2 Total Power Consumption. ....... o 1.2.3 Choice of Voltage Supply Magnitude..,.. Potential Versatility. ,,,,,..,...,..,,....,.... 1.3.1 Performance of All Logical Operations,. 1.3«2 Performance of Special Functions....... Packaging. ...,, ..o, ... ........ ................ . Cost ...... o ,,.„.,. o .,.,....,.... o o . o ....,.,,.. < Circuit Speed 1.6.1 Fast Turn On-- Turn Off Unspecified.... 1.6.2 Fast Turn Off --Turn On Unspecified.... 1.6.3 Symmetrical Operation. ................ , Noise Susceptibility. .. ....................... . Conclusion. ......... ,....,......,,. .... ....... . 1 1 1 2 h 5 6 6 7 8 8 9 9 12 12 16 A NOVEL CIRCUIT CONFIGURATION, 17 2 .1 Introduction. ................ 2.2 Performance of the Circuit... 2.2.1 Circuit Descriptions. 2.2.2 Element Functions.... 2.2.2.1 Resistor R 2.2.2.2 2.2.2.3 2.2.2.i^ 2.2,2.5 2.2.2.6 2.2.2.7 Resistor R Resistor R' Resistor Resistor R Transistor Summary, . , T and T 2' 17 21 21 22 22 22 23 25 26 28 28 CIRCUIT DECOMPOSITION FOR THE PURPOSE OF ANALYSIS. 30 3.1 Introduction. ........ 3.2 Output Decomposition. 30 30 -IV- TABLE OF CONTENTS (CONTINUED) 3.2.1 Description of Test Circuit Configuration 30 3.2.2 Description of the Measurement Technique 3^ 3.2.3 Results. .. = ........ 3k 3.2.3.1 Magnitude of R^ 37 3.2.3.2 Ratio of IqnAoFF... 37 3.3 Alternate Procedure for Output Decomposition.,... 38 3.3.1 Setup of Modified Type R Plug-In. 38 3 . 3 • 2 Measurement Procedure ..<,,...........,... kO 3. 3-3 Calculation of I /l at Symmetry. ......... . kl 3.3*^ Resultso o o ... o . o ..... o . o o ... o ,. o ..«.....,...,». . k2. 3 . h Input Circuit Treatments k2 3.^.1 Introduction o . o » o. .......... o,. ,,.„....,,.,.,.. . k2 3. ^"2 Input Transistor Operation. ... .... ,,0, ... ..,.,. . k2 3.^.3 Emitter Parameters .... ..<,., ..»....,, k2 3.^.^ Test Performed to Find More Exact Estimate of Emitter Parameters ... ... .... .... ............ , ^3 3.4.5 Results of Test„. o . 000 .0 o. ,. o .... o ,......,...,. . kk 3.5 Threshold Voltage .... o.. ,.0 o.,.,. ...... ,.,....,.,...,.. . kQ 3.6 Total Circuit Power Consumption. ^9 3.6.1 Results of Previous Two Sections................ 50 DESIGN PROCEDURE- ...... ,.0 o.. o .» ... ..o ,,.,„......., ....,,.... . 51 k.l Introduction. .. ... o.. ....... ...o ....................... , 51 k.2 Power Supply Magnitude ,. ..o .... ........................ . 51 4.3 Circuit Configuratio n --Output Section. ........,, 51 k.3'1 Output Transistor Base Drive. ... ............... . 53 k.3'2 Input Section. , o ...,.,,.,.. o ,,,....,........... . 5^ k,k Design Procedure Applied to the Inverting and Restoring Circuits .... o..,,. o.,.. .,.,,....,......,. . 5^ k.k.l Introduction. .„„,,, .... ....... ................. . 5^ k.k.2 Specified Conditions ... .....o ,.,.,,,...,.....,. , 55 k.k.3 Output Resistor R.o .. 00. o ................. o ... . 55 U.U.4 Output Transistor Analysis (Resistor R. ) 55 4.4.5 Summary. . o .......... o . o ..,..,......„..,... o .... . 58 CIRCUIT EFFICACY AND DESIGN FLEXIBILITY. ...................... 61 5 . 1 Introduction .,.,...........,, o,.,. ... .............. .0,. . 61 5 . 2 Circuit Efficacy. ......... ............................. . 61 5.2.1 Transistor Sample Test . ........................ . 61 5.2.1.1 Results of Test. ., o .......... . .... 61 5.2.2 Power Supply Variation Test. .................... 63 5.2.2.1 Results of Test....................... 63 -V- TABLE OF CONTENTS (CONTINUED) Page 5 . 3 Conclusions , . , 6^1- 5.^ Design Flexibility «...,... ,... 6k 5.^.1 Introduction.. , 6k 5.^.2 Power Supply Voltage 6k 5.^.3 Threshold Voltage .,......,,..,..,......, 65 '^.k.k Circuit Speed ............. ........... , 65 5 . 5 Cone lus ion ............................................. . 67 6. SPECIAL CIRCUIT FUNCTIONS AVAILABLE WITH MINOR MODIFICATIONS.. 69 6.1 Introduction. ., ........ ....... ,.,..... ...... ..o ........ , 6'^ 6.2 Flip Flop... ......,, ....... .,...., ..... ,,0 ,....,.,,..,,, 69 6.3 One-Shot Pulse Former. .....,........,......,.,,...,,..,. 7I 7. CONCLUSIONS .,......,.....,,,......,.,.,....,.,,..,...,..,..,,, 73 7 . 1 Conclus ions .................. ,,.o ..,...,,..,.,,,.,,.... . 73 7.2 Future Investigation. ......... ...,,..... 73 BIBLIOGRAPHY. ............. .............. .,,... .,,...... ..,....,.., . 75 APPENDIX A. ,....,,.,..,....,,........,,.,.,...,..,....,,.......... . 76 /VX X'^XjXMU.LA. j39900«0000O0«O09«00»»0*»090eo0«90O0«O0O09O90e00000»»0»OO0S j~7 APPENDIX C ............. o .......... o .. o .......... o ................. , 80 -VI- A NOVEL FAMILY OF DIGITAL CIRCUITS Donnell Michael Collins, Jr., M.S.E.E, Department of Electrical Engineering University of Illinois, 196^+ A set of digital logic circuits Is Introduced for which design properties are established and simple measures of circuit effectiveness examined. The original concept of the circuits Introduced Is a simple one derived from a consideration of the costs of various currently popular NOR/NAND circuit designs, particularly of their solution to the level shift problem. The conjecture upon which the investigation was begun is that an additional input transistor might be useful in the provision of level shift capability. An explanation of the circuits' operation is given. Each element's function is then discussed and analyzed. An appropriate pro- cedure for design of the two circuits is developed with limitations on the speed and component magnitude discussed. Tests are performed to check the effectiveness of the two circuit configurations , An evaluation of the circuits' design flexibility is given and a few special functions available from the basic circuits are presented. 1, REVIEW OF PROPERTIES OF A DIGITAL LOGIC CIRCUIT lol Introduction A necessary preamble to the description of a new family of switching circuits is review of those properties which in concert interact to define a desirable circuit o The properties to be considered will be shown below. Unequal treatment of the different properties will normally indicate the relative importance of the property described,, 1) Power Requirements 2) Potential Versatility 3) Packaging h) Cost 5) Circuit Speed 6) Noise Susceptibility 1,2 Power Requirements The discussion of this topic will be further divided into the following areas : 1) The number of supply voltages required 2) Total power consumption 3) The choice of power supply magnitude 1.2,1 The Number of Supply Voltages Required Clearly, if no other sacrifices are made, the ideal digital building block should use, at most, a single power supply. With this pre- requisite, the number of power pins to each logic block is held to a -1- -2- practical minimum of two. Similarly, the power distribution system connecting logic building blocks is minimized, particularly if the machine frame serves as ground reference. Slightly less obvious is the fact that a single power supply should, conceptually at least, reduce the requirement of closely regulated power supplies. That this is true for linear circuits may be shown using an example: Consider the currents in two initially balanced bridges. In the first, both legs of the bridge are fed by a single unregulated power supply. In the second, one leg is fed by an unregulated supply and the other by a stable supply having one terminal in common with the unregulated supply. In the first case, variation in the output of the unregulated supply does not affect the bridge balance, while in the second, variation of the unregulated supply alone causes unbalance in the bridge. In particular, an ideal digital building block using a single power supply minimizes the number of power pins and reduces the require- ment for close supply regulation, 1.2.2 Total Power Consumption A prerequisite for an ideal digital building block is low power consumption. The power considered is usually, though not always, average consumption. Two classes of binary logic circuits must be considered: In the first, there is nearly equal power consumption for each circuit state while the second has a large power consumption in only one of its two states, The first class of circuits (arbitrarily) are those in which the impedance seen by the voltage supply remains within a factor of two for either circuit state. In this case it is meaningful to consider an average circuit impedance level at all stages of the design. Low total power consumption will imply relatively high impedances for a given supply voltage choice. When the power consumed in the two circuit states differs by a factor of two or more, then two additional properties of the circuit and its use must be considered: (l) the power consumed in each state, and (2) the duty cycle. If a measure of each is available, then the average power consumption may be calculated directly. Typically, however, a priori knowledge of the circuit's duty cycle is unavailable to the designer and a worst-case evaluation must be made. An extreme example of a circuit in this class is one which consumes no power in its "off" state. Assuming a duty cycle of 0.5^ the power con- sumed in the "on" state can be twice that of a circuit of the first class and still retain the same total power consumption. As the duty cycle decreases, the circuit's "on" state power consumption can be increased, bounded only by the limits of the pulse power capability of the voltage distribution system. However, the exploitation of duty cycle is not the panacea it may appear, since the duty cycle can be specified only in special cases. Most often careful consideration of the total power consumption over a range of duty cycles must be given to this type of circuit before it is used within a computing system, since large digit-pattern-dependent variations in the total system power consumption may easily result. Duty cycle is defined as the circuit's "on" time divided by the sum of its "on" and "off" times, i.e., duty cycle = ("on" time )/( "on" time + "off" time). -li- lt may also be desirable to vary the operating power over a wide range by a few simple adjustments in order to accommodate unusual output requirements often found at equipment interfaces. If this feature, along with normal low total power consumption, can be incorporated in the circuit, then design flexibility is increased, 1.2.3 Choice of Voltage Supply Magnitude The choice of a voltage supply is dictated by a consideration of the following effects of voltage supply magnitude : 1) Power consumption 2 ) Impedance levels 3) Voltage swings The fact that the choice of supply depends on effects (l) and (2) can be shown with the aid of an example. An integral part of a computing system is the cable system connecting the main processing unit with the associated input-output equipment. The impedance levels of these cables is usually small, being in the range of 10 ohms to I50 ohms, and unless large amounts of power are used, have characteristic small signal levels. The use of a small magnitude supply for this application would result in small power consumption and production of the necessary signals at the proper levels. A large supply used for the same application is normally wasted. In most other logic circuits in which impedance is not fixed for some reason, a trade can be made between (l) and (2) with the possible end result that low power consumption, implying high impedances, may result often in slower circuits. -5- The voltage swings, produced by circuits with saturated output transistors, are normally related directly to the magnitude of the supply„ With a large voltage supply the two circuit states ("on" and "off") will have a large voltage separation and can be distinctly defined; with a small supply, the state distinction is less well defined since the voltage difference between states is smaller » Generally, the larger the magnitude of the supply, the better defined the circuit states will be. The final choice of supply magnitude, unless artificially constrained, will be dependent upon the three effects listed. It will result in a supply that is small enough to use small impedance levels without excessive power consumption, yet large enough for the circuit states to be well defined, 1, 3 Potential Versatility An ideal digital building block should possess the following attributes : 1) Perform all logical operations, 2) With minor revamping, perform effectively a majority of common special functions. Some of the special functions that are usually required of digital computer logic are: 1) Inversion 2) Cable -driving 3) Binary- storage h) Pulse production 5) Delay 6) Level restoration -6- 1.3.1 Performance of All Logical Operations For a logic system to perform all the logical operations, the building block must be logically complete as are NAND and NOR circuits for example. In this event, by interconnecting the logic block all definable Boolean logical operations can be performed o These inter- connections normally increase the requirement on the number of inputs and on the number of similar circuits which the output can drive. In brief, the logic block must be designed for high fan-in and fan-out to accommodate the gamut of logical operations, 1.3o2 Performance of Special Functions For effective performance of the majority of the common special functions, minor revamping of the circuit is often necessary and may result in changes to the circuit's configuration. The revamping may take the form of component additions and/ or wiring changes. The elements that must be added to the ideal digital building block may well be incorporated in the basic module. In this case revamping of the circuit could be accomplished by strapping special terminals without a major change of the circuit and its package. An example of this procedure can be shown by a restoring circuit with the property that if a resistor is connected across two nodes of the circuit it can be made to act as a flip flop. In this way the function of binary storage can be achieved without interconnection of two circuits and would be a valuable asset to the family of circuits. -7- l,k Packaeins The discussion of this topic will be broken down into the following areas : 1) the number of pins and. power buses 2) the number of elements per circuit Clearly^ in an ideal digital system,, for ease of production, there should be uniformity in the printed circuit boards or logic modules » Since each package has a specified number of pins and a certain area onto which components may be placed, both (l) and (2) above are limited by the physical size and shape of the package o In most cases the important factor limiting the number of circuits per circuit board is the number of pins required,. A majority of digital circuits have diode inputs where, in comparable technologies, diode size is approximately the same as the pin size. Therefore, each input to a circuit does not require a disproportionate board areao In at least one common circuit packaging approach, outputs from the circuits are limited to one for each circuit, so they do not affect the total area requirements appreciablyo Since the placement of the components may be in three dimensions (pins being a two dimensional array), there normally is enough space for components, particularly if accessibility to the circuits is not required. Since pin area seems more important than circuit volume, an ideal package will have a maximum amount of surface that could be used for pin connections. This would appear to utilize the module to the fullest,, In certain special cases where power transistors and elements of comparable size are required, there would be a definite limitation on the •8- number of elements per package. Hence, in these rare cases, the number of elements per circuit would be a packaging problem and pin limitation of no interest. 1.5 Cost Clearly, the cost of digital modules is one of the factors that determines whether or not the system will be produced or be doomed to failure before it ever leaves the original design stage. Since the digital system is composed of a multitude of switching blocks, the logic power and cost of each block will be a determining factor in the total cost of the system. But an overemphasis on the isolated cost of modules is not conclusive. A single expensive component used correctly may increase the cost per circuit, but if the component also increases the effectiveness and ease of use of the module, the total cost of the system may not be prejudiced. Thus, the final decision as to the minimum cost of the system must be made only after a comparison is made between expense and effectiveness of each logic building block. 1.6 Circuit Speed A digital system designed to enter the computer market now or in the future must be made as fast as possible provided its other properties are not adversely affected. However, this does not mean that all circuits are required to be exceptionally or uniformly fast. In fact, most circuits can be classified as follows: 1) Fast turn on - turn off unspecified 2) Fast turn off - turn on unspecified 3) Symmetrical operation ■9- 1.6.1 Fast Turn On--Turn Off Unspecified The cases where fast turn on is necessary and turn off is not specified result from specifications where information that must be recorded is available for very short periods of time. If the circuit does not turn on fast enough, the information is never received. An example of the use of this type of circuit is in the read circuits of a computer's core memory. Fast and uniform turn on in the read driver logic will ensure that at least one cause of non- simultaneous readout is eliminated. Slow and possibly variable turn off of the fast on - slow off circuit is often of no importance in the application. Other applications are sketched in Fig. 1, The inverting circuit chain can act either as a pulse restorer for long pulses or as a pulse discriminator for short pulses as shown. The non-inverting circuit chain having fast turn on and slow turn off times results in a stretching of the pulse in proportion to the number of circuits connected in series for long pulses, or as a pulse discriminator for very short input pulses. This type of circuit might, therefore, be used when a long pulse is needed to switch some relatively slow device or where a guarantee is required that short pulses (the size of the long pulse in diagram, for example) never be lost in a logic chain. 1.6.2 Fast Turn Off--Iurn On Unspecified The second class of circuits also has applications in computer systems where simultaneity of turn off of separate logic chains is necessary. In Fig. 2, the effects of a chain of such slow turn on fast turn off circuits are shown. The inverting circuit can be seen to act as a pulse ■10- NON-INVERTING CIRCUIT TURN ON DELAY TON 'turn off delay toff > T ON INPUT 1 2 7. ' LONG PULSE INPUT Tl ' TON SHORT PULSE INPUT Tg < " ^1 f u_ r— TOFF — - Ts .J TON-^ OUTPUT •2 •3 »B - OUTPUT _ PULSE STRETCHER (tB>>»A' PULSE DISCRIMINATOR INVERTING CIRCUIT - INPUT INPUT •2 OUTPUT •3 OUTPUT TURN ON DELAY T ON TURN OFF DELAY T OFF > T ON — »• OUTPUT LONG PULSE INPUT Tl > TOFF -Tl ♦o oj I— TOFF -I p^ OUTPUT '■ ' TON — K Toff / 9 TON TOFF Ton L_/.J ik '■ — 1 J PULSE RESTORER /»a*«A\ SHORT PULSE INPUT Tg T OFF TURN OFF DELAY TOFF INPUT OUTPUT LONG PULSE INPUT Tl > TON SHORT PULSE INPUT Ts < T ON TOFF -TON- PULSE DISCRIMINATOR INVERTING CIRCUIT TURN ON DELAY T ON =■ T OFF TURN OFF DELAY TOFF INPUT LONG PULSE INPUT Tl > TOFF »j T OFF- OUTPUT /T ON •2 OUTPUT "3 OUTPUT V I TON^ — t*-- TOFF I I I TON PULSE RESTORER (;::;:) OUTPUT SHORT PULSE INPUT Tg < TOFF Jl PULSE DISCRIMINATOR FIGUBE 2, IDEALIZED RESPONSE TO LONG AND SHORT PULSES APPLIED TO AN INVllRTINC AND A NON- INVERTING CHAIN OF CIRCUITS HAVING SLOW TURN ON- -FAST TURN OFF ■12- restorer for long input pulses and as a pulse discriminator for very short input pulses. The non-inverting circuit acts as a pulse discriminator or a pulse shrinker depending upon the pulse length of the input waveform. The pulse shrinker is handy for degenerating spiky pulses generated by commutation of signals in combinational logic or by the existence of logic race conditions. These first two classes of circuits are also applicable for flip flop gating or the formation of flip flops themselves. In either case, if the input pulse to the flip flop is short in duration, circuits of the asymmetric type will allow best resolution of the pulse. if correctly applied. 1.6,3 Symmetrical Operation Where symmetrical operation is specified, it is usually for the convenience of general purpose designs. In this event, the mixed blessings of asymmetric operating circuits need notbe considered. The penalty is often lower overall speed for a given small segment of logic in comparison with a custom design using asymmetric circuits. 1.7 Noise Susceptibility In contemplating an ideal digital building block, something that can easily be overlooked, in general analysis, is the effect that the noise of the computing system has upon the circuit. Noise in a computing system arises from two sources: (l) Interaction of circuits of the same class, and (2) extraneous signals from other circuit types, including electro- mechanical parts of typewriters, printers, and input/output devices generally. ■13- It is typically easy to guard against the first source and difficult to avoid the second. An ideal building block must have a large natural noise immunity, or the cost of shielded cabinets and enclosures, large ground planes, etc., may easily outweigh other system costs. The coupling of noise into and within a digital system can result by all the usual electromagnetic means. A particular culprit is the power system including so-called ground or common reference. The properties of an ideal circuit as regards its reaction to the "noise" of power supply variation, fast or slow, is illustrated graphically below in Fig. 3» Simply, the logic state should be independent of supply voltage over as wide a range as possible. SUPPLY VOLTAGE ON OFF CIRCUIT STATE FIGURE 3. PROPERTIES OF AN IDEAL CIRCUIT IN REGARD TO THE "NOISE" OF POWER SUPPLY VARIATION A method for enabling circuits to be immune to noise is to make the circuit have no low impedance couplings with the power supply „ A usable -Ik- circuit of this type is a coaxial-cable power-driver that is driven in turn by switched constant current sources as shown in Fig. k. +v o ; o -E FIGURE k. COAXIAL CABLE POWER DRIVER Even though the current sources use voltage power supplies for their power^ the current present is not a function of the voltage or noise in the voltage source. Therefore, this circuit would be immune to the noise of the supply and would have the characteristics shown in Fig. 3. Although this type of circuit is applicable for driving cables, it could not adapt itself cheaply to performing the many functions necessary for a general logic block. A general technique used to reject noise from all sources is the use of circuits that possess a large clear switching theshold. Although this method does not completely immunize the circuits to all magnitudes of noise, the threshold can be adjusted so that noise is not likely propagated by the circuits. -15- In order to take advantage of the relative stability of one of the terminals of the supply, the threshold is usually placed as close as possible to that end of the supply. In the usual common ground approach, the ground, so-called "sacred" reference, is considered to be less susceptible to noise. Therefore, in this case, the threshold would be placed as shown in Fig. 5« /Nv^v'^W^V VV^ ' ^v/ ^v^ V^^ "on" state (GRD.) X, TYPICAL DRIVING CIRCUIT ^1. K f -V RECEIVING CIRCUIT THRESHOLD "off" state (~v) FIGURE 5. PLACING OF THRESHOLD To illustrate this case in a manner similar to that used to illustrate power supply immunity, a representative diagram may be drawn as in Fig. 6. -16- INPUT VOLTAGE -V CIRCUIT STATE OFF ON CIRCUIT THRESHOLD FIGURE 6. REPRESENTATIVE DIAGRAM OF NOISE IMM UNITY' FOR THRESHOLD CIRCUITS As shown in Fig, 6, small amounts of noise do not cause a change in the state definition. But when the amount of noise is eifcessive, it does change the state of the circuit and the noise will he propagated. 1.8 Conclusion With the properties of a desirable digital circuit presented in this chapter^ it is now possible to introduce the novel digital circuits of this report and analyze them with respect to these properties. 2„ A NOA/EL CIRCUIT CONFIGURATION 2ol Introduction In the preceding chapter^ the desirable features of an ideal digital building block were reviewed „ From this basis the properties of a novel circuit configuration will be developed and a set of design objectives for the circuit obtained. The basic circuit configuration to be analyzed, shown in Fig, 1, is a NOR/NAND restoring logic element,, and as such, is logically complete. To be considered also is the restoring AND/oR element, also shown in Figo 7^ which is available as a trivial modification of the basic circuit. Though logically less powerful, the latter resolves some of the inefficiencies of NOR/NAND design, particularly in decoders, and for this reason, will be con- sidered together and interacting with the basic design. The original concept of the circuit is a simple one derived from a consideration of the costs of various currently-popular NOR/NAND circuit designs, particularly of their solution to the level shift problem. The majority of the current NOR/nAND designs utilize the equivalent of a single transistor inverter with level shifting circuitry to accommodate the basic disparity of input and output levels inherent in a grounded emitter design. At the present time, the majority of solutions to the level shift problem are expensive for various reasons. The zener or forward ILLIAC II NOR circuits use three forward-conducting silicon diodes, ILLIAC III control circuits use zener diodes, SDS circuits use zener diodes, CDC l604 circuits use resistor, emitter-follower scheme. -17- ■18- ^•V o— W <►- o-n — *> INPUTS I Tl > |R4 ^Ri SR: ; R5 OUTPUT / T2 o ^ INPUTS CIRCUIT 1- INVERTING I Tl |R4 + V A SRi 1.0K SIOK >560n OUTPUT -O < 2N706A RESTORER INPUT FIGURE 8, CIRCUITS USED FOR THE EXPERIMENTAL DEMONSTRATION OF COMPONENT FUNCTIONS -21- resulting speed changes for changes in individual resistor values were 1 plotted on straight line graph paper ■ 2.2 Performance of the Circuit 2.2.1 Circuit Descriptions (See Fig. ?) Circuit number one is an inverting circuit operating as follows : A positive going signal coupled from an input diode (all others assumed to be open) to the emitter of transistor T allows T, to turn on, causing T to turn on and the output to go negative. The negative going part of the input signal will turn T off, turning T off and producing a positive output signal. The action of this circuit is, therefore, to invert the incoming signal, the input and output having the opposite polarity (see Fig. 9) . INPUT OUTPUT FIGURE 9 Circuit number two is non-inverting and operates as follows: a negative going input signal coupled by an input diode to the base of transistor T, , turns on T, , supplying current to the base of T , turning on T , and causing a negative output. The action of this circuit is. See Appendix A for definitions of speed measurements, -22- therefore, to restore the incoming signal, the input and output having the same polarity. (See Fig. 10.) INPUT OUTPUT FIGURE 10 2.2.2 Element Functions In the sequel, the detailed functions of each component will be discussed, first in a general manner and then specifically with experimental verification. 2.2.2.1 - 2.2.2.2 Resistors R and R INVERTING CIRCUIT Resistors R and R establish the bias on the base of T, , hence, control the input threshold of the circuit. Since R and R , in series, form the total impedance seen by the power supply with the circuit in the "off" state, they are an important effect on the total power consumed by the circuit. Their effect on the circuit's turn on and turn off times should be secondary since only the threshold is changed, leaving the base current virtually unaffected. RESTORING CIRCUIT The Thevenin equivalent of resistors R and R determines the emitter impedance of T and with the voltage supply -23- establishes the input threshold of the circuit. Since both of these factors effect the turn on and turn off times, a change in either R or R should be more important here than in the inverting circuit. Since resistors R, and R limit the emitter current, hence the collector current, they limit the turn on current of T for a fixed value of R, and will, therefore, place primary limitations on fan-out. TEST PERFORMANCE Since the effects of small variations of R and R are complementary, an experiment with variation of R only was performed on the circuits shown in Fig. 8. The results are shown in Fig. 11, where the effect of R on circuit turn on and turn off times is given. From the graph, we see that the magnitude of R has a greater effect on the speed of the restoring circuit than on the inverting circuit, as expected. 2,2,2,3 Resistor R INVERTING CIRCUIT Resistor R forms the emitter impedance of transistor T and the input impedance of the circuit as seen by its driver. Since it limits the emitter current of T , hence, the turn on of T , it should effect the speed of the circuit considerably. Though it controls the "positive-pulling" load on the driving stage, this should be a secondary effect on the speed of the circuit. Also involved in the magnitude of R are effects upon fan-in and fan-out. Its effect on fan-in results from the loading on the driving ■2k- 80 70 60 50 SPEED (N SEC) 40 30 20 10 p I RpcTHBTPor: rToriiTT I = I SIVERTl NG CIRCUIT Vti TOFF^ -^ ^ :=£^ .Cr^ ^= ToNr" 7^ r— ^ M ) ' ^ ^- ) , ;^ r^ TOFFj .^ T ONj Turn on and turn off times in saturation will be important design parameters. 2.2.2o7 Summary Table 1 summarizes the results obtained. The numbers in the table give the level of importance of each element in affecting the six circuit functions. The number one indicates prime importance. -29- TABLE 1. SUMMARY OF THE IMPORTANCE OF EACH ELEMENT ON SIX CIRCUIT FUNCTIONS INVERTING CIRCUIT ELEME'NT(S) T ON T OFF PWR. CONSUMPTION i THRESHOLD FAN- IN FAN- OUT R and R 3 3 1 1 ^3 1 1 2 3 1 \ 1 1 1 ^ 2 2 2 2 \ 1 1 \ 1 1 RESTORING CIRCUIT ELEMENT(S) T ON T OFF PWR. CONSUMPTION THRESHOLD FAN- IN FAN- OUT P and R 1 I 1 1 1 ^3 3 3 2 3 \ 1 1 1 R 2 2 2 2 \ 1 1 T P 1 I NOTE; 1 = PRIMARY 2 -^ SECONDARY 3 = TERTIARY 3. CIRCUIT DECOMPOSITION FOR THE PURPOSE OF ANALYSIS 3.1 Introduction It has been stated previously that the inverting and restoring circuits discussed are possibly trivial modifications of each other. Consistent component labeling in Fig„ 7 and the experiments conducted in chapter 2 were based on the premise that dual circuits formed by rearrangement of components were possible „ This duality of circuits will be considered an implicit requirement in the following design description, 3o2 Output Decomposition Since the output sections of both circuits are identical^ they will be treated first „ The purpose of the treatment is to analyze the detailed effects of currents in the base of T on the turn on and turn 2 off times of the section „ The effect of T and the rest of the components affecting the operation of T are simulated by a constant current derived from a test resistor and a pulse source o 3 o 2 . 1 Description o f Test Circuit Configuration The circuit that will be used to test the isolated output section is shown in Fig, 13 » (Two circuits are shown since the decom- position is valid for both NPN or PNP output transistors.) Mechanisms for this rearrangement associated with packaging are described in section 1,4. -30- -31- + V (4.3v) PULSERfrUT B J- SUPPLY T FILTER PULSER &V1 B -L SUPPLY T FILTER FIGURE 13. FIRST DECOMPOSITION TEST CIRCUITS -32- In section 2.2.2.5^ it was shown that the effect of resistor R on the turn on and turn off times was not appreciable in the range of 500 ohms to 1000 ohms. The value R^ for this configuration waS;, therefore, chosen in this range so that any asymmetry noted in the output will "be due mainly to changes in the base drive currents. Resistor R, of the decomposition is identical in application to that in the actual circuit configuration. To simulate the rest of the circuit T and R^ were used as a constant current pulse source. To drive the transistor T , an ac-coupled pulser is used in conjunction with a dc-restoring circuit. By definition, the voltage drop across R, is V-^_ (nominal) and the voltage o drop across FL. is '^ (V , ^ ~ ^-op )> where the particular supply used was 4.3 volts. The independent variables are, therefore, the voltages across R^ and R, , and the dependent variables are the currents in the corresponding branches. (See Fig. l4,) The two currents are: V T - ^^T2 and ^•3 - V = T2 as shown in the figure. When transistor T is on, the excess current that results from the difference in I, and I, ( r, > Ii ) at node N, turns on transisto 4 X X 4 ' T . This current will, therefore, be called 1^-^. See Appendix A for V versus I^ plots, 2 Assuming saturation of T , V / \ < 0,1 volt ■33- 4.3v. A 4.3-VBET2 VBE T2 Ixl >R N I ON ^R. I OFF \ TRANSISTOR UNDER TEST FIGURE Ik. DIAGRAM FOR THE DEFINITION OF CURRENTS FOR THE FIRST DECOMPOSITION ■3h- -^ON ~ h ' \ When transistor T_, turns off, the current I is cut off immediately and L continues to flow. Therefore, I, is the current that aids transistor T in turning off and will be called I„t-,t-,. o OFF ^OFF '^k 3«2.2 Description of the Measurement Technique As R^ is used to simulate the rest of the actual circuit configuration its value was held constant and R, was varied. This results in changes in both I and Ip,-rTp» Based on the conjecture (subsequently proven untrue) that 1 might equal 1^,-^-^ for equal turn on and turn off times, the parameter chosen for display of the data was the ratio I^^Vl^^^. Measurements of the ■^ ON' OFF circuit speed were made and plotted as a function of the ratio I^-yi^^^ for ^ ON' OFF three different magnitudes of resistor R^ and for four different types of transistors in Figs. 15 and l6. The speed measurements were made using oscillo- 2 3 scope probes placed at points A and B in Fig. 13 . 3.2.3 Results The results of this test circuit will be separated and discussed as a function of (l) the magnitude of R^, and (2) the ratio of I /l_ . Small spring clips facilitated rapid change of Ri without intraducing stray elements into the current. 2 Tektronix 585 with Type 82 plug-in using 7-pf probes. 3 Using the techniques outlined in Appendix A. ■35- SPEED (N SEC) 50 100 I on/ I OFF 2N1305 1 50 SPEED (N SEC) i.OO 1.50 I on/ioff 2N967 2.50 FIGURE 15. CIRCUIT SPEED AS A FUNCTION OF THE RATIO Iqn/IoFF ^^D SOURCE IMPEDANCE R^ FOR THE 2N1305 and 2N967 TRANSISTORS ■36- SPEED (N SEC) 1 50 I ON /I OFF 2N706A 3.00 70 SPEED (N SEC) 30 100 1.50 ION /I OFF 2N2369 2 00 3.00 FIGURE l6. CIRCUIT SPEED AS A FUNCTION OF TKE RATIO Iqw/IoFF ^^° SOURCE IMPEDANCE R^ FOR THE 2N2369 AND 2N706A TRANSISTORS -37- 3.2.3.1 Magnitude of R ^ The magnitude of PL. has a well defined effect upon the speed of the circuit. As the magnitude of R was increased, hoth the turn on and A. turn off times curves were shifted upward, resulting in slower circuit operation. Examining the graphs more closely, it may be seen that, as R„ is increased, the intersection of the "on" and "off" curves moves to the left, for most transistors tested. This means, as R,^ is increased, the ratio I /l decreases slightly for symmetrical operation in which the on and off times are roughly equal. 3,2.3.2 mio_of_l^^/l^^^ The curves for all the transistors have cutoff points for low values of I /I „ This cutoff results from R^ "being sufficiently large compared to R, that, simply by voltage divider action, the voltage across R, (base-emitter of T^) is too low to turn on T . h 2 2 For small values of 1.^-/1.^^, transistor T^ turns on slowly OF OFF' 2 and turns off rapidly. As the ratio is increased, the transistor's turn on time decreases and turn off time increases. The ratio I^^Vl^^^ at the iboint of intersection of the turn on ON OFF and turn off curves (symmetrical operation) was shown by the graphs to vary for each transistor type tested, and this test will have to be performed for each transistor type considered for operation in the output section of the circuit. Though symmetrical operation of the circuit is stressed as an initial simplification, once the value of I^^^/l^„^ is found where the ON' OFF output section operates symm.etrically, a simple change in R, , whic h -38- causes changes in I /I ^ will allow other modes of operation. Hence^ the design for symmetry is merely a starting point and any type of output speed ratio is readily available from this basis. 3.3 Alternate Procedure for Output Decomposition The procedure described in section 3 =2 is adequate for establishing the parameters of the output section_, but a considerable amount of time was necessary for the original circuit setup and for varying resistors to get the speed and impedance levels established for the symmetrical circuit desired, A method requiring additional equipment^ but in which measurements can be made quickly, yet accurately, will follow. The alternate procedure for treating the output section uses a modified Tektronix Type R Plug- in Unit with a Tektronix 5^5 oscilloscope o The plug-in has the capability of displaying simultaneously the turn on and turn off transitions of a test circuit placed on a circuit-board attached to the plug-in. This simultaneous display allows one to find the symjnetrical operation point with a simple setup. 3.3,1 Setup of Modified Type R Plug- In (See Fig. I7 ) The plug-in has a variable base bias supply, a variable collector bias supply, a variable pulse supply, and a variable base resistor (internal). The external circuit-board allows a choice for the values of resistors R , R_„, and R^ , R^ was set equal to 56O ohms, the same n Dhi Li L> DCL File No, Modification of Type R Plug- in Unit. This file describes a circuit Improvement which facilitates the measurement required above. •39- MODIFIED TYPE R PLUG IN UNIT CIRCUIT ARRANGEMENT ON TYPE R PLUG IN CIRCUIT BOARD COLLECTOR BIAS SUPPLY T PULSE SUPPLY T X ( 4.3 VOLTS MERCURY SWITCH 50 n Ot o->A-o- 50 n r d=: VOLTS N I OFF S TRANSISTOR UNDER TEST (T2) <>R BE FIGURE IT. FIRST DECOMPOSITION ALTERNATE TESTING SETUP .1;0- value used for R in the previous method, R was chosen to be 1 K and R^^ was arranged to be conveniently varied. For the purpose of analyzing the output section, it was arranged that the base bias supply was set to zero volts, the collector supply voltage was set at 4,3 volts, the variable base resistor was set at 50 ohms. The pulse supply was varied as necessary to get the required symmetrical operation. This method differs from the preceding one in that, instead of varying R.^ for different source current levels, the pulse voltage was varied and R was changed to establish base impedance levels. That these were approximately equivalent procedures may be seen by the results obtained. 3.3-2 Measurement Procedure A value of R was chosen and placed in the appropriate position x3ilj on the circuit-board. The pulse supply was then varied until the on and off times were equal. To measure the speed of the circuit, the zero-time reference button on the plug-in is pressed. The time from this starting point to the 90 per cent point of 'both on and off time transitions is the circuit speed at symmetry. With another scope, the peak to peak voltage (pulse voltage) at point N (Fig. I7) was measured. Small spring clips facilitated rapid change of R, without introducing stray elements into the current. .1+1. 3-3.3 Calculation of 1^^^/!^^^ at Symmetry Using the Modified Type R Plug-in, the definition of the off current must be changed from that used in Section 3'2. The voltage at point N is not cut off after the pulse is removed as it was in the previous scheme using transistor T . Here it is grounded through two 50-ohm resistors as shown in Fig, 17. The peak off-current is therefore defined as the base emitter voltage divided by the parallel combination of R with R in series with the two 50-ohm resistors. (Eq. 3.1-) -OFF (100 + R3)||RBg V BE ^^ (3.1) The on current is calculated as before » It is the peak-to-peak voltage at node N minus the V of T divided by the resistance R^ minus the off current, (Eq. 3o2o ) V - V N BE I = i£ _ I (3^2) ON R^ OFF ^^ ^ The ratio I /l is then found by dividing the two currents. (Eq, 3o3j (V,, - v^^ )(ioo + r^)|1r^„ I N BE ^^ b'I' be Y^ = - fr^ ^ 1.0 (3.3) ^OFF B^^BE^2 The resulting ratio I /l is found by virtually no circuit component (JIM Or r manipulation and only a few minor calculations. This means that_, for each transistor considered for operating in the required configuration_, a simple method for finding the I /l ratio at symmetry is available. UiN (Jr r ■42- 3o3»4 Results The results of this method were found to be the same as the previous ones and will not be restated. 3.4 Input Circuit Treatments 3 o 4 o 1 Introduction In a preceding part of this report (see section 3"2), it was shown that the speed and response time of the output section were dependent on the current in the base of T . The production of these currents by the input transistor T will be discussed next, 3o4o2 Input Transistor Operation It may be noted by consideration of the circuits in Fig, 7 that in no case of normal input signals will the input transistor T saturate. Though this is obviously true in the inverting circuit for a reasonable choice of R-, and E , it also applies to the restoring circuit. This follows from the fact that the combined drop in the input diode and the emitter base junction of T, will exceed the emitter base drop of T with normal devices., If T does not saturate, then its collector current will always be directly related to the emitter current by alpha (o;), the current gain of T „ 3 . 4 . 3 Emitter Parameters Since in the two circuits under consideration the emitter impedances and voltages differ, the inputs of the restorer and inverter must be analyzed separately. -43- The inverting circuit has an emitter impedance of R and an emitter voltage of approximately the supply voltage less the base bias (threshold voltage) and the small emitter base voltage of T . V ~ V - V - V E SUPPLY THRESHOLD BE The restoring circuit has an emitter impedance and voltage determined by the Thevenin equivalent of R, _, R^ and the voltage supply. Since the Thevenin voltage is the same as the threshold voltage, the emitter voltage is just Y^^^-^^^rrrsT-r^' The emitter impedance is equal to the Thevenin impedance and is, THRESHOLD ±- ^ jr- ^ 2 therefore, equal to R-, in parallel with R „ To summarize: INVERTING CIRCUIT RESTORING CIRCUIT "^E ^ ^SUPPLY ~ Threshold " ^be ^e '" ^threshold ^ = «3 ^ = ''lll''2 The emitter current is then the emitter voltage divided by the emitter impedance. X 3 = h and the collector current is al^. h- 3»4«4 Test Performed to Find More Exact Estimate of Emitter Parameters To verify these effects the following test was performed: the effect of the emitter circuit parameters upon the collector current was Base bias (threshold voltage) is measured from ground reference. 2 See also Eq. 3.5, page ^7. ■kk- measured with the aid of the test circuit shown in Fig„ l8o Voltage V is the Thevenin voltage and R^ is the Thevenin resistance of the test setup. Voltage V is varied by changing the position of the wiper arm of the 2K trimpot. This voltage is held constant for pulses by the two capacitors which form an ac short to ground o The duty cycle of the input pulse must be low so as to leave the bias unaffected by the pulsed load. The current in the collector was measured via R and the pulse o voltage across it. Resistor R was kept small enough so that the voltage o across it never exceeded V (max) and therefore simulates the actual circuit conditions o 3»4<,5 Results of Test The results of the measurements for a 2N967 transistor are shown in Fig„ 19 » As expected, the collector current is linearly dependent on the emitter voltage „ The slopes of the curves were calculated to be l/Rrp- Although !_, goes to zero theoretically, it is impossible to measure in practice o The graphs were extrapolated for low values of I and were found to intersect the zero axis at 0„75 volts » This zero offset may be seen, by reference to Fig. I8, to result from the voltage drop in the input diode (Oo35 volts) and the base emitter junction of the input transistor (Oo40 volts).. Therefore, for the restoring circuit, the emitter Aroltage is" "^E ^THRESHOLD " ^BE '^INPUT DIODE and for the inverting circuit: ^E ^SUPPLY ' Threshold ~ ^be The emitter impedances remain as stated before, -45- 4.3v VERY LOW DUTY CYCLE DRIVER 4.3v. ! 4 2K TRIMPOT lO/if. (ELECTROLYTIC) 1 FIGURE l8o INPUT SECTION TEST CIRCUIT -k6- COLLECTORS CURRENT (M AMPS) 5 1 2 3 THEVENIN VOLTAGE (VOLTS) Y FIGURE 19, INPUT CIRCUIT DECOMPOSITION- -EFFECT ON COLLECTOR CURRENT OF EMITTER SOURCE EQUIVALENT CIRCUIT .i,7- A more exact estimate of the emitter impedances and voltages and resulting collector currents are summarized in Eq. 3-5' INVERTING CIRCUIT RESTORING CIRCUIT V = V - V - V E SUPPLY THRESHOLD BE \ Threshold " ^be ' ^input diode Rj = R, «E = «ll '^-i \ '^-"i (3.5) If the value of I is known from the results of the output decomposition and if the threshold voltage can be specified hy some means. then R of the inverting circuit and R-, and R of the restoring circuit can "be specified. 1 INVERTING CIRCUIT; (V R-, = ^ = = a SUPPLY V ~ V ) THRESHOLD BE^ RESTORING CIRCUIT; R1IIR2 «E = a (V - V ^THRESHOLD BE V ) INPUT DIODE ^ "Appendix C shows a simplified method, of calculating R and R from the Thevenin voltage and resistance. -ii8- From above the values of the resistances can be specified, but before a workable circuit can be defined, some bounds on the values of these resist- ances must be found. The factors limiting the values of the resistances are the threshold voltage and the total circuit power consumption. These two factors will be discussed in the next two sections. 3 „ 5 Threshold Voltage In the preceding section it was shown that inherent in the specification for the collector current was the input threshold voltage. Therefore, a specification for the threshold must be established before the circuits can be determined. From Eq. 3° 5 "the upper and lower limits upon the threshold can be found. The upper limit is fixed from the inverting circuit specifications. A value of threshold equal to the supply voltage minus the V of the transistor Bill would cause V„ to be zero and, therefore, the circuit could not function. This is therefore the upper limit. The lower limit is found by considering the restoring circuit's V . A threshold voltage equal to V^.^ + V^^^,^ T^T^-oT^ would cause V„ to be zero. BE INPUT DIODE E Thus, this is the lower limit. Hence, the limits on the threshold ares V+V ) Since R of the restoring circuit has no effect on the collector current of transistor T , a lower limit imposed on it is not serious o Resistors R in both circuits contribute to power consumption when the circuits are in the "on" state. To keep the total power consumption reasonable, these resistors must then also have a lower limit „ 3.6.1 Results of Previous Two Sections The results of this section and the preceding one, as to the limits placed on the resistor magnitudes, can be summarized as follows s 1) The output driving requirements dictate upper limits on R and R . 2) The total power consumption dictates lower limits on R^, R^, R^. and R^ . 3) Inverter current requirements dictate an upper limit on R , k. DESIGN PROCEDURE U.l Introduction In this chapter a discussion of general circuit design procedure will be presented and then the design procedure for the circuit configuration of this report will he given, ^„2 Power Supply Magnitude For all circuit designs an immediate boundary condition placed on the designer is the power supply magnitude. The magnitude of the supply is usually predetermined by one or more of the following conditions : 1) A power supply already exists and the circuit must be built using it, 2) A power supply made by an outside vendor is very cheap and therefore desirable, 3) Signals of a certain amplitude are necessary to make the circuit compatible with already existing equipment and a certain magnitude of supply is necessary to meet this specification, ^,3 Circuit Configuratio n-- Output Section After the power supply magnitude is established, an appropriate circuit configuration must be chosen. For this particular discussion, the choice of configuration is obvious. Definition of parameters of the circuit may proceed in several ways, but a common procedure is to consider the output section first. In UNIVERSITY OF "51" ILLINOIS LIBRARY -52- the class of circuits considered here, the output is normally driven in one direction only and relaxes into the "off" state hy virtue of loading. An output resistor is necessary, usually only from the point of view that it allows voltmeter and oscilloscope measurements to be taken independent of output loading. However, it also effects other circuit characteristics. The rise time of the output signal is determined by this resistor and the load, together with the transistor junction and stray wiring capacitances. These capacitances have to be driven positive in the present case to allow the circuits being switched to turn on. Therefore, for faster switching times independent of load current supplied, this resistor should be made small. As ra.ore circuits are added to the output, the amount of stray wiring capacitance increases resulting in larger rise times. The output resistor must therefore be chosen in concert with knowledge of the dynamic load properties to enable the circuit to drive the stray capacitances at the speed the user requires for switching. An example of the sort of calculations that must be made to determine the magnitude of the output resistor follows; Say there is 60 picofarads of stray capacitance on the output and the switching speed desired is 20 nanoseconds. Since in 2 PC time constants the voltage is approximately 83 per cent of its final value, the output resistor is cal- culated to be 167 ohms (Eq, 4.1). See Appendix A for discussion of transistor junction capacitances in affecting transition times. -53- 2 RC = 20(10'^) R .= ^Q^^Q ] = 167 ohms (i+a) 2(60)(10"^^) If these calculations of the circuit switching speed require the magnitude of the load resistor to be small, the propagation time of the signals to the driven circuits will be a minimum but the power consumption will be large. If it ever happens that freedom is present in the choice of the power supply, a small supply would be the best one^ In this case, relatively small load resistors could be used resulting in small RC rise times, no excessive power consumption, and good drive capabilityo Once the supply is chosen, however, constraints are placed on the magnitude of the load resistor and on the number of input circuits that can be driven since each represents a static and dynamic load -driving requirement, 4o3'l Output Transistor Base Drive The next step in the normal design procedure is the analysis of the base drive of the output transistor and its relationship to turn on and turn off times of the output stage „ The factors that must be considered in this aspect are the beta (6) of the output transistor and the charge storage in the transistor during the switching process » For a fixed output load the amount of base drive necessary to saturate the output transistor is inversely proportional to the P of the transistor, hence, the larger the beta, the smaller the base drive necessary for saturation. Base current in excess of that required to saturate the transistor contributes directly to the stored charge. Since the charge must recombine -54- or be removed in order to turn off the transistor, excess turn on drive will, in general, contribute to delay in turn off „ U<,3»2 Input Section The manner in which the output transistor's base drive is produced, in this configuration, depends on the input section,, Since the current (base drive) from, the first transistor is specified, its speed cannot also be specified, so that any resulting speed inadequacies of the input section must be corrected by changing the base drive requirements slightly using all powerful hindsight induced by further experiment. One further consideration of the input section is necessaryo Since the input transistor biases the base of the output transistor, its dc leakage at high temperatures m.ust be consideredo If the leakage is large enough to bias the output transistor "on" at high temperatures, then changes in the base bias resistor of the output transistor must be made„ After complete consideration has been given to both the input and the output sections of the circuit the design of the circuit is complete o k o h Design Procedure Applied to the Inverting and Restoring Circuits 4o^ol Introduction Following the same procedure just outlines it is now possible to specify the design of the inverting and restoring circuits, with the I doubles for every 10 C rise in temperature, -55- additional design constraint of equality of the corresponding elements in the two circuits. k.k.2 Specified Conditions The conditions specified for the sample design are a voltage supply magnitude of 4.3 volts and a threshold voltage of 2.15 volts. k.k,3 Output Resistor R Starting with the output section the resistor R^ will "be chosen first. Suppose that the required output rise time must be less than 35 nanoseconds and the circuits that the output must drive have a maximum of 30 picofarads of stray capacitances. The value of R can then be roughly calculated in the same manner as before^ i.e._, using Eq. k.l. 2 RC = 35(10"^) 2(30)(10"-^2) Using the nearest standard resistor value below 585 results in an R of 560 ohms and a speed of 33 -5 nanoseconds. h.k.k Output Transistor Analysis (Resistor R. ) The transistor chosen for the output section is the 2N706A since it is a relatively high-speed device. Since the output section was analyzed in section 3-2 for the 2N706A's "on" and "off" currents^ the next decision that must be made is for resistor R, which regulates the "on" and "off" ■56- currents and the speed of the output sectiono As shown in section 3„2.3o2, by first designing the output section for symmetrical operation^ the value of R, can be determined. For any other type of operation R, may be changed » It was also shown that the smaller the magnitude of R, , the faster the response of the output section and the larger the magnitude of the currents in the base of T (2N706a) o By looking at Fig. l6, a first choice for R, at 100 ohms, for fast operation, is made. The V of the 2N706A is approximately iiiii 0,80 voltSo The "off" current is found from Eq, 3»1 to be 8,0 mamps initiallyo .80 o n = 0,0 mamps OFF 100 ohms The "on" current is related to the "off" current by the ratio l^^Jl^^^ at ON' OFF symmetry. From Fig, l6_, the value of I /l at symmetry for the 2N706A is Ui\l Ur r approximately 0,6l, I is then calculated to be 4,9 mamps, I = (0,6l)(8,0) = 4,9 mamps Adding I^^^ and I^„^, the collector current of transistor T-, is specified. ON OFF 1 ^C = ^ON ■" ^OFF " ^^"5 "^^"^^^ The transistor chosen for the input section T-, is the 2N967 for reasons of speed and availability. At this point the design of the two circuits must be separated since the specifications for the generation of the collector current differs for each. For any other transistor the test for the "on" and "off" currents for symmetrical operation can be made using the methods in either section 3.2 or 3o3. 2 See Appendix B for V versus I curves. ■57- From Eq. 3.5 the V for the two circuits can be calculated with E the V ^ of the 2N967 equal to O.UO volts and the diode drop of the 1N995 BE equal to O.35 volts. INVERTING CIRCUIT RESTORING CIRCUIT v„ = k.3 - 2.15 - 0,^0 E Vg = 2.15 - o.iio - .35 V^ = 1.75 volts V„ = 1.40 volts E Now using the relationship for I and V (Eq. 3-5)^ Rp can be found. av^ «E = ON. \ = E _ (.99)(1.7^) 12.90 \ ^-^2^^ - 108 0^3 Ee=135 ohms R I j R = 108 ohms R = 135 ohms R = 216 ohms R = 216 ohms From section U.5 the specification for power consumption states that a lower limit is placed on R and R and R . With R-, and R equal to 216 ohms, the power consumed in both circuits when they are in the "off" state is ^33 milliwatts. (V y ^ SUPPLY^ R1 + R2 (4.3r 432 ^33 milliwatts -58- With R of both circuits equal to 135 ohms the power consumed in this resistor when the inverting circuit is "off" or in restoring circuit when it is "on" is 116 milliwatts. )2 = C^-B - ■35r , 116 „iiii„atts 135 This total power level is quite large and would be of interest only for a high-speed circuit. A second design with R, = 68O ohms results in: R^ = I.5K Rg = 1»5K R = 1.0 K In this case the power consumption for the same situations are 6. 15 and 15 milliwatts. ^°qI =6.15 milliwatts (3.95)^ ^^^^^ =15.0 milliwatts which are quite small for a digital circuit of this type. 4.U.5 Summary To summarize the design procedure the following steps are to be followed after the supply voltage and the threshold voltage have been determined. 1) Calculate R^ from output drive requirements. 5 2) Perform test on output transistor described in 3 '2 or 3«3 of text, finding I /l ratio for symmetrical operation. OJN Or r .59- 3) Choose an R, that will give specified output speed and symmetrical operation. h) Calculate !„„„. OFF 5) Calculate 1^.^ from l^.Jl^^^ specifications. ON ON OFF 6) Calculate the collector current necessary from the input transistor, (l^ = I^^ + 1^^^). 7) Calculate V for "both circuits using equation 3'5' ill 8) Calculate R^ of "both circuits. 9) Rp, is R of inverting circuit, and R.^ is R | | Rp for the . restoring circuit. 10 ) Calculate R and R using Appendix C. 11 ) Make R of restoring circuit = R of inverting circuit and R and R of inverting circuit equal to R and R of the restoring circuit. 12) Make preliminary calculations for power consumption for R , R , and R . 13) If power consumed is too large, return to step 3 and choose another R, . After the power consumption requirement has been met, the circuits should "be tested. Since no consideration was given to the on and off times of transistor T in this technique, any pecularities in its on and off times will have to be compensated for without unduly upsetting previous decisions. The easiest and best way is again to readjust R, slightly to compensate for the on and off time pecularities. If a -60- complete circuit cannot be designed with the required low power comsumption, a different type transistor for T must "be considered. The basic symmetrical design is easily modified to produce improved turn Off , for example, by decreasing the magnitude of R, . The effect on load driving capability must, of course, be considered. 5. CIRCUIT EFFICACY AND DESIGN FLEXIBILITY 5.1 Introduction Chapter k presented a procedure for the design of the inverting and restoring circuits. In this chapter the effectiveness of the circuit and the flexibility of the design will be considered. 5.2 Circuit Efficacy To show the effectiveness of the circuit design, two routine tests were performed. 5.2.1 Transistor Sample Test The first test was performed to establish the effects of transistor parameter variation on the speed of the circuit. The circuits used were the ones derived in section k.l with the value of 68O for resistor Rj^ and designed for symmetrical operation. Then five each of two brands of the 2N967 and 2N706a types of transistors were tested in positions of T and T„ of the two circuit configurations. Since the circuits were designed for symmetrical operation a meaningful measurement of the design effectiveness is the difference of the output times (turn on and turn off) divided by the total transition time expressed as percentages. 5.2.1.1 Results of Test The results were tabulated and presented with. the aid of the bar graphs shown in Fig. 20. The graphs show that the inverting circuit is -61- NUMBER OF TESTED COMBINATIONS 40 30 20 10 39 32 V7 -62- 18 4.5v. looon INPUT oh4 ABSOLUTE CENTER VALUE FOR TIME IS 82 N SEC. At 'DIFFERENCE OF TURN ON S TURN OFF TIMES t= TOTAL TRANSITION TIME 0-3 4-7 8-11 -P2q p3^ 12-15 16-19 20-23 24-27 .41 t (%) INVERTING 4.3v, NUMBER OF TESTED COMBINATIONS 40n 30 20- 10 22 f; 16 22 V7 1000 A 15 INPUTO ABSOLUTE CENTER VALUE FOR TIME IS 46 N SEC. At 'DIFFERENCE OF TURN ON a TURN OFF TIMES f TOTAL TRANSITION TIME 4 VA 0-3 4-7 8-9 12-15 16-19 20-23 24-27 -^ (%) RESTORING FIGURE 20, RESULTS OF SYMMETRICAL TIME MEASUREMENTS FOR TEN DIFFERENT 2N967 AND 2N706A TRANSISTORS IN THE INVERTING AND RESTORING CIRCUITS -63- least affected, with approximately 90 per cent of the tested combinations having less than 10 per cent deviation from symmetrical operation. Though the restoring circuit had only approximately 55 per cent of the tested com- binations within 10 per cent of symmetrical operation, this result is still very good. The inverting circuit (as stated in chapter 2) is the circuit that is of primary interest. It is faster, performs NAND/NOR functions, is there- for logically complete, and would thus be used, for a majority of the logical operations. The restoring circuit, useful occasionally for economy, need not be otherwise perfect. 5.2.2 Power Supply Variation Test The second test was performed to measure the effects of power supply magnitude on circuit operation. Using the same component values as in the preceding test, five of the inverting circuits were interconnected in a ring type formation. Since there is an odd number of inverting circuits, the ring will oscillate with one cycle of the oscillation representing ten average circuit transition times. The single supply voltage to the ring was varied over a 12 -volt range and the cycle time and peak-to-peak voltage were measured, 5o2.2,l Results of Test The results were as follows. The circuits functioned in the range of supply voltages from 3.2 to I5.O volts. The peak-to-peak voltage magnitude at the output of each circuit remained approximately at the supply's voltage magnitude throughout the entire range. The cycle time -6i+= varied from 200 nanoseconds at the lowest value (3 "2 volts) to 300 nanoseconds at the highest value ( 15 oO volts )» This result shows that the circuit will operate effectively over a large range of power supply magnitudes with no deterioration of the output pulse magnitude o It also shows that the turn on and turn off times of the circuits are only slightly affected by the magnitude of the supply voltage even though the circuit was designed for a particular supplyo 5 "3 Conclusion From these two tests it can be seen that the circuits are quite effective as regards consistency of their output speed with respect to transistor variation and power supply tolerance o 5.^ Design Flexibility 5o4=l Introduction For a digital circuit to be generally useful, it should possess flexibility in its design required for adaption to a variety of needs The configurations described in this report have such design flexibility in the choice of switching threshold, power supply voltage, and the circuit speeds 5»^o2 Power Supply Voltage Section 502 showed that the circuit operated well over a wide range of supply voltages with a miniinum of speed change.. Though that test Average operation times ranged, therefore, from 20 to 30 nanoseconds. -65- was performed using the same component values for all voltage settings, a complete redesign for each value of voltage would produce a more effective ., 1 circuit. 5-^-3 Threshold Voltage Although throughout the last chapter the switching threshold used was equal to one-half the voltage supply magnitude , it can be varied between the limits stated in Eq. 3-6. Within this range the threshold can be placed close to the stable (ground, reference) end of the supply for better noise immunity and to comply with the requirements for an ideal digital circuit as stated in section l.T- 3.h,k Circuit Speed The speed of the circuit also appears quite amenable to designed control. As shown previously, once the circuit is designed for symmetrical operation, the speed of the output section can be changed by varying the magnitude of R, , with all other components fixed. From Fig. 21, it can be seen that for a 2N706a transistor, using results of section 3 "2, the T /t ratio extends over quite a large range for all values of R^ and is limited only by the fact that when I^-^-n, = ^ar^imm^ "the circuit fails to function. The speed of the circuit for symmetrical operation can also be varied by using the design procedure of section k-.k and completely re- specifying the circuits' component values. Three examples of using such a The re-design for a new value of supply voltage would follow the procedure outlined in section k.k. ■GG- 2.5 J.5 ton/toff 0.5 Rx 1 O l.OK 1 O ^r\r\ c\ / Q 25C / / r A 3 i / / J c ^ .1 .2 .3 .4 .5 .6 I on/i source 2N706A ,8 1,0 FIGURE 21. THE RESULTS OF CHANGING R^^^ ( ^OFf/^ SOURCE ^ ^^ ^^ '^On/^OFF RATIO FOR A 2N706A TRANSISTOR USING THE RESULTS OF SECTION 3.2 -67- procedure are shown in Fig. 22. Fig. (a) is the design of a fast symmetrical circuit, (b) the design for a medi\im speed symmetrical circuit, and (c) the design for a slow speed symmetrical circuit. From these examples, it can be seen that almost any reasonable speed requirement can be met with this circuit design assuming there are no limitations on power consumption and current levels . 5.5 Conclusion Considering all the aspects of the circuits' design flexibility, the only limitations appear to be the total power consumption and the slight limitations of the threshold voltage. The choice of power supply voltage and the operating circuit speed appear to be quite free. -68- I O o w H IS CO EH H O « H O o &^ W en EH < CVJ CM H 6. SPECIAL CIRCUIT FUNCTIONS AVAILABLE WITH MINOR MODIFICATIONS 6.1 Introduction Although the NOR/nAND element is logically complete, since all combinational logic and memory functions are available as interconnections of such elements, certain common functions may be expensive if achieved by this straightforward means. Accordingly, the companion OR/aND element was introduced as a convenient modification offering some economies in encoder design. With additional components this latter element offers further design economy by providing common special functions. This possibility will be illustrated for the formation of two special elements, a flip flop and a one-shot or pulse forming circuit. 6.2 Flip Flop To form a flip flop or memory element, the additions shown by dashed lines in Fig. 23 will suffice. Resistor R is used to close the positive feedback loop. When the set pulse goes toward ground, the two transistors turn on, lowering the voltage at the output (collector of T ) to ground. If the ratio of R to R is small, then the input transistor will be held "on" even when the set signal is removed. Diode D added to the extension input allows resetting by a Ki positive pulse. Its reset threshold is determined by the voltage divider formed by R and R . -69- •To- ll) FLIP FLOP R. Rl D. R2 1) Closes positive feedback loop, 2) Voltage divider with R , provides bias for turn off via D „ i R2 1) Gives flip flop reset capability for positive pulses, 2) Reset threshold depends upon the voltage divider formed by R-, and R , 1) Gives flip flop reset capability for negative pulses, 2) Reset threshold depends upon the voltage divider formed by R and R^, FIGURE 23. FLIP FLOP--FIRST SPECIAL FUNCTION AVAILABLE BY COMPONENT ADDITION ■71- If the internal node at the junction of the two resistors R^ and R^ is available, diode D^„ may be added. Its purpose is to allow 1 d r\Ri ^~' >R 1 / T2 OUTPUT 1— ^ I HI— (2) ONE SHOT I Closes positive feedback loop, providing a negative output pulse of duration proportional to the product of C and the resistance of R and R m parallel, 1) Provides cutoff bias for Bi^ ensuring noise insensitivity.. 2) Acts with Ro in determining pulse times o 3) Connection of R to V ensures that T, remains unsaturated immediately after regeneration. FIGURE 2k. ONE SHOT- -SECOND SPECIAL FUNCTION AVAILABLE BY COMPONENT ADDITION 7. CONCLUSIONS 7.1 Conclusions Logic elements have been described which offer an apparently novel solution to the problem of compatibility of input and output levels. The basic design of an inverting NOR/NAND element has been developed, together with that of a restoring OR/AND variant, available with minor component rearrangement. The existence has been shown of workable circuits using identical components in either of the two available configurations . The resulting logic elements have several desirable features, including single power supply operation, absence of close tolerance requirements and simple control of switching thresholds. The OR/aND circuit, in addition to simplifying decoder design, has been shown to be suited to the economic production of the composite logic functions required by storage and pulse forming elements. 7 '2 Future Investigation Work remains to be done on packaging of the circuits. Some directions in which this work may take seem clear: The use of a dual purpose, mult ip in module affixed to an interconnecting board seems natural. Intra modular wiring on the inter- connecting board would establish which of the -73- _74- NOR/nAND or or/ AND variants is used. Additional components required for flip flops^ etCo^ could be mounted on the interconnecting board. BIBLIOGRAPHY 1. Dewitt, D., and A. L. Russofif, Transistor Electronics ; New York: McGraw-Hill, 1957- 2. Heckimian, N. C, "PNP-NPN Circuits: A New Look at a Familiar Connection"; Electronics , vol. 35^ no. h^ , pp. 42-46, November 23, 19^2. 3. Hiinter, L. P., Handbook of Semiconductor Electronics ; New York: McGraw-Hill, Inc., I962. h. Joyce, V. M., and K. K. Clarke, Transistor Circuit Analysis ; Reading: Addison-Wesle y , Inc., I961. 5. Pressman, A. I., Design of Transistorized Circuits For Digital Circuits; New York: J. F. Rider, Inc., 1959- 6. Silicon Logic Circuit Modules , Santa Monica: Scientific Data Systems, 1963. 7. Smith, K. C, "Modification of Type R Plug- in Unit"; (Unpublished) DCL File No., 1964. 8. Switching Transistor Handbook , Phoenix: Motorola, Inc . , 1963* 9. Transistor Manual , Sixth Edition; Syracuse: General Electric Co., 1962. ■75- APPENDIX A, DEFINITION OF TRANSITION TIMES USING A GROUNDED EMITTER SWITCH Referring to Fig„ 25^ a definition of transition times used throughout the report will be presented « At times t. the pulse generator delivers a step of voltage V. . 1 in Previously, the transistor has been cut off since the emitter base junction is reversed biased, allowing only a small leakage current to be present in the collector o At time t. the input current rises immediately, beginning to charge the transistor's input capacitances o Turn on does not begin until time t , The time required for the transistor to react to the input pulse (ioe,, to reach the beginning of the active region) is called the delay time„ Since turn on is rather gradual the beginning of the change at t is hard to define „ a Hence, the ten per cent point (t ) of the voltage waveform is used instead „ With the transistor at the edge of conduction, the emitter becomes fo2rward biased and starts to inject current into the base„ At this time the collector current starts to increase toward saturation„ But this does not happen instantaneously and the time that it takes for the voltage to reach its 90 per cent point (t ) of its final value from the 10 per cent point (t, ) is called the rise time (t - t, ) „ This slow rise results from a finite c b transit delay between the base and the collector currents which in turn is caused by the emitter and collector junction capacitances charging up to their "on" value. The total turn on time of the transistor is, therefore, the delay time plus the rise time (t - t.)o As long as the input current is kept on, no further changes will take place. But as soon as the base current pulse is turned off (t, ), the -76- -77- BASE RESISTANCE INPUT PULSE SUPPLY OUT -Vc i OUTPUT ^' 10% "N r 'in 90 %J^ INPUT PULSE OUTPUT PULSE FIGURE 25. CIRCUIT AND WAVEFORMS USED IN THE DEFINITION OF TRANSITION TIMES FOR A GROUNDED EMITTER SWITCH -78- pulse at the "base will rise with little delay. Again the transistor fails to react until time t . The time interval (t - t,) is called the storage e e d •= time of the transistor because it is the time that it takes the minority carriers in the base and in the collector to recombine to the state where the transistor is about to cross from the saturated to the active region » Again there is only a gradual change in the waveform so the 9O per cent point (t ) is chosen for reference. Now the transistor comes out of saturation and falls through the active region into the "off" state. The fall time is measured from the 9O per cent point to the 10 per cent point (t ) of the waveform for the same reasons S as stated for the rise time. The total "off" time of the transistor is. therefore, defined as the storage time plus the fall time (t - t,) g d APPENDIX B QCh- ov> h-Ui (/)»- CJ ZUJ o ^^-0-U.0J N S 1i ^'^ (K JO Ul S 2 O lO ^ Z z z z CJ CM CVJ CM O G <1 Hi' % o o o Q. o ** ro -i O ^ 0) 00 h- (0 lO ^ to CM o O o o CO o o -. o « O EH CQ H CO B M CQ f^ > W O EH M EH B a < W O TO < Q PQ W EH EH <; p < O TO < O TO M W >H EH ^ ■79- APPENDIX C. SIMPLIFIED METHOD FOR FINDING VALUES OF A VOLTAGE DIVIDER NETWORK FROM A THEVENIN EQUIVALENT NETWORK 'THEV I THEV VSUPPLY u i L_ Let ^2 ^ ^SUPPLY •^ = R-j^ + R THEV V R THEV 2 V R 4- R SUPPLY 1 2 V, THEV V = K SUPPLY K = R^ + R^ \^2 R K ~ ^ — p 1 ~ R^ + R THEV R, R. = THEV R, 1 K R^ = THEV 2 1 - K -80-