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UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN '■ DEC 16 «H L161 — O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/standardizationo400mart £(j. tJ Report No. UOO /TucX^ STANDARDIZATION OF CONTROL POINT REALIZATION COO-1018-1206 by Ronald Gustav Martin May 21, 1970 ihe library of th the library of the; JUk UNIVERSITY u, AT yWAI^PHAMPftiftNoiS AI URBANA-CHAMPAIGMI COO-1018-1206 Report No. U00 STANDARDIZATION OF CONTROL POINT REALIZATION* by Ronald Gustav Martin May, 1970 Department of Computer Science University of Illinois Urbana, Illinois 6l801 ^Supported in part by Contract Number U.S. AEC AT(ll-l)-10l8 and submitted in partial fulfillment for the degree of Masters of Science in Electrical Engineering, at the University of Illinois, May, 1970. Ill ACKNOWLEDGEMENT The author would like to thank his advisor, Professor Sylvian R. Ray, for his helpful advice and guidance in the preparation of this thesis. The author would also like to thank Mrs. Betty Gunsalus for typing the final draft and Mr . Stanley Zundo for preparing the figures included in this thesis and finally to Mr. Dennis Reed and the offset department for the reproduction of this thesis. iv TABLE OF CONTENTS Page INTRODUCTION 1 1. PSEUDO-ASYNCHRONOUS CONTROL DESIGN 2 1.1 Design Strategy 2 1 . 2 Control Reliability and Maintenance h 2 . FLOW CHART 6 2 . 1 Function 6 2.2 Notation 7 2 . 3 Examples 11 3. CONTROL POINT - A BUILDING BLOCK APPROACH IT 3.1 Description 17 3.1.1 Task Stage 18 3.1.2 Timing Stage 23 3 . 2 Sequence Stage 30 k . CONTROL LOGIC IMPLEMENTATION 38 k.l Conversion of Flow Charts to Control Logic Representation.. 38 1+.2 Hardware Realization 1+3 1+.3 Question of Minimization vs. Standardization 1+5 CONCLUSION 1+7 LIST OF REFERENCES kQ APPENDIX I. Examples of Actual Flow Chart to Logic Drawing Conversions.. 1+9 II. Test Results for Control Point Configuration 58 LIST OF TABLES Table Page 2.3.1 Mathematical Designation for M0NPAR 12 2.3.2 Identification of Terms for M0NPAR 12 2.3.3 Mathematical Designation for XSET Ik 2 .3. k Identification of Terms for XSET 15 i+.l.l Conversion of Flow Chart to Logic Representation... 39 VI LIST OF FIGURES Figure Page 2.2.1 Example of a Routine Symbol 9 2.2.2 Example of a Task Box 9 2.2.3 Example of Parallel Conditional Tasks 9 2.2.1+ Examples of Decision Symbol 10 2.2.5 Example of Reply Symbol 10 2.3.1 Flow Chart of M0NPAR 13 2.3.2 Flow Chart of XSET 16 3.1.1.1 Block Diagram of Task Stage Logic 19 3.1.1.2 Most Elementary Task Stage Configuration 20 3.1.1.3 Multiple "Advance In" Inputs to Memory Element 22 3.1.2.1 Timing Stage Using Internal Delay Element 2k 3.1.2.2 Timing Stage Equivalent Circuits 26 3.1.2.3 Delay Circuit with Diode to Enhance Recovery 28 3 . 1 . 2 . k Timing Stage Using External Reply 28 3.1.2.5 Control Point Block Diagram and Circuit Configuration... 29 3.2.1 Two Way Branch Sequence Stage Logic 31 3.2.2 WAIT Condition Using EN Gate 33 3.2.3 WAIT Condition Using A~~ Line 34 3.2.4 Interlocking Two Parallel Control Chains 35 3.2.5 "Calling Control Point" Circuit Configuration 37 4.1.1 Logic Drawing for M0NPAR 42 4.2.1 Control Point Card 44 INTRODUCTION The philosophy of computer control design has generally tended to be quite fluid in its approach. Variation in design approaches can be attri- buted to such factors as: control compatibility with computer configuration, advances in both hardware and software technology, and the consideration of speed and cost requirements. A control can be basically considered as being synchronous , asynchronous , pseudo-asynchronous , or microprogrammed and the design techniques used are a function of this classification. A problem area common to all control design techniques has been recognized for some time; there exists a discontinuity in the communication between the procedural or software control design approach and that of the implementation of this design into hardware by the engineer. The purpose of this paper is to specify some techniques which more closely bind together the software and hardware approaches to control design and in particular, the design of a pseudo-asynchronous type of control. 1. PSEUDO-ASYNCHRONOUS CONTROL DESIGN 1.1 Design Strategy Historically, the University of Illinois Digital Computer Labora- tory has been primarily involved in the investigation and construction of asynchronous computers. The use of asynchronous control has been dictated by the parallel operation of the various processors and the general complexity and speed considerations of the complete system. By designing the computer so that its behavior is independent of the relative speeds of the elements, one may ignore the problem of matching speeds and synchronizing signals to achieve correct operation. While asynchronous networks do have certain advantages over synchronous ones, there are some design restrictions as Braun (1963) has stated, "because of an indeterminate time for execution of operations and the complexities required in general for hazard free operation, asynchronous systems are considered more difficult to design, understand, and service." It then is the responsibility of both the mathematican and the logical design engineers to work together to optimize the design of the asynchronous control such that these restrictions are minimized. Control logic can generally be considered as being either speed-dependent or speed- independent is its operation. A speed-dependent circuit can be basically described as one in which the operation is a function of time as determined by a model flip-flop or timing delay. That is, once a control circuit is activated, there is a finite time allocated for the control to perform its various tasks. Each control function must be carefully analyzed to determine the minimum time required to perform its specific task. Consideration must be given to: the variations of component parameters, propagation delay times, and the effects of component aging and voltage changes. While the hardware realization from logical flow charts is quite straight forward for this type of control, there are some sacrifices to both operational speed and reliability. Speed-independent or asynchronous logic is different from speed- dependent logic in that reply signals are used to indicate the completion of a given operation. These reply signals are incorporated in the basic sequencing control logic and elimiates the need for model flip-flops or timing delays. The operational speed is a function of the time actually required to complete a specific task and there, therefore, can be considered to be optimized. While this type of control does not have the disadvantages of a speed-dependent system, it does require additional hardware which greatly increases the design complexity and renders a logical design problem of flow chart realization. Robert Swartout (1963) performed extensive studies in speed-independent logic for control and stated: "The majority of the logical design problems were presented as information flow charts to be realized. Unfortunately, the state of the speed- independent logical design art is still mostly an art and not a science. " * The design of the control units used in the Illiac III computer and the design techniques described in this paper are a combination of speed- dependent and speed-independent circuits (pseudo-asynchronous control) incorporating the advantages of both. Since the design of this particular control logic, like many other synthesis procedures, does not necessarily produce a unique topology, design tachniques have been developed in the Illiac III project to insure consistency throughout the control. * Illiac III is an AEC funded pattern recognition computer being constructed at the University of Illinois. 1.2 Control Reliability and Maintenance Anyone who has had the opportunity to be involved in the operation of a digital computer, will agree that it is only useful so long as it func- tions correctly and consistently. As digital computers have been designed to operate at faster and faster rates and have become greater in size and complexity, the requirements for malfunction-free operation by each circuit element in the machine have become extremely high. It is conceivable that circuit elements might be required to operate as many as 10 times in a single day without an error. This high degree of reliability can be attained by the proper selection of components, the utilization of specific fabrica- tion techniques , along with design strategies which have proven to function as free of malfunctions as possible. With the advances in both component and fabrication technologies, the assurance of control reliability becomes related very closely with the design techniques being employed. No matter how much consideration is given to control reliability, there will be certain unavoidable malfunctions which do occur. With the in- creasing size of computing machines, it does not require a great deal of imagination to envision the problems associated with the location of a defec- tive circuit element within a system that might employ thousands of these elements. It is, therefore, necessary that the computer control circuitry be so designed that not only are the apparently unattainable requirements for circuit reliability met, but also that it is relatively easy to service and maintain as well. In the past, a circuit malfunction which has been detected in a processor of the computer has usually been localized by the use of diagnostic routines. If a circuit within the control malfunctions, the probability of locating this trouble is much less than it would be for another unit or pro- cessor in the computer. This is due to the fact that the incorrectly opera- ting circuit can cause the diagnostic routines to be improperly executed, which might just add to the total confusion that already exists. The actual maintenance or "de-bugging" of the control then becomes one that is related to how clever or experienced the service personnel are and is at best, one that is strictly on a hit and miss proposition. The control should then be designed to operate with greater reli- ability and be easier to service than any other portion of the machine. 2. FLOW CHART 2.1 Function The flow chart is the means by which the mathematician or software orientated individual conveys to the logical designer the time or sequential ordering of operations to be performed in order that a given instruction/ routine, or subset of an instruction/routine, be properly executed. It can be one that contains only the essential information used in the initial planning stage of control design or it might be a detailed functional description used for check-out and maintenance. As Gillies (1961) noted: "As a practical matter, a flow chart nota- tion should preferably be compact, easily drawn freehand, and should exhibit only the essential information. This is important at the planning stage because such flow charts are very suscep- tible to error and must be redrawn, with correc- tions, many times." The flow chart is actually then a mathematical description that corresponds to a logical design and can be used to either implement this design into hardware or as a check to insure that the control design is correct. It is essential then that the mathematicians and logical designers work closely together to insure that these flow charts are representative of a design in which there has been a minimization of the number of steps required to perform a given operation or routine. There should also be mutual agree- ment to such trivial details as the naming of gates, registers, buffers, and other associated pieces of hardware that will be acted upon by the control. If the flow charts are presented to the logical designer in an optimized, final form, along with a detailed listing and description of names used in these charts, his task of implementing these flow charts into an actual logical hardware design will be greatly simplified. 2.2 Notation There are "basically only four different types of symbols used in the representation of these flow charts. There is also special consideration given to the notation contained within these symbols . The symbol f J is used to indicate either the entry or call of a routine with its name appearing within the symbol and is shown in Figure 2.2.1. Probably the most important and commonly used symbol in the flow charts is the task box . This box, as shown in Figure 2.2.2, indicates the task or operation that is to be performed in the time ordered sequence of events that occur during a given routine. Within the box is notation corre- sponding to the specific operation that occurs when the task box is entered. This notation follows the format XXX - Y - ZZ , where XXX is the name of the element or device upon which the task will be performed (i.e., the dependent variable), Y indicates the type of operation being executed by the box, and ZZ specifies the operational variable (i.e., the independent variable). For example, LSB/G = 1 indicates that the gate of an element LSB would be "turned on" during the operation of this particular control event. Another example is XDU «- A, where the value of a variable A, is loaded into a memory device XDU. Associated with each task is a certain duration of time after which a reply signal is generated and control proceeds along the exit line of the box. 8 When more than one task can be initiated concurrently , the condi- tions which must exist for the task to take place are indicated above the task entry line as shown in Figure 2.2.3. The reply lines of the TASK A and TASK B boxes merge together on one horizontal line. Control will advance to the next stage of the flow chart when both replies are true, that is when Reply A • Reply B = "l". The symbol <^ ^ is used to represent a decision is to be performed and the name of the dependent variable is noted within the symbol. Figure 2.2.U illustrates the use of this decision symbol. If DONE = "l", then go to X, whereas if DONE = "0", then control would go to Y. The decision could also be used to cause a "wait" until certain conditions are met. The termination or reply of a given routine is indicated by the symbol ( ) and is shown in Figure 2.2.5. The termination of a routine might be due to either an error occurring or just the normal completion of the tasks, so therefore, a memory element for either case is included with the reply signal. The flow chart will then consist of various combinations of these four symbols connected by lines with arrowheads indicating the direction of flow. In most instances, the chart will be layed out such that the flow will be from top to bottom. The selection of the symbols and notation described in this paper are those used by the author in the design of the Scanner-Monitor-Video Controller for the Illiac III computer and are actually quite arbitrary in nature. The specific symbolic and notational representation to use is strictly a matter of personal choice and mutual agreement between the software and hardware individual involved in the design of a control. A Figure 2.2.1 - Example of a Routine symbol LSB/G = 1 XDU «- A Figure 2.2.2 - Example of a Task Box T.C.A TASK A REPLY A T.C.B TASK B REPLY B T.C. = Task Condition FIGURE 2.2.3 - Example of Parallel Conditional Tasks 10 Figure 2.2.U - Examples of Decision Symbol DETECT \ NO ERROR TASK n I REPLY Figure 2.2.5 - Example of Reply Symbol 11 2.3 Examples Several flov charts will be examined to reinforce the initial ideas and views which were presented in the proceeding section. These examples will show the mathematicians design approach, along with the identification of terms, and the flow chart equivalent. The first example will show the hierarchy of subroutines contained within a routine called M0NPAB.* Table 2.3.1 is the mathematical design approach and the identification of terms has been listed in Table 2.3.2. The flow chart equivalent of M0WPAE can be seen in Figure 2.3-1. The second example will deal more explicitly with one of these sub- routines XSET. The mathematical approach and the identification of terms are shown in Table 2.3.3 and Table 2.3-^ respectively. Figure 2.3.2 illustrates the flow chart for this subroutine. * M0NPAR is a portion of the Scanner-Monitor Communication Control used in the Illiac III computer. 12 M0NPAR (SET MONITOR PARAMETERS) ® Called by BMC or INCR (D Call MINIT (3) Call a SET (where a e (W, X, Y, Z) ) © SEND = 1 (|) If DONE, go to (3) © Reply Table 2.3.1 Mathematical Designation for M0NPAR BMC, Beam Motion Control INCR , Incremental Control MINIT, Initialize monitor parameters routine aSET, (k) Set monitor parameter routines i.e., WSET, XSET, YSET, ZSET SEND, Flag communication bit DONE, Indicates all parameters are properly set Table 2.3.2 Identification of Terms for M0NPAR SET MONITOR PARAMETERS - (M0NPAR) 13 BMC ■W M0NPAR INCREMENTAL MINIT Figure 2.3.1 Flow Chart of M0NPAR 1U X-SET (Set x-axis parameters) © If DPQX, go to © © If A^G'tEXPX = p), go to © © If A-G- (EXPX = q), go to © © Go to @ © EXPX <- © DPQX «- 1 © If DHX, go to ^ © If (EXPX = h), go to (lg © EXPX +■ © DHX «■ 1 11) If (DF = 2) + K, go to (^ 2) If A-G, go to © 3) If (EXPX = n), go to QJJ) DN «- 1 @ MDCX «- 00 §) If A-G, go to @ J) MDCZ «• 00 ^ Go to © l|) EXPX *■ EXPX + 1 0) Reply Table 2.3-3 Mathematical Designation for XSET 15 EXPX, 3 "bit counter used to count up to values of p, q, h, and n DPQX, (EXPX = p or q) flip-flop DHX, (EXPX = h) flip-flop DN, (EXPX = n) flip-flop MDCX, 2 bit register used for transfer of information to X control MDCZ, 2 bit register used for transfer of information to Z control A, scan-axis informational bit G, rotation of scan-axis informational bit p, 3 bits of x-axis incrementing step size information q, 3 bits of y-axis incrementing step size information h, 3 bits of magnification information n, 2 bits of gray scale information K, constant data or constant sample rate informational bit (DF=2), raster type data format Table 2.3.U Identification of Terms for XSET 16 YES ' 'YES 1 EXPX ■>- DHX * 1 1 I DN ~ 1 MDCX * 00 S A • G ^ YES EXPX * EXPX ♦ 1 I i 1 1 ^rTJO MDCZ «■ 00 ( REPLY ) Figure 2.3.2 Flow Chaxt of JCSET IT 3. CONTROL POINT - A BUILDING BLOCK APPBOACH 3.1 Description Pseudo-asynchronous control is based on the concept that tasks be performed in controlled steps or in irregular time intervals dependent on the execution time of these tasks. This type of control has been implemented at Illinois by the use of logical circuits called control point . The control point originally developed as a modification of the Illiac II "speed indepen- dent" control circuits by Gilles, Robertson, and Swartwout (1961). Generally speaking, each control step is performed by one control point. In many cases, the control point may be used to implement several similar control steps from different parts of a sequence and will return to that part of the sequence from which it was called. The basic idea behind a control point is that it initiates some operation by turning on a given set of control lines. These control lines will remain on until either a certain length of time has passed, or a reply has been received indicating that the operation has been completed. As these control lines are turned off, an advance signal is initiated which will acti- vate the next control point. The use of control point, therefore, provides an ordered scheme for the assignment of specific tasks being performed in controlled steps. In other words, the control point renders to the logical designer a building block approach or technique in the design of pseudo-asynchronous control. The evolution of the control point design for Illiac III has been long and tortuous. The investigation and applications of several control 18 point configurations have "been made by Atkins and Nordmann (1969). The con- trol point configuration presented in this paper consists of two stages: a task stage and a timing stage. 3.1.1 Task Stage The function of the task stage is to perform certain operations on various hardware: i.e., gates are operated, flip-flops are set, counters in- cremented or other control points called. These operations may be conditional upon status conditions. Consider the block diagram of typical task stage logic as shown in Figure 3.1.1.1. The advance in line , A., is connected to an adjacent stage logic. When this line drops to "0" , the memory element is set and the task logic is said to be primed. When A. returns to "l", the task activation signal , DO, becomes "0" provided that the enable line, EN, is at "l". The task stage logic is now said to have been initiated. The DO signal from the memory box is one input to the conditional task logic, while the other inputs to this logic are external conditions appropriate to that task stage. Typical examples of these conditions are the outputs of counter decoders, the contents of parameter registers, or the out- puts of status flip-flops. The DO signal also activates the timing stage which, after a select- able duration, causes the advance out line, a o > "to go to "0". This action will reset the memory element, thus turning off the task element, and can be used to also prime and initiate the next succeeding task stage. Figure 3.1.1.2 illustrates the most elementary task stage configura- tion and an explanatory timing diagram. In this case the timing stage will consist of an internal timing model which will be explained later in this paper. 19 EXTERNAL CONDITIONS A. 1 V DO ^~ CONDITIONAL TASK LOGIC ■P* E] 1 f ^ i ^- } MEMORY ELEMENT TIMING STAGE A / i 1 A — ► TASK 1 TASK. TASK n EXTERNAL REPLY INPUT TO NEXT TASK STAGE A = f (internal time delay or external reply signal) Figure 3.1.1.1 Block Diagram of Task Stage Logic 20 EXTERNAL CONDITIONS i CONDITIONAL TASK LOGIC TASK LINES TIMING DIAGRAM: A. ® DO Assume that EN = 1 and CC = 1 Figure 3.1.1.2 Most Elementary Task Stage Configuration 21 No detailed logic is shown in the conditional task logic box since the configuration is highly variable from task stage to task stage. The most elementary configuration would be a direct connection of the DO (perhaps through an invertor or line driver) to the task lines. The enable input , EN, offers a facility for inhibiting the operation of the task stage. If this input is held at "0" , the control sequence will stop when the memory element of the inhibited stage is initiated. As EN returns to "l" , the normal operation of DO will resume. This input may then be used to either inhibit a control sequence conditional upon an asynchronous signal or serve as a maintenance stop. A maintenance stop may be performed either manually as a function of a control panel switch, or automatically by the use of a diagnostic testing routine. The common-clear input , CC , provides a means by which the task stage memory element can be set to the "off" state. Typically the CC input of all the task stages of a routine(s) are connected together and "initialized" at the start of a specific control sequence. It may be found desirable in some instances that a task stage be initiated from more than one advance in line. Figure 3. 1.1. 3 illustrates a method for implementing multiple advance in signals to a memory element. The A inputs are quiescently "l". When any one drops to "0", the memory element flip-flop is set such that@= "l". As long as any A. or the EN input is "0" the DO signal remains at "l" , but when they return to "l" DO drops to activate the task logic. The duration of the A. •-•A. signals must be long ° n enough to allow the memory flip-flops to set (i.e., compensate for the added propagation delay caused by the two additional NANDs). 22 DO Figure 3.1.1.3 Multiple "Advance In" Inputs to Memory Element 23 3.1.2 Timing Stage It is the function of this stage to provide a delay of the DO signal for a time period necessary to complete all the tasks of a given task stage. Associated with this time delay is the logic required for the genera- tion of a reply signal Ao used to reset the task memory flip-flop, which turns off the task lines , and drives the next sequence stage logic which primes and initiates the next task stage. In many cases this time delay is generated by an internal delay element which provides a timing model of the actual task. Figure 3.1.2.1 illustrates a timing stage configuration and an explanatory timing diagram. As DO goes to "0" , the output of NATO I, goes to "l". The advance out line, Aq , will be delayed from going to "0" by the amount of time required for the RC-network at the ® input of NAND II to charge to the logical "l" thres- hold. When this threshold is reached, Aq drops to "0" causing the task memory to be reset and therefore DO will return to "l". The following design information on this circuit configuration was obtained by the use of basic circuit transformation techniques. A simplified model of NAND II and the equivalent circuits used in this analysis are shown in Figure 3.1.2.2. The logic elements used in this design were 5^/7^ series TTL and the following assumptions have been made. V =5.0 volts cc V THRESHOLD = V (b) = l-^ volts (midpoint of uncertainty ^-'"l" range) R = l» Kfi (value given in T.I. -TTL handbook) R p = 8.2 K Q, (determined empirically) C = 100 pfd. 2\ DO r L. ® ® II -*- A ^ o TIMING DIAGRAM; DO © '1" THRESHOLD DELAY Figure 3.1-2.1 Timing Stage Using Internal Delay Element 25 Using the Thevenin equivalent circuit, the timing model has been reduced to a low-pass RC-network where V TH ' Vi^TT^ ' 5( lftf> m 3 - 36 VOltS B R B TH " I" T^ " 2 - 6 ? K a The delay time is related then to the equation for the charging of capacitor C V c = V TH ( 1 - e " t/(R th C) ) If we assume that V is initially zero and that the delay ends when V = threshold = l.k volts, then l.k = 3.36 (1 _ e -t/2.69 x 10" 7 ) ) t = (.538 x 2.69 x 10~ 7 ) = 1U5 nS The recovery time or the time required to discharge C is determined solely "by R^ and C. The discharge time can then be expressed by the equation: V = V (e" t/R 2 C ) C TH v ' If we assume that V is initially equal to V and that C is con- L In sidered to be discharged when 1 = .lV m „, then C in .336 = 3.36 (e- t/8 ' 2 X 10 " ?) ) t = (2.3 x 8.2 x 10" 7 ) = l885nS It can then be seen from the above calculation that approximately 13 delay times must elapse between the application of input pulses at (A) to 26 NAND II is typically S^OON EQUIVALENT CIRCUIT THEVENIN'S EQUIVALENT + 5 UK X TH R TH A/W + v © \ - *« *»* VV 1 " 6 ^' Figure 3.1.2.2 Timing Stage Equivalent Circuits 27 avoid interaction. If this constraint hinders circuit performance it may be greatly reduced by the addition of a diode as shown in Figure 3.1.2.3. This diode, a USD25 is a HP2800 hot carrier device with a low forward drop and junction capacitance, is used to discharge C when (A) goes to "0". With the addition of this diode, only 1.5 delay times are required between input pulses or the timing stage can be pulsed as soon as it has completed its delay function. Empirical tests have indicated a design center value for R of 8.2Kft with upper and lower limits of 12K and 6.2K respectively. Using R = 8.2KA, the following was found to hold: Delay - 1.5nS/pFd. Variation of + -5v in V - + 13% Variation between IC packages - + 15% Variation due to R = 6.2K -> 12K - 8% The delay time of the timing stage could also be a direct function of an external replay signal as has been shown in Figure 3.I.2.H. In this case the RC-network has been replaced by the reply line, GO. Once again as in the previous example, as DO goes to "0", the output of NAND I goes to "l" . The advance out line A will not go to "0" until GO has been set to "l". If GO were "l" as DO goes to "0", the delay time would then depend on the propagation time of NAND I and NAND II and the amount of time required for the task flip-flop to be reset by A The control point is then the combination of a task stage and a timing stage with the block diagram and circuit configuration being repre- sented in Figure 3.1.2.5. and actual test results are presented in Appendix II, 28 ®-H L. — w- USD25 8.2K X Figure 3.1.2.3 Delay Circuit with Diode to Enhance Recovery r ~\ DO ~T\® rr\ i — y © f ! (JO L _! Figure 3-1.2.U Timing Stage Using External Reply 29 i cc * — ► A A. CC where C = f (time delay required) Figure 3.1.2.5 Control Point Block Diagram and Circuit Configuration 30 3. 2 Sequence Stage Interspersed with the control points used to implement the asynchro- nous controlled steps is the sequence stage. The function of the stage is basically one of selection or steering. That is, as a control point completes its specific task the sequence stage makes the decision as to which control point (s) to initiate next. The most elementary example of sequence stage logic is merely a wire connecting the Aq output of one control point to the A. input of the next control point . In the case where two or more control points are to he called con- currently, the sequence stage logic will he AND'ed as a function of Aq and external conditions. Figure 3.2.1 illustrates an example of a two-way branch. The conditions, a and B, determine where the Aq pulse from the previous control point is directed. It is important that these conditions are set prior to the arrival of the A Q pulse, therefore, it is advisable that a or 3 not be determined by the action of the control point which generates the A Q pulse which they steer. It should be noted that at least one condition must be true or else the A pulse is lost and the control sequence hangs-up i.e., if o a = 3 = 0, an error exists. In many cases the conditional logic is designed such that a = 3 and this error situation is averted. The sequence stage may also be required to delay the continuation of control contingent upon an asynchronous wait condition. Since the arrival time of this signal is unknown, the circuit configuration of Figure 3.2.1 is not applicable. Figure 3.2.2 and Figure 3.2.3 illustrates methods of imple- menting this wait condition. A A, A. a, 3 ARE BRANCHING CONDITIONS Figure 3.2.1 Two Way Branch Sequence Stage Logic 31 A A. 32 In Figure 3.2.2 the wait signal is used to delay the action of con- trol point after it has been initiated. That is, DO will be inhibited from going to "0" until WAIT goes to "0". When the wait condition is satisfied, DO provides a means for keeping EN at "l" until the control point completes its normal operation. This same delay action to the control point operation could also be a function of a maintenance halt , MH, used for check-out and diagnostic procedures. In Figure 3.2.3 the wait signal is used to delay the propagation of the A ' signal. The DO signal is then a function of both the timing stage and the wait condition. Here the DO line will drop to "0" and remain there (even though the timing stage is done) until WAIT goes to "0". The A ' signal will then terminate the operation of the control point and initiate the next stage logic . This same wait logic configuration may also be used to interlock two or more parallel, independent control chains. The design requirement here is to make the A signal to the next stage wait until all the parallel tasks are complete. Figure 3.2.1* illustrates an example of this interlocked control chains. The A line of last control point of each chain is delay until a reply from all the chains is received. It is assumed that when one control chain is activated, then so is the other, i.e., that eventually both replies will be generated . Another application of the wait logic , similar to that shown in Figure 3.2.3, is where a control point is used to call some routine and will not advance control until the called routine has replied. For apparent reasons, this configuration has been named "calling control point" and is 33 DO r— ► a A. © DO WAIT EN (if MH = 0) Figure 3.2.2 WAIT Condition Using EN Gate 3k EN DO i — ► " a7 i A o cc — ► C.P. v T.TA Tip WAXi Y • ^ A ASSUME THAT EN = CC = 1 DO WAIT A * o Figure 3.2.3 Wait Condition Using A Line 35 1 0* u° " CM u- O rli ' ♦ " 1 1 o l< H P^ O H P^ O J k i " t l< H CM 25 H H w En O CO >H CO CO w o EH o EH o a a 0) •H w •H 43 o H o In o o H 0) Ph •rH O O H J-i INDICATES EXTERNAL PIN 2. (8) CONFIGURATION PER BOARD 3. VALUE OF C DEPENDENT ON FUNCTION OF DO Figure 4.2.1 Control Point Card U5 EN gate of all control points are connected to the etched board output pins to provide maintenance capabilities. This provides the capability for "stepping" the control sequence or routine through its normal operating functions at a level of individual control point increments. This has proven extremely useful in control check- out and .the detection of erroneous task operation. There still remains the specification of delay time required for the control point to perform its task. In some cases the control point may function in a speed-independent manner and therefore no delay capacitor is used in the timing stage. However if a delay capacitor is to be used, it is the responsibility of the logic designer to select a value of capacitance that will guarantee that the control point properly executes its task(s). Some design information related to control point operation is available in Appendix II. U.3 Question of Minimization vs. Standardization While the main theme of this paper has been concerned with the standardization of control design implementation, the hardware realization may not necessarily be of an optimized nature. That is, it is possible that not all the logic elements of a given IC chip have been used. It is also possible that not all the available IC socket locations are utilized due to the unique- ness of the design function or the output pin limitation of the etched board. In many cases these constraints have proven to be advantageous instead of being a disadvantage. It is often times necessary to make modi- fications and changes to the logic design as determined by the results of control check-out and testing. An extra logic element or IC socket location can often times be very handy in making these modifications. It is then the U6 responsibility of the logic designer to specify the type of logic elements (NAND's, ROR's, latches, drivers, etc.) to be used in a standardized control implementation approach while still trying to maintain a minimization of logic elements. ^7 CONCLUSION Since the design of a pseudo-asynchronous control logic does not necessarily produce a unique topology, a design technique or method has been developed to provide a standardized design approach. The specific technique chosen produced a comprehensive set of sequentially ordered control diagrams (flow charts) which could be converted directly to logical drawings using certain standard modeling procedures (control point). Additional considera- tion was given to such areas as control reliability, hardware realization, and the ease of control maintenance. The techniques and procedures offered in this paper were used in the design and implementation of the Illiac III Scanner-Monitor-Video Controller and proved to be extremely helpful in the realization of this control. While these techniques were applied to the control design for a specific computer, they may be applicable to other design disciplines. In particular, there appears to be a correlation to the work of Clark (1966) on the macromodular approach to computer design. kQ LIST OF REFERENCES Atkins, D. E. , (December 1969), "illiac III Computer System Manual: Arithmetic Units", Vol. I, Illinois Department of Computer Science Report No. 366 Braun, E. L. , (March 1963), "Digital Computer Design", Academic Press, New York Clark, W. A., (February, 1966), "A Macromodular Approach To Computer Design", Washington University Computer Research Laboratory Technical Report No. 1 Friedman, A. D. , (June 1968), "Synthesis of Asynchronous Sequential Circuits with Multiple Input Changes", IEEE Transactions on Computers, Vol. C-17 , No. 6 Gillies, D. B. , (August 1961), "A Flow Chart Notation for the Description of a Speed Independent Control", Department of Computer Science File No. 386 Langdon, G. G. , (December 1968), "Analysis of Asynchronous Circuits Under Different Delay Assumptions", IEEE Transactions on Computers, Vol. C-17, No. 12 Nordmann, B. J., (September 1969), "illiac III Computer System Manual: Taxicrinic Processor", Department of Computer Science Report (in process) Robertson, J. E. , (August 196l), "Problems in the Physical Realization of Speed- Independent Control", Department of Computer Science File No. 387 Swartwout , R. E. , (August 196l) , "One Method for Designing Speed-Independent Logic for a Control", Department of Computer Science File No. 388 Swartwout, R. E. , (December I963), "Further Studies in Speed- Independent Logic for a Control", PhD. Thesis, University of Illinois, Department of Computer Science Report No. 130 Appendix I This appendix contains actual flow charts and their logical representations for control routines of the Scanner-Monitor-Video Controller of Illiac III. 50 Flow Chart of SAMPLE SCAN A FIELD YES y 2 (VERNIER) 1 1 " B-DETECT MSAMPLE f(«) (Single (Called by b-detect) Routine) < 1 GVS * BUFR + 1 E-DETECT Ha) (Single Routine) MSAMPLE (Called by E-DETECT) YES FLYBACK f(a) (Single Routine) c REPLY ) Y f " VEFD y 2 = VEFD • R y,= VEFF-R SAMPLE (INCREMENT ROUTINE) Logic Draving of SAMPLE 51 Flow Chart of B-DETECT 52 FLYBACK (TS = l) a = f (XORY) aBC/S * 1 aCLOCK «■ 1 a BEGH - 1 MSAMPLE aCLOCK + aBC/S + SAMPLE (R - 1) ERR5 «■ 1 aCLOCK «- aBC/S -•- f REPLY J f INTERRUPT J B-DETECT ROUTINE Logic Drawing of B-DETECT 53 $ i Flow Chart of E-DETECT 5U A -► a A * a aE/S - 1 oCLOCK * 1 aBEGIN = 1 MSAMPLE ■SAMPLE BENABLE * F aCLOCK * BENABLE * aE/S «- aGVS + 1 LBUF * SBUF «- VLS «- VBOL*- I REPLY J NO aOUW 'YES YES INTERRUPT = 1 ERR5 * 1 BENABLE * ( INTERRUPT J E-DETECT ROUTINE Logic Drawing of E-DETECT 55 vt u * * (J o IS 18 Flow Chart of FLYBACK 56 PREPARE AW OTHER — FIELD SAMPLE' MRE5ET (MONITOR) f REPLY j FLYBACK YES aGB/G = 1 CRESET (Routine) MSAM * EOL - MSAM - 1 YES 1 1 M uDU «■ aDU aLM i- REVERSE 1 U'lONlTOR) 1 ' i [MO i <^BUF y uwu s YES B-DETECT f(a) (Routine) aDU *■ aDU aLM < 6 MSAMPLE (Called by B-Detect) REVERSE 2 (MONITOR) XORY-»a = X XORY — a = Y 4 8 = A = A CWC =_(DF = 1) • WRITE* C TS = G.(h = 0)'(D = 0,0)-V FLYBACK (Routine) Logic Drawing of FLYBACK 57 -. U k u. life 18 58 Appendix II This appendix contains test results for a typical control point configuration. The card used in these tests was Buffer Control A (32B-M20) Serial #016170 Control Point #1 (-TL) DATAPULSE *Spare NAM) used to obtain negative going pulse from DATAPULSE required to set flip-flop. The test results and photographs in this appendix all refer to the above circuit configuration. 59 SCOPE SETTINGS TOP TRACE: 2V/DIV. BOTTOM TRACE; IV/DIV. SWEEP SPEED: lOOnS/DIV, IDENTIFICATION TOP TRACE: Input pulse at pin k of B6 BOTTOM TRACE: PIN 5 of B6 - Charge & discharge curve of delay element (22 pfd. & 8.2K) without hot carrier diode, 6o SCOPE SETTINGS TOP TRACE: 2V/DIV. BOTTOM TRACE: 1V/DIV. SWEEP SPEED: 50nS/DIV. IDENTIFICATION TOP TRACE: Input pulse at pin h of B6 BOTTOM TRACE: Pin 5 of B6 - Change & discharge curve of delay elements (22 pfd. & 8.2K) with hot carrier diode 6l SCOPE SETTING TRACE; 2V/DIV. SWEEP SPEED: 20nS/DIV. IDENTIFICATION TRACE: Output pulse at pin 6 of C6 (DO) using no delay elements (R & C). Pulse width indicates the inherent delay of control point itself, consisting of collector delays, wiring capacitance, etc. NOTE: Typical control point cycle time is therefore approximately 20 MHz 62 awiiiiii 10 SCOPE SETTINGS ALL TRACES: 5V/DIV. SWEEP SPEED: 50nS/DIV. IDENTIFICATION TRACES: Output pulse at pin 6 of C6 (DO) using various yalues of capacitance in the timing element and R equal to 8.2K in all cases. TOP TPACE #1 #2 #3 BOTTOM #k C (pfd.) 22 hi 68 100 i AEC-427 U. S. ATOMIC ENERGY COMMISSION Kail UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFX AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) >EC REPORT NO. leport No. 1+00 :Q0-10l8-1206 2. TITLE STANDARDIZATION OF CONTROL POINT REALIZATION YPE OF DOCUMENT (Check one): fifl a. Scientific and technical report [~~l b. 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