ill LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN Digitized by the Internet Archive in 2013 http://archive.org/details/pruningbranching471naka 4{L Report No. ^71 ?/ August 1971 /Kcu-U} PRUNING AND BRANCHING METHODS FOR DESIGNING OPTIMAL NETWORKS BY THE BRANCH -AND -BOUND METHOD by Tomoyasu NAKAGAWA Hung Chi LAI Saburo MUROGA DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS .UNIVERSITY OF ILLINOIS ATI - Report No. k'Jl PRIMING AND BRANCHING METHODS FOR DESIGNING OPTIMAL NETWORKS BY THE BRANCH- AJTO- BOUND METHOD* Tomoyasu NAKAGAWA Hung Chi LAI Saburo MUROGA Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part by the National Science Foundation under Grant No. NSF GJ-5O3. CONTENTS INTRODUCTION 1. A method of reducing the number of redundant gates and connections in non-optimal NOR networks. 2. The branching strategy, and the enitre algorithm of the branch-and- bound method. 3. Computational experiment. INTRODUCTION In this paper, we present a branch- and-bound algorithm for obtaining optimal NOR networks [3, ^-1 • This algorithm differs from Davidson's in the inclusion of the following two new features; i.e., (i) an efficient pruning of non-optimal networks and (ii) a different branching strategy for enumer- ating feasible networks. The feature of pruning non-optimal networks is based on the construction of better networks by eliminating redundant gates and connections of the networks which the enumerative part of the branch- and-bound algorithm generates; we call this feature the redundancy check The principle of our branching strategy is based on an attempt to minimize the width of the search tree of the branch- and-bound algorithm. We present in section 1 the scheme of the redundancy check which we incorporated into our computer program of the branch-and-bound method, called ILLOD-(NOR-B) (Illinois LOgical Design with NOR-gates by Branch- and-bound method ) . In section 2, we describe the branching strategy. (The entire algorithm of the branch-and-bound method is presented in the paper [3].) For comparison, we summarize the differences in branching strategy be- tween Davidson's algorithm and ours, and present some computational results with both versions. Section 3 contains computational experiments comparing Davidson's branching strategy with the combination of our branching strategy and the gimmick of the redundancy check. The results include some 6-, J- f and 8-gate functions of four variables, among others. 1. A METHOD OF REDUCING THE NUMBER OF REDUNDANT GATES AND CONNECTIONS t IN NON-OPTIMAL NOR NETWORKS 1.1 Elimination of a Redundant Connection Suppose we are given NOR gates p, q, ... , t which are cascaded as shown in Fig. 1.1. Let us call this configuration a gate- chain . F ^^ F *'t V7 Fig. 1.1 A gate-chain consisting of gates p, q, ..., s, t. Let g denote the input under consideration which is connected to gate p. Let f ,'s be the inputs to gate p other than the input g; Let f ,'s be the pi qj inputs to gate q from outside of the gate-chain; and let f 's be the in- tK puts to gate t from outside of the gate chain. Property 1 In the above gate- chain, the input g is redundant with respect to the output of gate t, if and only if g implies the disjunction of the V s ' V s ' •••' and V s ' i - e - (f pl V f P 2 - -% - f q2 - ••' ) (f tl - f t2 - •••> - S (1 ' 1) - + The word 'connection' denotes either an input connection from an ex- ternal variable or an interconnection between two gates, unless other- wise specified. Proof Let $ , , .... and <3>, denote the disjunctions of f . 's, f .'s, .... and f ' s, respectively. The outputs of gates in the gate-chain are given' recursively as : *\ the output of gate p: F the output of gate q: F = F $ > (1.2). q P q / the output of gate t: F , = F <£>. t S "C Assume that the input g is disconnected from gate p. The output of gate p changes from I $ p to 5 p . This change propagates toward gate t. let F f F' , .... and F' denote the outputs of gates in the gate-chain after p q/ ' t ~ the disconnection of the input g from gate p: F' = $ , F' = F'cf> , .... and F' = F ,( &, • P P q P q ' t st The input g is redundant with respect to the output of gate t if F, = F' holds. The relation F. = F! is equivalent to F.@P! = 0. t t t t T, - U By substituting F i and F' $ t for F t and F.J., respectively, we have F (+\F* = $ (F £PiF' ) = $ (F ff)F' ). Continuing a similar sub- t • J t t s w s t s w s stitution process backwards to gate p, we have 0=F 9- F • = •••$ cf> g. t t "C (J p Therefore ••• $ *g =0 or equivalently, $ v v... v$, 3g, pq t & ' H Pq. t- & Q. E. D. Note that even if the above network consists of a single gate p, the property still holds. Suppose an input g is connected to gate p, which in turn feeds gate t through a subnetwork a in which there are two or more paths connecting gate p to gate t (Fig. 1.2). Fig. 1.2 An output g is connected to gate p, which in turn feeds gate t through a subnetwork a. In this case no simple expression such as (l.l) is found as a necessary and sufficient condition for g to be redundant with respect to the output of gate t. Let us introduce a function h* [g] with respect to g and the pair pt of gates p and t: h P*t W = F t * F t (1.3), where F is the output of gate t before disconnecting g from gate p, and F' is the output of gate t after dicormecting g from gate p. Clearly h* [g] = is a necessary and sufficient condition for g to be redundant pt with respect to the output of gate t. Notice that in the case of h* [g] =£ 0, the true vectors of h* [g] are the input vectors for which the output of gate pt t changes when g is disconnected from gate p. For later use, let us derive the following two sufficient conditions for g to be redundant in Fig. 1.2 by using Property 1. The proof is omitted since it is easy to see from the proof of Property 1. Property 2 Take a gate-chain among paths from gate p to gate t in Fig. 1.2. Let the labels p, q, . .., t denote the gates on this gate-chain (Fig. 1.3). a subnetwork a Fig. 1.3 A gate-chain from gate p to gate t in Fig. 1.2. When sy v . . . v- $ =■> g holds, we say the input g is redundant with respect to the output of gate t along this gate-chain , where <£>,, . . . , and 0, are the disjunctions of inputs originating outside of a to gate p, gate q, ..., and gate t, respectively. The input g is redundant with re- spect to the output of gate t if g is redundant (with respect to the out- put of gate t) along every gate-chain connecting gate p to gate t. Property 3 As a special case of Property 2 (Property 3 is mentioned later more often than Property 2), if v $ z> g holds, then g is redundant with re- P t — spect to gate t (Fig. l.k). Fig. l.k If $ v P $, ^ g holds, then g is redundant with respect to gate t, where is the disjunction of inputs (excluding g) to gate p, and $, is the disjunction of inputs to gate t originating outside of the subnetwork a. Let us show two examples* of redundant connections which can be detected in a given network due to Property 3« Example 1 (Triangular interconnection) Suppose we are given a network in which gate i is connected to two ;ates p and t, and gate p has only one output connection which goes to ;ate t (Fig. 1.5). gate p has no other output connections. Fig. 1.5 A triangular interconnection. These are known as a triangular interconnection and a generalized triangular interconnection in [8]. In this configuration, the connection from gate i to gate p is redundant. This is a special case of Property 3 where the subnetwork between gates p and t consists of only a single connection. Notice that a similar prop- erty holds when gate i is replaced by an external input x . Ju Example 2 (Generalized triangular interconnection) Suppose we are given a network in which gate i is connected to a certain subnetwork a, and to one other gate, gate t. Furthermore, all output connections from the subnetwork o go to gate t, but not to other gates (Fig. 1.6). no output connection to other gates. Fig. 1.6 A generalized triangular interconnection. In this configuration, all input connections from gate i to the subnetwork a are redundant. 1.2 Elimination Of A Gate ffy Substituting For Its Output Connections A Disjunction of Other Gate Outputs And/ Or External Variables Suppose we are given a network in which the outputs of two gates are identical. Obviously, if there was no fan-out restriction, we could always substitute for the output connections of one gate the output connections of the other gate and eliminate one gate and all its input connections (Fig. 1.7) ;^© :■ » Eliminate gate i and all inputs to gate i (b) Fig. 1.7 If the output of gate i is identical to the output of gate p in (a), then a better network is possible as shown in (b). Similarly, if a disjunction of certain external variables and/or outputs of other gates is found to be identical to the output of a gate, then we can substitute for the output connections of this gate the sum of those external variables and/or outputs of gates, eliminating one gate (Fig. 1.8). (The total number of connections could increase in this case.) » *©c._ :-^£^U©C. i-'^®) >&-- Eliminate gate i and all inputs to gate i (b) Fig. 1.8 If the output of gate i is identical to the disjunction of the outputs of gate p and gate q in (a), then we can obtain an equivalent network having one less gate as shown in (b). 1.3 Elimination Of A Gate Having A Single Output Connection By Intro - ducing New Connections Suppose gate i has only one output which is connected to gate p as input g. Let denote the disjunction of inputs to gate p, excluding g. Assume that ^ g does not hold. (if $ 3 g holds, we can eliminate the p — ° p — input g as explained in 1.1.) Property k If we have certain external variables and/or outputs of gates which are not fed hy gate p such that their disjunction e satisfies the equality (g e) = 0, then we can eliminate the input g from gate p after con- necting these external variables and/or gate outputs directly to gate p, (Fig. 1.9)> without changing the output function of gate p. Thus one gate (gate i) and all inputs to this gate are eliminated. ■>d£' Eliminate gate i and all inputs to gate i. (a) (b) Fig. 1.9 If we have certain external variables and/or outputs of gates whose disjunction, e, satisfies $ (g e) = in (a), then XT we can eliminate the input g after connecting those external variables and/or gate outputs to gate i, as shown in (b). Proof From <2> (g $ e) =0, we have $ g $ e = 0, which is equivalent to the 10 equality $ g = $ e. Therefore a replacement of g by e does not change the output F = g of gate p. P P Q.E.D. We can easily extend this property as follows. Suppose we are given a net- work in which a gate p, a subnetwork o-,, a gate r, a subnetwork a^, and a gate t are cascaded as shown in Fig. 1.10. The only output connection of gate i is connected to gate p as input g. (EH-^ Fig. 1.10 Gate p, subnetwork a-,, gate r, subnetwork a p , and gate t are cascaded, where the input g to gate p is the only output connection of gate i. Let us define two functions h , and e , as follows: pt rt (i) h , = F , F! pt t t (i.i0, where F is the output of gate t before disconnecting g from gate p, and F' is the output of gate t after disconnecting g from gate p. The function -£ h is the same as (1.3). (For simplicity, [g] is dropped.) Recall that pt the true input vectors of h , are the input vectors for which the output pt of gate t changes after disconnecting the input g from gate i. Define (ii) 'rt F 9 F; (1.5), where the F is the same as the one used for h* , and F 1 ! is the output n of gate t obtained by connecting the constant 1 (one) to gate r. Fig. 1.11 If e satisfies e ^ e => h , , then e can be connected to rt — — pt gate r without changing the output of gate t. P roperty 5 In Fig. 1.11, if we have certain external variables and/or outputs of outside gates such that their disjunction e satisfies (1.6), h , c e c e_, pt - — rt then, without changing the output of gate t, we can eliminate the input g from gate p after connecting these gate outputs and/or external variables (whose disjunction is e) to gate r. Proof Consider a true vector E of e , . Then by (1.5) F. $ F, =0 since e -1 for E. In other words F, = F" . Thus, even if e or e (since e c e ) is connected to gate r, the output of gate r does not change. Therefore it suffices to prove that the disconnection of g from gate i does not change the output of gate t when e is already connected to gate r. For this pur- pose, let us introduce a function h , similar to h , , defined by ' pr ' pt' J * t h = F F , where F is the output of gate r in the original network. pr r r r 12 and F' is the output of gate r when g is disconnected from gate p but e is not yet connected to gate r. Clearly h ^h . Now, assume that e is * * i •* _ connected to gate r. Using h , let us define another function h = h e. pr ' pr pr -*• The true input vectors of the function h are the input vectors for which the output of gate r changes by disconnecting g from gate "p. Thus, the true input vectors of h are the only input vectors for which the output of gate t might change by disconnecting g from gate p. However, the equality h' * h . = holds due to h = h e and the assumption of e ^ h , . In pr pt pr pr — pt other words, if h* = 1, then h\ must be 0. Therefore those changes in ' pr ' pt *t gate r corresponding to the true input vectors of h do not affect the output of gate t. Q. E.D. Notice that e , is the maximal Boolean function which can be connected rt to gate r without changing the output of gate t (Fig. l.U). In the computational procedure which will be presented in 1.6, we im- plement the following special three cases because it would be too time- consuming to implement general Property 5. Cases A and B are special cases of Property 5, and case C is an extension of cases A and B (A proof is omitted since it is easy). Property 5 for the following cases: Case A: r = p (Fig. 1.12 (a) ), Case B: r = t (Fig. 1.12 (b) ), and Case C: a combination of cases A and B, assuming that gate(s) t are the output gate(s) of the entire network. 13 ©r— > Fig. 1.12 (a) Fig. 1.12 (b) Case A: e can replace g, if e satisfies P P -* •* h c e ce 4 . pt - p - pt Case B: e. to gate t can replace g, if e, satisfies h P t - e t - e tt ' Fig. 1.12 (c) Case C: e and e, together replace g, if e p t P and e, satisfy eve, 3 h* , t p t — pt e c e , , and e, c e, , simultaneously, p — pt t — tt It is difficult, if not impossible, to extend Property 5 to the general case where some gate-chains from gate p to gate t do not contain gate r (Fig. 1.13) K ^ Fig. 1.13 Some gate-chains from gate p to gate r do not go through gate r. Ik Alternatively, let us investigate Fig. l.lU as a special case of Fig. 1.13. In Fig l.lU, we attempt to eliminate g "by connecting certain gate out- puts and/or external variables to each gate immediately preceding the out- put gate(s) of the entire network. We call this case Case D . Let gate r , k=l, . . . , a denote such gates immediately preceding the output gate t which are fed by gate p directly or through other gates. Let F denote the r k output of gate r, , k=l, . . . , a, and let 3>. denote the disjunction of inputs to gate t from outside of the subnetwork shown. e (iT^ 1 .'- - Fig. 1.1k Case D: We attempt to eliminate g by connecting e to gate r k for k=l, . . . , ol, respectively. Property 5' If we have a sets of certain gate outputs which are not fed by gate p directly or through other gates, and/or external variables whose dis- junctions e , k = 1, . . . , a, satisfy the following conditions simul- r k taneously; 15 h* c e - f v/ <&. ^ pt — r- - r.. t V 5 e 5 F v * t ) (1.7), 2 *2 5* " r a " r a * then we can eliminate g after connecting e to gate r for all k=l, . . . , a, k respectively. Proof Consider an arbitrary vector a of the function F v <£>, . Then <£> -1 or r fc -c t F =1 holds for a. Thus, even if a is connected to gate r. , the output of r k k gate t does not change since $,=1 or F =0 (Note that gate r is a NOR gate). Xi r, k k Therefore, even if e such that e c F s/ $, is connected to gate r n , the ' r, r, — r, t k 7 k k k output of gate t does not change. Now assume we connect e to gate x , for r k k all k=l, .... a. Since e satisfies h* — e for all k=l, .... 0;, the ' \ Pt - r fc ' ' > disconnection of g from gate p does not affect the output of gate t, as is shown in the proof of Property 5. Q,. E.D. In the computational procedure, we check Case D, when none of the cases A, B, and C lead to the disconnection of g. Furthermore, if case D does not lead to the disconnection of g, we attempt to eliminate g by connecting certain gate outputs (which are not fed by gate p directly or through other gates) and/or external variables to all of gates p, t, and gate r , for all k=l, ..., a, as a combination of Case A, Case B and Case D. We call this case Case E. 16 Fig. 1.15 Case E: We attempt to eliminate g by connecting e , e + , e^ , . . . , e^ , s imult aneous ly . T *' V ' r a l.k Elimination Of Connections By Introducing A New Connection Suppose an input g is connected to a subnetwork a, which in turn feeds gate t, as shown in Fig. I.l6 (a). Fig. 1.16 (a) An input g is connected to a subnetwork a whose output connections go to gate t. Property 6 In Fig. 1.16 (a), if g implies F , the negation of the output F of gate t, then the new network configuration of Fig. 1.16 (c) is equivalent to Fig. 1.16 (a) with respect to the output of gate t. 17 Fig. 1.16 (b) An intermediate stage of the reconfiguration of Fig. 1.16 (a). A duplicate g is added to gate t. Fig. 1.16 (c) A duplicate g is connected to gate t , and the original g is disconnected from the subnetwork a. Proof Consider an arbitrary true vector a of the function of F . Then F =0 for this a. This means that at least one input of NOR gate t assumes the value 1. Therefore even if g is duplicated at the input of gate t (see Fig. l.lo (b)), the output of gate t does not change if g C F,. "0 Uhing Property 3, we know the input g which is connected to the subnetwork a is redundant with respect to gate t. Q,. E.D. In the computational procedure which will be presented in Section 1.6, we implement Property 6 as follows. Consider a subnetwork a of the entire network such that all output connections from a go to only one gate. Let gate t denote this gate. Assume that a has an input g for Ifl which ~F 3 S holds, where F is the output of gate t (Fig. 1.17 (a)). Furthermore, let g., i=l, . .., a, denote the inputs to a, if any, such that each g. implies g, i.e., g ^g.. Let h , j=l, ..., (3 denote the inputs to o other than g. (Fig. 1.17 (a)). The outputs of the network. (a) A subnetwork a of the entire network such that all output connections from a go to only one gate t, and that a has an input g for which F , ^ g holds, 7»The output F, (b) The part of the entire network under consideration where F = g, and g 3 g for i=l, . . . , a hold. Fig. 1.17 Eliminating connections using Property 6. 19 g and all g. 's are disconnected. subnetwork o (c) This configuration is derived from (b) by (i) connecting a duplicate of g to gate t and (ii) disconnecting g and all g.'s from a. The outputs of the networks (d) The entire network derived by replacing (b) by (c). Fig. 1.17 (cont'd) Eliminating connections using Property 6. 20 In the above configuration (b), first connect a duplicate of g to gate t, and then disconnect g from cr. Since g^g. holds for i=l, . .., a, we disconnect all g.'s from a, by using Property 3. Fig. 1.17 (c) shows this transformation, and Fig. 1.17 (d) is the resulting entire network. Clearly Fig. 1.17 (d) has cc-1 fewer connections than the original network of Fig. 1.17 (a). Notice that when a has no g.'s for which g => g. holds, this transformation does not yield a reduction in the number of connections. But we will derive a new network of Fig. 1.17 (d) of the same number of connections, even in this case, because the new network has a different configuration, so that it can be used for further redundancy checking. 1. 5 * A Transformation Which May Allow The Elimination Of Some Connections Assume we have a network configuration as shown in Fig. 1.18 (a), where (i) the outputs of the subnetwork o go to two different gates r and t, (ii) the output of gate r goes only to the third gate s, (iii) the output of gate s goes only to gate t, (iv) gate s has one or more inputs g , g p , ..., g other than the input from gate r, and (v) the disjunction of all g.'s implies the output F of gate t, i.e., F t f gi v g 2 ^g^ . * We do not implement this checking scheme in our current computational procedure which will be presented in Section 1.6, because this case appears to occur only rarely judging from our preliminary experiments with the branch- and-bound algorithm. 21 The output of gate t. Fig. 1.18 (a) A network configuration which satisfies the assumptions (i) ~ (v). Property 7 Given Fig. 1.18 (a), we can obtain another network configuration Fig. 1.18 (c) which is equivalent to Fig. 1.18 (a) with respect to the output of gate t. Fig. 1.18 (b) An intermediate stage of the reconfiguration of Fig. 1.18 (a) 22 Fig. 1.18 (c) A network configuration equivalent to Fig. 1.18 (a), where (i) gate r and gate s are eliminated, (ii) the output connections from a to gate r are connected to gate t , (iii) two new gates p and q are connected in series following gate r, and (iv) g , . .., g are connected to gate p. Proof First, let us make a double negation of the output of gate t by connecting two single input NOR gates p and q in series after gate t. Since the out- put, F , of gate p is identical to F , F is implied by g. v .. v g due to the assumption (v). Therefore we can connect g^ , ..., g to gate p. This results in Fig. 1.18 (b). Using Property 3 with respect to gate p, we can eliminate all g. 's which are connected to gate s. After an elimination of all g.'s from gate s, gate s has only one input connection and one output connection. Therefore we can eliminate gate r and gate s, resulting in Fig. 1.18 (c). Q.E.D. 23 Fig. 1.19* shows a simple example of the transformation of Fig. 1.18. (After applying to Fig. 1.19 (a) the transformation of Fig. 1.18, we eliminate the input g to gate i by using Property 3> obtaining Fig. 1.19 (b)) fe^<£> F=F. h >^ g "©~ F=I (a) The original network realizing F. The dotted line indicates the subnetwork o for this case. (b) A new network realizing the same F. The network has one less connection than the original network (a). Fig. 1.19 An example of reconfiguration explained in Fig. 1.18. This reconfiguration was first found by J. Culliney. We generalized his finding later, resulting in Property 7. 2k 1.6 A Computational Procedure To Attempt To Improve Redundant Networks By Transformations Using the network transformations explained in Sections 1.1 through l.k, we implement a computational procedure to generate an improved net- work from a given (non- optimal*) network. For the implementation of a practical computational procedure, we have to compromise between the complexity and the power of the procedure. (An excessively complicated procedure may increase the total computation time of the algorithm, even while lowering the cost ceiling substantially by finding a much improved network. ) Thus, instead of incorporating all of the ideas in the previous sections, only simple cases are incorporated. The principle of the im- plementation is: (i) to attempt to eliminate redundant gates first, (ii) then to attempt to eliminate redundant connections. Let us first present the segments of the computational procedure which we implemented. Part I (Replacement of the output of a gate with a disjunction of other gate outputs and/or external variables.): Select a gate p which is not an output gate of the network. Let gates t f , t", ..., denote the gates to which gate p is connected. If there are certain external variables and/or outputs of gates which are not fed (di- rectly or through other gates) by gate p such that their disjunction is * When a given network is optimal, some transformations may yield other optmal networks. 25 identical to the output of gate p, then make new connections from these external variables and/or gates to gates t», t", . .., and remove the existing connections from gate p to gates t*, t", . .., along with all in- put connections of gate p. By this transformation, we eliminate one gate, i.e., gate p (although the number of connections might be increased). Part II (Elimination of a gate having a single output connection) Select a gate i which is not an output gate, and which has only one output connection. Let gate p denote the gate to which gate i is connected. Check whether or not h = (h is defined by (1. *0) for all gates t which are the output gates of the network. If the connection _is redundant, fi..e., h = 0) then remove the connection. By this transformation, we eliminate pt gate i and its inputs and output. If the connection is not redundant (i.e, h =£ for some t), then by applying Properties 5 or 5' we determine if pt there are any external variables and/or outputs of gates which are not fed by gate p, such that by introducing new connections from these ex- ternal variables and/or gates, the connection of gate i to gate p becomes redundant . As we explained in Section 1.3, the detailed checking procedure is: First check Case A (Fig. 1.12 (a) ). If Case A does not eliminate the gate having a single output connection, then check Case B (Fig. 1.12 (b)), Case C (Fig. 1.12 (c)), Case D (Fig. 1.1*0, and Case E (Fig. 1.15), successively. Part III- a (Elimination of a redundant connection of a gate) Select a gate i, which is not an output gate and has two or more output connections, or which is an output gate having output connections. 26 Determine 'whether or not an output connection from gate i to another gate, p, is redundant with respect to the output (s) of the entire network; this is done by checking whether or not h =0 (h [g] is defined by (1.3)), where g is the output connection under consideration from gate i to gate .v. p, and t denotes the output gate(s) of the entire network. If h [g] = pt for all output gates t, then remove the connection g. Part Ill-b (Elimination of a redundant connection of an external variable) Select an external variable x,. Determine whether or not the connection of x , to a certain gate is redundant with respect to the output (s) of the * r -\ entire network; this is done by checking whether or not h LgJ = 0, pt where g is the connection (of x,) under consideration to gate p, and t denotes the output gate(s) of the entire network. If h [g] = for all pt output gates t, then eliminate the connection g. Part IV ( Elimination of redundant connections by the introduction of a new connection) Select a portion of the entire network which consists of gate t and a subnetwork a, where the outputs from a go only to gate t (Fig. 1.17(a)). When an input g to a satisfies F => g, where F is the output of gate t, derive a new network as shown in Fig. 1.17. By this reconfiguration we eliminate tt-1 connections. (As noted, O-l could be 0.) Combining Parts I through IV, we complete the computational procedure for generating an improved network from the given (non-optimal) network. 27 2. THE BRANCHING STRATEGY"!" 2.1 Definitions Before presenting the branching strategy, we present the necessary definitions. The problem is to find NOR networks having minimal cost for given switching functions, where the cost C of a network is defined by Ax R+Bx I in which R is the number of gates, I is the number of inputs to gates, and A and B are arbitrary non-negative weights. Suppose the problem is to obtain the optimal networks each of which realizes the given m output functions f., i=l, . . . , m, of n variables, simultaneously. The initial solution is defined by a set of m gates; each gate i is assigned the output function f., i=l, ..., m. We represent the output of a gate with a 2 -tuple of 0-1 variables ]r, as (P , ..., P ), where P corresponds to the j-th input vector for j=0, ..., 2 . Notice, however, that the algorithm will not imme- diately assign a definite value or 1 to all the P^'s of a gate, so a symbol * is used to denote an unassigned value of P^ . The output of 2 n ~l gate i, i=l, ..., m, in the initial solution is (f., ..., f. ). Let us consider two gates, i and k, in a NOR network, where gate i 2 n 1 2 n 1 is connected to gate k. Let (P., ..., P. ) and (P. , ..., P ) denote XX ri K. the outputs of gate i and gate k, respectively. Because the gates per- form a NOR operation, the outputs of the gates must satisfy the following condition; f The concepts used for making our branching strategy are Davidson's [1, 2]. The details of this branching strategy are discussed in [3]. 23 P? = for all d such that F? = 1 F? = for all j such that P? = 1 i k A similar condition must hold for the output of each gate in a NOR network with respect to each of the connected external variables, x.. When the output of a gate in a NOR network satisfies the above con- dition with respect to all immediately preceding/ succeeding gates and all connected variables, we call this output a feasible assignment . There can be unas signed components in a feasible assignment. An intermediate solution is defined as a network of R gates, R > m, where the outputs of the first m gates are identical to those assigned in the initial solution; the outputs of other gates (gate i for i=m+l, ... , R), if any, are completely or incompletely specified; and the out- put of each gate i, i=l, ..., R, is a feasible assignment. Consider a O-component, P, , in gate k of an intermediate solution. If gate k has at least one input (from an external variable or another gate) whose j n -th component is 1, then P is said to be covered . J Otherwise, P, is said to be uncovered. ' k Our algorithm to derive an optimal network generates from the initial solution an intermediate solution in which all the O-components of all gates are covered. To facilitate our discussion, we introduce the con- cept of possible covers for an uncovered component: J 'o A possible cover for an uncovered component P, = in gate k is an external variable or a gate which satisfies one of the following conditions: 29 (i) An external variable, x. , which is not yet connected to gate k, = 1. (2.1) ^0 and which has x„ =1, and x^ =0 for all j such that P = 1. °0 (ii) A gate i which is connected to gate k, and P. = * (unassigned). (2.2) (iii) A gate i which is not yet connected to gate k, whose connection to gate k will not form any loops, which has P. = 1 or *, and P? = or * for all j such that P? = 1. (2.3) 1 K. (iv) A gate which is not yet incorporated into the intermediate solution. (This is called a new gate . ) The output components of this gate are all * (unassigned), and this gate is numbered R-fl, when the given intermediate solution has R gates. (2.k) Consider a possible cover for an uncovered component P = in gate k K of the given intermediate solution S. We cover P with the possible cover by the following implement at ion consisting of three steps: (Step l) If the possible cover is not yet connected to gate k, then connect it to gate k. (Step 2) If the j n -th component of the possible cover is not yet assigned, then assign the value 1 to it. (Step 3) Assign the value to unassigned components wherever such an assignment is necessary to make each output assignment feasible. The resulting intermediate solution is called the augmented intermediate solution of the given intermediate solution S. Starting from the initial solution, if we repeatedly cover uncovered components in intermediate solutions, we may eventually obtain an inter- mediate solution in which the 0- components in all of the gates are covered. 30 We call such an intermediate solution a feasible solution . Optimal solutions are feasible solutions having the least cost among all feasible solutions of a given problem. To enumerate all feasible solutions in a systematic way, we introduce a set of two rules, namely, the selection criterion of uncovered components (SCUC) and the implementation priority of possible covers (IPPC ) as defined below. The SCUC is the criterion under which an uncovered component, P7=0, XL is selected to be covered from an intermediate solution. The IPPC is the criterion under which the order of implementation is determined among the possible covers of a selected uncovered com- ponent. We call the heuristics of the SCUC and the IPPC the branching strategy . In order to obtain a 'good' branching strategy, let us introduce more de- finitions in the following. Examine a component P = of gate k. If K P. = is covered, then P n = is said to be of type COV. For an un- it k — — J covered component, P = 0, of gate k, types of possible covers are defined as follows . G-ate i which satisfies (2.2) is said to be of type G* . External variable x„ which satisfies (2.1) is said to be of type VC* . Gate i which satisfies (2.3) is assigned one of the following four types according to the values of its components: Type GC*0 , if P. = 1, and F? = for all j such that pJ = 1; Type GC*0 *, 1, and there is at least one ,j such that F: = * for Pr = 1; i l k Type G*C*0 , if P.° = *, and F? = for all j such that pj = 1; Type G*C*0 J i i if P = *, and there is at least one j such that P.=* for Pr=l. l ik 31 A new gate of definition (2.4) is said to be of Type NWG. Among the types introduced above, we define a desirability order, and then we define the types of uncovered components, and the types of gates, by means of the desirability order. The desirability order of types is the order defined by GOV - G* - VC* - GC*0 - GC*0* - G*C*0 - G*C*0* - NWG. (COV is the most desired) The type of an uncovered component is defined to be the most desirable type among the types of its possible covers. The type of a gate is defined as the least desirable type among all the 0- components in the gate. 2.2 Branching Strategy Based on the concepts defined in Section 2.1, the branching strategy, i.e., the selection criterion of uncovered components (SCUC) and the im- plementation priority of possible covers (IPPC), is as follows. If the current intermediate solution contains type NWG components, we employ Davidson's special scheme called 'Remove NF Vectors'*, which generates from the original intermediate solution with type NWG components another intermediate solution in which no type NWG components exist. This scheme is to choose certain type NWG components to be covered in order to maximize the number of new gates which must be introduced into the network. This results in the preclusion of some equivalent networks with permuted gate labels. For details, refer to [2]. Therefore, we This is explained in [2], as 'Special Treatment of Type NWG Components. 32 assume in the following that the current intermediate solution does not have uncovered components of type N¥G. The SCUC If the current intermediate solution has uncovered components of types VC* or less desirable, then select an uncovered component with the fewest possible covers, among those whose types are VC* or less desirable. If there are two or more uncovered components which have the same least num- ber of possible covers, then select one whose type is the least desirable. If the current intermediate solution has only uncovered components of type G*, then select an uncovered component (of type G*) which has the fewest possible covers. The IPPC Implement the possible covers of the selected uncovered component according to the following order G* - VC* - {GC*0, GC*0*, G*C*0, G*C*0*}+- NWG. (The possible cover(s) of type G* are assigned the highest priority.) The motivation of establishing this set of the SCUC and IPPC is as follows : An uncovered component which has a smaller number of possible covers is 'hard to cover' in a sense, since if we postpone a covering of this uncovered component until later, this uncovered component will most likely lose all possible covers except a new gate. Accordingly, we might miss + The possible covers of types GC*0, GC*0*, G*C*0, and G*C*0* are assigned an equal priority. 33 good networks in the early stages of the computation. Therefore, it seems a good rule to first cover an uncovered component which has the fewest possible covers in a given intermediate solution. However, if we take simply "the fewest possible covers" as the main criterion of selecting uncovered components without distinguishing type G* components from un- covered components, type G* components could be selected too frequently at an early stage of the branching steps. Concentration on covering type G* components may likely result in the following situation: one gate which is introduced as a new gate to cover a certain component of another gate realizes the negation of the latter gate. With the repetition of this process, we may create an indefinite number of inverters in series without realizing a feasible network. In order to avoid such a hazard, we select one uncovered component with the fewest possible covers among those whose types are VC* or less desirable. When the given intermediate solution has only uncovered components of type G*, we select one with the fewest possible covers. Once an uncovered component is selected, we cover this uncovered component with each of its possible covers, generating the corresponding augmented intermediate solutions. We have to order these possible covers in order to generate 'good' augmented intermediate solution first, i.e., one which is as close to a feasible solution as possible. The desirability order defined in Section 2.1 seems to be a good rule for this purpose. 3h 2.3 Differences of Our Branching Strategy From Davidson's t The branching strategy presented in Section 2.2 is different from Davidson's in the following three aspects. (i) Uncovered components of type 1-COV. Davidson classifies uncovered components which have type G* possible covers into two categories, namely, uncovered components of type 1-COV, J 'o and uncovered components of type G*. An uncovered component P of gate J o k is assigned type 1-C0V (a) if P has at least one possible cover gate i of type Q% and (b) if the j n -th component of every gate immediately pre- ceding gate i is 0. An uncovered component which has type G* possible covers none of which satisfy condition (b) above is assigned type G*. J J Type 1-COV P has the important property that covering of P with such K. K. a gate i does not introduce any uncovered components into the augmented intermediate solution (Fig. 2.1). Accordingly, when an intermediate solution contains only uncovered components whose types are 1-COV, this intermediate solution has already realized the given output function(s). Because of this property of type 1-COV, type 1-COV uncovered components need not be covered explicitly. For this reason, the SCUC is applied only to the uncovered components whose types are not 1-COV, in Davidson's branching strategy. -\- Davidson's strategy discussed in this paragraph is the version claimed by him to be the best among a total of eight different versions of his strategy. For the details of his strategy, see [1, 2]. 35 gate k gate P. ( o ( gate P„ ) ( d Fig. 2.1 An example of uncovered component P, of type 1-COV. P can be covered by gate l by setting P = 1, where setting P. =1 does K 1 not introduce any uncovered components into the augmented intermediate solution. In our branching strategy, we do not classify uncovered components having type G* possible covers into two categories as Davidson does. Thus, programming efforts and computation time which are spent on this classi- fication in Davidson's approach are completely eliminated. (ii) The selection criterion of uncovered components (SCUC). Davidson utilizes the desirability order as the main concept of the SCUC. In order to improve the algorithm, he concentrates on ways of distinguishing uncovered components, by introducing several finer classi- fications of types of their possible covers. One of the most important concepts to obtain these finer classifications is the classification of 36 of type VC* possible covers into "bad' VC* possible covers, and 'good' VC* possible covers. A bad VC* possible cover for an uncovered component P =0 • K. of gate k is an external variable x -whose covering of P (i.e., connecting x to gate k) results in a change of some type G* components in the immediatel succeeding gates to a less desirable type (Fig. 2.2). A possible cover of type VC* which is not 'bad' is called a 'good' VC* possible cover. vr J o J i p p s s gate s (J (1 ) J Ji P P, k gate k i ( * ) t J 3 ± x x • «, ( 1 1 ) Fig. 2.2 An example of a 'bad' VC* possible cover X. . Suppose x, is a possible cover (of type VC*) for P . Before x« is connected to gate k, h P in gate s is of type G*. However, if x, is connected to gate k, the type of P is changed to a less desirable type because P, becomes 0. Based on this concept and several other properties of possible covers of types G* and VC*, he classified uncovered components of the original types G* and VC* into seven types: 37 g*/d, vc*g*/ b ' > g*/c, vc*g*/ a ', g */ a ', g*/b', vc * a Ety combining the above classification of uncovered components, he obtains 'the selection order 1 as defined by: g*/d-vc*g*/ b ' -g*/c' -vc*g*/a' -g*/ a ' -g*/ b ' -vc*/a-g*c*o*-g*c*o-gc*o*-gc*o, where G*/D is the most desirable. (Definitions of uncovered components of types GC*0, GC*0*, G*C*0, and G*C*0* remain the same as ours.) This is the main part of his SCUC. According to this order, first he chooses a gate which contains uncovered components of the least desirable type, (if there are two or more such gates, he chooses the one with the smallest gate number in the case where the least desirable type is one of GC*0, GC*0*, G*C*0 or G*C*0*, otherwise he chooses the one with the largest gate number. ) If this gate has only one uncovered component of the least desirable type, then it must be chosen; but if this gate has two or more uncovered components of the same least desirable type, then he selects one which has the fewest possible covers. In contrast to his SCUC, our SCUC employs the 'fewest possible covers' as the main criterion. By this criterion we select an uncovered component which has the fewest possible covers throughout the entire network. When a tie occurs, we apply 'the desirability order' to break it- (iii) The implementation priority of possible covers (IPPC). Suppose we are given the possible covers of an uncovered component which is selectee from the current intermediate solution. Davidson determines the implementation priority of possible covers by using the lower bounds, C's, of the costs corresponding to these possible covers, 38 where C for each possible cover is calculated as follows: Li Let S denote the current intermediate solution, and let P denote the uncovered component which is selected according to the SCUC. Take a possible cover of P, and implement it, generating the augmented intermediate solution S'. If S' has type NWG components, then introduce appropriate new gates according to the scheme of 'Special treatment of type NWG components' described in Section 2.2. Rename the resulting intermediate solution as S' . Then calculate C T using the formula C = A X f the number of gates in S'} + BX ' the number of connections in S'} + b X f the number of gates whose types are VC* or less desirable} . If the possible cover under consideration is of type VC*, reduce C by the amount of A + B, i.e., the modified C = the original C - (A + B).1" In our version, the implementation priority of possible covers is determined by a simplified desirability order, G* - VC* - ( GC*0, GC*0*, G*C*0, G*C*0*} - NWG In summary, the difference between Davidson's branching strategy and our may be illustrated schematically in the following way. The entire searching + This treatment has the purpose of assigning a higher priority to possible covers of type VC* than the original C T indicates. 39 process of the branch- and- bound algorithm is represented by a tree (called a search tree) in which the root node corresponds to the initial solution of the problem, and non-terminal nodes and terminal nodes correspond to intermediate solutions and feasible solutions, respectively. Davidson's branching strategy is based on minimizing the length of paths from the root node to terminal nodes. Therefore, the search tree corresponding to his strategy is shallow in depth, but it may become broad in width. On the other hand, our branching strategy is based on minimizing the number of of branches originating from each node. Therefore the entire search tree corresponding to our strategy is generally thinner in width. i+0 3. COMPUTATIONAL RESULTS The entire algorithm [3] was coded by incorporating the redundancy- check and the branching strategy discussed in the previous sections. This computer program which is the modification of Davidson's algorithm with our branching strategy and the redundancy check procedure is called ILLOD-(NOR-B) [k]. In this section, we compare the above algorithm with Davidson's by solving problems of some single output functions and multiple output functions. Since his program was written in the CDC l60k Assembler, we first implemented a FORTRAN program according to his strategy. We call this FORTRAN program the FORTRAN equivalent of Davidson's program . Column (a) of Table 3>1 shows part of his results taken from [l], and column (b) shows the corresponding results by the FORTRAN equivalent of Davidson's program. We note that both programs are not completely identical as the discrepancy in the number of backtracks indicates. But such a discrepancy seems unavoidable because of the following: (i) Some of seven finely classified types G*/D, VC*G*/ B ' > G*/C, VC*G*/ A '> G*/A' 7 G*/B', VC*/A are not clearly defined in his text [1]. We had to guess the details to give a consistent definition for them. (ii) In order to break ties in the SCUC as well as in the IPPC, we needed more detailed rules which are not written in the text. An example is the case where a gate has two or more uncovered components whose types are the least desirable and which have the fewest possible covers. (in the FORTRAN program, we choose one which is introduced most recently into the gate, if this case happens.) In the rest of this section, we refer to this FORTRAN equivalent of Davidson's program, instead of Davidson's CDC 160^ program. in. O CQ O CQ 4) « O CQ 0) M ^-*^-^ w g w g w s "g CO LTN CO NO LTN OJ NO ON Kvo H t~co °0 _,. NO J- . OJ NO ***> W^ . a\ • H . . t- .-* o o M CO H ro H H -— sno rn H D — PO "— ' 1 R g H H aj aj -P -P R O O H ^— -P -P 1 M V CO O CQ O CQ O CQ XI o a) ;*: W a W )1A . J- . OJ • r— •-* C-O^ H H o -* OJ H n c-\ OO CM ^-> i « jlA H M O t— "S ■ g w s M g aj O G-\ t— ON CO m co o . LTN NO -* > U ai O CO -* • t— CO NO • CO ^oJ d fin roO d OJ H CT* W 3 ltn H OJ m- t) S ^ CO) o s o *h ra lis u 1-1 --.,-^ O ~ O H • CO OJ O CO vo d o en • J- m • OJ H X > O aj O ON hfl / -P IX -P n O +3 O X! <-l H rl II to • <; ii M . h R NO to p XJ IX -H !-. +J +> a) W X, fU ^~~ O ^ C aj aj H T3 -p R aj W -H «! a) 4CH o R to O •H |X a d ROM S3 Sh t) •H X a! a) 0) a) -H !h . aj H O fi C H ai |X H -S aj • Xi +> • • OJ > , O OJ ? H to a) t~- • •H > aj • • H o OJ Eh to to -P > OJ +3 M H CO) ro / E o to o X II Pi II o c , h ix ii H • R 3 OJ ai ^^ ^ aj C / l> C to O R . ONO R -r) C R XI O / H 63* W J- > < w m +3 o WO X < B to / - R ^t -P SHOO / ^ Er b: ^ M c O rn MR . O R a) H J R O hD /_ l M M HI M M H H > k2 O CO CU id w g r- o -3- . ro H O CO cu id o t— ON . OJ CO r- H O CO cu id W B o O -H- H O CO w & ro CJNVO • OJ NO H O CO cu id M g ON o -* . LTN CM O CO CU id ro On • f- no ro o CO CU 53 w g CO CO -3- . ro o O CO a) id w e c— O ON . CM OJ t— H O CO cu ^ NO _d" 6 O CO cu id ra B CM CO r— . CM NO H O CO cu id M g ro NO -3- o co CU id °e r- H J- • o ON h- O CO -P O 13 3 3 LTN C H -p a) O CU Ch CO C O H ii H--^ a) w < d « C g cu O M -H -p •• -rl O +> aj O -P Cm ft bD 1 O O p C to CO s; js cu cu < CU CO '"- T> cd CO ■a • j= c cd H O C -H - O-P -H -H O 03 .p cu 1 s c CU TJ H C C C O o O cd to o X k3 Notes for preceding Table 3«1» Note 1. All problems are single optimum problems, i.e., the program searches for only one optimal network for each problem. No fan- in or fan-out restriction is imposed. Note 2. A = 100 and B = 1 means to minimize the number of gates primarily, then to minimize the number of con- nections secondarily, and A = 1 and B = means to minimize the number of gates only. Note 3- Columns (b), (c), (d) and (e) are the results for the problems for dual functions of Davidson's, since these programs are for NOR networks, while (a) Davidson's program is for NAND networks. It should be worthwhile also to notice the difference of the languages used for both programs. For the logical design program by the branch-and- bound algorithm, coding by machine instructions seems to have an apparent advantage over the use of FORTRAN in terms of the efficiency of the pro- gram. For example, by using machine instructions, the output of each gate can be stored in a few (machine) words in which each bit represents the output component for an input vector. Access to the output of a gate during the computation (this is one of the operations most frequently used in the program) can be performed by a single instruction. However, in the FORTRAN program, each output component of a gate occupies one word. Therefore, the kh equivalent operation is completed by a repeated access to the set of words. (The more the external variables of the problem, the more the difference of the access method may affect the efficiency of the program. ) Before running ILLOD-(NOR-B), we experimented two more programs, the one is the FORTRAN equivalent of Davidson's program with the redundancy check procedure, and ILLOD-(NOR-B) without the redundancy check procedure. Columns (c) and (d) show the results by these two programs. Finally, we ran ILLOD-(NOR-B). The result is shown in column (e). Investigating the results shown in columns (b), (c), (d) and (e), let us discuss the difference of the programs in the two aspects, i.e., (i) the difference in the branching strategy, and (ii) the gimmick of the redundancy check. (i) In the first aspect, we compare the computation time by the FORTRAN equivalent of Davidson's program (column (b) ) with the one by ILLOD-(NOR-B) without the redundancy check procedure (column (d)). The result is that the latter program is faster than the former one, except for one problem (Problem III). The improvement would be greater for more gates. The number of backtracks counts generally more by the latter program than by the former one. This is due to the difference in counting backtracks. We must reduce the figures by the latter program by about ^0% if we want to compare them with the corresponding figures by the former program for the following reason. In the ILLOD-(NOR-B) without the redundancy check procedure, the cost lower bound C corresponding to a possible cover is obtained from the cost estimate of the current intermediate solution plus the cost estimate of possible cover under consideration. ^5 On the other hand, in Davidson's program, the cost lower bound C is obtained from the cost estimate of the augmented inter- Jj mediate solution corresponding to the possible cover under con- sideration. Clearly C T appears to be not less than C if both Jj possible covers are identical. In both cases, by the backtrack procedure, we search for an unimplemented possible cover whose cost lower bound does not exceed the cost ceiling C. When we encounter such a possible cover, we increment the number of backtracks by 1. Due to the above difference of the value of the cost lower bound, the number of backtracks by ILLOD-(NOR-B) should be not smaller than by Davidson's program, assuming that the search trees by both programs are identical. If we want to make the counting scheme of ILLOD-(NOR-B) identical to Davidson's, we count 1 only when we obtain a new augmented intermediate solution whose estimated cost does not exceed C. In ILLOD-(NOR-B) even if we count 1, the corresponding augmented solution may exceed the C and be immediately discarded. By this change of the counting scheme, the average number of backtracks for sample problems appears about ^0% fewer, according to the experiment. (The way of counting backtracks has nothing to do with the efficiency of the program at all. ) (ii) In the second aspect, i.e., the effect of the redundancy check on the improvement of computation speed, we compare the results in columns (b) and (c), and also the results in columns (d) and (e). For some problems, the gimmick of the redundancy 1+6 check reduces the computation time, but for some other problems, this gimmick does not. Clearly, if the first feasible solution happens to be optimal, this gimmick does not reduce the com- putation time, but rather adds a slight amount of running time spent for redundancy check; or, even if the first feasible solution is not optimal, this gimmick will not reduce the com- putation time if the total amount of time for the problem is very small. For many of the above test problems, these situations happen, thus the use of the redundancy check procedure is not well justified from the above results. In order to experiment the algorithms further, we took some 6-gate and 7-gate functions of four variables. Table 3*2 is the statistics of these functions, by using the above four FORTRAN programs. For 6-gate functions of four variables, ILLOD-(NOR-B) is slightly worse than ILLOD-(NOR-B) without the redundancy check procedure, even though the number of back- tracks is reduced by about 10$. But, for 7-gate functions of four variables, the redundancy check procedure reduces about 20$ of computation time from 20.33 seconds to 16.37 seconds. Thus, the gimmick of the redundancy check seems to improve the computation speed for those problems which require many gates. Tables 3.3 ~ 3.6 are the detailed statistics by the four FORTRAN programs, showing the computation time vs. the number of true vectors. These figures are plotted in Fig, 3*1 for 6-gate functions, and Fig. 3«2 for 7-gate functions. One thing should be worthwhile to mention about the statistics: hi The number of functions experimented are 83 for 6-gate functions, and k6 for 7-gate functions. But the FORTRAN equivalent of Davidson's program did not terminate the computation for one function among k6 7-gate functions in 700 seconds. (The best feasible solution found so far still contains 9-gates and 18 connections.) In order to take the average of computation times, therefore, we excluded this function, which resulted in the statistics of ^5 7-gate functions. kQ co a o •H -P O a CU H I O o k 9 — LTN H H OJ OO d o a o OO LT\ _h- * VO • H CM H LTN H OJ H OO OJ CVJ Lf\ on o oo OO • OO • H CVJ LTN t— E- -* • r- H OJ OO OJ VO c- oo oo CVJ o 0- • ir\ • H H cvi OJ -tf OJ o -=J- vo o t- oo a CVJ VO CD H LT\ H -=J- vo LTN CVJ C3N o -ct- LTN vo H Rl CO • o CVJ • d -=h • -=r H H CVJ -=f oo H ON H VO l>- ON OO ON • OJ On OO • VO -d- • o H oo LTN ON H OJ oo o oo OO LTN LTN OO • OO • VO -=t- • VO VO -=f VO o LT\ 00 LTN CVJ LTN o OO • LTN C- LA OO -=t- -=T VO LTN ON lt\ l>- -1- LT\ CVJ • -=f vo H • oo -4- D— H t— 3 oo VO OO LTN CO H t- t— o • LTN • o * -cJ- ON CO oo oo H oo H OO OJ -=h l>- O OO LT\ • OO • _J- • OO -=J- OO ro VO Pi OO o OJ OO CVJ VO LT\ on -=J- OO . OO • • c- CVJ CVJ CVJ 3 ON VO 00 O H TO ON C) O CO H CU CVJ W VO (1) OJ H • CO H § CVJ OO 03 VO H w h Sh >H O 0) CU co CU cu co rQ M -P o 1 s3 1 H cu O -P 3 (A o -P 3 a5 <+H CO o S3 rH Ch co o S3 Sh o O S3 c -P O S3 S3 •p cu O 3 J> <+H &H 3 !> CU •p S3 O •H +3 & OO oo m EH 03 CU H ■3 •H rH «3 l> rH o «)H - LTV S3 a3 CO S3 O •H ■P O CU ■s bO O I o vo rH bD O Sh ft S3 O 03 •H -p d O Sh S3 <*h •H T3 s 03 S cu 3 rH rH bO 03 O -H rH & ft-P co t3 - CU S3 T3 O 3 03 H -73 O •H . J> CU O m O CU H !> •H CO aj ^5 P &o cu o Ch i>- o fe s s 3 ■P Ph *h S3 Eh CU K -v H O rH a5 Ph 3 !> o •H CU <^H 3, ^3 D 1 -P «H CU o & -p 50 H LT\ CO -dr H H d ro o c— LTN -d" H c- • H C\J H LTN H CM H CO CM -d" LTN OO O en OO • -d- • H CVI LT\ t- -dr 00 CM CO H CM L(A CM -d- CO CM o CO • LTN • H H CM -=f- • o CM -d" H CM ITN OO CM O -d- O H H CM VO -^ -d" oo ON 6 -* vo o H H CM -d- CO OO O O O H OJ VO • CO • H t- -d" -d- CM oo OO ON r-\ rA OO VO CO 00 CO o ■ t- • ON H -=f -d- LTN -d" ON H o CM OO CO CO LTN CO OO VO CM VO _d- d LTN d t- t- ON CO H LTN -d" • -d- OO • t- LTN • CM • ON OO -d- O LTN -d- -d- ON o CM oo s -d" . -d- • VO • H -d- • LTN t- 3 t- CM -d- UA UN LT\ oo -d" . * CM > Lf\ CO CO VO CM OO -d" H LTN OO CM CO -d- OO CM • -d" • E— VO _d" oo • ON -d- • ON VO O H VO H H o O CM H O OO CM aj ON OO CM oo -d- -d- 00 VO o o O 02 H o LT\ CO OO CD • W O 0) • W cm H • 03 Ed s CM • w OO EH H CM oo m OO vo H W / ^ / Ph Ph o / CD cd w 0) CD M -f- 3 / i £ rQ ^ 1 B ,a M Ch o / e -h s ° g •H S o O (1) / O -P 3 co O +3 3 d > / <+H W o £ ?H <+h W o C Ph Ph O C a -P o id S3 CD S CD 0) / O 0) o CD M o CD O ,Q 3 / ^ -H CO -p ho o Ph -H bo •H $ % !h / CD -P co cd -P co +? 3 -p / & O *H CO ?H r^ ,a o %^ co Ph ,Q s e a 0) -p CD s c 3 !> 3 > (m / ^J a3 i ^ / §P •H +3 CU p>/ •B 9, u cd ^ £> ,Q o ?H cd ^ rQ -9 / § G cu P s a CU S. / w 3 Jj > d f> ch 3 3 > :=! t> ai 5*5 SH < P < O S t>0 / P a3 •H CI) *H s e -p ^ • <4H P( cu O O 3 £h -a Q) ch a; 9 O o O R CO ?H c O ft • •H r^ CO -p C) !> o 0) cu *J o d <£-i •H >i p> cu o -P ti C a3 cci O bn Ti •H i ti P> t- d cd t3 -P LT\ cu d -d- iH ft § >o a> O a ^J o cd +3 UA oo ^ m <; EH ON -d" ft CO oo I pq < EH ti •H P> O ti P> O cS cu cu 52 1 OJ o H H o CO OJ OO LT\ OO LTA ^t- • c- « -4- • o C— H OJ o OJ CM H H oo Lf\ OO LTN -=h • o . OO • OJ • CI H OJ H -rj- -=f -3- OO OJ J- CM vA oo E— • -=h • OJ o • VO H H H H c- -4- t— LTN -3" -* LTN c*- oo t- • 00 • 3 • H • o\ OJ H vo -d- CO t- -d- J- oo VO oo O • VO • O OJ • LT\ • vo H H OJ CO -=h VO oo / O +3 B cd o -P 3 a3

/

3 >

3 !>

cd u cp 3 o o CH m a; cp rQ o g CO a C o • •H to -P !> O a CD ,2 •H +3 CD -P fl cd o bn •H i -P r— flj P> LT\ a -d- ft 6 Tl o id a cd vo oo w r^ < EH 53 -* •- FORTRAN equivalent of Davidson's program. -X- - - -X- FORTRAN equivalent of Davidson's program with the redundancy check procedure. -O O- ILLOD-(NOR-B) without the redundancy check procedure. - A A- - ILLOD- (NOR-B) number of true vectors 12 13 14 15 ""no. true vectors Fig. 3*1 Computation time vs. number of true vectors for 6-gate functions of four variables. 5k Xr X- FORTRAN equivalent of Davidson's program FORTRAN equivalent of Davidson's program with the redundancy check procedure ILLOD-(NOR-B) without the redundancy check procedure ILLOD-(NOR-B) number of true vectors Fig. 3.2 Computation time vs. number of true vectors for 7-gate functions of four variables. 55 Finally we experimented functions of four variables which require 8 or more gates. Since these functions are more time-consuming than the previous ones we tested only a limited number of functions so far, and attempted to solve mainly by using ILLOD-(NOR-B). Table 3*7 shows the results. In Table 3«7.> each function is denoted by the hexadecimal equivalent of a l6-bit binary representation (a n , a , . .., a nc) > where a., i=0, . .., 15, are the coefficients of the minterm expansion of the function f: f = a Q x 1 x 2 x x^ sy a 1 x^ x g x x^ n/ & 2 x 1 x^ x x^ v a x^^ x g x x^ v ... v/ a 15 x ± x 2 x 3 x^ . Because of a limited number of test functions, we did not take the average of the computation times or of the number of backtracks. 56 Table 3-7 Follows 57 <^H -d- VO CO t- -d- NO NO H NO cu a h J- LfN CO co o CO ON o c- CO J- o c- LfN J- H Sh eb LfN o OJ UA rH NO H J- 02 LfN CO H oo ON o ON NO H O XI ON CO OJ CM NO NO ON o • « OJ ^o no tl ! J" OO ON J- H 3 -P-d- -d- CM O -d- H C— H O Eh H co co o s m H r-t •u c^- H CM H H H H s c •P H -_^ cd 1 13 ft o O CO 00 CO co CO CO CO n c t t t t t t fl tj t -P -d- H CM ON o NO J CD w • 0J CO CM 0J CO 0J H Sh !h H •H O fa 02 ON CM H ON O H o H ^T- cd cd CO CO NO H LTN -d" LTN •H h J*i -P — - 3 mo d ON CO NO* t— OO OJ a~ o > c- OJ b- CO ON uu H ~C C H CM H H H H « O cd •P H O ra -a ft o CO CO 00 CO CO CO Ft, T3 C O CO •h 3 t t t t t t 01 t> >o 1 XI aj cd •P o OJ ON ■3. CM 00 CO • Jh h •H O OJ OJ H 0J H ON CO" CO o O ON fa. M H H a Cd CO ON H J- -d- LfN -d- •rH fn •p ^ OJ LTN ON t- CO CM 3 60 2 a 1 o & a d ON NO IV- ro CO ID Jh E E OJ LTN J- H H P) O -H § w O EH t- OJ f- CO ON CO e g -P H H CM H H H H O M ft o CO CO" co CO CO CO fa TJ O CO •H t t t 1 t t CD > t ££ -p co • U H •H O t, CO o OJ 0\ OJ OJ CO ON H CO Ed o -H- OJ OJ o H ON ON •So -p a VO co ON ' o _d- H O CO Pd CM J- H H rS W ON £ o H a NO iH CO ON ON ON co O § c- EH O S ■*• O o rH CO O ON ON H CT\ H CO CO O a S, S O o o o OJ o H O O OJ o O ' CO O CO 5n 3 !h O S O X> -p -P p 58 r- NO -J- n -* in t— H OJ NO CO r> CO in m co OJ o r^ ON C- ON j- O ro OJ r- C\l NO NO CO -3- CO H iH H o OJ NO NO CO OJ NO □0 ON NO o OJ 3 J- ON CO in ON co in CO OJ OJ OJ NO H H H o u NU |1 1 UJ U\ njj -3- CU i-l H OJ ■ t* 3 . .-1 OJ OJ H OJ H H H H OJ H H H H CO CO CO CO CO 00 CO 00 CO ON CO CO 00 oo CO CO t t t t t t t t t t t t 1 1 1 t- NO -=f NO H -* in o ON r— on CO Si -3- a OJ OJ OJ OJ CO OJ OJ OJ CVJ OJ OJ OJ OJ o H d ON ON ON ON d 3 3 3 ON ON ON NO m j- CO CO -* m CO t— r- NO t— CO H o NO ON NO OJ l/N NO co J- f- H O CO no ON 00 t- E— OO NO in -3- OJ CO ON m ON ON H H CO ON ON TTn ^ H H H H H H CO CO CO CO CO CO t t t t t r- CO CO -* o OJ OJ OJ CM OJ CT\ d o H ON ON o CO H J- m H ON °°. t J- J- CO H C c C m NO a) at td -3- CO OJ OJ ■z 9. +J ON 5o -P ON t— CO H t— o O O -* m m 0) (UCO 0) CVJ H CO o £ O E O E CVJ .1 ON ■6n CO H H H H H 00 CO CO 00 CO" t t t t t o o OJ H -d- ON OJ OJ OJ co CVI H ON ON CO 0J~ ri ON CO o CO H t- in H NO O CO -1- in m CO CO NO H H □ ' 1 t " o OJ on ON m OJ H H to ao w w ON w w eq o ON H * CO w a fe H fe g w fc In fe 1 w o CO W W In o CO W ON ON pci ffl H bn ON NO i* w w w a o H OJ CO H H H H iH U g) > 3 O I O 59 REFERENCES 1. E. S. Davidson, "An algorithm for NAND decomposition of combinational switching functions," Ph.D dissertation, Department of Electrical Engineering and Coordinated Science Laboratory, University of Illinois, 1968. 2. T. Nakagawa and S. Muroga, "Exposition of Davidson's thesis 'An algorithm for NAND decomposition of combinational switching systems'," to be published, Department of Computer Science, University of Illinois. 3. T. Nakagawa and H. C. Lai, "A branch- and-bound algorithm for optimal NOR networks (The algorithm desceiption)," Report No. V38, Department of Computer Science, University of Illinois. k. T. Nakagawa and H. C. Lai, "Reference manual of FORTRAN program ILLOD-(NOR-B) for optimal NOR networks," to be published as a report, Department of Computer Science, University of Illinois. 5. T. Nakagawa, "A branch- and-bound algorithm for optimal AND-OR networks (The algorithm description)," to be published as a report, Department of Computer Science, University of Illinois. 6. T. Nakagawa, "Reference manual of FORTRAN program ILLOD-(AND-OR-B) for optimal AND-OR networks," to be published as a report, Department of Computer Science, University of Illinois. 7. S. W. Golomb and L. D. Baumert, "Backtrack programming," Journal of the Association for Computer Machinery , Vol. 12, no. k, pp. 516-521+ , October 1965. 8. C. R. Baugh, T. Ibaraki, T. K. Liu and S. Muroga, "Optimum network design using NOR and NOR-AND gates by integer programming," Report No. 293, Department of Computer Science, University of Illinois.