LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN XSHaY too. 2. 5^/ Report No. 381 'yyu^ COO-li+69-0156 THE OUTPUT DISPLAY OF TRMSFORMATRIX Yiu Kwan Wo February, I97O Digitized by the Internet Archive in 2013 http://archive.org/details/outputdisplayoft381woyi Report No. 38I THE OUTPUT DISPLAY OF TRMSFORMATRIX by Yiu Kwan Wo February, I97O Department of Computer Science University of Illinois at Urban a -Champaign Urbana, Illinois 618OI This work supported in part by the Atomic Energy Commission under Contract No. AEC AT(11-1) 1469 and submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering at the University of Illinois, Urbana, Illinois, February, 1970. Ill ACKNOWLEDGEMENT The author wishes to express his deep gratitude to his advisor, Professor W. J. Poppelbaum, for suggesting the topic and for his guidance and constant support. He would also like to extend his thanks to Professor S. Ray and Messrs. L. Ryan and 0. E. Marvel and many other members of the Hardware System Research Group for their advice and help which have made his work easier and more enjoyable. The author is also very grateful to Miss Carla Donaldson for typing the manuscript and to Messrs. M. Goebel and F. Hancock for their drafting. IV TABMI OF CONTENTS Page 1. INTRODUCTION 1 2. FUNCTIONS OF THE OUTPUT DISPLAY SUBSYSTEM AND ITS OPERATION MODES 5 3. PRINCIPLE OF OPERATION OF THE OUTPUT SUBSYSTEM o . . . 9 h. CIRCUIT DESCRIPTION l6 k.l Input Delay Circuit l6 k.2 Address Index Generator for Discrete Fourier Transform . . l6 ^.3 Circular Shifter „ 19 ^.4 The 33i'd Column and Row Generator 21 4.5 The 6-Bit D/A Converter 23 k.6 Blanking Network 28 h.6.1 The Unblanking Trigger Circuit 28 4.6.2 The Noise Discriminator 32 4.6.3 The Unblanking Pulse Generator 34 4.7 The Analog Summing Circuit 37 4.8 The Cathode Ray Tube Display Unit 37 5. PERFORMANCE OF THE SUBSYSTEM AND DISCUSSION 39 LIST OF REFERENCES 42 V LIST OF FIGURES Figure Page 1. Trans format rix Operation h 2. The Output Display Subsystem 10 3. A Delay Element I7 k. Address Indexes Generator I8 5. Circular Shifter 20 6. The 33]^d Column and Row Generator 22 7. The 6-Bit D/A Converter o 2U 8. Norton Equivalent of the Converter Circuit 25 9. The Analog Voltage Switch 27 10. The Blanking Network 29 11. Noise Due to Asynchronous Inputs to a NOR Gate 33 12. The Noise Discriminator o . . 35 13. Unblanking Pulse Generation and Timing 36 1^. Sujnming Circuit 38 15. 32 X 32 Output 40 16. 33 X 33 Output o . . . kO 1. INTRODUCTION Under the guidance of Professor Poppelbaum, the Circuit and System Research Group in the Computer Science Department at the University of Illinois has been involved in exploring and advancing the theories and hardware imple- mentation in stochastic computation. Following several successful attempts at developing stochastic computing machines operated on various principles developed in this laboratory ' ' , a new and more complex in scale stochastic graphical processor called Transformatrix is now taking shape. It is a highly parallel machine which can perform at television rate on its input picture, in a format of a square matrix of 32 x 32 points, three different types of operations; namely, the coordinate transformation, the two dimensional discrete Fourier transformation, and the pattern recognition. Its output, also in a format of a square matrix of points, is displayed with a cathode ray tube. In general, Transformatrix operation can be represented mathematically by the following expression: 31 31 i, j, k, i = 0,1,2,. . .,31 Subscripts i, j, k and £ are address or coordinate indexes whereas x. . denotes the signal value of the input picture at the position given by address indexes i and J. Similarly, y „ represents the signal value of the output picture at the position given by k and ^. The constants b „. . represent a ki/i J set of coefficients totalling (32) in num.ber and are calculated on-line by the coefficient processor of Transformatrix. With a different set of co- efficient '^'t^pAA, equation (l) represents a different type of Transformatrix 2 operation. It sho-uld "be noted that the most general form of mapping n input 2 signals onto n output signals is given by the expression n ^u = \i ^ iS Viij " ij (^-^^ i, j, k, i = 0,1,2, . . .,n The terms y, ^5 x. . and b, , . . have the same significants as that of equation (1) while the term a^. stands for a constant. It is therefore obvious that the Trans format rix operations are some specific cases of equation (l.A) in v/hich n equals to 3I and a „ equals to zero. From equation (l), one can easily see that operation of Trans formatrix involves the simultaneous formation of a very extensive combination of variable values. In the case of Fourier transform, for example, it amounts to over 60 million multiplication and summation operations per second. With such a high data processing rate, the capacity of most of the general purpose computers can be easily exhausted. However, it turns out that stochastic computations use simple digital AND gates and OR gates for the fundamental operations of multiplication and summation. Therefore the execution of such a complicated calculation as Fourier transformation can still be done with great ease and at a cost low enough to render important economical significance to building a highly parallel stochastic machine for this purpose. As pointed out in Dr. Poppelbaum's paper on stochastic computation, this is the very area where the advantages of stochastic computation over other forms of data processing stand out most predominantly. In fact, this characteristic has made Trans formatrix one of the most attractive applications of stochastic computation. Trans formatrix operation can be described most clearly in Figure 1. The input picture, consisting of a set of 102^ signals of x. . and denoted by X, refreshes at a rate up to 30 frames per second. The input pictiire X is obtained from an input sensing unit consisting of a matrix of 32 x 32 photo- conductors and is therefore a quantized version of the picture focused on the input picture plane. These quantized input signals x. . are then converted into synchronous random pulse sequence representation. In a synchronous random pulse sequence representation, the value of a variable is given by the probability of occurrence of a sequence of standardized pulses in fixed time slots synchronized with a clock. Each of these resulting 1024 values of x. . in synchronous random pulse sequences representation is now miiltiplied in parallel by the corresponding coefficient b „. ., also in synchronous random pulse sequence representation. The 102^ products are then summed together to produce an intensity value for a point in the output picture. In this way, the output pict\ire, consisting of a set of points y . and denoted by Y, is processed point by point serially. After it has been shown how the output picture Y is obtained from the input picture X, it is now ready to talk about another important part of Trans for matrix; namely, its output display subsystem. As a graphical processor, Transformatrix is designed to have visual output display. All amazing results of the output picture and magnificant features of Transformatrix are eventually conveyed to the observer through the output display subsystem. An effective display subsystem is therefore necessary to insure the high performance of Transformatrix. It is the purpose of this paper to describe the functions and design of this display subsystem. Also, some discussion will be given in Chapter 5 on the performance of the subsystem actually constructed. X II < 2 U x=> -o cr UJ I- c/) < ^§ to: U OOoOOOOO oj/oooy,oooo o oo-Xo oo o OOOOOOO o .o©oooooo o oo ooooo CVJ/OOO.OOOO o oo-Vo O OO ooo ooooo ^o o o ooo o o , UJ c > c UJ • o . O CO d o ^-^ ■p 05 u U- :=* QJ O = ft o JD 5 X q: ^ •H £-: -P ■ ^M ^ UJ o X c/f ^- .UJ n5 z — H — oc • H o 5h o -r cr j^ •H Q. ^ C^ 2. FUNCTIONS OF THE OUTPUT DISPLAY SUBSYSTEM AND ITS OPERATION MODES As mentioned earlier, the function of the output display subsystem is to show visually the output picture Y to the observer. A display subsystem designed for this purpose is to be described below. It is capable of dis- playing output pictures faithfully and acc\arately at the required frame rate. In addition, it can also display the output picture with some emphasis so as to bring to the attention of the observer some special feature of the output picture if so desired. These functions of the display subsystem are carried out with four different modes of display operation. They can be best illustrated by considering them separately as shown below. (l) In this mode of display operation, the processor of Trans for matrix performs the coordinate transformation or pattern recog- (7) nition operation. For the former case, the output picture Y is the result of any combination of rotation, translation, and magnification of the input picture X. Mathematically, y „ is related to x. . by the following expressions. Let U and V be the analog magnitude of the address indexes k and i respectively. Also, let u and v be defined as follows: u = -[U cose - V sine] - a (2. A) V = -[U sine - V cose] - b (2.B) In equation (2. A) and (2.B), m and n are scaling factors whereas a and b are translation factors. Then the relation of coordinate transformation is given P = Q[u] (3. A) 6 q = Q[v] (3.B) ^ [''pq p,q,k,i < ki [0 otherwise _ /pq p,q,k,i < 31 (u) where Q,[argument] represents a digitally quantized value of the analog argiiraent. It shoiild be noted that this set of equations describes a special case of the general equation (l) of Transformatrix operation. With the substitution of equation (2) and (3) into {k) together with a little manipulation, it is not difficult to write the result in the form of equation (l). In the latter case, the output picture Y shows only one bright point (or a few bright points) among the output square matrix of points at the position corresponding to the center of the pattern in the input picture plane whenever the pattern in the input picture matches a predetermined one. Other- wise, the output y „ will be identically zero, i.e. a totally black output picture would result if the pattern in the input picture is not similar to the predetermined one. This mode of display operation shall be referred to as the first mode. (2) In this mode of operation, the output picture Y is the result of Discrete Fourier Transform of the input picture X. Mathematically, this can be expressed by the following equation. V - ^ Z^ Z^ X expf -^^"^^^ -^ ^-^^ 1 (5) ^ki - 32 k=o iko \j ^"^PL 32 ^ ^^^ where s := -/^ and k, £, i, j are all integers running from zero to 31' As can be seen in equation (5), the output signal y „ is ordinarily a complex quantity although x. . is real. Unfortunately, there is no convenient way of J- J displaying visually a complex quantity such as y, /,• However, this difficulty can be solved with the compromised way of displaying separately the magnitude of the real part, the imaginary part, and the norm of the complex quantity, as it is actually the case here for Transformatrix. This mode of operation shall he referred to as the second mode later on. (3) This mode of operation, referred to as the third mode later on, is basically the same as the second mode except the output picture Y is displayed in a format of a square matrix of 33 x 33 points. In other words, k and l range from zero to 32 instead of from zero to 31* From equation (5) it is obvious that ^U - ^(32 + k)(32 + i) ^^^ Let the row having £ - and i = 32 be called the 1st and 33^d. row respectively. Likewise, col\jjims are referred to in the same way. Then equation (6) shows that the 33]^d row and coli:unn are the replicas of the 1st row and column respectively. These duplications are done electronically by the output sub- system in this mode of operation. The idea of displaying the output pict^ure in such a way is to make the symmetry in the output picture standing out more remarkably and distinctively. In so doing, the symmetry property of the output picture is emphasized. {k) The fourth mode of operation is to display the output picture of the first mode of operation in the format of a matrix of 33 x 33 points in the same way and for the same purpose as the third mode of operation does. In addition to these four modes of operation, the output subsystem can perform circular shifting operation of the output picture in both horizontal and vertical directions. In other words, instead of displaying Y-.g, the subsystem is capable of displaying a shifted one called sy which is defined by P = k # u (8) q = i # V (9) where # stands for modiilo -32 siira and u,v are integers representing the number of steps to be shifted in the k and i directions respectively. With such an arrangement, the capability of the output subsystem to display emphatically some output picture characteristics is enhanced. The output display subsystem consists of a cathode ray tube display unit and an electronic network for driving its x, y, and z axis inputs. They shall be discussed in detail in the following chapters. 3. PRINCIPI£ OF OPERATION OF THE OUTPUT SUBSYSTEM The output display functions described in Chapter 2 can be carried out with an analog-digital hybrid electronic system as shown in Figure 2. The inputs to this subsystem come directly from the processor. They are designated by IX for the address index in the x direction, lY for the address index in the y direction, and Z for the z axis intensity information. IX and lY are in 5-bit binary numbers while Z is in analog form. The refreshing rates of these input data are different for different modes of display operation. Never- theless, the frame rate is held fixed for all modes, as shall be seen more clearly later on. Upon arriving at the inputs of the subsystem, IX and lY are, first of all, delayed by one 3O.7KHZ clock period. This is due to the special arrangement in the processor which delivers the Z signal a clock period later than the associated IX and lY. After the delay, IX and lY are gated through a different signal path for a different operation. They are considered individually in the following. (1) For the first mode of operation, the delayed IX and lY, denoted by DX and DY, are refreshed every 3O.7KHZ clock cycle. They are gated to the horizontal and vertical circular shifters where the address index data DX and DY are shifted according to equations (8) and (9). The resulting 5-hit signals SX and SY are used to feed the first five bits of the 6-bit digital to analog converters while the sixth, and the most significant, bit input of the converter is grounded by the setting of switch 2a and 2b for this mode of operation. The analog output voltages from the digital to analog converters are now ready to drive the x and y inputs of the cathode ray tube display unit. The z axis intensity signal from the processor is fed to the z axis input of the display unit after blanking pulses have been inserted through the 10 z o K < oc UJ a. o o UJ § o Ul o o o 2 Z o 2 I UJ Q z o < ) o K -) O UJ I O 2 IJL (rt 1- u. C>J * 7 O I ( ) OD m < < 1- t- o Q. I (.J (0 « K X o 1- S m < < CD -p >3 H ft w •H o -p :i ft +^ CM b0 11 analog suinming circuit. Like all other modes of operation, blanking is provided diiring every transition period of the scanning of the electron beam. However it will be treated separately later ono (2) For the second mode of display operation, DX and DY are gated through the index generators before being fed to the circular shifter. The data rate of the inputs IX and lY from the processor for this mode of operation is about half as much as that of the first mode. The remaining part of the display subsystem for this mode of operation is the same as in the case of the first mode. As mentioned earlier, there are three different types of display for this mode; namely, the magnitude of the real part |Re[y . ]|, of the imaginary part |lm[y .]|, and of the norm |y, /;|. Happily enough, a close examination of equation (5) shows that ^h =^(32 - k)(32 - i) ^1°) where y^„ denotes the complex conjugate of y . . Therefore, it follows that ^kil - 1^(32 - k)(32 - i)l ^^^) and also that |Ee[y^^]| = |Re[y(32.^)(32.^)]| (12) |lm[yj^]| = |lr»[y(32 . ^^^j^ . ^^]\ (13) These relations suggest that once the intensity y, . of an output point (k,i) is calculated by the processor, it can be used for the point (32 - k, 32 - ^) 12 Further examination of these relations discloses that all except four of the output points have their intensities equal to one other point of the same picture. It becomes advantageous then for the processor to economize the calculation time by actually processing the four singular points of the output picture plus half of the rest. These four singular points are (0,0), (l6,0), (0,16), and (16,16). If equation (lO) is applied to these points, it is found that each of them is related to no other point of the same output picture but itself. Because the processor furnishes data for approximately half of the output points, the remaining ones have to be generated by the subsystem according to equation (lO) . This is exactly what the index generators are designed to perform. Upon receiving the address index data DX and DY, the generators gate them to its outputs for the first half of the clock period for this mode of operation, which is approximately half as high in frequency as that of the first mode of operation -- (102^/2 + l4-)/(l02J4) to be exact. For the second half of this clock period, the generators send out from their outputs the address index data (32 - DX) and (32 - DY) in 5-bit binary numbers. However, the intensity data Z remains unchanged for the entire clock cycle. Whenever any one of the four singular points is encountered, the outputs of the index generators remain \inchanged for the whole clock period. But the electron beam of the cathode ray tube is blanked out for the second half of the clock period. In this way, the output subsystem reconstructs the complete output picture with approximately half as much data as that of the first mode operation. Furthermore, it is not difficult to convince oneself that the output frame rate for the arrangement mentioned above is the same as that of the first mode although the input data rate from the processor is about half as fast. 13 (3) For the third mode of display operation, the output subsystem is operated in the same way as in the case of the second mode except that the sixth "bit inputs to the 6-bit digital to analog converters are connected to the outputs of the 33]^d column and row generator as shown in Figure 2. The function of this generator is to produce output picture points on the 33^d row and column. When the input data to this generator, SX and SY, correspond to an output point neither on the first row nor the first colijjnn, the outputs of this generator are held at logic "0" level for the entire clock period. In other words, the generator produces no effect on the output picture for this case. However when SX and SY have values corresponding to an output point either on the first column or the first row but not both, i.e. either SX = 00000 or SY = 00000, the generator is activated. For the case of SX equal to 00000, the output X6 of the generator is a logical "0" for the first half of the clock cycle and changes to a logical "1" for the second half, while the other output y6 remains at logic "0" for the entire clock period. Because the sixth bit input of the digital to analog converter for x axis signals is driven by X6, the output value of the converter is for the first half of the clock cycle and 32 units for the second half. Meanwhile, the output value of the digital to analog converter for y axis signal remains unchanged at a value given by SY for the entire clock cycle. Hence, the resulting scanning sequence of the electron beam is that the beam stays at the output point on the first coliomn for half a clock cycle and then switches to the position at the same row but 33rd column for the second half of the clock cycle. For the case of SY equal to 00000 but not SX, X6 and Y6 exchange the roles they play in the above case. All other operations of the subsystem are the same as that of the previous case. Ik When both SX and SY are equal to 00000, the generator output X6 is at logic "0" level for the first half of the clock cycle and logic "1" level for the second half. However, the output y6 switches between "0" level and "1" level every quarter of a clock cycle. This causes the electron beam to be steered to the output points (0,0), (32,0), (0,32) and (32,32) subsequently for each quarter of a clock cycle. The intensity signal Z remains unchanged for the entire clock cycle for all cases . Therefore the intensities of the output points on the 33rd row or column are identical with that of the corresponding points on the first row or column . Apparently, the function of the generator causes the electron beam to stay at a different output point over a different period of time. To insure a proper display operation, appropriate blanking is therefore necessary to keep a imiform display time for every output point. This shall be discussed in more detail later on. This is the way the 33rd row and column generator produces the replicas of the first row and column to form an output picture having a format of a matrix of 33 x 33 points. {h) For the fourth mode of operation, all arrajigements in Figure 2 are the same as in the case of the first mode with the only exception being that the outputs X6 and y6 of the 33^^^. column and row generator are connected to the sixth bit inputs of the digital to analog converter for x and y axis signals respectively. Hence, the output picture is similar to that in the first mode but in a format of 33 x 33 matrix. The 33rd column and row of the output picture are the replicas of the first column and row respectively, and they are reproduced by the 333^d row and col\imn generator in the same way as in the case of the third mode. 15 Blanking is used for all modes of operation. It has two-fold significance: to blank out the unwanted traces resulting from the transient spikes which often occur in the transition period of a change of input data; and to insure uniform display time for every output point as mentioned above. Blanking is provided by a circuit which sends out an unblanking pulse of fixed width every time the beam is steered to a new output point. 16 h. CIRCUIT DESCRIPTION k.l Input Delay Circuit A standard delay circuit is used for the input delay. It consists of ten one-bit shift registers in parallel. Each shift register is made up of an inverter and an SR flip-flop as shown in Figure 3« The flip-flop used here is of the master-slave type. When the clock goes HIGH, input information is gated to the master after it has "been isolated from the slave. When the clock goes LOW, data to the S and R inputs are inhibited and the information stored in the master is transferred to the slave. It is not difficult to see that this arrangement as shown in Figure 3 delays the signal by one clock cycle, k.2 Address Index Generator for Discrete Fourier Transform Two index generators are used, one for the index in the x direction and the other in the y direction. The circuit description below is in terms of the X index generator. However, it also applies to the y index generator. Figure k shows the schematic diagram of an index generator. When the clock signal is HIGH, the NOR gates are inhibited and the input data are gated through the AND and OR gates to the outputs. When the clock signal is LOW, and AND's are inhibited. The input data go through the 5-tiit subtractor where a binary number 00001 is subtracted from the inputs. The remainder is inverted as it passes through the NORs and then sent to the outputs. It is quite obvious that an inversion operation on a 5-bit data X having decimal value d corresponds to the operation (31 - d) in decimal representation. Taking into account that 00001 has been subtracted from the input data before the inversion operation, the output data after the inversion is equal to (32 - d) in J-bit binary representation when the clock is LOW. When the input data X is I 17 I I X II I X II P -P (U H 0) ■H fin I 18 XI > X2 > X3 > X4 > BINARY No 00001 Fi glare k. Address Indexes Generator 19 corresponding to a singular point mentioned earlier, it has a decimal value of 16. In this case, the output data remain unchanged for the entire clock cycle because both X and (32 - d) are equal to I6. k.3 Circular Shifter Figure 5 shows the structure of the circu3.ar shifter. Inputs to the shifter are the address index data for both x and y directions in 5-bit binary numbers. A circ-ular shift in the horizontal or vertical direction of the output picture can be obtained simply by adding moduloly onto the x and y address index respectively the amount by -which the picture is to be shifted. Therefore the inputs are fed to the 5-t)it adders. The other inputs to these adders are furnished by the outputs of two 5-'bit counters. The output value of the counter represents the amount of shifting. This value can be changed by enabling the clock to drive the counter. Furthermore, the counter outputs can be preset at a fixed value by the preset switch. For the shifter, it is preferable to have low clock frequency of the order of 1 Hz. Such a clock frequency results in a low shifting rate, a few steps per second, for the output picture while the clock input switch in Figure 5 is kept closed. This makes it easier for manual control of the clock switch to stop the shifting at a right place. The low frequency clock is obtained by scaling down the high frequency clock already available from the processor with ripple through counters connected in series. In the actual circuit, integrated circuit SF7493Ns are used to perform this function. The 5-t)it adder in Figiore 5 consists of two 2-bit full adders SN7^83N and a full adder SNY^SON. The 5-bit ripple counter consists of a SNYii93N and half of a dual flip-flop SN7i^76N. 20 XI >- X2 >- X3 >- X4 >- X5 >- 5 -BIT ADDER ? — v~f~j — r CLOCK INPUT SWITCH HIGH FREQ. CLOCK IN 4-BIT COUNTER FOR HORIZONTAL SHIFTING 5- BIT RIPPLE COUNTER RESET *"! 5- BIT RIPPLE COUNTER Yl >- Y2 >- Y3 >- Y4 >- Y5 >- t t I T T RESET -1 5-BIT ADDER oyH 0Y2 0Y3 ) 0Y4 I OYSJ FOR VERTICAL SHIFTING Fig\ire 5. Circular Shifter 21 k.h The 33rd. Column and Row Generator The schematic diagram of the generator is shown in Figure 6. When a 33 X 33 point output picture is to be displayed, i.e. for the case of the third or fourth mode of operation, the switch shown in Figure 6 is opened. It is closed otherwise. When the switch is closed, both X6 and y6 are at logic "0" level. The generator has no effect on the display in this case. When the switch is opened there are four different cases which are treated individually in the following. (1) When neither input SX nor input SY is equal to 00000, outputs of both gate 1 and gate 2 are HIGH. The outputs X6 and Y6 in this case are therefore at logic "0" level. (2) When the input SX, but not SY, equals 00000, output of gate 1 is LOW while that of gate 2 is HIGH. The SO.VKHz clock CI is therefore gated to X6. Hence, X6 is at levels "0" and "1" each for half of a CI clock cycle while y6 is kept at LOW level. (3) When the input SY, but not SX, equals 00000, gate 2 output is LOW but gate 1 output is HIGH. CI is gated to Y6 while X6 remains LOW. (4) When both SY and SX are equal to 00000, outputs of both gate 1 and gate 2 are LOW. CI is then gated to X6 but not to y6 because gate 8 is inhibited in this case. Instead, C2 of 6l.^KHz is gated to y6. Hence, X6 behaves the way it does in case (2) but y6 switches between "0" and "1" every quarter of a 3O.7KHZ clock cycle. 22 o U 0) c O K Ti 05 H O O oo (U XI EH 0) iaO •H SJS 23 h.3 The 6-Bit D/A Converter Figure 7 shows the circuit schematic of the 6-bit digit aJL to analog converter. Two converters are used: one for x axis signal and the other for y axis signal. The circuit consists of six analog switches and a weighted resistor summing network. The first five bits are driven by the five bits of the output of the pictiire circiilar shifter. The sixth bit is grounded for the first and second modes of display operation and is driven by the outputs of the 33rd. row and column generator for the third and foiorth modes. The output of an analog switch is at the reference voltage level when its input is a logical "0". When its input is "1", the output is grounded. The internal impedance of a switch is negligibly small comparing with the load impedance. If the Norton Theorem is applied to the network shown in Figure "J, an equivalent circuit showing more explicitly the digital to analog conversion function results. Such an equivalent circuit is shown in Figure 8. The combined equivalent current soiorce in this figure is given by I^ = V , ref rr.^ J^ ^3 ^2. T " l60kfi (2^x^ + 2 X + 2-^x, + 2 X + 2x + x ) (l4) It follows that the output voltage V, or the attenuated output V are proportional to the value of the 6-bit binary number of the inputs. Trimming potentiometers are used in series with each input branch. This is to provide customized adjustment for eliminating errors due to the non-zero output impedance of the voltage switch as well as the deviation in resistance value from the given one due to tolerance. It is well known that the resistance value of a resistor changes with temperature. This temperature effect would cause serious error for the converter if it is not taken care of properly, especially with the higher 2k '<6> '<5> X4> X3> X2> x,> SWITCH #■! SWITCH #2 SWITCH ^3 SWITCH #4 SWITCH ^b SWITCH #6 ♦— AAAr- 5K 5on i — ^AA^ <> lOK lOOil i— ^NAA^ <► 20K 5oon i Wy/ «' 40K IK i — ^AA/ <• 8 OK 5K i /WV- I60K lOK -O OUTPUT Figure 7- The 6-Bit D/A Converter in 25 ( » "-^AAr roby in in to in m in m X LU X 1- Ll O Ld LU O =5 .< -J >-. §S > Sr? LJ ^ o o o 9 2 CD -J UJ ^ ^5 C/) cc a: o LiJ o h- (/) UJ QC O Ld X o LU ^ LU X h- Ll. O I- z UJ < > o UJ o I- q: o X Jf o > ISI o > HI' ^ ^AAr 4-> •H =i CJ Jh ■H O H 0) 3 -p or > — ^ o o o 0) 1- ^ z -p LU Ch _l o < -p a > — " H 3 03 o > •H UJ =! 0^ Q W UJ d O O -P 3 ^ Q O UJ (T ^ 00 **"■** ^ OJ V— ^ ^ =1 bD •H Ph 26 significant bit circuit. To ensure accurate conversion over the entire temperature range of operation, metal film and wire wound resistors with low temperature coefficients are therefore used in the key places such as the weighted resistors of the higher significant bits. The circuit diagram of the analog voltage switch in Figure 7 is shown in Figure 9" A buffer amplifier stage is employed in the switch input network to insure that the signal swing is larger than the reference voltage of 12 volts. The output of the buffer stage is DC coupled to the complementary pair 2NI308 and 2N1309 through the current limiting resistors R5 and R6. The transistors 2N1308 and 2N1309 are operated in an inverted mode configuration. This is because transistors have small collector to emitter saturation voltage in such a configioration and it leads to smaller off-set error of the digital to analog converter. The emitter of the transistor 2N36U2 returns to -2.5 volts supply, which is provided by a forward biased diode device SV3163A. The diode device SV31^3A, being forward biased at 30mA through the resistor R, , has exceptionally low dynamic internal impedance of about 2 ohms and a forward drop of 2.5 volts. To lower the internal impedance of the -2.5 volts supply further, CI and C2 are connected in parallel with the SV31^3A. C3 is solid tantalum type capacitor of high capacitance for low frequency harmonic filtering while C2 is ceramic type high frequency capacitor. The resistor chain R and R is used to hold the base of 2N36^2 at about -3 volts to insure the 2N3642 being cut off when the input X. is at logic level "0". When transistor T-, is off, the collector base junctions of the 2N1308 and 2NI309, both operated in inverted mode, are forward and reversed biased respectively. Hence, the 2N1308 is turned on while the 2N1309 is off, causing the output to be held at the reference voltage of 12 volts. Similarly, the output is grounded when T is turned on. It should be noted that the emitter I.5K X|N> VSA^ + I5V A .47/xF 27 REFERENCE VOLTAGE 4 VREF--I2V R5 470ri Re 470 il "^2 r 2N3642 ^2 .47^F SV3I43A + I5V T2 2NI308 -O OUTPUT T3 2NI309 Figure 9. The Analog Voltage Switch 28 base junction of transistor T is reverse biased at 3 volts when T is off. Hence, transistor T is required to have emitter base bresikdown voltage more than 3 volts. The same requirement is needed for transistor T^ as a resiilt of a similar argijment for the case in which T is on. h.6 Blanking Network To perform the blanking operation as mentioned in Chapter 3, a circuit shown in Figure 10 is used. In fact, the electron beam is blanked out ordinarily. An unblanking pulse of fixed width is sent out by this circuit every time a new data is to be displayed. During the unblanking period, the beam intensity is held at a level determined by the z axis data. The circuit in Figure 10 can be decomposed into three parts: an unblanking trigger circuit, a noise discriminator, and an unblanking pulse generator. The unblanking trigger circuit sends out a triggering pulse whenever unblanking is needed. This triggering pulse passes through the noise discriminator where false triggers arising from various kinds of noise phenomenon are rejected. Also, the discriminator delays the trigger for 2 microseconds and shapes it into a pulse of 1 microsecond width. This delayed triggering pulse is then sent to activate the unblanking pulse generator. An unblanking pulse which begins at 3 microseconds after the beginning of the corresponding clock period and has fixed width is then obtained from the output of the generator. They are described separately below in more detail. k,6.1 The Unblanking Trigger Circuit As shown in Figirre 10, when the switches are set for the first mode of operation, g8 and G3 are inhibited. C2 is therefore gated to the output R of the unblanking trigger circuit. C2 is a clock of 3O.7KHZ from the processor. I I 29 i a: o o 2 o i u. a z s s Z e X % I 03 ffi < < X o s < 4 o J — 3C i^ « OR f^ W J^ -^ x: < « m iO UJ -1 — — IC « f-j p- ff. 8 o )C I.) * ?■ o £ ? * 1 ) ^ «T * ^ >'i M O -P EH CVI H (D •H to 4. A CD 2 < 00 2 3 36 TRIGGER IN Cx Rx Vcc J I m A^^V— J PULSE WIDTH = 0.36-RxCx UNBLANKING TRIGGER DELAYED TRIGGER UNBLANKING PULSE 2m EL 3mS lU, IMS ■♦ t •— W— J W IS FROM 3.5mS TO 25mS ADUSTABLE Figure 13 . Unblanking Pulse Generation and Timing 37 ^•7 The Analog Siiinming Circuit The unblanklng pulse is superimposed onto the z axis signal through an analog siunming circuit. A standard weighted resistor sujnniing circuit, shown in Figure 1^, is used for this purpose. Note that a limiter is connected to the output. During the blanking period, the output of the summing circuit is driven beyond -10 volts. But the limiter keeps the output at a constant voltage level -- about -9-1 volts -- during the entire blanking period so as to protect the cathode ray tube display unit from excessive drive. ^•8 The Cathode Ray Tube Display Unit Among various existing display devices, the cathode ray tube appears to be a most suitable one for the application at hand as it has better capability for displaying pictures at high frame rates. After some testing on the performance of different models of cathode ray tube display units, a Tektronix type 602 display \mit was chosen. It has a 5-inch cathode ray tube with p4 phosphor, which is generally considered to be the best type for pictorial display at standard television rates because of its high efficiency in light emission, medium persistance, and wide spectrum of emitted light. The X, y, and z inputs have a bandwidth from DC to IMHz. 38 lOK UNBLANK PULSE > yX 20K Z-AXIS SIGNAL > yX TO CATHODE RAY TUBE DISPLAY UNIT IN757A N757A Figure 14. Sumnaing Circuit 39 5. PERFORMANCE OF THE SUBSYSTEM MD DISCUSSION The output display subsystem of Trans formatrix as described in the preceeding chapters has been implemented. Most parts of it have been tested and have shown to perform satisfactorily. At the present time, the input subsystem and the processor of Trans formatrix are still under construction. Therefore, testing is carried out by simulation. A 10-bit synchronous counter, simulating the processor, feeds the display subsystem with x and y address data whereas the z axis signal is held fixed. Figures 15 and l6 show the typical formats of the output pictiire. Testing shows that this subsystem can be operated successfully at any display rate up to about kO pictirres per second, making it more than capable of displaying the output picture of Trans formatrix. Above this rate, the quality of the output picture would decline because of insufficient brightness due to the fact that the portion of the time period in which the beam is unblanked decreases as the display rate increases. During the design process of the display subsystem, it has been understood that some modification in the characteristics of the input data from the processor to the display subsystem may occur later on because of the complexity of the design of the processor and the many problems which may arise in the course of its implementation. Consequently, high interface flexibility with the processor is an important feature incorporated in the design of the display subsystem. It is so designed that it is capable of taking input data at any sequence in which the processor finds it easiest to operate. In addition, the display subsystem can be operated at any display rates the processor is set for. Furthermore, the processor can choose as the coordinates origin of the output picture, which is the DC spatial frequency 1+0 Figure 15. 32 x 32 Output Figure l6. 33 x 33 Output 1+1 component in the case of the discrete Fourier transform, any point which makes the hardware implementation of the processor easiest. The display subsystem then shifts the coordinate origin of the output picture through the x and y circular shifters to wherever it appeals to the observer most. Although the display subsystem performs satisfactorily, there is still room for modification and improvement. The most challenging problem to be tackled appears to be the stability of the displayed picture. Like the situation in many television displays, it is found that some small wobble movement of the entire picture exists. It is believed that it is caused by some small oscillation occurring in the cathode ray tube driving circuits in the Tektronix type 602 display unit and locked into the frequency of the inputs to these circuits. Finally, the design of the display subsystem described in this paper is a successful one, although more than one design configuration can lead to the same end purpose and performance. The underlying principles during the entire course of the design were circuit simplicity, reliability, as well as practicality in terms of time and facilities available. Different design principles, of course, lead to different ways of implementation of the display subsystem. k2 LIST OF REFERENCES 1. Afuso, C, "Analog Computation with Random- Pulse Sequences", Report No. 255 J Department of Computer Science, University of Illinois, February I968. 2. Esch, J. W., "A Display For Demonstrating Analog Computation with Random Pulse Sequences", Report No. 312, Department of Computer Science, University of Illinos, March 1969. 3. Marvel, 0. E., "Model T, A Demonstration of Image Multiplication Using Stochastic Sequence", Report No. 3^9? Department of Computer Science, University of Illinois, August I96U. h, Poppelbaum, W. J., Afuso, C, and Esch, J. W. , "Stochastic Computing Elements and System", AFIPS Proceedings , I967 FJCC, Vol. 31, pp. 635-64U. 5. Esch, J. W. , "A Programmable Analog Computer Based on A Regular Array of Stochastic Computing Element Logic", Report No. 332, Department of Computer Science, University of Illinois, February 1969' 6. Ryan, L. , Marvel, O.E. and Wo, Y., "The Coordination Transformation", Quarterly Technical Progress Report, April, May, June, I968 , Department of Computer Science, University of Illinois. 7. Ryan, L., "Pattern Recognition", Quarterly Technical Progress Report, April, May, June, I969 , Department of Computer Science, University of Illinois. 8. Ryan, L., Marvel, O.E. and Wo, Y., "Two Dimensional Discrete Fourier Transforms", Quarterly Technical Progress Report, October, November, December, I968, Department of Computer Science, University of Illinois. Form AEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UWIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFJC AND TECHNICAL DOCUMENT (S»e Instructions on R»v»ne Side ) 1. AEC REPORT NO. COO-1469-0156 2. TITLE THE OUTPUT DISPLAY OF TRMSFORMATRIX 3. TYPE OF DOCUMENT (Check one): t^a. Scientific and technical report r~l b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): ^^a. AEC's normal announcement and distribution procedures may be followed. I I b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. I I c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) Yiu Kwan Wo Reseaxch Assistant Organization Department of Computer Science University of Illinois Urbana, Illinois 6iSQl Signature ^aW ^c Date January 26, I97O FOR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: 8. PATENT CLEARANCE: LJ a. AEC patent clearance has been granted by responsible AEC patent group. I I b. Report has been sent to responsible AEC patent group for clearance. r~l c. Patent clearance not required. INSTRUCTIONS Who uses this form; AEC contract administrators will designate the APX contractors who are to use this form. Generally speaking, it will be used by educational institu- tions and other "not for profit" institutions. AEC National Laboratories and other major contractors will generally use the longer form, AEC-426. When to use this form: AEC contractors are required under their contracts to transmit specified types of documents to the AEC. Some, but not all, of these are transmitted by AEC contract administrators to AEC's Division of Technical Information (DTI) and may be incorporated into AEC's technical information documentation system. Types of documents which will be transmitted to DTI are identified in instructions which the contractor receives from his contract administrator. Each such document is to be accompanied by one copy of this transmittal form in order to instruct DTI regarding announcement and distribution of the document. (Exception: Reprints of journal articles may be transmitted to DTI, but no transmittal form should be used with such reprints.) Documents which the contractor may be required to submit to the AEC under his contract but which are not of the type to be transmitted to DTI should not be accompanied by a copy of this transmittal form. Examples of types of documents in this latter category include such items as: contract proposals, manuscripts and preprints of journal articles, and manuscripts of oral presentations which are to be published in a journal in substantially the same form and detail. Where to send this form: Send the document and the attached form AEC-427 to the AEC contract administrator for transmittal to DTI unless the AEC contract administrator specifies otherwise. Item instructions: Item 1. The first element in the number shall be an AEC-approved code. This may be a code which is unique to the contractor, e.g., MIT, or it may be the code of the AEC Operations Office, i.e., NYO, COO, ORO, IDO, SRO, SAN, ALO, RLO, NVO. The contract administrator will specify the code which is to be used. The code shall be followed by a sequential number, or by a contract number plus a sequential number, as follows: (a) Contractors with unique codes may complete the report number by adding a sequential number to the code, e.g., MIT-101, MIT-102, etc.; or they may add the identifying portion of the contract number and a sequential number, e.g., ABC-2105-1, ABC-2105-2, etc.; (b) Contractors using the operations office code shall complete the report number by adding the identifying portion of the contract number and a sequential number, e.g., NYO-2200-1, NYO-2200-2, etc. Item 2. Give title exactly as on the document itself. Item 3. If box c is checked, indicate type of item being sent, e.g., thesis, translation, computer program, etc. Item 4. The "normal announcement and distribution procedures" for unclassified documents may include listing in DTI's "Weekly Accessions List of Unlimited Reports" {TID-4401); abstracting in "Nuclear Science Abstracts" (NSA); and distribution to appropriate TID-4 500 ("Standard Distribution for Unclassified Scientific and Technical Reports") addressees, to AEC depository libraries, to the Clearinghouse for Federal Scientific and Technical Information for sale to the public, and to authorized foreign recipients. Check 4b or 4c if there is need for limiting announcement and distribution procedures described above. The normal expectation is that there should seldom be a necessity to check 4c. Item 5. If 4b or 4c is checked, give reason for recommending announcement or distribution restrictions, e.g., "preliminary information", "prepared primarily for internal use", etc. Item 6. Enter name of person to whom inquiries concerning the recommendations on this form may be addressed. Item 7. AEC contract administrators may use this space to show concurrence or nonconcurrence with the recommendation in item 4 and to make other recommendations. Item 8. AEC contract administrator or patent group representative should check a, b, or c, and forward 4;his form and the document to: USAEC - Technical Information P. O. Box 62 Oak Ridge, Tennessee 37830 GPO 960-S35 %., f"^ %/?? i