LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN ETIO-8 TJL(or no. 547-55Z cop- 2. from l/Sfc^y Ar •3400 t"«AA,. 5*AA4ft 'A/CN Digitized by the Internet Archive in 2013 http://archive.org/details/illiaciiicompute551goya 7A w UIUCDCS-R-73-551 V77 ^X4( ILLIAC III COMPUTER SYSTEM MANUAL: ARITHMETIC UNITS —VOLUME 2 Toy Lakshmi N. Goyal January 1973 COO-2118-OOUl V / *a DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS UIUCDCS-R- 73-551 ILLIAC III COMPUTER SYSTEM MANUAL: ARITHMETIC UNITS* VOLUME 2 by LAKSHMI N. GOYAL January 1973 Department of Computer Science University of Illinois Urbana, Illinois 6l801 * This work was supported by the U.S. Atomic Energy Commission under Contract No. AT (ll-l) 2118. Ill ACKNOWLEDGMENT The present work is concerned with the Control Logic and the- hardware implementation of the arithmetic algorithms of Illiac III Arithmetic Units. This volume has been made possible by the contributions of many people. The author would like to express his appreciation to these people in general. In particular, the author will like to mention a few principal names. Dr. Daniel E. Atkins and Prof. James E. Robertson provided the original conceptual design,, Dr. Atkins was mainly responsible for the design of the processing hardware and the arithmetic algorithms. These arithmetic algorithms are the basis for the control sequences reported in this work. The author is very grateful to his friend, Dr. Atkins, for his gracious help and time which he so ungrudingly gave, in the clarifications and understanding of the arithmetic algorithms. Mention should be made of Mrs. Tuh-Kai Koo who wrote extensive simulation programs which were used in validating the arithmetic algorithms. The author would also like to thank Professor Bruce H. McCormick under whose overall direction this work was undertaken and who taught the author the merits of logical segmentation of control logic in terms of Procedures and Subroutines. The logic design and different versions of Control Points used in designing the control logic evolved from the contributions of many people. The principal contributors were Dr. Daniel E. Atkins, Dr. J. Divilbiss, Dr. B. J. Nordmann, Mr. S. Paul Krabbe, Mr. Ron Martin, Mr. Val Tareski and the author. The author is very thankful to Mr. S. Paul Krabbe under whose direct supervision this control logic has been layed out on logic cards and their fabrication completed. He has borne the weight of the ardous task of super- vising the wiring tables generation, back panel wiring, logic cards check out, etc, IV In addition, he is chiefly responsible for the design of interface driver logic and numerous other hardware and circuit details. The illustrations were prepared by Mr. Stan Zundo who labored over many revisions of the illustrations and drawings. His humor and cheerful disposi- tion always made it a pleasure to go to the drafting section. Thanks are to due to Mrs. Barbara Bunting and Mrs. Barbara Armstrong for doing a good job of typing and finally to Mr. Dennis Reed for the meticulous reproduction of this manual. V TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. STRATEGY OF CONTROL DESIGN h 2 . 1 General Remarks *+ 2.2 Control Point Flow Chart Conventions 5 2.2.1 Task Stage 5 2.2.2 Sequence Stage 9 2.2.3 "Entry" and "Exit" Symbols 11 2.2.U "JOIN" Symbol 13 2.2.5 Miscellaneous Notations 13 2.3 Logic Implementation of Control-Point Flow Charts IT 2.3.1 Modifications to Martin's Control Point 19 2.3-1.1 Memory Element Reset Logic 19 2.3.1.2 Delayed Task Generation (DETAG) Control Point . 19 2.3.1.3 Calling Control Point 23 2.3.1.1* Interlocking of Two Parallel Independent Control Chains 25 2.3.2 Conversion of Control Flow Charts into Control Logic Drawings 27 2.3.2.1 Control Point Drawing 27 2.3.2.2 Task Signal Collector and Task Driver Drawings 29 2.3.3 Control Logic Drawing Conventions and Notations . . 31 2.3.3.1 Control Point Standard Symbolic Representation 31 2.3.3.2 Control Point Signal Name Conventions . . . 33 2.3.3.3 Sequence Stage Signal Name Convention . . . 35 2.3.3. h "Task Signal Collector" and "Task Driver" Drawings ' Signal Name Convention 35 VI Page CONTROL SEQUENCES, CONTROL-POINT FLOW CHARTS AND THEIR OPERATIONAL DESCRIPTION 37 3 .1 Introduction 37 3 . 2 Instruction Decoding UO 3.2.1 Instruction Variant and Number Type Decoding . ... UO 3.2.2 Decimal Operand Sign Register and Decoder (DOSIREP) 1+3 3.2.3 Logic Implementation kh 3.3 V-Bus Input Operand Load (VIN) Control Sequence U5 3.3.1 Global Floy Description U6 3.3.2 Control-Point Flow Description 50 3.3.3 Logic Implementation 5^- 3.U Result Formatting and Transmission (REFOTRAN) Control Sequence 55 3.U.1 Global Flow Description 55 3.^.2 Control Point Flow Description 57 3.U.2.1 EXIT 57 3. h. 2. 1.1 N0RMUQ 59 3.U.2.2 SFBIN 61 3.U.2.3 X-0UT 65 3 . h . 3 ' Logic Implementation 68 3-5 Add, Subtract, Compare Algebraic (ASC) Instructions Control Sequence 69 3-5.1 Global Flow Description 70 3.5-2 Control-Point Flow Description 72 3.5.2.1 OPACAS 72 3.5.2.1.1 ALNUH 75 3.5.2.1.2 ALNUQ 77 3.5.2.1.3 UHTUQ 79 3.5-2.2 CAL 81 3.5.2.3 ASIM 87 3.5.3 Logic Implementation 89 VI 1 Page 3.6 Multiply (MPY) Instruction Control Sequence 90 3.6.1 Global Flow Description 91 3.6.2 Control-Point Flow Description 93 3.6.3 Logic Implementation 98 3 . 7 Divide Instruction Control Sequence 99 3.7-1 Global Flow Description 100 3.7.2 Control Point Flow Description 10** 3.7.2.1 DFL 10U 3.7.2.2 DIVIDE 107 3.7-2.3 DFX 113 3.7.3 Logic Implementation 120 3.8 Number System Conversion Control Sequences 121 3.8.1 Introduction 121 3.8.2 Conversion to Long Fixed Point (CVL) Control Sequence 122 3.8.2.1 Global Flow Description 123 3.8.2.2 Control-Point Flow Description 126 3.8.2.2.1 CVL-FLT 127 3.8.2.2.2 FL-N0RM-FX 131 3.8.2.2.3 CVL-DEC 133 3.8.2.2.3.1 DVB 135 3.8.2.2.1* ujp^ 139 3.8.2.2.5 COMPL lUl 3.8.2.3 Logic Implementation 1U3 3.8.3 Conversion to Floating Point (CVF) Control Sequence ikk 3.8.3.1 Global Flow Description ll*5 3.8.3.2 Control-Point Flow Description ikf 3.8.3.3 Logic Implementation ll*9 3.8.U Conversion to Decimal (CVD) Control Sequence . . . . 150 3.8.1*.l Global Flow Description 151 3. 8.1*. 2 Control Point Flow Description 15U 3. 8.1*. 2.1 CVD-FIXOCAFLOX 155 3. 8.1*. 2. 2 GETDEC 158 Vlll Page 3.8.U.2.3 GETDIG l6h 3.8.U.2.J+ SETSIGN . . 166 3.8.U.3 Logic Implementation 168 3.9 Initialization and Power Turn-On 169 3.9.1 CREST 170 3.9.2 Power Turn -ON 172 3.10 'Miscellaneous' Control Logic 173 3.10.1 Electronic Push-button Selector Switches Yjk 3.10.2 Single Step Mode 175 3.10.3 Final Level Task Drivers 178 h. AU DRIVER INTERFACE 179 k.l Introduction 179 h .2 Control Logic to Processing Hardware Driver Interface . . 180 k .3 Processing Hardware to Control Logic Driver Interface . . l8l 5. CONTROL LOGIC DRAWINGS AND THEIR INDEX 182 6. CONTROL SIGNAL NAMES AND THEIR FUNCTIONAL DESCRIPTION 263 BIBLIOGRAPHY 280 APPENDIX A.O Introduction 282 A. CONTROL POINT - A BUILDING BLOCK APPROACH 283 A.l Description 283 A. 1.1 Task Stage 28U A. 1.2 Timing Stage 289 A. 2 Sequence Stage 296 IX LIST OF FIGURES Figure No. Page 2.2.1.1 Symbols Used in a Task Stage 6 2.2.2.1 Sequence Stage and Control Step Illustration. ... 10 2.2.3.1 Control Point Flow Chart "Entry", "Exit" and Subroutine Terminal Symbols 12 2.2.U.1 "JOIN" Symbol for Interlocking Parallel Control Chains lU 2.2.5.1 Miscellaneous Symbols Used in a Task Stage lU 2.2.5.2 Representation of a Logical Condition on the 'Enable' Input of a Control Point for Asynchronous Operation 16 2.3.1 Martin's Basic Control Point 18 2.3.1.1 Martin's Control Point with a Modified Memory Element Reset-Logic with Delayed Initiation Only . . 20 2.3.1.2 Martin's Control Point with a Modified Memory Element Reset Logic with Delayed Priming and Initiation of Next Control Point 21 2.3.1.2.1 Delayed Task Generation Control-Point, its Symbolic Representation and Timing Diagram. . . 22 2.3.1.3.1 Calling Control- Point , its Symbolic Representation and Timing Diagram 2U 2.3.1.U.1 Interlocking of Two Parallel Independent Control Chains (Subsequences) 26 2.3.2.1.1 Task Stage Symbols and Corresponding Control Point Symbolic Representation 28 2.3.3.1.1 Control Point (Without Memory Element Reset) Standard Symbolic Representation 32 3.3.1.1 Global Flow Diagram for "VI N — Input Operand Load from V-Bus and Branch to Appropriate Arithmetic Order Control Sequence U7 3.3.1.2 Order of Word Transmission to AU kQ Figure No, Page 3.3.2.1 FIWLOB — First Word Load and Branch. 51 3.3.2.2 SEWLO and BRAIN — Second Word Load and Branch to Appropriate Instruction 52 3.3.2.3 TIFOWLOB— Third and Fourth Words Load and Branch 53 3.^.1.1 Global Flow Diagram for "REFOTRAN— Result Formatting and Transmission" Control Sequence. . . 56 3.1*. 2.1 EXIT 58 3. h. 2. 1.1 N0RMUQ— Normalize UQ 60 3. k. 2. 2.1 SFBIN— Set Flags, Bogus and Arithmetic Indicators 63 3.U.2.2.2 Flag Bit Designation for Arithmetic Indicators . . 6h 3.U.2.3 X-0UT— Transfer Result to Processor via Exchange-Net 67 3.5.1.1 Global Flow Diagram for "ASC— Add, Subtract and Compare Algebraic" Control Sequence 71 3.5.2.1 ASC_OPACAS — Add, Subtract, Compare Algebraic -Operand Alignment Call Set-Up 7^ 3.5.2.1.1 ALNUH— Align Contents of Register UH 76 3.5-2.1.2 ALNUQ— Align Contents of Register UQ 78 3.5.2.1.3 UHTUQ—Transfer Contents of Register UH to Register UQ 80 3.5.2.2.1 Boolean Expressions for Control Signals NEG0 , NEG1 and SR, for a priori predictability of sign of Result 85 3.5.2.2 CAL — Sum or Difference Calculation 86 3.5.2.3 ASIM — Conversion from Signed-Digit to Conventional Representation 88 3.6.1.1 Global Flow Diagram for "MPY— Multiplication Process (Fx. Pt . and PI. Pt . ) " Control Sequence. . 92 3.6.2.1 MPY_REPROG— Multiply (Fl. Pt . and Fx. Pt.) — Redundant Form Product Generation 96 XI Figure No. Page 3.6.2.2 MPYEND — Conventional Form Product Formation and 0V Status Indicator Set-Up. ..... 97 3.7.1.1 Global Flow Diagram for "DIV — Division Process (Fx. Pt. and Fl. Pt . ) " Control Sequence 103 3.7.2.1 DFL — Floating Point Division 106 3.7.2.2.1 DIVIDE—Redundant Form Quotient Generation. . . . 110 3.7-2.2.2 DIVIDE — Redundant Form Quotient Generation. . . . Ill 3.7.2.2.3 Block Diagram of MODEL DIVISION Logic 112 3.7.2.3.1 DFX_DIZETC0M — Fixed Point Division— Divisor/ Divident Zero Test and 2's Complementation. . . . llU 3.7.2.3.2 SCALFIXDR— Scale Fixed Point Divisor and Divident 115 3.7-2.3.3 FORMQAREM — Form Quotient and Remainder 116 3.7-2.3.U COSREM — Correct Sign of Remainder 117 3.7.2.3.5 QASS — Quotient Assimilation into Conventional Representation 118 3.7.2.3.6 RES CALEREM— Remainder Posts caling 119 3.8.2.1 Global Flow Diagram for "CVL — Conversion to Long Fixed Point" Control Sequence 125 3.8.2.2.1.1 CVL_FLT — CVL Floating Point Operand 129 3.8.2.2.1.2 NEGATE— Negate a Positive Number 130 3.8.2.2.2.1 FL_N0RM_FX— Convert a Floating Point Operand to Fixed Point Operand 132 3.8.2.2.3.1 CVLJDEC— CVL Decimal Operand 13U 3.8.2.2.3.2 DVB— Decimal to Binary Conversion 137 3.8.2.2.3.3 DVB — Decimal to Binary Conversion 138 3.8.2.2.U.1 LUQ— Left Adjust Contents of Register UQ lUO 3.8.2.2.5.1 COMPL— Form 2»s Complement of the Contents of Register UQ lU2 XI 1 Figure No. Page 3.8.3.1.1 Global Flov Diagram for "CVF — Conversion to Floating Point" Control Sequence . 146 3.8.3.2.1 CVF_DEFIX— CVF Decimal and Fixed Point Operands. . l48 3.8.4.1.1 Global Flow Diagram for "CVD— Conversion to Decimal" Control Sequences 153 3. 8. 4. 2.1 CVD_FIXOCAFLOX--CVC_Fixed Point Operands' Complementation and Floating Point to Fixed Point Conversion 157 3.8.4.2.2.1 GETDEC_CAQOREM— Generate Decimal Digits- Calculation of Quotient and Remainder 162 3.8.4.2.2.2 GETDEC_QUODECM— Generate Decimal Digits — Quotient Decrement 163 3. 8. 4. 2. 3.1 GETDIG— Transfer Decimal Digits to Result Register UQ 165 3. 8. 4.2. 4.1 SETSIGN— Set Proper Decimal Sign Code in Result Register UQ 167 3.9.1.1 CREST— Clear and Reset 171 3.10.2.1 Illustration of Single Step Mode 177 A. 1.1.1 Block Diagram of Task Stage Logic 285 A. 1.1. 2 Most Elementary Task Stage Configuration 286 A. 1.1. 3 Multiple "Advance In" Input to Memory Element. . . 287 A. 1.2.1 Timing Stage Using Internal Delay Element 290 A. 1.2. 2 Timing Stage Equivalent Circuits 292 A. 1.2. 3 Delay Circuit with Diode to Enhance Recovery . . . 294 A. 1.2. 4 Timing Stage Using External Reply 294 A. 1.2. 5 Control Point Block Diagram and Circuit Configuration 295 A. 2.1 Two Way Branch Sequence Stage Logic 297 A. 2. 2 WAIT Condition Using EN Gate 299 XI 11 Figure No. Page A. 2. 3 Wait Condition Using A Line 300 A.2.U Interlocking Two Parallel Control Chains 301 A. 2. 5 "Calling Control Point" Circuit Configuration. . . 303 1 . INTRODUCTION This report is the second volume of Illiac III computer system manual on arithmetic units. The first volume described the various arith- metic orders to "be executed in the arithmetic unit and the internal static description or in other words, the processing hardware of the Arithmetic Unit. This volume describes the control logic hardware and gives its operational description. This report assumes that the reader is familiar with previously- published reports and documents regarding the arithmetic unit. In particular the familiarity with the following documents is very essential. DCS Report No. 366: "Illiac IV Computer System Manual: Arithmetic Units, Volume 1 by D. E. Atkins - This describes the processing hardware consisting of various registers, data paths, SDS-array, multiplier, recoder, model division and shifting network of the arithmetic unit. DCS Report No. Ul8: "Arithmetic Unit of Illiac III: Simulation and Logical Design - Part II by P. L. Koo, D. E. Atkins. Revised by L. N. GOYAL - November 10, 1970". - This report describes the control algorithms for the execution of various arithmetic orders and their simulation at a very detailed, almost hardware level. The present report does not describe the control algorithms in detail bat assumes that the reader is familiar with them from Report No. Ul8. The author recommends that the present report should be read after reading once more the Report No. Ul8 and then keeping Report No. Ul8 always in close proximity. This report is divided into various sections and subsections. The ; major sections are Strategy of Control Design, Control Point Flow charts and their description, Control Logic and Processing Hardware Interface and func- tional description of control signals. Section 2 describes the technique of control point design, the various variations of control points, conventions and notations "both in control point flow charts and the various logic drawings that implement them and can he read independently of any other section. Section 3 gives the control point charts for the control sequences and subsequences necessary for the various arithmetic orders to be executed in the arithmetic unit. An operational description of the control sequences and subsequences is also given, both in an overall global sense as well as in more detailed local sense. Besides the control sequences for various arithmetic orders, some other related logic is described and is grouped under the heading "Miscellaneous" . Section k describes briefly the interface logic between the control logic hardware and the processing hardware which have been implemented wixh different logic families - the former with TTL and the latter with DTL. Section 5 shows an index of the control logic drawings, followed by a set of these drawings. Section 6 is an alphabetized list of control signal names together with their functional definition. This list includes many signal names whose definition already appears in Volume 1, DCS Report No. 366. Finally, there is an appendix at the end. It should be noted that this report is a working document for the design, construction* checkout and maintenance of the arithmetic unit for Illiac III. It is an evolving document and vill he updated specially as the checkout reveals any deficiencies. Readers are encouraged to bring to the author's attention any errors and suggestions. 2. STRATEGY OF CONTROL DESIGN 2.1 General Remarks The control of the arithmetic units essentially consists in executing a time-ordered sequence of elementary micro-operations like operat- ating of ates, the setting or clearing of a flip-flop etc. This time-ordered sequence can "best be illustrated as in computer programming, with a flow chart. Each control sequence in the arithmetic unit (AU) has been broken down into control steps. A control step consists of two stages: the Task Stage and the Sequence Stage . In the task stage, elementary micro-operation (s ) is (are) per- formed conditional upon status conditions on the processing hardware i.e., gates are operated, counters incremented etc. Within the sequence stage, the decision is made as to which task stages to initiate next. The sequence stages are interleaved with the task stages. The control steps are performed by logical circuits called control points. Hence the control flow charts are called Control Point Flow Charts. 2.2 Control Point Flow Chart Conventions A control point flow chart essentially consists of task stages inter- leaved with sequence stages "besides the entry point (s) to and exit point (s) from the flow chart. 2.2.1 Task Stage : A task stage indicates all the elementary micro-operations, condi- tional and/or unconditional, that can be performed at that instant of time in the time-ordered sequence of events. This elementary micro-operation or a set of these micro-operations (unconditional or conditional on the same status con- dition) is called a task. A task is designated by a rectangular box with an input from the top and an output, a reply, from the bottom such as shown in Figure 2.2.1.1a. The arrowheads indicating directions of flow are optional. If they are not shown, flow is assumed to be from top to bottom. Within the task box are written the signal names which are operated to execute the task, when the task box is entered during the control flow. However, at times» instead of the signal names, we write a micro-operation in the format X •«- Y where X is the dependent variable (a flip-flop in actual implementation) and Y is the independent variable. This is shown in Figure 2. 2. 1.1. bo Associated with each task is a certain duration of time after which a reply signal is generated and control proceeds along the exit line of the box. When more than one task is initiated concurrently, the conditions which must exist for the task to take place are indicated above the task entry line as shown in Figure 2.2.1.1c. The task condition "none" indicates that the initiation of task requires only an initiating signal from the previous stage S0V SCNTICCUP SICCEQ14 ' ' FM — FLMTCH EQ-UQEZ GT^SR-UQEZ ' (a) Task Box (b) Task Box Til l(none) TI 2 1 xyz- ■i • xyz - i 1 xyz- TASK A TASK C TASK B i 1 ^.^ (c) Task Stage (From Task Condition Delayed Task Generation (DETAG) e) Subroutine (Control Subsequence) Call Figure 2.2.1.1. Symbols Used in a Task Stage and -will always be performed once that task stage is entered. Note that the task conditions need not "be mutually exclusive. The tasks whose reply signals merge on the same horizontal line are assumed to he of the same duration. In terms of hardware, this means that they may share the same timing model and hence all these task signals are capable of being generated by a single control point. The delay of the timing model used in the corresponding control point is £. the largest operating time of all the tasks whose reply lines merge on the same horizontal line. Another symbol used, at times ? in the task stages of the control flow chart is a rectangular task box divided by a horizontal line towards the bottom as depicted in Figure 2.2.1.Ld. The task signals are written in the box both above and below the line. The interpretation of this box is that the signals written below the line are to be turned on, a controllable delay later than the task signals written above the line. Such task boxes are very suitable for indicating the loading of a register from another. The signal above the line will select the source register to the input of the register being loaded. After the selector gets settled, the load signal (essentially equivalent to a gating signal) written below the line is turned on. In this way one can affect a savings in control points during the implementation. Still another rectangle with a dividing vertical line at each end of the box (Figure 2.2.1.1.e) is used for indicating a subroutine or procedure call. This symbol is identical to the predefined process symbol of ANSI flow chart standards. The control sequence of the arithmetic units has been divided into Procedures and Subroutines. A subroutine is a control logic subsequence which can be called from different parts of the same sequence or even from different 8 control sequences. The obvious reason for this type of structure is that it reduces the logic by allowing common subsequences to be done using the same physical logic. Similarly a Procedure is also a control logic subsequence. However the difference between a Subroutine and a Procedure is that when a control subsequence corresponding to the Subroutine is finished, the reply signal from the subsequence must return to the point, where it was called in the main sequence so that the control flow can continue. But, in the case of the Procedure, the control flow essentially branches off from the main sequence, and at the end of the Procedure subsequence, the reply signal can continue to do other tasks, call Subroutines or go to other Procedures. The advantage of so dividing the control logic sequence into Procedures and Sub- routines is that it is easier to visualize conceptually when it is placed in such a modular format, and is also easier to debug and checkout. In actual hardware, a subroutine call is implemented by a special kind of Control Point called Calling Control Point. (For more details see section 2.3.1.3). In the symbol for subroutine call task, is written the name of the subroutine. The task signal initiates the subroutine control logic subsequence, and the reply from the subsequence is returned to the task stage where this subsequence was called (i.e., initiating signal was generated) so that the control flow for the sequence can continue. It may be noted, however, that, at times, the names of the other task signals may also be written in the box in addition to the subroutine name. This means that these elementary micro-operations are to be done in parallel with the execution of the subsequence. A set of these task blocks, external conditions for entry to a task "box (e.g. contents of a register equal zero) and reply generation facilities con- stitute a Task Stage . Each task rectangle is labelled with the name of that task stage. The label has the format XYZ-i where XYZ is the name abbreviated from the sequence name and i is a numerical number. This label is also the name of the control point executing this task stage. 2.2.2 Sequence Stage Interleaved between task stages are sequence stages: that portion of control which determines which task step (stage) or subsequence is executed next. The sequence may cause a branch to another subsequence of control flow. This subsequence called a Procedure is identified by the same symbolic box as for Subroutine call in the task stage, with the name of the Procedure subsequence written inside the rectangle as shown in Figure 2. 2. 2.1. a. This facilitates the description of the Procedure Subsequence on a different flow chart of the same main sequence. The branching conditions or the Sequence Conditions (SIj) are shown in the same way that the Task Conditions (TIj ) are shown in the task stage. A task stage followed by a sequence stage constitutes a Control Step . On the flow charts, the boundary between task stage and sequence stage is indicated by horizontal dashed line. It is shown in Figure 2.2.2.1.b. In the sequence and task conditions SIj and TIj respectively, I stands for the number of the control step which is the same as numerical number i in the name of the task stage and j identifies the number of the condition (task 10 (From Sequence Condition) (a) Sequence Stage Branch to a Procedure (Control Subsequence' Control Step I Task Stage I Sequence Stage I TASK y TASK B (b) A Task Stage Followed by a Sequence Stage Figure 2.2.2.1. Sequence Stage and Control Step Illustration Task Stage! 11 or sequence) within that control step. The Boolean equations for the task and sequence conditions are also shown on the flow chart. Note that the Procedure subsequences (or branches) are initiated by the sequence steps and Subroutine subsequences are initiated by task steps. 2.2.3 "Entry" and "Exit" Symbols The single circle(s) represent (s) the Entry point(s) to a new control block (i.e., a subsequence) or a new page of the flow chart when it appears at the top of the page. The double circle indicates the Exit from the page, when the whole sequence or subsequence can't be fitted on one page. These two symbols are shown in Figures 2. 2. 3.1. a and 2.2.3.1.b respectively. In case of multiple entry points to a flow chart, the name of the control step where the entry takes place is written in the Entry circle. In case of single entry, where no confusion is created, the name of the control step may or may not be written. Every double Exit Circle must have a corresponding entry circle in the collection of flow charts. Inside the Exit Circle, we write the same name as the name in the corresponding entry circle. Note that an exit from a page or control flow also takes place when the sequence stage causes a branch to a Procedure subsequence indicated by the Procedure/Subroutine rectangle. Finally, a terminal symbol (Figure 2.2.3.1 .c) also appears on the flow charts which indicates the end of the main sequence or a Subroutine subse- quence. In case of Subroutine, the word 'RETURN' is written inside the terminal symbol signifying that the control should return to the calling point in the 12 (a) 'Entry' Symbol (b) 'Exit' Symbol RETURN (c) Subroutine Terminal Symbol Figure 2.2.3.1. Control Point Flow Chart "Entry", "Exit" and Subroutine Terminal Symbols 13 main sequence. In case of the end of the sequence, the word 'OUT' is written to indicate that the sequence is ended and the control should go out of this sequence. Figures 3.7.2.1 and 3.7.2.2.1 illustrate an example of use of task and sequence stages, entry and exit circles, etc. in one control point flow chart. 2.2.H "JOIN" Symbol This is required when two control subsequences are initiated in parallel and if the control flow demands that both the subsequences be finished before the control flow can proceed further. A symbol shown in Figure 2.2.U.1 and resembling a Pentagon called "JOIN" is used to indicate that the replies from both the subsequences must be true before the control flow can go on. An example of its use is given in the flow chart for GETDEC in Figure 3. 8. k. 2. 2.1. 2.2.5 Miscellaneous Notations It was stated earlier that in the Delayed Task Generation (DETAG) rectangle, the task signal below the horizontal dividing line was the delayed task signal. In some cases, no task signal name appears below the horizontal dividing line, but. rather a wait is indicated for some logical circuit or condi- tion to settle down. This notation is used simply to indicate that a Control Point with two cascaded timing models are used in the physical realization of Control sequence. For an example, see the DETAG rectangle CVD-11 in the flow chart for GETDEC in Figure 3. 8. h. 2. 2.1. Sometimes, instead of task signal names, the word "Dummy" is written inside the task box. It indicates that no control signals are activated and tk Figure 2.2.U.I. "JOIN" Symbol for Interlocking Parallel Control Chains DUMMY Wait for Data to propagate through SDS -Array and propagation logic circuit Figure 2.2.5.1. Miscellaneous Symbols Used in a Task Stage 15 has no logical significance, but is added for hardware considerations. Similarly, instead of the word "Dummy" , a wait may be indicated for some logical condition or circuit to stabilize. An example of each of these occurs in the control- point flow charts for DVB and CAL respectively as' shown in Figures 3.8.2.2.3.2 and 3.5.2.2. When conditions other than Manual ENable (MEN) are present on the ENABLE (EN) input of a control point, these conditions are indicated as shown in Figure 2.2.5.2. If no conditions are shown, then it is assumed that the control point is enabled unless the maintenance stop is activated. 16 O- TK, tTK. TASK A TASK B TK, TASK C Y = Boolean expression to represent the logical condition on EN input of corresponding control point Figure 2.2.5.2. Representation of a Logical Condition on the 'Enable ■ Input of a Control Point for Asynchronous Operation 17 2.3 Logic Implementation of Control-Point Flov Charts As stated in the previous section, the control flow charts specifying the time-ordered sequence of micro-operations are implemented in logic by a basic building block called control point (Figure 2.3.1) and its few variants. The flow charts are specifically so drawn that there is one to one correspondence between the flow charts and the logic implementation. The task stage of each control step is implemented by the control point and the sequence stage is realized by a sequence stage combinational logic. The basic control point used in the Arithmetic Units' Control is the same as described by R. Martin in DCS Report No. U00. For completeness sake, his description is reproduced in the appendix at the end. However, certain modifications have been made, and they are described in the following sections. 18 o -p c > I ° l< -P o «. < .^-|ii- cd •H Q d a •H O a3 -P a; Q O (h -P C o o en a) PQ P C\J CD 19 2.3.1 Modifications to Martin's Control Point 2.3.1.1 Memory Element Reset Logic A modification has "been made in the feedback path "between Advance-out, Ao, and the reset input, Rs , of the memory element in the control point. A signal called GODELY is used to delay the resetting of the memory element of the presently active control point which in turn delays the priming and/or initiation of the next control point in the control flow sequence, as shown in Figures 2.3.1.2/1. This facility of GODELY is used for single stepping through the control points during the check-out. Note that in case of Martin's strategy, configuration of Figure A. 2. 2 using EN gate was used for diagnostic and check-out purposes. 2.3.1.2 Delayed Task Generation (DETAG) Control Point As mentioned earlier in Section 2.2.1, the task stage uses a DETAG rectangle in which the control signals written below the horizontal dividing line should be turned on a little delay later than those written above the line in the box. This is physically realized by essentially having two cas- caded (in series) timing models. However, the other timing model is placed in the feedback path and the regular Ao becomes second D02 (Do Task) signal. The Advance-out, Ao' , is produced as shown in the Figure 2.3.1.2.1. The same configuration of cascaded timing models is also used when the delay needed in the timing model is very large. This is to avoid the use of a large capacitor at one input of the Nand gate of the timing model. 20 GODELY (a) Symbolic Representation GODELY Figure 2.3.1.1 (b) Timing Diagram Martin's Control Point with a Modified Memory Element Reset-Logic with Delayed Initiation Only 21 i» . Ai CC RS EN DO A — *- ■ dC / cf H * ' \ GODELY (a) Symbolic Representation EN DO- GODELY- Ao.RS- Figure 2.3.1.2 ■A r (b) Timing Diagram Martin's Control Point with a Modified Memory Element Reset Logic with Delayed Priming and Initiation of Next Control Point 22 A rt -» GODELY a) Symbolic Representation GODELY A n ,RS Figure 2.3.1.2.1 (b) Timing Diagram Delayed Task Generation Control-Point, its Symbolic Representation and Timing Diagram 23 2.3.1.3 Calling Control Point As mentioned in Section 2.2.1, the calling control point is used by a control sequence to call another subsequence just as the main program calls a subroutine. The logic implementation and operation of calling control point is exactly indentical to Martin's calling control point as described in Section A. 2 of the appendix. Figure 2.3.1.3.1 shows the circuit configuration and timing diagram for the calling control point. The calling control point (CCP) generates a pulsed task signal which has a labelling format 'CALL Subroutine Name'. It goes to set a control flip- flop and at the same time initiate the first control point of the called sub- routine control sequence. This control flip-flop appears on the same logic drawing and the same logic card as the subroutine control sequence. As soon as this control flip-flop is set by the calling control signal, a reply signal from the quiescently '1' side of the flip-flop output goes down and inhibits the resetting of calling control point. As soon as the called subroutine control sequence has finished, the control flip-flop is reset and the reply signal goes up to '1' state to remove the inhibition on control point reset logic. If no other control signal, for example, GODELY, wants to inhibit the resetting of control point, the calling control point is reset and at the same time, the resetting control signal primes the next control point in sequence. For an example of the calling Control Point and its use, see the con- trol subsequence MPYEND whose control point flow chart is shown in Figure 3.6.2.2 of Section 3.6.2. In this subsequence, task stage MPY8 is implemented with a calling control point MPY8 shown in Drawing AUO-OT-361-02 and calls the subroutine control sequence ASIM. Logic implementation of control subsequence ASIM is An- * CC RS < EN DO <3 CALLASIM <»A •ASIMWAIT GODELY (a) Symbolic Representation 21+ DO CALLASIM ASIMWAIT A ,RS ■A L h i i (b) Timing Diagram Figure 2.3.1.3.1. Calling Control-Point, its Symbolic Representation and Timing Diagram 25 shown in Drawing AUO-0T-3T1-OU. The control signal ASIMWAIT is the reply signal which inhibits the resetting of calling control point MPY8 till the resetting signal of control point ASM2 resets the control flip-flop. It should he clearly noted that since the logic cards for the called control subsequence may he located quite far from the logic of calling control sequence, the time dealy in calling control point (which also determines the width of pulsed calling task signal) should he large enough so that the reset inhibit reply control signal from the subroutine wait-reply control flip-flop becomes effective lest the calling control point should be reset prematurely. t 2.3.1.U Interlocking of Two Parallel Independent Control Chains Whenever two (or more) independent control chains (subsequences) are started in parallel, a flip-flop for each control chain is set to indicate that the control chains are active. When each control subsequence finished (in general they will finish at different times), each resets its corresponding active flip-flop. When both (or all in case of more than two) flip-flops are reset, then and only then the control is allowed to advance to the next control point in sequence. This approach, though slightly expensive because of the use of an extra flip-flop for each subsequence, is more useful for diagnostic pur- poses, since the active status of the subsequence is indicated by the true output of the flip-flops. This is shown in the Figure 2.3.1.^.1. 26 _J >- UJ Q o Oj c a CD a 1 03 en C ■H ,£ O o fn -P C o o +J a; ft H cti in ni o Cm O a o 0) -p a H CM OJ %-, bD 27 2.3.2 Conversion of Control Flow Charts into Control Logic Prayings Logic implementation of the flow charts result in three "broad categories of drawings. They are: a) Control Point Drawings (CPD), b) Task Signal Collector Drawing (TSCD) and c) Task Driver Drawing (TDD). 2.3.2.1 Control Point Drawing CPD's are the drawings which implement the task and sequence stages of the flow charts with the help of control points and combinational logic. The control flow charts are so designed and drawn that there is almost one to one correspondence between the logic drawing and the control flow charts. The task stage is implemented by an appropriate control point and the sequence stage by a combinational logic. As explained earlier, there are three kinds of 'rectangular' symbols used in the task stages of Figure 2.3.2.1.1. shows the corresponding control point symbolic configuration used to implement the task stage. (See also Section 2.3.3.1.) In most cases, each flow chart has one separate logic drawing, although in a few cases, one flow chart has its corresponding logic implementa- tion spread out on more than one drawing. Similarly, two flow charts may share the same logic drawing. Each logic drawing is given a title which is the same as the name (or names) of the Control Sequence, Procedure, or Sub- routine, the logic drawing is implementing. This helps in correlating the flow charts and the logic drawings. Further, the names of the control point imple- menting a given task stage is the same as that of the task stage (i.e. the Control Point Flow Chart Task Stage Symbol Corresponding Logic Drawing Control Point Symbol RS Tl <3=^<3 GODELY Tl T2 ES. < Ac Tl u <__} GODELY T2 ii CALLASIM Ai Ii < o ASIMWAIT GODELY Figure 2.3.2.1.1 Task Stage Symbols and Corresponding Control Point Symbolic Representation 29 label written on the task boxes of the task stage). Any exceptions to the above-mentioned general rules are indicated, wherever deemed to be necessary, in the documentation. 2.3.2.2 Task Signal Collector and Task Driver Drawings The Control sequence for many arithmetic instructions (e.g. DIV (Division), and CVD (Convert to Decimal) etc.) is composed of many control subsequences (Procedures and Subroutines). Many of these control subsequences form separate logic drawings. Task signals with the same functional name (and hence significance) may appear on different drawings of the sequence because they are made active quite often at different time instants in the control sequence. All these task signals with the same functional significance and appearing more than once in the control sequence for any arithmetic instruction are logically ORed together on the Task Signal Collector (TSC) drawings. Since all the task signals with the same functional significance from different sequences will have to be logically combined into one single control line to provide the final control signal to the processing hardware to do the task, it is better to group these signals first locally within each sequence and then from these various groups into the final control signal. The former grouping of signals within the same sequence is done on Task Signal Collector Drawings and later grouping to generate the final control signal is done on Task Driver (TD) Drawings. For example the drawings 370-12, -13, -lh and 38U-06 are the TSC drawings for control sequences DIV and CVD and 388-01, -02, -03 are the TD drawings. Thus, the inputs to the TSC drawings are output signals from control point drawings and their outputs go to the input of TD drawings . 30 The outputs of TD drawings are cable driven to the input of the processing hardware to perform the required task. This hierarchical grouping of signals provides a modular way of collecting signals, and in case of future necessity, other signals can be easily added. The hardest part in designing such drawings is partitioning the output control signals on the control point drawings among the TSC drawings so that the total number of pins used on these drawings or cards is minimal. To do so it is necessary to place the grouping logic for signals, which are often turned on by the same control point task signal control lines, together on the same card or TSC drawing. This allows one input pin on a card to be used for turning on more than one functional control signal. Unfortunately this can be an extremely time consuming process. 31 2.3.3 Control Logic Drawing Conventions and Notations This section describes the symbolic notation used for the representa- tion of a control point, the signal name conventions for the output of both the control point conditional task logic and the sequence stage logic. Ik addition, the signal name conventions for the "Task Signal Collector" and "Task Driver" drawings are also described. 2.3.3.1 Control Point Standard Symbolic Representation In this paper, a control point is understood to consist of not only the memory element and the timing stage (as in Martin's Case), but also the logic associated with the feedback path between the output of timing model and the reset input of the memory element (Figure 2.3.2.1.1). For ease of use, the combination of memory element and the basic timing model is represented on the main logic drawings by one of the symbol used in Figure 2.3.3.1.1. Note that the various input and output signals are indicated by letters at the points where they enter and leave the box. The upper part of the symbol is divided into either two or three boxes (depending on the control point variant being used) which represent the chips used to implement the control point logic. The letters at the center of each box represent the location of these chips on the printed circuit board. The four boxes in the lower part of the symbol are used to describe parameters for the control point. The left most box contains the control point delay in nanoseconds. The second box is unused at present. The third and fourth boxes contain the control point variant name and the unique name for that point respectively. The variant types are described by a 3 or h character 32 " 4 i > EN IN DO A^ cc Dl RS DO Al D2 — -* 30ns AOl ASC-1 (a) Single Input Control Point _ IN Aji ^ 2 Dl cc U1 RS 20ns EN DO D2 BOi DO CI Ao ASC-2 (b) Two Input Control Point Figure 2.3.3.1.1. Control Point (Without Memory Element Reset) Standard Symbolic Representation 33 code in which the first letter represents the general type of control point, the second and third numbers represent the variant number and the last letter (always a D, if it is present at all) indicates that a speed up diode is used. The unique name associated with the control point is the same as that associated with the task stage (or its various task "boxes) it is used to implement. Accordingly, the name has the format XYZ-i were XYZ is the name abbreviated from the sequence or subsequence name (to give some functional significance to the control point) and i signifies that it is the ith control point (hence the task stage) out of a totality of control points used to implement that sequence or subsequence. In a few cases, four letters are also used to indicate the name. IN signifies Indicator. This output from the control point is used for monitoring the Active/Inactive status of the control point. It is very useful for check-out and/or for display at the engineering console. On the logic drawings, the inputs CC (Common Clear) and EN (Enable) to the control point are now shown on the standard symbol for the control point although they are supposed to be present. However, EN is shown specifically in those cases where an external conditional logic is attached to this input of the control point. 2.3o3.2„ Control Point Signal Name Conventions Associated with each control point (including conditional task logic) are output control lines which carry control signals, input lines carrying task conditions and/or variables making up the task condition (external conditions), 3k the Advance-in and Advance-out signals and the indicator signals. All the control lines except those carrying external conditions have the name of the corresponding control point associated with it. A task control line carrying one or more control signals is labelled XYZiTn where XYZi is the name of the control point, T stands for task and n indicates that it is the nth task control line associated with that control point. In case of DETAG control point, the delayed task control line is labelled as XYZiDTn where XYZi and n have the same meanings as before and DT stands for delayed task signal. Note that one control line may activate quite a few control signals and the functional names (abbreviated from the type of control function they perform) of these control signals (which are the same as written in the task boxes of the task stage) are also written on the control line. This helps in identifying the functional (in the control sense) significance of the particular control lines. In general, there are as many control lines as there are task boxes in one task stage. However, if on the same logic drawing two or more control points have control lines carrying the same functional control (task) signals, the control lines are logically-ORed together to form only one output control line so as to make better use of available pins on the control logic card. The input control line directly connected to the Advance-in input of the control point carries the functional name XYZiAI where XYZi is the name of the control point. Nothing specific can be said about the control line name because in general it can come from different parts of the control logic. Quite often it will come from the sequence stage of other control points. 35 Each control point has an indcator output IN. This indicator control line (via a driver) is labelled XYZNi where XYZi is the control point name and N stands for the indicator. Note that the numerical part (i) of the name appears at the end of label unlike the task control line label. 2.3.3.3 Sequence Stage Signal Name Convention Following each control point, there is the sequence stage which is essentially combination logic. The input to this combinational logic are the variables making up the sequence condition and the Advance-out signal of the control point. If the output of the sequence stage is connected to some logic on the same logic drawing, then this output is not labelled. However, if it goes to an output pin on the card (because it is connected to a control point on some other drawing and hence PCB) then the corresponding control line is identified as XYZisn where XYZi is the control point name, s stands for sequence stage and n indicates that it is the nth sequence control line for that sequence stage. The functional name associated with the sequence control line is either the name of the Procedure which it initiates or a name with a format XYZiAI where XYZi is the name of the control point which it primes and initiates . 2.3.3. 1 * "Task Signal Collector" and "Task Driver" Drawings' Signal Name Convention The input signals to the TSC drawings are the control point task signal control lines and hence carry the label format XYZiTn whose interpreta- tion is explained earlier. The output signal on the TSC drawings are identified by the functional name of the signal followed by a slash and either of the 36 letters A, B, CD or E. Each of these five letters identifies the TSC drawing signals as heing the result of logical OR of control point task signal control lines from a different set of drawings. For example the letter B identifies the signal as belonging to the set of drawings 370-On (n = 1, 2, .... 12) for DIV instruction control sequence. These letters are necessary to uniquely identify electrically distinct nodes although logically they may he the same. However, in those cases where one physical node on TSC drawing activates, simultaneously, functionally distinct signals, this node carries a label with a format ZYZTDn, where XYZ stands for the sequence name and n is a numeric (n = 1, 2, ....), whose value signifies that it is nth signal node in the TSC drawings for that sequence, for example, the signal node CVDTB~ on TSC Drawing No. 38U-06. Just as in control point drawings, the functional names of all the signals associated with this signal node are written on the line. The inputs to the Task Driver drawings are the output signals from TSC drawings and hence carry the label XYZTDn. The output signal nodes of the Task Driver drawings are labelled the same as the corresponding input nodes of the processing hardware to which they are to be connected. These labels are the functional names of the control signals. For an example, see the output node labels on Drawings 388-01, -02, -03. 37 3. CONTROL SEQUENCES, CONTROL-POINT FLOW CHARTS and THEIR OPERATIONAL DESCRIPTION 3.1 Introduction This section describes the control sequences for the execution of various arithmetic orders . These control sequences have been divided into subsequences for ease of description, comprehension and modularity. Each control subsequence is described in terms of 'Control-Point' flow chart which shows the various control signals, their time order and the conditions under which they would be activated. Each control sequence is first represented by a 'Global Flow (GF) diagram' . This GF diagram shows the various control subsequences which make up that control sequence and grossly shows the flow of control from one subsequence to another. An overall gross description is given of the control sequence in terms of the functional significance of the various subsequences that make up the global flow diagram. Next, a detailed operational description of each subsequence is given in terms of the control point flow chart and the actions performed by the various stages of the control point flow chart. Still another subsection entitled "Logic implementation" shows the logic drawing number on which the actual logic hardware implementation is shown. To understand the control sequences, one needs to be familiar with the control algorithms for the execution of corresponding instructions. In this report, the operational description of control algorithms is not given in detail. DCS Report No. Ul8, which describes the simulation of the control algorithms at the hardware level, gives a description of the control algorithms and the motivation for the various steps in the algorithm. The present report 38 assumes that the reader is familiar with the contents of Report No. Ul8, and it is recommended that the two reports should be read concurrently. Since the simulation described in Report No. Ul8 was done at the hardware level, there is an almost one-to-one correspondence between the simulation flow charts and the control flow charts. However, there are certain differences which can be pointed out in general. a). Simulation was performed on IBM/360 which is basically a sequential machine. However, in hardware control realization, many of the functions could be done in parallel which in simulation flow charts are shown as being serial. This fact is pointed out whereever deemed necessary in the documentation. b) All gate functions and shift logic functions are simulated as procedures, whereas in actual hardware, they are realized by activating a 'Select' signal which selects the proper data bus followed by a 'Load' signal. As an example, consider LHRUUH . This means that contents of LH register is right shifted four bits and transmitted to UH register. In simulation flow charts, it suffices to write LHRUUH, whereas in control flow charts, we have to first turn on SLHRllUH which sets the selector flip-flop to select the shifted data to the input of the register UH , and then the gating signal LDUH is turned on which sets the register UH according to the contents of the bus . c) Illiac III AU contains four cascaded signed-digit subtractors (SDS). In AU simulation, one SDS is simulated as a subprogram and is called four times in succession to simulate the SDS array. In the control logic, the whole Subtrac tor /Adder array is activated at the same time in parallel. Any other marked differences between the simulation flow charts and the control flow charts are indicated in place whenever considered necessary to avoid confusion, 39 Besides describing the various control sequences in terms of their flowcharts, the two other subsections describe briefly some other hardware which complements the hardware which implements the control point flow charts These are the final level task drivers discussed in Section 3.10.3 and other miscellaneous hardware like electronic pushbutton selector switches, power turn on and 'clear and reset' logic, etc. Before moving further to study the control point flow chart, it should be borne in mind that the AU control logic, as implemented here, assumes that the floating point operands sent by the processor to the AU are normalized to base 16. It is TP's responsibility to guarantee this before transmitting operands to the AU. If the processor fails to do so, the AU control logic might hang up. Also, it is assumed that TP will not send any arithmetic order which involves the processing of decimal operands except the instructions CVL (convert to long-fixed point) and CVF (convert to floating). It is necessary because none of the arithmetic orders ADD, SUB, CPRA, MPY, DIV, with decimal operands is implemented as of present. Finally, it should be noted that the arithmetic order POLY for polynomial evaluation is not implemented either. ko 3.2 INSTRUCTION DECODING 3.2.1 Instruction Variant and Number Type Decoding The order to be executed by an arithmetic unit is indicated by the four bits of the Instruction Variant (IV) together with the two bits of Number Type (NT) code. Bits number U-7 of the V-BUS are gated into the IV-Register under control of the signal IVDIVR. The true outputs of the IV-Register flip-flops are designated IV - IV, , corresponding to V, - V respectively. Similarly, bits number 8 and 9 of the V-BUS are gated into the NT-Register under control of the signal NTDNTR. The true outputs of the NT -Register flip-flops are designated NT and NT , corresponding to Vq and V Q The true and complement outputs of the NT-Register drive the NT-Decoder to produce both the true and complement of the following signals. SFIX = NT • NT LFIX = NT • NT FLT = NT • NT DEC s NT • NT FIX = SFIX v LFIX = NT The logic for the IV- and NT-Registers and Decoders is shown in Drawing AUO-07 -321-01. The true and complement outputs of the IV-Register drive the IV -Decoder, which produces the true value of the following signals: kl CVL = IV. CVL = IV. CVD = IV n ADD = IV i SUB = IV 1 CPRA = IV. MPY = IV. 1 POLY = IV 1 DIV = IV. • iv 2 - iv 3 - • iv iv 3 - • iv 2 - iv 3 - • iv 2 - iy 3 - • iv 2 - i V • W 2 - iv 3 - • iv iv 3 . • iv 2 - Iv 3 - • iv„ • iv^ • IV, IV, IV, IV, IV, IV, IV, IV, IV, 1 2 3 ASC = ADD v SUB v CPRA In addition, a signal to indicate the arrival of a coefficient (other than the first) for a POLY order is generated. It is defined as follows POLYCO = IV, • IV • IV • IV, • POLIP 1 2 3 h where POLIP = POLY in Progress. Note that not all bit patterns of IV and NT correspond to legal instructions. If an invalid pattern is sent to the AU, an ILL0P (illegal Operation) condition is generated. A map of the ILL0P condition is given in Table 3.2.1. 1+2 Mnemonic Binary Code 0000 CVL 0001 CVF 0010 CVD 0011 0100 0101 0110 0111 ADD 1000 1001 SUB 1010 CERA 1011 MPY 1100 POET 1101 DIV 1110 POLY 1111 IV \ NT SFTX LEIX Decimal Code \ 1 1 2 3 h 5 6 7 8 9 10 11 12 13 Ik 15 FLT 2 DEC 3 1 1 1 1 1 l Co o> o o) 1 c (p~ o;- 1 i l i 1 l l i 1 l l i 1 l l i 1 l l ® 1 l l i 1 l l © 1 l l 1 0") 1 l l § 1 0~ 61 1 1 1 l 1 - = don't care Table 3-2.1 - Map for ILL0P Conditions 1+3 The most efficient implementation is realized by writing an expression for the 'O's" in the table. Thus, if we represent the IV- string by its decimal equivalent (for example 0001 = (l^ , then ILL0P = (ll ' FIX v(2^ ' FLT v(?) * DEC v(8) • FLT v(10) • FLT v(ll)- FLT v(l2)- DEC v(13)- FLT v(lk)' DEC 3.2.2 Decimal Operand Sign Register and Decoder (DOSIREP) In case of decimal operand instruction, bits numbered 15-18 of the V-BUS are gated into the Decimal Operand Sign (DOS) Register under control of the signal LDDSIGNA. The true and complement outputs of the DOS-Register drive the DOS-Decoder which produces two signals, SSIGNAPOS and SSIGNANEG, for positive and negative sign of the operands respectively. These signals in turn set the sign flip-flop, SIGNA (Drawing AUO- 390-07-08) , of the decimal operand A to the positive and negative state respectively. In case the given sign code does not conform to the USASCII code, possibly due to some error, then an illegal decimal operand signal ILLD0P becomes true. This is shown in drawing AUO-OT-321-01. uju. 3.2.3 Logic Implementation Logic implementation of Instruction Variant and Number type decoding is shown in control drawing AUO-07-321-01 . Also shown on the same drawing is Decimal Operand Sign Register and Decoder (DOSIRED) . U5 3.3 V-BUS INPUT OPERAND LOAD (VIN) CONTROL SEQUENCE Upon rapid initial decoding of the instruction variant and number type, VIN control sequence loads the operands as received, one word at a time, into appropriate registers. After all operands have been loaded, the control of execution is switched to an appropriate control sequence according to the instruction variant. After the execution of that control sequence is completed, control is switched back to VIN for the next arithmetic order. 1+6 3.3.1 Global Flow Description Figure 3.3.1.1 shows the global flow diagram for VIN control sequence. VIN control sequence is composed of four control subsequences, some or all of which are entered depending on the type of instruction variant and number type. The operand is received one word at a time, in the following order: left word of operand A, left word of operand B, then the right word of operand A, and finally the right word of operand B. Figure 3.3.1.2 shows the order of word transmission from TP to AU in the case of various number types Subsequence FIWLOB loads the instruction variant and number type registers from the control byte of V-Bus Input word, decodes the instruction and then loads the first word of the operand into appropriate registers in the AU processing hardware. If there is any parity error or the instruction decoding logic indicates an illegal operand, then an appropriate exit is taken. Since the instructions CVD and CVF involve unary operation and single word operand, the control sequence branches to CVD and CVF subsequences and in all other types of instructions , the control sequence goes to SEWLO and BRAIN to load the next word of the operands . SEWLO loads either the second word of the double word operand for unary operations (e.g., number type conversion instructions for decimal and floating point operands) or the first word of second operand in case of other instructions. BRAIN causes the control sequence to branch to an appropriate control sequence, for example, to CVL, CVD and CVF in case of floating and decimal operands and unary instructions, and to control subsequences MPY and DIV for fixed point operants. For binary instructions require double word operands, VIN control goes to TIFOWLOB. hi Figure 3.3.1.1. Global Flow Diagram for "VIN— Input Operand Load from V-Bus and Branch to Appropriate Arithmetic Order" Control Sequence U8 Binary Operation Double-word Operands Unary Operation Double-word Operand Binary Operation Single-word Operands Unary Operation Single-word Operand A Operand B Operand A i A 2 B i \ . 0SP Order of Transmission: A , B_ , A , B A Operand A i A 2 1 0SP Order of Transmission: A.^ , k r A, 0SP Order of Transmission: A , B A. 0SP Order of Transmission: A, = 1 word = k bytes = 32 bits + k flags 0SP = Operand Stack Pointer Figure 3.3.1.2. Order of Word Transmission to AU kg TIFOWLOB loads the second words of operands A and B into appropriate registers, checks for the parity errors and then branches to an appropriate control sequence depending on the instruction type as decoded in FIWLOB . It may "be noted that the control sequence for arithmetic instruction POLY has not been implemented and for the present it has been decided that the TP would not send any POLY order to the arithmetic unit. 50 3.3.2 Control-Point Flow Description : Figures 3.3.2.1, 3.3.2.2 and 3.3.2.3 show the control point flow- charts of various subsequences used in VIN control sequence. Task stage VTN-1 loads the IV-Register and NT-Register and sets the AUBUSY indicator. Branch SI in sequence stage SI should be carefully noted. This branch is taken whenever an illegal instruction variant or number type is indicated by the instruction decoder. The words from the V-Bus are trans- ferred to appropriate registers depending upon the instruction and the control sequence will operate only if the various task and sequence conditions are satisfied. Whenever the instruction variant and/or number type received by the control are invalid, the control sequence flow will hang up if a branch is not taken to the EXIT control subsequence. In the EXIT subsequence, the control flow must wait for a duration necessary for the double-word binary operands transfer which is the maximum time TP ever takes in transferring data to the AU,before the AU calls back the TP to inform it of an invalid command. In the simulation flow charts , a check for parity error is not specifically indicated whereas the control-point flow charts do show a parity check in the form of loading the parity error flip-flop (LDPEi, i = 1-3). The rest of the control-point flow chart is almost identical to the simulation flow charts and should not cause any confusion. 51 ( STAVTN j G> v r v : i r VIN-1 •AUBUSY.MEN IVDIVF. NTDNTR SAUBUSY SI, SI, SI. T2. T2. f 2 k T2„ T2, T2. VIN-2 LDFSIGNA VIN-2 LDDSIGNA VIN-2 VIN-2 FA1LFA LDFAL LDFE1 VDUQU7 LDUQ S2, S2, VIN-2 VDUQO LDUQ \< VIN-S VDUQ13 LDUQ 1 ' VIN-2 SEADEUU LDEUU S2. S2, CVF (Entry CVFIX) EXIT (Entry 3) Sl n - ILL0P Sl 2 - (ILL0P v POLYCO) si 3 ■ POLYCO T2 1 ■ DEC T2 2 - DEC T2. . NONE T2^ = FIX.(CVD v MPY^ T2, = FIX.(CVF v DIV) T2 ' 6 = FIX v (CVF v DIV) T2„ = FLT S2 X ■ CVD.FIX.PERP. S2 2 = CW. FIX. PEER S2. = PERK. (CVD. FIX v CVF. FIX) 32^ = (CVD.FIX v CVF. FIX) Figure 3.3.2.1. FIWLOB— First Word Load and Branch 52 | VIN3 ) 0- V .MEN T3, T3, T3, VIN-3 vduqJ+7 FA2RFA LDUQVf LDFAR VIN-3 SEBDEUM LDEUM EXDEUX T3, T3 C VIN-3 SEUDIFF VIN-3 LDFSIGNB FB1LFB VDUH13 LDUH VIN-3 VDUHO LDUH VIN-3 B3 IE S3 1A S3 C S3. S3. S3. EXIT (Entry 3) CVF (Entry CVFDEC) T3 1 - (IV^ v DIV.FDC) T3 2 = IV. .FIX T3- = FLT.MPY T3, IV, S3,„ = CVL. DEC. ILLD0P. PERR J 1B S3 1A CVL.FLT.FERB S3, = CVD.FLT.FERR S3 = CVF.DEC.ILLDp.FERR S3, MPY. FIX. PERR T3c = FIX T3g = (NONE) S3 = DIV.FIX. FERR S3o = (CVL.FLT V CVL.DEC v CVF. DEC v CVD.FLT v MPY. FIX v DIV.FLX) PERR v (CVL.DEC v CVF. DEC) PERR.ILLD0P S3, IV . FLT . POLYCO . PERR S3 ? = POLYCO Figure 3.3.2.2 SEWLO and BRAIN — Second Word Load and Branch to Appropriate Instruction 53 ( VINU ) e> VIN-U FA2FA LDFAB VDUQl*7 LDUQi+7 LDPE3 V .MEN . V . MEN VIN-5 FB2RFB VDUHl+7 LDUHU7 LDPE3 LDESDEUL 85- S5 C S5, EXIT (Entry 3) 85, - PERB S5 2 - ASC.PERR S5o - MPr.'PERP 85^ - DIV.raRR S5 5 - POLY.raRR Figure 3.3.2.3. TIFOWLOB — Third and Fourth Words Load and Branch 5k 3.3.3 Logic Implementation Logic implementation of control sequence VIN is shown in control drawings AUO-07-332-01 to AUO-07-332-OU. The table below shows the names of the various control subsequences, their control point flow chart figure number, and the number of the corresponding drawing on which the control point flow chart is logically implemented in hardware. • Control subsequence Figure Number Corresponding logic name drawing no . FIWLOB 3.3.2.1 AUO-07-332-01 SEWLO 3.3.2.2 -332-02 BRAIN 3.3.2.2 -332-03 TIFLOWLOB 3.3.2.3 -332 -0U 55 3.U RESULT FORMATTING AND TRANSMISSION (REFOTRAN) CONTROL SEQUENCE This subsequence forms the last part of each control sequence and is used to format the result properly before transmission. The formatting involves the normalization of the result, setting of proper flags and error indicators. The final part of the subsequence transfers the result to the TP via the Exchange Net . 3.^.1 Global Flow Description Figure 3.U.1.1 shows the global flow diagram for REFOTRAN control sequence. This control sequence is composed of three subsequences which perform different operations. In control subsequence EXIT, either the contents of register UQ, and hence the result, is normalized if no illegal operand (illegal op code and/or parity error) is encountered during processing, or the normalization of UQ is skipped. The normalization of the result is done by calling the subroutine N0RMUQ. Next the control branches to subsequence SFBIN where overflow/ underflow conditions are tested to appropriately set the exponent of the result to corresponding unique values (V=l=>EUL should be all ones, etc.), and also the flags are set to indicate either errors and exceptional conditions and/or the result (>,=,<) of executing the arithmetic order CPRA. Now the result is ready in proper format and the control branches to subsequence X-0UT which causes the transmission of one or two words in the result. After the result transfer is complete, the control goes to sequence CREST which reinitializes the AU control and processing hardware to await the next arithmetic order. 56 .REFOTRAN JN0RMUQ SFBIN Figure 3. I*. 1.1. Global Flow Diagram for "REFOTRAN — Result Formatting and Transmission" Control Sequence 57 3.U.2 Control Point Flow Description 3.U.2.1 EXIT Figure 3.^.2.1 shows the control point flow chart for the EXIT control subsequence . It is composed of four task stages and has four entry points. Entry 1 indicates that no illegal data or operand were encountered during the arithmetic order processing, and hence the task stage EXIT-1 calls the control sequence N0RMUQ which normalizes the result which was placed in the register UQ earlier by another control sequence. Entry 2 takes place when an illegal instruction variant or number type is recognized by the VIN control sequence. In such a case, the control would have hung up if an attempt was made to load the operands instead of bypassing the VIN sequence. Task stage EXIT-2 sets a flip-flop ID indicating Illegal Data and control then goes to task stage EXIT-3 • This stage is a dummy stage, produces no task control signals except waiting for the worst time it takes for the VTN-Control sequence in any situation. This duration will be found by trial and error. Entry-3 leads to task stage EXIT-U in which the flip-flop ID is set because an illegal decimal operand (wrong decimal sign code) was pointed out by the decoder. Entry k does nothing but is placed here only for uniformity. After all the task stages have finished their task, the EXIT control subsequence branches to subsequence SFBIN where flags and indicators are set. Note that there is no corresponding procedure in AU simulation. 58 [Entry 1 j ( Entry 3 J f Entry h J EXT-1 N0RMJQ EXT-^ ( Entry 2 j EXT- 2 SID EXT-3 Wait for a time it takes to load all the four operands from TP to AU via EN Tk = ILLDjZSP Figure 3.U.2.I. EXIT 59 3. k. 2. 1.1 N0RMUQ Figure 3.^.2.1.1 shows the control point flow chart for N0RMUQ. This control sequence serves two purposes; one is to normalize the contents of UQ (base l6) such that no more than three leading zeros are retained in the mantissa of the result, and the other purpose is to confine the mantissa to 56 bits so that the leading eight bits of the first word may contain the exponent of the result. Sequence stage SO checks if the result, i.e. the contents of UQ, need reformatting. If they do (condition SO ) , the task stage NUQ-1 is entered. Under condition? Tl and Tl , the paths are established for left shifting the contents of UQ by h or 8 bits, respectively, and at the same time, the exponent in EUL counter-register is decremented by one or two. Under task condition Tl , where the mantissa of the result has overflowed into space for the exponent, the task NUQ-1 sets up the path for right shifting the contents of UQ by k bits and increases the exponent by one. Task stage NUQ-2 gates the shifted contents of UQ into register UQ. Task stage NUQ-3 is a dummy stage to provide for enough time so that the condition detect logic at the output of register UQ is stable before the control loops back again to see if the control needs to go through another iteration for normalization. 6o /> m — so l so 2 ■ Tl Tl l± l 1X 2 v Tl 3 - r NUQ-1 , r NUQ-1 J NUQ-1 UQDLQ slqrUuq SBY0NE SEUCTRDIR UQDLQ SLQLAUQ SBY0NE CEUCTRDIR UQDLQ SLQL8UQ CBY0NE CEUCTRDIR CP CP CP 1 r , , NUQ-2 / f~ "N I RETURN ) LDUQ l , NUC 1-3 Wait for UQ Condition detect to settle SC^ = (UQEZ v UQ58EZ.UQ912EZ) so 2 = so 1 Tl 1 = UQ58EZ Tl 2 = UQ58EZ .UQ912EZ .UQ1316EZ Tl 3 = UQ58EZ.UQ912EZ.UQ13l6EZ.UQEZ Figure 3. k. 2. 1.1 N0RMUQ— Normalize UQ 61 3.U.2.2 SFBIN Figure 3. k. 2. 2.1 shows the control point flow chart for the control subsequence SFBIN whose function is to Set Flags and Bogus and Arithmetic Ind icators . Flag bit designation for arithmetic indicators is given in Figure 3.^.2.2.2 which is reproduced here from Volume 1, DCS Report No. 366. It is recommended that the reader should recapitulate the Sections 1.5 and 1.6 of the Volume 1 (DCS Report No. 366) to fully appreciate the functions of this control subsequence. Task stage SFB-1 under task conditions Tl and Tl sets the exponent of the result as +63 and -6U — the largest and the smallest values of the exponent. These task conditions indicate the overflow and underflow of the exponent. Task condition Tl applies only for the Algebraic Comparison arithmetic order and sets the arithmetic indicators (flags) according to the result of the comparison. Task condition Tl, sets the loss of significance indicator LS when the mantissa of the result is all zero and the exponent is other than zero. If any of the exceptional arithmetic conditions has occurred during the arithmetic order processing, then task stage SFB-2 sets the Bogus Result (BR) indicator flip-flop. It should be noted that although the flow chart indicates that if the exceptional conditions have not occurred, the flip-flop BR should be cleared (set to zero state), but in actual control hardware, no action is taken because the flip-flop BR is already in zero state, being made so during subsequence CREST or during initialization and power turn on . The control next enters sequence stage S2 and decides whether the indicator flags should be set or not. When the arithmetic order is Compare Algebraic (CPRA) or if any exceptional arithmetic condition has occurred (condition S2 ) , the signal INDFA is turned on followed by LDFAL, LDFAR, 62 which respectively select and load the various indicators into the flag register FA. Finally, the control goes to subsequence X-0UT which transmits the result to the TP via the exchange net. If the sequence condition S2 is false, the control directly bypasses to subsequence X-0UT. A discrepancy should be noted in the flag bit designations for arithmetic indicators as given in the simulation manual (DCS Report No. Ul8, p. Ul) and as specified in DCS Report No. 366, Section 1.6.1 — 2/3. But, the latter one is correct because it agrees with the interpretation by the TP. Figure 3.1+.2.2 shows the correct flag bit designation for arithmetic indicators, 63 Tl. SFB-1 FM *- FLMTCH EQ — U QEZ GT — SR.UQEZ LT — SR^UGJSZ Tl, Tl, SFB-1 LS — EULEZ.UQEZ 1 SFB-1 SEULALL0NE T2, T2,. SFB-2 S2, SFB-2 S2, SFB-3 [NDF/ LDFAR Tl = (EUA0V v EUAUN) Tl- = CPRA Tl^ = (ADD v SUB) v POLY.FLT Tl = EUA0V Tl 2 = EUAUN Tl„ SFB-1 SEULALLZER0 T2 X = (0V v UN v LS v ID) T2 2 = T2^ 8B 1 -82 1 S2 = (BR v CPRA) Figure 3. U. 2. 2.1. SFBIN— Set Flags, Bogus and Arithmetic Indicators Long Fixed M M 0V El ID EI Short Fixed 0V ID 1X3 M 6k Floating LS EI UN m ID M GT EI LT EI FM El Decimal LS EI EI 0V EI ID EI GT Et EQ EI LT EI FM g] = Flag of Byte (Bit #9) * = Not Used in this Number Type Figure 3.^.2.2.2. Flag Bit Designation for Arithmetic Indicators 65 3.U.2.3 X-0UT Figure 3.^.2.3 shows the control point flow chart for the sub- sequence X-0UT which performs the function of transmitting the result of arithmetic processing to the taxicrinic processor (TP) which is waiting for the result. This transmission takes place via the exchange net and this subsequence mainly requests and obtains access to the exchange net and then transmits the result to the TP. Sequence stage SO examines the ILL0P ( ille gal Operation Code) flip-flop and enters or bypasses the task stage X0UT-1 depending where the flip-flop is in zero or one state, respectively. When the operation code is legal, the task stage X0UT-1 sets up the data paths for the transfer of the exponent and first three most significant bytes of the result (to XT-bus ) if the number type of the result is floating point (task condition Tl ) ; otherwise, the data paths for bytes 0-k of register UQ which holds the result are set up. In both cases, the flip-flop SCWORD is set to zero state indicating that the first word of the result is being transferred. If the Operation Code is illegal, task stage X0UT-1 is bypassed because UQ is blank as it was not loaded during the VIN sequence, and hence there is no need to set up any paths for data transfer. Task stage X0UT-2 sets to '1' state the two control flip-flops XTDES and UREN . The control signal XTDES sets up a path for transfer of the result to the exchange net and UREN control signal requests the exchange net access . The control now transfers to the task stage X0UT-3 where the control waits for a reply from the exchange net, granting access as indicated by V • MS . As soon as the access is granted, the control task stage X0UT-3 generates a TI0 pulse which is transferred to the processor via the exchange net control 66 "byte and is used by the processor to accept the data from the exchange net. For more details see DCS File No. 790 which discusses "Processor-Unit Communication via the Exchange Net" in more detail. Sequence stage S3 decides whether "both the words of the result have been transferred. If not, as indicated by S3-,, the data path for the transfer of second word is set up by setting the flip-flop UQJ+7DXT to '1* state, and at the same time, the flip-flop SCWORD is set to '1' state indicating that second word is being transferred. The control again loops back to task stage X0UT-3 where the data transfer takes place as described earlier. If the second word has already been transferred, the control exits to task stage X0UT-5 where the flip-flop SCWORD is again set to zero state to make the subsequence ready for further use in the next arithmetic order processing control sequence. It should be carefully noted here that although the fixed-point type result has only one word of valid data, the subsequence X-0UT always transfers two words as if the result was always floating point type. It causes no problem as far as the TP is concerned because it can ignore the second word, whereas this way the control is simplified and does not have to use special condition detect logic for fixed point type result. The control finally branches to control subsequence CREST (clear and reset) which resets every control flip-flop to the initial state, and the control gets ready to accept another arithmetic order from a processor. NOTE : It should be noted that in case of parity error during VIN sequence, the result transferred out during subsequence X-0UT is not all zero as mentioned in Section 2.4.2 — h/h of Illiac III Arithmetic Unit, Vol. 1, DCS Report No. 366, but rather the contents of UQ which is one of the operands. It may or may not be the one which has the improper parity. 67 so, Tl, so„ Tl. X0T-1 SEULDXT SUQ13DXT CLSCWORD X0T-1 SUQODXT SUQ13DXT CLSCWORD X0T-2 SXTDES SUKBN x;:- 3 TI0" S3, S 3l - X3T-5 CLSCWORD 1 | X0T-1* SSCWORD suqUtdxt CHEBT SO, - ILL0P S0 2 - ILL0P Tl, - (FLT V CVF) (CVD.FLT T CVL.FLT) Tl p - (FLT v CVF) v (CVD.FLT v CVL.FLT) - Tl, S3 - SCWORD S3, - SCWORD -S3, Figure 3.U.2.3. X-0UT — Transfer Result to Processor via Exchange-Net 68 3.4.3 Logic Implementation Logic implementation of REFOTRAN control sequence is shown in control drawings AUO-07-332-05 , AU0-07-352-04 through 352-06. The table below summarizes the correspondence between the control point flow charts of subsequences and their logic implementation drawings. Control subsequence Figure Number Corresponding logic name drawing no . EXIT 3.1*. 2.1 AUO-07-332-05 N0RMUQ 3.^.2.1.1 -352-04 SFBIN 3. k. 2. 2.1 -352-05 X-0UT 3.4.2.3 -352-06 69 3.5 ADD, SUBTRACT, COMPARE ALGEBRAIC (ASC) INSTRUCTIONS CONTROL SEQUENCE This control sequence is entered whenever the arithmetic instruction to be executed is any one of Add, Subtract (SUB) or Compare Algebraic (CPRA). All these three instructions have been lumped into one control sequence because their execution use almost the same control subsequences and in essentially the same time order. This control sequence is used for floating point addition, subtraction or comparison. Fixed point addition, subtraction and comparison operations are done in the TP. 70 3.5.1 Global Flov Description Figure 3.5.1.1 shows the global flow diagram of ASC control-sequence. Since this control sequence is used for floating point addition, subtraction and comparison, the first order of business is to do the operand alignment. The control subsequence OPACAS examines the algebraic value of the difference of the exponents calculated by the exponent unit processing hardware. It then calls up, using this information, the appropriate operand shifting control subsequence and depending upon whether the sign of the result SR is predictable or not, it sets the SDB ( Sign-Digit-Bypass ) indicator. If the exponent unit adder indicates either an overflow/underflow or if the difference of exponents is > |l3J, which means that one operand is insigni- ficantly small compared to the other and consequently the control sequence goes to subsequence X-0UT which transfers the result (the bigger of the two operands) to the TP via the exchange net. However, if the difference of the exponent is < 13 , the control branches to control subsequence CAL. CAL subse- quence provides the control signals to the Adder /Subtract or array which per- forms the actual addition or subtraction depending on the instruction variant. Subsequence CAL makes use of another subsequence ASIM in order to convert the output of SDS-array into the conventional form. After the result is calculated, the control branches to subsequence EXIT which calls upon subsequences N0RMUQ and SFBIN to normalize the result and set the flags and other indicators respectively. Now the result is ready to be transmitted to the TP and thus control switches over to control subsequence X-0UT and after the result is transferred to the TP, the control finally goes to subsequence CREST where the control logic is reset to await for the next instruction. 71 COMPARE ALGEBRAIC ADD a 'SUBTRACT ,(ASC) ^••/alnuh] TYasimJ Figure 3.5.1.1. Global Flow Diagram for "ASC— Add, Subtract and Compare Algebraic" Control Sequence 72 3.5.2 Control-Point Flow Description 3.5.2.1 OPACAS Figure 3.5.2.1 shows the control-point flow chart for OPACAS and logic drawing AU0-0T-352-01 shows the corresponding logic implementation. Task stage ASC-1 appropriately sets the flip-flops SR (sign of the result) and SDB (sign-digit-bypass) depending on whether the sign of the result is predictable simply by looking at the difference of the exponent and sign of the two operands as well as the arithmetic instruction. A table for the pre- diction of SR is given below. Difference of SIGNA = Arithmetic SDB SR Exponent SIGNB order > Yes or No Any 1 SIGNA < Yes or No Any 1 SIGNB = Yes ADD 1 SIGNA SUB CPRA No ADD SUB 1 SIGNA CPRA 1 SIGNA In addition, this control point (task stage) sets up the path, under task condition Tl , for transfer of operands to M and UM registers. It also sets the proper path through the SDS array to be used in Subsequence CAL for calculating the sum or difference of the operands. Besides a control flip-flop AEXPGT is set if the difference of exponents is greater than zero. Now, if the arithmetic 73 order is either ADD or SUB, the second task stage ASC-2 is entered which calls the operand alignment (shifting) control subsequence (ALNUH or ALNUQ) if the difference of exponents is in range. However, if the exponent unit adder under- flows or if the difference of exponent is •< -13, it implies that operand A is insignificant compared to operand B and the result is operand B which should be transferred to result register UQ. ASC-2 achieves this by calling upon the subsequence UHTUQ. If the arithmetic order is CPRA, (floating point comparison), the control sequence bypass ASC-2 and proceeds directly to sequence stage S2 where the control branches to any one of the three control subsequences. If there is no overflow /underflow and the difference of exponents is in range (i.e. < | 13 | ) or if the sign of the result is unpredictable (SDB = 0), the control branches to subsequence CAL to calculate sum or difference. 7^ DEXPEZ.SIGNA.SDB v DEXPGTZ.SIGNA V DEXPLTZ. (SIGNA © SUB Tl„ = Tl T1 4 = Tl 5 = T1 6 = Tl = J 51 1 = si 2 = T2 ± = T2„ = (SIGNA © SIGNB © ADD) v DEXPEZ (NONE) IDEXPLTML3 V EUAUlO S2 1 = CPRA.SDB S2„ (CPRA v SDB) (e v Tl ) S2 3 = CPRA.(0 v Tl ) 3 = (DEXPGT13 V EUA0V) cpra -dexpez -6 ''pra.dexftpr cpra.dexpinr ^pra.tTT 'i ASC-2 ASC-1 Figure 3.5.2.1. ASC_OPACAS— Add, Subtract, Compare Algebraic- Operand Alignment Call Set -Up 75 3.5.2.1.1 ALNUH Figure 3.5.2.1.1 shows the control point flow chart for ALNUH and logic drawing AUO-07-352-02 shows the corresponding logic implementation. The task stage AUH-1 shifts right the contents of UH register by either 8 or h hits and correspondingly decreases the exponent unit counter till the counter contents go to zero. At this instant, the operands are aligned and the subsequence replies back to the calling control point of calling sequence OPACAS. Note that the exponent unit counter and condition (DEXPEZ) detect logic should be completely stabalized before the control loops back again to determine whether to go through another pass of the loop. That is why, it was decided to use second task stage AUH-2 so that enough time is available for condition to stabilize. 16 Sl- Sl_ 1 i' i Tl- Tl. I v 2 1 1 AUH-1 AUH-1 UHDLH UHDLH SLHR8UH SLHRi+UH CBY0NE SBY0NE CEUCTRDIR CEUCTRDIR i CP CP ' r RETURN ) V. J \ r — — AUH-2 LDUH SI = DEXPEZ = EULEZ SI, SI, Tl 1 = DEXPGE2 Tig = DEXPGE2. DEXPEZ = DEXPGE2. EULEZ Figure 3.5.2.1.1. ALNUH— Align Contents of Register UH 77 3.5.2.1.2 ALNUQ Figure 3.5.2.1.2 shows the control point flow chart for ALNUQ and logic Drawing AUO-07-352-02 shows the corresponding logic implementation. ALNUQ is exactly identical to ALNUH. 78 Sl- SI- 1 ' » •d Tl Tl. 1 " d m AU( 1-1 !i AUQ-1 UQDLQ ' i SLQR8UQ CBY0NE SEUCTRDIR UQDLQ slqrUuq SBY0NE SEUCTRDIR f RETURN J CP CP i 1 AUQ-2 LDUQ S]^ = DEXPEZ = EULEZ Sl 2 = DEXPEZ = EULEZ Tl x = DEXPLEM2 Tl 2 = DEXPLEM2. DEXPEZ Figure 3-5.2.1.2. ALNUQ— Align Contents of Register UQ 79 3.5.2.1.3 UHTUQ Figure 3. 5. 1-1. 3 and logic Drawing AUO-07-352-02 show the control point flow chart and logic implementation for UHTUQ. Since there is no direct path "between registers UH and UQ, the control makes use of the SDS-array to do the transfer. Task stage UHQ-1 sets up the path through the array and also trans- fers UH to register M. Note that since the transfer through the array begins after the register M has "been loaded, the duration of the second delay in the delayed task generation (LDM) should he sufficient not only to load the register M but should be large enough for the new contents of M» travel through the last stage of SDS-array (SMDYU). Now the control enters the second task stage UHQ-2 where the output of SDS-array is transferred to register LM and thence to register UQ by control signal LDUQ. Note that the path "between LM and UQ had been established earlier in task stage UHQ-1 by control signal SLMDUQ. 80 \ > UHQ-1 SUHDM SLMDUQ SMDYU CLG123U CLNEGaS 1 * LDM 1 ' UHQ-2 zUdlm LDUQ ' ' ( RET URN J Figure 3. 5. 2. 1.3. UHTUQ — Transfer Contents of Register UHL to Register UQ 81 3.5.2.2 CAL This Procedure (control subsequence) is used to claculate the sum or difference of the two operands. Two important things to note here are the derivation of Boolean expression (shown in Figure 3.5.2.2.1) for setting and resetting the NEG0 and NEG1 control signals of the SDS-array and the assimila- tion of the result into conventional number representation. Tables 3. 5. 2 2,1 and 3.5.2.2.2 show the value of control signals NEG0 and NEG1 for all combina- tions of SIGNA and SIGNB and for SUB, CPRA and ADD. Since the floating point representation is sign and magnitude representation and maintissa is always positive, the choice of NEG0 and NEG1 should be such that the result of adding or subtracting the mantissas of the two operands in the SDS-array should be positive. Under the column heading "Effective Operation" in the tables, the entries are written so that the mantissa of the result will always be positive in those cases when the sign of the result is predictable. In the cases, where the sign of the result is not predictable a priori, operand B is subtracted from Operand A and if the result is negative, the order of subtrac- tion of the two mantissas is changed by complementing NEG1 as in task stage CAL-3. Note that in the SDS-array, NEG0 negates the mantissa A and NEG1 negates the difference of mantissas A and B. Under the column heading, "Comment", the entries show how the values of NEG0 and NEG1 achieve a positive mantissa of the result. In the simulation flow chart, an explicit call to subroutine "ASIM" is shown for assimilation of signed digit result into conventional form but the control point flow chart does not show the call explicitly, because some of the necessary control signals for Assimilation (SG1CLG2G3GU, SPDY*+ ) have been set 82 earlier in task stage ASC-1 in control subsequence OPACAS and others have been set either in control subsequence CREST (e.g. CY2SFF, CY3SFF, CLNEG23U) or in task stage CAL-1 (e.g. SUMDXI, SUSDS1, NEG0, KEGl) and task stage CAL-U (e.g. ZUDLM). Task stage CAL-1 sets the control signals NEG0, NEG1 to appropriate state and also transfers the exponent of the either operand whichever exponent is higher, as the exponent of the result to the register counter EUL in the exponent arithmetic section of the processing hardware. Task stage CAL-2 is only a dummy stage and provides enough time for SDS-array and propagation logic to settle down. Sequence stage S2 checks whether the sign of the result was predictable a priori; if not, it goes to task stage CAL-3 to check whether the sign of the difference/sum of the two mantissas at the output of SDS-array is positive or negative. If it is negative as determined by task condition T3-, , the order of the subtraction is changed. In this context , the difference from the simulation flow chart should be carefully noted. In the simulation flow chart, Z is examined to see if the assimilated output of Zi is negative, whereas in control hardware, Z< i.e. the leftmost bit of Zi output is used. It does not really make any difference because Z« and Z are the same always. Task stage CAL-U transfers the assimilated result's mantissa to register UQ via register LM and the control then branches to subsequence EXIT» 83 Function: SUB, CPRA. Effective SIGNA SIGNB DEXP SR Operation SDB NEG0 NEG1 Comment >0 A-B 1 A-B < 1 -(B-A) 1 1 -(A-B) = ?* A-B (A-B) 1 1 >0 1 -A+B =-(-B+A) 1 (A-B) < -A+B 1 n 1 -(A-B) =0 ?* -A+B 1 -(A-B) 1 >0 A+B 1 1 1 -(-A-B) < A+B 1 1 1 -(-A-B) =0 A+B 1 1 1 -(-A-B) 1 >0 1 -(A+B) 1 1 1 -(-A+B) < 1 -(A+B) 1 1 1 -(-A-B) =0 1 -(A+B) 1 1 1 -(-A-B) Table 3.5.2.2.1 - Determination of Values of NEG0 , NEG1 for arithmetic orders SUB and CPRA 8U Function: ADD Effective Comment SIGNA SIGNB DEXP SR 0p< s rat ion SDB NEG0 NEG1 Magnitude >0 A+B 1 1 1 -(-A-B) < A+B 1 1 1 -(-A-B) = A+B 1 1 1 -(-A-B) 1 1 >0 1 -A-B 1 1 1 -(-A-B) < 1 -A-B 1 1 1 -(-A-B) =0 1 -A-B 1 1 1 -(-A-B) 1 >0 A-B 1 (A-B) <0 1 _. (A-B) -(B-A) 1 1 -(A-B) =0 ?* A-B (A-B) 1 >0 1 = . -A+B -(A-B) 1 (A-B) ; < -A+B =(B+A) 1 1 -(A+B) , =0 •?* -A+B 1 -(A-B) Table 3.5-2.2.2 - Determination of Values of NEG0, NEG1 for arithmetic order ADD. 85 PL, o pq CO PQ g H CO © o M CO > Q o M CO CJ H CO ft o CO 25 CO ® O H CO > Q O W CO M CO pq B CO o M CO EH ft w Q 0] H bO -H •H 03 CO H O O Ji >> -P -P C -H O H O +3 •H c: a; o U ft W -H -p 0) U H 5h O d ft -H W X Sh CD W ft PC o o pc CO H T3 oj 3 CVJ rH • n LTs s P 1 (U ts. u MS ft o 86 CAL-l Wait for Data to propagate thru SDS Array and Propagation Logic Circuit. S2, T3, T3o CAL-3 C0MPNEG1 SSDB SSR CAL-3 CSR S3, S3, Tl_ = NONE Tl„ = (SIGNA© SI0NB).ADD v (SIGNA © SIGNB).(SUB V CPRA) Tl^ = [(SIGNB©SR) v NEGOJ.ADD v [(SIGNB © SR) v NEGO].(SUB v CPRA) Tl = AEXPGT Ti 6 .fi; T3 1 = Vi T3 2 - T3-L B3 1 - SR S2„ CAL-U Figure 3.5.2.2. CAL-- Sum or Difference Calculation 87 3.5.2,3. ASIM Figure 3.5.2.3 shows the control point flow chart for the subroutine control sequence ASIM. This control sequence is used to convert the signed digit numbers into conventional binary representation. This is a very common and often used control subsequence of the AU control. This control point flow chart very closely resembles the simulation flow chart ASIM. This control subsequence consists of only two task stages. Task stage ASM-1 sets up the SDS-array such that the input Y2 and Y3 to the SDS2 and SDS3 respectively are all zero. Also the gate signals Gi and negate signal NEGi to SDS2, 3, h are also set to state 'zero'. Input Yk to SDS*+ comes from the output of propagation logic and signals USDS1 and UMDX1 transfer the contents of registers US and UM to the SDS-array. Control signals for SDS1 are set to proper state before calling the subroutine control subsequence ASIM. After the data to be assimilated has filtered through the SDS-array and propagation logic, the assimilated data is available at the output of SDSU and then task stage ASM-2 provides the gate control signal ZUDLM which loads the assimilated data in register LM. After this, the control returns back to the calling control point which called this subsequence. 88 ASM-1 CY2SFF CY3SFF CLNEG23J+ SG1CLG2G3GU SFDYk SUSDS1 SUMDX1 < f ASM-2 Figure 3-5.2.3. ASIM — Conversion from Signed-Digit to Conventional Representation 89 3.5.3 Logic Implementation Logic implementation of the various control subsequences of ASC control sequence is summarized in the table below which shows the correspondence between control point flow charts and their logic implementation. Besides, the table also shows the drawing number of any task signal collector (TSC) drawings for the sequence. Control Sub- sequence Name CP flow chart Figure Number 3.5.2.1 Corres. Logic Drawing No. AUO-OT-352-01 OPACAS ALNUH 3.5.2.1. 1 -352-02 ALNUQ 3.5.2.1. 2 -352-02 UHTUQ 3.5.2.1. 3 -352-02 CAL 3.5.2.2 -352-03 ASIM 3.5.2.3 -371-0U REFOTRAN -332-05 -352-0U, 05, 06 Task Signal Collector "A." -352-07 Task Signal Collector "A " -352-08 90 3.6 MULTIPLY (MPY) INSTRUCTION CONTROL SEQUENCE This control sequence is used for the execution of Multiplication process for both floating and fixed point number systems. 91 3.6.1 Global Flow Description Figure 3.6.1.1 shows the global flow diagram for the MPY control sequence. It is mainly comprised of two subsequences MPY-REPROG and MPYEND besides the subsequence REFOTRAN which is common to all the arithmetic orders. Control subsequence MPY-REPROG provides control signals for the multiplication of the two operands. The two operands in registers UQ and UH are in conven- tional form but the product formed by the subsequence MPY-REPROG is in the signed digit form. Since the result to be transmitted to the TP should be in conven- tional form, the subsequence MPYEND calls upon the assimilation subsequence ASIM to convert the product to the conventional form. Besides, the subse- quence MPYEND checks whether, in case of fixed point multiplication, the pro- duct has overflowed and accordingly sets the overflow flip-flop V to the appropriate state. At the end of these two subsequences, the control branches to sub- sequence REFOTRAN which formats the result properly and then transmits the formatted result along with proper indicators and flags to the waiting TP via the exchange net. Finally the control goes to subsequence CREST which initializes and readies the control for another arithmetic order. MULTIPLY/ (MPY) 92 MPY- REPROG ■jQ EXIT SFBIN 3 CREST Figure 3.6.1.1. Global Flow Diagram for "MPY — Multiplication Process (Fx. Pt . and Fl . Pt . ) " Control Sequence 93 3.6.2 Control-Point Flow Description Control point flow charts are almost identical to the simulation flow charts with a few exceptions. For example, in the simulation flow chart, the setting up of the SDS-array and M-shift array is done sequentially, one SDS-array and M-shift array stage at a time whereas in actual control, this is done in parallel hy the already wired in combination logic and task stage MPY-3. Another exception is the use of only one counter ICC and some combinational logic for 'multiplication-loop-termination' condition detect, whereas the simulation flow chart shows the use of the register NCC and the counter ICC for the same purpose A brief description of the action performed by each task stage is given below. Multiplicand and the multiplier are in registers UH and UQ respectively, being placed there by the VIN control sequence. In addition, the exponents of the two operands are processed in the exponent arithmetic unit, where the two exponents are added and exponent overflow/underflow condition is detected. In sequence stage stage SO, the sequence condition SO determines whether operand is zero and if so, task stage MPY-2 sets the result register UQ to all zero and also sets the register EUL, which holds the exponent of the result, to all zero state. Then the control sequence branches to subsequence EXIT where flags are set and eventually the result is transmitted to the TP as explained earlier in sequence REFOTRAN. If the number type of the operand is fixed point, then the contents of the register UH(i.e. the multiplicand operand) is shifted right by 8 bits in task stage MPY-1 so that the same logic and control sequence may be utilized for both the fixed point and floating point operands' multiplication. 9* In case of floating point non-zero operands (condition SOg), the task stage MPY-3 sets up the data path for the transfer of the multiplicand from the UH register to register M and then provides the gate signal LDM for the actual transfer. Task stage MPY-3 also sets up the SDS-array for the multi- plication loop. Besides it clears the loop counter ICC which is bidirectional and sets it up for the count-up state. Finally the data path between the register UQ and the multiplier recoder (SUQDMR) is set up. The output of the multiplier is directly connected to the M-shift array which shifts the multiplicand in the M-register appropriately into the SDS-array. Task stage MPY-^ updates the counter ICC and transfers UQ contents direct to LQ for the right shifting of the multiplier. The path for right shift from LQ to UQ was set up in task stage MPY-3 (SLQR8UQ). This task stage also provides the necessary time interval for the SDS-array to settle down. Task stage MPY-5 transfers the partial product at the output of SDS-array to the registers LM and LS and also gates the output of LQ to UQ with an eight-bit right shift. Since the task stage MPY-6 provides the gating signals for the transfer of the contents of LS and LM (which is the partial product) into registers US and UM respectively, a special action has to be taken, in case long fixed point product generation is complete, before entering the task stage MPY-6 after going around the multiplication loop four times. In this case, the task state MPY-5 sets up a data path for direct transfer of redundant- form product into registers US, UM for conversion to conventional form by sub- sequence ASIM, later on, in the sequence. This special action is necessary because task stage MPY-3 had set up a path between LS, LM and US, UM which would have right shifted the contents of LS, LM by 8 bits. 95 Task stage MPY-6 besides gating the contents of LS, LM into US, UM with an appropriate shift, also generates the control signal LDMEXPRE which provides, in case of floating point, extended precision of four bits. For a detailed discussion of extended precision, refer to Section 2.9.3 of DCS Report No. 366. Care should be taken to understand the timing relationship between the control signals MEPGATE and MEPLATCH because of the Earl latch type buffer used for extended precision bits MEPPO, MEPB - MEPB, . Sequence stage S6 detects whether the redundant form product genera- tion loop should be terminated or continued. The termination condition is detected by the logic for control signal MPYSTOP whose Boolean expression is given below. MPYSTOP = FLT-ICCEQJ „ LFIX'ICCEQU „ SFIX-ICCEQ2. Task stage MPY-T breaks the data path between UQ and the multiplier recoder and sets up the control signals NEGO, NEG1 and data input Yl to appro- priate state for the assimilation of the redundant form product to conventional form. Task stage MPY-8 calls upon the subsequence ASIM which provides the proper signals for converting the result to the conventional form. The conven- tional form result is available in register LM. Task stage MPY-9 transfers the result to result register UQ. Sequence stage S9 branches the control to task stage MPY-10 if the multiplication operands are fixed point type. Task stage MPY-10 checks for the overflow condition and accordingly sets the overflow flip-flop V to the appropriate state. In case of floating point operands, the control branches to sequence REFOTRAN via subsequence EXIT directly from sequence stage S9 whereas in case of fixed point operands, the control goes to terminating sequence REFOTRAN at the end of task stage MPY-10. 96 MPY-2 CLUQSFF SEULALLZER0 CSR LDUQ EXIT (Entry h) S0 2 = FLT. (UHEZ v UQEZ) SO = FIX. (UHEZ V UQEZ) T5 2 = (NONE) T5, = MPYST0P.LFIX T6 = MPYST0P.FLT T6 £ = NONE T3, = NONE T3 = SIGNA © SIGNB . T 3 3 = T3 2 S6 1 = MPYSTOP s6 £ = s5^ MPYSTOP = FLT-ICCEQ7 v LFIX-ICCEQl* v SFIX -ICCEQ2 T5 n MPY-1 UHDLH SLHR8UH SIGNBMPY— SIGNB LDUH 13, T3 13. MPY-3 SUHDM CSIGNBMPY SUSDS1 SUMDX1 SG1G2G3GU SLSR8US SLMR8UM SLQB8UQ CLICC SICCCNTUP SUQDMR LDM li MPY-3 SSR MPY-3 MPY-lf UQDLQ CNTICCUP Wait for Propagation through SDS Array. T5, MPY-5 SLSDUS SLMDUM MPY-5 m Z4DLM Tl+DIfi LDUQ To, t6„ MPY-6 LDMEXPKE MPY-6 LDUS LDUM S6, S6„ MPYEND Figure 3.6.2.1 MPY_REPROG— Multiply (Fl. Pt . and Fx. Pt.) — Redundant Form Product Generation 97 T7„ | mpt-7 SHEGO SHEG1 SMDY1 S9 n T10, T10„ MPY-10 S0V ( MKEHD ) T7 T7, MPy-7 CL1EGO CLHEG1 CY1SFF MPY-7 CLUQIMR MPY- ASIM MPy-9 SLMDUQ LDUQ S9 MPy-io CL0V EXIT (Entry >*) EXIT (Entry 1) T7 2 ■ FLT.Ut^, T7 3 - T7^ 17^^ - NONE S9 FIX FLT TIO, SFIX.SR. UQU5A0 T10 2 - V SFIX .5K. (UQ1+EZ.UQ5EZ) v sfdc .sr. uqo3a0" v SFIX.SR.UQ03EZ TIOT Figure 3.6.2.2, MPYEND — Conventional Form Product Formation 'and 0V Status Indicator Set-Up 98 3.6.3 Logic Implementation Logic implementation of the various control subsequences of MPY control sequence, other than those of terminal sequence REFOTRAN, is summarized in the table below. Control Subse- CP flow chart Corres. logic quence Name Figure Number Drawing No . MPY-REPROG 3.6.2.1 AUO-07-361-01 MPYEND 3.6.2.2 -36l-02 ASIM 3.5.2.3 -371-01* REFOTRAN _331_05 -352-01*, 05, 06 99 3.7 DIVIDE INSTRUCTION CONTROL SEQUENCE This control sequence is entered whenever the arithmetic order to be processed is 'DIVISION instruction' for "both the floating point and fixed point operands. This is the longest sequence among all the arithmetic orders processed "by the AU and fixed point division forms the major part of the control sequence. 100 3.7.1 Global Flow Description : Figure 3.7.1.1 shows the global flow diagram of 'Divide' instruction control sequence for both the fixed and floating point operands. It consists of many control subsequences (procedures) and a brief description of each is given below. The very first procedure subsequence to be entered is DFL which, in conjunction with subroutine control subsequence DIVIDE, provides for the division of floating point operands. It also sets up the data paths for the transfer of operands to the proper registers M and UM besides setting the loop counter and the 'sign of the result 'flip-flop SR. This initial set-up operation is common to both fixed and floating point operands and hence forms the initial part of DFL subsequence. This subsequence also provides, after the initial set up, an exit to subsequence DFX-DIZETCOM which forms the initial part of sequence DFX used for 'fixed point division' - arithmetic order. The subsequence DFL ultimately branches to EXIT subsequence of terminal sequence REFOTRAN where the result is formatted and then transmitted to the processor. In case of fixed point division, the first subsequence is DFX-DIZETCOM, except for the initial entrance to DFL as explained earlier. In this subse- quence, a test is made to see if either the dividend or the divisor is zero. If the divisor is zero, an error will occur. The <|>V will be set and the bogus 31 result is 2 -1. For a zero dividend and nonzero divisor, the quotient is zero, result register UQ is cleared and then control branches to EXIT subsequence of terminal sequence REFOTRAN. For nonzero dividend and divisor, a test is made if any or both of the operands is negative. If so, the contents of register UQ which holds both the operands are 2's complemented so that the quotient is 101 positive - and same control logic can be shared, as is used with floating point operands where the mantissas are always positive. The control then branches to another procedure subsequence SCALFIXDR. In this subsequence SCALFIXDR, both the divisor and the dividend in registers UH and UQ respectively are scaled by left shifting UH and UQ till the divisor is ^ 1/2 and the dividend is ;>. — *- , At the same time, a record. is kept in control counters NDRL8, NDDL8, NDRL1 and control flip-flop NDRLU of the total number of shifts made, so that both the quotient and the remainder can be post-scaled properly to calculate the correct result. This scaling is necessary so that the same algorithm and hence the control logic can be shared as with floating point operands. Now that the dividend and divisor are properly scaled, the control passes to subsequence FORMQAREM where the quotient and the remainder are calculated by calling on the subroutine control sequence DIVIDE. Actual division is per- formed by the subroutine sequence DIVIDE. The quotient and remainder obtained from the control sequence DIVIDE is in signed-digit form, but task stages DFX-22 to DFX-2U convert these into conventional form. After the quotient and remainder are assimilated into conventional form, the control goes to procedure control subsequence COSREM. The main function of this subsequence is to make the sign of remainder the same as that of the dividend and sets a control flip-flop NEGR for any necessary correction in the quotient at the same time. After the sign of the remainder is corrected, the remainder is assimilated into the conventional form and the control goes to subsequence QASS, if the arithmetic order being processed is fixed point division. However, if the arithmetic order is CVD (Convert to decimal) which shares the subsequences 102 FORMQAREM and COSREM with 'Fixed point Division' arithmetic order, the control . replies back to the calling point in CVD control sequence. In the subsequence QASS, the necessary correction of unit indicated by the state of control flip-flop NEGR, is made in the magnitude of the quotient and at the same time, a proper sign is attached to the quotient depending upon whether the sign of the result indicated by SR = (SIGNA # SIGNB) is positive or negative. Finally, the control passes on to the control subsequence RESCALEREM before entering the terminal sequence REFOTRAN. In the control subsequence RESCALEREM, the assimilated remainder which is in register UQ is scaled again to get the correct remainder. This post scaling is necessary because the divisor was earlier scaled to lie between 1/2 and 1 due to the requirements of 'Model Division'. After post-scaling, the assimilated quotient in register LM is transferred to bytes U-7 of the result register UQ which already holds the remainder in its bytes 1-3. Ultimately, the control enters the terminal sequence REFOTRAN where the flags and indicators are set and the result transmitted to the TP, before finally entering the initialization subsequence CREST. 103 Figure 3.7.1.1. Global Flow Diagram for "DIV — Division Process (Fx. Pt. and Fl . Pt.)" Control Sequence loU 3.T.2 Control Point Flow Description 3.7-2.1 DFL Figure 3.7.2.1 shows the control point flow chart for procedure control subsequence DFL. It resembles very closely the simulation flow chart with one or two differences. Task stage DFL-1 sets up data path for transfer of operands to registers M and UM and at the same time initializes the division loop counter ICC and sets the flip-flop SR to appropriate state. Register M and UM will respectively contain the divisor and the dividend. This state is common to both the fixed point and floating point divide. Sequence stage SI checks for either operand being zero. If dividend is zero (SI ), the task stage DFL-2 is entered which sets the exponent of the result to zero, the mantissa in UQ is already zero, If mantissa of the divisor is zero (SI ), control flip-flop V, to indicate overflow., is set in task stage DFL-3 and result register UQ and exponent is set to all '1' state. Both the task stages DFL-2 and DFL-3 lead finally to sequence REFOTRAN via subsequence EXIT. If the arithmetic order being processed is fixed point division, the con- trol exits to sequence DFX. In case of non-zero floating point operands (SI, ), the control branches to either task stage DFL-U or DFL-6, according as the divisor (UH) is in the range -$ (UH) < 1 or not respectively. In task stage DFL-U and DFL-5 , the contents of UH and UQ are left shifted till the divisor in UH lies between — and 1. A departure from the simulation flow chart logic should be noted here. In the simulation flow chart, only the divisor is scaled, not the dividend and the quotient is scaled in opposite direction by the same amount as the divisor towards the end of the sequence. However, in the control both the operands are scaled at the same 105 time. At first thought, it may appear to he -wrong hut the fact that any signi- ficant hits of the dividend in UQ go into first "byte of UQ and are not lost should convince the reader that this will work. Note that the top eight hits of scaled dividend do take part in the calculation of the quotient. One more thing to he noted here is that the DFL control assumes that the operands are normalized to "base l6 and it is the TP's responsibility to see that it is true . No check is made in AU for this purpose. The reason to examine UH for scaling of the divisor instead of UH is that hits UH n are zero due to the loading of the operands. Further it is necessary that dividend be less than the divisor, and it is ensured by the fact that scaled dividend in UM will contain at least five leading zeros whereas the divisor in M ,-, has no leading zero as far as calculation of quotient is con- cerned. Task stage DFL-6 gates the scaled operands in registers M and UM and also loads the loop counter ICC. Task stage DFL-T sets up a call to subroutine control sequence DIVIDE which provides the control signals to the combinational logic of Model Division and SDS-array to perform the actual division. For details of the sub- sequence DIVIDE, see Section 3.7.2.2. DIVIDE control suhsequence provides the quotient in signed-digit form in the register UH and UQ and task stages DFL-3, 9, 10 assimilate the quotient into conventional binary form. The assimilated quotient is available in register LM from where it is transferred to the result output register UQ by task stage DFL-11. Finally the control enters the ter- minal sequence REFOTRAN via subsequence EXIT where the result is normalized, properly formatted and then transmitted to the TP. 106 si. DFX (Fix Divide) DFL-1 Sl„ t S1 3 DFL-2 SEULALLZER0 CSR DFL-3 seulall^ne S0V SETUQO30NE SETUQU70NE LDUQ SI- SI, DFL-U SLHL1UH SLQL1UQ UHDLH UQDLQ DFL-5 LDUQ LDUH EXIT (Entry k) Tl 7 = (NONE) Tl = Tl 3 2 SI, = FLT.UQEZ.UHEZ Sl^ = FLT. (UQEZ v UHEZ ) si 5 =W~ g Slg = S^ = UH 9 DFL-6 LDM LDUM LDICC DFL-7 DIVIDE DFL-8 SUHDUS SUQDUM DFL-9 LDUS LDUM SNEG0 SNEG1 CY1SFF DFL-10 SLMDUQ LDUQ EXIT (Entry 1) Figure 3.7.2.1. DFL— Floating Point Division 107 3.7.2.2 DIVIDE Figures 3.7.2.2.1 and 3.7.2.2.2 shows the control point flow chart for the subroutine control subsequence DIVIDE. This subsequence provides the neces- sary timing control signals to logic hardware of MODEL DIVISION and SDS-array to perform the actual division and calculate the quotient and/or the remainder. The major difference with the simulation flow chart procedure DIVID lies mainly in the sequential nature of simulation as compared to combinational logic hardware of MODEL DIVISION used to calculate the quotient in actual Control hardware. The simulation flow chart calls upon the procedure for SDS every- time it is needed in contrast to control hardware which makes use of the four copies of SDS physically available in SDS-array. Task stage DIV-1 initializes the SDS-array to all clear state in order to set the register LM and LS to all zero state - in task stage DIV-2. It is very important that LS and LM be all clear to zero state before actual division and quotient calculation begins. Since this subsequence is also used by sequence CVD where the divisor is always ten, the task stage DIV-2 sets the control signal DRTEN if the arithmetic order is CVD, otherwise it sets the control signal MDDINT. Both the control signals DRTEN and MDDINT are input to "Divisor Interval Select" table-look up logic. Task stage DIV-3 sets up the SDS-array, the data paths for looping the SDS-array for division loop, and the data paths for left shifting the registers UQ and UH to make space for the quotient. Note that in one pass of the complete SDS-array, 8 bits of the quotient are calculated. Sequence stage S3 tests for the terminating condition of the division loop. If the necessary passes through the loop are not finished, the task 108 stage DIV-4 activates the control signal DODMD which transfers most signi- ficant six digits of the signed-digit partial remainder (dividend for the very first time) in registers of US and UM to Model Division hardware There, these six digits are assimilated into conventional form and are used in conjunction with 'Divisior Interval Select' logic output to calculate the quotient. This is shown in Figure 3.7.2.2.3 which shows the block diagram of model division. At the same time, contents of UQ and UH are transferred to LQ and LH in order to left shift the contents of UQ and UH later on in task stage DIV-9. This task stage calculates first two bits of the quotient of this pass of the loop (note that each pass obtains 8 bits of quotient). After the output of quotient select table is completely stable, the delayed control task signal LDQMS12 gates the quotient digits into the quotient buffer QM and QS. Since the quotient digits' calculation involve many levels of logic, the gating signal LDQMS12 should be delayed as much as necessary in order that the quotient digits are stable before being gated. Task stages DIV-5, DIV-6, DIV-7 also calculate the other six digits, 2 digits each, of the quotient in the same way as the task stage DTV-4. In the simulation flow charts, the setting of NFBM is shown explicitly whereas in the actual hardware, this is wired-in already as shown in Drawing AU0-07-210-C1. It is achieved by the following Boolean logic. PS n = (US, © LMo) DODMD (T © Z n JD1DMD 1 1 o v 1,3 1,2 (T © Z , ) D2DMD (T_ _ © Z_ ,)D3DMD. 2,? 2,4 v 3 9 j 3 s b Task stage DIV-8 deactivates the Model Division logic, whereas the task stage DIV-9 and DIV-10 provide the gating signals for the shift of the contents of UQ, UH, and of LS and LM into US and UM. At the same time, the task stage 109 DIV-9 decrements the loop counter by unity and the control loops hack to sequence stage S3. When all the passes through the division loop are com- plete, the quotient is in registers UQ and UH and the remainder is in LS and LM. The control now returns hack to the control point in main sequence where this subroutine control sequence was called. 110 ( DIVIDE \ DIV-1 CY1SFF CY2SFF CY3SFF CYUSFF CLNEG1 CLNEG23U 015123^ CUMDX1 CUSDS1 T2, DIV-2 SDRTEN S3 n C RETURN ) T2 = NONE S3 S3 *T2 t 2 DIV-2 DIV-3 SUMDX1 SUSDS1 SG1G2G3GU SQJBDUQH SLSL8US SLML8UM SLHL8UH SLQL8UQ T2„ DIV-2 zUdlm tUdls sicccntdn S3. DIVU div-U sdodmd UQDLQ UHDLH LDQMS12 DIV-5 SD1DMD LDQMS3U DIV-6 SD2DMD LDQMS56 Large amount of time in timing model is necessary because SDiDMD signals travel through quite a few levels. See figure 2.10.2.2 of AU manual, vol. 1. Figure 3-7.2.2.1. DIVIDE— Redundant Form Quotient Generation Ill DIV-9 tUdls zUdlm LDUQ LDUH CNTICCDN DIV-10 Figure 3.7.2.2.2. DIVIDE-— Redundant Form Quotient Generation 112 __ CNJ CM Kll"»» >->->- >- >>->->- _ CJ c\J ro ro *f fy.tpin^-iOC\J— O >->->->->>-*O_00'O*_l_l_J_l I I — I — i torn -ooooozzz z z z z z JJJJJJQWuljJldliJlJLJUJUJ UJUJUJllJ SSSSSSSZZZZZHI-I-I-Ht-HH ■z. < CD 3 CL TT TT Q O O D 55 5 S O > O o D Q _i — O — N ei o o o o o o i ' ! I I I < ^ CL LU o ' Z < Q LU O < CO CO < I I z LU r- o 3 O 3 CD a z < X CO o cr o v cj ^r u> co — ro m r~ J2 to «(/) 5 2 Z 5 o o o o o a o a i ■ ■ — « — O 3 O Ld CO Ld CD < cc o < > i- c_> c/> cr Ld > Ld Ld Q z CO I O o o o 5 S 5 5 O o Q Q OhNIO Q D Q O o o H CO H > w Q § bO CLJ •H P ^ O o r-t on CM c\j 00 0) Jh S, ■H 113 3.7.2.3 DFX The control sequence DFX is used for fixed point division and comprises many procedure subsequences which are DIZETCOM, SCALFIXDR, FORMQAREM, COSREM, QASS and RESCALEREM. Although procedures "by these very names do not exist in the simulation flow charts, but all the actions performed "by these subsequences are present almost in the same time .sequence as they occur in control point flow charts for DFX. There are hardly any significant differences, worth special mention, between these control point subsequences and flow charts and so the action of each task stage will not be specifically described here. A brief functional description of each of these control subsequences is already given in global flow description in Section 3.7.1. It is hoped that the reader would have no difficulty in understanding the control flow once he knows the func- tional interpretation of each control signal in the task stages of these con- trol subsequences and also if he has carefully studied and understood the simu- lation flow charts. lilt SCL SO, SCL Tl, DFX-1 SNEG0V7 SUQ33DUS33 DFX- 2 SLMDUft LDUM CY1SFF CLNEG1 SLML32UH i. DFX-3 ASIM DFX-U LDUH LDUQ03 DFX- 5 CLUQ65 CLUQSFF LDUQ>7 SCALFDCDR Tl„ Tl., Tl,. Tl„ DFX-1 SNEG0O3 SUQ1DUS1 DFX-1 CLNEG0O3 - 1 DFX-1 CLNEG047 DFX-1 CLUSSFF LDUS DFX-6 Tl, = UQ. 33 Tl r (NONE) Tl„ = UQ, Tl, Tl, SO, = UQ 33 ^ = UQ r UQ^ UHEZ.UQ03EZ.(UQ v UG^) SO„ = SO, T6 1 = P6 3 = T6,= t6„ = (S0 1 V SOj) = UHEZ.UQ03EZ (UHEZ v UQ03EZ) UHEZ.UQ03EZ (NONE) UHEZ (UQ 33 v UQ 1 ) UHEZ.SIGNA UHEZ UHEZ.SIGNA Figure 3.7-2.3.1. DFX_DIZETCOM— Fixed Point Division- Divisor /Dividend Zero Test and 2's Complementation 115 ,i ,i 38 12 DFX- 11 UQDLQ SLQL8UQ SICCCNTDN SNDDL8UP DFX- 12 LDUQ CTJTICCDN CNTNDDL8UP 36, S8 11 DFX-9 UHDLH SLHL8UH SICCCNTUP SNDRL8UP [SCALFDCDR] s8 23 DFX-17 SICCCNTUP OWICCUP DW-10 LDUH cimccup CNTNDRLSUP FORMQAREM 36, DFX-7 UHDLH UQDLQ SLHR8UH SLQR8UQ SNDRF.8 DFX-8 LDUH LDUQ S8„ 88, 22 DFX- 15 UHDLH UQDLQ SLHL1UH SLQL1UQ SNDRL1UP S8 21 DFX- 13 UHDLH UQDLQ SLHLtoH SLQLtoQ ' DFX-16 LDUH LDUQ CNTNDRL1UP I n DFX-lU LDUH LDUQ SNDRLl* S6 X - UQ18EZ.UH18EZ 36, *I 8& 1 - (UH916EZ v UQ916EZ) S8 2 - sB^ S8 n - UH916EZ S8 12 - UQ916EZ.UH916EZ S8 gl - UH912EZ.UH1316EZ 58 22 = UH912EZ.UH 58 23 - UH 9 UH916EZ = UH912EZ.UH1316EZ UQ916EZ - UQ912EZ.UQ1316EZ Figure 3-7.2.3.2. SCALFIXDR— Scale Fixed Point Divisor and Dividend 116 ( CVDIV ) [FORMQAREMj DFX-19 SUHDUS SUQPUM LDUS LDUM S20, 520 1 = ICCGTZ 520 2 = ICCGTZ DFX-18 SUHDM CLUSSFF CUQ133DUS133 SUQPUM LDM LDUM LDUS DFX-20 CLUQSFF CLUQ65 CLUHSFF LDUH LDUQ S20„ DFX-21 DIVIDE DFX-22 SLSDUS SLMDUM LDUS LDUM DFX-23 SNEG0 SNEG1 CY1SPT DFX-2^ ASIM COSREM Figure 3.7-2.3.3 FORMQAREM — Form Quotient and Remainder 117 S24, S2**-, S24. T25-, DFX-25 SNEGR S27 n C RETURN CVD ) T25, T25, DFX-25 SMDY1 - 1 DFX-25 STENDY1 i . DFX-26 SNEG0 SIGNACDNEG1 DFX-27 ASIM S27, QASS T25, > t DFX -25 CY1SFF S2U = UL.SIGNA.CVD S2^ 2 » (LR, v SIGNA) S2U„ LN^, SIGNA. CVD T25 x = LM L T25 2 = LM^DIV T25, = LM^CVD T25^ = LM X . SIGNA S27, = CVD S27 2 = S27^ Figure 3. 7-2. 3. U. COSREM— Correct Sign of Remainder 118 1 DFX-28 SUHDUS SUQDUM SLMDUQ. CIMSFF LDUS IDUM LDM \ DFX-29 LDUQ CIJJEG0 T3C \< T30 2 ,, DFX-30 ,. BY SMDY1 SETM61+0NE ' 1 3FX-31 SRCDNEG1 — — 1 D] ^-32 ASIM ' r RESCALEREM T30 x = NEGR T30 2 = NEGR Figure 3.7.2.3.5. QASS -^Quotient. Assimilation into Conventional Representation 119 DFX- JDDI ■'•DNDRI^. DFX-35 3NDRI.8DN UwDLQ S INJECTS ICTI ' DU'./ dfx -3^ •iHDRRR SNDR1.8DN DFX-36 NTNDR] ^D!: S3B, dfx-'i UOJDI-G SI.QL8U0 DUC - SICR1U0O3 SNDR1 1DN "NTNDR I 1DN S32, B3 S33, - NDRRP.NDRI.fEr 837, = ndrlU S37 ? = s?7~ S33 2 = NDRR.'-.NDRlBEr S33, = NDRJ^.MLWLOi^ 833^ = NDRrF. NDRL8EZ S38 1 ■ NDRL1EQZ S38 ? = Wl S37,. DFX- 38 UQDLQ slqrUuq sinjectsign LDUO S38„ DFX-UO SLMDUQ LDUQU7 EXIT (Entry k) Figure 3.T.2.3.6. RESCALEREM — Remainder Postscaling 120 3.7.3 Logic Implementation - Table below shows the various control subsequences necessary for the DIV control sequence for both fixed point and floating point operands. It also shows the figure number of their control point flow charts and the number of corresponding logic drawing on which these flow charts are implemented. Besides, this also shows the drawing numbers of TSC drawings. Control Subse- CP flowchart quence Name Figure No. DFL 3.7.2.1 DIVIDE 3.7.2.2.1 3.7.2.2.2 ASIM 3.5.2.3 DFX-DIZETCOM 3.7.2.3.1 SCALFIXDR 3.7.2.3.2 FORMQAREM 3.7.2.3.3 COSREM 3.7.2.3.U QASS 3.7.2.3.5 RESCALEREM 3.7.2.3.6 REFOTRAN Counters Task Signal Collector "B " Task Signal Collector "B " Corres. Logic Drawing No . AUO-07-371-01 -371-02 -371-02, 03 -371-01+ -371-01+ , 05 -371-08 -371-08 -371-09A -371-09B -371-10, 11 -332-05 -352-0^, 05, 06 -371-15 -371-12 -371-13 Task Signal Collector "B " -371-1^ 121 3.8 NUMBER SYSTEM CONVERSION CONTROL SEQUENCES 3.8.1 Introduction This section describes control sequences which are used to transform an operand of a given number type into an equivalent operand of another specified number type. These sequences are CVL (Convert to Long Fixed Point), CVF (Con- vert to floating point) and CVD (Convert to Decimal). Each of these control sequence corresponds to one arithmetic order of the same name. Each control sequence is broken up into many Procedure Subsequences which are functionally meaningful and ease the comprehension of the control flow. In many cases, these subsequences bear the same name as the various procedures in simulation flow charts. 122 3.8.2 Conversion to Long Fixed Point (CVL) Control Sequence This control sequence is used to convert either a floating point number or a decimal number into a long-fixed point number. If the converted fixed 31 —31 number is greater than (2 -l) or less than (-2 ), an overflow will occur and the result returned to TP will be the low order 31 bits with correct sign bit. 123 3.8.2.1 Global Flow Description Figure 3.8.2.1 shows the global flow diagram for the CVL control sequence. As can be seen from the flow diagram, there are two distinct types of CVL: floating point to long-fixed point number and decimal to long-fixed point number. In order to convert a floating point operand into long-fixed type, the subsequence CVL-FLT in entered by the control. Since the exponent is represented in excess 6U , this sequence subtracts 6U from the exponent and then checks whether the long-fixed-point number equivalent to the given floating point number can be represented in one word. If the absolute value of the 21 given floating point number is less than 1 or greater than l6 , the converted number is zero and accordingly the result register is set to zero. If the absolute value |x| is l6 < |x| < l6 " i.e. if the exponent lies between 8 and 21, converted number will overflow but will possess significant digits so that low-order 31 bits with correct sign are transmitted to the process along with an overflow indicator flag. In case the exponent is less than or equal to 21, the CVL-FLT control subsequence' calls the subsequence FL-N0RM-FX which converts the floating point number to a double word fixed point number by shifting right or left the contents of UQ register according to the exponent of the floating point number. The control sequence FL-N£RM-FX has exactly the same functional significance as the same procedure in simulation flow chart. If the floating point number is negative, then the converted long- fixed point number is converted to 2's complement form by entering the control subsequence NEGATE which calls upon the subroutine control subsequence COMPL. 12k Then the control passes on to subsequence LUQ which left adjusts the UQ„ Finally, the control branches to terminal sequence REFOTRAN. However, if the given number to be converted is decimal, the control enters the subsequence CVL-DEC which calls upon the subroutine control sequence DVB to convert the decimal digits into binary bits which are right adjusted in register UQ. The control sequence DVB itself makes use of subroutine control sequence ASIM. Again, if the given number is negative, the converted number obtained from subsequences DVB is transformed to 2's complement representation,, by the subsequence NEGATE. Then the control passes on to subsequences LUQ which left adjusts the contents of UQ so that the first word transmitted out of UQ to TP will contain the necessary converted number and the flag indica- tors. Finally, the control branches to terminal sequence REFOTRAN via subse- quence EXIT, which transmits the result to the processor. The processor will ignore the second word of UQ transmitted in subsequence X-0UT because this word contains no useful information. 125 . ,2.1. Global Flow Diagram for "CVL — Conversion to Long Fixed Point" Control Sequence 126 3.8.2.2 Control-Point Flow Description When the given operand to be converted is floating point type, the number is in register UQ, bits 9 through 6k and the exponent is in register EUU, in contrast to the simulation flow chart and the sign bit of the given operand is in SIGNA control flip-flop. 127 3.8.2.2.1 CVL-FLT The control enters the subsequence CVL-FLT whose control point flow chart is shown in Figure 3.8.2.2.1.1. Task stages CVL-1 and CVL-2 transfer the contents of EUU i.e. the exponent of the operand to the counter register EUL through the exponent adder path. This transfer is necessary because the exponent 'magnitude check logic' is at the output of counter- register EUL only. Note that no subtraction of 6h is done in control hardware because the exponent magnitude check logic can handle excess 6k representa- tion easily. Secondly, the sum or difference of exponents in registers EUU and EUM available in EUL is always in excess 6U representation. Sequence stage S2 checks the exponent to see whether the converted number will be all zero (S2 i.e. whether the exponent is ^0 and >2l), whether the number will overflow but have significant digits (condition S2 ) or whether the converted number will be in ranve for full significance representa- tion (condition S2^ i.e. the 1,< exponent ^8). In case of converted number being all zero, task stage CVL-U clears the result register UQ and the control then goes to terminal sequence REFOTRAK via subsequences EXIT. For overflow cases, task stage CVL-3 sets the control flip-flop 4>V and then branches to task stage CVL-U if exponent is > 21 or to the task stage CVL-5 if exponent is 4 21. Task stage CVL-5 is also entered from the sequence stage S2 under condition S2 . Task stage CVL-5 calls the subroutine control sequence FL-N0RM-FX shown in Figure 3.8.2.2.2.1. This sequence shifts the number in UQ either to the right if exponent is less than lU, to the left if exponent is greater than lU or none at all if exponent is lU. At the end of FL-N0RM-FX control sequence, the floating point number is changed to an equivalent double word fixed-point number in register UQ. 128 Sequence stage S5 checks whether the converted number has overflowed - (i.e. number is >(2 31 -l) or < (-2 31 ). Task stage CVL-6 sets the control flip- flop <|>V in case of overflow, and then the control passes to procedure subse- quence NEGATE shown in Figure 3.8.2.2.1.2. If the given number to be converted is positive, the NEGATE subsequence is bypassed and the control goes to subse- quence LUQ, which left adjusts the contents of UQ. If however, the number is negative, Task stage CVL-10 clears the register US and sets the negate con- trol signal NEG0 so as to complement the output of UM. Task stage CVL-11 calls the subroutine control sequence COMPL where the contents of UQ are complemented with the help of SDS-array, assimilated into conventional form and then transferred to the result register UQ. Control point flow chart for COMPL is shown in Figure 3.8.2.2.5.1. At the end of NEGATE subsequence, the converted number is available in result register UQ but right justified. However, since the TP expects the converted number in the very first word transmitted to it, and secondly since the flag indicators V and ID are transmitted always with the first word, the contents of UQ must be left adjusted. So the control passes to the procedure control subsequence LUQ whose 'control point flow chart is shown in Figure 3.8.2.2.U.1 and is explained in Section 3.8.2.2.1*. After the converted number is left adjusted in result output register UQ, the control finally passes to the terminal sequence REFOTKAN via the sub- sequence EXIT. 129 S2, CVl.-k <"LUQSFF LDUG EXIT (Entry V CLEUMSFF SEUMEZ CEUDIFF LDEUM CVL-2 LDESDEUL S2„ S2 X = EULLEZ - EU11 S2 2 - EULGT8 v EULCT21 S2, - S2 1 v S2 ? S0V CVL-3 S5, S3, CVL-5 FL-N0RM-FX CVT-6 S0V NEGATE S3 2 « EULGT8.EULGT21 S5 X - W^ v SIGNA » S5^ S5g = UQj,. SIGNA Figure 3.8.2.2.1.1. CVL_FLT— CVL Floating Point Operand 130 S9-, S9. CVL-10 CLUSSFF SNEG0 LDUS CVL-11 S9 X = S9 2 S9 2 = SIGNA Figure 3.8.2.2.1.2. NEGATE— Negate a Positive Number 131 3.3.2.2.2 FL-N0RM-FX This sequence is shown in Figure 3.8.2.2.2.1 and is absolutely identical to the simulation flow chart of the same name. Its functional descrip- tion is already fiven in global flow description. Task stages FLX-1 and FLX-2 decrease the exponent in EUL "by lU. Task stage FLX-3 is a dummy stage with no task signals hut acts only as a time buffer for the sequence condition, obtained from the tEUL condition detect logic', to be stable. Task stage FLX-U shifts the contents of UQ by eight bits either to the left or right according as the exponent difference is positive or negative, where Task-stage FLX-5 shifts the same by four bits. The number of shifts necessary is dependent on the difference as obtained in Task stages FLX-1 and FLX-2 . 132 FLX-l SEUMEQlU SEUDIFF LDEUM FLX-2 CBY0NE LDESDEUL FLX-3 Wait for EUL Condi- tion Detect Logic to settle S3, TU, S3. Tl+, TU, T5- T5i FLX-1+ SLQL8UQ CEUCTRDIR FLX-U SLQR8UQ SEUCTRDIR FLX-1+ UQDLQ, LDUQ CP FLX-5 UQDLQ LDUQ T5, FLX-5 FLX-5 SLQLlrtJQ SLQPUUQ 53 1 = (DEXPGE2 v DEXPLEM2) 53 2 = (DEXPE1 v DEXPEM1) S3 3 = (S3 1 v S3 2 l TU, DEXPGE2 Ti+ = (NONE) T5, = DEXFE1 T5 2 = DEXPEML T5, = (NONE) c RETURN J Ti+ 2 = DEXPLEM2 Figure 3.8.2.2.2.1. FL_N0RM_FX— Convert a Floating Point Operand to Fixed Point Operand 133 3.8.2.2.3 CVL-DEC The control point flow chart for this control subsequence is shown in Figure 3.8.2.2.3.1 and is entered when the number to be converted to long- fixed point format is of decimal type. The task stage CVL-8 calls the subroutine control sequence DVB which converts the decimal digits into binary bits which are right justified in UQ„ For details of DVB, see Section 3.8.2.2.3.1. Then the sequence stage S8 checks for overflow condition in the converted number and either bypasses the Task stage CVL-9 which sets control flip-flop $V or goes through it depending upon the overflow condition. Now if the original number to be converted was negative, then this converted number must be changed to 2's complement form as was done in case of floating point operands explained earlier. 13k S8, NEGATE S8, II CVL-9 S8 = UQ03EZ S8 2 = SB^ = UQ03EZ Figure 3.8.2.2.3.1. CVL_DEC — CVL Decimal Operand 135 3.8.2.2.3.1 DVB Figures 3.8.2.2.3.2 and 3.8.2.2.3.3 show the control point flow charts for the subroutine control subsequence DVB. It is used to convert the decimal digits, stored in bits 9-6^ of UQ register, into binary bits, into binary bits which are right adjusted in UQ. This routine is used both both by CVL and CVF whenever the number type is decimal. The control point flow chart is exactly identical to the simulation flow chart of the same name. The only difference is the first task stage DVB-1 which is really a dummy control point with no task signal. However, it does perform a useful hardware function in generating the return signal if the number to be converted is all zero. This control point simplifies the generation of reply signal from the DVB subroutine control subsequence. Task stage DVB-2 sets the exponent counter register EUL to 1^ and in a downward counting direction with a step down of 2 in each counting. Task stage DVB-3 shifts the contents of UQ to get rid of leading zero decimal digits. After the leading zeros are gone, DVB-U transfers the first nonzero decimal digit to be converted to register M,and the control goes to the conversion loop's first Task stage DVB-5° DVB- 5 clears registers US, UM and transfers second most significant decimal digit to register UM. Task stage DVB-6 sets up the SDS-array and M-array such that the digit in register M is multiplied by 10 and added to the digit in UM. The result is available at the output of SDS*+ from where it is trans- ferred back again to register UM, US to do the assimilation of the sum obtained. Loop counter is decremented by unity and SDS-array is prepared for subroutine control sequence ASIM. 136 Task stage DVB-8 calls the control subsequence ASIM which assimilates the conversion result of preceeding digits into conventional form. Sequence stage S8 checks if all the digits have been converted. If not, contents of UQ are lect shifted by h bits, next decimal digit is transferred to M and the control loops back to Task stage DVB-5 to begin another conversion pass. If, however, all the digits have been converted, the assimilated and converted out- put is available in LM from where it is transferred right justified to result register UQ by Task stage DVB-10. 137 DVB-l Dummy SI, f RETURN J U0PI.0 LDUO CP Tl, DVB- 3 SLQL8UQ DVB-3 SLQLl+UQ SBY0NE SEULEQ1 1 * CEUCTRDIR CBY0NE I DVB-l* SUQ58DM616U S^ =. UQ17EZ S1-, ■■; S2 1 - UQ58EZ > ■ S2~~ S2, Tl ■ (none) Tl 2 ' UQ512EZ Tl • CLUSSFF CLUMSFF SUQ912R52UM LDUS LDUM DVB-6 SUSDS1 SUMDX1 nflSFT CY2SIT SML3Y3 SML1Y4 SG1G2G3GU CLNEG0 CLNEG1 SNEG2 CLNEG3 SNEGl* CLUQ912R52UM Wait for SDS Array to settle down. J DVB5 j Figure 3.8.2.2.3.2. DVB — Decimal to Binary Conversion 138 DVB-9 ( DVB7 ) DVB- 7 tUdls ZtoLM SLMDUM SLSDUS SBY0NE CEUCTRDIR LDUS LDUM CP CLNEG0 CLNEG1 CY1SFF DVB-fc ASIM S8„ DVB-10 SLMDUQ LDUQ f RETURN J S8 = EULEZ S8 g = EULEZ = SB~ Figure 3.8.2.2.3.3. DVB— Decimal to Binary Conversion 139 3.8.2.2.1* LUQ Control point flow chart for this procedure control subsequence is shown in Figure 3.8.2.2.^.1. This subsequence left adjusts the one word of data lying in the last four bytes of 8 byte long result legister UQ. Task stage LUQ-1 clears the byte shift bidirectional counter ICC and also sets it to the upward counting state. Besides, it sets up the left shift path between the register LQ and register UQ. Task stage LUQ-2 transfers contents of UQ without any shift to register LQ and updates the byte shift counter by unity. Task stage LUQ-3 gates the contents of LQ shifted 8 bits to the left into register UQ. Sequence stage S3 checks if the total shift of h bytes has taken place. If not, the control loopsback to the input of Task stage LUQ-2 and the process is repeated till sequence stage S3 detects the end of the loop Finally the control passes to the subsequence EXIT. ( LUQ J lUO i 1 LUQ-1 CLICC SICCCNTUP SLQL8UQ S3. S3 = ICCEQ14 S3 2 = ICCEQU } t LUQ-2 UQDLQ CNTICCUP 1 LUQ-3 LDUQ = S3. Figure 3. 8. 2. 2. U.I LUQ— Left Adjust Contents of Register UQ 3.8.2.2.5 COMPL Figure 3.8.2.2.5.1 shows the control point flow chart of control subsequence COMPL. This is used to do 2's complementation of the contents of UQ. This is very similar to the simulation flow chart and is fairly simple and so needs no special explanation. ll*2 SUQPUM CY1SFF CLNEG1 LDUM CMP-1 CMP- 2 CMP- 3 Figure 3.8.2.2.5.1 COMPL— Form 2's Complement of the Contents of Register UQ 143 3.8.2.3 Logic Implementation Table below lists the names of various control subsequences necessary for CVL control sequence, the figure numbers of their control point flow charts and the number of the corresponding logic drawing which implements the control subsequence. Control Subse- quence Name CP flow chart Figure No. Corres Drawin . Logic g No. CVL-FLT 3.8.2.2.1.1 AUO- -07 -382-01 FL-N0RM-FX 3.8.2.2.2.1 382-03 CVL-DEC 3.8.2.2.3.1 382-01+ DVB 3.8.2.2.3.2 3.8.2.2.3.3 382-OU, 05 ASIM 3.5.2.3 371-OU NEGATE 3.8.2.2.1.2 382-02 COMPL 3.8.2.2.5.1 382-05 LUQ 3.8.2.2.H.1 382-02A REFOTRAN 332-05 352-04, 05, 06 Task Signal Collector "C " 382-06 Task Signal Collector "C " 382-07 lUU 3.8.3. CONVERSION TO FLOATING POINT (CVF) CONTROL SEQUENCE This control sequence is used to convert either a fixed point number (both long and short) or a decimal number into a floating point number. It shares a few control subsequences which are also used by other conversion instructions. 1U5 3.8.3.1 Global Flow Description Figure 3.8.3.1.1 shows the global flow diagram for CVF control sequence. It mainly consists of one subsequence CVF-DEFIX which calls upon other subroutine control subsequences DVB, COMPL and N0RMUQ, besides the terminal sequence REFOTRAN. The control subsequence CVF-DEFIX calls upon the subroutine sequence DVB to convert the given decimal number to binary. It then loads the proper exponent in the exponent register. Later, it normalizes the mantissa of the converted number before entering the terminal sequence REFOTRAN If, however, the number to be converted is in fixed point format, this control sequence provides control signals to load the proper exponent in the exponent register EUL, to shift the register UQ in order to share the subroutine control sequence N0RMUQ. It also complements the number, in case it is negative, so that the mantissa of the resulting floating point number be positive. After complementation and normalization, the control enters finally the terminal sequence REFOTRAN . lh6 (COMPL U- (NORMUQr X°*y Figure 3.8.3.1.1. Global Flow Diagram for "CVF — Conversion to Floating Point" Control Sequence ikj 3.8.3.2 Control-Point Flow Description Figure 3.8.3.2.1 shows the control point flow chart for the subsequence CVF-DEFIX. This subsequence has two entries: entry CVFIX for fixed point operands and entry CVFDEC for decimal operands . For decimal operands, the number to be converted is in UQ register bite 9 through 6k and the sign bit is in control flip-flop SIGNA. Task stage CFD-1 calls the subroutine control sequence DVB described earlier in Section 3.8.2.2.3.1 which converts the decimal number in register UQ into an equivalent binary number which is right-adjusted in result register UQ. Then the task stage CFD-2 loads the exponent result register EUL with binary number equivalent to decimal Ik , in excess 6k representation. Task stage CFD-3 calls upon the subroutine control sequence N0RMUQ which normalizes the converted number to lie between l/l6 and 1. Control point flow chart for subsequence N0RMUQ is shown in Figure 3. U. 2. 1.1. Task stage CFD-U loads the control flip-flop SR (which gives the sign of the result) with the sign of the number to be converted and finally the control goes to terminal sequence REFOTRAN via subsequence EXIT. For fixed-point operands , the number to be converted is in register UQ bits 1 through 32. Task stage CFX-1 loads the exponent result register EUL with an excess 6k binary representation of decimal 8 and at the same time shifts the contents of UQ right by 8 bits so that it can share the subroutine control sequences COMPL and N0RMUQ. If the given fixed-point number is negative (sequence condition SI ) , the task stages CFX-2 and CFX-3 complement the given 2's complement representation of fixed-point operand in register UQ so that a positive mantissa can be obtained. Then the control branches to task stage CFD-3 and follows the same path as in case of decimal operands. 1U8 si. CFX-2 SSIGNA SNEG0 CLUSSFF SUS9 LDUS ' r CFX-3 COMPL ( CVFIX \ ■ ' CF X-1 SEULEQ8 UQDLQ SLQR8UQ LDUQ [ CVFDEC ] Sl„ CFD-1 DVB H CFD-2 SEULEQ14 ■ i CFD-3 N0RMUQ ' ' CFD-1+ SIGNADSR EXIT (Entry k) Sl x = UQ 9 Big = UQ 9 Figure 3.8.3.2.1 CVFJDEFIX — CVF Decimal and Fixed Point Operands lU9 3.8.3.3 Logic Implementation In the table below is shown the names of various control subsequences which make up the CVF control sequence, the figure numbers of their flow charts and the number of the corresponding logic drawing which implements the control sequence in hardware. Control Subsequence CP Flowchart Corres . Logic name Figure No. Drawing No . DVF-DEFIX 3.8.3.2.1 AUO-07-383-01 DVB 3.8.2.2.3.2 -382-OU 3.8.2.2.3.3 -382-05 COMPL 3.8.2.2.5.1 -382-05 N0RMUQ 3.^.2.1.1 -352-OU REFOTRAN -332-0 5 352-OU -05 -06 150 3.8.U CONVERSION TO DECIMAL (CVD) CONTROL SEQUENCE This control sequence is used to convert either a fixed point number (both short and long) or a floating point number into a decimal number of Illiac III format. 151 3.8-4.1 Global Flow Description Figure 3.8.4.1.1 shows the global flow diagram for CVD control sequence. This control sequence comprises of many subsequences some of which are shared, by other arithmetic order control sequences. The first subsequence CVD-FIXOCAFLOX calls upon the subroutine control sequence COMPL to complement the given fixed point number if it is negative. In case of floating point number, a check, is made to see if the given floating point number will give rise to an out-of-range converted decimal number. If so, the control flip-flop 0V is set. Further, if the exponent is so large that no significant figures in the converted number can be represented in result register UQ of finite length, then the result register is cleared and the control branches to the procedure control sub- sequence SETSIGN which generates the decimal code for sign of the number and finally the control enters the terminal sequence REFOTRAN. If, however, the converted number is within the range of representation with at least some significant digits, the control calls upon the subroutine control subsequence FL-N0RM-FX which converts the floating point number into an equivalent fixed point representation. The control then branches to subsequence GETDEC which converts the so far obtained equivalent fixed point number into an equivalent decimal number, in concert with the control subsequence QUODECM. The control sequence GETDEC calls upon the subroutine control subsequence FORMQAREM at entry marked CVDIV to divide contents of UQ or partial remainders by 10 to obtain decimal digits. Subsequence QUODECM decreases quotient by 1, if the remainder obtained by FORMQAREM is negative. 152 After the equivalent decimal number has been obtained, the control subsequence GETDIG transfers the converted decimal number to the result output register UQ and then the control passes on to the control subsequence SETSIGN. This subsequence generates the decimal code for sign of the result in the result register and finally the control enters the terminal sequence REFOTRAN for flag setting and final onward transmission to the TP. 153 ( COMPLj Figure 3. 8.U. 1.1. Globa] Mow Diagram for "CVD-- Conversion to Decimal" Control Sequence 15* 3.8.U.2 Control Point Flow Description The control point flow chart of CVF control sequence involves many control point subsequences as explained in the global flow diagram. A brief description of control point flow chart associated with each of the subsequences is given below. These flow charts resemble very closely the simulation flow charts. 155 3.8.^.2.1 CVD-FIXOCAFLOX Figure 3. 8. k. 2.1 shows the control point flow chart for this subsequence. For a fixed point number, the number to be converted is in register UQ bits 33 through 6U, >fcere bit 33 is the sign bit. For a floating point operand, the mantissa of number to be converted is in reg- ister UQ bits 9 through 6h and the exponent is in register EUU of the exponent arithmetic unit. Task stage CVD-1 provides control signals to transfer the exponent via the EU Adder to the input of register EUL of the exponent arithmetic unit. Note that this task stage is entered even if the given number to be converted is of fixed point type. It is unnecessary to do so, but it was allowed to stay because it does not do any harm. Task stage CVD-1 also temporarily stores the sign of the operand in control flip-flop SR. If the fixed-point number to be converted is negative (SI ) , task stage CVD-2 transfers the number to register US and sets the control signal NEG0 to appropriate state so that the number can be complemented by subroutine control sequence COMPL which is called by the task stage CVD-3. After the number has been complemented, the control branches to procedure control subsequence GETDEC. If number to be converted is fixed point and positive (SI ) , the control from the sequence stage SI directly passes to the sub- sequence GETDEC. In case of floating point operand (SI ), task stage CVD-U gates the output of exponent unit adder to register EUL. Transfer of exponent to register EUL is necessary because exponent magnitude 'detection logic' is at the output of register EUL only. 156 Since the decimal number can have only ik digits and if the absolute / Ik V '- value of the floating number to be converted is greater than (10 -1) which is less than l6 , an overflow indicator should be set if exponent is >_13. Task stage CVD-5 sets the control flip-flop 0V when such a condition occurs . However, if the 13 <_ exponent <_ 28 (sequence condition S5 ) , the converted number will still have some significant digits and so the control branches to task stage CVD-7 which calls the subroutine control subsequence FL-N0RM-FX. If exponent >28, the converted number is too large to be represented by any significant digit in the finite length result register UQ and the control goes to task stage CVD-6 which clears the result register UQ. Then the control branches to procedure control subsequence SETSIGN to generate the decimal code for sign of the number. In sequence stage Sk , if < exponent < 13 as indicated by condition Sk , the control directly goes to task stage CVD-7. However, if the exponent <0, the given floating point number is a fraction and hence the equivalent decimal integer number is zero and so the control branches to task stage CVD-6. Task stage CVD-7 calls the subroutine control subsequence FL-N0RM-FX which transforms the given floating point number to a fixed point number. From the output of task stage CVD-7, the control passes on to the procedure control subsequence GETDEC . The reader should note that the simulation flow chart on page 106 of DCS Report Wo. Ul8 does not show the checking of condition EULGE13 to set the overflow indicator. But, it still would not cause any problems because the overflow condition would again be detected in procedure GETDEC when ND becomes greater than ik . si. c;m-i CIUSSFF SUQ33DUS?? CLNEG05 SNEGV7 LDUS ZVD-i :ompl GETDEC CVD-1 CLEUMSFF SEUMEZ CEUDIFF SIGNADSP, CSIGNA LDEUM Sl+, S5, 1 CVD-7 FL-N0RM-FX SI. \> CVD-k LDESDEUL 3^ CVD-5 S0V 157 su. S5, :vd-6 CLUOSFF LDUQ SETSIGN SI = FIX.UQ33 Sl 2 - FDC.UQ33 SI = FIT SU = DEXPGE13 SU, = DEXPGTZ-DEXPGT13 SU = DEXPGTZ S5, = EULGT28 S5 2 = EULGT28 Figure 3. 8. h. 2.1. CVD_FIXOCAFLOX—CVD_ Fixed Point Operands' Complementation and Floating Point to Fixed Point Conversion 158 3.8.U.2.2 GETDEC Figures 3. 8. k. 2. 2.1 and 3. 8. h. 2. 2. 2 show the flow charts for control subsequence GETDEC which provides control signals to generate decimal equivalent of the contents of UQ. The decimal digits are available in register M at the end of the sequence. In brief, the algorithm to do the conversion is as follows. The contents of register UQ is used as dividend and is divided by 10. The decimal digits are generated from the least significant to the most significant. The remainder after each division is a decimal digit. The M register is used to store the converted decimal digit. Every time a division is completed, the contents of M is right shifted four bits and the new remainder (bite 9-12 of LM register) i.e. the decimal digit is inserted in bits 9-12 of M. The quotient formed in registers UH and UQ is used as the new dividend to calculate the next decimal digit and the whole process is repeated until the number of decimal digits formed exceeds ik or the contents of register UQ is zero. Task stage CVD-8 loads the division loop counter ICC and also clears the decimal digit counter WD. The control now passes to decimal-digit- calculation loop. Task stage CVD-9 increments the counter WD. Sequence stage S9 checks if more than ik digits have already been formed, and if so, the decimal number has overflowed. Thus, the control branches to task stage CVD-10 which sets the control flip-flop 0V and later the control goes to procedure control subsequence SETSIGW. If, however, the number of decimal digits formed so far has not exceeded lU, more decimal digits need to be formed and the control goes on to activate, in parallel, the task stage CvD-11 and the dividend-scaling loop consisting of task stages CVD-13, lU, 15. 159 A difference from the simulation flow chart should be noted here. In simulation manual, the shifting of M by four bits to the right is done first, and the scaling of dividend in register UQ, UH is done later in time sequence due to sequential nature of simulation. However, since the control hardware can execute in parallel, the M-shift control consisting of task stages CVD-11 and CVD-12 and the dividend scaling loop are activated in parallel because both involve separate and independent hardware. Task stage CVD-11 sets up the SDS-array and sets the control signal MDYU to transfer contents of M to the output of SDS array. At the same time, it sets up the data path for the right shift of the contents of register LM and then activates a delayed gate signal LDM to load the contents of LM right shifted four bits into register M. The control then waits for the dividend -scaling loop to finish. Dividend scaling loop scales the dividend in register UQ lies between 1/2 and 1 and thus decreases the number of passes through the division loop. Task stage CVD-13 shifts the contents of UQ and UH, left by eight bits and at the same time sets the ICC counter to downward counting state. Task stage CVD-lU activates the count down pulse and the control loops back to do further shifting. If all the top eight bits of the dividend are not zero, the contents of UQ and UH are shifted left by four bits and then the control waits for a reply from the task stage CVD-12 of M-shift logic. When both the in-parallel activated control chains have replied as indicated by the 'JOIN* symbol, the task stage CVD-16 calls the subroutine control sequence FORMQAREM at entry CVDIV to divide the dividend in UQ by 10. i6o The subsequence F0RMQAREM gives rise to unassimilated quotient in registers UQ, UH and the assimilated remainder in register LM. If, however, the remainder is negative, then subsequence COSKEM corrects the remainder such that it becomes positive and also sets the flip-flop NEGR. This corrected remainder is the correct decimal digit. The control now passes to procedure control subsequence QUODECM whose control point flow chart is shown in Figure 3.8.4.2.2.2. Sequence stage SI 6 tests whether the control flip-flop NEGR is set. If so, the remainder in subsequence F0RMQAREM was negative and the quotient must be decremented by unity. Task stages CVD-17, 18 and 19 perform this function via the SDS-array. Task stage CVD-1T transfers the unassimilated quotient from registers UQ, UH to the registers UM, US which serve as input SDS-array. Task stage CVD-18 sets up and activates the SDS-array for decrementing the contents of US, UM by unity. Task stage CVD-19 is a dummy stage and only acts as a time buffer to allow the SDS-array to stabilize. Task stage CVD-20 transfers the bits 9-12 of LM to the bits 9-12 of register M. This is the corrected remainder (hence, the correct decimal digit) obtained earlier in subsequence COSREM of subsequence F0RMAQAREM. It should be carefully noted here that whereas in the simulation flow chart the transfer of LM to M is shown to be done before decrementing the quotient, it cannot be done in actual hardware. The reason is that in task stage CVD-18, one needs to clear the register M and turn on control signal SETM6U0NE to achieve Y ^ = and Y^, = 1 for unity decrementation of the quotient . So it had to be postponed to the task stage CVD-20 but before CVD-21 because in CVD-21 the original contents of LM is destroyed. 161 Task stage CVD-21 transfers the decremented quotient from the output of SDS-array to registers LS , LM and then gates them into the registers UH, UQ, respectively. Task stage CVD-22 again transfers this corrected quotient which now serves as the new dividend for the calculation of another decimal digit to input registers US, UM of SDS-array and the control loops back again to calculate new decimal digit. The control continues to loop till either the quotient is zero (S8 ) whence the control branches to subsequence GETDIG or till Ik decimal digits have been formed in which case an overflow flip-flop 0V is set by task stage CVD-10 and control branches to SETSIGN control subsequence. 162 CVD-10 CVD-8 SICCEQ7 CLNDCNT CLUQ55 LDICC S8, ii CVD-9 CNTND S8„ GETDIG 38^^ = UQEZ-UQ65 = S8 2 S8 2 = UQEZ.UQ65 S9 = NDEQ15 59 2 = NDEQ15 59 3 = UQ9X6EZ S9 U = UQ916EZ CVD-16 F0RMQAREM (Entry CVDIV) GETDEC. QUODECM Figure 3. 8. U. 2. 2.1 GETDEC_CAQOREM— Generate Decimal Digits- Calculation of Quotient and Remainder 163 Sl6, Sl6„ CVD-17 SUHDUS SUQDUM LDUS LDUM CVD-18 CLNEG0 CLNEG1 CLNEG23 1 * SG1G2G3G4 SMDY1 CY2SFF CY3SFF CYl*SFF SLSDUH SLMDUQ CLMSFF SETMS40NE SUSDS1 SUMDX1 LDM CVD-19 Walt for SDS Array and Prop. Logic to settle down CVD-i SLM912DM912 S20, S20„ Zl*DLM TUDLS cyn-2i LDUH LDUQ Sl6 1 - NEGP Sl6 2 - NEGR S20 • irecR 820 2 • NEGR CVD-22 BUHDU8 SUQDUM LDUM LDUS Figure 3. 8. U. 2. 2. 2. GETDEC_QUODECM— Generate Decimal Digits- Quotient Decrement 16k 3.8.4.2.3 GETDIG Figure 3. 8. k. 2. 3.1 shows the control point flow chart of control subsequence GETDIG, whose function is to transfer the converted decimal number in register M to the output result register UQ. Since there is no direct path from M to UQ, the transfer takes place through the SDS-array and registers LM, LS . Task stage CVD-23 sets up the SDS-array for the transfer of the contents of M to the output of SDS-array via the M-shift array control signal MDYU. Task stage CVD-24 loads the output of SDS-array into register LM and clears the register UQ. Task stage CVD-25 transfers the contents of LM, the converted decimal number to the output result register UQ. Then the control goes to subsequence SETSIGN. 165 CLUQOT SMDYU CY1SFF CY2SFF CY3SJT CLG123U CLNEG0 CLNEG1 CLNEG23U CUSDS1 CUMDX1 Wait for SDS Array and Prop. logic to settle down. CVD-21+ zUdlm LDUQ CVD-25 SLMDUQ LDUQ SETSIGN Figure 3. 8. U. 2. 3.1 GETDIG — Transfer Decimal Digits to Result Register UQ 166 3.8.4.2 .U SETSIGN Figure 3.8.4.2.4.1 shows the control point flow chart of control subsequence SETSIGN. This subsequence is very short and involves only one task stage . Task stage CVD-26 generates the binary pattern for the decimal code for plus or minus sign of the number to be converted and gates it into bits 5-8 of result register UQ. Now the result is ready to be transferred out to the processor and the control passes on to the terminal sequence REFOTRAN via the subsequence EXIT. 167 CVD-26 SETDECSIGN LDUQ EXIT (Entry k) Figure 3.8.U.2.U.I. SETSIGN— Set Proper Decimal Sign Code in Result Register UQ 168 3.8.U.3 Logic Implementation Table "below shows the names of the various control subsequences which comprise the CVD control sequence. It also lists the figure number of their flow control point flow charts and the number of corresponding logic drawing which implements the subsequence in hardware. Control Sequence CP Flowchart Corres . Logic game Figure No. Drawing No. CVD_FIXOCAFLOX 3. 8. k. 2.1 AUO-07-381+-01 FL-N0RM-FX 3.8.2.2.2.1 -382-03 CQMPL 3.8.2.2.5.1 -382-05 GETDEC__CAQ0REM 3. 8. k. 2. 2.1 -38U-02, 03 F0RMQAREM 3.7-2.3.3 -371-08 COSREM 3.7-2.3.U -371-09A GETDEC_QU0DECM 3.8.^.2.2.2 -38U-0U GETDIG 3. 8. k. 2. 3.1 -38U-05 SETSIGN 3.8.U.2.U.1 -38U-05 REFOTRAN . -332-05 -352-0U -05 -06 Task Signal Collector "D" -38U-06 169 3.9 INITIALIZATION AND POWER TURN-ON. This section describes the initializing control subsequence CREST which forms the last part of every arithmetic control sequence. This sequence clears all the memory elements in the control logic and readies the control for the process- ing of next arithmetical order. In addition, this section also describes very briefly the power turn-on. 170 3.9.1 CREST Figure 3.9.1.1 shows the control point flow chart of this control sub- sequence. There is hardly any sequence involved here because it consists of only one task stage. This sub-sequence is entered at the end of the control sequence of every arithmetic order after the terminal sequence REFOTRAN. This sub- sequence is used to clear every memory element in the control hardware e.g. con- trol points, control flip-flops, selector switch flip-flops as well as many registers in the processing hardware. Task stage CLR-1 is implemented with a DETAG type control point, as shown in Drawing AU0- 07-399-01. The regular task signal activates the control signal COMCLR which clears most memory elements except the hardware registers. Control signal COMCLR puts an all-zero pattern on the input of various hardware registers by resetting all the selector switches, but a gate signal is necessary to feed this all- zero pattern into the registers to clear them. This signal is provided by delayed task signal CLREGS (CLRlDTl) which acts as the clearing gate signal to the various registers. After this clearing and resetting operation is over, the control goes back to Operand Input load (VIW) control sequence to await the arrival of a new arithmetic order and operands for processing by AU. ( CREST ) 171 CLR-l COMCLR CLREGS f STAVIN J Figure 3.9.1.1 - CREST - Clear and Reset 172 3.9.2 Pover Turn-ON Turning on the power or depressing a pushbutton labelled CL (Clear) in the AU activates the task stage (hence the control point) CLR1 of the control sequence CREST. This subsequence clears (resets) every memory element in the control logic hardware, for example, control points, control flip-flops selector switch flip-flops in addition to many registers in the Processing hardware logic. Section 3.9.1 gives an operational description of control sub-sequence CREST. The logic implementation of power turn-on mechanism is shown in Drawing AU 0-07-399 -01. 173 3.10 'MISCELLANEOUS' CONTROL LOGIC This section briefly describes various segments of control logic hardware which are unrelated to each other. These segments of control logic do not involve any control point flow charts. In this section, the mechanisms for electronic push-button selection of data paths and for single stepping through the control sequence are discussed. In addition, the final level task signal drivers' logic is also explained 17 U 3.10.1 Electronic Push-button Selector Switches There are many registers in the arithmetic unit which have inputs from many different sources. At any time, in general, the registers receive input from only one source. So it is necessary that at any one time, only one input path be active and the others should be inhibited. Electronic push- button selector switches provide such a function very conveniently. These switches are shown in Drawings AU0-07-390-01 to AU0-07-390-08. Basically, these selector switches consist of as many flip-flops as there are paths at the input of a register. The output of each flip-flop activates one unique path. The set and reset logic at the input of each flip-flop is very simple and acts in such a way that the set signal for one flip-flop acts as the reset signal for the other flip-flops. Thus, at one time only one flip-flop is active which activates the desired path and the other paths are inhibited because the other flip-flops are reset. That is why, this selector switching logic is called the Electronic Push-button selector switches. It is called electronic because flip-flops are electronic and no mechanical switches as such are involved. The various registers whose input selector paths are controlled by electronic push-button selector switches are UM, US, UQ, UH and register M. Besides the above registers, electronic selector switches also control SDS-array's gate signal Gi and negation signal NEGi ani the control signals of M-shift array and Model Division's Dividend selector signals. 175 3.10.2 Single Step Mode The single step mode permits one to manually control the sequential turn-on and turn-off of each control point (associated with an asynchronous operation) in any control sequence. The implication in this statement is that stepping is NOT permitted in those control points which are used for transferring data into or out of the AU. The two signals labelled EN (Enable) and GODELY (Godelay) shown in Figure 3.10.2.1 control the stepping operations. These two signals are tied to corresponding inputs of all Control Points associated with asynchronous sequencing operations. Both of these signals are in logical ' 1' state when the machine is in the Run Mode i.e. not in the Single Step Mode. When in the Signal Step mode, these two signals are always complementary (EN ^ GODELY) of each others. Note that when EN = 0, a Control Point may be "primed" (i.e. its flip-flop is set) but cannot activate a task signal; when GODELY = 0, a Control Point can come on (i.e. activate a task signal) but it cannot be turned off (i.e. its flip-flop cannot be reset). These features together with an inherent property of the Control Point. (The coming-on of any Control Point i primes the next control Point i + 1 in the sequence, but does not permit Control Point i + 1 to come on. Control Point i + 1 is only permitted to come on after Control Point i has gone off) permit the stepping mode operation. The Single Step Mode involves the use of three switches shown in the Drawing AU0-0T-399-01. These switches are called the Stepping Mode Switch SM, the STEP/RUN switch SR and the Step Switch ST. The SR switch has two positions - STEP and RUN. In the RUN position, EN = GODELY ■ 'l f ; in the STEP position, the ST switch determines which of the logical conditions "EN = '0', GODELY = »l'"or"EN = '!', GODELY = '0'" occurs. 176 The SM switch provides the option of stepping by single instruction. This is accomplished "by putting the SM switch in the Single Instruction Mode (SIN0D) position. In this position, the alternating EN and GODELY signals are only applied to Control Point CLR1; for all other Control Points, EN = GODELY = '1', When the switch SM is not in the SIM0D position, the alternating EN and GODELY signals are applied to all Control Points, including CLR1. 177 <3=£h GODELY V 1 V«rn v/I + 1 GODELY J 1+1 GODELY TM | 1 1 1 r LlM UUULLT 1 1 L 1 L <-^_ -> IN 1 — T 1 L EN 1 nn "~ 1 1 _ 1 „ Control UU] 1 Point I GODELY 1 _J 1 _J Ti" 7i + i M o t M i m A r " . *i ■^ TN I+l 1 ~1 IN I FM I + 1 1 _ 1 L N no , Control UU2 -■ - 1 _J Point I + 1 rnnr 1 v r+ 1 uUULLT ~l A 7 * 1 1 A !a i+1 i- — H J Figure 3.10.2.1. Illustration of Single Step Mode 178 3.10.3 Final Level Task Drivers This task driver logic represents the final level of task signals' collection before these task signals are taken to the input of processing hardware through the interface logic. The implementation of this logic is shown in logic Drawings AU0-07-388-01 to AU0-07-388-03. The input to these drivers is in general the output from the task signal collector logic of each arithmetical control sequence. 179 h. AU DRIVER INTERFACE k.l Introduction There is need for a driver interface between the control logic hardware and the processing hardware because of the load requirements and the logic level differences. This section describes briefly the interface for signals that run from control hardware to processing hardware and vice versa. 180 k.2 Control Logic to Processi ng Hardware Driver Interface A large number of control signals generated in the control hardware go to activate the various functions in the processing hardware and each con- trol signal may involve, in general, quite a heavy load on it. Secondly, the output of TTL logic with which control hardware is implemented is different from the level required at the input of DTL logic from which the processing hardware is constructed. Hence a driver interface has been provided to trans- form the logic levels appropriately and also to provide the necessary drive capability. DTL logic card 1018-262-XX provides the necessary drive and the level transformation and acts as the interface logic card. This interface logic is shown in control Drawings AUO-07-^OO-C^ to AU0-0T-U00-12. 181 U.3 Processing Hardvare to Control Logic Driver Interface There is a relatively small number (~50) of signals which originate in the Processing hardware and terminate in the Control logic hardware. The drivers for these signals are not collected and shown on a separate set of drawings as in the case of Control to Processing hardware driver interface. Rather they are shown on the various Processing hardware drawings themselves where the signals originate. Spare drivers left over from the unused sections of Logic cards in Processing hardware are used as interface drivers. These drivers more than meet the current requirements of the load but fail to meet the voltage (level) requirements. To make these drivers compatible with the load, terminating resistors are added to the load. For more detailed informa- tion concerning levels, loading, hardware description and other notations etc., the reader should consult DCL File #872 written by Mr. Paul Krabbe. 182 5.0 CONTROL LOGIC DRAWINGS AND THEIR INDEX This section contains an index of Control Logic drawings which show the logic implementation of various control sequences and sub-sequences discussed earlier. The index shows the drawing number followed by the title of the drawing and the corresponding page number on which the drawing appears. The index is followed by a set of the Control Logic drawings. The Control Logic drawings reflect the latest state of the logic, as it appears at the time of writing of this report. These drawings may undergo some minor changes and modifications due to shortcomings which will become known in the check-out phase. 183 LOGIC DRAWING TITLE Page No NUMBFR 192 193 AUO-C7-212-01 AU EXPGNENT-ARITHNETIC LOGIC BLOCK DIAGRAM 187 AUO-C7-212-02 EUM AND EUU REGISTERS WITH IN/OUT GATING 3.88 AUC-C7-212-03 EXPCNENT UNIT ADDER ± q 9 AUO-C7-212-C4 EUL REGISTER-COUNTER, BITS 1-4 190 AUO-C7-212-05 EUL P EG I ST EP-COUNTER, BITS 5-7 AND CONDITION DETECT LOGIC 191 AUO-07-212-06 EUL LOAC ANC PRFSET LOGIC FOR EUL AUO-C7-212-07 EUL CCNDITICN DETECT AUO-C7-212-08 EUM AND EUU SELECTOR SWITCHFS 19 \± AUO-C7-212-09 TASK SIGNAL CCLLECTCR 195 AUC-07-321-C1 OP COCE AND NUMBER TYPE DECODER 19 £ AUO-C7-?^?-Cl FULOB FIRST WCPD LOAD AND PRANCH 197 AUC-C7-332-0? SEfcLO SECOND WCRD LOAD 19 8 AUC-C7-332-03 PRAIN FRANCH TC APPROPRIATE INSTRUCTION 199 AUO-C7-332-04 TIFCbLOE THIPC AND FORTH WORCS LOAC AND BRANCH 200 AUO-C7-33P-05 EXIT 201 AUO-07-352-01 OPACAS CPERANOS ALIGNMENT CALL S<=T UP 202 AUC-C7-352-C2 ALNLH, ALMQ, UHTLO ALIGN UQ, ALIGN UH UH TO UO 203 AUO-C7-352-C3 CAL SUM CR DIFFERENCE CALCULATION 20U AUO-C7-352-04 NGPMUQ NORMALIZE UO 205 AU0-07-3 c 2-05 SFeiN SFT FLAGS, BHGUS AND STATUS INDICATORS 2 06 AUO-C"7-?'2-C6 XCUT TRANSFER RESULTS TO PROCESSOR 207 AU0-07-352-C7 TASK SIGNAL COLLECTOR "Al» 208 AUO-C7--> C ?-08 TASK SIGNAL COLLECTOR "A2" 209 AUO-07-361-01 REPPOG REDUNDANT FORM PRODUCT GENERATION 2 10 AUC-07-361-02 MPYEND CCNVENTIONAL PRODUCT FORMATION AND STATUS INDICATOR SET UP 211 LOGIC DRAWING NUMRER TITLE 18U Page No, AUP-C7-371-01 AUC-C7-371-C2 AUO-07-371-C3 AUO-07-371-04 AUO-C7-371-05 MJ0-C7- AUO-07- AU0-C7- AU0-C7- AUG-C7- AU0-C7- AUG-C7- AUC-C7- AU0-C7- AUC-07- AUO-C7- AU0-C7- AU0-C7- AU0-C7- AU0-C7- AUO-07- AUO-07- ■371-06 •371-07 ■371-C8 ^71-0<3A ■371-09R ■371-10 ■371-11 371-12 371-13 371-14 371-15 382-01 382-02 : ?82-C2A 382-03 382-04 3P2-05 DIZETSCAL DIVISOR/DIVIDEND ZERO t E sT AND SCALING 212 DIVIDE REDUNDANT QUOTIENT GENERATION 213 DIVIOE AND DEL •DIVIDE 1 AND QUOTIENT ASSIMILATION 21 U ASIM CCNVERSION TO CONVENTIONAL REPRESENTATION 215 DIZETCCM DIVISOR/DIVIDEND ZERO TEST AND 2'S COMPLEMENTATION 2l6 SCALFIXDR DIVISOR SCALING TO GE 1/2 2 17 SCALFIXDR CI VI SOP SCALING TO GE 1/2 218 FORMCAREM- — QUOTIENT AND REMAINDER GENERATION 2 19 CCSPEM REMAINDER'S SIGN CORRECTION QASS QUOTIENT ASSIMILATION PESCALEPEM REMAINDER POST-SCALING RESCALEREM REMAINDER POST-SCALING TASK SIGNAL COLLECTOR "31" TASK SIGNAL COLLECTOR "R2" TASK SIGNAL COLLECTOR "B3" COLNTERS ICC, NPRL8, NDDL8, NDRL1 CVL-FLT CVL FLOATING POINT OPERAND CVL-DEC CVL DECIMAL OPERAND LUQ LEFT ACJUST UQ FL-NOPM-FX FLOATING-NORMAL I ZE-FIX DVR DECIMAL TO BINARY CONVERSION 220 221 222 223 22l+ 225 226 227 228 229 .230' 231 232 DVB ANC CCMPL CECIMAL TO BINARY CONVEPSION2 AND COMPLEMENTATION 233 AIJO-C7-382-06 AUC-C7-382-C7 TASK SIGNAL COLLECTOR "CI" TASK SIGNAL COLLECTOR «C2" 23U 235 LOGIC DRAWING NUMBFR TITLE 185 Page No, AUG— 07-383-01 AUO-C7-384-01 AUO-07-384-02 AUO-C7-384-C3 AUn-C7-384-04 AIJP-C7-384-05 AUC-C7-384-06 AUO-07-388-C1 AUC-C7-388-02 AUO-C7-3P8-C3 AUG— C7-3S0-01 AUC-C7-^90-0? aup-07-^90-C3 MJ0-C7-3 90-04 Aun-C7-3qo-C5 AUO-C7-390-06 AIJP-07-390-C7 AUD-C7-390-C8 AUO07-3S9-01 AU0-C7-4C0-04 AUP-C7-4C0-0 5 41^-07-400-0* AUO-C7-*00-07 CVF-DFFIX CVF DECIMAL AND FIXED POINT OPFPANCS 236 FIXCCAFLOX FX.PT. OPERAND CCNPLEMENTAT ION AND FL. PT. TO FX. PT. CONVERSION 237 GETCEC-CACCREM DECIMAL DIGITS GENERATION- CALCULATE QUOTIENT AND REMAINDER 238 GETCEC-CAGOREV DECIMAL DIGITS GENERATION- CALCULATE OLOTIFNT AND REMAINDER 239 GETCEC-CUCCCV DECIMAL DIGIT GENERATION- QUOTIENT CECREMFNT 2 k0 GETCIG AND SETSIGN DECIMAL DIGITS TO UQ 2U1 TASK SIGNAL COLLECTOR "D" 2U2 TASK CRTVER "Fl" 2^3 TASK CPIVER "F?" 2kk TASK COIVER "« r 3" 2^5 UV,LS PFGISTFP SELECTORS 2k6 UH REGISTER SFLFCTOR 2kj m REGISTER SELFCTCR,SPTUQ330NE,SFTUQ337ERO, SPTLQ47rNE,QBDUQH 2U8 UQ REGISTER SELECTCR 2U9 MODEL CIVISION DIVISOR SELECTORS, SDS GATE SIGNAL GI SELECTORS 250 M SFIFT ARRAY SELECTORS 251 TASK SIGNAL COLLECTOR 252 SDS NEGI SIGNAL SELECTORS f SR • SI GNA 253 CREST-CLEAR RESET, POWER TIJPN-ON ANO SINGLE STEP MQDE LOGIC 25U CCNTRCl-PPCCESSING HARDWARE INTERFACE 255 CCNTROL-PPCCESSING HARDWARE INTERFACE 256 CCNTRCL-PPCCESSING HARDWARE INTERFACE 257 CCNTROL-PPCCESSING HARDWARE INTERFACE 258 LOGIC DRAWING NUMBER TITLE 186 Page No, AUO-C7-4C0-08 AUO-C7-A00-O9 AU0-C7-4C0-11 AUC-C7-400-12 CCNTROL-PROCESSING HARDWARE INTERFACE CCNTRDL-PRCCESSING HARDWARE INTERFACE CCNTPCL-PROCESSING HARDWARE INTERFACE CCNTRCL-PRCCESSINC HARDWARE INTERFACE 259 260 261 262 187 JJVIS IONS DEPARTMENT of COMPUTER SCIENCE Unlvtrdty of Illinois AU EXPONENT- ARITHMETIC LOGIC BLOCK DIAGRAM Browlnn No. AUO - 07" 2 1 2 - 01 18£ 212-09 EU01FF(E) 388-03 LDEUM(w} 212-08 SEUMZERO©- 212-08 EBDEUM(3) 212-08 EUXDEUM ©■ Y).C. EXDEUX ©■ EUDIFF 212-08 SEUMEQM ©■ 352-03 { V J7 212-05 EUL 7 ©■ L&aAL. 4->i-li REVISIONS DEPARTMENT of COMPUTER SCIENCE University of Illinois Approved by Supartadci dwg. card location: C-26 T,TlE AU EXPONENT -ARITHMETIC LOGIC EUM AND EUU REGISTERS WITH IN/OUT GATING Drowing No. AUO-07-212-02 189 212-08 C0MCLR 0- 312-02 EUU 212-02 EUU 212-02 EAYl EUU 7 EAY 7 EUU 6 EAY 6 EUU 5 EAY 5 EUU 4 EAY 4 EUDIFF Al (i) EUA0V 352-01,05; 212-07 ■© EUAUN 352-01,05,212-07 -® ESl 212-C <£> ES 3 "© ES 7 -® ES 6 -® ES 5 -© ES 4 LbuLL. < ,1 1L H VI1IONS DEPARTMENT of COMPUTER SCIENCE University of Illinois 0,.-n b f s z a TG card location: C-26 TITLE AU EXPONENT- ARITHMETIC LOGIC EXPONENT UNIT ADDER D,o.i n „ No. AUO-07-212-03 212-06 PEUL1 ' EUL2 212-04 1 EUL3 . EUL4 EUL5 212-05 i EUL6 EUL7 CPUP ®- 212-05 EUL2 12-04 <{ EUL3 EUL4 EUL5 EUL6 EUL7 CPDWN CEUL1 PEUL2 ©- ®- CEUL2 ©- PEUL3 ®- CEUL3 ©- PEUL4 ©- 212-06 CEUL4 ®- fi B MOOVIO, 3 7400V6. 7400 VI0- 5| 7406VS_ B3. 7420\-£_ C4 /^ 7400\jO - _5] 74O0V§_ 12 SN7474N Al CL A2 A2 SN7474N A5 EULl 212-05 -© EULl 382-01; 212-07 -© EULl — EULl - EUL2 » i © EUL2 r © EUL2 EUL2 212 -04,05 EUL3 212-04,05 * i © EUL3 212-07 ♦— © EUL3 212-02,07 EUL3 212-04,05 EUL4 212-04,05 ■ t © EUL4 212-07 f— © EUL4 212-02,07 EUL4 £12-04,05 No. 530 Cho«g« ordc Approvd by >-i'- 7i REVISIONS ■ DEPARTMENT of COMPUTER SCIENCE University of Illinois LN6 o.td bv Drown by LRS 6 -IS"- 71 5-20-71 CARD location: C-22 All EXPONENT- ARITHMETIC LOGIC EUL REGISTER -COUNTER, BITS 1-4 Shot Draw!., N.. AUO-07-2I2-04_ 191 212-06 PEUL5 212-09 CP 212-09 BY0NE 212-06 CEUL7 iie-OB C9MCLR 212-09 EUCTRDIR ©- 06-\J2_ 7402 EUCTR0V tic EUCTRUN »c EULEZ 212-07 ^SS^- iJmo, D6XJ CPUP 212-04 CPOWN 212-04 t&tiL 4 1171 , ■>. » i visions I DEPARTMENT ol COMPUTER SCIENCE Unlvfi-ilty of Illinois %> 0'.-. b> T G CARD location: C-22 TIU£ AU EXPONENT- ARITMETIC LOGIC EUL REGISTER- COUNTER, BITS 5-7 AND CONDITION DETECT LOGIC ol oro.mo no.AUQ- 07-2 12-05 ■"^dE)^ 212-03 ESj 0- 212-09 SEULALLZER0 ®- &—$£? ^> 212-09 SEULALL0NE ©- 2,2- 03 es 2 ® r^f^y 2 ^T)i J&* 212-03 ES, ©- l^— 3^> 2,2-03 es 4 ® — A^y± — S^y 2,2-03 ES © t ' [d3 J> 2,2-03 ES 6 ® » ? | D3~V* LDESDEUL ®— 1 UJ03\>i 03 _uJ77\jo $E> -jfeyL ^y ■d^> es 7 (^-^ryi—JiT^ 383-01 212-09 SEULE014 ®- $7> ;JE> 4 t M ]7)>i 4—^ D3 V C5 J> cTOlI ~ny* >^oTy — © Dl\>§ ^|D6\> " ®PEUU ~C6~V T^)^ ©CEUL2 -j^T)>s— ^^2 ©mn. [pT)o^ ®CEUL3 6 131 ■^TTy <^y* — ©PEuEf I. ' A ~cTy$ '{°£y ©CEUL4 ~D2y2 ^[d7)c4 ©PEUL4 ilTTVS ^f^V © CEUL5 5«)^ ^7^° @PEUL5 foTV^ ©CEUL6 10 iiy HTTV2 STdTV @PEUL6 _]!} — — J4"cT)> 12 ^D4^ ©CEUL7 z|b7)^ ;5fe>2 — 2j^ — @PEDC7 B E V I S I O N S DEPARTMENT of COMPUTER SCIENCE University of Illinois M^. Drawn by LRS !«pwuon dwo. card position: C-24 T,TLE AU EXPONENT- ARITHMETIC LOGIC EUL LOAD AND PRESET LOGIC FOR EUL Sh**( of Drawing No. AUO-07-212-06 382-03 FLX1T1 212-08 C0MCLR H C4 V n.C. SEUXDEUM 212-09 EUTOi 0- 332-01 VIN2T6 399-01 C0MCLR ©■ 332-02 VIN3T6 n.C. SEULOEUU 352-03 CAL1T6 (8 0SEUMEO14 212-02 0SEUMZER0 212-02 0EUXDEUM 212-02 0EBDEUM 212-02 0EULDEUU 212-02 0EADEUU 212-02 0SEUUZER0 212-02 0C0MCLR 212-3, 8,9, i" Inu. |CK.ng« »i<« (Ltiuiit 5~- 25-- 12 R E V I S I O N S DEPARTMENT of COMPUTER SCIENCE University or Illinois J&fc. Drown t,, T. G. 8-12-71 Supar.cdai d»p. CARD position: C28 T,TLE AU EXPONENT- ARITHMETIC LOGIC EUM AND EUU SELECTOR SWITCHES Sh«.t of Drawing No. AUO-Q7-212-QJL 195 352-07 SEUCTRDIR/A 0H 382-03 FLX4T1 0- 352-07 CEUCTRDIR/A 0- 382-06 CEUCTRDIR/C 0- 352-07 382-06 352-07 382-06 332-02 382-03 352-03 382-01 384-01 SBY0NE/A 0- SBY0NE/C @- CBY0NE/A @- CBY0NE/C @- VIN3T8 @- FLX1T1 0- CAL1T5 0- CVL1T1 (7)- CVD1T1 0f- 212-08 C0MCLR 0- 13 SEUCTRDIR 01 Jo 13 CEUCTRDIR SBYBNE Dljo- 10 CBY0NE ~^Ty SEUDIFF ^T)> 10 SEUMEZ, CLEUMSFF, CEUDIFF & TttJqTV tjig> ri£> T~3]76V T 6JcT )t> T 6jD5j)o 0EUCTRDIR 212-05 0BY0NE 212-05 ■0EUD1FF 212-02 SEUMEZ , CLEUMSFF Qg^ 212 . 08 382-04 383-01 DVB2T1 0- CFD2T1 0- D2~V 10 SEULE014 TigX -0SEULEQ14 212-06 352-05 SFB1T2 0- 361-01 MPY2T1 0- 371-01 DFL2T1 0? ~^y 6 SEULALLZER0 tigy -0SEULALLZER0 212-06 352-05 371-01 SFB1T1 — DFL3T1 0^- ;^r> 6 SEULALLgNE T~?gV- -0SEULALL0NE 212-06 352-03 382-07 332-04 384-01 CAL1DT1 LDESDEUL/C VIN3T1 CV040T1 0(5" M^- Tig> -0LDESDEUL 212-06 352-08 382-06 CP/A 0- Cp£ 0- E> -0CP II ( V I S I O N S I DEPARTMENT of COMPUTER SCIENCE Unlvcrilly of Illinois Droit b, T G CARD position: C-18 TIUE AU EXPONENT- ARITHMETIC LOGIC TASK SIGNAL COLLECTOR Sh..c of Dr,wl„ B No. AUQ-Q7-2 12 -Q9 19 IV-REGISTER 332-01 VINlTiCv)- 11121 *- 130-10 v 6 230-10 V 7 (?} 332-01 VIN2T4©- L£S - 230-10 230-10 332-01 VINlTl(?> (j) ADD 352-01,01,05. (?) CPRA 352-01.03,05 332-02,03 332-04 332-03j 352-06 {l) CVF 332-01,03j 352-06 332-01,03; 371-02, 352-06, 5 71 -09/» 352-01,03,05 332-01,02,03,04 {a) POLY 332-04; 352-05 332-01,02,03,04 37I-02.09A 400-12 (?) OIV B) P0LYC0 332 -01, 03 @ SSIGNAPOS 390-08 (n) ILLD0P 332-03,05 ) SSIGNANEG 390-oa 9JILL0P 332-01 352-06 (S) LFIX 361-01,02,371-15 (7)SFIX 361- 02, 371- IS ®FLT 332-01,01,03.03, 3*«-« 352-04,, »*l-Ol,»«;»TI-0l,l5. ®J3*-05 DEC 3Si-01,03 (7) FIX 332- 01,02,03; 361-01.02 37I-OI, 364 -Oi card location: c-48 PKnUU REVISIONS DEPARTMENT of COMPUTER SCIENCE University of Illinois Appro. .d b r Drown by s.z Ool. 1-11-72. Sup»n«d«» dwg. TIUE AU DECODE CONTROL LOGIC OP CODE AND NUMBER TYPE DECODER Drcwins No. AUQ-Q7- 321 -01 _ 199 321-01 ILLD0P © f-4 ClV 332-02 VIN3A0 © 4 04 J> P0LYC0 ©■ 230-06 PE1 @rx 230-07 PE2 ©yr 230-08 PE3 ©yy 230-09 PE4 ©tr 332-01 VIN2OT10- ^^ - 332-02 VIN30T1 ® — '■^ i 332-04 VIN40T3© l PPC? *■ 33202 C0MCLR ©■ ©VIN3S1A 382-01 -©VIN3S1B 382-02 m)VIN3S8 332-05 ©VIN3S2 383-01 ©VIN3S3 384-01 ©VIN3S4 361-01 ©VIN3S5 371-01 ©VIN3S6 332-04 ©VIN3S7 332-04 ©XB 6 2J0 - l0 ©PERR 332-01,04 NO. 3*9 r, tfaUu ill l l » t VISIONS DEPARTMENT of COMPUTER SCIENCE Unlviriliy of Illinois INIM4 k f D..-» br TO card location: C-60 TITtE AU OPERANDS -LOAD CONTROL LOGIC BRANCH TO APPROPRIATE INSTRUCTION -BRAIN- Sh»t of Drawing No. AUQ- 07~ 332-Q3 332-02 MEN (20> 332-02 C0MCLR V 3 ©■ 332-02 VIN3T1 (u> 332-03 VIN3S6 332-03 VIN3S7 (?> If— (g> 321-01 321-01 ASC 0- MPY 0- DIV ©- 321-01 P0LY 0- 332-03 PERR @- 0VIN4DT3 332-03 jo£>2 VINN5 ■©VIN5T1 400-06 0VIN5T1 212-09 FB2RFB, LDESOEUL 4 VPUH47, LPUH47 ■ LDUH47 ©VIN5T2 400-04 pB^ *y -S B4 Vl0 13 -0 VIN5S2 352-01 7y±- -0 VIN5S3 361-01 vy^ -©VIN5S4 371-01 ~c£p*- -©VIN5SS n.c. ZnflTy -0VIN5S1 332-05 NO. 627 NO 545 I ' K"~>~JTi CKong« ord*' Appro-ad by D l-3t 13 <-"-n » E V I S 10 N S DEPARTMENT of COMPUTER SCIENCE University of Illinois Data 10-15-71 Saii'iidii J-«. card location; C-58 Tine AU OPERANDS -LOAD CONTROL LOGIC THIRD AND FOURTH WORDS LOAD AND BRANCH -TIFOWLOB- Shait Drawing No. AUQ- 07- 332~04 201 '.-02 MEN @ M D2 j£ LR © ^D2^4 332- OZ C0MC 352-03 CAL4A0 371-03 DFLHAB @- 361-02 MPY9S1 352-04 WAITN0RMUQ (?) 332-01 VIN1S1 0- 321- 01 332 03 3 32 ■01 332 ■04 IILD0P (e) VIN3S8 0- VIN2S1 @- 3S2-OI ASC2S1 (l4> 361-01 MPY2A0 361-02 MPY1OA0 363-01 CFD4DT1 384-05 CVO26A0 (0 Wl-14 SETFLAG4I/8 362-07 SETFLAfl4I/C (S> ON CONTROL POINTS G0DELY @ ^J D2 JoJ VIN5S1 -__/ I > ■© EXTN1 0EXT1T1 352-04 NOTE 1 THE TIME DELAY SHOULD BE VERY LARGE TO SIMULATE THE TIME NECESSARY TO LOAD ALL FOUR OPERANDS IN WORST CASE {h) EXTN2 EXT2T1 352-05 EXTN3 EXTN4 SETFLA6A! 352-05 m ua . £_! 6 * »cc" 3S2 -oa MEN ©- TO CONTROL POINTS 321-01 CVD ©- 321-01 CVL ©- 321 01 321-01 399-01 0NLINE ©- 352-08 XOUTAI ffij 321-01 ILL0P ©- 230-10 Vj ©jj- V2 ©, 352-08 C0DELY ©- J4l N _C^aT)o!2 ' ■>> « SUQ47DXT ¥* t*|s ^ : < -SEULOXT -©EULDXT 400-05 )^L^>5 © UOODXT 400-05 -©X0TN1 -®XB t -© XTOES 400-05 ^ ©> SUOL30XT rvL. ^A3>^ © X0TN3 ^> '° Tlg ©XB 3 A3>^ © X0TN4 -©U013DXT 400-05 -® UQ47DXT 400-05 4*3>* ©WfN5 ClRESET ©X0T5A0 399-01 f&t » l VISIONS DEPARTMENT of COMPUTER SCIENCE Unlvcrilty of Illinois Drlw I hy T G 1-17-72 Sue.n.d.. d.g. 20T CARD location: C-46 TIUE AU-REF0TRAN CONTROL LOGIC TRANSFER RESULTS TO PROCESSOR X0UT Sh..l of Drowinfl no.AUO-07-352-06 208. 352-02 UHQ1T1 ©- 352-03 CAL4T1 ©- 352-01 ASC1T3 ®- 352-02 UHQ2T1 ©- TPy- ~oTy- & Tzig> -® SLMDUQ/A 390-04 rig> -© SUHDM/A 390-03 352-02 AUQ1T3 ©- 352-04 NUQ1T4 ®- 352-04 NUQ1T1 (f)- 352-02 AUQ1T2 ©- ZL3H> j^> ^Ty- T l4j 0rVS © SEUCTRDIR/A 212-09 T=gy -© UQDLQ/A 388-01 T sY dTV* ® SLQR4UQ/A 390-04 352-01 ASC1T1 ®- 352-03 CAL3T2 ©- 3^> Tl^osV -© SSR/A 390-07 352-01 ASC1T2 ®- 352-03 CAL3T1 @- & "C|o=>: -© CSR/A 390-07 352-02 AUQ1T4 ©- 352-04 NUQ1T5 ®- ^ry. T_i£>- -© SBY0NE/A 212-09 352-02 AUQ1T5 ®- 352-04 NUQ1T3 @- jJT)£ ti£> 2 - -® CBY0NE/A 212-09 352-02 AUH1T3 ©- 352-04 RD5TT8 ©- TTy T llj oOo^ ® CEUCTRDIR/A 212-09 lnw Chang* ofdar Approved by Do R E V I SIONS 2 No 617 //^Jl^, S-/Q-TL i DEPARTMENT of COMPUTER SCIENCE University of Illinois approved b r D.own b, T. G. Del* 7-29-71 Sup«n*d«i dwg. card location: C-38 titie AU-ASC CONTROL LOGIC TASK SIGNAL COLLECTOR "Al" Shot of Drawing No. AU0"07- 352*07 352-02 UHQ2DT1 ©- 352-03 CAL4DT1 ©- 352-04 NUQ2T1 ©- ~^y Tij 06\t i- C6>2 ® LDUO/A 388-01 352-02 UH01DT1 @- 352-03 CAL1T7 (n>- JT)£ T^X 1 fe> i © LDM/A 388-03 352-02 AU010T1 ©- 352-04 NU010T7 ®- TTy -tSgy -® CP/A 212-09 352-01 ASC2S3 @- 352-05 SF83S1 ©- rjH> ■tqH>° -©XOUTAI 352-06 399-01 C0MCLR (J)^- 4^> -©C0MCLR 352-1,2,3,4,5,6 399-01 MEN ©rjr -0MEN 352-1,2,3,4,5,6 399-01 GBDELY ©TT" -©GflDELY 352-1,2,3,4,5,6 209 No 616 No 394 ^^ tio.1l II V I S I O N s DEPARTMENT of COMPUTER SCIENCE Unlvtriliy of Illinois L G. &xL_ 8-3-71 \*,.,..d.. j.. CARD location: C40 t.tie AU-ASC CONTROL LOGIC TASK SIGNAL COLLECTOR "A2" thtii of erowine No. AU0-07- 352-08 211 361-01 COMCLR 0- [13Ta?VU->CC 1-01 MEN ©- 361-01 MPY5A0 @1 TO CONTROL POINTS 371-15 MPYSTOP 0- m Cfl o o r> m -t X m c o o z r-t ? m 5 * 5 ° ? 1 s 2 p o o 3 o c .. o w X W m m X J> - _, H O 2 1- M K c 5 si 361-01 MPY3T1 0ii!2™5 290-01 UQ65 0^ H A2 \£- 371-04 ASIMWAIT @- 361-01 G0DELY @- 321-01 321-01 FLT @~ FIX 0- 4 LDMEXPREi CI > £ 3C n^ J^L W j^E>^ 211-02 UQ5EZ 07J- 211-02 UQ4EZ ©rs- 211-03 UQ45A3 0n- 211-03 UQO3A0 ©rs- 390-02 UQ03EZ wl — E rHr-T ~K - ^_ ® l -© MPY6T1 38 8- Cl\) 14 . L% iJ HA5> " MEPLATCH 400-06 MPY4AI2 s-\ 0MPY6S1 361-01 ^JA3>£ ©MPYN7 \n~* -0MPY7T1 390- O" 5 A5> ©UQDMR 400-06 ^ ~|a F 13 CY1SFF,CLNEG0,CLNEG1 SNEG8, SNEGl,SM0Yy->, „„ ! — --2 :(jjMPY7T2 390-06,07 ©MPY7T3 390-06,07 HA5>^ ©MPYN8 -0MPY8T1 371-0 -©MPY9S1 332-05 IS ^j«>^ ©MPYN9 -0MPY9T1 388-01 -H -©MPY1OA0 332-05 ^ -0MPYN1O 390-08 SR 0tj — • «1-01 SFIX @- ig)^ 321-01 LFIX 0- -0MPY1OT2 352-05 -©MPY10T1 371-14 ,*\*Um, D t V I S I O N S DEPARTMENT of COMPUTER SCIENCE University of I lllnols Drawn b* TO. i-U-li- 1-9-72 CARD location: E54 title AU _ MPY CONTROL LOGIC CONVENTIONAL PRODUCT FORMATION AND STATUS INDICATOR SET UP MPYEND Sha.l Of Drawing No. ALIO" 07-361-02 2i; 332-03 VIN3S5 ©^ 332-01 VIN5S4 ©^ 321-01 390-05 FIX ©- UOEZ ©- 390-08 SIGNA ©- 332-02 SIGNB ®- 390-05 UHEZ ©- 321-01 FLT (?)- UH9 ©- 371-04 G0DELY @- 371-02 OIVIDEWAIT ®- MEN @- 371-04 C0MCLR ©- -^y "jjIpTV frEN TO CONTROL POINTS (?)DFLN1 0DFL1T1 371-14,15 -©FIXDIV 371-04,05 SEULALLaNE,sav,SUQ47gNE,SUQO5Wt0 3Fi:gTi 212 . 09)371 .| ■0 DFL3DT1 371-13 SLHLIUH,SLOLIUO,UH0LH,UQ0LO -©DFLN4 0FL4T1 371-13 -0DFLN5 -®DFL3T1 371-13 3E ^ ^ l2 © DFLN6 0DFL6T1 371-13,15 -© DFL7A0 371-03 W -©DFLN7 :^-py -0DFL7T1 371-02 ! : ; <#&■ 8-IO. 7i Ri VIS IONS DEPARTMENT of COMPUTER SCIENCE University of Illinois *~y Drown by T G. 1-4-72 CARD location: H-50 t| tle All DIVISION (Fl.Pt.) CONTROL LOGIC DIVISOR/DIVIDEND ZERO TEST AND SCALING - OIZETSCAL- SH..I of D,.win 9 N,. AUO-07-371-01 213 371-01 DFL7T1 0- 371-08 DFX21T1 (7} CALLDIVIDE 14 :ALLDIvrDE 15 G0DELY 0- i^> div 0- wl — ^7y CVD ©- 371-03 DIVID1OA0 0- 371-15 ICCEQZ 0- •'ihsWA-i, > M f> o o > S 5 'Ih^vv-L iH 01 J>l ,^oTy :: — a^r> A j> ©DIVN1 CY4SFF,CY3SFF,CY2SFF,CY1SFF,CLNEG234 CLNEG1,CLG1234,CUM0X1,CUSDS1 2 ' — ^-0DIV1T1 371-12,388-02, 390-05,06 -0MDDINT 400-12 ©DIVN2 Z4DLM ,T40"LS,SICCCNTDN ^\ DIV -, T . -0DRTEN 400-12 JLL |tt>2 ©01^3 SQS0UQH.SLSL8US ,SLML8UM,SLHL8UH ' '' SL0lBUQ,SUMDx1,SG1G2G3G4 1 SUSDS ^-©DIV3T1 371-12,390-01,03,05 > -0D1VIDEWAIT 371-01,08 HA^>^ 01 VN4 371-H MEN @- >7MI C0MCLR 0- II ** ^f^y r*'-' CI i>i KV)D1V4DT1 400-12 A4>^ DIVN5 -0DIV5T1 390-05 A^ LDQMS34 ©DIV 5D T1 400 -,2 -HA4>^ DIVN6 52S2M2 ©DIV6TI 390-05 A5^ " LDQMS56 ©DIV6DT1 400- ,2 22±± 0DIVID7AO 371-03 HA4>^ © DIVN7 1222*2 0DIV7TI 390-05 ^J9)DIV7DT1 400-12 \\*LL i i" ■•2 » C VISIONS 1 DEPARTMENT of COMPUTER SCIENCE University of Illinois 0.a-n l>> T G caho location: H-38 title AU DIVISION CONTROL LOGIC REDUNDANT QUOTIENT GENERATION - DIVIDE- She«l of Dr=win 9 No. AUO -07-37 1-Q2 371-02 DIVID7A0 (i?) 3 71-11 G0DELY (|T> DIVJD8A1 371-01 DFL7A0 @- 371-C5 ASIMWAIT (J5> 371-n C0MCLR (7) (?) DIVN8 D4>2 © DIVN9 CWTICCDN,Z4DLM,T4DLS,LDUH Q^Ml 371-12,13 ©DIVNIO !S ©DFLN8 sUHDUS,srjQDUM^ )5FriT - 1 371 . 14 ■©DFLN9 SNEGi ^EG0,CYls FF_ < 7 )M:iT - 1 ,„.„ @ H05V+EN <7)DFLN10 !S— en] -JSg)o!ipccJ TO CONTROL POINTS 371-03 DFL10T1 © 371-05 DFX3T1 © 371-09A DFX27T1 © 371-08 DFX24T1 © 382-05 DVB8T2 ©T«- 371-09B DFX3271 © 361-02 MPY8T1 @— ©- ""^VroCALLASIM iTcTV £ "h^W 399-01 C0MCLR ©7^ 371-05 DFX5T1 ©-^ 371-01 FIXDIV © 390-02 UQ03EZ © 390-05 UHEZ © 371-04 GOOELY © 390-08 SIGNA © )a dgy -©ASIMWAIT 361-02,371-5, w 94,98 HC2>2 ® ASMN1 CY3SFF,CY2SFF,CLNEG234,SG1CLG2G3G4, SPDY4,SUSDS1,SUMDX1 ©ASM1T1 371-12,390-05,06 HC2>^ © ASMN2 2^ ©ASM2T1 371-12 -©C0MCLR 371-1,4,9A,9B,10,15 FIXEND -©DFX6A0 371-14 | C > >5 ® DFXN6 ^rif(^)^ijir)>2 ^°^ ©0FX5T2 371-14 LDUO -©DFX6DT1 371-13 SBV.SIGNAOSR -©DFX6T1 371-14, -©DFX6T3 371-14 SUO33ZER0,SUO47 WE @ p F ^ J90 . 03 SUQ » eN£ ©DFX6T4 390-03 399-01 MEN ©, 4_°f> 399-01 G0DELY ©nr -©MEN 371-1,4,94,98,10 -©G0DELY M-IA.lArfBttO NO. 342 NO 5 35 REVISIONS r-u-n 3 30-7X II DEPARTMENT of COMPUTER SCIENCE University of Illinois ••Id k. Dr«w« by T G Sup*n*d«i dwg. CARD LOCATION: H52 "UEAU DIVISION (FL.PT) CONTROL LOGIC CONVERSION TO CONVENTIONAL REPRESENTATION ASIM Shot of Drowlng No. AU0~07- 37 1~04 3 71-11 COMCLR 0- 371-M -MEN (0 371-10 DFX34T1 211-02 U014EZ 371-11 U058EZ 211-01 UH14EZ @^T7 211-01 UH58EZ 371-05 DFX5A0 371-11 UQ912EZ 0- 371-05 UQ1M6EZ 211-01 UH912EZ 0- 211-01 UH1M6EZ 37111 GODELY 217 0NDRR8 371-10 0DFXN7 sI5r8U5 , sIhr85h q^^ 371 . 14 , 390 . , 0DFX7T2 371-13 0DFX7T3 371-13 ■0DFXN8 0DFX8T1 371-13 0DFX8T2 371-13 0DFXN9 0DFX9T1 371-12,15 0DFX9A0 371-07 0UO916EZ 371-07, 384-03 0UH916EZ 371-07, 0DFXNIO 0DFX1OT1 371-12 0DFX1OT2 371-15 0DFXN11 sJ5 rjuQ,SN55L aup l ( ^ nFxnT| STt . 12ll5 11 JA6> if ©DFXN12 CNTICC0N 0DFX12T1 371-12 0DFX12T2 371-15 » t VISIONS II DEPARTMENT of COMPUTER SCIENCE University of Illinois — _ Drown by T G 1-18-72 S*| l.i 0.O. CARD location: H-28 titleau DIVISION (FL.PT.) CONTROL LOGIC DIVISOR SCALING TO >l/2 SCALFIXDR Sf...l of D,owin B No. AU0"07-371-06 371-06 371-06 211-01 211-01 371 12 JN @ £] D5V2 ►en' COMCLR 0- CLNDRL4 (9} U0916EZ 0- TO CONTROL POINTS ®DFXN13 5LHL4UH,SLQL4UQ Q DFX13T1 390 _ 02|04 ■0DFX13T2 371-13 ■©DFXN14 ■0NDRL4 (d)DFXN15 {m)DFX15T1 371-13,1 ■©DFX14T1 371-13 371-11 G0DELY ©■ 382-02S LU01T2 @- 382-02A LU02T1 ©- (e)DFXN16 0OFX16T1 371-15 ^ ©DFXN17 SICCCNTPUP QppxiTri 371-12 ^r^yrjTD^ io cnticcup Q DFX17DTl 371 . 12 No.629 NO. 599 No 582 /-30-73 3-3n71 J-Jo-7^ REVIS I O N S I DEPARTMENT of COMPUTER SCIENCE University of Illinois T. G. CARD location: H34 TmE AU DIVISION (FL.PT.) CONTROL LOG K DIVISOR SCALING TO > 1/2 SCALFIXDR Drawing No. AUQ-Q7- 371' 07_ 219 371-07 DFX17A0 (g)£22M2AREM 371-11 MEN @ M A5jC>2 «-EN 371-11 C0MCLR M A5\> 2 » » CC 384-03 CVD16T1 (ay 371-09A RETURNCVD 0- 371-15 ICCGTZ ©• 371-02 OIVIDEWAIT ©■ 37i-u g25ely ©■ 371-05 ASIMWAIT (a) ■0DFXN18 (i)DFX18Tl 371-05,14 ©DFX18T2 371-14 - 3 71-04 GODELY (g) ^- [dT^ 1 g i — E^ o| >] ^ -©DFXN28 SUHOUS, SUQDUM, SLMDUQ , CLMSFF^-n — ' ^^ ' (JJDFX28T1 371-14,390-03 LDUS, LDUM.LOM ■©DFX28DT1 371-13 9^ CLNEG0,LOUQ -©DFXN29 ■©DFX29T1 371-13,390-07 ^ -©DFXN30 - t l[ osy -©DFX30T2 390-06 4gy -0DFX3OT1 390-03 £>= -0DFXN31 -©DFX31T1 390-08 £ '■&* RESCALEREM ■©DFX32A0 371-10 ^ -©0FXN32 i2l C2 -©DFX32T1 371-04 11V I S I O N S ^1 DEPARTMENT of COMPUTER SCIENCE University of Illinois L G 11-22-71 Sup«>i*4*» dwfl. card location: H-56 " nE AU DIVISION(FxPt) CONTROL LOGIC quotient assimilation - QASS- Sh..t of Drawing No. AUO - 07- 371- 09B 222 371-098 DFX32A0 Qt 371-15 ICCGTZ © 371-15 NDRL8EZ © 371-06 NDRR8 © RESCALEREM 371-04 G0DELY © 371-04 C0MCLR 0- p45>E> ©DFXN33 ©DFX33T1 371-15 Bl>2 © DFXN34 5Di5 ^ -QpFXMTi 371-, ©DFX34T2 371-15 b£>^ ©DFXN35 ;LQR8UQ ' SINJECTS1GN ©DFX35tT 371-14 \ 2 LOUQ /^\ C6 p ©DFX35DT1 371- JB^ 12 © DFXN36 CNTN0RL8DN @ofX36T1 371-15 ■0DFX37AO 371-11 p£>^ ©DFXN37 ^QLSUQ ©QFX37T1 371-12 ©DFX35T2 371-13 men © 5_r C eT\ > ±_»- E NJ P01 REV I S I O N S DEPARTMENT of COMPUTER SCIENCE University of Illinois ipprovad by Supanadai d« CARD LOCATION H-54 title AU DIVISION (Fx.Pt.) CONTROL LOGIC REMAINDER POST-SCALING -RESCALEREM- Sheet of D, win 9 No. AUO-07-37i-10_ 223 390-08 SIGNA (?) 371-10 DFX35T1 ©■ 371-10 DFX37A0 Qy 371-07 NDRL4 (TV 371-15 N0RL1EZ (7}~ 211-02 U058EZ ©ft 211 02 UQ912EZ 0^ 3'1-n G0DELY ©■ J'l-ll C0MCL 599-01 C0MCLR 0^: J99-01 MEN ©rar 3»9-01 GODELY @t; SN0RL10N SL0H1UQ03 /~\ ' °'-' J "'- uw " J (l)DFX39T1 371-15,390-03,04 l— {J3)C0MCLR 371 2,3,5,6,7,8,11 371-2,3,5,6,7,8,11 (|3)G0DELY 371-2,3,5,6,7,8,11 No 6 15 No 600 '' 1 mi/n /J* 71 JJVIS IONS I DEPARTMENT ol COMPUTER SCIENCE University ol Illinois __ 1-26-71 CARD location: H32 T,ue AU - DIVISION (FL.PT) CONTROL LOGIC REMAINDER POST-SCALING RESCALEREM Sh.al ol Orowin. No.AUO-07-371-11 221 371-02 371-03 371-05 371-08 371- 09 A DIV1T1 0- DFL9T1 @- DFX2T1 0- DFX23T1 0- DFX25T20- 371-04 ASM1T1 0- 371-02 DIV3T1 0- 371-09A DFX26T1 0- 371-06 371- 10 371-07 361-01 371-02 371-03 371-06 371-06 371-07 384-03 226-02 DFX11T1 0- DFX37T10- 371-06 DFX9T1 0- OFX17T10- MPY3T1 0- DIV2T1 0- DIV9T1 0- 371-04 ASM2T1 @- 0FX12T1 ©- DFX1OT10- DFX17DT1©- CVD13710- UH9 0H; Hig>^_ 01J>- l^Ty. Try 12 DSjO^ l*y j^y Try T7y Try T?y Tzya. TTy Tiy TTTgV -0 CY1SFF/B 390-06 r-qg>^ CY2SFF/B.CY3SFF/B 0DIVTD1 -n5g> : Tigy TZiE> I SUSDS1/B.SUMDX1/B rrgy rrg)^- tig> T-fgV tjgy r^y TzSj^y ■r-f^y t^x- 0DIVTD2 -0SNEG0/B -0SNEG1/8 390-06 -0CLNEG1/B 390-07 -0CLNEG234/B 390-07 390-07 -0SLQL8UQ/B 390-04 -0SLHL8UH/B 390-02 -0SICCCNTUP/B 371.-15 -0T4DL5/B 388-02 -0Z4DLM/B 388-02 -0CNTICCON/B 371-15 -0CNTICCUP/B 371-15 -0SICCCNTDN/B 371-15 -0UH9 371-01,07 P to I WX 3-3Q.72 REVISIONS DEPARTMENT of COMPUTER SCIENCE University of I llinols &L. Drown by T. G. 11- 1- 71 Sup*r>*d*i d- CARD location: H44 T,TLE AU DIVISION (FxPt) CONTROL LOGIC TASK SIGNAL COLLECTOR "Bl" Drawing No. AUO -Q7~ 37 1-12 . 225 371-01 371-03 371-04 371-06 371-07 371-08 371-096 DFL3DT1 0- DFL11DT10- DFX6DT1 ©- DFX8T2 0- DFX14T1 0- DFX20DT1 ©- DFX29T1 0- 371-10 DFX35DT1 0- 371-11 DFX38DT1 0- 371-03 DIV9T10- 371-01 371-05 371-06 DFL5T1 0- 0FX4T1 @- DFX8T1 @- 371-09B DFX28DT1 0- 371-01 DFL6T1 0- 371-08 DFX18DT1 0- 371-03 DIV10T1 0- 371-05 DFX2T1 0- 371-08 DFX18DT2 0- 371-03 DFX1DT10- 371- 01 0FL4T1 0- 371-02 DIV4T1 0- 371-06 DFX7T2 0- 371-07 DFX13T2 0- 371-06 DFX7T30- 371- 10 DFX35T2 0- 371-u DFX38T2 0- 371-07 DFX13T1 0- l[E> ]^ Try 399.01 ClR1BTi0-^ L[77y ^?y i> -cif^y jy ]e> E>* -jgy Ti£T> rn^y T nj liP)^ nig>± Tlgy -0LDUO/B 388-C -0LDUH/B 388-01 -0LOM/B -0LDUM/B 388-02 -0LDUS/B 383-02 -0UHDLH/B 388-01 -0UODLO/B 388-01 T^T o?)o l!i 5LML1W . SL9 L1 WP 0DIVTD3 Nil i, Ml i-.-ii >" 71 IIVISIONi m £~g DEPARTMENT of COMPUTER SCIENCE University of Illinois V" O-.-r. by T G CARD location: H-46 T,TlE AU DIVISION (Fx.Pt.) CONTROL LOGIC TASK SIGNAL COLLECTOR "B2" Drowioa N,. AUO-07- 371-13 371-03 DFL8T1 0- 371-08 DFX19T1 0- 371-09B DFX28T1 0- 371-01 DFL1T1 0- 371-08 DFX18T2 ©- 371-08 DFX18T1 ©- 371-03 0FL11T1 0- 371-11 DFX40T1 0- 371-05 DFX2T1 @- 371-05 DFX1T1 0- 371-04 DFX5T2 @- 371-08 DFX20T1 ®- 371-05 DFX5T1 ©- 371-10 DFX35T1 ©- 371-06 DFX7T1 @- 371-05 DFX5DT1 ®- 371-11 DFX40DT1 ®- !- ±!E> i^y OAJP* l£y j^y ~E> Tdg> -Hgy Tn§™y ■Hlgy r^BX T-JTgV -rig> Ti£y 21 -0SUHDUS/B 390-01 -0SUQDUM/B 390-01 -0SUHDM/B 390-03 -0SLMDUO/B 390-04 -0CLUSSFF/B 390-01 -0CLUOSFF/B 390-04 T mT tjTV^ H a>^ © C LU065 -0SLOR8UO/B 390-04 -0LDUQ47/B 388-01 371-01 DFL3T1 @- 371-04 DFX6T1 ©- 361-02 MPY10T1 0- ^T)^ tnqgy -0S0V/B 371-01 DFL2A0 0- 371-11 DFX4OA0 0- 371-04 DFX6AC 0- ^Ty ri£y ; -0SETFLAGAI/B 352-05 371-01 DFL1T3 0- 371-04 DFX6T3 0- ' /OudL l^y ■3-30-72 REVISION S r-qgv DEPARTMENT of COMPUTER SCIENCE University of Illinois Drown by T. G 11-3-71 Suptnadai dwg. -0CSR/B 390-07 CARD location: H-40 T,TLE AU DIVISION (Fx.Pt.) CONTROL LOGIC TASK SIGNAL COLLECTOR "B3" Drowinfl N.. AU0- 07- 371-11 332-03 VIN3S1A 0- JA4>^ ® CVLN1 SBJg2,CEUMFF^^g^^ n - i 212 _ 212-0? EULGT8 (3) 212-07 EULGT21 212-04 EUL1 0- 390-05 UQ33 (je) 390-08 SIGNA (ra> 390-08 FLN0FXWAIT®- 382-02 G0DELY (jT) 382- 02 C0MCLR ©■ MEN (20> ®CVL1DT1 382-07 a -n REVISION S II DEPARTMENT of COMPUTER SCIENCE University of Illinois Drawn by T, G. Sup.r.fld.i dwa. card location: E-2B title AU-CVL CONTROL LOGIC FLOATING POINT OPERAND CVL FLT Sheet of Drawing No. AUO -07~382-01 229 382-02 MEN ©- 362-02 C0MCLR 0- TO CONTROL POINTS 332-03 VIN3S1B ©^ 382-02 G0DELY (£j)-- 382-04 DVBWAIT 0- 211-02 UQ03EZ (gh 382-01 CVL5DT1 @- 39901 C0MCLR 0r; 390-08 SIGNA ©- 9-01 MEN 0h 382-0S C0MPLWAIT ©- £ £cT)* k^y 1 ^ cTV a || t 'Ir^WH SI J?' J^ B6>2 0CVLN8 10 CALLDV8 -0CVL8T1 382-04 i HE X -0CVLN9 -0CVL9T1 382-07 -(?)C0MCLR 382-1,2,3,4,5,24 -©CVLN10 ' USSFF . SNEOO ■0CVL1OT1 382-07, 390- lBUs -0CVL1ODT1 382-06 -0MEN 382-l,2,3,4,5,2A ^y 2 ©CVLN11 ;yp -©CVL11T1 382- -®CVLUS1 382-02A 399-01 G0DELY 0TJC- '' '■"■ ■'■■■■ -Jo 7J II VISIONS J2)4 DEPARTMENT of COMPUTER SCIENCE Unlvtrslty of Illinois T G -<0G0OELY 382-1, 2, 3, 4, 5,2« CARD location: E24 title AU _ C vl CONTROL LOGIC DECIMAL OPERAND CVL DEC Shoal of Drowlno No. AUO - Q 7~ 382~ 02 23- 362-02 C0MCLR ©- 382-02 £7=7; /rp. cvLnsi © LuQifti M | ^r)> 382-02 G0DELY (fi) 371-15 ICCE04 ©■ 212-07 0EXPE1 ©■ 212-07 DEXPEMl FLX4DT1 382-06 382-06 »*fitdti d«g CARD location: E-18 titie AU-CVL CONTROL LOGIC FLOATING -NORMALIZE - FIX - FL-N0RM-FX - Sktii of cowl,., no. AUO- 07-382-03 382-02 C0MCLR 0- 382-02 MEN @- 381-05 CLDVBWAIT 0- 382-02 CVL8T1 @- 383-01 CFDiTi 211-02 U017EZ 0- ^T)o±l^ 371-u UQ58EZ @- 371-n UQ912EZ 382-05 OVB9A0 (J9> 3 82-02 G0DELY 0DVBWAIT 382-02,383-01 0DVBN1 0DVBN2 C§YgNE,CEUCTRDm,gEULEql4 _ QdVBItI 212-09,382-06 0dvbn3 0DVB3T1 382-06 0DVB3T2 382-06 SBYONE ^• Zm ©DVB3DTT 382-06 I> '° §U5U5U5 ©DVB3T3 382-06 0DVBN4 0DVB4T1 390-03 0DVB4DT1 382-07 0DVBN5 CLUSSFF,CLUMSFF , SUQ912R52UM 0OVB5T1 382-07, 390-C 0DVB5DT1 382-06,07 DVB6DT1 382-05 0DVBN6 0DVB6T1 388-02, 390-05, 06,08,01 D6 V l OiSML5y3,Cy2SFF,CYlSFF,SMLlY4,0 5ggg?i 3 __• CUQ912R52UM,SUSDS1,SUMDX1, v -- / CLNEG1 ,CLNEG3, SNEG4.SNEG2 , CLNEGO No 610 P A,UuJ~i- ■lf> Ti RJVI S IONS 1 DEPARTMENT of COMPUTER SCIENCE University of Illinois M^ 12-3-71 CARD LOCATION E-22 TITLE AU-CVL CONTROL LOGIC DECIMAL TO BINARY CONVERSION - DVB- Sti.et of Drawino No. AU0"07- 382"04 233 2-04 DVB6DT1 0. L(K G0DELY © ^JoT^ 105 ASIMWAIT0 2-07 EULEZ 0- S2-02 CVLliTl 3301 CFX3T3 CV03Ti 384-02 MEN C0MCLR 382-02 © 1 ]«> r\*/*U. 'if 71 « E VISIONS I DEPARTMENT of COMPUTER SCIENCE University of Illinois T. G Swp.M.tf.. d-g title AU _ CVL CONTROL LOGIC DECIMAL TO BINARY CONVERSION 8 COMPLEMENTATION DVB AND COMPL Sh..l of Drawing No. AUO" 07" 382"05 23 382-04 DV86T1 0- 382-05 DVB7DT3 0- 382-05 DVB7DT1 0- 382-03 FLX4T2 0- 382-04 DVB3T3 ©- 382-02A LU01T2 (0- 382-04 DVB2T1 0- 382-05 DVB7T1 0- 382-03 FLX2T1 0- 382-04 DVB3T2 0- 382-03 FLX5T1 0- 382-05 DVB9T1 0- 382-04 0VB3T1 0- 382-03 FLX4T3 0- 382-02A LU02T1 (w)- 382-03 FLX4DT1 0- 382-04 DVB3DT1 0- 382-01 CVL4DT1 0- 382-03 FLX4DT2 ®- 382-05 DVB10DT1 0- 382-024 LUQ3T1 0- 382-04 DVB5DT1 0- 382-02 CVL10DT1 0- J Pg>^ l*y l*y ]^y ■ij>* l^y ~]*y ~z3Ey^ l^y- ~m)£- ■jlPy ^y ^y ;g«>" IS) " ~^y^ \ Jy>$y > I CLNEG1/C r^gy II I D5 T kY dTV 1 r^Tgv r-fjgy- tnrgy D3 T^g> -0CVLTD1 6l C2 -0 CLNEG0/C 390-07 H0SLQL8UO/C 390-04 -0CEUCTRDIR/C 212-09 -0CBY0NE/C 212-09 -0SBY0NE/C 212-09 -0SLQL4UQ/C 390-04 -0UODLO/C 388-01 -0CP/C Ha^ © LDUQ/C ~ r~r\ ~czy£ — ^j^ 4 © ldus/c §3? jIL !^L /-3o 73 REV I S I O N S I DEPARTMENT of COMPUTER SCIENCE University of Illinois fc Drown by T. G. 11-5-71 card location: E-20 T,TLE AU - CVL CONTROL LOGIC TASK SIGNAL COLLECTOR "Cl" Sheet of Drowino No. AUO" 07" 382~06 235 382-04 DVB5DT1 0- 382-05 DVB7DT2 ©- " 3 J DS^O-i | C > >? ©LDUM/C 388-02 332-01 CVL1DT1 0- 382-03 FLX1DT1 @- j^y T s) DfT^O 2 H$^ ©LDEUM/C 382-01 CVL4A0 ©- 382-024 LUQ3S1 @- J^ye- Tigy -©SETFLAGAI/C 332-05 382-01 CVL3T1 ©- 382-02 CVL9T1 @- Ht> rigy -<|)S0V/C 352- 382-02 CVL10T1 ©- 382-04 DVB5T1 ©- E> "tzuj^y- -©CLUSSFF/C 390-01 382-04 DVB4DT1 @- 382-05 0VB9DT1 ®- E> T^joTV ^jc6>S ©ldmTc 382-01 CVLZTi @- 582-03 FLX2DT1 @- 3«> rrrfgy -©LDESDEUL/C 212-09 L&JtL its-ii ft e visions DEPARTMENT o( COMPUTER SCIENCE University or Illinois o.o.n b, T G M± I CARD location: E-26 title AU . CVL CONTROL LOGIC TASK SIGNAL COLLECTOR "C2" Sh..l of Drawing No. AUO~ 07- 382-Q1 332-03 VIN3S2 (?) 361-01 382-04 G0DELY @- DVBWAIT (3) 352-04 WAITN0RMUQ0- VTN2S2 © BEXCVFFIX 290-01 UQ9 ($} 382-05 C0MPLWAIT Q} 361-01 MEN @) 361-01 C0MCLR ■0 CFD4D "T1 352-05 ■©CFX1T1 388-01 <(5) CFX1T1 212-06, 390-04 ■0CFX1DT1 388-0 ■©CFX2T1 390-01,07,08 ?^— *) B2 ^ 212-07 DEXPGTZ 0- 399-01 C0MCLR ©■ 21207 EULGT26 0- MEN 399-01 G0DELY 0tt 384-01 G0DELY 362-03 FLN0FXWAIT <»" 01 C0MCLR 584 01 MEN @- 0CVDN1 0CVD1T1 212-09,390- 0CVD1DT1 388-03,390- 0CVD1A0 384-02 -0CVDN4 0CVD4DT1 212-09 0C0MCLR 384-1,2,3,4,5 0CVON5 0CVD5T1 384-C 0MEN 384-1,2,3,4,5 0CVD6A0 384 0CVDN6 0CVD6T1 384-06 0CVD6DT1 384-06 0G0DELY 384 1,2,3,4,5 0CVD7A0 384-02 ^^ ©C -foTy^ ^cALLRNar* ©cvDTTi 332-03 '■&— NO 6 34 hli NO 60 3 * t VISIONS I DEPARTMENT of COMPUTER SCIENCE Unl vcrjlty of Illinois 'T' D.own by T G 12-20-71 CARD LOCATION E60 title AU - CVD CONTROL LOGIC Fx Pt OPERAND COMPLEMENTATION AND Fl Pt -t-Fx Pt -FIXOCAFLOX- Shaat >f Drowing No. AUO - 07- 384'Ql 390-05 U033 321-01 FIX 0- 384-01 CVD1A0 0- CLUSSFF,SUQ33DUS33. CLNEG03.SNEG047 384-01 CVD7A0 0- 382-05 COMPLWAIT0 384-04 CVD22A0 290-01 U065 390-05 UQEZ JA3>2 CVDN3 CUJQ65 - SKCM7 (M)CVD§Tl 371-15 -©CVD8DT1 371-15 GETDIG /s ■0CVD8A01 384-05 384-01 G0DELY MEN 0CVDN2 0CVD2T1 371-05,390-01, 0CVD2DT1 384-06 0CVD3T1 382-05 0CVDN8 0CVDN1O 0CVD1OT1 384-06 0CVD1OA0 384-06 CVD11A0 384-03 0CVD9A0 384-03 0CVD11T1 384-06,390- I N * " C0MCLR y AlJoS-»cc " ° P.r^U. 3->t>- 72 REV) SIONS DEPARTMENT of COMPUTER SCIENCE University of Illinois QU- Drawn br T.G. 12-10-71 S uo ..,.d., dw CARD LOCATION E-56 title AU-CVD CONTROL LOGIC DECIMAL DIGITS GENERATION - CALCULATE QUOTIENT S REMAINDER -GETDEC-CAQOREM- Sheet of Drowino No. AU0"0 7" 3842 239 384-02 CVD11A0 0- 371-06 U0916EZ (7) 384-02 CVD9A0 ©■ 384-01 G0DELY ©■ 371-08 CVOOIVWAIT0- 384-01 C0MCLR 0- 384-01 MEN ©■ |b>^ © CVDN12 -0CVD12T1 384-06 -0CVD12DT1 384-06 ffll^ © C VDN13 SICCCNTON,SLHL8UH,S 1 i3U»UQ Q^ 5i5ri 371 . 12 , 390 . 2 ,04 4joT)o ' 1 ^OLO . UHOLM @cWl3f2 388- Bl^ ©CVDN14 ™ TlE ^ @ CVDi4Ti 371-15 i[j^^g)M||0 CVD13DTl J81>^ ©CVDN15 1 ' - '■ '" ' -"^"- QcvbTstI '•' ' T n:v /C^vttt {T)CVD16A0 384-04 *|ei>* ©< -©CVD16T1 371" DC VISIONS DEPARTMENT of COMPUTER SCIENCE University ol Illinois 12- 7- 71 '.,,......!.. d.g CARD LOCATION. E-56 Iim AU-CVD CONTROL LOGIC DECIMAL DIGITS GENERATION - CALCULATE QUOTIENT & REMAINDER -GETDEC - CAQOREM - Shi orow,n 9 no. AUO- 07- 384-03 384-03 CVD16A0 02 371-09A NEGR ©- 364-01 G0DELY 0- 384-01 C0MCLR 0- 384-01 MEN 0- '{E> ? oTyz- CD || U3 ■■hr^ CD II ID CD V _* UJ / I 1 I OJ ?'■ -"hrv^ co it £ CVDN19 $>• -©CVDN20 SLM912DM912 -0CVD2OT1 390-03 -^A3>^ ©CVDN21 '^■'^ ©CVDZlTi 384-06,388- LDUH, LDUO -0CVD21DT1 384-06 NEXT01V -©CVD22A3 384- ^ !5|7isJ4 4g> -©CVDN22 151 D4 12] D4 SUHDUS.SUQDUM ® cvSSStZ 390-01 ^ ^UN»,^S © CVD22DT1 384-06,368-02 NO. 539 Char> 9 « o.d. r/W A Appfovd by REVISIONS io -7j ■ DEPARTMENT of COMPUTER SCIENCE University of Illinois L. G. A»,r<>.«d by €»1 Drawn b)r T. G. 12-22-71 CARD LOCATION: E-64 title AU-CVD CONTROL LOGIC DECIMAL DIGIT GENERATION - QUOTIENT DECREMENT GETDEC-OUODCM Drawing No. AUO -Q7- 384-Qj 2lu 384-02 CVD8A01 0- 394-01 GODELY 384-06 SETSIGN ©■ CVDN23 0CVD23T1 384- 384-01 COMCLR 0- 584-01 MEN © HdTV^ — » C N ^DZ^ ©CVDN24 ^°^ -©CVD24T1 384-06 0CVD24DT1 384-06 ©CVDN25 0CVD25T1 384- -0CVD26A0 332-05 D2>^ © CVDN26 P2>^ © CVD26T l 400-05 TO CONTROL POINTS Chsnga ..4. » e v isions &m DEPARTMENT of COMPUTER SCIENC ■-.9 University of Illinois L G T. G 1 -21-72 card location: E-66 AU-CVD CONTROL LOGIC DECIMAL DIGITS TO UQ GETDIG AND SETSIGN Shad of Drawing No. AUO - 07" 384 "05 384-02 CVD11T1 0- 384-01 CVD18T1 0- 384-05 CVD23T1 0- 384-01 CVD6T1 0- 384-05 CVD25T1 0- IJm)^ V 14 C6 JO— ■ 3 ' i^y IS 10 C Y2SFF.CY3SFF, CLNEG0, CLNEG1 -0CVDTD1 390-06,07 Zk^y 6 CU MD Xl,CUS D Sl,CL e i234 |S MDY4,CYlSFF Q CVDTD2 388-02 ;39 . 05 ,, ri£r> Ti£> ti£>^ -0CLUQSFF/D 390-04 -©CLNEG234/D 390-07 -0SLMDUO/D 390-04 384-02 CVD2DT1 0- 384-04 CVD22DT1 0- rigy -0LDUS/D 388-02 384-01 CV05T1 0- 384-02 CVD10T1 0- TF^D4V -® S0V/D 352- 384-01 CVD6A0 0- 384-02 CVD1OA0 0- E>" ■t±g> -0 SETSIGN 384-05 384-03 CVD12DT1 0- 384-04 CVD18DT1 0- 5> tigy -0 LDM/D 388-03 384-03 CVD12T1 0- 384-04 CVD21T1 0- 384-05 CV024T1 0- 384-01 CVD6DT1 0- 384-03 CV013DT1 0- 384-04 CVD21DT1 0- 384-05 CVD24DT1 0- i!D* , 1 *IE> ^ry Tig> T^ypTV Ti&y -0Z4DLM/D 388-02 -0LDUO/D 388-01 -0LDUH/D 388-01 Appro**d by ievi S I O N S I DEPARTMENT of COMPUTER SCIENCE University of Illinois <&L Drown by T. G, 11-10-71 Sup«n«d«» d.j. card location: E-62 TITLE AU-CVD CONTROL LOGIC TASK SIGNAL COLLECTOR "D" Sh»»t of Drawing No. AUQ-Q7- 384-Q6 243 332 352 361- 371- 361- 382 383 384 VINZT10 ©— LOUO/A (D^j- mpy26tT ©— LOUQ/B ® MPY9T1 (?) LOUO/C 0-j- CFX1DT1 LOUO/O ]»> -0LDUQ 332 361- 332 371- 384 AUH2T1 0-jr- MPY1DT1 0— 02 01 02 vTnTTC ©- 13 LOUH/B 0- 06 LDUH/D 0- 332-04 VIN4T2 0- 371-14 LDU047/B 0- 383-01 CFX1T1 0- 362-06 UODLQ/C 0- 371-13 UODLO/B ©- 3B2-07 UODLO/A 0- 384-03 CVD13T2 0— 332-02 AUH1T3 0W 361-01 HP7ITT ©— 371-13 UHDLH/B 332-01 VIN2T7 0- pCE> ]«>*- £> :^> I^> i*y> M>2 D6>S ^6>i- ^2>>^ -0LDUH 400-04 -0LDUQ47 400-05 -0UQOLQ 400-04 -0UHDLH 400-04 -0VDUO47 400-03 NO. 338 Ula*. ¥t <** ■ I v I 6 I ONI I DEPARTMENT of COMPUTER SCIENCE Unlvtrilty of Illinois L *•»'•••* kr jSmL. T G 11-8-71 CARD location: H-64 T,ue AU FINAL LEVEL TASK DRIVERS TASK DRIVER "Fl" Sh.«l of Drawing No. AUQ- 07~ 388- 01 CVD21T1 0- T4DLS/B ©- 384-04 371-12 382-05 DVB7T1 0^ 361-01 MPY5T2 0- Z4DLM/A 0f Z4DLM/B 0- 352-07 371-12 384-06 Z4DLM/D 0- 352-03 371-13 382-07 CAL1T7 ©rx- LDUM/B @— LDUM/C ©7 384-04 CVD22DT1 0- 361-02 MPY6T1 @- 371-02 384-06 CFX2DT1 ®- LDUS/B ©- 383-01 371-13 382-06 ldus/c 0nr 384-06 LDUS/D ©- 3 99-01 C0MCLR 0-t 384-04 CVD18T1 0- 382-04 DVB6T1 0iK" 371-12 DIVTD2 ©- 361-01 MpVSTl ©- DIV1T1 CVDTD2 l~°*y ^y T[y i^y &> JJm^oI M>!i -0 T4DLS 400-08 -0Z4DLM 400-C -0LOUM 400-07 -0LDUS 400-07 0UMDX1 400-08 0USDS1 400-08 NO. 709 NO. 554 Hl-li Hi VISIONS I DEPARTMENT of COMPUTER SCIENCE University of Illinois L. G. §gL Diawn kr T. G. Date l-M-TZ 11-8-71 Sg»»n«d«» J*o- CARD location: H-62 AU FINAL LEVEL TASK DRIVERS TASK DRIVER "F2" Sh..t Drawing No. AUQ-Q7- 388-Q 2k5 VIN3T6 0- 332-02 352-03 CAL1T5 07; 382-07 LDEUM/C 0=, 384-01 CVD1DT1 0- 77y 1E> m 0LDEUM 212-02 332-01 352-03 VINHT6 0- CAL1T6 0r; ^y £> -0LOEUU 332-04 VIN4T4 0- 352-05 SFB3DT1 ®- 332-01 VIN2T2 0- 352-08 LOM/A ©Tfj- 361-01 MPY3DT1 © 371-13 LDMTB 382-07 LDM/C 0£J- 384-06 LDM/O ;3t>^i©> &— i©> ^T)>" -0LDFAR 400- -0LOFAL 400-06 -0LOM felt i) u • I V I S I O N S DEPARTMENT of COMPUTER SCIENCE University of Illinois 11-9-71 CARD location: H-66 TITlE AU FINAL LEVEL TASK DRIVERS TASK DRIVER "F3" Drawing No. AUO " 07" 388"03 247 390-05 C0MCLR(7> 371-08 DFX20T1 (g> 371-13 0IVTD3 (£> 371-05 DFX2T1 ©■ 384-04 CVD18T1 <§> 371-12 SLHL8UH/B (f> 384-03 CV013T1 ©■ 371-07 DFX13Tl(Ti> 384-03 CVD15T1 (§> 352-02 AUH1T2 (J3> 352-02 AUH1T1 @- 361-01 MPY1T1 ©■ 371-06 DFX7T1 ©■ 211-02 U003EZ 0- ■©UQ03EZ 371-04,05,361-02 /: * U fe , CK«ngt «rda, Aao.a.ari by D » E VISION S -? ^ 72 DEPARTMENT of COMPUTER SCIENCE University of Illinois L G JM_ 7-23-71 Supanadai d« . card location: E38 TIUE AU REGISTER SELECTORS UH REGISTER SELECTOR Drowin 9 n„. AUO- 07-390-02 371-098 DFX28T1 384-04 CVD18~ 390-05 C0MCIR© J B4* V i 3 [ B4~V- 352-07 SUHDM/A (7 361-01 MPY3T1 <£ 371-14 SUHDM/B <£ 384-02 CVD11T1 ®- 382-05 DVB9T1 (Ti> 371-09B DFX30T1 ©- 382-04 DVB4T1 © 384-04 CVD20T1 (g> 371-01 DFL3T1 06) 371-04 DFX6T2 (T 371-04 DFX6T4 ©■ 371-02 DIV3T1 ©■ 400-07 D6V-© SETM640NE 400-07 400-07 D5>-^— © UQ58DM6164 400-07 OS^- 1 — ® LM912DM912 400-07 D5>- 2 — (3) SETUQ470NE 400-06 D5y-^-d) SETUQ330NE 400-06 D5^>^— ® SETUQ33ZER0 400-06 400-04 Cheng* order Approved by D REVISIONS I DEPARTMENT of COMPUTER SCIENCE University of Illinois Approved by 5V- TG. 7-22-71 Supariodai dwg. card location: E-46 T,TLE AU REGISTER SELECTORS M REGISTER SELECTOR, SETUQ330NE, SETUQ33ZER0, SETUQ470NE, QBDUQH Sh.et of Drawing No. AU0-07-39OQ1 390-05 C0MCLR (V) — ^ B4 361-01 MPY2T1 0- 371-14 CLUQSFF/B ®- 1J o^ WO I 382-01 CVL4T1 ©- 384-06 CLUQSFF/D ©- 371-01 DFL3T1 ©- 371-13 DIVTD3 ©- llH[B?y-^. 371-11 DFX39T1©- 352-07 S LMDUQ/A ©- 361-02 MPY7T1 @- 371-14 SLMDUO/B ©- 382-05 DVB10T1 @- 384-06 SLMDUO/D @- 352-04 NUQ1T3 @- 371-12 SLQL8UQ/8 ©- 382-06 SL0L8UQ/C ©- 384-03 CVD13T1 ©- 352-04 NUQ1T2 Qg»- 371-07 DFX13T1 ©- 382-06 SLQL4UQ/C ©- 384-03 CVD15T1 ®- 352-07 SU0R4UQ/A ®- 371-11 DFX38T1 ®- 382-03 FLX5T2 ®- 352-02 AU01T1 ©- 361-01 MPY3T1 ©- 371-14 SLQR8UQ/B ©- 383-01 CFX1T1 ©- "b£)d! 2. SLQL1UQ !5| D „ VI & i|„, TV2 - SLQR1UQ03 La[BTy l£y 10 SLMDUQ L^7T)£ 77)> 10 SL0L8U0 L-u[bT)^ Zi> 6 SLQL4U0 L^[77y «V 0.SLQR4UQ 77)£ i l^y 77)^ TT)^! - 77> 77)^- 77> |77> 1.7)^ A»p>»»ad b r J. 7J REVISIONS 2)+9 SETUOO30NE 400-05 D6>2 © LQR1UQ03 400-05 LE jj|J_3 D5>£— (w) I N J E C T SI G N DEPARTMENT of COMPUTER SCIENCE Unlvtnlty of Illinois f -~-l — N.|,.....l.. dw«. card position: E-40 TITLE AU REGISTER SELECTORS UQ REGISTER SELECTOR Drowin 8 No. AU0-Q7-39Q-Q4 390-05 C0MCLR Q^\ C4^ 371-03 DIV8T1 (§> 371-02 DIV4T1 ©■ 371-02 DIV5T1 <£> 371-02 DIV6T1 ©■ 1-02 DIV7T1 ©■ 352-02 UHQ1T1 ®- 371-02 DIV1T1 ©■ 384-06 CVDTD2 (|> 352-01 371-04 361-01 371-02 382-04 384-04 MPY3T1 ©■ DIV3T1 ©■ DVB6T1 (D CVD18T1 (f> 399-01 C0MCLR ©■ 211-02 UQEZ (n> 211-01 UHEZ (l) 227-05 UQ33 @- 400-11 A3C1T3 © a -r~\ ) 6 SGI asmiti 05) h — y — @C0MCLR 400-11 400-9 P Kr^LU. ■>s-71 REVISIONS 1 DEPARTMENT of COMPUTER SCIENCE University of Illinois L.G. Approved by Drawn by T. G. 8-1-71 $up»r*»d»» dwg, titie AU REGISTER SELECTORS MODEL DIVISION DIVISOR SELECTORS, SDS GATE SIGNAL Gi SELECTORS Shot of Drawing No. AUG-Q7-39Q-_05_ 361-02 MPY7T3 Q9> 371-12 C Y1SFF/B ©- 382-06 CVLTD1 @" 384-06 CVDTD2 fj6> ril N C © 390-05 C0MCLR ®— N.C. ©- 352-01 ASC1T3 @- 361-02 MPY7T2 ©- 371-09A DFV25T3 @- 384-04 CV018T1 ©- 371-09B DFX30T2 ©- NC ®_ 371-09A DFX25T1 ©■ ^£y 382-04 DVB6T1 ®- 352-02 U0H1T1 ©- 371-04 ASM1T1 <3> 371-02 DIV1T1 ©- 371-12 D1VTD1 ©- 384-06 CV0TD1 ® f H c ©- N C ®- NC ©- f fa*jLL ;s 7T> 10 CYiSFF *{^y ITy SML7Y1 ©°» SML6Y1 ^2> rE)^" ^ SMDYl f^B?)* ^T)^ {b7)^ STENDY1 £T> 6 . SML1Y4 '{TTy^ ~^y aTV A6 3 1 SPDY4 ;> 6 CY4SFF? glT V CY2SFFi [^V iaj — - / ' — I r^" Vz SML5Y2 a B Ba rtEy I^V^SMLSYJ «V c7)^ 02V cT)^ I ry y 0* L>= igy ^E> J) MDYl ML7Y1 400-C 7-21-71 TIUE AU REGISTER SELECTORS M SHIFT ARRAY SELECTORS Shsat of 251 Drowina No. AUQ-07" 39O06 352-03 361-02 371-09B 382-06 384-06 352-03 371-12 382-06 352-03 361-02 371-12 382-02 383-01 352-03 371-12 ''!— f ;i]^> CAL1T1 ®- MPY7T3 ©- 0FX29T1 ®- CLNEG0/C 0- CVDTD1 ©- CAL1T3 ®- C LNEG1/B ©- CVLTD1 (w>- CAL1T2 ©- MPY7T2®- SNEG0/B ©- CVL10T1 @- CFX2T1 ©- CAL1T4©- SNEG1/B©- j*)^ -f!^) ^ ll)oB 15 / -ogy -ntg^ T^gy TJgV -(g) CLNEG0 390-08 -© CLNEG1 390-08 -@ SNEG0 390-08 -© SNEG1 390-08 371-05 352-02 371-12 384-06 371-05 384-02 DFX1T5 @- UHQ1T1 @- CLNEG234/B ©- CLNEG234/D (§>- DFX1T2 (9>- CVD2T1 ®- 7-E^ TT)>£- t3E>* rigy rigy rtgy -© CLNEG0O3 390-08 -@ CLNEG234 390-08 -© SNEG047 390-08 352-07 361-01 371-14 CSR/A ©- MPY3T3 ©- CSR/B ©- ^> -r-Jgy -® CSR 390-08 352-07 361-01 371-01 SSR/A 0- MPY3T2 (D- DFL1T2 ©- 1T)£ ngy -©SSR 390-08 REVISION S I DEPARTMENT of COMPUTER SCIENCE University of Illinois Approved by Drown by TG 7-28-71 Sup«riad«t dwg. CARD location: E-34 TITLE AU REGISTER SELECTORS TASK SIGNAL COLLECTOR Sheet of Drowin. No. AUO "07- 390-07 253 321-01 384-01 390-05 SSIGNAPOS ©- CVD1DT1 (|> C SIGN A 383-01 CFX2T1 (4> SSI.GNA 321-01 332-01 SSIGNANEG ©- VIN2T3 ©- Vll®- LDFSIGNA 371-04 383-01 384-01 390-07 390-07 371-098 390-07 371-09A 352-03 DFX6T1 ®- CFD4T1 ©- CVD1T1 ®- CSR ©- SSR (g>- DFX31T1 ®- SRCDNEG1 390-07 CLNEG1 ©- 382-04 390-07 DVB6T1 @- CLNEG234 ©- 390-07 SNEG0 ®- 390-07 CLNEG0 ©- 371-05 DFXlT3(y>SISES20jJ 390-07 390-07 CLNEG0O3 ©- SNEG047 ©- 371-05 DFX1T4 © CLNEGflTT 1 — "TTY; 4 06 X> -<§) SIGNA 352-01, 371-09A 382-01 -© SIGNA 371-01,11,04 352-03,01 382-02 !S—L P) SIGNR 400-05 -® SR H) SIGNR 400-05 5|a^>!2-©n EG1 400-09 - B i i - 1 H I K 12 262-00 M 13 -68 H I 17 V 20 * JIVIS I ONS §i DEPARTMENT of COMPUTER SCIENCE University of Illinois RtnaJl* s z •-IO-11 AU DRIVER INTERFACE CONTROL -* PROCESSING HARDWARE Drawing No . AUO-07-400-04 352-06 390 -04 388-01 371 -05 388 -01 352-06 390 -08 390 OS EULDXT INJECTSIGN LDUQ LDU003 LDU047 U047DXT SIGNR 371-n SETREMSIGN 8 H 9 K 12 262-00 M 13 M-65 R EULDXT INJECTSIGN LDUQ 240 227 1.227 240 227- 227- 227- -0S 01 LDUQ03 09 LDUQ47 UQ47DXT SIGNR 01 ,OS 10, 240-01 SIGNR 10 SETREMSIGN oi 371- IJ -02 04 -02 04- . INHBINJECT 390 LHL1UH 390 LMDUQ 390 LML32UH L0L1UQ LQL4UQ 390 L0L8U0 LQR1UQ03 LQR4UQ LQR8UQ INHBINJECT 227- 226- 227 226 ■ 227 Ol LHL1UH IO LMDUQ 09 LML32UH IO LQL1UQ LQL4UQ LQL8UQ -o; LQR1UQ03 LQR4UQ LQR8U0 J 384- 05 ot < 06 06 OG -o& -Ol • Ol - 01 -06 CVD26T1 390- 390- ;etuqo3cne TENDYl 390 UHDY1 352- UQODXT 352 UQ13DXT 332 VIN2T5 332 VIN2T8 368 352 VDUQ47 XTDES SETDECSIGN 227 227 280 227- 2.40 240 . 227 240 IO SETUQO30NE TENDYl 09 19 UHDY1 09 UQODXT OS UQ13DXT -05 VDUQO VDUQ13 -OS VDUQ47 XTDES 05 RE V I S I O N S I DEPARTMENT of COMPUTER SCIENCE University of Illinois P&aUc 3-/0-72 3-7-72 Supifi.dti d. B . AU DRIVER INTERFACE CONTROL -* PROCESSING HARDWARE n fl N< AUO-07-400-5 257 390-O3 SETUQ33ZER0 390-03 SETUQ330NE 371-14 CLUQ65 399-01 COMCLR 2 4 5 e 9 C A e E H K >2 262-00 M _ 13 16 P-64 R T — 17 V — 20 W SETUQ33ZER0 227- OS SETUQ330NE 227-OS CLU065 290-01 COMCLR 29O-0I UOOMR 3SZ-05 EQ 390- 03 SETUQ470NE r EUL1 212-07^ EUL2 l EUL3 352-OS UN 3S2-0S 10 C 4 5 8 e - 3 12 262-00 K M 13 P-65 H 16 17 20 T V — — — Z 4 5 | c B F — - — i 8 9 12 262-02 M ' ' 13 R 16 P-66 r 17 V 20 * EQ SETUQ470NE 227-12 EUL1 1 EUL2 r 240-01 EUL3 J UN 2 1 1 - 04 ID 2 1 1 - 04 2I2-07V EUL4 EUL5 EUL6 EUL7 332-OI VIN2T1 332-o* VIN4T1 ■ 332-02 VIN3T7 • 3S2-04 VIN5T1 ■ 352 -OS FM- 3S2- OS GT ■ B 262-00 m R P-67 EUL4 EUL5 EUL6 ■ 240 -Ol EUL7 FA1LFA 211 - o4 FA2RFA 211 - 04 FB1LFB 211 - 05 FB2RFB 211 - 03 FM 211 - 04 GT 211 - 04- 352-OS SFB3T1- 368 03 LDFAL 388-03 LDFAR 352 -OS LS 3SZ -OS LT • 361-02 MEPGATE • 361 -Ol MEPLATCH- 332- OS BV/A - INDFA LDFAL LDFAR ■ 211 -04 LS LT J MEPGATE 290 -03 MEPLATCH 290 -03 OV 211-04 >l»l S I O N S 01 DEPARTMENT of COMPUTER SCIENCE Unl veriliy of Illinois l' '-u.il.. 3 IP '12 •..,.,..*., d.„ AU DRIVER INTERFACE CONTROL -» PROCESSING HARDWARE Drow,n 9 N..AU0-07-400-06 388 -03 LEW- 388 -02 LDUM 3O8-02 LOUS !LMDM LMR4M LM912DM912 390-01 LSDUS 390-OI LSL8US 390-06 NEG0 C 4 5 B E - e H 12 262-00 M 1 ■ ■ f ' " 13 T-65 R 16 17 T V 20 2 | c w A 4 B - 5 E - e H — 12 262-02 M 1.1 R 16 T-66 T - 17 20 V W LDUM LDUS 222- 09 222 -09 LMDM 22! -09 LMR4M LM912DM912 2 21-01,02,03,05,06,07,08 221-01 LSDUS 222-09 LSL8US NEG0 222 -09 223 -13 390- 01 03 LSR8US 390- SETM640NE 390- 03 UHDM 383 - OJ -Ol CFX2T2 390 UHDUS 371 ■ OS UQ1DUS1 371 OS U033DUS33 390 -03 UQ58DM6164 390 • 01 UQ912R52UM | 2 C i - 4 5 8 B E K M 12 262-00 13 16 17 20 T-67 R T V w LSR8US 222 221- 09 SETM640NE oa UHDM 221 - 09 SETUS90NE 222 222 - 01 UHDUS - 09 UQ1DUS1 222 - Ol U033DUS33 222 -OS; 2ZI -OS U058DM6164 221- OO U0912R52UM 223 -08 | 2 C a 4 B 5 E - 8 H — 9 K — 12 262-00 M 13 16 -68 R. T 17 v - 20 w JJVISI O N S ■ DEPARTMENT of COMPUTER SCIENCE University of Illinois Approved b r Drown by S Z 3-/0-72 3-7-72 AU DRIVER INTERFACE CONTROL -» PROCESSING HARDWARE Df owin B No. AU - 07' 400 - 259 - 2 C 4 - 4 8 - 5 e - e H - 9 K - 12 262-00 M : 13 IS -64 R T 17 V 20 W "I 02 -01 02 02 02 - 08 - 08 LMDUM 390- LML8UM LMR8UM 388 T40LS 390 UOOUM 388 388- Z4DLM UMDXi 388 USDS! 390 NEG0O3A 190 NEGB47A 9 K 12 262-00 M 13 V-65 R LMLBUM LMR8UM ■ T4DLS ■USDS1 Z2S - OS 222-09 225- OS 2 C a 4 B ! E a H • : > K 2 262-02 M 13 16 -66 Ft r 17 V 20 * 2 c .-. •> H 9 t a N 9 K 1! 262-00 M 13 16 -67 R l 17 •J 10 * | - 2 c 4 - -1 B 9 [ 8 H 9 K 12 262-00 M — 13 16 -68 R l 17 V 20 w » E V I S IONS DEPARTMENT of COMPUTER SCIENCE University of Illinois Lii»^_ 0.... »r sz Dal* 3- '3 72 AU DRIVER INTERFACE CONTROL -* PROCESSING HARDWARE Drawino No. AUO - 07" 40C-08 | 2 c A 4 B 5 E 8 H 9 K 12 262-00 M 13 16 -64 H T 17 V 20 yv 390 OS 64 390- 05 gI Ofe . MDYl 390 ML1Y4 PDY4 MDY4 390 ■ 08 NEG1 190 -08 -06 NEG4 390 ML6Y1 39O-06 ML7Y1 2 4 C A e 5 e 9 12 13 E H K M 262-00 X-65 16 T 17 V 20 W G4 2S0- 20 gT 250 ■ 17 MDYl 250 1 ■17 ML1Y4 PDY4 [•aso -20 MDY4 1 NEGl 250- 17 NEG4 250- 2SO 250 20 ML6Y1 ■ 17 ML7Y1 - 17 ? C a 4 B 5 E 6 H 9 K 12 262-02 M 13 16 -66 R T 17 V 20 W 2 C A 4 B 5 E e M 9 K 12 262-00 M 13 16 -67 fi T IT V 20 A 2 C A 4 8 5 E 8 H 9 K 12 262-00 M 13 16 -68 R T IT V 20 W REVISI O N S DEPARTMENT of COMPUTER SCIENCE University of Illinois f Ai^Zo S-/3-?2 3-7-72 AU DRIVER INTERFACE CONTROL -► PROCESSING HARDWARE Orowi„, no. AU0-Q7-400-09 261 - 2 C 4 4 e 5 E e H 9 K 12 262-00 M _ 13 16 -64 H T — 17 V 20 w 390- 05 G3 390- 05 06 06 62 390- ML2Y3 390 ML3Y3 OODMO 390 - OS ■ OlDMD D2DMD D3DMD 390 ■08 NEG2 390 - 08 NEG3 2 A 4 5 e 9 12 262-00 3 BB-65 3 e K M ■i ■■■ ■ i i ■ i 1 ■ — 1 p T V W 20 1 2 C A 4 B 5 E e 9 H i2 262-02 M 13 BB-66 16 17 H V — 20 w G3 2S0 -19 G2 250 250 250 - 18 ML2Y3 19 ML3Y3 19 OODMD " D1DMD D2DMD •210- 01,05 D3DMD NEG2 250 - 18 NEG3 250 - 19 390 -06 390 - 06 ML5Y2 2 C A 4 5 8 B E 9 K i2 262-00 M 13 BB-67 16 H T 17 V 20 w 250 - 18 230 - 18 II VI S I O N S I DEPARTMENT of COMPUTER SCIENCE University of Illinois '' >^i sz .3-/3-72 Su,....d.. d.| AU DRIVER INTERFACE CONTROL ■* PROCESSING HARDWARE Drawing No. A UP '07-400 - 1 1 2 C A A a - 5 E - 8 H - 9 K 12 262-00 M 13 -64 R — 16 T — 17 V 20 W 321-01 CVD 321 -01 OIV 0IV4DT1 DIV5DT1 371-02 i, 0IV6DT1 DIV7DT1 MDOINT DRTEN 1 *—<< • < — 2 C 4 A B 5 S E H K M R T V i2 262-00 3 DD-65 17 — 20 w - 1 2 C 4 5 A 8 E — 8 H — 9 K 12 262-02 M 13 R 1 — DD-66 16 T — - 17 V — — 20 V. CVD DIV LD0MS12 LDQMS34 LD0MS56 LD0MS78 MDDINT 210-02 DRTEN 210-02 210- 06 210-05,06 S-2I0-O5 1 2 C A 4 B 5 E 8 H 9 K 12 262-00 M 13 16 -67 R T 17 V 20 W 1 2 c A 4 8 5 E B H 9 K 2 262-00 M 13 IS -68 R - T 17 v - 20 W - » E V I S I ON! £=)■ DEPARTMENT of COMPUTER SCIENCE ^™ University of Illinois ? Ku*u 3-/5-72 3 7-72 AU DRIVER INTERFACE CONTROL -» PROCESSING HARDWARE Drawing Nc AUO-07-400-12 263 6.0 CONTROL SIGNAL NAMES AND THEIR FUNCTIONAL DESCRIPTION This section gives a listing of Control Signals which, appear on the Control logic drawings. These signals together with their functional descrip- tion are printed in an alphabetical order. PL/l description of many of these signals is also available in Volume 1 of Illiac III Arithmetic Unit manual (DCS Report No. 366). It is necessary for the reader to be conversant with the static description of the AU (date paths, registers' structure etc.) and strategy of control point technique for implementing the control sequences to fully understand the functional description of the signal names. SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 26k ADD ARITHMETIC ORDER ADD AEXPGT A»S EXPONENT IS GREATER ALNUHWAIT SUBROUTINE ALIGN UH WAIT ALNUQWAIT SUBROUTINE ALIGN UQ WAIT ASC ARITHMETIC ORDER ADD OR SUBTRACT OR COMPARE ASIMWAIT SUBROUTINE ASSIMILATE WAIT AUBUSY AU IS BUSY BEXASC BEGIN EXECUTION OF A CONTROL SEQUENCE FOR ASC BEXCVDFIX BEGIN EXECTUION OF CONTROL SEQUENCE FOR CVD, FIXED POINT OPERAND BEXCVDFLT BEGIN EXECUTION OF CONTROL SEQUENCE FOR CVDt FLOATING POINT OPERANO BEXCVFDEC BEGIN EXECUTION OF CONTROL SEQUENCE FOR CVF, DECIMAL OPERAND BEXCVFIX BEGIN EXECUTION OF CONTROL SEQUENCE FOR CVF, FIXED POINT OPERAND BEXCVLDEC BEGIN EXECUTION OF CONTROL SEQUENCE FOR CVL , DECIMAL OPERAND BEXCVLFLT BEGIN EXECUTION OF CONTROL SEQUENCE FOR CVL, FLOATING POINT OPERAND BEXDIVFIX BEGIN EXECUTION OF CONTROL SEQUENCE FOR DIV, FIXED POINT OPERANDS BEXDIVFLT BEGIN EXECUTION OF CONTROL SEQUENCE FOR DIV, FLOATING POINT OPERANDS BEXMPYFIX BEGIN EXECUTION OF CONTROL SEQUENCE FOR MPY, FIXED POINT OPERANDS BEXMPYFLT BEGIN EXECUTION OF CONTROL SEQUENCE FOR MPY, FLOATING POINT OPERANDS BEXPOLY BEGIN EXECUTION OF CONTROL SEQUENCE FOR POLY. BR BOGUS RESULT CALLALNUH CALL SUBROUTINE ALIGN UH(ALNUH) CALLALNUQ CALL SUBROUTINE ALIGN UQ(ALNUQ) 265 SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION CALLASIM CALL SUBROUTINE ASSIMILATE (ASIM) CALLCOMPL CALL SUBROUTINE COMPLEMENT (COMPL) CALLCVDDIV CALL SUBROUTINE CVDCIV CALLOIVIDE CALL SUBROUTINE DIVIDE CALLDVB CALL SUBROUTINE DVB CALLFLNOFX CALL SUBROUTINE FL-NORM-FIX CALLNORMUQ CALL SUBROUTINE NORMALISE UQ (NORMUO) CALLUHTUG CALL SUBROUTINE UHTUQ CAL1AI CONTROL POINT CAL1 ADVANCE-IN CBYONE CLEAR FLIP-FLOP BYONE CEUCTRDIR CLEAR FLIP-FLOP EUCTRDIR (EUC COUNTER DIRECTION) CEUDIFF CLEAR FLIP-FLOP EUDIFF (EXPONENT DIFFERENCE) CLDDMDSFF CLEAR DDMD (DIVIDEND DIRECT TO MODEL DIVISION) SELECTOR FLIP-FLOPS CLDVBWAIT CLEAR FLIP-FLOP DVBWAIT CLEUMSFF CLEAR EUM SELECTOR FLIP-FLOPS CLEUUSFF CLEAR EUU SELECTOR FLIP-FLOPS CLG1234 CLEAR SOS-ARRAY GATE SIGNALS G1,G2,G3,GA CLG4 CLEAR S0S4 GATE SIGNAL G4 CLICC CLEAR COUNTER ICC CLMSFF CLEAR M REGISTER SELECTOR FLIP-FLOPS CLNDCNT CLEAR COUNTER ND(NUMBER OF DECIMAL DIGITS) CLNDRR8 CLEAR FLIP-FLOP NDRR8 (NUMBER OF DIVISOR'S 8 BIT RIGHT SHIFTS) CLNEGO CLEAR FLIP-FLOP NEGO. (NEGO FLIP-FLOP GENERATES CONTROL NEGO) CLNEG003 CLEAR FLIP-FLOP NEG003 CLNEG0A7 CLEAR FLIP-FLOP NEG047 SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 266 CLNEG1 CLNEG2 CLNEG234 CLNEG3 CLNEG4 CLSCWORO CLUHSFF CLUMSFF CLUQDMR CLUQSFF CLUQ65 CLUREN CLUSSFF CNTICCDN CNTICCUP CNTND CNTNDDL8UP CNTNORL1DN CNTNORL1UP CNTN0RL80N CNTNORL8UP COMPLWAIT COMPNEG1 CORREM CLEAR FLIP-FLOP NEG1. (NEG1 FLIP-FLOP GENERATES CONTROL SIGNAL NEG1) CLEAR FLIP-FLOP NEG2. ( NEG2 FLIP-FLOP GENERATES CONTROL SIGNAL NEG2) CLEAR FLIP-FLOPS NEG2 t NEG3 ,NEG4 CLEAR FLIP-FLOP NEG3. (NEG3 FLIP-FLOP GENERATES CONTROL SIGNAL NEG3) CLEAR FLIP-FLOP NEG4. (NEG4 FLIP-FLOP GENERATES CONTROL SIGNAL NEG4) CLEAR FLIP-FLOP •SCWORO' (INDICATES NUMBER OF WORD BEINI TRANSMITTED) CLEAR UH REGISTER SELECTOR FLIP-FLOPS CLEAR UM REGISTER SELECTOR FLIP-FLOPS CLEAR FLIP-FLOP UQDMR (REGISTER UQ LEAST SIGNIFICANT BYTE TO MULTIPLIER RECORDER) CLEAR REGISTER UO SELECTOR FLIP-FLOPS CLEAR BIT 65 OF REGISTER UQ CLEAR FLIP-FLOP UREN (UNIT REQUESTS ACCESS TO EXCHANGE NET) CLEAR REGISTER US SELECTOR FLIP-FLOPS COUNT ICC DOWNWARD COUNT ICC UPWARD COUNT COUNTER NO UPWARD COUNT NDDL8 UPWARD COUNT NDRL1 DOWNWARD COUNT NDRL1 UPWARD COUNT NDRL8 DOWNWARD COUNT NDRL8 UPWARD SUBROUTINE COMPL WAIT. COMPLEMENT CONTROL SIGNAL NEG1 CORRECT REMAINDER 267 SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION CP COUNT PULSE CPRA ARITHMETIC ORDER COMPARE ALGEBRAIC CSIGNA CLEAR FLIP-FLOP SIGNA (SIGN OF OPERAND A) CSR CLEAR FLIP-FLOP SR (SIGN OF RESULT) CUMDX1 CLEAR FLIP-FLOP UMDX1 CUQ133DUS133 CLEAR FLIP-FLOP UQ133DUS133 (REGISTER UQ BITS 1 TO 33 DIRECT OT REGISTER US BITS 1 TO 33) CUQ912R52UM CLEAR FLIP-FLOP UQ912R52UM (REGISTER UO BITS 9 TO 12 SHIFTED RIGHT BY 52 POSITIONS TO UM ) CUSDS1 CLEAR FLIP-FLOP USDS1 CVD ARITHMETIC ORDER CVD (CONVERT TO DECIMAL) CVDDIVWAIT SUBROUTINE CVDDIV WAIT CVD12AI CONTROL POINT CVD12 ADVANCE-IN. CVD13AI CONTROL POINT CVD13 AOVANCE-IN. CVF ARITHMETIC ORDER CVF (CONVERT TO FLOATING POINT) CVL ARITHMETIC ORDER CVL (CONVERT TO LONG FIXED POINT) CYiSFF CLEAR Yl SELECTOR FLIP-FLOPS. CY2SFF CLEAR Y2 SELECTOR FLIP-FLOPS CY3SFF CLEAR Y3 SELECTOR FLIP-FLOPS CY4SFF CLEAR Y4 SELECTOR FLIP-FLOPS DEC NUMBER TYPE DECIMAL DEXPGE2 DIFFERENCE OF EXPONENT GREATER THAN OR EQUAL TO 2 IN EXCESS 64 REPRESENTATION DEXPGTZ DIFFERENCE OF EXPONENT GREATER THAN ZERO IN EXCESS 64 REPRESENTATION DEXPGT13 CIFFERENCE OF EXPONENT GREATER THAN 13 IN EXCESS 64 REPRESENTATION DEXPINP CIFFERENCE OF EXPONENT IS IN NEGATIVE RANGE DEXPIPR DIFFERENCE OF EXPONENT IS IN POSITIVE RANGE SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 268 DEXPLEM2 0EXPLTM13 OEXPLTZ OIV OIVIOEWAIT OIVIOIOAO OIVI011AI 0IVI07AO ORTEN OVBWAIT DV85AI DVB7AI DODMD DIOMO D2DMD D3DMD EADEUU EBDEUM EQ EUDIFF EULDEUU EULDXI1 EULGT21 EULGT28 EULGT8 DIFFERENCE OF EXPONENT IS LESS THAN OR EQUAL TO -2 IN EXCESS 64 REPRESENTATION DIFFERENCE OF EXPONENT IS LESS THAN -13 IN EXCESS 64 REPRESENTATION DIFFERENCE OF EXPONENT IS LESS THAN ZERO ARITHMETIC ORDER DIV (DIVISION) SUBROUTINE DIVIDE WAIT CONTROL POINT DIVIDIO ADVANCE-OUT CONTROL POINT DIVID11 AOVANCE-IN CONTROL POINT DIVID7 ADVANCE OUT DIVISOR IS TEN SUBROUTINE DVB WAIT CONTROL POINT DVB5 ADVANCE-IN CONTROL POINT DVB7 AOVANCE-IN GATE DIVIDEND DIRECT TO MODEL DIVISION GATE FIRST PARTIAL REMAINCER DIRECT TO MODEL DIVISION GATE SECOND PARTIAL REMAINDER DIRECT TO MODEL DIVISION GATE THIRD PARTIAL REMAINDER OIRECT TO MODEL DIVISION GATE EXPONENT OF OPERAND A DIRECT TO REGISTER EUU GATE EXPONENT OF OPERAND B DIRECT TO REGISTER EUM EQUAL EXPONENT DIFFERENCE GATE CONTENTS OF REGISTER EUL DIRECT TO EUU GATE CONTENTS OF REGISTER EUL DIRECT TO OUTBUS XT CONTENTS OF REGISTER EUL IS GREATER THAN 21 IN EXCESS 64 REPRESENTATION CONTENTS OF REGISTER EUL IS GREATER THAN 28 IN EXCESS 64 REPRESENTATION CONTENTS OF REGISTER EUL IS GREATER THAN 8 IN EXCESS 64 REPRESENTATION SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 269 EUXDEUM EXOEUX FA1LFA FA2RFA FB1LF8 FB2RFB FIX FIXDIV FIXDIV1AAI FLNOFXWAIT FLT FM GETDEC GETOIG GOTOEXIT2 G0T0EXIT3 GT Gl G2 G3 G4 ICCEQZ ICCGT7 ID ILLDOP GATE CONTENTS OF REGISTER EUX DIRECT TO REGISTER EUM GATE EXPONENT OF OPERAND X (USED IN POLY) DIRECT TO REGISTER EUX GATE FLAGS OF WORD 1 OF OPERAND A TO LEFT HALF OF REGISTER FA GATE FLAGS OF WORD 2 OF OPERAND A TO RIGHT HALF OF REGISTER FA GATE FLAGS OF WORD 1 OF OPERAND B TO LEFT HALF OF REGISTER FB GATE FLAGS OF WORD 2 OF OPERAND B TO RIGHT HALF OF REGISTER FB NUMBER TYPE IS FIXED POINT CONTROL SEQUENCE DIV WITH-FIXED POINT OPERANOS CONTROL POINT DFX14 ADVANCE-IN SUBROUTINE FL-NORM-FX WAIT NUMBER TYPE IS FLOATING POINT FLAG MATCH GENERATE OECIMAL DIGITES TRANSFER DECIMAL DIGITS TO REGISTER UO GO TO CONTRCL POINT EXIT2 GO TO CONTROL POINT EXIT3 GREATER THAN SDS GATE SIGNAL Gl SDS GATE SIGNAL G2 SDS GATE SIGNAL G3 SDS GATE SIGNAL G4 CONTENTS OF COUNTER ICC EQUALS ZERO CONTENTS OF COUNTES ICC IS GREATER THAN ZERO ILLEGAL DATA ILLEGAL DECIMAL OPERAND SIGNAL NAME 270 SIGNAL FUNCTIONAL DESCRIPTION ILLOP INDFA IVOIVR IV1 LDOSIGNA LDESDEUL LDEUM LOFAL LOFAR LOFSIGNA LDICC LDM LOPE L0PE1 L0PE2 L0PE3 LDQMS12 LDQMS34 LDQMS56 LDQMS78 LDUH LDUH47 LDUM LDUQ LDUQ03 LDUQ47 ILLEGAL OPERATION CODE GATE INDICATORS DIRECT TO FLAG REGISTER FA GATE INSTRUCTION VARIANT BITS DIRECT TO INSTRUCTION VARIANT REGISTER IVR INSTRUCTION VARIANT BIT 1 LOAC SIGN OF DECIMAL OPERAND A TO FLIP FLOP SIGNA GATE (LOAD) OUTPUT OF EXPONENT UNIT ADDER TO REGISTER EUL LOAD REGISTER EUM LOAO LEFT HALF OF FLAG REGISTER FA LOAD RIGHT HALF OF FLAG REGISTER FA LOAD SIGN OF FLOATING OR FIXED POINT OPERAND A TO FLIP-FLOP SIGNA LOAD COUNTER ICC LOAC REGISTER M LOAD PARITY ERROR FLIP-FLOP LOAD PARITY ERROR OF FIRST WORD LOAO PARITY ERROR OF SECOND WORD LOAD PARITY ERROR OF THIRD WORD LOAD BITS 1 AND 2 OF QUOTIENT BUFFER REGISTERS QM AND QS LOAD BITS 3 AND 4 OF QUOTIENT BUFFER REGISTERS QM AND QS LOAD BITS 5 AND 6 OF QUOTIENT BUFFER REGISTERS QM AND QS LOAD BITS 7 AND 8 OF QUOTIENT BUFFER REGISTERS QM AND QS LOAD REGISTER UH LOAD BYTES 4 TO 7 OF REGISTER UH LOAD REGISTER UM LOAD REGISTER UQ LOAD BYTES TO 3 OF REGISTER UQ LOAD BYTES 4 TO 7 OF REGISTER UQ SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 271 LDUS LFIX LHL1UH LHL4UH LHL8UH LHR4UH LHR8UH LMOM LMDUM LMDUQ LML32UH LML8UM LMR4M LMR8UM LM912DM912 LQL1UO LQL4UQ LQL8UQ LQR1U003 LOAD REGISTER US NUMBER TYPE IS LONG FIXEO SELECT CONTENTS OF REGISTER LH SHIFTED LEFT BY 1 BIT INTO REGISTER UH SELECT CONTENTS OF REGISTER LH SHIFTEO LEFT BY 4 BITS INTO REGISTER UH SELECT CONTENTS OF REGISTER LH SHIFTED LEFT BY 8 BIT INTO REGISTER UH SELECT CONTENTS OF REGISTER LH SHIFTED RIGHT BY 4 BITS INTO REGISTER UH SELECT CONTENTS OF REGISTER LH SHIFTED RIGHT BY 8 BITS INTO REGISTER UH SELECT CONTENTS OF REGISTER LM DIRECT INTO REGISTER M SELECT CONTENTS OF REGISTER LM CIRECT INTO REGISTER UM SELECT CONTENTS OF REGISTER LM DIRECT INTO REGISTER UO SELECT CONTENTS OF REGISTER LM SHIFTED LEFT BY 32 BITS INTO REGISTER UH SELECT CONTENTS OF REGISTER LM SHIFTED LEFT BY 8 BITS INTO REGISTER UM SELECT CONTENTS OF REGISTER LM SHIFTED RIGHT BY A BITS INTO REGISTER M SELECT CONTENTS OF REGISTER LM SHIFTED RIGHT BY 8 BITS INTO REGISTER UM SELECT BITS 9 TO 12 OF REGISTER LM DIRECT TO BITS 9 TO 12 OF REGISTER M SELECT CONTENTS OF REGISTER LO SHIFTED LEFT BY 1 BIT INTO REGISTER UO SELECT CONTENTS OF REGISTER LO SHIFTED LEFT BY A BITS INTO REGISTER UO SELECT CONTENTS OF REGISTER LQ SHIFTED LEFT BY 8 BITS INTO REGISTER UO SELECT CONTENTS OF BYTES TO 3 OF REGISTER LO SHIFTED RIGHT BY ONE BIT TO BYTES TO 3 OF REGISTER UQ SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 2?2 LQR4UQ LQR8UQ LS LSDUH LSOUS LSL8US LSR8US LT MDY1 MDY4 MDOINT MEPGATE MEPLATCH ML1Y4 ML2Y3 ML3Y3 ML4Y2 ML5Y2 ML6Y1 ML7Y1 SELECT CONTENTS OF REGISTER LQ SHIFTED RIGHT BY 4 BITS TO REGISTER UQ SELECT CONTENTS OF REGISTER LQ SHIFTED RIGHT BY 8 BITS TO REGISTER UQ LOSS OF SIGNIFICANCE SELECT CONTENTS OF REGISTER LS, DIRECT TO REGISTER UH SELECT CONTENTS OF REGISTER LS DIRECT TO REGISTER US SELECT CONTENTS OF REGISTER LS SHIFTED LEFT BY 8 BITS TO REGISTER US SELECT CONTENTS OF REGISTER LS SHIFTED RIGHT BY 8 BITS TO REGESTER US LESS THAN SELECT CONTENTS OF M OIRECT TO Yl SELECT CONTENTS OF M DIRECT TO Y4 GATE CONTENTS OF BITS 10 TO 12 OF REGISTER M TO DIVISOR INTERVAL SESECT GATE MULTIPLY-EXTENOED-PRECISION BITS LATCH MULTIPLY-EXTENDED-PRECISON BITS SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 1 BIT TO Y4 SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 1 BIT TO Y3 SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 3 BITS TO Y3 SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 4 BITS TO Y2 SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 5 BITS TO Y2 SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 6 BITS TO Yl SELECT CONTENTS OF REGISTER M SHIFTED LEFT BY 7 BITS TO Yl MPY ARITHMETIC ORDER MULTIPLY SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 273 MPYSTOP MPY7AI MPY5AI2 NDDL8DNDRL8 NDRL1EZ NDRL4 NDRL8EZ NORR8 NEGATE NEGR NEXTOIV NORMUO NTDNTR OV PDY4 PERR POLY POLYCO QASS QBDUQH RESCALEREM RESTODIV RETURNCVD SBYONE SCALFIXDDR SOB SDODMD MULTIPLICATION LOOP STOP CONTROL POINT MPY7 ADVANCE-IN CONTROL POINT MPY5 ADVANCE-IN 2. GATE CONTENTS OF COUNTER NDDL8 CIRECT TO COUNTER NDRL8 CONTENTS OF COUNTER NDRL1 EQUALS ZERO DIVISOR HAS BEEN SHIFTED LEFT ONCE BY FOUR BITS CONTENTS OF COUNTER NDRL8 EOUALS ZERO DIVISOR HAS BEEN SHIFTED RIGHT BY 8 BITS ONCE INPUT TO PROCEDURE NEGATE NEGATIVE REMAINDER ENTER DIVISICN LOOP AT ENTRY NEXTOIV FOR ANOTHER PASS NORMALIZE UQ GATE NUMBER TYPE BITS DIRECT TO REGISTER NTR OVERFLOW SELECT OUTPUT OF PROPAGATION LOGIC DIRECT TO Y4 PARITY ERROR ARITHMETIC ORDER POLY POLY OPERATION CONTINUED QUOTIENT ASSIMILATION GATE QUOTIENT BUFFER REGISTERS QM AND OS TO REGISTER UQ AND UH RESCALE REMAINDER RESTORING DIVISION RETURN TC CONTROL SEQUENCE CVD SET FLIP-FLOP BYONE SCALE FIXED-POINT DIVISOR SIGN DETERMINATION BYPASS SET SELECTOR FLIP-FLOP DODMD SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 27^ SD1DHD SD20MD SD3DMD SEADEUU SEBDEUM SETOECSIGN SETFLAGAI SETM640NE SETSIGN SETUQ030NE SETUQ330NE SETUQ33ZERO SETUQ470NE SEUUEZ SEUCTRDIR SEUDIFF SEULALLCNE SEULALLZERO SEULEQ14 SEULE08 SEUMEQ14 SEUMEZ SEUMZERO SEUUEZ SET SELECTOR FLIP-FLOP D1DMD SET SELECTOR FLIP-FLOP D2DMD SET SELECTOR FLIP-FLOP 030MO SET SELECTOR FLIP-FLOP EAOEUU SET SELECTOR FLIP-FLOP EBDEUM SET SELECTOR FLIP-FLOP DECSIGN CONTROL SEQUENCE SFBIN AOVANCE-IN (SET FLAGS CONTROL SUBSEQUENCE AOVANCE-IN) SET BIT 64 OF REGISTER M TO ONE STATE. SET SIGN (ADVANCE-IN SIGNAL TO PROCEDURE SUBSEQUENCE SETSIGN) SET BYTES TO 3 OF REGISTER UQ TO ALL •!• STATE SET BIT 33 OF REGISTER UQ TO •!• STATE SET BIT 33 OF REGISTER UQ TO •0« STATE SET BYTES 4 TO 7 OF REGISTER UQ TO ALL "1« STATE SET CONTENTS OF REGISTER EUU EQUAL TO ZERO IN EXCESS 64 REPRESENTATION SET FLIP-FLOP EUCTROIR (EUL COUNTER DIRECTION) SET FLIP-FLOP EUDIFF TO »1" STATE SET REGISTER EUL TO ALL ■!• STATE SET REGISTER EUL TO ALL 'O 1 STATE SET CONTENTS OF REGISTER EUL EQUAL TO 14 SET CONTENTS OF REGISTER EUL EQUAL TO 8 SET CONTENTS OF REGISTER EUM EQUAL TO 14 SET CONTENTS OF REGISTER EUM EQUAL TO ZERO IN EXCESS 64 REPRESENTATION SET BIT 1 OF REGISTER EUM TO «l f STATE SET CONTENTS OF REGISTER EUU EQUAL TO ZERO IN EXCESS 64 REPRESENTATION SEUUZERO SET BIT 1 OF REGISTER EUU TO •!• STATE SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 275 SFIX SG1CLG2G3G4 SG1G2G3G4 SICCCNTON SICCCNTUP SICCEQ7 SICCE08 SID SIGNACONEG1 SIGNAOSR SIGN8 SIGNBMPY SINJECTSIGN SLHL1UH SLHL4UH SLHL8UH SLHL4UH SLHR8UH SLMDM SLMDUM SLMDUO SLMDUQ03 SLMDUQ47 SLML32UH SLML8UM SLMR4M SHORT FIXED POINT SET SDS GATE SIGNALS Gl=»l»* G2=G3=G4=«0« SET SDS GATE SIGNELS G1=G2=G3=G4= • 1» SET ICC COUNTER DIRECTION FLIP-FLOP TO, DOWNWARD COUNTING STATE SET ICC COUNTER DIRECTION FLIP-FLOP TO UPWARD COUNTING STATE SET CONTENTS CF COUNTER ICC EQUAL TO 7 SET CONTENTS OF COUNTER ICC EQUAL TO 8 SET ILLEGAL DATA FLIP-FLOP ID GATE COMPLEMENT OF FLIP-FLOP SIGNA TO FLIP-FLOP NEG1 GATE CONTENTS OF FLIP-FLOP SIGNA TO FLIP-FLOP SR SIGN OF OPERAND B SIGN OF PERAND B DURING CONTROL SEQUENCE MPY (TEMPORARY STORAGE) SET FLIP-FLOP INJECTSIGN SET SELECTOR FLIP-FLOP LHL1UH TO •!• STATE SET SELECTOR FLIP-FLOP LHL4UH TO »1« STATE SET SELECTOR FLIP-FLOP LHL8UH TO "l 1 STATE SET SELECTOR FLIP-FLOP LHR4UH TO »1« STATE SET SELECTOR FLIP-FLOP LHR8UH TO •!■ STATE SET SELECTOR FLIP-FLOP LMDM TO »1" STATE SET SELECTOR FLIP-FLOP LMDUM TO "l 1 STATE SET SELECTOR FLIP-FLOP LMDUQ TO "l" STATE SET SELECTOR FLIP-FLOP LMDUQ03 TO ■!• STATE SET SELECTOR FLIP-FLOP LMDUQ47 TO »1" STATE SET SELECTOR FLIP-FLOP LML32UH TO 'l* STATE SET SELECTOR FLIP-FLOP LML8UM TO •!■ STATE SET SELECTOR FLIP-FLOP LMR4M TO ■!« STATE SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 276 SLMR8UM SLM9120M912 SLQL1UO SLQL4U0 SLQL8UQ SLQL8UQ SLQR1UQ03 SLQR4UQ SLQR8UQ SLSOUH SLSOUS SLSL8US SLSR8US SMOY1 SMDY4 SML1Y4 SML3Y3 SMYRECODON SND0L8UP SNDRLION SNDRL1UP SNDRL80N SNDRL8UP SNEGO SNEG003 SET SELECTOR FLIP-FLOP LMR8UM TO "l" STATE SET SELECTOR FLIP-FLOP LM9120M912 TO "1« STATE SET SELECTOR FLIP-FLOP LQL1UQ TO «1« STATE SET SELECTOR FLIP-FLOP LQL4UQ TO 'l* STATE SET SELECTOR FLIP-FLOP LQL8UQ TO ■!■ STATE SET SELECTOR FLIP-FLOP LQL8UQ TO "1' STATE SET SELECTOR FLIP-FLOP LQR1UQ03 TO • 1 • STATE SET SELECTOR FLIP-FLOP LQR4UQ TO "1" STATE SET SELECTOR FLIP-FLOP L0R8UQ TO •!• STATE SET SELECTOR FLIP-FLOP LSOUH TO "1« STATE SET SELECTOR FLIP-FLOP LSOUS TO »l f SATE SET SELECTOR FLIP FLOP LSL8US TO »!■ STATE SET SELECTOR FLIP-FLOP LSR8US TO »1« STATE SET SELECTOR FLIP-FLOP MOY1 TO »l f STATE SET SELECTOR FLIP-FLOP M0Y4 TO •!• STATE SET SELECTOR FLIP-FLOP ML1Y4 TO •!• STATE SET SELECTOR FLIP-FLOP ML3Y3 TO •!■ STATE SET CONTROL FLIP-FLOP MYRECOD(MULTI PLY RECODER) SET N0DL8 COUNTER DIRECTION FLIP-FLOP TO UPWARD COUNTING STATE SET NDRL1 COUNTER DIRECTION FLIP-FLOP TO DOWNWARD COUNTING STATE SET NDRL1 COUNTER DIRECTION FLIP-FLOP TO UPWARD COUNTING STATE SET NDRL8 COUNTER DIRECTION FLIP-FLOP TO DOWNWARD COUNTING STATE SET NDRL8 COUNTER DIRECTION FLIP-FLOP TO UPWARD COUNTING STATE SET SELECTOR FLIP-FLOP NEGO SET SELECTOR FLIP-FLOP NEG003 SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 277 SNEG047 SNEG1 SNEG2 SNEG4 SOV SPDY4 SQ8DUQH SRCDNEG1 SSIGNA SSCWORD SSR STENOY1 SUB SEULALLZERO SUHOM SUHDUS SUMDX1 SUQDMR SUQDUM SUQ330US33 SUQ330NE SUQ33ZERO SUQ470NE SUQ58DM6164 SUQ912R52UM SUSDS1 SUS9 SET SELECTOR FLIP-FLOP NEG047 SET SELECTOR FLIP-FLOP NEG1 SET SELECTOR FLIP-FLOP NEG2 SET SELECTOR FLIP-FLOP NEG4 SET OVERFLOW FLIP-FLOP OV SET SELECTOR FLIP-FLOP PDY4 SET SELECTOR FLIP-FLOP QBDUOH GATE COMPLEMENT OF FLIP-FLOP SR TO FLIP-FLOP NEG1 SET FLIP-FLOP SIGNA (SIGN OF OPERANC A) SET FLIP-FLOP SCWORD SET FLIP-FLOP SR (SIGN OF RESULT) SET SELECTOR FLIP-FLOP TENDY1 ARITHMETIC ORDER SUBTRACT SET ALL BITS OF EUL REGISTER TO , 0« STATE SET SELECTOR FLIP-FLOP UHDM SET SELECTOR FLIP-FLOP UHDUS SET GATING SIGNAL FLIP-FLOP UMDX1 SET GATING SIGNAL FLIP-FLOP UQDMR SET SELECTOR FLIP-FLOP UCDUM SET SELECTOR FLIP-FLOP U033DUS33 SET BIT 33 OF REGISTER UQ TO »1« STATE SET BIT 33 OF REGISTER UQ TO •0« STATE SET BIT 47 OF REGISTER UQ TO "1" STATE SET SELECTOR FLIP-FLOP UQ58DM6164 SET SELECTOR FLIP-FLOP UQ912R52UM SET GATING SIGNAL FLIP-FLOP USDS1 SET BIT 9 OF REGISTER US TO •!' STATE SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 278 TIO T4DLS UHOLH UHOM UHOUS UHDYl UQ1DUS1 U013DXT UQ330US33 UQ47DXT UQ58DM6164 UQ912R52UM UQ916EZ UREN V0UH3 V0UH13 VDUH47 VOUOO VDUQ13 VUDQ47 VIN3AI VIN3AO VIN4AI VIN5AI •TRANSFER INFORMATION OUT* TO EXCHANGE NET, PULSE GATE SDS4 OUTPUT T4 OIRECT INTO REGISTER LS GATE CONTENTS OF REGISTER UH OIRECT INTO REGISTER LH SELECT CONTENTS OF REGISTER UH DIRECT TO REGISTER M SELECT CONTENTS OF REGISTER UH DIRECT TO REGISTER US SELECT CONTENTS OF REGISTER UH DIRECT TO Yl SELECT BIT 1 OF UQ DIRECT TO BIT 1 OF US SELECT BYTES 1 TO 3 OF REGISTER UQ DIRECT TO OUTBUS XT SELECT BIT 33 OF REGISTER UQ DIRECT TO BIT 33 OF US SELECT BYTES 4 TO 7 OF REGISTER UQ DIRECT TO OUTBUS SELECT BITS 5 TO 8 OF REGISTER UQ DIRECT TO BITS 61 TO 64 OF REGISTER M SELECT BITS 9 TO 12 OF REGISTER UQ SHIFTED RIGHT BY 52 BITS TO REGISTER UM CONTENTS OF BITS 9 TO 16 OF REGISTER UQ EQUALS ZERO UNIT REGUESTS THE EXCHANGE NET SELECT BITS 1U TO 18 OF V-BUS INTO BYTE OF REGISTER UH SELECT IBTS 21-28,31-38 AND 41-48 OF V-BUS INTO BYTES I TO 3 OF REGISTER UH SELECT BITS 11-18,21-28,31-38,41-48 OF V-BUS TO BYTES 4 TO 7 OF REGISTER UH SELECT BITS 11-18 OF V-BUS TO BYTES OF REGISTER UQ SELECT BITS 21-28,31-38,41-48 TO BYTES 1 TO 3 OF REGISTER UQ SELECT BITS 11-18,21-28,31-38,41-48 OF V-BUS TO BYTES 4 TO 7 OF REGISTER UQ CONTROL POINT VIN3 AOVANCE-IN CONTROL POINT VIN3 ADVANCE-OUT CONTROL POINT VIN4 ADVANCE-IN CONTROL POINT VIN5 ADVANCE-IN SIGNAL NAME SIGNAL FUNCTIONAL DESCRIPTION 279 WAITNORMUQ XOUTAI XTDES ZERODIVND Z4DLM UHTUOWAIT UH916EZ UN UQOLO UQDMR UQDUM UOODXT SUBROUTINE NORMUO WAIT CONTROL SEQUENCE X-OUT AOVANCE-IN GATE EXITBUS XT CONTENTS DIRECT TO EXCHANGE NET ZERO DIVIOEND GATE SDS4 OUTPUT Z4 DIRECT INTO REGESTER LM SUBROUTINE UHTUO WAIT CONTENTS OF BITS 9 TO 12 OF REGISTER UH EQUALS ZERO UNDERFLOW GATE CONTENTS OF UQ DIRECT TO LQ GATE UQ DIRECT TO MULTIPLIER RECODER SELECT CONTENTS OF UQ DIRECT TO REGISTER UM SELECT CONTENTS OF BYTE OF REGISTER UQ TO OUTBUS XT 280 BIBLIOGRAPHY Atkins, D. E. "Illiac III Computer System Manual: Arithmetic Units," Volume 1, Department of Computer Science Report No. 366, University of Illinois at Urbana-Champaign, December 1969. Atkins, D. E. "Design of the Arithmetic Units of Illiac III: Use of Redundancy and Higher-Radix Methods," Department of Computer Science Report No. 333, University of Illinois at Urbana- Champaign, May 1969. Goyal, L. N. , Koo, P. L. and Atkins, D. E. "Arithmetic Unit of Illiac III: Simulation and Logical Design — Part II," Department of Computer Science Report No. Ul8, University of Illinois at Urbana-Champaign, November 1970 . Krabbe, S. P. "A Discussion of Illiac III Process or -Unit Communication via the Exchange Net," Department of Computer Science File No. 790, University of Illinois at Urbana-Champaign, March 1969 . Krabbe, S. P. "Illiac III Check-Out and Maintenance Manual: Arithmetic Unit 0," Department of Computer Science File No. 872, University of Illinois at Urbana-Champaign (in preparation). Martin, R. G. "Standardization of Control Point Realization," Department of Computer Science Report No. *i00 (M.S. Thesis), University of Illinois at Urbana-Champaign, May 1970. Nordmann, B. J. and Atkins, D. E. "Supplementary Material on Control Point Logic Design," classnotes for CS 29^+, Fall 1969-70, University of Illinois at Urbana-Champaign. 281 APPENDIX 282 A.O Introduction This section is a reproduction* of Section 3 entitled 'CONTROL POINT - A Building Block Approach 1 of DCS Report No. 1+00 by Mr. R. G. Martin. This report is a reproduction of his M. S. thesis entitled 'Standardization of Control Point Realization'. This section describes, in detail, the task stage and sequence stage and the timing stage of a basic Control Point and their corresponding logic design. Variants of the basic control point are also discussed. Reproduced with the author's permission. 283 A • CONTROL POINT - A BUILDING BLOCK APPROACH A.l Description Pseudo-asynchronous control is based on the concept that tasks be performed in controlled steps or in irregular time intervals dependent on the execution time of these tasks. This type of control has been implemented at Illinois by the use of logical circuits called control point . The control point originally developed as a modification of the Illiac II "speed indepen- dent" control circuits by Gilles, Robertson, and Swartwout (1961). Generally speaking, each control step is performed by one control point. In many cases, the control point may be used to implement several similar control steps from different parts of a sequence and will return to that part of the sequence from which it was called. The basic idea behind a control point is that it initiates some operation by turning on a given set of control lines. These control lines will remain on until either a certain length of time has passed, or a reply has been received indicating that the operation has been completed. As these control lines are turned off, an advance signal is initiated which will acti- vate the next control point. The use of control point , therefore , provides an ordered scheme for the assignment of specific tasks being performed in controlled steps. In other words, the control point renders to the logical designer a building block approach or technique in the design of pseudo-asynchronous control. The evolution of the control point design for Illiac III has been long and tortuous. The investigation and applications of several control 28U point configurations have been made by Atkins and Nordmann (1969). The con- trol point configuration presented in this paper, consists of two stages: a task stage and a timing stage. A. 1.1 Task Stage The function of the task stage is to perform certain operations on various hardware: i.e., gates are operated, flip-flops are set, counters in- cremented or other control points called. These operations may be conditional upon status conditions. Consider the block diagram of typical task stage logic as shown in Figure A. 1.1.1. The advance in the I ± is connected to an adjacent stage logic. When this line drops to "0", the memory element is set and the task logic is said to be primed. When A. returns to "l", the task activation signal , DO, becomes "0" provided that the enable line, EN, is at "1". The task stage logic is now said to have been initiated. The DO signal from the memory box is one input to the conditional task logic, while the other inputs to this logic are external conditions appropriate to that task stage. Typical examples of these conditions are the outputs of special condition detect logic at the output of certain registers, or the outputs of status flip-flops, etc. The DO signal also activates the timing stage which, after a select- able duration, causes the advance out line, A^, "bo go to "0". This action will reset the memory element, thus turning off the task element, and can be used to also prime and initiate the next succeeding task stage. Figure A. 1.1. 2 illustrated the most elementary. task stage configura- tion and an explanatory timing diagram. In this case the timing stage will consist of an internal timing model which will be explained later in this paper. 285 EXTERNAL CONDITIONS it A. DO *- CONDITIONAL TASK LOGIC El 3 1 ^- v MEMORY ELEMENT TIMING STAGE A / I 1 A ► ° — ^- TASIC TASK,. TASK n EXTERNAL REPLY INPUT TO NEXT TASK STAGE A = f (internal time delay or external reply signal) Figure A. 1.1.1. Block Diagram of Task Stage Logic TASK CONDITIONS 286 1 CONDITIONAL TASK LOGIC TASK LINES A TIMING DIAGRAM: A. 1 DO A Assume that EN = 1 and CC = 1 Figure A. 1.1. 2. Most Elementary Task Stage Configuration 287 DO Figure A. 1.1. 3. Multiple "Advance In" Input to Memory 'Element 288 No detailed logic is shown in the conditional task logic box since the configuration is highly variable from task stage to task stage. The most elementary configuration would be a direct connection of the DO (perhaps through an invertor or line driver) to the task lines. The enable input , EN, offers a facility for inhibiting the operation of the task stage. If this input is held at "0" , the control sequence will stop -when the memory element of the inhibited stage is initiated. As EN returns to "l" , the normal operation of DO will resume. This input may then be used to either inhibit a control sequence conditional upon an asynchronous signal or serve as a maintenance stop. A maintenance stop may be performed either manually as a function of a control panel switch, or automatically by the use of a diagnostic testing routine. The common-clear input , CC , provides a means by which the task stage memory element can be set to the "off" state. Typically the CC input of all the task stages of a routine(s) are connected together and "initialized" at the start of a specific control sequence. It may be found desirable in some instances that a task stage be initiated from more than one advance in line. Figure A .1.1.3 illustrates a method for implementing multiple advance in signals to a memory element. The A inputs are quiescently "l". When any one drops to "0", the memory element flip-flop is set such that@= "l". As long as any A. or the EN input is "0" the DO signal remains at "l" , but when they return to "l" DO" drops to activate the task logic. The duration of the A. •-• A. signals must be long 3 n enough to allow the memory flip-flops to set (i.e., compensate for the added propagation delay caused by the two additional NANDs). 289 A. 1.2 Timing Stage It is the function of this stage to provide a delay of the DO signal for a time period necessary to complete all the tasks of a given task stage. Associated with this time delay is the logic required for the genera- tion of a reply signal Ao used to reset the task memory flip-flop, which turns off the task lines , and drives the next sequence stage logic which primes and initiates the next task stage. In many cases this time delay is generated by an internal delay element which provides a timing model of the actual task. Figure A. 1.2.1 illustrates a timing stage configuration and an explanatory timing diagram. As DO goes to "0" ® , the output of NAND I, goes to "l". The advance out line, Aq , will be delayed from going to "0" by the amount of time required for the RC-network at the (B) input of NAND II to charge to the logical "l" thres- hold. When this threshold is reached, Aq drops to "0" causing the task memory to be reset and therefore DO will return to "l". The following design information on this circuit configuration was obtained by the use of basic circuit transformation techniques. A simplified model of NAND II and the equivalent circuits used in this analysis are shown in Figure A. 1.2. 2. The logic elements used in this design were 5^/7^ series TTL and the following assumptions have been made. V =5-0 volts cc V m _ = V/s\ = l.U volts (midpoint of uncertainty range , THRESHOLD <& nn fi) R = h K tt (value given in T.I. -TTL handbook) R = 8.2 K Q (determined empirically) C = 100 pfd. DO ® O-^ — r\ TIMING DIAGRAM: "*■ o 290 DO ® T' THRESHOLD DELAY Figure A. 1.2.1. Timing Stage Using Internal Delay Element 291 Using the Thevenin equivalent circuit, the timing model has been reduced to a low-pass RC-network where V TH " VS^T!^ " 5 = 3 - 36 T0ltS B H The delay time is related then to the equation for the charging of capacitor C V c =• V TH ( 1- e " t/(R th C) ) If we assume that V is initially zero and that the delay ends when V = threshold = l.k volts, then l.U = 3.36 (1 . e -t/2.69 x 10" 7 ) } t = (.538 x 2.69 x 10" 7 ) = 1^5 nS The recovery time or the time required to discharge C is determined solely by R p and C. The discharge time can then be expressed by the equation: V = V (e" t/R 2 C ) V C TH v ; If we assume that V is initially equal to V TH and that C is con- sidered to be discharged when V = .IV , then ^c o ^ ( -t/8.2 x 10" 7 ) , .336 = 3.36 (e ) t = (2.3 x 8.2 x 10" 7 ) = l885nS It can then be seen from the above calculation that approximately 13 delay times must elapse between the application of input pulses at ® to 292 V NAND II rt\- ®° — I® L. X NAND II is typically SNT^OON EQUIVALENT CIRCUIT THEVENIN'S EQUIVALENT + 5 UK i :> X TH AA/V- TH + V © *. = \n ^° V o = V TH (l-a t/R TH C ) Figure A. 1.2. 2 Timing Stage Equivalent Circuits 293 avoid interaction. If this constraint hinders circuit performance it may be greatly reduced by the addition of a diode as shown in Figure A. 1.2. 3. This diode, a USD25 is a HP2800 hot carrier device with a low forward drop and junction capacitance, is used to discharge C when @ goes to "0". With the addition of this diode, only 1.5 delay times are required between input pulses or the timing stage can be pulsed as soon as it has completed its delay function. Empirical tests have indicated a design center value for R_ of 8.2KS2 with upper and lower limits of 12K and 6.2K respectively. Using R = 8.2Kfi, the following was found to hold: Delay - 1.5nS/pFd. Variation of + .5v in V - + 15% Variation between IC packages - +_ 15% Variation due to R = 6.2K ->• 12K - Q% The delay time of the timing stage could also be a direct function of an external replay signal as has been shown in Figure A.I.2.U. In this case the RC-network has been replaced by the reply line, GO. Once again as in the previous example, as DO goes to "0", the output of NAND I goes to "l". The advance out line A will not go to "0" until GO has been set to "l". If GO were "l" as DO goes to "0", the delay time would then depend on the propagation time of NAND I and NAND II and the amount of time required for the task flip-flop to be reset by A q . The control point is then the combination of a task stage and a timing stage with the block diagram and circuit configuration being repre- sented in Figure A. 1.2. 5- ®/7 ® L. USD25 J 8.2K X Figure A. 1.2. 3 Delay Circuit with Diode to Enhance Recovery 29^ DO GO r ,® L. I> Figure A-1.2.U Timing Stage Using External Reply 295 A. 1 CC f — ► A A. l CC where C = f (time delay required) Figure A. 1.2. 5 Control Point Block Diagram and Circuit Configuration 296 A. 2 Sequence Stage Interspersed with the control points used to implement the asynchro- nous controlled steps is the sequence stage. The function of the stage is "basically one of selection or steering. That is, as a control point completes its specific task the sequence stage makes the decision as to which control point (s) to initiate next. The most elementary example of sequence stage logic is merely a wire connecting the Aq output of one control point to the A. input of the next control point. In the case where two or more control points are to he called con- currently, the sequence stage logic will he AND'ed as a function of Aq and external conditions. Figure A.2.1 illustrates an example of a two-way branch. The conditions, a and 3, determine where the Aq pulse from the previous control point is directed. It is important that these conditions are set prior to the arrival of the A Q pulse, therefore, it is advisable that a or 3 not he determined by the action of the control point which generates the A Q pulse which they steer. It should be noted that at least one condition must be true or else the A pulse is lost and the control sequence hangs-up i.e., if a = 3 = , an error exists. In many cases the conditional logic is designed such that a = 3 and this error situation is averted. The sequence stage may also be required to delay the continuation of control contingent upon an asynchronous wait condition. Since the arrival time of this signal is unknown, the circuit configuration of Figure 3.2.1 is not applicable. Figure A. 2. 2 and Figure A. 2. 3 illustrates methods of imple- menting this wait condition. 297 a, 3 ARE BRANCHING CONDITIONS A. 1 Figure A. 2.1 Two Way Branch Sequence Stage Logic 298 In Figure A. 2. 2 the wait signal is used to delay the action of con- trol point after it has been initiated. That is, DO will be inhibited from going to "0" until WAIT goes to "0", When the wait condition is satisfied, DO provides a means for keeping EN at "l" until the control point completes its normal operation. This same delay action to the control point operation could also be a function of a maintenance halt , MH, used for check-out and diagnostic procedures. In Figure A. 2. 3 the wait signal is used to delay the propagation of the A ' signal. The DO signal is then a function of both the timing stage and the wait condition. Here the DO line will drop to "0" and remain there (even though the timing stage is done) until WAIT goes to "0". The A ' signal will then terminate the operation of the control point and initiate the next stage logic . This same wait logic configuration may also be used to interlock two or more parallel, independent control chains. The design requirement here is to make the A signal to the next stage wait until all the parallel tasks are complete. Figure A.2.U illustrates an example of this interlocked control chains. The A line of last control point of each chain is delay until a reply from all the chains is received. It is assumed that when one control chain is activated, then so is the other, i.e., that eventually both replies will be generated. Another application of the wait logic , similar to that shown in Figure A. 2. 3, is where a control point is used to call some routine and will not advance control until the called routine has replied. For apparent reasons, this configuration has been named "calling control point" and is 299 DO © DO WAIT EN (if MH = o; Figure A. 2. 2 WAIT Condition Using EN Gate 300 ASSUME THAT EN = CC = 1 DO WAIT A • o Figure A. 2. 3 Wait Condition Using A Line 301 \< o" u° CM CM Oh CM O 1 'H O •r -4j ' ♦ " \ 1 o ■t 1 .H H Cm c_> H CM o •r «' ' f " 1 l< H CM 4 5 § H Si >H CO CO W o EH O S3 c_> U En W En O a ■H H O Jh -P El O u H 0) H CM bO •H o o H U CM bD •H Ix, U C_> 302 shown in Figure A. 2.5. The DO* line will go to "0" as the control point is initiated (i.e., DO goes to "0" and A is at "l" ) . After a specific delay- time, due to the timing stage, A Q goes to "0" causing DO' to return to "l" . This action of DO' may have been used to prime and initiate a control point in a routine. When this routine has completed its task, it replies and WAIT goes to "0". 303 CC ASSUME THAT EN = CC = 1 A. l DO DO' WAIT A ' o Figure A. 2. 5 "Calling Control Point" Circuit Configuration orm AEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFJC AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) AEC REPORT NO. C00-21l8-00Ul 2. TITLE ILLIAC III COMPUTER SYSTEM MANUAL: ARITHEMTIC UNITS — VOLUME 2 i. TYPE OF DOCUMENT (Check one): I3 a. Scientific and technical report |"~l b. Conference paper not to be published in a journal: Title of conference ___ Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) I RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): fxj a. AEC's normal announcement and distribution procedures may be followed. 3 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. ~2 c. Make no announcement or distrubution. i. REASON FOR RECOMMENDED RESTRICTIONS: i. SUBMITTED BY: NAME AND POSITION (Please print or type) Lakshmi N. Goyal Research Assistant Organization Department of Computer Science University of Illinois Urbana, Illinois 6l801 Signature /^4c^yvu i\J- M#v|,OL Date January 1973 FOR AEC USE ONLY AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: 1~~) a. AEC patent clearance has been granted by responsible AEC patent group. I I b. Report has been sent to responsible AEC patent group for clearance. I I c. Patent clearance not required. IBLIOGRAPHIC DATA HEET Title and Subtitle 1. Report No. UIUCDCS-R-72-551 ILLIAC III COMPUTER SYSTEM MANUAL: ARITHMETIC UNITS—VOLUME 2 3. Recipient's Accession No. 5- Report Date November 1972 Lakshmi N. Goyal 8. Performing Organization Rept. No. COO -21 18-0 041 Performing Organization Name and Address Department of Computer Science University of Illinois Urbana, Illinois 6l801 10. Project/Task/Work Unit No. 11. Contract /Grant No. US AEC AT (11-1) 2118 2. Sponsoring Organization Name and Address US AEC Chicago Operations Office 9800 South Cass Avenue Argonne, Illinois 13. Type of Report & Period Covered systems manual 14. 5. Supplementary Notes 6. Abstracts This report is the second volume of Illiac III computer system manual on arithmetic units. The first volume described the various arithmetic orders to be executed in the arithmetic unit and the internal statis description or in other words, the processing hardware of the Arithmetic Unit. This volume describes the control logic hardware and gives its operational description. This report assumes that the reader is familiar with previously published reports and documents regarding the arithmetic. 7. Key Words and Document Analysis. 17a. Descriptors strategy of control design control point flow charts control logic processing hardware interface point design arithmetic addition, subtraction multiplication, division, number conversion signed-digit arithmetic 7b. ldentif iers/Opcn-Ended Terms 17c. ( OSA I I Field/Group 18. Availability Statement availability unlimited 19. Security Class (This Report) ^CLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 318 22. Price ORM NTI3-1B ( 10-701 USCOMM-DC 40329-P7I oc-s a 9 \973