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UNIVERSITY OF ILLINOIS
GRADUATE COLLEGE
DIGITAL COMPUTER LABORATORY
INTERNAL REPORT NO, 5k
A DYNAMIC MAGNETIC CORE MEMORY
Bt
J. M. Vier
January J, 19 5*+
This work has been supported by
Contract N6ori-71 Task XXIV
United States Navy
OHR NR OkQ 09^
ABSTRACT
A method for utilizing rectangular hysteresis loop magnetic
cores in a magnetic core matrix memory is discussed . This method of operation
consists essentially in employing a single large unsquare matrix for the
memory for a digital computer. This matrix is operated with a three to one
selection ratio using previously known methods. By arranging the matrix
so that it is equal to the number of words in one dimension and the number
of digits in the other, very good ratios of selected to unselected signals
are obtained, even on extremely large matrices,, The lacing of the cores is
also considerably simplified by making special arrangements of the pickup
winding unnecessary due to the elimination of spurious unselected signals.
Two methods of operating such a matrix are discussed, One of
these is a very straightforward vacuum tube driven device which would be
considerably more expensive in tubes than the normal Williams system. The
second would make extensive use of a large magnetic matrix switch whose
proper realization would require that the magnetic switch have good current
regulation on the output with rather widely varying loads. It does, however,
offer a substantial saving in tubes and so is worthy of more careful in-
vestigation.
An estimate of the amount of power and equipment necessary to
obtain a tube driven 102^ word memory of ^0 binary digits per word is
presented.
The arrangement of the storage matrix and the utilization of the
large magnetic core matrix switch for word selection is believed to be an
original development.
A DYNAMIC MAGNETIC CORE MEMORY
I INTRODUCTION
With the advent of very thin tapewound steel cores and of ferrite
cores considerable work has been done in adapting these materials for use
in computers. Early efforts used the saturable properties of these materials
to perform logical operations. With the advent of the very square hysteresis
loop materials, a number of different memories were proposed and built. An
auxiliary magnetic memory was constructed by the Burroughs Corporation for
(1)
the ENIAC in which the necessary switching is done by germanium diodes..
Various sorts of magnetic shift registers were devised which are used as
(2)
memory devices such as those proposed by Wang, among others .
A suggestion for using magnetic cores as memory elements and employing
their nonlinearities to provide the necessary switching was proposed by
Forrester. This memory provides a nonvolatile type of storage with a short
access time. It also seems to provide a high degree of reliability, but
requires considerable driving current for all of the materials now available.
It is also necessary that the cores be very uniform in order to provide the
necessary switching properties.
II THE NORMAL MODE OF OPERATION OF MAGNETIC CORE MEMORIES
The operation of the magnetic cores in existing matrix memories
is illustrated in Figure 1. This is a drawing of the saturation hysteresis
loop of a typical ferrite magnetic core. Since H is related to the driving
current by a multiplying constant, a given value of current will furnish a
fixed H so the axis of abscissas might just as accurately be labelled in
terms of current. From the figure it is to be seen that applying H^/2 units
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of magnetomotive force will force a core, which is initially at the point
-B r , only out to the knee. H units will cause it to move to the positive
saturation curve. In similar fashion, -H /2 and -H cause the core which
is initially at +B to move to the positive B knee and to negative B res-
r s
pectively. Now, if the process of moving from one of the remanent points,
B , to the knee may be made reversible, a large number of H /2 pulses may
be applied to the core without affecting its stored information,, Further,
since a change in state may be brought about by applying two H /2 pulses
simultaneously, the core may be used both as a storage element and a two
input "and" circuit at the same time.
The operation of the magnetic matrix memory is illustrated in
Figure 2. Let each one of these cores have hysteresis loops like that shown
in Figure 1 and let them have a reversible minor loop from the knee back to
the remanent points . Now, if the I, of Figure 2 corresponds to the H of
Figure 1, applying I-./2 to one driving line in each dimension yields a total
of I, linking the intersection core, namely number 5 in this drawing. This
will be sufficient to move 5 to the positive saturation region regardless
of its former state, In the process, no other core is disturbed by more than
I,/2 so the signal induced in the pickup winding will principally result from
the information stored at the intersection core. If core 5 was in the -B
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state, a relatively large flux change will take place when I is applied and
a correspondingly large voltage will be induced in the pickup windings If
core 5 was in the +B state, the output signal will be relatively small.
These two states may then be distinguished at the output. Since, in any case,
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core 5 is on the positive saturation curve after the above interrogation,
■writing may he accomplished by reversing the currents I /2. To leave the core
at the +B point, only one dimension need be activated, the other being in-
active., To return to the -B state, both lines may be fed with -I„/2. Of
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course, in the writing process it would be possible to prevent activation
of either line in the case of leaving the core in the -f-B state, but this
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usually involves a prohibitively large amount of circuitry.
Only two very extensive core memories of this type have been built „
One of these is at the Massachusetts Institute of Technology being used on the
Whirlwind computer and the other is in the laboratories of the Radio Corporation
(h) (5)
of America. " This latter memory is a 10,000 bit, single plane device.
The MIT memory is driven by vacuum tube drivers. Reading is
accomplished as outlined above. Writing of information is done by always
activating both of the -I,/2 drives and then inhibiting writing with a +1, /2
current through all of the cores of the plane if it is desired to remain in
the +B state. In this memory there are as many planes as there are digits
in the normal word plus one parity check plane. All planes have their selection
lines driven in series by the common driving tubes. One inhibition winding,
called a Z axis winding, exists for each digit plane.
The RCA memory employs matrix switch drivers for the selection lines
and writes by manipulating these driving matrices. This memory is particularly
significant in that the 10,000 core plane is much larger than any plane
attempted elsewhere.
The difficulties which arise in actual practice stem principally
A-
from the fact that the hysteresis loops of these cores are not rectangular .
The presence of a slope which is not zero from the remanent state, B , to
the knee of the curve causes spurious signals to appear in the pickup winding
due to the change in flux associated with this slope. Thus, as the size of
the matrix increases, the number of half selected cores on the selection
lines increases until the sum of the half selected signals from the cores
on the selection lines becomes large with respect to the contribution from
the selected core,, This condition is reached in the 1.0,000 bit plane and
the amplitude signal to noise ratio is less than one. This difficulty is
reduced by integrating the output signals. This integral is a measure of
the net flux change linking the pickup winding. Since, with perfectly re-
versible half selected signals, all of these unwanted signals would integrate
to 0, the remaining signal would be the desired one. Eventually this integra-
tion process fails since the half selected signals are not perfectly reversible
with merely a traverse from the remanent point, B , to the knee of the curve
and return. Thus a practical limit is placed on the size of a given plane
if the heretofore used method is to be employed. It is with this aspect of
the problem that this report deals .
Ill A PROPOSED METHOD OF OPERATION
In order to reduce or eliminate the effect of the half selected
core contributions to the output signal, a different method of operation is
proposed. It has been shown that it is also possible to obtain a 3 to 1
selection ratio by applying suitable signals. The method for accomplishing
this is illustrated in Figure 3. If currents are applied to the various
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selection lines as shown, only the core at the intersection of the I,/3 and
+21, /3 lines will be linked by a full I,. In the figure this is core number
5. The remainder of the cores will have only +I,/3 linking them and so are
disturbed by only that amount. Obviously, reversing all of the currents
provides a means of reversing the state of a given core and so may be used
for writing back into the core. This mode of operation will be used to im-
prove the selected to unselected drive ratio. This added margin of safety
over the two to one ratio may be used to allow looser tolerances on core selection,
to increase the speed of operation or merely to insure a larger margin of
safety. It is felt that the latter is the best use to which this margin may
be put.
A further piece of information is available from Figure 3» That is
that one may control whether the intersection core turns over or not when the
21, /3 current is applied merely by setting the other dimension to -I-./3 to
prevent turnover, or turning it to +I,/3 to allow turnover. This property
will be utilized in the method to be proposed.
A large unsquare rectangular matrix will be considered. Figure k-
is a schematic of the layout for a matrix which is 102^ x k-0 cores in size.
Let each column be associated with one of h-0 digit positions. Thus there is
a line of 102^ cores for each position in the case represented. We now have
a single large matrix. By using the information presented in previous para-
graphs an operating memory may be designed which will perform all of the
storage functions which a multiple plane set of matrices of the earlier types
will do. For the moment, the enormity of the task of performing the selection
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f unction on the 1024 rows will be ignored.
First, let it be assumed that it is desired to read out the contents
of some word. Call this word number n. The grids on the tubes driving the
n'th row are then raised from -50v to Ov. At the same time the right-hand
grid of all the column driving tubes is placed at volts, the opposite
grid being at -50 volts. Ordinarily this latter condition will already be
the case before the reading operation starts . After enough time elapses for
any disturbances which are caused by this process to die down in the amplifier,
the read gate is reduced from +25v to -25v. This allows the tube driving the
n'th row in the +1 direction to deliver +2I,/3 to the n'th row of cores .
This adds to the +I,/3 coming from each of the column drivers to move all of
the cores in the n'th row to the positive saturation region. The cores in
all the remaining rows are disturbed in a d.c. manner to the extent of +1 , /3»
Since this change occurred before the 21, /3 change, at the advent of the
latter current, only one core in each column is disturbed and so the signal
present on the pickup winding in each column is a very much undisturbed measure
of the contents of the n'th digit in that column, being large if a large flux
change occurred and small if only a small one resulted. From this fact it
is very important to observe that the number of rows may become very large
and disturbance-free operation will still result. Thus the plane capacity
restriction on previous modes of operation has been removed by this means .
The writing operation is always performed after the above reading
process takes place. Thus in the above case, all of the cores in the n'th
row are in the positive saturation state. To write information into this row,
-7-
again hold the n'th row tube grids at volts, the other row grids being at
-50 volts. At the same time, the left hand grids of all of the column driving
tubes are put to volts if a "1" is to be written in and -50 volts if a "0"
is to be inserted. The other grid of the column driving tubes is set at the
inverted state of its mate. The write gate is then moved from +25 volts to
-25 volts. At this time, all cores into which a "l" is to be written have
(-2I-./3 - I-./3) = -I-i linking them to cause the cores to move to the negative
saturation region. All those cores into which a "0" is to be written have
(-21^/3 + I-./3) = -I-. /3 linking them, thus leaving the cores in the positive
region. Writing has now been accomplished and the 21, /3 drive is removed.
As a matter of policy, all of the column drivers will always be
left delivering +I-./3 to the column. This means that no disturbance will
have to die out as a result of changing this drive when reading is to take
place and so reading will be correspondingly faster.
It should be stressed that at no time has any unselected core been
disturbed by more than I-i/3 during either reading or writing. Thus the
improved 3 to 1 selection ratio is maintained.
The effect on the stored information in all of the other memory
positions during the read write process is of interest also. If the information
to be written into the selected digit of the selected word is a "0", the
:ore must be left on the positive part of the hysteresis loop. The driver
:ommon to all the digits of a plane will initially be at +I,/3 in order to
perform the reading operation. After reading, in order to leave the selected
:ore at +B , nothing need be done to the +I,/3 drive to write a "0". Thus,
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the unselected cores in the digit line have remained at +I-./3 during the
entire process so no change is made in the stored information in any way.
On the other hand, if a "1" is to be written by returning the selected core
to the negative part of the hysteresis curve, the +I,/3 drive used in
reading must be reversed to give -I../3. Thus, all of the unselected cores
on this driving line move past the H = line to a point removed the same
distance back of the line as they were previously before it. Figure 5
illustrates approximate paths for cores initially in one or the other magnetic
state. The hysteresis curve is drawn as flux density B, versus driving
current, I. A core initially in the positive B state would start at point
b and move to b', following the arrows. In a similar way a core in the
negative B state would start at point a and move to a_[_. In both cases,
when the writing process is over, the drive will be returned immediately
to +I-./3 to await future orders to read. Thus in both cases, the unselected
cores will move back toward their initial states, a or b. On the saturation
curve, this may not occur exactly as indicated and the loop may not close
precisely, there being a net motion toward the I axis . However, if storage
Is to take place in the presence of extensive reading and writing, this
ninor loop must reach a terminal value which does not move closer and closer
to the I axis. Otherwise, the two stored states would become indistinguish-
able and no information would remain. Fortunately this is the case and
reversible loops are finally reached which are relatively far removed from
the I axis.
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IV DISCUSSION OF POSSIBLE SELECTION AND DRIVE TECHNIQUES
In the method which has been proposed, the most obvious difficulties
to be overcome are those of decoding an address for the selection of one of
many words and of proving sufficient current to drive the various words .
Let the driving problem be considered first. From the discussion of the
method of storage it is to be seen that each word will have to have a drive
capable of supplying +21, /3 pulses and one which is zero between these pulses.
It further is evident that in the read-write cycle which is traversed with
each access, the drive first supplies a +21 /3 pulse for reading. It then
always supplies a -21, /3 pulse for writing. Since these pulses are of the
same size and of opposite polarity, this suggests the possibility of a trans-
former coupled drive. The most obvious type of drive of this type is a
magnetic matrix switch since this switch may also supply the decoding function.
Thus, with a 1024 word memory, 102^ driving cores would be necessary. In
order to simplify the winding problem, a d.c. biased magnetic matrix switch
discussed in reference (5) may be used. This switch is a rectangular array
with two sets of orthogonal drive wires, a rectangular loop core being
linked by two drives at each intersection. All cores are d.c. biased by a
common winding far back on the saturation part of the hysteresis loops of the
cores. The sizes of the two orthogonal drive currents are such as to re-
quire the presence of two currents to drive the core to the opposite satura-
tion state. A single current only moves the core along the saturation curve
some distance. Since two currents will cause a large change in flux and one
only causes a very small change, we may consider all of the cores to be two
input "and" circuits. In order to select one core of the array, one may
-10-
deliver current to one wire in each dimension. The core at which the wires
carrying these currents intersect will deliver an output pulse. If it is
feasible to make this driver capable of delivering a current of + 21 /3 with-
out regard to the number of cores which turn over on the line which the
core drives, a 32 x 32 core matrix driver like this will suffice to provide
the drive for the storage cores. This problem has been considered to some
length but only relatively minor tests have been made. Using a steel core
driver, it was found possible to drive any number from to 10 ferrite cores
this way with no significant change in current amplitude. Tests on long
term stability of this current have not been conducted, but since this current
is a rather critical function of the wave shape of the currents driving the
magnetic selection matrix, it is felt that some automatic control would be
desirable to control this quantity.
In order to match the impedances of the tubes driving the selection
matrix to that of the storage matrix, multiple windings may be employed
on the selection matrix.
Viewed as a complete 102^ word selection system, an address of 10
binary digits is decoded electronically to two sets of 32. These then are
activated such that only one line of each set of 32 is activated. These two
signals control the flow of current through the vacuum tubes which drive the
selection matrix. A timing signal initiates the time at which these currents
start to flow. The two currents pass through two orthogonal drive wires
which intersect in the selected driving core. The turning over of this core
causes current to flow in the selected word line of the storage matrix.
-11-
In order to reverse the current in the wire through the selected storage
cores, the driving core is turned back over merely by removing the two
orthogonal selection currents and allowing the common d.c. bias current to
return the driving core to its original state. A four core version of such
a switch is shown in Figure 6.
As the above system has not been fully investigated and since it
seems quite difficult to control the output currents very accurately through
the matrix switch, another form of driver seems desirable if one is available
and feasible which may be more easily controlled. A form utilizing power
diodes has been envisioned which is still in the realm of practicality for
memories of present sizes. Before discussing the diode switch, a further
property of the proposed matrix should be discussed. Since it is possible
to pass all of the wires for a given digit line through the storage cores
on the same pass by bundling them together, it becomes completely practical
to consider multiple turn windings, within the limits of core size. By
passing five wires through all of the storage cores in the same pass, their
ends may be connected in series to form a pair of two turn windings which
may be used as linking windings for the push pull tube drivers in each plane .
The extra winding may be used as the pickup winding, The same possibility
exists in the other dimension and by passing four wires through in that
direction, another pair of two turn windings suitable for a tube drive is
available. With the standard size 0.050" inside diameter, 0„080" outside
diameter, it is possible to pass as many as fifteen #32 wires through the
available opening,, Thus it is fairly simple to pass nine wires through
the core. This information will be utilized in the proposed diode switch.
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Figure 7 is a schematic of a method which may be used to perform
the selection using rectifier diodes. For simplicity, only a four position
model is shown. There are two such matrices, one for reading and one for
writing. The upper tubes are only present once in the array since it is
necessary to supply current only to either the read or write tubes and not
both at any one time. The tubes at the side are repeated, one set for
reading, one for writing. There are actually two times as many diodes as
those shown, one set for reading, one for writing. The storage cores are
in series with the diode plate leads. The read wires link the storage cores
in a direction opposite to that of the write wires. The operation of the
switch may be understood by observing the conditions necessary for current
to pass through a given diode and consequently through a set of cores in
series with that diode. These are that its plate be pulled positive and its
cathode simultaneously be pulled negative. This can occur only if the row
driving tube whose plate is connected to the cathode of the diode is in the
conducting state and if the plate of the diode is held up by its column
driving tube. With signals applied as shown in Figure 7> only one diode
will conduct when one row and one column is activated, namely that diode
at the intersection point. The time of application of the signal is determined
by the time at which the gate voltage lowers to -25 volts from +25 volts.
For the 102^ word memory which was previously indicated, it is
evident that 20*4-8 diodes or 102 1 ! double diodes would be necessary to per-
form the switching function. This is excessive since the filament power
alone would be quite large. Using tubes capable of supplying the currents
needed, about 1000 amperes would be required. The dc* requirements are
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rather small in any case since only two current supplies are needed. In
order to materially reduce the number of tubes, we may employ a slightly
different selection scheme. Suppose we had a memory with 256 words of 160
binary digits each. The same memory capacity results since (256) (l60) =
(102*0 (k0) . By associating four of the 256 digit columns with each of
the *+0 memory positions, we may obtain a 102*+ word memory, each word of
1+0 binary digits. Thus 256 double diodes will exist as word drivers. Each
of these will select four words of *+0 digits each. As we are interested
in but one of these four words, it is possible to unselect three of them.
This may be done by a current to all of the unselected column lines equal
to I-|/3 in magnitude and of opposite polarity to the 21, /3 word selection
drive. This will require more tubes at each digit position, but the
number added is far smaller than the savings in diodes achieved by its use.
If the added tubes are counted it is found that each memory position has
had 5 power tubes added per position plus two small double diodes. This
is a total of only 200 added power tubes plus 80 small double tubes. This
reduces a.c. power requirements considerably and makes the net number of
tubes much smaller. It also reduces the decoding problem associated with
driving the diode word selection matrix.
In order to achieve the above reduction, another simplification
in the driving of the unselected digit columns is desirable. Since all of
the cores always have either +I-./3 °r ~^i/3 flowing through them, common
drivers may be employed for several memory positions. These drivers are
always of opposite polarity to the 21.. /3 drives in such a manner that
automatic rejection of all reading and writing is achieved on three of four
-14-
columns of every position. Then the selected line is adjusted to the proper
value in the chassis position by adding a current of +21 /3 to inhibit writing
in the selected column when writing of a "0" is required. This process is
illustrated for a single set of four lines in Figure 8. Only three cores
per line are shown. By using the common line driving tubes, single turn
windings may be utilized to make less net winding necessary. Since corresponding
columns in several memory positions are driven in series, a better impedance
match to the driving tubes is obtained due to the large number of cores in
series with the plate leads .
At the present time, an effort appears to be being made to standardize
storage cores which are made of ferrite materials at the 0.050" I.D., 0.080"
O.D., 0.025" ht size. Square loop materials are also available which vary
in their current requirements with the above core size. One type requires
about 820 ma turns to cause a change in state. It changes in one microsecond
and delivers unloaded output pulses of about 100 mv per turn. A second type
requires only 520 ma turns, changes in two microseconds and yields 50 mv per
turn. A third type requires 350 ma turns, changes in five microseconds and
yields 25 mv per turn. It is felt that the second type is a convenient com-
promise of speed with current requirements. Using this material with the core,
the diode selection matrix may be made using 6AX5 full wave rectifier tubes.
Using two turn windings, the tube would be required to supply about 175 ma pulses
with a low duty cycle. This is well within the peak rating of 375 ma. The
type 6CD6 may be used in constructing drivers for the diode matrix, in common
column drivers and in the individual chassis for inserting information to be
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written. Total d.c. current requirements for driving the cores necessary
to provide a memory with the properties of the present Illiac memory would
be about 7-9 amperes. Most of this current would flow from the +150 volt supply
to the -300 volt supply. Considerable additional current would be required
for amplifiers and switching circuits, probably on the order of that now
necessary for the Williams memory on the Illiac. The filament requirements
are equal to those for the Williams memory plus about 850 amperes at 6.3
volts.
V SUMMARY AND CONCLUSIONS
It is possible to construct a large unsquare magnetic core matrix
memory which appears to have relatively better stability than other proposed
and constructed core memories and promises long term trouble-free operation.
Two methods of drive for this matrix have been considered. One uses magnetic
cores to a considerable extent as switches and drivers and presents a current
regulation problem as yet not properly investigated. The second method
utilizes a direct vacuum tube drive which probably is simpler and more reliable
in principle, but which requires more tubes and driving current.
It is proposed that both of these methods of operation be investiga-
ted further and that additional test apparatus be constructed for the convenient
testing of magnetic cores .
JMW/nrh
January 7> 195^
(1) Auerbach, Isaac L., "Fast Acting Digital Memory Systems",
Electrical Manufacturing, pp. 105-106; October 1953-
(2) Wang, An, "Magnetic Delay Line Storage", Proc. IRE, Vol. 39,
pp. ^01-^07; April 1951.
(3) Forrester, Jay W., "Digital Information Storage in Three
Dimensions Using Magnetic Cores", Project Whirlwind Report
R-I87. (May 16, 1950) MIT Servomechanisms Laboratory.
(k) Papian, William N., "A Coincident Current Magnetic Memory
Cell for the Storage of Digital Information", Proc. IRE,
Vol. 40, pp. V75-U78; April 1952.
(5) Rajchman, Jan A., "A Myriabit Magnetic-Core Matrix Memory",
Proc. IRE, Vol. 41, pp. 1407-1421; October 1953-
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