Digitized by the Internet Archive in 2013 http://archive.org/details/designofirredund896yehc CENTRAL CIRCULATION BOOKSTACKS The person charging this material is re- sponsible for its renewal or its return to the library from which it was borrowed on or before the Latest Date stamped below. You may be charged a minimum fee of $75.00 for each lost book. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. TO RENEW CALL TELEPHONE CENTER, 333-8400 UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN JUN 1 8 1936 SEP 2 3 jog? JUN 3 1997 When renewing by phone, write new due date below previous due date. L162 uiucDcs-R-77-896 September 1977 ;/c2 // UILU-ENG 77 1750 DESIGN OF IRREDUNDANT MULTIPLE-LEVEL MOS NETWORKS FOR MULTIPLE -OUTPUT AND INCOMPLETELY SPECIFIED FUNCTIONS by Chi -Chung Yeh MBMM DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHA. UIUCDCS-R-77-896 DESIGN OF IRREDUNDANT MULTIPLE-LEVEL MOS NETWORKS FOR MULTIPLE- OUTPUT AND INCOMPLETELY SPECIFIED FUNCTIONS by Chi -Chung Yeh September 1977 Department of Computer Science University of Illinois at Urban a- Champaign Urbana, Illinois This work was supported in part by the National Science Foundation under Grant No. MCS77-097Mj- and was submitted in partial fulfillment for the degree of Master of Science in Computer Science, 1977- Ill ACKNOWLEDGEMENT The author is greatly grateful to Professor Saburo Muroga for his enthusiastic guidance and encouragement during the preparation of this thesis, and particularly for his careful reading and valuable suggestions of the original manuscript. The author also wishes to thank K. C. Hu for his helpful guidance and discussion. IV TABLE OF CONTENTS CHAPTER Page 1. INTRODUCTION 1 2. THEORETICAL BACKGROUND k 3. PROCEDURE DIMN 33 3.1 Internal Data Representation 36 3 . 2 General Organization of Program DIMN k-2 3.3 Descriptions about Subroutines h5 k. INPUT DATA SETUP 62 k. 1 Input Data Card Format 62 k. 2 Restriction on Problem Size 68 5. OUTPUT OF PROCEDURE DIMN 75 5.1 Output Format 75 5.2 Networks Obtained by Program DIMN ■ 80 6. CONCLUSION Qk REFERENCES 85 APPENDICES A - Networks Obtained by Program DIMN 86 B - Program Listing 103 1. INTRODUCTION The recent progress in integrated circuit technology has been improving the main drawback of MOS devices, slow speed, and the MOS logic circuits have become one of the most important logic families for digital systems. MOS logic circuits have many advantages over bipolar devices such as high packing density, lower power consumption, simple production processes, etc. Since an MOS cell can theoretically realize an arbitrary negative function, it is generally referred to as a negative gate . Several algorithms for the synthesis of negative gate networks have been developed. An algorithm for designing two-level networks with a minimal number of negative gates was first derived by T. Ibaraki and S. Muroga [1]. The synthesis of multi-level networks with minimum numbers of negative gates was introduced by T. Nakamura, N. Tokura, and T. Kasami [2] based on a general structure of a feed-forward negative gate network. A similar approach to design multi- level or two- level networks with a minimal number of negative gates was independently devised by T. K. Liu [3]. Although these algorithms do guarantee the minimality of the number of negative gates, they consider neither the number of connections nor the complexity in each negative gate. Thus a network designed by the above algorithms may contain redundant con- nections or driver MOSFET's. Recently, a new algorithm named DM (D_esign of Irredundant MOS Network), which finds irredundant multi-level MOS networks with a minimum number of negative gates for a given set of functions, was introduced by H. C. Lai [k]. An MOS network is irredundant if any driver MOSFET in the network is removed (by short-circuiting or open- circuiting the drain and source terminals of that MOSFET, as we dicuss later), then the network will not realize the original network output function any more. Lai's algorithm for designing irredundant multi-level MOS networks with a minimum number of negative gates contains Algorithm DIMN and Modified Algorithm DIMN. Algorithm DIMN (i.e., the simplest case of Lai's algorithm) is to design irredundant MOS networks with minimum number of negative gates for a completely specified single-output function. This Algorithm DIMN is modified for designing an irredundant MOS network for a set of completely specified output functions and is referred to as the Modified Algorithm DIMN. Algorithm DIMN and Modified Algorithm DIMN can easily be extended to the cases of an incompletely specified single- output function and a set of incompletely specified output functions, respectively. For multiple- output functions, two different MOS network configurations can be obtained by Lai's algorithm, that is, the networks with all the output functions restricted to the last level and the networks with all the output functions restricted to the last m levels, where m is the number of output functions. Lai's algorithm except the case where the output functions restricted to the last level was implemented with a FORTRAN program by K. Yamamoto [5]- This paper describes a newly developed program which combines the implementation of the algorithm for realizing the networks with all the output functions restricted to the last level with Yamamoto' s program. This program which is named program DIMN covers all the algorithms introduced in Lai's paper and has the capability to realize networks for any single- output or multiple -output, completely or incompletely specified function. The contents of this thesis are introduced below. Chapter 2 reviews Lai ■ s algorithm (Algorithm DIMN and Modified Algorithm DIMN). Chapter 3 discussed Yamamoto's program as well as the modifications of Yamamoto's program in detail. Chapter k explains how to prepare the input format for using the program and the restriction on the problem size that program DIMN can handle. Chapter 5 describes the output format of program DIMN. It also compares the results obtained by- program DIMN under the conditions that the output functions are realized at the last level, with the results under the conditions that the output functions are realized at the last m levels. Finally, the networks obtained for several three and four variable functions and a complete listing of FORTRAN program DIMN are given in Appendices A and B, respectively. 2. THEORETICAL BACKGROUND The power consumed in a static MOS network is approximately proportional to the number of MOS cells that the network has. Furthermore, an MOS network with fewer MOS cells tends to contain fewer connections or intercell connections than a network which has more cells. Therefore, the minimization of the number of MOS cells in MOS networks appears to be most important objective in designing most compact MOS networks [6]. The methods for designing negative gate networks with minimum number of negative gates which have been developed before Lai contain the following three steps. Step 1 : Find the minimum number of MOS cells required to realize the given functions. Step 2 : Obtain a function for each MOS cell. Step 3 ^ Design internal MOS cell configuration for each function obtained in Step 2. Since the design of each cell is done in Step 3 separately from Step 1 and 2 (i.e., there is no interplay between these steps), each cell may become unnecessarily complex and the network designed may contain many redundant connections (MOSFET's). The aim of Lai's algorithm is to design an irredundant MOS network with a minimum number of cells. Instead of applying the above steps once, Lai's algorithm applies Step 2 and Step 3 iteratively. In Step 2 a function is obtained such that it contains as many don't care's as possible, then in Step 3? an irredundant MOS cell configuration is designed by utilizing these don't care's to the maximum extent. In order to facilitate a review of Lai's algorithm, let us introduce the following definitions and terminologies. Negative Function A negative function is a switching function which has a disjunctive form consisting of complemented variables only. For example, function f = xx v x x is a negative function and function f = x x p x v- x x is not a negative function. Negative Gate A negative gate is a logic gate which can realize a negative function. N-Cube This is a lattice which represents the switching functions with n external input variables. There are 2 vertices in an N-cube and each vertex corresponds to an input vector of the functions. Vertices with same weight (number of ones in an input vector assigned to the vertex) are in the same level. Every pair of vertices is connected by an edge if their corresponding input vectors differ in one bit position only. Labeled N-Cube An N-cube is referred to as a labeled N-cube with respect to functions f, ,...,f When a binary integer, m m-i L(A) = i(A;f_,...,f ) = Z f.(A) 2 \ * v ' 1' ' m . _ i i=l is attached to each vertex A of N-cube as a label. An example of a labeled 3-cube for one "bit full adder (N = 3> f-, = carry = x x v x -i x o v x p x , f p = sum = x,XpX„ v x n x p x n/ xxx ^ x,x x ) is shown in Fig. 2.1. Fig. 2.1 Labeled 3-cube for one bit full adder \ I , = C — X, X_ \/ X. X_ v X^jX_ , I ,_> = S = X-. x,_x^ \/ X, x o x o v x -i X p X o v X "l X p X o ' * Directed Edge When two vectors A = (a...... a ) and B = (b n ,...,b ) are given such I 5 ' n v 1' ' n ° that a. > b. for every i, this is denoted with A > B. If a. >b. furthermore l—i J ' — 11 holds with some i, this is denoted with A>B. The edge between vertices A and B in an N - cube is directed from A to B if A>B and is denoted by A B. Inverse Edge A directed edge A B is said to be an inverse edge of a labeled N-cube if and only if £(A;f v ... > f m ) > ^(B;f 1? ...,f m ) For example, every directed edge in Fig. 2.1 is an inverse edge. A generalized form of a loop-free network consisting of R negative gates is shown in Fig. 2.2, where R is the number of negative gates (MOS cells) required to realize the function f, x..,...,x are n external input variables, and g. is the i-th gate counting from the left for i = 1,...,R with g being the output gate. Let u.(x..,...,x ) be the function realized by gate g. with respect to the external input variables x.,...,x . The values of u. for combinations of inputs x n ,...,x will be called the i ^ 1 J ' n components of u.. Since every gate is a negative gate, u. is negative with respect to the inputs x , ...,x , u,,...,u. 1 of g. and is an incompletely specified negative function of n + i - 1 variables. Our design objective is to find a negative gate network with a minimum number of negative gates. When the number of gates is minimized, R will be referred to as R . Negative Function Sequence In the generalized form of the loop-free network in Fig. 2.2, the sequence of ordered negative functions u , . . . ,u_ is called a negative function sequence of length R for function f and is denoted by NFS(R,f) = (u, ,...,u_). Here, Up represents the output of the network, i.e., u_ = f. Partially Specified Negative Function Sequence A partially specified negative function sequence of length R and degree i for a function f is a sequence of R negative functions denoted • a/ \/ XL SL by NFS (R,f) = (u^ . . . i\,U- ±+1 > . . . ,u R _ 1 ,u R ) such that v. ±+1> . . . jU^ ^ e -X -X- unspecified functions (i.e., all components of u. _,..., u__, are don't n "H = f Fig. 2.2 Generalized form of a loop-free network consisting of R negative gates. cares) and u.. , . . . ,u. are completely specified functions of x, , . . . jX... Here, (u, , ...,u.) is an NFS of length i. In particular, NFS (R,f) = ■Jfr -x- (u , ...,u^ ,il) where superscript o means that no function except u^ = f is specified and all components of u. are don't cares. An NFS(R,f) can be obtained by assigning O's and l's to those don't cares of a feasible partially specified NFS (R,f). This is called a completion of NFS 1 (R,f). A completion of NFS 1 (R,f) is called feasible if the resulting labeled N-cube has no inverse edge. A partially specified NFS (R,f) is feasible if there exists at least one feasible completion of NFS 1 (R,f); otherwise NFS 1 (R,f) is infeasible . Algorithm CMNL : (Conditional Mnlmum labeling) This algorithm obtains a conditional minimum labeling, NFS (R„,f) = (u, ,...,u. _ ,ti. , . . . ,Ud -|?f)j based on a given feasible NFS (R_p,f) = -X- -X- (u.. , . . . ,u._ ,u. , . . . ,u_ ,jf) for a function f. (Notice the underline.) The NFS 1 " (R f ,f) is a completion of NFS 1_1 (R ,f) such that the label ^(A;u , ...,u. _ ,u. , . . . ,« ,f) = L ' (A) assigned for each vertex A in the corresponding N-cube has the minimum value among all feasible completions of NFS 1 " (R f ,f). f . i-1 R -k Step 1 Assign as L ' (i) the value Z 2 ^K^ + f ( I )> "where I k=l represents the top vertex in the N-cube. Step 2 When L ' (A) is assigned to each vertex A of weight w (l < w < n) in the N-cube, assign as L ' " (B) to each vertex B of weight ' ° mn w - 1 the smallest binary integer satisfying the following three conditions: 10 (a) The k-th most significant bit of L ' " (B) is u. (B) for (b) The least significant bit of L ' 1-1 (B) is f(B); (c) L ' " (B) > L ' (A) for every directed edge AB terminating at B. Step 3 Repeat Step 2 until L ' " (0) is assigned, -where denotes the bottom vertex in the corresponding N-cube. Step k The k-th most significant bit of L ' (A) is denoted by ^.(A) for k = i,...,R -1 and the completion of NFS 1 " (R f ,l), NFS 1 " (R f) = (u.,...,u. ,u.,...,u^ -,,f), has been obtained. 1 X-X — X — n^-X Algorithm CMKL : (Conditional Maximum _Labeling) This algorithm obtains a conditional maximum labeling, NFS (R-jf) = (u,, . . . ,u._ 1 ,u. , . . . ,u_ ,,f), for a given feasible NFS " (R„ ,f ) = (u,, . . . , * * \ ^ i-1/ u. ,u. , . . . ,u_ ,,f), The NFS (R , f) is a complete specification of NFS 1_1 (R f ,f) such that the label i(A;u x , . . . ,vl ± . 3 u ± , . . .,Ug _ ± ,t) = L^ 1_1 (A) assigned to each vertex A in the corresponding N-cube takes the maximum value among all feasible completions of NFS " (R,,,f). f , , i-1 R.-k R f -1 R -k Step 1 Assign as L ' " (0) the value Z 2 u. (0) + Z 2 + f(0) mx . k. , k=l k=x Step 2 When L ' (A) is assigned to each vertex A of weight w (0 < w < n-l) in N-cube, assign as L ' (B) to each vertex B of weight w+1 the mx largest binary integer satisfying the following three conditions: (a) The k-th most significant bit of L jl " (B) is u, (B) for k = 1, mx J£ ...,i-l; 11 (b) The least significant bit of L f,1-1 (B) is f(B); (c) L ' (B)f )-,. The corresponding MOS network for both NFS(3,f)'s is shown in (s). Similarly, from (o), the algorithm obtains NFS 1 (3,f) , NFS 1 (3,f)o 5 and NFS 1 (3,f)^ = NFS(3,f)o? as shown in (p), (q), and (r), respectively. The MOS network corresponding to NFS(3,f)o is shown in (t). As observed from the above example, given a NFS " (R ,f), sequences NFS 1 " (R f ,f), NFS 1_1 (R ,f), and NFS 1 " 1 (R f ,f) are uniquely determined in Step 2, 3, and i* of Algorithm DIMN, respectively. On the other hand, Step 5 may obtain more than one irredundant MOS cell configuration for a given u. . Ik (a) C.({) for f = xxv x,x . (b) NFS'O.f) - (u x , u 2 , f), (c) NFS"(3,f) = (0 r u 2 , f), (d) KFS°(3,f) - (Jfj.-u*. f). 1O0 (S 1 (3,f) 2 = (x 2 , u 2 . f) (n) NFS (3.f) 2 - NFS(3,f) 2 - (Xj.Xj.f). 110 100 (o) NFS (3,f) * (k ,u 2 ,f) obtained from (d). (p) NFS (3,f)- = (x "u , f ) . 110 100 />. 1 (<]) NFS (3,f) 3 - (r. v ? , f), (r) NF'S (3.0- 3 - NFS(3,f) - (x^. f, f) Fig. 2.3 (Continued) 17 gj(g 2 ) Q 8 2 (g x ) O It __ _T -of (s) Irredundant MOS network corresponding to NFS(3,f)'s in (i) and (n) 9 g- •of (t) Irredundant MOS network corresponding to NFS(3,f)_ in (r) . Fig. 2.3 (Continued) 18 Another point to be noted is that the exhaustion of all alternatives in Step 5 may not give all possible irredundant MOS networks for the given func- tion. If we are only interested in obtaining one irredundant MOS network for f, any one of NFS 1 " (R^f) obtained in Step 5 of Algorithm DIMN is a solution. No matter which particular irredundant MOS cell configuration is chosen, the designed MOS network will be irredundant. In the multiple- output function case, there are two algorithms for designing irredundant MOS networks for a given set of functions. One algorithm is for the case where given set of functions are restricted to be realized at the last m levels, where m is the number of output functions; the other algorithm is for the case where all output functions are restricted to be realized at the last level (in other words, any negative gate which realizes, an output function is not allowed to feed other negative gates in the network). Only the latter case will be discussed below since the former case is discussed in [5]. The generalized form of a network in which functions f .,,..., f are to 1' ' m realized at the last level is shown in Fig. 2.k, where R - r + m and negative gates g , ..., g realize the given functions f , ...,f , respectively. Let us consider the subnetwork consisting of gates g,,...,g ,g -, • This subnetwork is in the generalized form of networks consisting of r + 1 negative gates shown in Fig. 2.2. Therefore, the sequence of functions (u,,...,u ,f, ) constitutes a negative function sequence of length r + 1, i.e., NFS(r+l,f, ). Similarly, the sequence of functions (u, ,...,u ,f.) is also a NFS(r+l,f . ) , for i = 2, . . . ,m. For convenience, let NFS(r;f , . . . ,f ) = (u, , . . . ,u ; f,,...,f ) be a negative function sequence corresponding to the network in 19 C^> * ! Fig. 2.k Generalized form of a network which consists of R = r+m negative gates with all m output gates realized in the output level. 20 the form of Fig. 2.k and i(A;u.. , . . . ,u ;f_, . . . ,f _) be the label assigned to each vertex A in the N-cube. It should be noted that the label consists of two parts: (u. , . . . ,u ) and (f _,..., f ). (u n ,...,u ) is considered as a r \ 2_> T 1' ' m 1 r binary interger of r bits and (f , ...,f ) is considered as a vector of m bits. The relationships between two labels in vertices A and B are defined below. (1) &(A;u v . i . s n T ;f l9 ... i t m ) = ^(B;^, . . . ,V f l' . . . ,f m ) if and only if u. (A) = u. (B) for i = 1, . . . ,r and f . (a) = f . (B) for i = 1, . . . ,m; (2) £ (A;^,..., u^j f .,_,..., f m ) > ^(Bju^ . ..,1^;^,. . .,f m ) if and only if either i(A;u, , . . . ,u ) > ^(B;u, , ...,u ) , or i(A;u.. , . . . ,u ) = i(B; u v ...,u r ) and (f 1 (A),...,f m (A)) > (f^B),. . . ,^(B)).* The Algorithm CMNL can be modified as follows in order to design an f^, . . . ,f m ;i-l irredundant MOS network in the form of Fig. 2.k. Let L " (A) = D mn i(A;u.. , . . . ,u. , ,u. , . . . ,u. ) be the first part of the label to be assigned to each vertex A in the N-cube by the Modified Algorithm CMNL. Modified Algorithm CMNL Step 1 Assign vertex I the value E 2 R_k u. (I) + 2 2 m * J f.(l). k=l k d-1 d i(A;u, ,...,u ) represents the binary value of (u, , . . . ,u ) of vertex A. Similarly with i(B;u , ...,u ). (f,(A),...,f (A)) > (f,(B),...,f (B)) means the vector comparison defined in page 6. 21 f^, . . . ,f m ;i-l Step 2 When L (A) is assigned to each vertex A of weight A- , . . . J-l- m > J- J- w (l < w < n) in the N-cube, assign as L (B) to each vertex B of weight w - 1 the smallest binary integer satisfying the following conditions for each directed edge A B in the N-cube. f^, . . . jf^i-l (a) The k-th most significant bit of L (B) is u. (B) for k = 1, ... ji-1; (b) The m least significant bits of i(B;u.. , . . . ,u ;f,,...,f ) are the values of the given output functions f..(B),...,f (B). (c) L X m (B) > L ± m (A) if (f.(A),...,f (A)) < v ' mn v — mn 1 " ' m ^ '' — (f,(B),...,f (B)); or L L m (B) > L L m (A) v l v /J 5 m mn mn if (f^A),...,^))^ (f 1 (B),...,f m (B)). + f f • i -1 1' * " * ' m Step 3 Repeat Step 2 until L (0) is assigned. Step 4 The k-th most significant bit of L (A) is denoted by u. (A) for i = 1, . . . ,r and NFS " (r+m;f , ...,f ) = (u, , . . . ,u. -, u.,....u ;f _...., f ) has been obtained. —a.' — r 1 irr t (f 1 (A),...,f m (A)) _£ (f 1 (B),...,f m (B)) means that either (f^A),..., f (A)) >(f (B),...,f (B)) or they are incomparable, where two vectors (f 1 (A),...,f (A))and (f^B),. . . ,f (B)) are "incomparable" if there exist two integers i and j, 1 < i, j < m, such that f . (a) > f . (B) and f.(A) < f (B). J J 22 Algorithm CMXL can "be similarly modified and the modified algorithm f^, . . . , f^ji-1 CMXL assigns a maximum possible label L (A) = i(A;u, ,..., /\ /\ u. -,,u.,...,u ) to each vertex A in the N-cube satisfying the same i-l' 1' r conditions as those in modified Algorithm CMNL. Based on these two modified algorithms, Algorithm DIMN can be modified as follows. Modified Algorithm DIMN : Design of irredundant MOS networks for a given " f 1' ' m set of functions f n ,...,f vyi with these output functions to be realized at the last level. Step 1 Let NFS°(r+m:f _,..., f ) = (u_ , . . . ,u ;f _,..., f ) and set i = 1 — v 1 m 1 r 1 m (if r is not known at this step, it will be determined after NFS (r+m;f , ...,f ) is obtained in Step 2 by applying the modified CMNL. ) Step 2 Using the modified Algorithm CMNL, obtain NFS 1 " (r+m;^, . . . ,f ) = v 1' » i-l 7 — i' '— r 1 ' m ^ i-l/ \ Step 3 Using the modified Algorithm CMXL, obtain NFS (r+m;f , ...,f ) = ( U 1) * • • )U i_]_' U i' * * * J U v.5 f-l 5 • • * 5 f_J • Step k Obtain function u. satisfying u ± (A) = 0, if u.(A) = u ± (A) = C; u. (A) = 1, if u. (A) = u. (A) = 1; and U. (A) = *, if u. (A) = and u. (A) = 1. The function, u., obtained by this step is the MPF (Maximum Permissible Function) for the feasible NFS " (r+m;f n , . . . ,f ). — — v 7 1 m After applying this step, the negative function sequence, (u, , . . . , * * \ ~ i-l/ \ u. , ,u. ,u. . , . . . ,u ;f n ,...,f ) is denoted as NFS (r+m,f). i-l l i+l' ' r 1' ' m \ * / 23 Step 5 Obtain an irredundant configuration for MOS cell g. with function u. with respect to x.,...,x ,u..,...,U. n . Let u. be the function 1 r 1 n' 1' ' l-l i realized by this cell. Thus, NFS (r+m, f) = (u, , ...,u. ,,u., * *- . u. ,,...,. u ; f_....,f )-has been obtained, l+l r' 1' ' nr Step 6 If i = r, design an irredundant MOS cell configuration for each output gate g . for function f. with respect to x , . ..,x , u , ...,u for o = 1, . . . ,m and terminate this algorithm; otherwise set i = i + 1 and go to Step 2. Similar to the Algorithm DTMN, this modified Algorithm DIMN applies at most r times of the loop consisting of Step 2 - Step 3 - Step k - Step 5 but the Step 5 of this algorithm alone must be executed m additional times in order to obtain the irredundant MOS cell configuration for f .,..., f . Let us consider two examples with the same set of output functions. One shows the step-by- step design procedure for designing an irredundant MOS network with output functions realized at the last m levels, and the other shows the results with all output functions realized at the last level. Example 2.2 Assume the m output functions f , ...,f are realized at the last m levels. Let P_,.-...P be a set of numbers which determines the cell 1' ' m positions of output functions in such a way that p. = j if and only if the o-th cell (g.) realizes the i-th function f.. Then NFS°(R„;f n , . . . ,f ; u v °0 i f 1 m P , ...,P ) = (u, , . . . ,iO represents the partially specified negative function sequence for output functions with output cell positions p, ,...,P . Two functions f, and f are given in Fig. 2.5(a). Fig. 2.5(b) shows 21+ EFS°(i+;f 1 ,f 2 ;3, i +) = (upu^f^) and NFS°(U;f ;L ,f 2 ;3, 1 +) = (o^u^f^fg). / o ^ o \ (upper and lower labels in vertices show NFS and NFS , respectively. ) By comparing^ and n ±3 NFS 1 (l+;f 1 ,f 2 ;3, i +) 1 , NFS 1 ^; f-^f^, 1 *)^ and NFS (l+;f , f ; 3,^)0 are obtained as shown in (c), (f), and (j)> respectively. Next, by repeating the algorithm, NFS (k;f ,f ',3^). and NFS 1 (^;f f ',3^). are obtained for i = 1,2,3, as shown in (d), (g), and (k), respectively. NFS 1 (U;f 1 ,f 2 ;3, 1 +) i and WS 2 (h;f 1 ,f 2 ;3 3 h) ± = WS(k;f v t 2 ;3 9 h) ± are then derived, as shown in (e), (h), (i), (£) . The irredundant MOS networks corresponding to NFS(^;f, ,f ;3>*0 • are shown in (m), (n), and (o) for i = 1,2, 3 j respectively. Example 2.3 All three solutions given in Example 2.2 have a connection from gate g„ to g. , i.e., the gate realizing function f, is not in the output level. Here, let us design an irredundant MOS network for f_ and fp with the gates realizing these two functions at the last level. Fig. 2.6(a) shows NFS°(4;f 1 ,f 2 ) = (u^Ugjf^fg) and NFS°(U;f 1 f 2 ) = (u u ;f f ) obtained by Steps 2 and 3 of Modified Algorithm DIMN, respectively. Comparing u and u, in Step 4, u is obtained, and hence NFS (4;f ,f ) = (u ,u 2 ;f ,f ) is obtained as shown in (b). The only irredundant MOS cell configuration for u is u = x x_, being obtained by Step 5, and the corresponding NFS (4;f..fp) = (u,,u p ;f f p ) is shown in (c). Fig. 2.6(d) shows both NFS 1 (U;f f ) = (u ,u ;f f £ ) and NFS (k;f ,f ) = (u ,u ;f ,f ) obtained by Steps 2 and 3, respectively. Since Up(A) = u ? (A) for all vertices A in the 3-cube; u p = Up = u p is completely specified, and the solution NFS(U;f, f p ) is obtained as shown in (e). The network corresponding to this NFS is obtained by designing irredundant MOS cell configurations for u p , f , , and f ? and is shown in (f). 100 (a) Cjtfj.fj). (b) NFS"(«; f x .f 2 ; 3, A) - (Uj.Uj, fj.tj). NFS°(4, Ij.fjj 3,4) ■ (0 1 ,u 2 , fj.fj). f 2 - Uj (u^xvx.Vfj) (f) NFS (4; f r f 2 ; 3,4> 2 - (x^, u*. ^.fj)- (c) NFS 1 (A; fj.fj; 3,/.) - NFS (4; fj.fji 3.4) (u 1>U2 . t v t 2 ), Fig. 2.5 Example 2.2. 26 100 i 100 (g) nk£ (*; f 1 .£ 2 ; 3.4)2 - (uj.uj.tj.fj) NFS 1 (A; f x ,f 2 ; 3.A) 2 - (iij ,6 2> f j ,f 2 > lllf Oil] (I.) NFS 1 **; fj.fjj 3,4) 2 - (Ujiij, fyfj). (k) HKS*(«i fj.fji 3,4) 3 nTs'(/.; t x , f 2 ; 3,4) 3 . f 2 - vijfxjVXjVf j) 0) NFS (4; fpfjl 3.4> 3 - NFS(A; f j . f 2 ; 3,4) 3 " ( Fig. 2. 5 (Continued) (u r u 2 , f x ,f 2 ). 27 r~i J L ro *T rH H o 00 /-*- >T M O » * * i r M H n H 3 »D O — 1 1 1 1 ^H CM vr a m in Pu 2: o 4-1 oo ^*N c *T3 •H 0) X) 3 C c o •H ex ■U w c QJ o M CJ M N-^ O o IA ^ • M C\J o S • 4J w QJ •H a Pn 28 CM Q X 1 1 1 1 ~1 « r U « t • . —1 i t 1 m X ? i J L rn cn bO o — r CM X m J L i r CM H CM ^J • M CVI O 5 . 4-t 01 (U •H z t* M O *" H" rn 29 C\l co C ) 1 bO ° ' ' > w ► 1 1 F 1 *-< 14-1 O bO 00 o — r + — <> bO °^ J U, m (Nl on 00 c •H -o C o a, en a> M o o u o iJ OJ S5 H M O 1 ► 1 1 < [ H" i 1 I en C •H o LP OJ •H Pn 30 no 100 (b) Mi's (2; f r f 2 ) - (u lt uj; f r f 2 ). 100 (d) UTS (2; t v ( 2 ) - (tij.ttji f r f 2 )- NFS 1 (2; f r f 2 ) - (u lf a 2 ; ^.fj). f - u. (x-V ",U.,) V x.u. £ 2 - u 2 „0„1 («) NFS (2 1 f,.f 2 ) " NFS (2; ^.fj) - NFS(2; fj.fj) Fig. 2.6 Example 2.3 31 o 7 -o f . ,^, HE l. Ih 1 •"-r -i -of. (f) Network corresponding to NFS(2; f,^) of ^ Fig. 2.6 (Continued) 32 It is interesting to see that the network in Fig. 2.6(f) consists of only 17 FETs (including load MOSFETs) while the networks shown in Fig. 2.5 (m), (n) and (o) consist of 19, 20 and 18 FETs, respectively. The networks designed with all output gates at the last level tend to contain more FETs than the networks designed with all output gates at the last m levels. However, the results obtained by the later case depend on the output cell positions of the output functions f , ...,£.. With different output cell positions, different MOS network configurations are usually produced. Usually, we do not know which permutation for the later case will result in better MOS networks. 33 3. PROCEDURE DIMN This chapter will discuss FORTRAN program DIMN for designing irredundant MOS networks. The program DIMN consists of two main parts: one part is for implementing the Algorithm DIMN for finding irredundant MOS networks in the cases of single-output function and multiple -output functions with all the output functions realized at the last m levels and the other part is for implementing the Modified Algorithm DIMN for finding irredundant MOS networks in the multiple- output functions case with all the output functions realized at the last level. The flowchart of Algorithm DIMN is shown in Fig. 3.0.1 and the flowchart of Modified Algorithm DIMN is shown in Fig. 3*0.2. A flag FL is used to distinguish these two cases for designing irredundant MOS networks with multiple- output functions. The flowchart in Fig. 3*0.1 or Fig. 3 .0.2 will he applied according to whether FL is set to or 1, respectively. For the case of incompletely- specified functions (single -output or multiple- output), Fig. 3.0.1 and Fig. 3.0.2 are slightly modified. The modifications will not be shown. The program DIMN is written in FORTRAN for IBM 360 (also Cyber 175). The entire program requires 100 K bytes of core storage, about 6k K being occupied by the actual program instructions and 36 K by the stored data. In the following, Section 3.1 describes internal data representation, that is, the representation of a labeled N-cube. Although the internal data representation is exactly the same as that described in Yamamoto's thesis, the description will be given in Section 3-1 in order to explain i-1/ Use Algorithm CMNL to obtain NFS (F ,f , ..., f M )=(u 1 ,....u 1-1 ,u 1 ^.m^,...,^. 4-1/ Use Algorithm CMXL to obtain N3F (R ,f , ..., f M )=(u l U i-l'V---' a R f -M' ? l'---'V- Obtain MPF u ± by setting u. (A) = 0, if u. (A) = u.(A) -0; u i (A)=l, if u.(A) =u 1 (A) =1; u. (A) - *, if UjU) ^(A). Then NFS 1 " 1 ^ f . . , f M ) = (u r . . . , Vr VVr • • • 'Vm> *v ' • " t\.) is obtained. M Obtain an irredundant MOS cell configuration for u. with respect to x.., . . . ,x .u.. , . . . ,u, .. . Let u. denote the function realized by this cell. After applying this step, NFS (R f , f, ... ,f„) is obtained. 1 M i = i + 1 No Obtain an irredundant MOS cell configuration for f . f END j 3h Fig. 3.0.1 Flowchart of Algorithm DIMN. 1 START J 35 Let NFS (r+m;f lt ...,f M ) = (u 1> . . . .u^^, . . . , f..) and set i - 1. M Use. Modified Algorithm CMNL to' obtain NFS 1_1 (r+m;f , . . ; ,f M ) = (i^, . . . ,u 1 __ 1 ,u ±I 33 r ;fl,...ffn'j • Use. Modified Algorithm CMXL to obtain NFS 1 " 1 (r+m;f 1 ,...,f ) = (u^...,^ v Obtain MPF u. by setting u.(A) =0, if u. (A) = u\(A) ,0; u\(A) =1, if u (A) = u. (A) = 1; u .(A) = *, if u.(A) tu. (A). Then NFSi-^r+m; f, , 1 1 1 ...,f M ) =(u 1 ,...,u._ 1 ,u.,u* +1) ...,u*; , f,„ ) is obtained. M Obtain an irredundant MOS cell configuration for u. with respect to t x ,u. u, ., Let u. denote the function realized by this cell. After applying this step, NFS (r+m; f, ,...,f„) is obtained. 1 M i = i + 1 Yes Obtain an irredundant MOS cell configuration for f., j = 1,...,M. END Fig. 3.0.2 Flowchart of Modified Algorithm DIMN . 36 the flowchart in Section 3-3. Section 3.2 describes the general organization of program DIMN and Section 3*3 explains the modifications of suhprocedures in detail. All other subprocedures which were explained in detail in Yamamoto's thesis [5] will not be repeated in this paper. The following notations and explanations will be used throughout the program DIMN and this paper, N is the number of external input variables, M is the number of output functions and IL, is the number of MOS cells obtained by this program, where R^ is R_ used in the previous chapters, F here denoting the previous f, II is a pointer which indicates the iteration of the program loop for determining one MOS cell configuration. For example, if _II_ is three, the third MOS cell configuration is going to be determined. 3.1. Internal Data Representation In order to implement DIMN program (The flowcharts of this program are shown in Fig. 3.0.1 and Fig. 3*0. 2), two kinds of labeled N-cubes are required. One is the labeled N-cube for storing input data, and internal results, and obtaining MFF (Maximum permissible Function). The other is the labeled N-cube for obtaining an irredundant MOS cell configuration. The labeled N-cube for obtaining MPF is accessed in blocks 2, 3? and k in both Fig. 3*0.1 and Fig. 3.0.2. In the comments of the program listing in Appendix B, this labeled N-cube is simply referred to as the N-cube and each vertex is assigned a vertex number which represents the input vector in binary form. As shown in Fig. 3.1«1 5 each vertex in a N-cube has the following 37 five fields; LABEL, DCARE, MNL, MXL and CHAIN. LABEL field, together with DCARE field, stores the partially specified negative function sequence (The notation, NFS (R^f, , . . . ,f ) , shown in Fig. 3«0.1 or the notation, NFS i-1 (r+m;f , . . .,f ), shown in Fig. 3.0.2). MNL and MXL fields store NFS 1 " 1 (R F ,f 1 ,...,f M )(or NFS 1 " 1 (r+m;f 1 ,...,f M )) that is the VERTEX NUMBER LABEL DCARE MNL MXL CHAIN Fig. 3»1»1 The vertex in the N-cube. completion of NFS 1_1 (R^,f , . . . ,f )(or NFS 1- (r+m;f , . . . ,f )) by CMNL, and NFS 1- (R^f,, . . . ,f ) (or NFS 1- (r+m;f , . . . ,f ) ) that is the completion of NFS 1-1 (R F ,f 1 ,...,f M )(or NFS 1 " 1 (r+m;f 1 , . . . ,f M ) ) by CMXL, respectively. CHAIN field stores the link to the next vertex in the list of the vertices of the same weight. In general, the vertex with vertex number (j-l) contains the j-th elements of these arrays as shown in Fig. 3«1«2. This is because the index of an array in FORTRAN cannot be zero. Therefore, vertex 0, that is, the vertex with binary value corresponds to the first elements of the arrays LABEL, DCARE, MNL, MXL and VERTEX (j-l) LABEL(j) DCARE(j) MNL(j) MXL(j) CHAIN(j) Fig. 3«1»2 The vertex with vertex number (j-l). 38 CHAIN; vertex 1, that is, the vertex with binary value 1 corresponds to the second elements of these arrays and so on. An example of the 3-cube is shown in Fig. 3.1-3. Fig. 3^1^ is the actual representation of this 3- cube in the computer memory. As can be seen in Fig. 3.1«3 5 the first and the last vertices in the lists of the vertices with the same weight are pointed by pointer arrays STARTL and ENDL, respectively. For example, vertex 3? the first vertex in the list of the vertices with weight 2 is pointed by pointer STARTL(3) and vertex 6, the last vertex in the same list is pointed by pointer ENDL(3). In general, the first and the last vertices in the list of the vertices with weight K is pointed by pointers STARTL(K+l) and ENDL(K+l), respectively. INDEX (1) (2) (3) (h) (5) (6) (7) (8) LABEL DC ARE MNL MXL CHAIN (1) (2) (3) 00 STARTL ENDL Fig. 3«1»^ Computer internal representation of the 3- cube in Ficr. ^.1.^. in Fig. 3.1.3 39 w H > .-! § oo hJ /*~\ ^ OO w pj /--s <: oo u ^^ n .j w #^^s pQ oo 3 *"* t vO Q ►J w S3 m o ^o ?2 M 3 u 1-J s hJ § -n U >^^ co Q ►J W /"N >-H PQ sfARTF 001 010 J 100 (2) (3) (5) ^1 1 (2) START] • 3.1.5 000 (1) ENDF(l) 2-cube. Fig 3-d: .mension al Larg ENDF(3) EfrDF(2) FUNC LINK (1) (2) (3) (A) (5) (6) (7) (8) STARTF (1) 1 (2) 2 (3) A (A) 8 Fig- 3.1.6 int« ENDF Large-cube in Fig. 3«1«5- 1+2 Similar to the N-cube, each vertex in the Large-cube which consists of two fields, FUNC and LINK, is assigned a vertex number which represents the input vector in binary form. The LINK field corresponds to the CHAIN field of the N-cube and points to the next vertex with the same weight. MPF (Maximum Permissible Function) is stored in the FUNC field after MPF is obtained at the end of block k in Fig. 3-0.1 or Fig. 3.0.2. Fig. 3.1.5 shows an example of the 3-din i ensional Large-cube and Fig. 3«1»6 is the internal representation of the 3-dimensional Large-cube shown in Fig. 3 .1.5. As can be seen in Fig. 3- 1*5? two pointer arrays, STARTF and ENDF, correspond to those two pointer arrays, STARTL and ENDL, in Fig. 3.1.3. 3.2 General Organization of Program DIMN This section shows the general organization of program DIMN and outlines each subprogram. Fig. 3.2.1 describes the general organization program DIMN. This program consists of subroutine MAIN and the following subroutines: INPUT, NCUBE, CMNL, CMXL, MPF, IMC, ASFUN1, ASFUN2, INCMNT, DSCAN, ASIGN1, DCRMNT, CMPR and PRINT. In order to include the Modified Algorithm DIMN in this program, three subroutines, MAIN, CMNL, and CMXL have to be modified and will be explained in greater detail in next section. The other subroutines were discussed in detail in Yamamoto's thesis. In Fig. 3*2.1, an arrow from block i to block j means that the subroutine represented by block i calls the subroutine represented by block j. h3 CN £ C/l < fH — B C/3 < erf • Q P4 2 ^ § «D M M 60 O u (X q_i O g C u O •H 4-1 Q CO N S3 d cd M 00 iH o 55 ^^ hJ O ■H ^ M £ M I* Subroutine INPUT : This subroutine reads in an N-cube input data, i.e., network parameters and given output functions. Input data setup is described in detail in Chapter k. Subroutine NCUBE : This subroutine constructs the N-cube for the input data. If the number of external input variables is N, this N-cube will contain 2 vertices. Subroutine NCUBE will examine the input vector in binary form which is to be assigned to each vertex in the N-cube one by one and will link the vertices with the same weight together. Subroutine CMNL: This subroutine calls subroutines INCMNT and DSCAN to execute the conditional minimum labeling based on the output function values read into the N-cube. E_, the number of MOS cells which is required to realize the given function(s) is determined at the first execution of this subroutine CMNL. Subroutine CMXL : This subroutine executes the conditional maximum labeling based on the output function values read into the N-cube. Subroutines DSCAN, ASIGN1 and DCRMNT are called by this subroutine. Subroutine MPF : This subroutine obtains the maximum permissible function from the results obtained in MNL and MXL fields in the N-cube by subroutines CMNL and CMXL, respectively. Then this subroutine stores the resulting MPF in the FUNC field of the Large- cube. Subroutine IMC: This subroutine obtains an irredundant MOS cell configuration from the maximum permissible function in the Large-cube 1+5 obtained by subroutine MPF. This subroutine calls subroutines CMPR and PRINT whenever necessary. Subroutine ASFUN1 : Under certain circumstances (e.g., while realizing the last gate), the maximum permissible function does not need to be obtained. This means that the program loop which consists of CMNL, CMXL and MPF need not be executed and by detecting such circumstances, the computation time can be saved. This subroutine is called under such circumstances. The function values stored in LABEL field in the N-cube are directly stored by this subroutine in the FUNC field in the Large- cube. Subroutine ASFUN2: This subroutine is called when MNL is identical to MXL at some iteration i of the program loop. The values in the MNL field in the N-cube are stored by this subroutine in FUNC field in the Large-cube. Subroutine DSCAN: This subroutine determines the number of don't care bits in the function part of the label assigned to each vertex in the N- cube and the weight assigned to these don't care bits. Subroutine MAIN : This subroutine calls the subroutines shown in Fig. 3*2.1, whenever necessary, and implements Algorithm DIMN and Modified Algorithm BTMN. 3»3 Descriptions about Subroutines In this section, three modified subroutines, MAIN, CMNL and CMXL, are explained. Although the explanation of the variables and arrays appearing h6 in these subroutines can be found in the program listing in Appendix B, some variables (which are not defined in [5]) are defined in this section in order to explain each flowchart. (1) Subroutine MAIN (Fig. 3.3-1) In block 1, parameters N, M and FL are read in and if these parameters do not satisfy the restriction on problem size (discussed in detail in Section U.2), an error message is printed and the program execution is terminated. This block also tests EOF (end of file) condition and if all data have been exhausted, the program execution is terminated. In block 2, the LABEL and DCARE fields in the N-cube are initialized to zero. In block 3> the subroutine INPUT is called and values on output function cards are read into the LABEL and DCARE fields in the N-cube. A logical variable, CS, is set to "true" if all values on output function cards are completely specified; otherwise, CS is set to "false'.'. In block k, the N-cube is constructed based on the external variables, N. In block 5, II? the pointer which indicates the number of iterations of the program loop is initialized to 1. One MOS cell configuration is determined each time the loop is executed. Block 6 executes conditional minimum labeling (CMNL) and at the first execution of this block the value of B- (the minimum number of MOS cells) is determined. In block 7, the obtained IL, value is examined and if it is equal to the number of given output functions, that is, all the given output functions are negative functions, the maximum permissible function (MPF) need not U7 O^T- IS READ PARAMETERS INITIALIZE LABEL, DC ARE CALL INPUT CALL NCUBE EOF ERROR f END J II - 1 > «— <* rflT.T. r CALL CMNL PRINT STATISTICS 51 20 CALL IMC CALL ASFUN2 ^1 YES CALL CMXL CALL MPF CALL IMC II*- II +1 CALL IMC YES CALL IMC l l II I -II + 1 Fie. "3.^.1 Flowchart of Subroutine MAIN. 48 be obtained; the MOS cell configuration can be obtained immediately by- calling subroutines ASFUN1 and IMC. If IL, j= M, the subroutine CMXL is called to implement conditional maximum labeling. In block 9> the labels assigned to the N-cube by CMNL and CMXL are compared and if the labels assigned by CMNL and CMXL take the same value at every vertex in the N-cube, there exists the unique minimum negative gate network (i.e., unique maximum permissible function) and block 9 is immediately followed by the loop (Block 20, 21, ) for obtaining an irredundant MOS cell configuration. Under this condition, the execution of subroutines CMNL, CMXL and MPF is skipped. In block 10 and block 11, subroutine MPF and subroutine IMC are called if the labels assigned by CMNL and CMXL to the N-cube take different values at some vertices. After the implementation of block 11, the configuration for the MOS cell indicated by pointer II is determined (i.e., the II-th MOS cell is obtained). In block 12, Pointer II is increased by one. FL is examined in block 13 and if FL is equal to 1 (multiple- output functions with all output functions to be realized at the last level), block ik is executed; otherwise (multiple- output functions with all output functions to be realized at the last M levels), block 26 is executed. In block lk, if we are not going to determine the output gates, the program control is returned to block 6. If the M output gates are going to be determined, the loop of the procedures for determining MOS cell configuration is immediately followed (Blocks 15, l6, 17 and 18) and the procedure for obtaining MPF is skipped. After applying this loop, an irredundant MOS network which realizes the given output functions is obtained. ^9 In block 27, if II is not equal to IL, in other words, if we are not going to determine the configuration of the last MOS cell in the network with all output functions realized at the last M levels, the program control is returned to block 6. If II is equal to R^, that is, if the configuration of the last MOS cell is going to be determined, blocks 28 and 29 are followed to determine this configuration of the last MOS cell. In block 19, the statistics about the obtained network are printed out and the program control is transferred to block 1. The contents of the statistics are described in detail in Chapter 5. In block 1, if problem cards are not exhausted, a new problem is read in and the entire process is repeated. If problem cards have already- been exhausted, the program is terminated. In block 26, the logical variable CS is examined and if CS is true, this block is followed by block Ik. In the case of multiple- output functions, the maximum permissible function need not be obtained for the output function which is completely specified. Therefore, if one of the MOS cells which realize the completely specified output functions is being considered, block l4 is immediately followed by the loop for determining MOS cell configuration and the process for obtaining the maximum permissible function is skipped. (2) Subroutine CMNL (Fig. 3-3.2) The following is the definition of variables and arrays which appear in this subroutine. USPFY : As mentioned in Section 3'1 3 array LABEL stores a partially specified negative function sequence. USPFY stores the number of unspecified 50 "bits in array LABEL. The relation between USPFY, R_, II and M is shown in Fig. 3.3.3. W: This variable stores an actual weight plus one. PTRB : This is a pointer to vertex B to which the minimum possible value is to be assigned. PTRA: This is a pointer to vertex A which is connected to vertex B by the edge from vertex A to vertex B. The vertex A has a greater weight II \ \ / I A \ 1 1 USEFY = B_, - II + 1 Fig. 3.3.3 Relation between USPFY, element of array LABEL. V II and M for an than vertex B by one. LBX : This is a variable which stores LABEL field of vertex pointed by pointer B (For the case where FL = 0). LAX : This is a variable which stores the minimum label assigned to vertex A (For the case where FL = 0). LBY : This is a variable which stores DCARE field of vertex pointed by pointer B (to be examined in subroutine DSCAN). The number of don't care bits and the weight assigned to each don't care bit are determined. NDCARE : This is a variable which stores the number of don't care bits. This value is determined in subroutine DSCAN. 51 BWEIT: This is an array which stores the weight assigned to each don't care bit. PTB.BX : This is a variable which stores the input vector in binary form assigned to vertex B (to be examined bit by bit). PRTA will be determined from this variable and variable SHIFT. INB : This is a counter for the increment of LBX (used for the case where FL = 0). LBZ : This is a variable which stores the first part of label (i.e., (u, ,...,u )) for vertex B (used for the case where FL = l). LAZ: This is a variable which stores the first part of label for vertex A (used for the case where FL = l). L_: This is a variable which stores the weight of output function bits in array LABEL. J: This is a variable which stores the index value of array BWEIT. LBT : This is a variable which stores the first part of label together with the first (M-L) bits of output functions stored in LABEL field for vertex. B. This variable is used for examining the (M-L)th function value at vertex B under the condition that FL = 1. LAT: This is a variable which has the same meaning as that of LBT except being used to describe vertex A. LB : This is a variable which stores the first part of a label together with one of the output function bits. This function bit is determined by L such that LB represents the sequence (u, , . . . ,u ,f.) for i = M - L. LA : This is a variable which has the same meaning as that of LB except being used to describe vertex A. INC : This is a counter for the increment of LB (used for that case we where FL = l) . 52 Fig. 3.3.U shows the structures for LBZ, and LBT and Fig. 3*3.5 shows the structure of LB, for some vertex B in the N-cube. 'A LBZ F M \ A 1 , , .. ., f l - - - - f M V LBT Fig. 3.3.1+ The structures of LBZ and LBT for the LABEL field of vertex B. M / \ u l - - - - u r f. 1 \ LB _ / Fig. 3-3«5 The internal representation of LB for vertex B, where i = 1, . . . ,M. Each time LB is constructed, i is equal to M -L. 53 The following is the detailed explanation of Fig. 3.3.2(a) and (b). In block 1 (Fig. 3.3.2(a)), the minimum possible label is assigned to the vertex with weight N. Since LABEL is initialized to zero in block 2 in subroutine MAIN, the unspecified bits in LABEL ( STARTL (N+l ) ) have already been assigned zero, the minimum possible value. As shown in Fig. 3.3«3> the number of unspecified bits is obtained by calculating B— - II + 1. Although IL is obtained after the first implementation of subroutine CMNL, the value of IL, has to be specified in subroutine MAIN before CMNL is called for the first time. Let us consider FL = first. After assigning a label to the vertex with weight N, a minimum possible label is asigned to every other vertex in the following way. In the loop consisting of blocks k through l6, each vertex pointed by PTRB (vertex B) is assigned a minimum label. In general, as shown in Fig. 3*3.6, there exist several vertices which are directly connected to vertex B by edges. Minimum labels which have already been VERTEX (PTRA-l) PTRA PTRB VERTEX ( PTRB- 1) Fig. 3.3.6 Relation between vertices A and B in CMNL. f START J 5h YES MNL(STARTL (N+l))- LABEL (STARTL(N+l)), USPFY- R„- II + 1 F W - N PTRB- STARTL(W) LBX - LABEL (PTRB). LBY - DCARE (PTRB). INB-O, SHIFT- 1. CALL DSCAN I 1=1 PTRBX- (PTRB 1) /SHIFT PTRA- PTRB + SHIFT 10 I LAX-MNL (PTRA) YES 18 PTRB- CHAIN (PTRB) OBTAIN ( RETURN J * ± L i SHIFT = 2* SHIFT 1=1 + 1 LBX - LABEL (PTRB) 13 16 CALL INCMNT MNL(PTRB) - LBX NO * Fig. 3.3.2(a ) Flowchart of subroutine CMNL. >1» LBZ' - LBX/2* *M i.AZ- - LAX/2**M •5 V L - J - 1 26 LBT - LBX/2**L LAT - LAX/2**L 28 YES LB-2*LBZ LB-2*LBZ + 1 31 YES LA-2*LAZ LA - 2*LAZ + 1 38 YES — -"BWEIT J) 39 INC =0 LBX- LBX + BWEIT(J) 5c ' ( LB-LB + 1 INC - INC + 1 in LB > LA = 2**L^>_ [0 v , U6 LB- LB + 2 LBX-LBX + 2**M J- J + 1 L-L + 1 LBZ - LB/2 7F NO NO YES 1+2 YES J = J + 1 1+5 INC/,*2 = INC kk LBX - LBX + BWEIT(J) LBX- LBX + 2**M- BWEIT(J) 55 Fig. 3.3.2(b ) Flowchart of subroutine CMNL (continued) 56 assigned to these vertices are compared with LEX one by one ( block ll) and LBX is increased by one ( block 13) until none of the labels assigned to these vertices is larger than the label assigned to vertex B. In block 9, PTRA is calculated by PTRA = PTRB + SHIFT. As vertices with the same weight, say (w-l), are linked by CHAIN field, starting from the vertex pointed by STARTL(W), all the vertices within the linked list can be exhausted by this scheme (block 3? 17 and 18). Starting from the vertices with weight (N-l), the above procedure is applied to every set of vertices with the same weight until a label is assigned to the vertex with weight zero. The value of IL, is obtained ( blocks 21 and 22) at the first execution of this subroutine. When FL is 1, the loop (blocks 11, 12 and 13) in Fig. 3.3.2(a) is replaced by the whole flowchart in Fig. 3.3.2(b). The main difference between these two cases is the way to compare the minimum label which has been assigned to every vertex A with the label assigned to the correspond- ing vertex B. In Fig. 3.3.2(b), the output function values in LABEL field for each vertex are considered as a vector. This means that LB (i.e. , (u (b) , . . . ,u (B),f.) of vertex B) has to be greater than or equal to every LA (i.e., (u, , (A) , . . . ,u (A),f.) for every vertex A connected to this vertex B) , for i = 1, . . . ,M. One of the vertices which directly connect to vertex B and have weight greater by one than that of vertex B is obtained in block 9« Therefore, the main task in Fig. 3«3«2(b) is to compare M LB's of vertex B with the corresponding M LA's of this vertex A one by one and LB is increased by one repeatedly until none of the LA's assigned to this vertex A is larger than the corresponding LB assigned to vertex B. Then, the program control is transferred to block lk 57 in Fig. 3.3.2(a) and a next vertex A is obtained (block 7) and the same process in Fig. 3. 3.2(b) is repeated until all possible vertex A is exhausted. The program control is then transferred to block 16. In Fig. 3.3.2(b), blocks 2k,..., 32 obtain one LB of vertex B and the corresponding LA of vertex A. Block 33 compares these two values. If LB is greater than or equal to LA, the loop including block 3^ is executed; otherwise, block 38 is executed. If the last bit in LB is originally a don't care of output function values (tested in block 3*0 , the corresponding weight of this don't care bit is skipped in block 35 (since LB is greater than or equal to LA, this don't care bit needs not be set to one). In block 36? the weight of output function values is increased by one and the first part of label (i.e., (u , ...,u )) assigned to this LB is stored back to LBZ. If all the possible LA's of this vertex A are exhausted, the program control is transferred to block 1^ in Fig. 3.3.2(a); otherwise the program control is returned to block 26. As mentioned above, if LA is not smaller than LB, block 38 is executed. If the last bit in LB is not originally a don't care of output function values, LB is increased by two (i.e., increase the first part of label by one) each time the loop consisting of blocks h6 and k-7 is executed until LB is greater than or equal to LA. Then, the program control is transferred to block 36 and the next pair of LB and LA is examined. If the last bit of LB is originally a don't care, this don't care bit is set to one (in block 39) and the counter, INC, is increased by one (in block kO) . Then, block Ul compares LB and LA. If LA is not smaller than LB, LB is increased by one each time the loop consisting of blocks k3, hk or k-5, h0 is 58 executed until LA becomes smaller than LB, and then the index of array BWEIT is increased and the program control is transferred to block 36. (3) Subroutine CMXL (Fig. 3-3.7) This subroutine is executed in almost the same way as the subroutine CMNL is. The flowchart in Fig. 3.3.7(b) (i.e., for the case of FL = l) is the same as that in Fig. 3.3.2(b), except that after l's are assigned to the unspecified bits of the label field of vertex B by calling sub- routine ASIGN1, the label in subroutine CMXL is decreased instead of being increased in subroutine CMNL. The following is the definitions of variables used in this subroutine. Variables with the same definition as those in subroutine CMNL are omitted. PTRB : This is a pointer to vertex B to which the maximum possible value is to be assigned. PTRA: This is a pointer to vertex A which is connected to vertex B by edge. The vertex B has a larger weight than vertex A by one. The relation between vertex A and vertex B is shown in Fig. 3*3 .8. VERTEX (PTRB-1) PTRB PTRA VERTEX (PTRA-1) Fig. 3.3.8 Relation between vertices A and B in CMXL. 59 1 ( START ) V LBX - LABEL (STARTL(D) LEY- DC ARE (STARTL(D) USPFY-R^-II+1 F 2 I CALL ASIGN1 3 > ' MXL(STARTL (l))-LBX k J, W - 2 5 * PTRB- STARTL(W) ' 6 ,, ^ LBY- DCARE(PTRB) 7 1 t CALL DSCAN 8 > * LBX - LABEL (PTRB) LBY - DCARE (PTRB) 9 ^ t CALL ASIGN1 10 1 r LBXX - LBX INB-0 I *■ 1 SHIF r P- 1 11 X >? 'TRBX- (PTRB - 1)/SHIF1 YES 12 PTRA- PTRB ■ SHIFT 111 LAX-MXL(PTRA) LBXX -LBX 18 CALL DCRMNT 19 . ^ nT I-I + l SHIFT - 2*SHIF1 MXL(PTRB) - LBXX Iig^3.i3j_7(ai Flowchart of subroutine CMXL. 60 26 27 LBZ- LBXXA **M LAZ - LAX£ **M ST- L ► J - 1 28 LBT-LBXX/ 2 **L LAT - LAX/ 2 **L 30 YES LB - 2*LBZ LB-2*LBZ + 1 33 YES LA-2*LAZ LA - 2*LAZ + 1 J - J + 1 LBXX-LBXX BWEIT(J) LBXX - LBXX - 2**M+BWEIT(J) Fig. 3.3.7(b) Flowchart of subroutine CMXL (continued) 6l LEX : This is a variable where LABEL(PTRB) is stored after l's are assigned to the unspecified bits in LABEL (PTRB) . LBXX : This is a variable which stores contents of LBX. LAX : This is a variable which stores the maximum label that has already been assigned to vertex A. INB : This is a counter for decreasing LBXX (used in the case of FL = 0). INC : This is a counter for decreasing LB (used in the case of FL = l). In blocks 1, 2 and 3 (Fig. 3.3.7(a)), the maximum label is assigned to the vertex with weight zero. Starting from the vertices with weight zero ( block 2), a maximum possible label is assigned to every vertex in the N-cube in a manner similar to the case of subroutine CMNL. The loop consisting of blocks l6, 17 and 18 is replaced by the whole flowchart in Fig. 3.3.7(b) when FL is 1. In block 13, PTRA is obtained by subtracting SHIFT from PTRB. 62 k. INPUT DATA SETUP Because of the implementation of the design algorithm described in Chapter 2, some modifications in input data setup of Yamamoto's program have been made. Two main differences are in the parameter card and the restriction on problem size. For users' convenience, not only the differences but also the ■whole detailed format description are presented as follows. k.l Input Data Card Format For each problem, the following two sets of input data cards must be submitted: < parameter card > and < output function card >s. (a) < parameter card > This card contains 3 parameters N, M and FL. The meaning of these parameters is explained below. N N is the number of external variables of the given switching function, It is specified in columns 1 and 2, and it is right justified. M M is the number of output functions. It is specified in columns 5 and 6, and it is right justified. FL FL is a logical variable. It is used to indicate which multiple- output case is considered. When FL is specified to 1, it implies that the output functions will be realized at the output level. When FL is 63 specified to 1, it implies that the output functions will "be realized at the output level. When FL is specified to 0, it means that the output functions will be realized at the last M levels. In single- output case, FL can have either 1 or 0. FL is specified in column 9« Column 3 - column h, column 7 - column 8 and all the other columns are blank, (b) < output function card >s Although output functions are submitted to this program in the truth table form, the input vector for each output function value is implicitly specified by the order in which the function values are specified in each output function card(s). The truth table with N external input variables and M output functions is shown in Fig. k.l. Each output function is specified on one or several output function cards, depending on the number of external input variables, N. For N external input variables, there are 2 possible combinations of input vectors and so the number of components of each output function value is 2 . In Fig. k.l, the first component of the column for the first function f is specified in the first column of the first output function card(s). It is specified to 1, 0, or * if f_ is 1, 0, or a don't care, respectively, f, , the second component of function f is specified in the second column and so forth. After specifying all the function values of function f_ , function f is specified on separate output function card(s). The above process is repeated until M output functions are specified on M separate sets of output function card(s). Since blank column terminates one output function specification (the program DLMN interprets the blank character 6k x l x 2 * • * ^-l *N f l f 2 " " f M ... *? 4 -- - - f ° M ... 1 * 4 -- - - f 1 M ... 1 • ... 1 1 1 1 ... 1 '<■ ■2 J°-2 2 2 N -2 "- f M 1 1 ... 1 1 £ ■1 2 N -1 f 2 /-I M Fig, k.l Truth table with N external input variables and M output functions. as terminator of one output function specification), the blank character should not be inserted among function specification except at the end of each function specification. Since each component of an output function value is specified in one column in the output function card(s), the number of cards needed to specify one output function is 80 where |r] denotes the smallest integer not smaller than r. Therefore, if the number of external input variables, N, N is larger than or equal to 7, then the number of input vectors, 2 , will exceed the number of columns in one card and consequently two or more output 65 function cards are required in order to specify one output function. For ' o9 1 example, if N=9, then 2^ = 512 and 80 = 7. This means that we need 7 cards to specify each output function with nine external input variables. In Fig. h.2, input data cards for one problem are shown and in Fig. ^-.3(a), and input card sequence for the execution of a typical DIMN problem using the batch system of I EM 3^0 is shown. (Fig. U.3(b) shows that for Cyber 175. ) If there exists a format error in input data, the following error message is printed out and the program execution halts. "INPUT ERROR IN DATA CARD I = *** J - *** K = ***" This message means that an error occurred at the K-th column of the J-th output function card which specifies the I-th output function. / input data / cards | < parameter card > ■c C output function \ cards \ output function specification for f output function specification for f r output function specification for f M Fig, k.2 The output data cards for one problem. 66 // JOB /* ID < ID card information > /* ID REGION = 300K, TIME - (00,30), LINES = 06000 // EXEC FORTLDGO, REGION. GO = 300K FORTRAN Source Program h II GO. SYSIN DD * input data \ cards c r f i < parameter card > < output function card > s < parameter card > < output function card > s the first problem the second problem < parameter card > < output function card > s the last problem Fig. U.3(a ) Input card sequence for the execution of a typical DIMN problem on IBM 360. JOB. SIGNON (ID NUMBER) < PASSWORD > < CHARGE INFORMATION > FTN. LGO. /7/8/9 67 FORTRAN Source Program /T/8/9 S [ < parameter card > | < output function card > s input data cards < c < parameter card > ; output function card > s f < parameter card > ( < output function card > s 76/7/8/9 the first problem the second problem the last problem Fig. U.3(b ) Input card sequence for the execution of a typical DIMN problem on CYBER 175. 68 k.2 Restriction on Problem Size Some restrictions on the size of an acceptable problem are required in order to pack problems into a finite amount of space. The size restriction of each problem to be solved by this program DIMN depends on the dimension of the Large-cube. For single-output functions, the dimension of the Large- cube will be N + i - 1 at the i-th iteration of the program loop, and each time the program loop is executed, the dimension of the Large-cube will be increased by one. Therefore, at the last iteration of this program loop (when i=lO the dimension of the Large-cube will be N + R_-l. The restriction on the problem size is due to this memory size. Let D (0) denote the maximum number of inverse edges over all directed paths from vertex I to vertex in the N-cube. Then, R^ can be represented as follows. R F = log 2 (D^(0) + 1) + 1 (h.i) (See Corollary 3»2 in Lai's thesis.) In single-output case, the maximum value of D (0) can be N/2 or (N+l)/2, depending on whether N is even or odd, respectively. Thus R^ = log„(D (0) + 1) I + 1 = |log 2 (|+l) ^N+l . v 10g 2 (-7f- + 1) + 1 holds if N is even, or R„ holds if N is odd. It follows that the restriction on problem size has to satisfy the following relationships. + 1 or N + 1 + N + 1 + log 2 ( 2 + 1) < L if I is even \ log 2 (— + 1) < L if N is odd where L is the reserved dimension for the corresponding Large-cube. 69 Based on the above relationships, the maximum number of external variables which the program DIMN can handle is eight (since the space reserved for Large-cube in program DIMN is kK, i.e., L = 12). This is the size restriction for single-output functions. Let us consider the cases of multiple- output functions. Obviously it is possible that every directed edge in the N-cube for a multiple- output function is an inverse edge. An example of 3 external input variables and 2 output functions is shown in Fig. h.k. Therefore, in the worst case of multiple- output functions, D (0) is equal to the number of 110 100 Fig, k.h Every directed edge in this 3- cube is an inverse edge. external input variables, N. The last term in eq. (k.l) represents that only one output gate is required to realize the given single-output function. Therefore, if all the output functions f , , ...,f are realized at the last M levels, the last term in eq. (U.l) must be changed to M because the output functions f ,,..., f. -. together with the sequence x.. , . . . jX^jU, , . . . ,u_ _ M are used as input vectors to the corresponding Large-cube to realize function f., for i = 1, . . . ,M. Consequently, the 70 restriction on problem size for multiple- output functions with all out- put functions realized at the last M levels has to satisfy the following relationship. / N + M + log 2 (N+l) 1* The relationship between the maximum number of external variables and the maximum number of output functions which the program DTMW can handle is shown in Table k.l assuming that L is 12. maximum number of external variables, N 7 6 5 k 3 2 maximum number of output functions, M 2 3 k 5 7 8 Table k.l Size restriction for multiple -output functions with all output functions realized at the last M levels that program DIMM can handle. If all the output functions f , ...,f are realized at the last level, the number of negative gates required to realize the desired MOS network, i.e., R , can be expressed by eq. (k.l) where D (0) is replaced by N (as explained previously). The reason is that gates which realize output functions do not feed other gates in the network. While realizing output functions f. for i = 1,...,M, only the sequence x, , . . . ,x„,u,, . . . ,u are used as input vectors to the corresponding Large- cube. By Step 6 of the 71 Modified Algorithm DIMN, all output functions f. for i = 1, . . . ,M are realized as M single-output functions with respect to external inputs x^ , . . . ,x^,u, , . . . ,u . Consequently, the restriction on problem size for multiple -output functions with all the output functions realized at the last level has to satisfy the following relationship: N + 1 + log 2 (N+l) < L . Based on this relationship, the maximum number of external input variables that the program DIMN can handle for multiple- output functions with all the output functions realized at the last level is seven. If the above restriction is violated, the following error message is printed and the program execution halts. "INPUT ERROR IN PARAMETER CARD N = *** M = *** FL = *-**" In this error message, N is the number of external variables, M is the number of output functions, and FL is the flag which indicates which case of multiple- output functions is being solved. These limitations are essentially imposed by the array sizes in the programs presently written. The restriction can be loosened by increasing array dimension appropriately. The above restriction on problem size is derived based on the worst-case assumption for each case. Actually, the size limitation depends on each particular problem. Example ^.1 The truth table for this example function is shown in Fig. U.5. The input data setup for the network with three external variables (N=3) and two completely specified output functions (M=2) is shown in Fig. k.6. The output functions are realized at the last 2 levels (FL=0). 72 Example k.2 The truth table for the functions is shown in Fig. h.J. The input data setup for the network with three external variables (N=3) and two incompletely specified output functions (M=2) is shown in Fig. k.8. The output functions are realized at the last level (FL=l). 73 x l X 2 X 3 f l f 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fig, k.5 Truth table for Example k.l. column no. 000000000111 123 I+56789012 output function card (f 2 ) output function card (f ) parameter card Fig, k.6 Possible setup of data cards to specify the problem given in Example k.l. - represents the blank character. Ik x l X 2 X 3 f l f 2 1 * 1 •* 1 1 1 1 1 # 1 * 1 1 * -* 1 1 1 1 1 1 1 1 Fig, k.7 Truth table for Example k.2, column no. 000000000111 123^56789012 Fig. 4.8 Possible setup of data cards to specify the problem given in Example k.2 75 5. OUTPUT OF PROCEUDRE DIMN In this chapter, the output of program DIMN is described. The output format for a typical DIMN problem is shown in Section 5.1. Some MOS networks obtained by program DIMN are compared for both restrictions on output positions in Section 5.2. 5.1 Output Format Fig. 5.1 and Fig. 5*3 show the printouts obtained by program DIMN for two typical examples. In Fig. 5.1, the number of external variables and the number of output functions are printed first. Then the restriction on output cell positions and the two output functions in truth table form are shown. The MOS network configuration for each cell is then printed. Here each variable x ,x p ,...,x^ represents a driver MOSFET which is fed by the corresponding external variable x- ,x p , . . . ,x„ and each variable U, ,U p , . . . ,U_ represents a driver MOSFET which is fed by the corresponding output of cell g_ ,gp, ...,g_. In this example, since the given output functions are realized at the last level, MOS cell 3 (or g_) and MOS cell k (or g^) realize output functions f, and f , respectively, and both cells are at the last level. Finally the number of MOS cells, the number of driver MOSFET' s and the time elapsed are shown one by one. Fig. 5.2 shows the network obtained from the MOS cell configuration printed in Fig. 5.1. For the I'M 360/75J computer, STEPZ in FORTRAN system subroutines is used as a timing subroutine. In addition, program DIMN is compiled by FORTRAN G compiler. 76 ***************************************** * * * DESIGN OF TRRFDUNDANT MOS NETWORK * ***************************************** X = EXTERNAL VARIABLE U = OUTPUT OF MOS CEIL ***************************************** NUMBER OF EXTERNAL VARIABLES = 3 NUMBER OP OUTPUT FUNCTIONS = 2 GIVEN FUNCTIONS ARE REALIZED AT LAST LEVEL FUNCTION 1 01101001 FUNCTION 2 00010111 NETWORK CONFIGURATION I — X2--X 3 — | I I MOS CEIL 1 0--| --X1--X3-- I--0 I--X1--X2--I I--X1--X2--X3-- I MCS CELL 2 0--| --X3--U1 I--X2--U1 I I--X1--U1 --0 MOS CELL 3 U2 MOS CELL ^ Ul NUMBER OF MOS CELLS = H NUMBER OF MCS FETS = 3 7 (WITHOUT FACTORING) ELAPSED TIME = . 1 2 S EC Fig. 5.1 Printout for given functions is realized in output level. 77 p -3- OJ o X OJ X on X CVJ P -#-<» on X H X H OJ H P fciD -4-41 X n o •H -P ce •H o o o m s -P O 0) •H o3 • -P H £> • O LT\ U o -P OJ bO •H £ OJ 78 ***************************************** * * * DESIGW OF TRREDUNDANT MOS NETWORK * * * ***************************************** Y. = EXTERNAL VARIABLE U = OUTPUT OF MOS CELL ***************************************** NUMBER OF EXTERNAL VARIABLES = 3 NUMBEP OF OUTPUT FUNCTIONS ■ 2 GIVEN FUNCTIONS ARE REALIZED AT LAST 2 CELLS FUNCTION 1 01101O0J FUNCTION 2 000301 1 1 NETWORK CONFIGURATION MOS CELL i 73 I— X2--01--I I MOS CELL 2 0— | — X1--D1 — I--X1— X2--| --0 MOS CELL 3 0-- I — XI— X2 — Ul~ f --U1--U2 --X2--U2 --X1--U2 — | — U2--U3— MOS CELL U Q — | — Ul — 03— I— Ul— U2— — NUMBER OF MOS CELLS = «■ NUMBER OF HOS RETS = 22 (WITHOUT FACTORING) ELAPSED TIME = 0. 17 SEC Fig. 5.3 Printout for given functions is realized in last 2 levels. 79 CM 4 — <> "t- t /-in c nVitalmoil >vir -r\v>r\rr-v*a-m ViTMTtd functions obtained by program DIMN. 81 No. of variables No. of output functions cases * Functions No. of MOS cells No. of driver FETs No. of interconnections 2 FL => 1 1-bit full adder u 17 5 3 FL = W II k 22 13 B » k 17 5 3 FL = 1 2-bit full adder 6 158 6l 5 FL = W 11 6 166 72 B tl 6 106 h9 2 FL = 1 f x = B9, fg = IE »+ 13 It 3 FL = W II k 16 7 B II 3 15 It 2 FL = 1 f l = 3A ' f 2 = 2B U 12 6 3 FL = W II It lit 8 B 11 U 10 It 2 FL = 1 t x = Jic, f 2 = 8A 3 7 2 3 FL = W H 3 7 3 B " 3 7 2 2 FL = 1 f ± = 95, f 2 = 27 It lit 6 3 FL = W il It lit 8 B » It lit 6 2 FL = 1 f x = B3, f 2 = U2 It 15 5 3 FL - W it It 13 5 B " 3 lit 5 FL = 1 indicates the designed network with all the output functions realized at the last level. FL = indicates the designed network with all the output functions realized at the last M levels. W represents the worst result for the case of FL = 0. B represents the best result for the case of FL = 0. without factoring 82 we mean that the number of MOS cells in the network obtained is the smallest among all networks corresponding to all output cell positions. Similarly with "worst result". In particular, in the case that all networks have the same number of MOS cells, the best result is the network that has the smallest number of driver MOSFETs and the worst result is the network that has the largest number of driver MOSFETs. In the case that all networks have the same number of MOS cells and the same number of driver MOSFETs, the best result is the network that has the smallest number of interconnections and the worst result is the network that has the largest number of interconnections. In this table, functions are represented in hexadecimal form. For example, function f = 01001100 is represented in hexadecimal form f = kC. As can be seen in this table, the results obtained for networks with output functions f , ...,f realized at the last M levels extremely depend on the permutation of output functions. If a permutation is chosen inappropriately, not only the number of MOS cells but also the number of driver FETs or (and) the number of interconnections obtained may be greater than those obtained by other permutations. However, those permutations from which the best results are obtained are usually not possible to be found unless we exhaust all the possible permutations. Although different permutations (for a network with M output functions, there are MJ permutations) may result in different MOS networks, each network designed by Lai's algorithm is guaranteed to be irredundant. For a given set of functions, only networks with all output functions to be realized at the last level or networks with all output function to 85 REFERENCES [1] T. Ibaraki and S. Muroga, "Synthesis of networks with a minimum number of negative gates," IEEE Trans. Computers, Vol. C-20, pp. 1+9-58, Jan. 1971. [2] K. Nakamura, N. Tokura, and T. Kasami, "Minimal negative gate networks," IEEE Trans. Computer, Vol. C-21, pp. 5-11, Jan. 1972. [3] T. K. Liu, "Synthesis of logic networks with MOS complex cells," Report No. UIUCDCS-R-72-517, Department of Computer Science, University of Illinois, Urbana, Illinois, May 1972. [k] H. C. Lai, "Design of diagnosable networks," Ph.D. thesis, 197& Department of Computer Science, University of Illinois, Urbana, Illinois. [5] K. Yamamoto, "Design of irredundant MOS networks: A program manual for the design Algorithm DIMN," Report No. UIUCDCS-R-76-78^, Department of Computer Science, University of Illinois. [6] S. Muroga, CS 363 - "Integrated Circuit Logical Design," classnotes, Department of Computer Science, University of Illinois, Urbana, Illinois* APPENDIX A Networks Obtained by Program DIMN 86 85 REFERENCES [1] T. Ibaraki and S. Muroga, "Synthesis of networks with a minimum number of negative gates," IEEE Trans. Computers, Vol. C-20, pp. 1+9-58, Jan. 1971. [2] K. Nakamura, N. Tokura, and T. Kasami, "Minimal negative gate networks," IEEE Trans. Computer, Vol. C-21, pp. 5-11, Jan. 1972. [3] T. K. Liu, "Synthesis of logic networks with MOS complex cells," Report No. UIUCDCS-R-72-517, Department of Computer Science, University of Illinois, Urbana, Illinois, May 1972. [h] H. C. Lai, "Design of diagnosable networks," Ph.D. thesis, 1976 Department of Computer Science, University of Illinois, Urbana, Illinois. [5] K. Yamamoto, "Design of irredundant MOS networks: A program manual for the design Algorithm DIMN," Report No. UIUCDCS-R-76-781+, Department of Computer Science, University of Illinois. [6] S. Muroga, CS 3^3 - "Integrated Circuit Logical Design," classnotes, Department of Computer Science, University of Illinois, Urbana, Illinois. 86 APPENDIX A Networks Obtained by Program DIMN 87 x & • • * ft • * ft • • ft • X. « ft • u. * ft - » o » ft * • re » ft * H « ft *r- • UJ » ft • as » ft » * ft II II o o • w * ft 1 1 • c « ft w I • * so » ft u 1 ■ • • ft JW 1 O 1 1 • H • i-l ft CQ3S 1 1 i 1 o • B£ « MM ft •SO r*j 1 O* 1 fnvo M • < • -1W ft HH X 1 D 1 (0 • a • ou * KH I 1 1 1 * JB « •M ft ««U SB I 1 1 1 II II m • D • MM ft >sc o r- tr) « r- r- * Q • WO ft o H M X k e V) «-. • # U • ««E ft ►Jft- H 1 1 I • _Jinri O • M * > ft ac •« 1 1 I I .JHSB • V. « u- ft XH i- ' ft. 1 1 i ii MMM • m • -JO ft BP ^ D 1 1 I UMM • • «! ft U0< o o 1 1 • O II • t», » SKf-i ft HH ^ H O O O WtftH • o « p-,E> ft KO o 6. oou H * « WCb ft HO t-O 5». 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K U> •4 I>1 KILO « ^ • • ioru •XL t-o h-f- O U U C> u U4I»4B « r«T3 • cecc M (.'»- O* 3B WBQM • * «r! t> us* ZO f-« * c;H T FT = LBY /2 UE ♦ 1 I = L,USPFY = LBX ♦ SHIFT ,RF ,MNL (102U) ,ENDL(1 1) ,STARTF( !5) ,FL ,MXL (102U) ,FUNC (U096) ,ENDF(15) RY UNSPECIFIED BIT OF LABELS 110 SHIFT = 2 * SHIFT 60 CONTINUE 70 PETURN END £************************ C * ' C SUBROUTINE TNCMNT * C * C** ******** ************** SUBROUTINE INCMNT ( INB, NDC APE . LBX. K. BWEIT ) C THIS SUBR^U^TNE INCREMENTS THE LABEL ASSIGNED TO THE VERTEX POINTED C BY POINTEP-P~RB. IMPLICIT IN^EGERf A-Z ) INTEGER BWEIT f 10 ) C INB IS THE COUNTER WHICH HAS SPECIFIED WEIGHT FOR EACH BIT. INB = INB ♦ 1 INBX = INB J = 1 SHIFT = 2 ** ( M - NDCARE ) 10 IF( INBX .EQ. ) JO TO UO IF { INBV/2** .EO. INBY ) GO TO 30 I'M J .LE. NDCARE ) GO TO 20 LBX = L3X + SHIFT GO TO 3 20 L3X = LBX ♦ BWEIT ( J ) 30 J = J ♦ 1 SHIFT = 2 * SHIFT INBX = INBX / 2 GO TO 10 <40 FETURN END C ************************ c * C SUBROUTINE DCRMNT * C * C** *************** ******* SUBROUTINE DCRMNT ( INB , NDCARE, L3XX , M, BWEIT ) C THIS SURPTUTINE DECREMENT THE LABEL ASSIGNED TO THE VERTEX POINTED C BY POINTER-PTPB TEGEP.f A-Z ) INB ♦ 1 = INB J = 1 INTEGER BWEIT ( INB = INB ♦ 1 INBX = INB SHIFT = 2 ** ( M - NDCARE ) 10 IF( INP V . EQ. ) GO TO UO IF ( INBX/2*? .EO. INBX ) GO TO IF( J .LE. NDCARE ) GO TO 20 LBX* = LPXX - SHIFT GO TO 3 20 LBXX = LBXX - BWEITf J ) 30 J = J ♦ 1 SHIFT = 2 * SHIFT INBX = INBX / 2 GO TO 10 UO PETURN END C*********************** C * C SUBROUTINE DSCAN * C * 30 Ill r *********** ************ SUBROUTINE DSCAN( LB Y, USPF Y, NDC APE ,BWETT ) C THIS SUBROUTINE SCAM THE DCARE WHICH IS ASSIGNED TO EACH VEFTEX C AND OBTAIN THE NUMBER OF DONTCAEE BITS AND THE WEIGHT ASSIGNED C TO EACH DONTCAPE BIT. IMPLICIT INTE1E3( A-Z ) INTEGER BWEIT (10) C BWEIT( 10 ) STORES THE WEIGHT ASSI3NED TO EACH DONTCARE BIT. C NDCARE STORES THE NUMBER OF DONTCARE BITS IN ONE VERTEX. NDCARE = DO 5 I = 1, 1 5 BWEIT ( I ) = I = 1 SHIFT = 1 DO 20 I = 1 ,HSPFY IF( LBY . EO. ) GO TO 30 IF( LBY/2*? .EG. LBY ) GO TO 10 NDCARE = NDCARE «■ 1 BWEIT( NDCARE ) = SHIFT 10 SHIP" = 2 * SHIFT LBY = LBY / 2 20 CONTINUE 30 RETURN END C *********** *********** c * C SUBROUTINE CMNL * C * c** ********* *********** SUBRCUT T NE TKNL C THIS SUBR^U^I'JE IMPLEMENTS CONDITIONAL MINIMUM LABELING. C THIS SUBPOUTINE CALLS SUBROUTI NE-DSCAN AND SU9ROUT 111 E-INCMNT . IMPLICIT INTEGER ( A-Z ) INTE3ER*2 LABEL ,DCARE ,MNL ,MXL , CHAIN ,FUNC ,LINK 1 , MINV COMMON II ,N .M ,?F ,FL 1 ,LABEL(10?U) ,DCARE(102<4) ,MNL(*024) ,MXL( 1 02U) 2 ,CHATN(102U) ,STARTL (H) ,ENDL(11) ,FUNC(U096) 3 ,LINK(U09t) ,HXNV(a 10 150 S4IFT=2*SHIFT 160 CONTINUE MNL (PTPB)=L3X IP (PTRB.EO. E»:DL (W) ) PPRB=CHAIN (P-RB) SO TO 2 170 W=W-1 IP( W .GE. I?( II .NE. F.P = MNL V . = 1NT. (1) 180 I? ( YNLX .EO. MNLX = MNLV2 F.p=RP* 1 GO TO 1 80 200 RETURN L.JD -»♦♦**♦♦♦**♦ *♦♦**♦***** GO TO 60 90 V GO TO ) GO TO 30 TO 170 10 200 ) GO TO 200 113 c c c SUBROUTINE CMXL C TH C TH C SU PT VE 20 ******** S'IBPOUTT IS SUBRO 15 SUBF^ BROUTTNE IMPLICIT INTEGER* COMMON , LABEL f CH.\IN ,LINK( INTEGER R3 POINT XIMUM P^ P^ POINT RTEX- B A F = M L3X = LA LBY = DC US PRY = CALL ASI KXL( STA K = 3 ♦ DO ^70 W PTRB L3Y = CALL LBX - LBY = CALL LBXX SHIFT = 16 P T P * * * ********* NE CM V L UT7NE IMP UTINE CAT -DCRMNT. IVTEGEF ( 2 LABEL ,MINV II (102U) ro2u 4095) BW5IT ("0) S TO .HE SSTRLE LA S TO THE ND CONN EC LEMENTS LS SUBPO A-Z ) f DC ARE ,N ,DCA?E ( ,STA?TL , MINV(4 VERTEX-B BEL. VERT EX- A TED TO V CONDITIONAL MAXIMUM LABELING. UTINE-DSCAN, SUBROUTINE-ASIGtfl AND , MNL 1 0~U) ,MXL , CHAIN ,PUNC ,LINK ,RF ,MNL (102U) ,ENDLM 1 ) * ITT ' 096) ,STAR?F('*5) FOP WHICH WE A3E SEEKING FOR THE ,PL ,MXL ("02 4) ,FUNC (4095) ,ENDF 15) BEL( ARE( P* - GN"" ( RTL( 1 STAR STAF II ♦ hspf 1 ) tlJ i ! ) Y,F,LBX,LBY ) ) = LBX WHICH HAS SMALLER WEIGHT BY CNE THAN ERTEX-B BY THE EDGE IN N-CUBE. ) = 2,K = STA?.TL( DC A RE ( ? DSCAW ( LP LABEL DC»PS A SIGN" = LBX W ) TRB ) Y,USP?Y, TRB ) •"RB ) 3PFY,F,L NDCARE,BWEIT ) BX,LBY ) INB DO 22 25 30 40 50 fO IP I p LB CALL P" 1 LA ( PL . ( LBXV XX = L DCR 22 LB LA L= J= LB LA IF LB GO LB IF LA GO LA 1=1, V PBX-. (PTRB (PTRBX/2 RA=PTRB-S X = MXL ( EO. 1 ) G .LB. LAX BY MNT( INE,NDCARE,L -1) /SHIFT *2. EO. PTRBX) GO TO 150 HIFT PTPA ) TO 25 ) 30 TO 150 BXX,F,BKEIT ) :*M Z=LBXX/2* : Z=LAX/2**' 1 T=LBXT/2* J T=LAX/2** (LBT/2*2 = 2*LBZ + i ' TO 5 =2*LB7 LAT/2*2.E0.LAT) GO TO 60 =2*LAZ*1 TO 70 =2*LAZ •EQ.LBT) GO TO 40 114 70 80 90 "00 110 120 130 140 150 160 170 IP (tB.LE.LM GO TO 1 30 IF (RWEIT (J) .EQ.2**L) LB=LB-2 LBXY=LErr-2**M IP (L3.LE.LA) 30 TO 140 GO TO 8 lbxx=lbxx-bweit (J) INC = LB=LB-1 INC = INC ♦ 1 IF (LB.T.E.I.A) GO TO IP ( IN'C/2*2 .EQ. INC LBXX=LBXX-?**M+BWEIT 30 TO 100 LBVT = LB7X-BWEIT (J) GO TO "»00 GO TO 90 120 ) GO (J) TO 110 GO TO 150 J=J*1 GO TO 140 IP (BWEIT (J).NE.2**L) GO TO 140 J=J+1 L=L+1 LPZ=LB/2 IP (L.GE.M) 30 TO ?0 SHIFT=2*SHIFT CONTINUE MXL (P?PB)=LBXT IF (PTFB. EQ. ENDL (W) ) 30 TO 170 PTRB=CHAIN (PTPB) GO TO 20 CONTINUE RETURN ENO ***************** C**** C C SUBROUTINE TM C C**** C c c c c C c c c c c c c c c c c c ******* SU3ROU HIS SUB HE 1A.TI HIS SUB STEP-' STEP-2 STEP-3 STEP-4 STEP-5 STEP-6 IMPLI INTEGE ****** T T N E I foUTTN MUM PE 3 U T I N COM ASS THA P( OBT CBT cov OB'" IN STO THI TV IN PLF THE R*2"' L ,n INTEGER PPTA Y \ TAIN *** MC( E PMT E I ST? IGN T T Y A Kill EFS ATM STE RES S S FUN PRE EAD CO EGE ABE INV RY ( * * * * TFET,* ) B7AINS IRF.EDUNDANT MOS CELL CCK FIGURATION FROM SS T BLE FUNCTI^li. s"made of the'fcllowtng s ucts lapge-cube func ( 2** S "0" CP. " 1 " T C THE VERTE HE D E EXISTS NO VERTEX-Y S = ii 1 ti IX STEPS. (E + II - !) ). X-X WITH D0 2JTO.ES SUCH ATISFYIN3 Y > X AMD S TH S TH EVE S AH P-4. THE TEP vi on Y ST NT EM R ( A L . E SE" OF MINIMUM VECT E SUBSET OF THE SET FY VERTEX WITH 0RI3IN IPFEDUNDANT SUBSET F RESULT TO THE VERTEX CONTAINS EFF.OR CHECKI N VALUES FROM MO.S CEL S STEPS APE DIFFERENT ?RED IN ARFAY-LABEL, TS OF ARRAY-LABEL IS -Z ) DCARE ,MKL ,MXL ORS. ? MINIMUM VECTCPS WHICH AL "0". ROM THE SUBSET OBTAINED IN N-CUBS ( LAPEL ) . NG ROUTINE. L CONFIGURATION OBTAINED FROM THE FUNCTION VALUES E3P0H MESSAGE AND PRINTED. , CHAIN ,FUNC ,LINK 20 ) 115 LOGICA LOGICA cosmo:; 1 ,LA9 2 ,CHA 3 .LIS INTEGE i 2 3 ERROR REPEAT II ( 1 02U) 1024 U096f X( D( 10 ) ,N .M , DCARE(1&24) ,STARTL M") .MINV (4096 I Y1 t I '.'2 • ' • — 5f7« INTEGER BLANK/ FOPM3/ 2 POP16/ 3 FORM9/ PFTARY ( 20 ) •--TI2' , •--U7« , FORM"/ • I ' FOPN.a/ • | • FORM7/ ' • ERFOR rs:iift USPFY IP( FL GO TO « IF ( 1 INPD = SCALE LSHIFI GO TD 5 INPD = SCALE LSHIFT 8 NVTEXL MXVTXL NVTEXF KXVTX? ERROR STEP-"! 5 SP 3 PF EQ. • — 16' • — U1« •--U6' ' / I ' / •-0 ' / •0 • / print buffer for configuraticn. is set if error occurs ** J RP - II ) - II ♦ 1 1 ) GO TO U ,R? ,MNL (1 02U) , ENDLM1) ,SIARTF( i5) i — v 3 t i — v 4 i i — y g i i — ^9 i ' — U3' ,'' — UU' • — U3' ,• --U9' i — Y51 •-X v 0' • - - u 5 • •-U'0» FORM?/ • FORM 5/ • FORMS/ • L xl(: UNC NDF 1 /, 1 02.4) U096) 1C ) PRINTING IN OBTAINED MOS CONSTRUCTING GA NE ::2i TE TWORK. FY . ♦ p 2**M •■ 2** I ♦ I 7*PS : "> * ■■ 2 * ■ ttVT ■ 2 * : NVT .PAL GT. M ) GO TO 5 P - M ( R? - M ) T _ « HIFT J | II - 1 ) ET.l - 1 * INPD EYF - 1 SE. L = INPD ♦ * DO 10 I = 1,1 10 STARTF ( I ) =0 1 = 20 Y = I W = 30 IF ( Y .EO. ) GO TO IF ( Y/2*2 .EO. Y ) w = w ♦ 1 ao Y = Y / 2 '0 GO TO 50 IF LI EN GO TO 60 STARTFf W ♦ ' I S T \ ^ ^ p ( [NK('"END?l JDF( W ♦ 1 ) TO 70 W «■ W ♦ ) = , 1 i c GO TO 40 ) .EO.O ) GO ) ) = I ♦ * TO 60 I ♦ 1 ♦ 1 1 ENDF ( 70 I = I ♦ 1 IF( I.LE.MXVTXF ) GO TO 20 STEP-2 IF( PUNC( STAPTFJ INPD ♦ • ) ) .NE. ) F'JNC{ START? { INPD ♦ 1 ) ) =3 GO TC 110 116 I'Q W = INPD 120 pr" PTRB = STAPTFf W ) 130 IF ( FUN~j P T RB ).NE.O ) GO TO 160 SHIFT = * DO '50 I = \7VPD PTRBX = ( PTRB - 1 ) / SHIFT IF( PTR5V/?*2 .TIE. PTP.BX ) GO TO 140 PTFA = PTRB + SHIFT IF( FUNCf PTPA ).HE.2 ) GO TO 140 FONC ( PTRB ) = 2 30 TO 160 140 SHIFT = 2 * SHIFT 150 CONTINUE F'JNCf PTFB ) = 3 160 IF( PTPB. EO.ENDF ( W ) ) GO TO 170 PTRB = LTNKf PTRB ) GO TO '30 170 K = W - 1 IF ( W.GE.1 ) STEP-3 GO TO 120 K = 1 KMINV = W = INPD ♦ 210 PTRB = START? ( 220 IF ( FUNG f PTRB ) SHIFT = * DO W ) EQ.2 ) GO TO 250 24 I = 1,I>!?D PTRBX = (PTRB - 1 ) / SHIFT IF( PTRB v /2*2 .EO. PTRBX ) GO TO 230 PTRA = a ~RB - SHIFT IFf FUNCf PTRA L-NE.2 ) GO TO 250 230 SHIFT = ^ * SHIFT 2 40 CONTINUE KINV ( K ) = PTRB - 1 NMINV = NKINV ♦ 1 K = K + 1 250 IFf PTRB. EO.ENDF ( W ) ) GO TO 260 PTRB = LINK( PTRB ) GO TO 220 2 60 W = W - 1 I?( W.GE.1 ) GO TO 210 STEP-4 DO 3 i I = 1.NVTEXF 3"0 LINKf I ) = 320 REPEAT = .PP.LSE. DO 34 .7 = 1 , NVTEXP IF ( FUNC ( J ).NE.1 ) GO TO 340 J X = J ~ 1 MINX = MINV ( I ) CALL C01PR ( ,7v ,MINX,G330 ) LINK ( J ) = LINK ( J ) ♦ " GO TO 3U0 330 IFf LTNKf .7 ).NE.O ) GO TO 340 RE?F.\T = .TRUE. 340 C^VTT'lUE IP ( REPEAT ) GO TO 350 117 ) 30 TO 410 NSIRR = I GO TO 16 350 I = I ♦ < GO TO ??0 360 CONTINUE STEP- 5 I = NSIRR - 1 DO 450 I = i ,L DO 4 10 .7 = 1 ,NVTEXF IF ( FUNC ( J ) .NE.1 jv = i _ -J MINX = MIKV J I ) CALL COMPRf JX, MINX, 6410 ) LINK ( J ) = LINK ( J ) - 1 IF ( LTNK( J J.EQ.O ) 30 TO 420 U10 CONTINUE GO TO 4U0 420 IF( FUNC ( J ).NE.1 ) 30 TO 430 JX = J - 1 MIHV = MTNV ( I ) CALL COMPR( JX, MINX, 6430 ) LINK ( J ) = LINK ( J ) ♦ 1 4 30 J = J - 1 IF ( J.GE.1 ) GO TO 420 30 T"> H50 440 MINV ( I ) = -1 450 CONTINUE PRINT MOS GATE CONFIGURATION I BIHH = MXEET = DO 490 I = *• ,NSIRP IF ( MINV ( I ) .LT, NIRR = NIRP + 1 ) GO TO 4 90 460 MTN Y = MTNV ( I ) NFET = IF( MINT .EO. IFf MIMX/2*2 . EQ NFET = NFE m ♦ * 2 ) 30 TC 480 . MINX ) GC TO 470 NFET «XFET ) GO TO 490 470 MINX = MINX / GO TO 460 480 TFE m - T"ET ♦ IFf NFET .LE. MTFET = NFET 490 CONTINUE PRINT 4 "00 4")00 FORMAT ( »0» ) 1 = L = 2 * NIRR - 1 DO 4290 LINE = * ,1 ' IF( LINE/2*? .EO. LINE ) GC TO 4240 PRINT ODD LINE 4101 I = IF ♦ 1 IF( MINV( IF] LINE PRTAPYf 1 ( T ) -LT. ) GO TC 4101 EO. NIRR ) GO TO 4 MO ) = F0RM1 118 GO TO 4120 1110 IF ( NIRR . EO. 1 ) GO TO 4M1 PRTAPY ( 1 ) = P0RM2 GO TO 4^20 U111 PRTARY ( 1 ) = FORM9 4120 K = IP ( PL . EO. ) GO TO . n Y ( ' ) = FC P M » ;o TO 4' , *0 PRTAPY DO 'APY r 1 ) = 4270 J = 1, FOPK2 MX PET 119 0270 PRTAPY ( J + 1 :f( lk!e .eg. prtapy ( ^fet PRTARYf rFF.I JO ^0 '» 43 U280 PRTA°Y( MXFET PRTAPY ( KZFET GO TO U220 0290 CONTINUE IF( NIRR . EQ. STEP-6 ) = BLANK NIRR ♦ 2 ♦ 3 J 30 TO U = FORK 4 = BLANK !80 = F0P18 F0PM6 ♦ 3 i = NKINV ) GO TC 610 THE SIZE OF TPREDUNDANT SUBSET IS SOT EQUAL TO THE SIZE CF MINIMUM VECTOR SET. 1=0 510 J = I*LSHTFT ♦ LA5EL(I*1 ) /SCALE DO 5 20 K = i,rSIHR IF( MTNV ( K ) .LT. ) 30 TO 520 JX = J HINT = MTNVf K ) CALL CViPRf JX, MINX, 6520 ) GO TO 540 520 CONTINUE IF( P? - II ♦ 1 . 3T.M ) 30 TO 520 DCAHX = DCA^Ef I + 1 ) / PSHIFT IFf DC?. D "/?*2 .NE. DCARX ) 30 TO 530 LABELX = LARELf I + * ) / RSHIFT IPf LABEL r !/2*2 .NE. LABELX ) 30 TO 550 EPROH ~ .TRUE. GO TO 5 C 530 LABEL ( I + 1 ) = LABEL ( I + 1 ) + RSHIPT GO TO 55 540 I?( RF - II + 1 -GT. H ) GO TO 550 DC AFX = DCAREf I ♦ 1 ) / RSHIPT IFf DCAPX/2*2 .NE. DC L*3ELZ = LABEL( I + ' IF ( LABEL*/?*? . EQ. L DCARX ) GO TO 550 550 ) / RSHIFT ( LABEL*/?*? '.EO. LABELX ) GO TO 550 ERROR = .TPUE. 1 = 1+1 IFf I .IE. MXVTXL ) GO TO 510 GO TO 660 THE SIZE OF I D ?EDIINDANT SUBSET IS EQUAL TO THE SIZE OF MINIMUM VECTOR SET. 610 1=0 620 J = T*LSHIFT ♦ LABEL (1 + 1 )/SCALE IF ( FUNCf J ♦ 1 ) .EQ. ? ) GO TO 630 IFf RF - T 7 ♦ 1 .GT. 1 ) GO TO 6 50 DCAPX = DCAREf I ♦ 1 ) / FSHIFT IF( DC.\R"/2*2 .NE.- DCARX ) 30 TO 650 LABELX = LA BEL ( I ♦ 1 ) •/ RSHIFT I p | LABEL y /2*2 .SO. LABELX ) 30 TO 650 ERR1R = .TFUE. GO TO 6^0 6 30 IFf RP - II ♦ 1 .GT. M ) GO TO 6 40 DCARX = DCA^Ef I ♦ 1 ) / PSHIFT I p ( DCA?X/2*2 . NE. DCAPX ) GO TO 640 LABELX = LAPEL ( 1*1)/ RSHIFT 120 IFf LABELX/?*2 .NE. LABELX ) GO TO 650 ERROR = .TRUE. GO TO 6*0 6U0 LABELf I ♦ 1 ) = LABEL( I ♦ 1 ) ♦ R3HIPT 650 I = I ♦ " IFf I .LE. M V VTXL ) GO TO 620 660 IF ( ERROR ) GO TO 6^0 GO TO 6? 670 PRINT 6S0.II 660 FCRMMf 'O^'HRPOR IN CONSTRUCTING MOS GATE', 13 ) CALL PRINT ( LABEL, NVTEXL ) PET URN ' 6 90 RETURN END Q** ******** *********** c * C SUBROUTINE M PF * C * Q ******* ************** SUBROUTINE MPF C THIS SUBF^UYTNE OBTAINS MAXIMUM PERMISSIBLE FUNCTICN FROK MINIMUM C LABEL AND MAXIMUM LABEL AND STOPES THE RESULT TO FUNC ( NVTEXF ). IMPLICIT INTEGER ( A-Z ) , DCARE ,MNL INTEGER*? LABEL 1 , M I N V COMMON TI 1 , LABEL f0?U) 2 , CH.'. IN { 1 0?U) 3 ,LINK (U096) KXVTXL = ?**N - 1 NVTE"F = ?** ( N + PSHIFT = 2** ( RF - II ) LSHIFT = 2**( II - 1 DO '0 I = 1, NVTEXF 10 FUNCf I ) = 20 RNL" , M XL , CHAIN ,PUNC ,LINK ,V . M ,DCAFE(102U) ,STAFTL (11) , MINV (U096) TT - 1 ) ) ) RF *MHL (102U) ,ENDL(1') ,STARTF( 15) ,FL ,MXL( 02ti) ,FUNC (CO 96) ,ENDF(15) to no RNL7. = V NL ( T + " ) / PSHIFT K*LX = MXLf I ♦ ' / PSHIFT J = I*L5HIFT + MNLV/2 IF( MNL"'/2*2 .EO.MNLV ) GO TO 30 IFf MX i, r/2* 2 . EO. MXLJI ) GO TO UO FUNC ( J ♦ 1 ) = 2 GO TO UO 30 IF( MVLUTT,NE CCKPMPS 7 ) THIS SUD'^UT'TNE CORPAIPS THE SIZE OF TWO VECTOPS JY AND MINX 10 I p ( MINX/2*2 .EO. KINX ) SC TC 20 IP( JV" , *2 .EO. JX )PETURN1 20 J v = J 7 / 2 MINX = MINX / 2 IFf J7.NE.0 .OR. MINX.NE.O ) GO TO 10 121 RETURN END ■♦♦ ♦**♦** * * * * ***** SUBROUTINE NCU C******* **** * SUBROU" 1 C THIS SUB" C VARIABLES C VERTEX ON IKPLICI INTEGER CO 1 2 3 MX L DO 10 ST I 20 X w 30 IF IF W uo x GO 50 IP CH EN GO 60 ST en 70 I IP RE EN C******* C C SUBR r C******* su C THIS C OK I C IS T MMOS' , I.ABE , C H A T , L I N - K VTXL - N ♦ 10 I ARTL ( = = I = ( X. E ( r/2 = w ♦ = X/2 f *ST? \TN( DL { W TO 7 R1TL ( DL J K = I ♦ ( I.L TURN D **** * *** E •! TIN CHE 3Y INT L »5 10? 1 0? on- 2 ** ****** * BE * * ****** CUBE E ccnstpuct CK THE INPU ONE t ND LIN EGER( t.-Z EEL IMV T I- 1 KS CARE [CUBE ACCORDING TC THE NUMRE!" Or EXTERNAL 'ECTCR IN BINARY FORM ASSIGNED TO EACH THE VERTICES WITH THE SAME HEIGHT. I DC A P. ST - R auiv S* 1 {no ,MNL 02U) 96 , MXL v CHAIN , FUNC ,LINK ,3F ,SNL (102 4) ,ENDL(1!) ,STARTF(15) ,FL ,MXL ('02t) ,FUNC ("0*6) f EN OF (15) ) = O.O ) GC TO 50 *2.E0.X ) 30 TO UO ?TL ( W ♦ 1 ) . EQ.O ) EVDL ( * f 1 ) = I ) ) = I 1 GO TO 60 ♦ 1 W ♦ i ) =1 + 1 ♦ 1 ) = I ♦ 1 E.VXVTXL ) GO TO 20 ********** OUTINE INPUT in IN 1 CO I 2 3 LO IN IN CHAR *** * * 3R0UT SUBP 'I PUT ERMIN T = PLICT :e;er imon , t,;.be ,CHM , LINK GICAL TESoR re;EP ( 90 **** * TNE I U ? I N 2 p P O D \ T E D . FIJNC T INT *2 L T L (102 N -02 (UQ9^ Co *? cu *2 3L ) *** ** NPUT ( E RE* , THE Tynvi ' EGE^ ( ABEL INV T U' a' ) AR ( A N K / ' CHA * * * * * CS,* ) DS DATA I FOLLOWIN "10. J = A-Z ) , DC A RE ,N NTO LABEL ( 2**N ) AND DCAREf 2**N ) G MESSAGE IS PRINTED OUT AND EXECUTION DCAREf 1 6'2 U ) 96 CA D D NO. K = COLUMN NO. ,MNL ,MXL , CHAIN ,FUNC l ,LINK STARTL ( MINV (UO J.1NL (1 02U) , SNDLf 1") r 3rASTF(15) #FL ,!1XL (102U) ,FUNC(U096) 1C ) ',FUNC(< ,ENDF{' ) •/.ZERO/ IACTEP BU • 0* /, ONE/' 1 * /, DCR/'* 1 / FFER FOR ONE CARD. 122 CS IS SET IF THE GIVEN FUNCTIONS ARE COMPLETELY SPECIFIED. CS = .TRUE. IF( ?**N/90*90 .EO. 2**N ) GO TO 10 NCAPD = ?**N/B0 ♦ 1 GO TO 20 10 NCAPD = 2**N/90 20D0 1 UOI- , ,M PRINT ''0,1 FORMAT( { 0' , 'FUNCTION 1 ,13 ) VTEX = i 30 UO 50 60 70 80 DO 100 J = 1 ,NCARD READ '4 , C H A ? FORMAT ( 8 0V1 ) DO 80 K = 1 ,90 IF IF IF I? CHAP ( K CHA^ ( K CHAP K CHA? { K EO. BLANK ) GO TO 1 i EO. ZERO ) 20 TO 7 E • ONE EQ. DCR GO TO 5 ;o TO 60 G° TO 15i LABEL ( VTEX ) = LABEL ( VTEX ) GO TO 70 DCAREf VTEX ) = DCARE ( VTEX ) CS = . FALSE. V^EX = VTEX ♦ 1 CONTINUE ppT.j T qQ.CHAP ♦ 2** ( M - I ) ♦ 2** ( H - I ) ' •,3^,80A1 ) 90 F R 1 A "" ( 100 CONTINUE GO TO 120 IF( J . NE. NCAPD ) GO TO 150 IF] V^EX .KB. 2**N + 1 ) GO TO PRINT *?0,CHAR F C R M A T ( ' • , 9 A 1 ) 1U0 CONTINUE GO TO 170 150 PRINT 160. I, J, f 160 F0R:1AT ( ' 0' , 'I! 110 120 130 150 K NPU' K =',13 ) ERPOR IN DATA CARD',3X,'I =',I3,'J =',13, RETURN"! 170 RETURN END £***************** ****** c * C SUBROUTINE PRINT * C * C*********************** C THIS SU3PCMTirE PRINTS THE CONTENTS OF AN ARRAY( L AD EL , DC AR E, ETC. ). C A PAY IS THE ARRAY TO PF PRINTED. C SIZE INDICATES THE NUMBER OF THE ELEMENTS IN THE AFPAY TC BE C PRINTED. SUBROUTINE PF.TN? ( APAY,SIZE ) IMPLICIT" INTEGER ( A-Z ) INTEGER*? ».PAY( 1 2 U ),PBU P ( 16 ) PRINT 10 10 format ( «o' , • ♦****du«p***** 1 )• DO 6 I = 1.ST7E ARAY"' = AFAY ( I ) J = 16 20 IF ( AFAYY/2*2 .EO. ARAYK ) GO TO 30 PB'JF ( J ) = 1 123 30 no 50 60 g:> to PB'JF A PAY/' J = J I? ( J. GE. PRINT c 0. FORMAT ( ' COUTIUUE PETURH END UO [ J ) =0 = ARAYv; / 2 - 1 ' ) GO TO 20 ( ?BUF { JJ ) ,JJ = 1 ,1 6 ) M6H ) DGRAPHIC DATA r 1. Report No. UIUCDCS-R-77-896 3. Recipient's Accession No. f and Subtitle [GN OF IRREDUNDANT MULTIPLE -LEVEL MOS NETWORKS FOR riPLE -OUTPUT AND INCOMPLETELY SPECIFIED FUNCTIONS 5- Report Date September 1977 ior(s1 CHI -CHUNG YEH 8. Performing Organization Rept. No - UIUCDCS-R-77-896 orming Organization Name and Address jartment of Computer Science .versity of Illinois >ana, 111. 6l801 10. Project/Task/Work Unit No. 11. Contract /Grant No. NSF No. MCS77-097MI insoring Organization Name and Address ;ional Science Foundation )0 G Street, N.W. ihington, D.C. 20550 13. Type of Report & Period Covered Technical 14. iplementary Notes tracts This paper describes a program package for the design of irredundant single- iut or multiple- output MOS networks. This program is an implementation of H.C.Lai's irithms for the design of irredundant MOS networks with a minimum number of MOS .s for any given switching function. The given function can be completely specified ncompletely specified and only uncomplemented external variables are permitted as fork inputs. For multiple- output functions, both the case that the outputs are rioted at the last level and the case that the outputs are restricted at the last vels are included, where m is the number of given functions. The output of the ;ram is a graphic representation of the MOS network configurations. The restric- 3 on the problem size are described and the listing of the FORTRAN program is uded in the paper. f Words and Document Analysis. 17a. Descriptors design, logic circuits, logic elements, programs (computers) entif iers/Open-Ended Terms uter- aided- design, MOS networks, irredundant networks, single-output networks, iple-output networks, optimal networks, MOS cells, MOS, FET. OSATI Field/Group (liability Statement UNLIMITED 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 126 22. Price ITIS-35 (10-70) USCOMM-DC 40329-P7 1 2 5 m c