II UU il MifffnMfflM BH B9Hi3&8 mm fflSM HHHHHffiH HBhI BB&hsSbSIh Hill 1UHH ■Hill an ■HH mi 81 S ■ ■■vHHHH HMHBMflM n il hi Ha BH^d 89 11! HI MR ■T ■■BH ■■■MM BmBBRm ■ SH I 31 H Hi ■H US Wa Bis H Wmm mmXm WSBBBm iilillll wmBmEm HHHR iSBnl ffimm HHBh MMMMM wBfilMm iiffiBB lllilHH i§§|§||| a&S3 El In LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 Ulfcr cop. 2. CENTRAL CIRCULATION BOOKSTACKS The person charging this material is re- sponsible for its renewal or its return to the library from which it was borrowed on or before the Latest Date stamped below. You may be charged a minimum fee of $75.00 for each lost book. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. TO RENEW CALL TELEPHONE CENTER, 333-8400 UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN MAR 1 1 1998 When renewing by phone, write new due date below previous due date. L162 Digitized by the Internet Archive in 2013 http://archive.org/details/microprocessorco812plev uiucDCS-R-76-812 A MICROPROCESSOR-CONTROLLED INTERFACE FOR BURST PROCESSING by ROBERT MILTON PLEVA July, 1976 UIUCDCS-R-T6-812 A MICROPROCESSOR-CONTROLLED INTERFACE FOR BURST PROCESSING BY ROBERT MILTON PLEVA July 1976 Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part by Contract No. USNAVY N001U-T5-C-0982 and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science, at the University of Illinois. Ill 5/0.9+ Tl(pfo ACKNOWLEDGEMENT The author wishes to express his gratitude to his thesis advisor, Professor Michael Faiman, and to IEL Director W. J. Poppelbaum for their support and guidance in this effort. Thanks are also due to Mrs. Kathy Gee for her help with the manuscript, and to the staff of the Information Engineering Laboratory for their valued friendship. IV TABLE OF CONTENTS Page 1 INTRODUCTION 1 1.0 Background 1 1.1 The BURST Representation 2 1.2 BURST Generation Techniques 5 1.3 The Need for "Intelligent" Control .... 10 2 SYSTEM STRUCTURE AND CAPABILITIES 13 2.0 General 13 2.1 Receivers 15 2.2 Transmitters 19 2.3 Crosspoint Network 20 2. It Processor and Support Hardware 21 3 CIRCUIT DESCRIPTIONS 25 3.0 Bus Operation 25 3.1 Receiver Circuits 26 3.2 Transmitters 27 3.3 Crosspoint Switch 28 3. It Processor 28 3 . 5 Memory 29 3.6 Serial Interface 30 3-7 Interrupt Priority 30 h SYSTEM SOFTWARE 31 U.O General 31 h . 1 ISP Command Language 32 It. 1.1 Crosspoint Commands 33 It. 1.2 Read Command 3^ It. 1.3 Write Command 3 It It. 2 BPU Driver Routines 3*t It. 3 Interrupt Servicing 35 It. It 1/0 Routines 36 5 CONCLUSIONS 37 APPENDIX A: CIRCUIT DIAGRAMS 39 APPENDIX B: INITIAL ISP LISTING U8 LIST OF REFERENCES 62 LIST OF FIGURES Figure Page la Packed Burst Format 1+ lb Unpacked Burst Format h 2 Stairstep Burst Encoder 8 3 Two-Decade Vernier Encoder 9 1+a Generalized Model of a Processor- Controlled Burst System lU 1+b MICROBURST System Block Diagram lU Al.l Control Bus Pinouts 1+0 A1.2 Receiver Circuit 1+1 A1.3 Transmitter Circuit 1+2 A1.1+ Crosspoint Switch Circuit 1+3 A1.5 Processor Circuit 1+1+ A1.6 Memory Circuit 1+5 A1.7 Serial Interface Circuit 1+6 A1.8 Interrupt Priority Circuit 1+7 VI LIST OF TABLES Table Page 1 Receiver Addressing 18 2 Transmitter Addressing lo 3 Crosspoint Addressing lo h Memory Space Decoding 23 5 Serial Interface Addressing 23 6 Port Number Assignments 23 1 INTRODUCTION 1 . Background Burst Processing represents a new concept in the encoding, transmission, and processing of analog-derived data. Numerous hardware prototypes have demonstrated the applicability of this technique to a variety of problem areas— e.g. , arithmetic processing, audio and video-bandwidth data trans- 2 3 h mission, audio noise suppression, and even AM and FM demodulation. ' The Burst technique is basically a combination of two elementary notions, namely, that of a unary (radix one) encoding of digital data, and the principle of averaging to obtain increased precision (as in stochastic processing). A more detailed description of the Burst representation will be presented in the next section, but suffice it to say that the aforementioned characteristics suggest the use of Burst processing for applications such as shipboard communications links where wide-bandwidth transmission channels (e.g., coaxial cables or optical fibers) are available and some degree of noise tolerance is a major requirement. As desirable as Burst processing is for a certain class of problems, it is clear that the weighted-binary codings traditional in digital computers are still of primary importance for generalized numerical processing and essentially all processing of non-numeric (e.g., control) information. Demonstration of some degree of compatibility, therefore, between the Burst and weighted-binary modes of data representation is essential if Burst processing is to achieve the status of a viable and useful technique. This is not to argue that Burst systems must always depend upon the proximity of a classical digital system to be useful — indeed a great deal of autonomous con- trol can be provided for in the Burst hardware itself, including magnitude comparison and ranging, peak detection, and error correction. But certain elementary functions — data storage being a prime example — are not well- suited to the Burst representation due to the low information content/bit inherent in the unary encoding. For these functions, traditional techniques continue to be required. Thus, for a very complex system as is represented by the total electronics of a modern naval vessel, compatibility between all modes of data representation, whether analog, binary, stochastic, or Burst, is essential. Such compatibility is necessary to provide all desired functions, as already argued, and provides additional system integrity by allowing cross-monitoring between various subsystems to check for proper operation, and by providing redundant systems to reduce the impact of isolated hardware failures. The MICROBURST project was undertaken to investigate this question of compatibility, and to construct hardware which would allow the interconnection of a hypothetical classical computer system to a multichannel Burst network. The goal was not, of course, to define a completely general-purpose interface, since experience has shown that such "universal" solutions rarely, if ever, fulfill their claim. Instead, the goal has been to define a structure , along with the elementary hardware required for most applications, which would greatly ease the problem of interfacing particular systems. Greatest flexibility and hardware simplicity has been obtained through the use of a low-cost micro- processor as control element for the interface system. 1.1 The BURST Representation The most fundamental notion of Burst processing is that of transmitting a sequence of digits in some radix in such a manner that the average of these digits corresponds to the value of the datum being represented. Of course, since finiteness of the data stream is a practical necessity, the precision of the representation is limited by both the encoding and decoding processes. The attractiveness of the resulting digit-serial representation lies in the possibility of doing on-line manipulation of such data using very simple (i.. e. , essentially one digit) processing elements. A secondary, albeit very important, concept of Burst processing is the unary encoding used to represent the "digits" in the data stream. Such a unary code obviously requires a number of bits (or time slots, in a serial system) equal to the radix; the resulting bit inefficiency is a disadvantage, but the greatly decreased sensitivity to single-bit errors must also be con- sidered when comparing with standard weighted-binary codes. For convenience, the "radix" assumed when discussing Burst processing systems has come to be standardized at ten. Thus the Burst digit (or "frame" as it is often called) consists of ten time slots during each of which either a pulse (corresponding to a unit) or no pulse is transmitted. If all of the units to be transmitted in a given frame occur in a string immediately after the beginning of the frame, the frame is said to be in "packed Burst format." If, on the other hand, units are scattered at random throughout the frame, the resulting format is termed "unpacked. " A schematic representa- tion of these two possible formats is shown in Figure 1. Although the mere ■ representation of data favors neither format, most important processing functions require the packed format, and this has become the standard technique. In Figure 1, the Burst data is shown in a Return-to-Zero (RZ) format; that is, each data bit is separated from adjacent bits by time intervals during which the data line is spacing (i.e., at logical "0"). This format makes oscilloscope interpretation of data streams more convenient, but NRZ (Not- Return-to-Zero) coding may be used equally well. Either of these techniques requires that clocking information be provided on a separate line. Any of FRAME VALUE = 0.5 TIME 10 TIME SL0TS= I FRAME "o"J-ff- (A Figure la Packed Burst Format A ! I FRAME VALUE = 0.5 'A i i TIME SLOT' TIME Figure l"b Unpacked Burst Format the standard self-clocked codings such as phase or frequency modulation may be used to eliminate the requirement for a separate clock line, although these techniques have found little use to date. The Burst representation of negative numbers is another problem which may be approached in several ways. The most straightforward technique is a "sign- plus-Burst-magnitude" scheme which again requires an additional line (carrying sign information) for each Burst data line. This approach has actually been 2 used in at least one Burst prototype , but the need for parallel signal lines in an inherently serial system is highly undesirable. Another possibility is bipolar modulation, wherein positive-going pulses (say) indicate magnitudes greater than zero, and negative-going pulses define negative values. The most direct approach, however, is the biased representation which maps a signal magni- tude of zero onto half-filled Burst frames. This technique has the advantages of requiring no special hardware to couple the logic circuits to the channel, and of requiring no additional signal lines as well. Thus, this mapping has become the favored approach when representation of negative values is necessary. 1.2 BURST Generation Techniques In order to better understand some of the unique advantages of the microprocessor -controlled interface, it will be useful to consider the standard techniques used for generating Burst data from analog sources. Note that for a Burst stream to accurately represent an analog variable, it is necessary that the analog information be effectively at DC with respect to the averaging time needed to obtain the desired precision. Now the averaging time needed to obtain r decimal digits of precision from any deterministic unary-encoded data stream operating at a bit rate of f Hertz is clearly: r t = -^— [ E q. 1.2] d Since the maximum value of the derivative of sin(2frft) is 2iTf, we can insure that the waveform represented will change by a relative amount less — r than 10 if the highest frequency component of the input signal, f , satisfies 2irf„t < 10~ r Mr — Thus, M — 2r 2tt • 10 Note that this is an exceedingly severe restriction, since it implies that for a precision of three decimal digits (.1 percent) and a data rate of f =1 MHz, the highest frequency component of the input signal must be limited to f <_— Hz = .15 Hz. This limitation applies only when the analog variable is presented directly to a Burst encoder without the benefit of sample- and-hold circuitry. If S/H hardware is included, of course, then the band- width restriction is defined only by the Nyquist criterion requiring two samples per cycle of the highest frequency component, and the time necessary to output this data to the required precision (t ). In this case, it is easy to see that: f , f M,S/H " 2 . 1Q r Therefore, if an S/H-equipped encoder is used with the figures of the previous calculations, we find that f need only be limited to 500 Hz or less — a bandwidth increase of greater than three orders of magnitude. The conclusion, then, is that sample-and-hold circuitry is a practical necessity for high precision representation of even audio-frequency signals due to the very long time needed to encode the value. We shall assume, then, that these bandwidth restrictions are adhered to as we describe the encoding techniques in the following paragraphs. Figure 2 demonstrates the operation of the simplest Burst encoder based upon a staircase waveform generated by shifting ones into a Block Sum Register. [Note: A Block Sum Register, or BSR, is simply a shift register with each bit position connected to a current source; the currents are summed on a bus and converted to a voltage output. It is thus simply an unweighted (unary) digital- to-analog converter with a shift register.] The encoder merely outputs a one during each bit time until the staircase voltage exceeds the analog input signal. When completely filled, the register is direct cleared and the cycle repeats. The encoder thus produces a continuous Burst stream, which is however accurate to only 10 percent (the resolution of a single frame) since successive frames represent different samples of the input signal. In this case averaging over a number of frames does not necessarily increase the precision of the result. A straightforward extension of this scheme called the "vernier encoder" can be used when greater precision is required. Essentially a cascade of simple encoders having a decade relationship between fullscale output currents, the circuit operates as illustrated in Figure 3. Although the circuit is simple and produces a correct stream average, its output does not converge to the correct result as quickly as possible as can be seen by considering the encoder output for a signal value of 3.2. The output stream in this example consists of 2 frames of value k followed by 8 frames of value 3, at which point the "ramp" registers are cleared and the cycle repeats. Fastest convergence, however, would clearly be provided if the 10-frame output sequence were 3343333^33 . While such an optimal decomposition is very difficult to CLOCK- CLEAR N-BIT SHIFT REGISTER N-l EQUAL CURRENT SOURCES R — ii wv^ V. \ CURRENT SUMMING BUS ANALOG INPUT COMPARATOR CLOCK BLOCK , SUM REGISTER BURST OUTPUT 1 1 Vs VOLTAGt AT R -^ INPUT 'in LEVEL 1 Figure 2 Stairstep Burst Encoder CLOCK ANALOG INPUT RAMP BURST OUTPUT VERNIER EXAMPLE OF VOLTAGES AT P: 1ST BLOCK 2ND BLOCK 3RD BLOCK .... 10TH BLOCK .00 .01 .02 .... .09 .10 .11 .12 19 .20 .21 .31 .22 29 .30 .32 .42 39 .40 .41 49 .50 .51 .52 59 .60 .61 .62 69 .70 .71 .72 79 .80 .81 .82 89 .90 .91 .92 99 4 4 3 . . . . .... 3 Figure 3 Two-Decade Vernier Encoder 10 obtain from simple analog-to-Burst generation circuitry, the MICROBURST inter- face provides Burst outputs having this property, as will be discussed in more detail in later sections. 1.3 The Need for "Intelligent" Control As was briefly mentioned earlier, the MICROBURST interface incorporates a small computer system — built around a standard microcomputer chip — functioning as a control element. Since the inclusion of such an "intelligent" control device adds considerable cost and complexity to the hardware, it is necessary to define just how its presence will enhance the performance of the final system. Some of the more obvious and important justifications for the micro- processor-based architecture are discussed in this section. Since Burst-encoded data is represented by bit streams which are, in principle at least, doubly infinite in time scale, it is usually necessary that each variable be transmitted along a separate wire. Various time-division multiplexing schemes can be used to conserve data lines, but such methods tend to negate the most important feature of Burst processing, which is circuit simplicity. Also, such multiplexing demands that synchronization be rigorously maintained which again contradicts the inherently synchronization- free nature of the Burst representation. Ideally, one would like to use a smaller number of wires, each carrying only a Burst value which is needed for processing at that time. In this way, the demultiplexing problem is reduced to merely activating the appropriate processing devices after the corresponding data has been established on the lines. There is thus an immediate need for control in such a system to perform the channel switching functions and to enable the appropriate processing subsystems. 11 A related problem is that of reconfiguring a Burst system to perform tasks other than those for which it was originally designed. Here again the most flexible solution is to partition the system into an array of Burst Processing Units (hereafter referred to as BPU's) connected by data lines carrying Burst-encoded information. If these data lines can be switched as mentioned above and the operation of the various BPU's controlled by a pro- grammed device, then the entire system can be readily configured to perform any functions for which the appropriate BPU's are available. Then, too, it must be recognized that there are many operations which are more readily performed by traditional computer methods than by constructing equivalent BPU's. Examples of such operations are: nonlinear transformations, statistical analyses, evaluation of complex functions, and long-term storage. Certain processing systems may tend to require large numbers of simple arithmetic operations and only very few special operations of the type just described. Systems of this type may benefit from the simplicity of performing arithmetic on Burst-encoded data while requiring only limited processing (for the special functions) from a traditional computer. Furthermore, as was briefly alluded to in the previous section, it is possible to use the processing capability of a small computer to advantage in actually improving the characteristics of generated Burst streams. In particular, we can "arrange" the frame values in such a way as to maximize the rate of convergence of the stream average towards the exact value to be represented. This may or may not be a significant advantage in any particular application (it will be of value only if the stream average is formed sequentially rather than all at once, as can be done by using "long" BSR ' s or "perverted-adder" summing trees), but it is easily obtained if a small computer is available. 12 A final point, but one which is especially important until the details of the Burst representation have become firmly standardized, is the flexibility in the interpretation of Burst-encoded data afforded by the inclusion of a classical processing element. In particular, the various approaches to the representation of negative numbers discussed earlier can all be accommodated with ease if the received data is interpreted by a programmed device. The use of differing bias (offset) values then requires only a slight program modification; even different representations within a single system could be handled if so desired. The high-level of control over hardware functions afforded by the use of a classical processor allows the interface device to act, in effect, as a general "Burst simulator". What this means is that even networks which are not required to interface to computer systems in normal operation can be debugged and evaluated "off-line" by using the interface to represent the "Burst world" within which the network is designed to operate. In this sense the device is useful as "programmed instrumentation" in the development of Burst hardware. This is only a partial list of the benefits to be derived from including a small computer in the hardware of a general -purpose Burst interface system. These advantages can be largely summed up in a single word — versatility. Any procedure which can be programmed can be readily implemented in such a system. This includes, but is obviously not limited to, such desirable capabilities as automatic scanning of channels, checking against predefined limits, dynamic reconfiguration, etc. Thus the inclusion of an "intelligent" control mechanism — in this case a one-chip microprocessor — is a powerful addition to the interface hardware. 13 2 SYSTEM STRUCTURE AND CAPABILITIES 2.0 General The MICROBURST interface was designed to provide as much capability as possible with existing hardware while allowing other functions to be implemented with a minimum of additional effort. The basic architecture adopted follows the general form shown in Figure k (a); a number of BPU's (in this case 5 are initially provided) interfacing external Burst data channels, with each BPU's activities controlled by a Central Processing Unit. To realize the goal of simplified substitution of other BPU's, a common control bus scheme was utilized. The control bus layout and protocol actually used borrow heavily from another in-house effort — the MUMS project. MUMS (for Modular Unified Microprocessor System) is an attempt to define a very general microcomputer system architecture which is capable of supporting a wide variety of processors, system modules (e.g., read/write and read-only memories, direct memory access channels, etc.), and peripheral devices. Although the current (MUMS III) standard is a more general and powerful design, the MICROBURST bus is based on an earlier version (MUMS II ) which is completely adequate for the specific application and has the advantage of using the in-house standard 80 contact circuit cards and edge connectors. Also, two modules constructed for the MUMS II prototype system — a Teletype compatible serial interface card and an interrupt priority card — were immediately available, thereby avoiding unnecessary duplication of effort. The basic interface function is one of data translation — i.e., generating Burst outputs from binary-coded data and interpreting Burst stream inputs in a computer-compatible format. Also, the ability to perform channel switching operations is an important requirement in Burst systems, as already noted. Ill • • BPU MICRO- PROCESSOR l COMMUNI- CATIONS UNIT > Figure Ha Generalized Model of a Processor- Controlled Burst System TELETYPE *> 6502 PROCESSOR (4 SERIAL INTERFACE + INTERRUPT CARD ) zs DATA ADDRESS- xz INTERFACE SOFTWARE PACKAGE (ISP) Figure hh BURST RECEIVER V^. BURST RECEIVER BURST TRANS- MITTER "a" 4X4 BIDIRECTIONAL CROSSPOINT SWITCH © BURST CHANNELS MICROBURST System Block Diagram BURST TRANS- MITTER "B" © © 15 Thus, the interface circuits included in the MICROBUEST hardware consist of two Burst generators ("transmitters") and two receivers, and a dual 1| x I bidirectional crosspoint switch which permits arbitrary interconnections of Burst channels to interface units. Four Burst channels may thus be interfaced directly with the device: more channels may be supported by extending the crosspoint network. The assignment of channels as inputs and outputs is defined by the state of the switching matrix. A block diagram of the interface hardware is shown in Figure h (b). An ASR Model 33 teletype is used for input and output of commands and data, so front panel controls and indicators are minimized. There are two front-panel switches — one is a latching pushbutton which can be used to switch primary power to external power supplies, and the other is a reset button (momentary contact) which pulls the system reset line low when depressed. Two indicator arrays on the front panel show the status of the individual interface circuits. Each transmitter and receiver has a LED on the panel which indicates when that particular module is active. Also, a k x h array of LED's is used to indicate which nodes of the crosspoint array are currently closed. Six connectors on the front panel provide input and output data to the device. Four 5 -pin connectors carry clock and Burst data signals to and from the interface. A single 25-pin socket is wired to accept the Teletype plug. An identical connector is also provided for possible future use as a parallel input/output port. 2.1 Receivers Since the precision of a Burst-encoded representation increases with the number of frames averaged (up to the limit imposed by the encoding process), it is clear that greater precision requires more time [Eq. 1.2]. It is 16 therefore undesirable to perform all channel "read" operations to a fixed precision, since this implies an unnecessary reduction in repetition rate when lower precision values will suffice. For this reason the averaging time to be used is a programmed quantity specified as a number of decimal digits (l, 2 or 3) at the beginning of each read operation. This allows a maximum precision of .1 percent, which probably represents the upper limit of practicability in analog-derived Burst systems based on the long averaging times and tight encoder component tolerances necessary. In order to make the completed interface as useful as possible in future Burst-processing research efforts, it was decided that the receivers should include some capability to "diagnose" a Burst data stream, i.e., to check the stream characteristics during a read operation for illegal or other significant format conditions. Since the receivers function basically as counters, they will provide a correct interpretation of any unary-encoded data, regardless of the specific data format involved. The notion of the "packed" Burst format has already been introduced (Sec l.l) — its importance to the hardware simplicity of many processing functions makes it an essential characteristic of the Burst representation. If we define an unfilled time slot followed by a filled slot as a "SYNC" transition, it is clear that unpacked Burst frames will have two or more SYNC periods in a 10-bit time interval. The occurrence of no SYNC transitions in a frame interval represents a "Loss-of-Sync" (LOS) condition. It should be noted that LOS is not an invalid Burst format — frame values of and 1 (in a 10-slot system) will both result in LOS conditions — in the former case all slots are zeroes and in the latter case all slots are ones. IT Although LOS is not in general an error condition, several specialized Burst devices have been proposed which do require that frame synchronization he maintained. In such cases the LOS status signal can be used to detect this undesired condition. To isolate the source of the LOS condition two additional status hits Z (zero frame) and F (full frame) are maintained which flag the appearance of 10 consecutive zero or one data hits, respectively. A fourth status hit, U, flags the occurrence of "unpacked" data occurring in the Burst stream. This condition is sensed by detecting multiple SYNC transitions within a frame interval. Operation of the receivers is a simple procedure. Address bits Ao-A are set to the I/O page address, bits A -A„ are set to the appropriate receiver port number, and bits A and A are set to indicate the desired precision of the read operation (see Table 1 for receiver addressing conventions). When a write operation is performed to this address, the counter chains are cleared and the Burst clock and data lines are enabled. Upon completion of the appropriate counting interval (10, 100, or 1000 clock times), further counting is inhibited and an interrupt is requested to the priority card. Each receiver represents four input ports to the processor for reading data. The address is set up as for the "start" operation just described with bits A and A now specifying the data items to be read. Each data value is a four-bit quantity with the digits appearing in standard BCD format. The status word is composed of the four flags already described: Bit Flag 3 U 2 LOS 1 Z F 18 A_ R/W R READ STATUS REG 1 R READ LSD 1 R READ M D 1 1 R READ M S D 1 W INIT READ , PREC= 1 1 W INIT READ , PREC=2 1 1 W INIT READ , PREC=3 Table 1 Receiver Addressing A, A R/W W LOAD 8 BITS 1 W LOAD 4 BITS 1 X W LOAD BASE a START Table 2 Transmitter Addressing A, A o R/W W LOAD Tl MASK 1 W LOAD T2 MASK 1 W LOAD Rl MASK 1 1 w LOAD R2 MASK Table 3 Crosspoint Addressing 19 These data are typically read and processed as part of the interrupt servicing routine. 2.2 Transmitters In order to understand the mode of data representation within the Burst transmitters, it is necessary to make an important observation: in any "averaging sequence" (sequence of digits a. which is used to represent a value 1 n x as x = — I a. ) which minimizes the error in the approximation as n is i=o increased, the digits in the sequence will take on only one of two values — namely the digit values which "bracket the value of x. This is a simple and intuitive notion and does not warrant a formal proof here. The idea is simply that no 5's will occur in a sequence which is to represent the value 2.3 with minimum error at each step. When the fact is realized, then it becomes clear that a minimum-error sequence can be efficiently represented by a bit string (equal in length to the cycle length of the output sequence) and a single digit value. Then the averaging sequence to be produced is defined by the simple rule that a zero value in the bit string specifies that a frame value equal to the stored digit value be output, while a one encountered in the bit string requires that a frame value one greater than the stored value be produced. A Burst stream is represented in exactly this fashion within the transmitter hardware. Since a "ten-slot" frame is assumed, a four-bit counter is used to hold the "BASE DIGIT." Each bit of a 100-bit recirculating shift register is used to represent a frame value equal to the BASE DIGIT (if the bit is a zero) or a frame value of BASE DIGIT + 1 (if the bit is a one). 20 The actual unary frames are produced from the frame value counter by straightforward combinational and sequential circuits. As each 10-slot frame is completed, the shift register is circulated one bit position and the frame value counter is adjusted appropriately. It should be mentioned here that the circuitry used to generate the unary frames is incapable of producing a frame value equal to zero (a full frame is produced in this case). This means that values in the range <_ x < .100 cannot be represented. However a full decade of values may still be produced (.100 <^ x < 1.000), and since the Burst format is inherently a "scaled" representation this was not deemed to be a deficiency. Thus the use of the transmitter requires only that the 100-bit shift register be loaded with the desired bit pattern and the BASE DIGIT be set. (Transmitter addressing conventions are detailed in Table 2.) Since each shift register bit represents an entire Burst frame, the use of 100 bits in -3 the register implies a Burst output represented to a precision of 10 which is consistent with the maximum receiver resolution of 3 decimal digits. Each transmitter has an on-board clock generator which is disabled when- ever the shift register is loaded and enabled when a BASE DIGIT is entered. 2.3 Crosspoint Network The It x 1| crosspoint switch has been included to allow efficient switching of data between the four Burst channels supported by the device and the four transmitter/receiver circuits which it incorporates. This array is actually two identically constructed and controlled k x k networks, with one handling data channels and the other carrying clocking information. 21 The switches used are CT)ho66 CMOS analog switches, which are useful because of their low on-resistance , high off-resistance, and "bidirectional nature. Four such chips (with four switches per chip) are used in each array. Sixteen flipflops store the control (switches on/off) data for each node, and drive the front-panel switch status lights. Addressing formats for referencing the crosspoint control flipflops are described in Table 3. Data may be routed through several successive nodes to achieve whatever interconnection pattern is desired. Up to four nodes may be traversed without severe degradation of the signal waveforms , but greater numbers tend to intro- duce excessive series resistance into the signal path and provide unreliable operation. 2.U Processor and Support Hardware The central processor utilized is the MOS Technology Inc. MCS 6502. This is an 8-bit n-channel MOS device which operates off a single supply of +5 volts and has a basic clock rate of 1 MHz. Four particular attributes suggested an advantage for the 6502 over other processors then available. They are, in order of importance: 1) Low Cost — by far the lowest (twenty dollars in unit quantities) of any comparable 8-bit device. 2) Decimal Arithmetic Capability — which simplifies some of the decimal-oriented functions performed by the interface software. 3) Multiple Addressing Modes — this tends to reduce program length for functions such as table-driven routines and string operations. h) Zero Page Addressing — which leads to a further reduction in program size when all or part of the program workspace can be confined to page zero. 22 To create a usable computer system from a device of this nature requires that a moderate amount of additional circuitry be added external to the processor chip itself. Naturally, memory must be provided for program and data storage. More chips are required, however, for such purposes as buffering of all address, data, control, and clock lines, and generation of I/O and memory control signals which conform to the protocol defined for the bus structure in use. The addition of more sophisticated capabilities such as hardware interrupt arbiting, direct memory access, single cycle/instruction execution, etc., each requires that external logic be implemented. Four circuit cards comprise the processing section of the interface. These are a processor card, a memory card, an interrupt priority card, and a serial interface card. The processor and memory cards constitute the actual "computer". Programs are loaded into 2,0U8-bit ROM's of the 1702 type which are inserted into one of eight sockets on the memory board. Each socket represents a different "page" (256-word segment) of the memory addressing space. The memory address decoding is such that all possible l6-bit addresses map into one of ten physical pages of memory (or the I/O device "page" which is decoded on the processor board.) Of these, eight are ROM's as already mentioned, and two pages are read/write memory used for program workspace. The ROM pages are indicated by a one in address bit 15; the individual ROM is then selected by bits An, A , and A (see Table h) . A zero in A specifies a reference to read/write memory, and Aq then selects between page "zero" and "one." Address bits A_-A 7 are used as a common address bus to all memory chips . 23 A * A,4 A,3 A 1? A„ A l

t> 8 — 8 — ■ ■ X ir: -j o => -I s 5 3 8 r- ^ — tfi •H (1) O a; CM H •H 'I -I ,1 k2 3 a ■H O Jn -p -p •H 6 cd EH ro 0) •H U3 CO < CO o z o < _i CO < "a "5 ) O | V£5 CD U w •H P-h §3 k6 I I YYVV > Q_ LU O UJ -J 5 a i/> o Z O a. 3 v u ■H O QJ O a) Cm u a> -p B M •H 0) H bO hi m pj gP i>h n n-|i. Hi- Hi- Hi- Hi- Hi- Hi- -p •H Pi O •H O !» -P •H Sh O ■H fH -p Ph *H -' in VM/* — " — ■Hi- Ujw> 1—W\flM- in WVlM- h& APPENDIX B : INITIAL ISP LISTING ^9 PAGE ZERO MAP Hex Address 00: 01 02 03; OA: OB: oc 10 11: 12 15 16: IT 18 20 21 30 31: 32: 33: BO Bl: B2 B3 Variable Name STATE . LO STATE . HI NEXTSTATE.LO NEXTSTATE . HI NUM1 NUM2 NUM3 EFLAG EMSGINDX PREQZ OP DEVICE CHANNEL PRECISION OUTFILE . LO OUTFILE.HI MAP MAP + 1 MAP + 2 MAP + 3 TEMP TEMP + 1 TEMP + 2 TEMP + 3 50 PAGE ZERO MAP (cont'd. Hex Address F0 Fl F2 F3 FU F5 Variable Name PORT PVAL PVAL* SIGNACC ACC BITS 51 PAGE = F8 MAIN: LDAI n 11 JSR WRITECHAR LDAI gOPCODE.LO STAZ STATE. LO LDAI gOPCODE.HI STAZ STATE . HI LDAI *RESET STAZ EFLAG NEXT: JSR READCHAR CMP I "RTN" BNE PO JMP EXEC PO: BITZ EFLAG BMI NEXT JMPI STATE OPCODE : CMPI ii ii BNE PI JMP NEXT PI: CMPI „ c „ BEQ FIX CMPI "D" BNE CHECK FIX: LDXI gDEVICE.LO STXZ NEXTSTATE . LO LDXI gDEVICE.HI STXZ NEXTSTATE . HI JMP OUT CHECK: CMPI "W" BNE LASTCHANCE LDXI @TRANS . LO STXZ NEXTSTATE . LO JMP OUT LASTCHANCE : CMPI "R" BNE ERROR1 LDXI @RCVR.LO STXZ NEXTSTATE. LO LDXI gRCVR.HI STXZ NEXTSTATE . HI OUT: LDXI @BLANK.LO STXZ STATE . LO LDXI @BLANK.HI STXZ STATE. HI STAZ OP JMP NEXT ERROR1 : LDAI *SET STAZ EFLAG LDAI ERR1 STAZ EMSGINDX JMP NEXT ; WRITE PROMPT CHAR ;SET STATE = OPCODE ; CLEAR ERROR FLAG ;WAIT FOR TTY_ENTRY ;EXECUTE IF "RETURN" ; IGNORE IF ERROR SET ;GO TO CHAR ROUTINE ;SKIP IF BLANK ; BRANCA IF NOT XPT OP ;SET NEXTSTATE = DEVICE ; "WRITE" OPCODE? ;SET NEXTSTATE = TRANS ;"READ" OPCODE? ; INVALID OPCODE ;SET NEXTSTATE = RCVR ;SET STATE = BLANK ; STORE OPCODE ;NEXT CHARACTER ;SET ERROR FLAG ; STORE MSG POINTER ;NEXT CHARACTER 52 BLANK: CMPI " " BNE ERR0R2 LDAZ NEXTSTATE . LO STAZ STATE. LO LDAZ NEXTSTATE. HI STAZ STATE. HI JMP NEXT ERR0R2: LDAI *SET STAZ EFLAG LDAI ERR2 STAZ EMSGINDX JMP NEXT DEVICE P2 P3 PU ERROR3 DEVNO P5 P6 CMPI BNE JMP CMPI BNE LDXI STXZ BPL CMPI BNE LDXI STXZ LDXI STXZ LDXI STXZ JMP LDAI STAZ LDAI STAZ JMP LDXI STXZ LDXI STXZ CMPI BNE INCZ BPL CMPI BNE LDAI CMPZ BEQ LDAI CMPZZ BNE P2 NEXT Mm" P3 00 DEVICE PU "R" ERR0R3 02 DEVICE @DEVNO . LO STATE . LO gDEVNO.HI STATE . HI NEXT *SET EFLAG ERR3 EMSGINDX NEXT gBLANK.LO STATE . LO gBLANK.HI STATE . HI tip" P5 DEVICE P6 ii -i it ERROR h „ c „ OP XPTOP "D" OP READWRITE ;ERROR IF NONBLANK ;TRANSFER NEXTSTATE. ; ... TO STATE ;NEXT CHARACTER SKIP IF BLANK TRANSMITTER? CHECK IF RCVR ;DEVICE = TRANS ^RECEIVER? ;ERROR IF NOT ;DEVICE = RCVR ;SET STATE = DEVNO ;NEXT CHARACTER ;SET STATE = BLANK ;DEVICE #2? jIF SO, ADJUST "DEVICE" ;DEVICE #1? ;ERROR IF NOT ;IS OP C OR D? ; BRANCH IF NOT 53 XPTOP: LDAI @CHAN . LO STAZ NEXTSTATE . ,LO LDAI gCHAN.HI STAZ NEXTSTATE. HI JMP NEXT READWRITE : LDAI "W" CMPZ OP BNE READ? LDAI gDECPT.LO STAZ NEXTSTATE . LO LDAI @DECPT.HI STAZ NEXTSTATE . ,HI JMP NEXT READ? : LDAI @PREC . LO STAZ NEXTSTATE. LO LDAI gPREC . HI STAZ NEXTSTATE. HI JMP NEXT PAGE = F9 S ERRORU : LDAI *SET STAZ EFLAG LDAI ERRU STAZ EMSGINDX JMP NEXT PREC: CMPI it it BNE PT JMP NEXT PT: CMPI tt-i tt BCC ERROR 5 CMPI n^ii BCS ERROR 5 ANDI 07 STAZ PRECISION LDAI @EXEC . LO STAZ STATE. LO LDAI gEXEC.HI STAZ STATE. HI JMP NEXT ERROR 5: LDAI *SET STAZ EFLAG LDAI ERR 5 STAZ EMSGINDX JMP NEXT ;SET NEXTSTATE = CHAN ;NEXT CHARACTER ; "WRITE" OP? j IF NOT, IT'S A READ ;SET NEXTSTATE = DECPT ;NEXT CHARACTER ;SET NEXTSTATE = PREC ;NEXT CHARACTER ;ERR0R: INVALD DEVICE NUMBER ;SKIP IF BLANK ;CHAR < 1? ;ERROR IF SO ;CHAR >_ U? ;ERROR IF SO ; STORE PRECISION ;SET STATE = EXEC ;NEXT CHARACTER ;ERROR: ILLEGAL PRECISION 5h CHANNEL : CMPI it ii BNE P8 JMP NEXT P8: TAX LDAI 01 CPXI "A" BEQ MATCH ASLA CPXI "B" BEQ MATCH ASLA CPXI "C" BEQ MATCH ASLA CPXI „ D „ BNE ERR0R6 MATCH: STAZ CHANNEL LDAI @EXEC . LO STAZ STATE . LO LDAI @EXEC . HI STAZ STATE. HI JMP NEXT ERR0R6 : LDAI *SET STAZ EFLAG LDAI ERR 6 STAZ EMSGINDX JMP NEXT TRANS: CMPI ii ii BNE P9 JMP NEXT P9: CMPI llrpll BEQ plO JMP ERR0R3 P10: LDAI @DEVNO . LO STAZ STATE . LO LDAI gDEVNO.HI STAZ STATE. HI LDAI 00 STAZ DEVICE JMP NEXT RCVR: CMPI ii ii BNE Pll JMP NEXT Pll: CMPI "R" BEQ P12 JMP ERR0R3 P12: LDAI @DEVNO . LO STAZ STATE . LO LDAI gDEVNO . HI STAZ STATE. HI LDAI 02 STAZ DEVICE JMP NEXT SKIP IF BLANK FORM CHANNEL MASK LOAD MASK BIT CHAR = A? IF SO, EXIT SHIFT MASK BIT CHAR = "B"? IF SO, EXIT SHIFT MASK BIT CHAR = "C"? IF SO, EXIT SHIFT MASK BIT CHAR = "D"? IF NOT, ERROR STORE MASK SET STATE = EXEC ;NEXT CHARACTER ;ERROR: NO SUCH CHANNEL ;SKIP IF BLANK ;DEVICE A TRANS? ;IF NOT, ERROR ;SET STATE = DEVNO ;DEVICE = TRANS ;NEXT CHARACTER ;SKIP IF BLANK ;DEVICE A RCVR? ;IF NOT, ERROR ;SET STATE = DEVNO ;DEVICE = RCVR ;NEXT CHARACTER 55 DECPT: CMP I M ii BNE P13 JMP NEXT P13: CMPI ti ii BNE ERRORT LDAI 00 STAZ NUM1 STAZ NUM2 STAZ NUM3 LDAI gNUMl.LO STAZ STATE . LO LDAI @NUM1 . HI STAZ STATE. HI JMP NEXT ERRORT : LDAI *SET STAZ EFLAG LDAI ERR7 STAZ EMSGINDX JMP NEXT NUM1: CMPI "0" BEQ ERROR8 CMPI ti -i ii BCC ERRORT CMPI "9"+l BCS ERRORT AND I OT STAZ NUM1 LDAI @NUM2 . LO STAZ STATE . LO LDAI @NUM2 . HI STAZ STATE . HI JMP NEXT ERROR8 : LDAI *RESET STAZ EFLAG LDAI ERR8 STAZ EMSGINDX JMP NEXT NUM2: CMPI it it BNE Pl4 LDAI gEXEC.LO STAZ STATE . LO LDAI gEXEC.HI STAZ STATE . HI JMP NEXT PAGE = FA PlU: CMPI "0" BCC BADNUM CMPI M 9"+l BCS BADNUM AUDI OF ;SKIP IF BLANK ;CHAR A PERIOD? ;IF NOT, ERROR ;INTIALIZE NUM1-3 ;SET STATE = NUM1 ;NEXT CHARACTER ;ERR0R: INVALID VAL SYNTAX ;NUM1 = 0? ;IF SO, UNNORMALIZED ;NUM1 < 1?. ;IF SO, ERROR ;NUM1 > 9? ;IF SO, ERROR ; STORE IT ;SET STATE = NUM2 ;NEXT CHARACTER ; ERROR: INVALID VAL SYNTAX ;CHAR A BLANK? ;IF SO, READY TO GO :SET STATE = EXEC ; CHECK FOR VALID NO, 56 STAZ NUM2 LDAI @NUM3 . LO STAZ STATE. LO LDAI @NUM3.HI STAZ STATE. HI JMP NEXT BADNUM : JMP ERRORT NUM3: CMPI 11 ti BEQ TERM CMPI "0" BCC NOPE CMPI "9"+l BCS NOPE ANDI OF STAZ NUM3 TERM: LDAI @EXEC . LO STAZ STATE . LO LDAI gEXEC.HI STAZ STATE. HI JMP NEXT NOPE: JMP ERRORT PAGE = FB XPT: LDXZ DEVICE LDAI "C" CMPZ OP BEQ CONN DCON: LDAZ CHANNEL EORI FF ANDZ,X MAP STAZ,X MAP STA,X XPTSWITCH RTS CONN: LDAZ CHANNEL CPXI 02 BCC CHEK ORAZ,X MAP STAZ,X MAP STA,X XPTSWITCH RTS CHEK: TXA EORI 01 TAY LDAZ CHANNEL AND,Y MAP BNE CONFLICT LDAZ CHANNEL ORAZ ,X MAP STAZ,X MAP STA,X XPTSWITCH RTS ; STORE IT ;SET STATE = NUM3 DONE IF BLANK IN RANGE? IF NOT, ERROR. ; STORE IT ; READY TO GO ;SET STATE = EXEC ;NEXT CHARACTER ;GET DEVICE CODE ;0P A CONNECT? IF NOT GET MASK INVERT IT "AND" WITH CURRENT MASK STORE NEW MASK WRITE TO XPT OP IS CONNECT TRANS CONNECT? IF SO, BRANCH "OR" IN NEW MASK STORE NEW MASK WRITE TO XPT ; REFERENCE OTHER TRANS GET NEW MASK "AND" WITH OTHER T-MASK NO CONFLICT IF ZERO "OR" IN NEW MASK STORE NEW MASK WRITE TO XPT 57 CONFLICT: LDAI MSG JSR OUTPUT LDAI "RTN" JSR WRITECHAR LDAI "LF" JSR WRITECHAR RTS RCVRSET : LDXZ DEVICE LDAI 60 CPXI 03 BCC RCVR1 LDAI TO RCVR1 : ORAZ TAX PRECISION STA,X I/O INF: SEC BCS INF DCOMP: LDAZ DEVICE BEQ TR1 LDAI 50 STAZ PORT BPL INIT TR1: LDAI ko STAZ PORT TWIT: LDAZ ASLA ASLA ASLA ASLA NUM2 ORAZ NUM3 STAZ PVAL LDAI 99 SEC SED SBCZ PVAL CLC ADCI 01 STAZ PVAL* LDAI 00 STAZ ACC STAZ SIGNACC LDXI OD LDYZ PORT BLOOP : DEX BEQ EXIT JSR INTRPSTP LDAZ BITS STA,Y I/O JMP BLOOP ;WRITE CONFLICT MSG i RESET TTY TO LHS ;GET DEVICE CODE ;LOAD Rl PORT NO. ;IS IT Rl? ;IF NOT, LOAD R2 PORT NO. ;FORM PROPER ADDRESS... ;...FROM PORT NO. AND PREC ;WRITE TO RCVR ;WAIT FOR INTERRUPT ;GET DEVICE NO. ; BRANCH IF Tl ;T2 PORT NO. ;T1 PORT NO. ;GET MIDDLE DIGIT MOVE TO H.O. FOUR FORM PACKED BCD KEEP FOR INTERP. ;MODE=DECIMAL ;100 - PVAL ;KEEP FOR INTERP. ilNIT FOR INTERP. CALL INTERP ROUTINE GET RESULTS WRITE TO TRANS 58 EXIT: JSR INY INTRPSTP LDAZ BITS STA,Y I/O LDAZ NUM1 INY STA,Y I/O CLD RTS INTRPSTP : TXA PHA LDXI 09 NEXT: DEX BEQ DONE BITZ SIGNACC BMI NEG POS: CLC ROLZ BITS LDAZ ACC SEC SBCZ PVAL ^ STAZ ACC BCS NEXT LDAI FF STAZ SIGNACC BMI NEXT NEG: SEC ROLZ BITS LDAZ ACC CLC ADCZ PVAL* STAZ ACC BCC NEXT LDAI 00 STAZ SIGNACC BPL NEXT DONE: PLA TAX ; RESTORE RTS PAGE = FC INT: PLA PLA PLA LDA PREQ ANDI 01 STAZ PREQZ BEQ Rl LDYI 73 BPL READ LAST TIME PORT=LOAD k GET RESULTS WRITE k TO TRANS GET BASE DIGIT PORT=BASE DIGIT LOAD BASE DIGIT MODE=BINARY ;SAVE INDEX REG. ;CHECK SIGN ;STRINGBIT=0 ;FORM NEW ACC ;SAVE IT ; CHANGE SIGN ACC ;UNCONDITIONAL ;STRINGBIT=1 ;FORM NEW ACC ;SAVE IT ; CHANGE SIGN ACC ^UNCONDITIONAL INDEX REG. ;DESTROY RTN ADDRESS ;READ PRTY. ACK. VECTOR ; STORE IT ; BRANCH IF LEVEL ;SET PORT = RCVRZ 59 Rl: LDYI 63 READ: LDXI Ok INLOOP : DEX BMI EXIT LDA,Y I/O ANDI OF ORAI 30 STAZ ,X TEMP DEY BPL INLOOP EXIT: LDAI MSG2 JSR OUTPUT LDXZ PREQZ INX TXA ORAI 30 JSR WRITECRAR LDAI MSG3 JSR OUTPUT LDXI OU OUTLOOP : DEX BEQ THRU LDAZ ,X TEMP JSR WRITECHAR JMP OUTLOOP THRU: LDAI MSGU JSR OUTPUT LDXI 05 SLOOP : DEX BEQ DUN LSRZ TEMP BCS ONEOUT LDAI 30 JSR WRITECHAR BCC SLOOP ONEOUT : LDAI 31 JSR WRITECHAR BCS SLOOP DOT: LDAI "RTN" JSR WRITECHAR LDAI "LF" JSR WRITECHAR LDA PREQ NOP CLI JMP MAIN PAGE = FF WRITECRAR: BIT TTY_STATU BPL WRITECHAR STA TTY RTS ;SET PORT = RCVR1 ;LOOP INDEX ;READ RCVR DATA ; CONVERT TO ASCII ; STORE IT ; PRINT HEADER ;GET PREQ VECTOR ;MAKE IT ASCII ;WRITE IT ;PRINT ":fc:" ;LOOP INDEX ; FETCH RCVR DATA ;PRINT IT ; PR INT STATHEADER ;LOOP INDEX INSPECT SxATUS BIT BRANCH IF A ONE LOAD "0" PRINT IT ;LOAD "1" ; PR INT IT ; RESET TTY ; CLEAR INTERRUPT FLAG ;NEXT COMMAND TTY BUSY? IF SO, LOOP WRITE ACC. 60 hEALCIIAR : BIT TTY_STATUS ;TTY DATA AVAILABLE? BVC hEADCHAR ;IF NOT, LOOP LDA TTY ;READ DATA ANDI TF JSR WRITECHAR ;ECHO IT CMPI "RTN" ;IF RTN, WRITE LF TOO BNE FINIS LDA I "LF" JSR WRITECHAR LDAI "RTN" FINIS: RTS OUTPUT : ASLA TAX ;MULT INDEX BY Z LDA,X MSGTBL ;GET LO STRING ADDRESS STAZ OUTFILE.LO INX LDA,X MSGTBL ;GET HI STRING ADDRESS STAZ OUTFILE.HI LDYI 00 ;IN IT STRING INDEX PLOOP : LDAZ,Y OUTFILE.LO ;GET STRING CHAR BMI OUTT ;CHAR = TERM? JSR WRITECHAR ;IF NOT, WRITE IT INY ; INCREMENT STRING INDEX BPL PLOOP OUTT: RTS EXEC: CMPI "RTN" ;SKIP IF NOT RETURN BEQ GO JMP NEXT GO: BITZ EFLAG BPL DOIT ; EXECUTE IF NO ERROR LDAZ EMSGINDX ; PRINT ERROR MESSAGE JSR WRITECHAR LDAI "LF" JSR WRITECHAR JSR WRITECHAR JMP MAIN ;NEXT COMMAND DOIT: LDAZ OP CMPI K ;SEE IF XPT OP BCS RD/WR ;BRANCH IF NOT XPTOP: JSR XPT ;D0 XPT FUNCTION LDAI "LF" ;RESET TTY JSP. WRITECHAR JMP MAIN RD/WR: CMPI "W" ;SEE IF "WRITE" OP BEQ, WR ; BRANCH IF SO JMP RCVRSET ;RCVR ROUTINE WR: JSP DCOMP ;CALL DCOMP LDAI "LF" JSR WRITECHAR ; RESET TTY JMP MAIN ;NEXT COMMAND 6i SYSINIT : LDXI FF TXS CLC CLD LDAI 00 STA T1,BITS STA T2,BITS STA XPT STA XPT + 1 STA XPT + 2 STA XPT + 3 STAZ MAP STAZ MAP + 1 STAZ MAP + 2 STAZ MAP + 3 LDAI "CR" JSR WRITECHAR LDAI "LF" JSR WRITECHAR CLI JMP MAIN VECTORS: RES.LO BO RES. HI FF INT . LO 00 INT. HI FC ;INIT STACK POINTER ;MODE = BINARY ;TURN OFF Tl & T2 ; CLEAR XPT SWITCH ; CLEAR XPT MAP ; RESET TTY ;WAIT FOR COMMAND ;RESET AND INTERRUPT SECTORING 62 LIST OF REFERENCES 1. Poppelbaum, W. J., Appendix I to "A Practicability Program in Stochastic Processing," Department of Computer Science, University of Illinois, March, 197^. 2. Bracha, E. , "BURSTCALC (A BURST CALCulator) ," Report UIUCDCS- R-75-769, Department of Computer Science, University of Illi- nois, October, 1975. 3. Mohan, P. L., et al., "Performance Evaluation of the Digital AM Receiver," Report UIUCDCS-R-75-757 , Department of Comp- uter Science, University of Illinois, April, 1975. h. Mohan, P. L. , "The Application of Burst Processing to Digital FM Receivers," Report UIUCDCS-R-T6-T80 , Department of Comp- uter Science, University of Illinois, January, 1976. 5. Poppelbaum, W. J., "Application of Stochastic and Burst Pro- cessing to Communication and Computing Systems," Proposal, Department of Computer Science, University of Illinois, July, 1975. 6. Catlin, R. W. , "MUMS: A Modular Unified Microprocessor System," Report UIUCDCS-R-76-809, Department of Computer Science, Uni- versity of Illinois, July, 1976. 7. Peatman, J. B. , The Design of Digital Systems , McGraw-Hill Co., New York, 1972. Unclassified SECURITY CLASSIFICATION OF THIS PAGE (Whan Data Entarad) r REPORT DOCUMENTATION PAGE READ INSTRUCTIONS BEFORE COMPLETING FORM 1 REPORT NUMBER UIUCDCS-R-76-812 2. GOVT ACCESSION NO 3. RECIPIENT'S CATALOG NUMBER 4 TITLE (and Submit) A MICROPROCESSOR-CONTROLLED INTERFACE FOR BURST PROCESSING 5. TYPE OF REPORT ft PERIOD COVERED Master's Thesis «. PERFORMING ORG. REPORT NUMBER UIUCDCS-R-76-812 7. AUTHORC*; Pleva, Robert M. I. CONTRACT OP GRANT NUMBERfa) N000 1U-75-C-0982 9 PERFORMING ORGANIZATION NAME AND ADDRESS Department of Computer Science University of Illinois at Urb ana-Champaign Urbana, Illinois 6l801 10. PROGRAM ELEMENT, PROJECT, TASK AREA « WORK UNIT NUMBERS , CONTROLLING OFFICE NAME AND ADDRESS Office of Naval Research 219 South Dearborn Street Chic ago. Illinois 6n 6oU 12. REPORT DATE July 1976 13. NUMBER OF PAGES 70 U MONITORING AGENCY NAME ft ADDRESS*"// dlllarant trotn Controlling Olliem) IS. SECURITY CLASS, (ol thl, report.) Unclassified 15«. DECLASSIFICATION/ DOWNGRADING SCHEDULE 16. DISTRIBUTION ST ATEMEN T (ol thla Report) 17. DISTRIBUTION STATEMENT (ol tha mbatrmcl antarad In Block 30, II dltlarant (ran Raport) •8 SUPPLEMENTARY NOTES k 19. KEY WORDS (Contlnua on tavaraa alda II nacaaaarj and idanttty by block numbar) Burst processing Unary encodings Microprocessor-based systems Serial data transmission 20. ABSTRACT (Continue on ravaraa alda It nacmaamry and Idanttty by block numbar) As part of the research effort investigating the properties and applications of Burst processing, the question of compatibility with the more usual weighted-binary data representations has been considered The MICROBURST system is a microprocessor-controlled, general -purpose interface system capable of operating in a multichannel Burst environ- ment. System structure, programming details, and support software are discussed. DD , X 73 1473 EDITION OF 1 NOV 68 IS OBSOLETE S/N 0102-014-6601 | Uncla.ss-if-ipH SECURITY CLASSIFICATION OF THIS PAGE (Whan Dmlm Kntarad) BIBLIOGRAPHIC DATA SHEET 1. Report No. UIUCDCS-R-76-812 3. Recipient's Accession No. l. Title and Subtitle A MICROPROCESSOR-CONTROLLED INTERFACE FOR BURST PROCESSING 5. Report Date July, 1976 . Author(s) Robert M. Pleva 8- Performing Organization Rept. N °- UIUCDCS-R-76-812 Performing Organization Name and Address Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 6l801 10. Project/Task/Work Unit No. 11. Contract/Grant No. N000 1U-75-C-0982 2. Sponsoring Organization Name and Address Office of Naval Research 219 South Dearborn Street Chicago, Illinois 6o60h 13. Type of Report & Period Covered Master's Thesis 14. 5. Supplementary Notes 6. Abstracts As part of the research effort investigating the properties and applications of Burst processing, the question of compatibility with the more usual weighted-binary data representations has been consider- ed. The MICROBURST system is a microprocessor-controlled, general- purpose interface system capable of operating in a multichannel Burst environment. System structure, programming details, and support soft- ware are discussed. 7. Key Words and Document Analysis. 17a. Descriptors Burst processing Unary encodings Microprocessor-based systems Serial data transmission 7b. Identifiers/Open-Ended Terms 7c. COSATI Field/Group J. Availability Statement )RM NTIS-35 ( 10-70) 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 70 22. Price USCOMM-DC 40329-P7 1