LIBRARY OF THE 
 
 UNIVERSITY OF ILLINOIS 
 
 AT URBANA-CHAMPAIGN 
 
 51 . 84 
 
 l^6T 
 
 no. 171-187 
 
 cop. a. 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/graphicalprocess187casa 
 
it*"' 
 
 Report No. 187 
 
 GRAPHICAL PROCESSING USING HYBRID ANA LOG -DIGITAL CIRCUITRY 
 
 by 
 David P. Casasent 
 
 August 30, 1965 
 
Report No. 187 
 
 GRAPHICAL PROCESSING USING HYBRID ANA LOG -DIGITAL CIRCUITRY 
 
 by 
 
 David P. Casasent 
 
 August 30, 1965 
 
 Department of Computer Science 
 
 University of Illinois 
 
 Urbana, Illinois 
 
 This work was supported in part by the Office of Naval Research under 
 Contract Nonr-l83U(l5) . 
 
ACKNOWLEDGMENTS 
 
 The author wishes to express his sincerest thanks to his 
 advisor, Professor W. J. Poppelbaum, for his good counsel, support, and 
 encouragement. Thanks are also extended to Mr. M. Faiman for his helpful 
 suggestions . 
 
 111 
 
TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 1.1 Pararaatrix System 1 
 
 1.2 Transformer 1 
 
 1.3 The Equations of Transformation 2 
 
 l.h Block Diagram of the Paramatrix System h 
 
 2 . GENERATION OF X i and Y 6 
 
 2.1 X and Y Counter . J 6 
 
 2.2 X and Y Control 6 
 
 2.3 Resistance Chain 6 
 
 2.U Diamond Gate 10 
 
 3. ROTATION: SINE-COSINE POTENTIOMETER 12 
 
 k. TRANSLATION lk 
 
 k.l Current Amplifier lU 
 
 U.2 Resistive Summing Network lU 
 
 5. MAGNIFICATION: VOLTAGE AMPLIFIER 22 
 
 5.1 Specifications 22 
 
 5.2 Methods of Amplification 22 
 
 5.3 Sources of Drift 23 
 
 5.U Input Stage 26 
 
 5.5 Second Stage 28 
 
 5.6 Output Stage 28 
 
 5.7 Amplifier Topology 30 
 
 5.8 Emitter- Follower Output 3^ 
 
 5.9 D-C Analysis 36 
 
 5.10 V e b Variations and Gain kk 
 
 5.11 V e b Variations and Linearity ^8 
 
 5.12 Influence of Thermal Variations 50 
 
 5.13 Effect of Thermal V eb Variations 55 
 
 5.1^- Output Stage Compensation 55 
 
 5.15 Experimental Data 58 
 
 5.16 Component Replacement 60 
 
 5.17 Output Range 63 
 
 5.18 Input Range 67 
 
 5.19 Frequency Range 68 
 
 5.20 Single Two-Stage Amplifier Design 68 
 
 5.21 Summary 69 
 
 6. CONCLUSIONS 72 
 
 BIBLIOGRAPHY 7^ 
 
 iv 
 
1. INTRODUCTION 
 
 1 1 Paramatrix System 
 
 The Paramatrix system of pattern representation and manipulation, 
 proposed by W. J Poppelbaum, employs hybrid analog-digital circuits to 
 represent and manipulate (i.e., translate, rotate, magnify) a line drawing. 
 
 This line drawing is displayed on a two-dimensional grid of lights 
 which is called a "matrix/' The feed-system of the lights is composed of 32 
 parallel X lines and 32 parallel Y lines p thus creating 102U points of 
 intersection. Each X and Y line is referred to by some reference voltage 
 level to enable transformation of points to be done by conventional analog 
 methods . 
 
 The graph of X versus F(x) is referred to as the input pattern. 
 
 It is set on potentiometers If F(X ) is V volts ? then the matrix intersection 
 
 (X.. Y.) where Y. = V volts, the analog level of line Y., is illuminated by 
 i J J J 
 
 means of a flipflop which drives a light bulb placed at the intersection. 
 
 Obviously to illuminate more than one light bulb in a given row, 
 more than one F(x) versus X graph must be provided „ 
 
 1,2 Transformer 
 
 Once the F(X) versus X graphs are set and the line drawing has been 
 displayed by the matrix array of light bulbs, it may be desirable to transform 
 this line drawing by any or all of the following transformations: translation, 
 rotation, magnification. The device which performs these operations is called 
 the transformer. 
 
 Various limits have been fixed on the above three operations. 
 Translation up or down and left or right by as many as 32 steps, rotation 
 about the geometric center of the matrix by an angle 0, < 9 < 3&0 , and 
 
 -1- 
 
-2- 
 
 magnif ication by m in the X direction and n in the Y direction where m does 
 
 not have'to equal n, r- < m,n < ^, must be made available. These operations must 
 
 be done at a speed of about 100 kc and with an accuracy of one per cent. 
 
 The 32 X coordinates have been assigned voltages -7=5 < X. < 8,0 volts. 
 
 Thus the voltage by which X is designated differs from that of X. . by 
 
 1 i+l 
 
 0.500 volts. The Y coordinates are similarly designated. 
 
 1.3 The Equations of Transformation 
 
 The voltages which designate the X and Y coordinates under investigation 
 were chosen so that they would be symmetric about the center of the matrix. 
 This makes the operation of magnification one of simply multiplying each X and 
 Y coordinate value by the magnification factor desired. This, however, implies 
 that the line drawing to be magnified be centered at the (0.0 volt, 0.0 volt) 
 matrix point which shall be designated the origin. This was found to be the 
 best method of magnification despite this limitation. 
 
 Similarly, rotation occurs about the matrix origin and this implies 
 that the geometric center of the figure lie at the matrix origin. Since this 
 is necessary anyway for magnification, this restriction is very minor. 
 
 In transforming a figure the following order is the one which will 
 yield the desired results most easily: 
 
 (1) Translation of the figure until the geometric center lies 
 at the matrix origin, 
 
 (2) Magnification, and 
 
 (3) Rotation. 
 
 Designating the initial coordinates of the figure as x, y and the 
 transformed coordinates as X, Y, the transformation equation is 
 
 (X,Y) = RMT(x,y) . (l.l) 
 
-3- 
 
 Defining a as the amount of translation in the X direction, b 
 
 as the amount of translation in the Y direction, Q as the angle of rotation, 
 
 m as the magnification factor in the X direction, and n as the magnification 
 factor in the Y direction, the equations of transformation become; 
 
 X - m(x + a) cos 9 + n(y + b) sin 9 (1.2) 
 
 Y = -m(x + a) sin 9 4 n(y + b) cos 9 . (l.3) 
 
 The transformer, however, inspects 3ach of the 102^ matrix points 
 
 (X , Y.), i, j =0 ... 31 and determines what initial matrix point with the 
 -*- J 
 
 given values of a, b, 0, m> and n would have generated the point in question. 
 In other words, the inputs to the transformer are X and Y, the output or 
 transformed coordinates^ and the outputs are x and y, the initial coordinates. 
 
 There will be 102^ pairs of inputs, one for each of the 102^ 
 matrix points. For each of these the transformer will generate a corresponding 
 pair of input coordinates (x. ., y. .) which, under the transformation chosen, 
 would yield the output coordinates (X., Y.) which are being investigated. 
 Depending on whether the generated matrix intersection (; . .,y. .) was activated 
 on the initial figure, the corresponding transformed point (X . , Y„) will be 
 activated or left alone. The following intersection (X , Y„ ) is then 
 similarly inspected and the process continues until the entire matrix grid 
 has been scanned. 
 
 This method of transformation is the simplest to implement in 
 hardware , 
 
 The transformation equations that the transformer solves correspond 
 to performing the inverse operations done on the matrix and in the opposite 
 order. The order of the operations that the transformer performs is rotation, 
 demagnification, and translation, Rotation and translation are performed with 
 the opposite sign conventions as before. The actual equations of transformation 
 take the following form? 
 
-4- 
 
 x. . = - [X. cos e - Y. sin q] - a (l.M 
 
 ij m 1 j 
 
 y. . = - [X. sin + Y. cos 0] - b (1.5) 
 
 J ij n 1 j 
 
 i, J = ... 31 
 
 where X. and Y. assume all 102*+ possible combinations of 32 X and 32 Y 
 coordinates . 
 
 Theoretically,, the order for the operations of magnification and 
 rotation is unimportant since both require only that the center of the figure 
 lie at the matrix origin. Obviously translation must be performed first on 
 the matrix . If the order of magnification and rotation were not chosen as in 
 equations (l.2) and (l„3) then the common factors l/m and l/n would not occur 
 in equations (lA) and (l.5) and the 'equations of transformation would be 
 more difficult to generate. 
 
 It is quite possible that in the generation of the equations of 
 transformation certain coordinate voltage levels after magnification and 
 translation could reach quite high values . The circuits of the transformer 
 are designed so that such voltages will be set to +10 volts or -10 volts, 
 
 1,*+ Block Diagram of the Paramatrix System 
 
 Figure 1 contains a block diagram of the Paramatrix system. 
 
 This paper will be concerned only with the transformer portion of 
 
 the Paramatrix system together with part of its peripheral equipment 
 
 necessary to generate the equations of transformation. The major emphasis 
 
 will be on an ultralinear voltage amplifier (Section 5). 
 
 Further information and discussion regarding the other portions of 
 
 this system can be found in the various DCS Technical Progress Reports listed 
 
 in the Bibliography, 
 
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2. GENERATION OF X. AND Y. 
 
 i J 
 
 2.1 X and Y Counter 
 
 The X and Y matrix coordinates have been designated X ... X 
 and Y Q ... Y with (X Q , Y ) occurring in the bottom left corner of the matrix. 
 The scanning process involves the orderly generation of all 102U matrix 
 coordinates. This is accomplished by means of a 5-bit Y Counter controlled 
 by a clock. This counter controls a 5-bit X Counter. The X Counter is 
 stepped up by one each time the Y Counter completes its cycle of 32 steps. 
 In this way the matrix is scanned sequentially column by column from bottom to top, 
 
 2.2 X and Y Control 
 
 The specific coordinates are available as the outputs of two 
 5-bit binary decoders which have the five flipflop outputs of the counters as 
 inputs. These two decoders are referred to as X Control and Y Control in 
 Figure 1. One and only one of the 32 outputs of each decoder is a "l" 
 depending on the binary number contained in the corresponding counter. 
 
 2.3 Resistance Chain 
 
 These 6U digital signals from the two decoders are changed into 
 their corresponding analog values -7.5 < X., Y. < 8,0 volts by means of the 
 system shown in Figure 2. 
 
 The diamond- shaped symbol represents a diamond gate circuit (Section 
 2.^-). It is a hybrid analog-digital circuit whose input equals its output when 
 
 the gate is a "1," otherwise its output floats; gX. and gY. are the digital 
 
 J 
 
 outputs of the X and Y decoders . 
 
 If V is fixed at 8 volts and if R n = R = R 00 = R_ then V through 
 
 1 n 32 
 
 V\ n assume the values -7.5 < V < 8,0 in 0.5 volts increments. These are 
 31 - n - 
 
 precisely the voltage levels corresponding to the X and Y coordinates . 
 
 -6- 
 
■7- 
 
 gv 
 
 +v 
 
 Q 
 
 31 
 
 gX 
 
 31 
 
 31 
 
 gY 30 >Rig><30 
 
 V 3 c 
 
 gY 29 J R2 gx 29 
 
 V 2 8 
 
 gYie g x 
 
 <R15 
 
 g Y i6 gXi 
 
 Vie 
 
 •^Hz&- -6- 
 
 < Y 16- Y 3l) 
 
 <>R16 
 
 s\ 
 
 XL 
 
 gY 15 gx i5 
 
 ViT 
 
 <>■ '<^^>' 
 
 <v ( ^, 
 
 gY 14 > R17 gx t < 
 
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 ■aV 
 
 gYi 2 J. R15 gx 12 
 
 v i2 
 
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 Y Jri4 Y „Y <No Y 
 
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 A kA ,kM^>. 
 
 gY 4 gx 
 
 < x 16"" x 31> 
 
 Vo 
 
 %"Y«) t R32 
 
 (x -x 15 ) 
 
 Yj 
 
 Figure 2, Resistance Chain with Diamond Gates 
 
-8- 
 
 Thusj if gX. is a "l" then the X output is the analog voltage corresponding to 
 
 X. on the matrix. The Y. output operates similarly. 
 
 The effect of a load current, I , can be predicted by considering 
 the case shown in Figure 3. The dependence of V on n and I is derived as 
 follows : 
 
 V - V V - 
 
 n n 
 
 (l6-n)R nR 
 v 
 
 = I, 
 
 V = — [nV - n(l6-n) I H 
 n l6 L 
 
 IL 
 
 + V 
 
 I 
 
 
 "\ 
 
 > 16-n 
 
 i 
 
 >n 
 
 Figure 3- Resistance Chain for Tolerance Analysis 
 
 The change in V due to L 4 is 
 n L ' 
 
■9- 
 
 n(l6-n) I T R 
 
 & \ = TS 
 
 AV n= n(1 "I6 5 T L R 
 
 where < n < l6 
 
 cAV 2n 
 
 ~ = I T Rn (1 " TZ) 
 
 an - J L "0 ^ " 16' 
 cAV 
 
 AV is maximum at n = 8 C The maximum AV is thus 
 n n 
 
 AV = 8(1 - « ) I R 
 
 n max„ 16 L 
 
 AV = kl r R^ . (2.1) 
 
 n max L 
 
 The effects of variation in resistor values can be investigated 
 
 by again referring to Figure 3? For worsl>>case analysis^ the l6-n resistors 
 
 are assumed to be the lowest possible and the n resistors the highest 
 
 possible within the resistor tolerances. Denoting the resistor tolerance 
 
 by CT R - . R, . and R = R. . , the equation for AV in terms of the 
 Umax. - Dmin : n 
 
 resistor tolerance o; r is: 
 
 V nR 
 
 n " nR + (l6-n)R 
 
 n(l + CT ) R 
 
 v _______ _ o_ _ 
 
 n " n(l + CT )R + (l6-nJ[T~^~a r ^ R 
 
 Defining V as V when cr = 
 B nO n 
 
-10- 
 
 V - V - ^- r 16(1 + «') , 1 AV - 
 
 V n V n0 - 16 L n(l + a' ) + (l6-n)(l - a') ' l] = ^ V r 
 
 AV > . ^«1 r 32 - 2n 
 n " 16 L 16 - 16 a' + 2ra 
 
 -*rp - (32 - l+n)(l6 - 16a 1 + 2nQ; , ) - n(32 - 2n)2a' 
 -^~ = 32(l6)(l - a' ) - 6Un(l - a' ) - ^n a 1 . 
 
 Assuming the resistors will be small tolerance a' « 1, AV J is then 
 
 ' n 
 
 me 
 
 ximum at n = 8 and 
 
 AV nmax " 2 
 
 (2.2) 
 
 2.h Diamond Gate 
 
 The diamond gate used in Figure 2 is shown in Figure k. The 
 
 inputs to the diamond are the analog voltages corresponding to the various 
 
 matrix coordinates. The gate signal is the gX. or gY^ signal from the 
 
 X or Y control. These gX. and gY . signals are the outputs of NOR circuits 
 
 and their level is either volts for "l" or -5.0 volts for "0." 
 
 If the gate signal is a "1" (0 volts), V. = V ' T, is off since its 
 
 3 in out 1 
 
 base is well above the base of T . Fifteen milliamps then flows through 
 
 T_ and T . The diode drops are the same and V. = V , . 
 23 ^ in out 
 
 If the gate signal is a "0" (-5.0 volts), T is on and T is off 
 
 since the base of T is above that of T . Current thus flows around the 
 
 diamond through R„, T_, and R, . V . thus floats and is restricted to the 
 3 3 h out 
 
 range -10 < V < +10 volts by the choice of base voltages of T^ and T . 
 — out — 23 
 
-11- 
 
 + 25v 
 
 +10v 
 
 T1.2 
 T3 
 
 SM5333 
 SM1530 
 
 BRIDGE DIODES 
 
 1N995 
 
 14v ZENER 
 DIODE 
 
 GATE 
 
 Vqut 
 
 -25v 
 
 Figure h. Diamond Gate Circuit. 
 
3. ROTATION: SINE-COSINE POTENTIOMETER 
 
 The simplest way of accurately generating the sine and cosine of 
 an angle is by means of a sine-cosine potentiometer. The potentiometer is 
 wirewound with continuous rotation. It has four wipers separated by 90 . 
 Figure 5 shows that, with inputs + V, the outputs are + V sin Q, + V cos G. 
 The potentiometer used is accurate to within one per cent. The figure shows 
 that the potentiometer is not wound linearly, but rather is proportional to 
 the sine and cosine curves. 
 
 This sine- cosine potentiometer can be combined with the resistance 
 chain to generate the rotation terms in the equations of transformation. 
 Figure 6 shows the connections necessary. They simply involve replacing the 
 + 8 volts supplies by + 8 sin 0, + 8 cos 0„ 
 
 Due to the fact that all four trigonometric values with positive 
 and negative signs can be generated, it is not necessary to subtract two 
 voltage levels or to attempt to invert analog signals. These two operations 
 would be difficult to perform to the desired accuracy of less than one per 
 cent. Such operations would also employ more circuitry. 
 
 The four outputs shown in Figure 6 are precisely the first four 
 terms in the equations of transformation with appropriate signs already 
 included in the generated values. 
 
 The sine-cosine potentiometer must have a fixed load if its 
 accuracy is to be maintained. The potentiometer used has a specified fixed 
 load of 320 ft. Each resistor R in the resistance chain is thus 20 Q. 
 Equation (2.2) predicts a worst— case error of ^4-0 mv if one per cent 
 resistors are used. 
 
 -12- 
 
-13- 
 
 + Vo 
 
 Figure 5° Sine-Cosine Potentiometer „ 
 
 +Vcos0 
 
 g x 3i? gy 3 i 
 
 9 X 30 > 9 Y 30 
 
 9 X 17 9Yl7 
 
 -vcos e 
 gv ? gx 
 
 gYi I gx 
 
 ■~6K>~' ~&+6~' 
 
 +Vsin0 
 ? 9 X 3i 
 
 gY < gx 30 
 
 > 
 
 gY 14 J gX 16 
 
 gY i5 
 
 -Vsin 6 
 
 ? gY 3i 
 
 g x o > gY 3 o 
 
 i 
 i 
 i 
 
 g x i4 J gYi6 
 
 + Ycos0 +Xcos0 
 
 4Xsin0 -Ysin0 
 
 Figure 6, Resistance Chain with Sine-Cosine Potentiometer 
 and Diamond Gates „ 
 
h . TRANSLATION 
 
 h . 1 Current Amplifier 
 
 Before discussing the manner in which translation is achieved a 
 current amplifier will be discussed. 
 
 At many points in this system more current was needed than the 
 particular point in question was capable of furnishing with the desired 
 accuracy . A simple emitter-follower would introduce too much error and thus 
 a current amplifier was necessary, capable of furnishing or receiving 10 ma 
 
 and for which V, = V + 50 mv over the range -10 < V. < + 10 volts, 
 m out _ — in — 
 
 The circuit is shown in Figure 7 and used in Figure 8. T is a 
 
 constant- current source and T is a constant- current sink, thus the current 
 
 flowing in T^ is constant and V , _ is constant. T^ and T^ are a difference 
 2 eb2 5 o 
 
 amplifier connected between input and output. If the output is above the 
 
 input, T/- passes more current and the bases of T and T, are lowered thus 
 
 lowering the output. Similarly, if the output is below the input, T/- passes 
 
 less current and the bases of T and T, are raised thus raising the output. 
 
 The output transistors T_ and T« enable this circuit to provide or receive 
 
 current. Only one output transistor is on at a time depending on whether 
 
 the output is positive or negative. The output voltage is again restricted 
 
 to tie range - 10 < V < +10 volts by the two collector supplies of T„ and T, 
 
 — out — 5 ^ 
 
 h , 2 Resistive Summing Net work 
 
 The easiest way of adding two voltages is by means of a resistive 
 summing network. Figure 8 shows the topology necessary to generate the 
 equations of transformation. The four inputs to the first two resistive 
 summing networks are the outputs of the four diamond gate chains shown in 
 Figure 6. 
 
 -Ik- 
 
■15- 
 
 + 25v 
 
 SM3936 
 2N1308 
 2N1309 
 2N706A 
 
 -25v 
 
 Figure 7= Current Amplifier Circuit 
 
-16- 
 
 Any output current from the diamond gate must be supplied at the 
 input. The inputs to the diamond gstes are points on the resistance chain „ 
 Equation (2.l) shows that for even a 1 ma load current in one diamond chain 
 the voltages on the resistance chain are in error by as much as 80 mv« This 
 error can easily be eliminated by inserting current amplifiers at the outputs 
 of the four diamond gate chains as shown in Figure 8. 
 
 The error in the current amplifier is approximately 5 mv per ma of 
 load current. The output currents will be restricted to a maximum of about 
 5 ma to improve accuracy. 
 
 A resistive summing network will not be accurate unless negligible 
 current is drawn from its summing junction. The current amplifiers placed 
 at the output of the first stage resistive summing networks insure this 
 operating condition. It will be shown that the voltage drop across R can 
 reach a maximum of 5 volts . The current in R must be limited to 10 ma due to 
 the current amplifier and the limit chosen is 5 ma. This determines the value 
 of R . The value of R is variable and reaches UR as a maximum. This prevents 
 using widely different impedance levels for the stage 1 and stage 2 voltage 
 dividers instead of the extra two current amplifiers . 
 
 The loss in the resistive summing network used as the second stage 
 adder is fixed at approximately l/2.2 and the input controlling the translation 
 quantities a and b is varied. This was necessary since the coefficient 
 of a and b in the equations of transformation is -1. Using a fixed source for 
 a or b and varying the summing resistor would vary a and b as is desired but 
 it would also vary the coefficient of the first two terms in the equations of 
 transformation by this same variable coefficient. This would make the 
 potentiometer settings for various values of m, n, a, and b very difficult 
 if not impossible to determine. 
 
-17- 
 
 xl cos e 
 o 
 
 -Yj SIN 9 
 O 
 
 X[ SIN 9 
 o 
 
 Yj COS 9 
 
 \iy-^- 
 
 £> 
 
 C 
 
 ^(X L COSfi-Yj SIN 9) X L COS 9 - Yj SIN0 _a 
 
 £> 
 
 R2 
 
 -v" ♦ 
 
 £> 
 
 R7 C 
 
 - 2.2a 
 G 
 
 A^ 
 
 R8 
 -V ♦ 
 
 Gm G 
 
 l> 
 
 XL COS fl-Yj SIN 9 
 
 R5 
 
 i 
 
 Rll 
 
 £> 
 
 R3 
 
 Xi SIN 0+ Yj COS 9 b 
 R6 -^I^(XL SIN 9 +Yj COS6) ( Gn " G 
 
 l> 
 
 R4 
 
 /' 
 
 &• 
 
 R9 
 
 2.2b 
 
 A^> 
 
 RIO 
 -v 1 ' 
 
 £> 
 
 X L SIN + Yj COS 9 
 
 — ! -I 
 
 < R12 
 
 Figure 8„ Translation by Voltage Dividers and Current Amplifiers, 
 
 + IOv 
 
 i>10K <2.7K 
 
 I 10K 
 
 r — 
 
 -o- 
 
 2.2a 
 
 •VlOK 
 
 u Rl 
 v l o v/— 
 
 R2 
 v 2 o ,A- 
 
 <i o v 
 
 $ R3 
 
 •lOv 
 
 Figure 9-» Translation Control 
 
 Figure 10. Voltage Divider, 
 
-18- 
 Similar reasons apply to the possibility of a single resistive 
 summing network with three inputs replacing the two -stage arrangement of 
 Figure 8. 
 
 Figure 9 shows the simple arrangement for generating the variable 
 
 2 2 2 2 
 voltages - —=— a and - —7-^ b where G « 20 and -l6 < a, b < + l6 volts. 
 
 The voltage ranges are approximately: 
 
 ■1.76 < - ^ a, - ^ b < +1.76 v . (4.1) 
 
 These supplies must be capable of furnishing h ma at all voltage levels. 
 
 Referring to the resistive summing network of Figure 10, the output 
 in terms of the two inputs is 
 
 II 12 
 
 R 1 + R P 
 V = x i_ 1 • (^2) 
 
 R l + R 2 + R 3 
 
 Choosing R = R 
 
 v ■ (v i + V 577^ • (u - 3) 
 
 The term R /(R + 2R ) is defined as the resistive summing network coefficient, 
 K. 
 
 Referring to Figure 8, the coefficient for the first stage summing 
 network is 1= 2.2/(Gm) where G p, 20 and l/k < m < k. Thus the range of K 
 becomes 
 
 .0275 < K < M ( h ^) 
 
-19- 
 The coefficient, K , is restricted to the range < K < l/2. 
 Equation (U.4) shows that K does satisfy this inequality. The value of K , 
 the coefficient for the second stage resistive summing network, was chosen as 
 1/2.2 to insure that K for the first stage resistive summing network is within 
 the allowed range since l/K appears in K . For the model of Figure 10 the 
 inequalities become 
 
 0275 < 
 
 J_ 
 
 R l + 2R 3 
 
 < M 
 
 (h.5) 
 
 or 
 
 ,0291 R < R < 3c6t r 
 
 (h.6) 
 
 The maximum value of V , the voltage across R , will be 
 
 zot^n [x i cos e 
 
 - Y. sin e] 
 
 j max : 
 
 It can easily be shown that 
 
 [(*) cos q + (*) sin 0]_ : + [J X 2 t Y 2 ] 
 
 max. 
 
 max , 
 
 = + 8vT2 
 
 + 11.3 v 
 
 (h.l) 
 
 Thub, 
 
 2,2 11.3 . 
 
 F max : ~ 20 
 
 ^ ss + 4,95 v 
 
 (^.8) 
 
 The voltage across R in Figure 8 is 
 
-20- 
 
 V D = X. (1 - K. ) cos 9 + Y. K n sin Q 
 
 tirj 1 1 J 1 
 
 V c a/2~6v. (1+ o) 
 
 R max. \^*yj 
 
 If R = R = R = R, = IK the load current of the four current amplifiers is 
 restricted to 
 
 < I_ < 6 ma . (^.10) 
 
 Li 
 
 The first stage summing resistors must vary in the range 
 
 27.5 a < R 5 , R 6 < h.6 K fl . (^.11) 
 
 By a similar analysis the second stage voltage divider resistor values are 
 
 R T = R 8 - R 9 = R io = 50 ° Q 
 
 R u = R 12 = 2.5 k n 
 
 The base currents of the current amplifier will be constant since 
 the current in the input transistor is constant and under proper operation 
 the current in the feedback difference amplifier will be constant. This means 
 that whatever base current flows, it is constant. Its amplitude has been 
 measured as only 5 M-a but with m = k this flows into a k.h K fi summing 
 resistor and thus produces a 22 mv error. This can be corrected by adjusting 
 the summing resistors. 
 
 Since resistive summing networks are used and the input resistors 
 are equal, the coefficient K is always less than l/n where n is the number of 
 inputs. Such a network cannot give gain and since the required gain l/m lies 
 in the range 
 
-21- 
 
 r < ~ < h (U.12) 
 
 h - m — v ' 
 
 a voltage amplifier is necessary. Its gain has been assumed to be about 20. 
 It is symbolized in Figure 8 by 
 
 c V c 
 
 The resistors in the first stage voltage divider could be fixed and 
 then the problem would become one of designing a highly accurate and fast 
 voltage amplifier capable of an output range -10 < V < +10 volts with the 
 additional stipulation that the gain be variable It is far more direct to 
 vary the summing resistor in the resistor adder and keep the gain of the 
 voltage amplifier constant. 
 
 The remainder of this thesis will be devoted to an extensive 
 analysis of such a voltage amplifier. 
 
5 . MAGNIFICATION : VOLTAGE AMPLIFIER 
 
 5.1 Specifications 
 
 The voltage amplifier necessary must conform to the following 
 specifications : 
 
 (1) A high input impedance, 
 
 (2) An output capable of supplying 10 ma, 
 
 (3) An output range of -10 < V < +10 volts, 
 (h) A frequency range of d-c to 1 mc, 
 
 (5) A constant gain of about 20 with an error of less than one 
 per cent over the entire voltage range, 
 
 (6) A drift of less than 30 niv over the entire voltage range, 
 
 (7) An output offset voltage of less than 10 mv when the input 
 is switched from any level to ground, and 
 
 (8) The capability of interchange of components with no loss 
 of accuracy. 
 
 It is also desirable that this circuit be uncomplicated. No 
 special components will be used such as matched transistor pairs, thermistors, 
 temperature sensing diodes, or hot or cold ovens. In other words the circuit 
 should be simple, and the topology and not the components should be the 
 basis for the accuracy. 
 
 5.2 Methods of Amplification 
 
 Many d-c amplifiers employ operational amplifiers with parallel 
 feedback and the gain is then the ratio of feedback resistance to input 
 resistance if the gain of the amplifier is of the order of 10 . 
 
 -22- 
 
-23- 
 
 Amplifiers capable of responding to direct current or voltage 
 
 present many problems , Resistive coupling of several amplifier stages 
 
 produces an amplifier which responds to direct current or voltage. However, 
 
 such amplifiers cannot distinguish between signals generated externally or 
 
 signals generated internally. A change in V . or I . . is amplified as 
 
 eb cbO 
 
 readily as an input signal. An amplifier which responds only to a-c signals 
 does not have this cumulative drift— error. For this reason, normally when 
 very accurate d-c amplifiers are desired, the input d-c signal is changed into 
 an a-c signal by means of a transistor chopper „ The a-c signal is then 
 amplified and then rectified for a d-c output „ 
 
 Another newly developed method of amplification of d-c levels 
 fairly accurately and over wide frequency ranges is that of integrated 
 circuitry. With present techniques transistor parameters can be made equal 
 within 0.01 per cent Transistors can be made on the same block and all 
 elements are thus at the same temperature and thermal problems are greatly 
 reduced c In this manner very drift- free circuits can be produced. 
 
 Such methods are not readily available, and methods employing 
 transistor choppers and rectifiers, many of which employ matched transistor 
 pairs to cancel leakage currents and parameter variations, require very 
 much circuitry, 
 
 5,3 Sour ces of Drift 
 
 The method of introduction to the final amplifier design will be 
 to state the well known transistor phenomena which produce drift and loss 
 of accuracy, The merits of various methods of compensating these errors 
 will be discussed. In this way the best theoretical input stage and a 
 novel output stage will be developed. From these observations the final 
 circuit topology will be produced. 
 
-2k- 
 
 The major reasons for drift in a transistor are variations in the 
 d-c properties of the collector-base and emitter-base diodes and the d-c 
 transfer ratio. The T— equivalent circuit for a transistor is shown in 
 Figure 11. 
 
 l e *I e +Ale 
 E Q **~ ^ 1 
 
 Vbe 
 
 + 
 O— 
 
 r , • ,, 
 
 e v b 7j 
 
 f lb 8 lb + Alb Al 
 
 e 
 
 T 
 
 B 
 
 Figure 11 „ T-Equivalent Transistor Circuit . 
 
 The parameters r , r, , r and a are the conventional small 
 e' b c 
 
 signal parameters at the operating point. The battery V' , generator I' n , 
 and d-c transfer ratio OL provide necessary current and voltage for the 
 operating point „ The currents denoted by capital letters are quiescent 
 values and the deviations from these values are denoted by Ai . 
 From Figure 11 : 
 
 V = V" + Lr^ + I r 
 be be b b e e 
 
 (5.1) 
 
-25- 
 
 I , . = I' + V /r (5.2) 
 
 cbO c bO cb' c 
 
 Ai = ai + QAi . (5.3) 
 
 e e e w Jl 
 
 Thus, as the emitter current or the collector current vary. V , 
 
 be 
 
 I ._. and A vary. This fact is well known. Various biasing methods involving 
 cbO 
 
 current and voltage feedback and other techniques have been used to reduce 
 these variations. 
 
 One other factor of great importance is that of power dissipation. 
 It is a known fact that as the power dissipation at the collector junction 
 increases the junction temperature, T., will increase causing a A V and a 
 A I n „ If the collector junction does not remain at the ambient temperature, 
 T , the operating point will shift. This effect can be minimized by choosing 
 transistors with reasonable I and thermal conductivity and circuits with 
 low power, low voltage, and low stability factor, S. 
 
 Negative feedback has been found to be very useful in amplifier design, 
 It possesses three well known properties: 
 
 (1) It increases stability, 
 
 (2) It reduces frequency and phase distortion, and 
 
 (3) It reduces nonlinear distortion. 
 
 Local current and voltage feedback are frequently used in d-c amplifiers. 
 Before proceeding further three stability parameters will be defined. 
 
 (1) Input voltage drift is the change in input voltage required 
 to maintain constant output conditions when the parameters 
 of the circuit vary, 
 
 (2) Input current drift is the change in input current required 
 to maintain constant output conditions when the parameters of 
 the circuit vary. 
 
-26- 
 (3) Stability, S, is the ratio of the change in collector 
 current to the change in I , 
 
 5 o^ Input Stage 
 
 Figure 12 shows the equivalent circuit for a typical NPN difference 
 d-c amplifier stage. The equivalent input voltage drift is 
 
 AV 1 " AV 2 = " Kel - AV be 2 ) " ^ 1 ^^ 1 ^ (AI cbQ1 - AI cbQ2 ) 
 
 R + r + R + r 
 "bee 
 
 (5oM 
 
 (z^il I _ - m n I _) 
 
 a % 1 el 2 e2 
 
 This expression is similar to that for a single-ended stage, however, now 
 any error due to parameter variations is reduced appreciably since in the 
 differential arrangement the corresponding parameters of the two transistors 
 are subtractive „ By choosing suitable circuit values, this drift can be 
 made very small, 
 
 Such drift reduction by compensation does not materially affect 
 the gain and thus produces a noticeable improvement in the minimum detectable 
 input signal. This should be contrasted to othsr methods of stabilization 
 involving local degeneration which reduces the gain and decreases the minimum 
 detectable signal. 
 
 The stability, S, of each side of the difference amplifier of 
 Figure 13 can be calculated to be 
 
 dl 2R + R^ 
 q c _ e b / q c-n 
 
 hi n " 2R + Rfl - a) ' °° ; 
 
 cO e b 
 
 However, if the parameters of the two transistors are not 
 balanced, the emitter resistance of each side will be the parallel combination 
 
-27- 
 
 Al cl Al c2 
 
 CI o- 
 
 Al C boi + Aajiei 
 1-ai l-a 
 
 1 CD 
 
 •> tl-ai)r cl 
 
 I 
 
 AL 
 
 l M 
 
 Bl <? A- 
 
 R b 
 
 I 
 
 Av ± ? r .tl 
 
 El o 
 
 <? C2 
 
 (l-atJrca '■ 
 
 a 2 r C2 ALb 2 (") 
 
 Alrhn? Aa 
 
 o- 
 
 Cb02 ^ a 2 l e2 
 
 a 2 l-a 2 
 
 Alb 2 
 ■v p B2 
 
 r b2 
 
 AV be2 
 Ve2 
 
 T 
 
 O B 
 '»R> 
 
 :^="AV ; 
 
 OE2 
 
 Re 
 
 Figure 12. Drift Equivalent Circuit for NPN Difference Amplifier, 
 
 + 
 
 A 
 
 
 %Rb 
 
 ! 
 
 d q 
 
 > Rb 
 
 i Re 
 
 Figure 13 . NPN Difference Amplifier for Stability Analysis 
 
-28- 
 of R and R b /(P + l). The effective emitter resistance is thus R,/(p + i). 
 The worst-case stability factor is then p/2. 
 
 It can be concluded that the best input stage would be a difference 
 amplifier with negative feedback applied appropriately in the input stage. 
 The input drift of a differential stage has been found to be much better 
 than that of an equivalent single-ended stage. This improvement can be 
 partly attributed to the inherent consistency of A V /A T coefficients 
 which, for unmatched transistors of a given type, differ by less than ten 
 per cent. Other similar benefits occur. If the currents in this input stage 
 are restricted to low values the drift will be further reduced. 
 
 5 .5 Second Stage 
 
 A simple second stage as shown in Figure l^t- produced interesting 
 benefits o Figure lk is shown with values of drift in stages 1 and 2. For 
 clarity at present, stage 1 is shown as a single-ended amplifier. Figure 1 it- 
 shows the effect of second stage drift referred to the first stage. For 
 the single-ended first stage amplifier shown, the current and voltage drifts 
 of stage 2 tend to cancel those of stage 1. For a normal difference amplifier 
 the stage 2 drift may add or oppose the first stage drift. 
 
 The minimization of the drift in stage 1 is very important since any 
 drift present will be multiplied by the gain of stage 2. 
 
 5 .6 Output Stage 
 
 Past attempts at such an amplifier with an open-loop gain greater 
 than 100 reduced by feedback to a closed-loop gain of about 20 were accurate 
 to about three per cent and commonly possessed drifts of about 150 mv. The 
 obvious reason for this drift and nonlinearity was the fact that the output 
 of this amplifier had a range of 20 volts and had to be capable of handling 
 
-29- 
 
 i-CL 
 
 (Al h5 > + 
 
 [ji (Alb2+ r ± 
 
 AV 
 
 b«2 
 
 Figure lU„ Drift Currents and Voltages in Two-Stage Amplifier. 
 
 both positive and negative voltages „ When the output was changed from its 
 
 maximum positive value to its maximum negative value^ every transistor 
 
 junction in the circuit either went from its highest temperature to its 
 
 lowest or vice versa, Under such conditions all transistor parameters 
 
 changed by their greatest amount and many of these changes were magnified 
 
 in one or the other or both of the amplifier stages. These problems are 
 
 typical of most d-c amplifiers. The solution chosen was the novel output 
 
 stage shown in Figure 15 , 
 
 The voltage V is the output of a two-stage amplifier similar to 
 
 Figure lk„ The voltage V is the output of a similar two-stage amplifier 
 
 but with the polarity of all transistors reversed. The voltages V and V 
 
 are chosen such that at V. =0 volts? the voltage drop across the 
 
 in J ox- 
 
-JJU- 
 
 V20 
 
 100 n 
 
 O Vi 
 
 6 
 
 v 0UT 
 
 Figure 15 . Constant-Current Output Stage 
 
 potentiometer is 1.0 volts. Since V and V 2 are the outputs of two 
 
 similar two-stage amplifiers, the inputs of both amplifiers may be 
 
 connected with the result that for a given increment in input voltage V 1 
 
 and V increase by approximately equal increments depending on the equality 
 
 of their respective gains . This maintains a constant voltage across the 
 
 potentiometer and thus the current through both transistors is constant and 
 
 the V drops of both transistors are constant. The output wiper can be 
 eb 
 
 adjusted at V ±n = to give V^ = 0. Thereafter V^ = K (^ + V g ) where 
 K is a constant and depends on the position on the potentiometer where the 
 wiper is placed. This circuit is called a constant-current output stage. 
 
 5.7 Amplifier Topology 
 
 The amplifier is shown in Figure l6 with resistor values and the 
 transistor types used in this application. As noted previously, it is 
 composed of two similar two-stage amplifiers whose output voltages are 
 offset by a constant amount feeding the modified output stage of Figure 15 
 which goes through an emitter-follower whose output is fed back to the two non- 
 input bases of the two difference amplifiers with negative feedback. It has 
 an open-loop gain of 107 and a closed-loop gain of about 21. 
 
•31- 
 
 + 25v 
 
 IN O ii 
 
 O OUT 
 
 TRANSISTORS 2N1308 
 RESISTORS ±1% 1/2 W 
 ZENERS 1N746 
 
 DIODE 1N995 
 
 -25v 
 
 Figure l6. Ultralinear Voltage Amplifier, 
 
-32- 
 
 Equation (5 .k) demonstrated the low input-voltage drift possible 
 with this input stage. Due to the negative feedback, the insertion of 
 resistors directly in the emitters of the difference amplifier transistors to 
 drastically reduce any difference in r and to improve linearity, the choice 
 of transistors with P > 50, and the use of constant— current drive in place 
 of a resistor returned to a supply voltage, equation (5.5) can be used to 
 calculate the stability. The value of R in equation (5.5) n ow becomes 
 
 e 
 
 R « r + (p + 1) R« (5.6) 
 
 e c e 
 
 due to the constant -current drive, where R' is the external emitter 
 
 ' e 
 
 resistance of the constant-current generator. Using the values of Figure l6 
 
 R » 2 Mfl (5.7) 
 
 e 
 
 and the stability, S, of the input stage is found to be 
 
 k x 10 + 10 3 f on 
 
 S w —^ (5.o) 
 
 ^ x 10 +20 
 
 The second stage of the amplifier consists of T_,^, R Q , R n _ for one 
 
 10' cr 11 
 
 amplifier and T , R , R for the other. The feedback ratio is chosen to 
 be greater than the final gain of the amplifier as will be shown later „ 
 This fact means that the input transistor's base voltage varies by a 
 larger increment than does the base voltage controlled by the feedback. 
 This enables the input stage which is actually a difference amplifier 
 to be treated as a single-ended amplifier as far as the investigation and 
 effect of voltage and current drift are concerned, yet as a difference 
 amplifier as far as compensation is concerned. The two stages thus have the 
 same properties as the two- stage amplifier of Figure lk, namely that any 
 drift voltage or current from the second stage tends to cancel the drift 
 
-33- 
 voltage and current of the first stage thus creating a quite stable input 
 stage. The first stage gain of each amplifier should be very nearly the 
 same and quite linear. 
 
 The feedback is such as to properly compensate for any errors due 
 to parameter variations. If the output voltage is too high, the bases of 
 Tj and T will be too high, decreasing the current in R, and increasing the 
 current in R . This causes the current in T to increase and in T to 
 decrease. The bases of T and T rise_, causing the bases of Tq and T 
 to fall which reduces the output. This is the desired effect for the chosen 
 case of too high an output. The feedback works similarly to increase an 
 output which is too low. 
 
 The stability of the second stage gain will be discussed in 
 
 conjunction with the output stage. The fairly linear gains of both two-stage 
 
 amplifiers will keep the initial offset voltage between the bases of Tq 
 
 and T rather constant. This constant difference maintains the emitter 
 y 
 
 currents of T and T at constant values and thus V . and V , _ remain 
 o 9 ebo eb9 
 
 nearly constant. The resistors R^- and R merely serve to fix the two 
 
 collectors at convenient points where V , . cannot be reached and the 
 
 cb mm. 
 
 value of V can be kept as low as possible without using two additional 
 
 power supplies and connecting the collectors directly to them. 
 
 This topology produces a circuit which is thermally quite stable 
 
 despite the large voltage ranges. The magnitude of the current sources 
 
 are chosen such that the portion of the V , versus I curve which is used 
 
 eb c 
 
 can quite easily be linearized. This was necessary since over the voltage 
 range necessary it was impossible to completely cancel V between 
 transistors although the differential input stage employed does this 
 to a great extent. 
 
-3U- 
 
 A more rigorous treatment of the thermal stability of the circuit 
 appears in Sections 5.12, 5.13, and 5.1 1 +. The effect of V variations on 
 linearity is treated similarly in Sections 5-10 and 5.H. 
 
 The gain of the first stage is about 10, reduced by feedback 
 to about 2, the second stage gain is 10. 
 
 5 .8 Emitter-Follower Output 
 
 The reason for the output NPN emitter-follower T can be seen from 
 a consideration of the driving capabilities of the output of Figure 15. The 
 output circuit is redrawn in Figure 17 with the feedback resistor R of 
 Figure l6 as shown. 
 
 O Vi 
 
 O V; 
 
 V L 
 
 I 
 
 -O0UT 
 
 R 20 
 
 Figure 17. Loaded Output Stage. 
 
 The effect of a load current on the output can be determined 
 from the following equation: 
 
 V - v v - v 2 
 
 ■ - 1 = - 
 
 R 
 
 1 
 
 R, 
 
-35- 
 
 Let the potentiometer resistance be R and define K such that 
 
 R l + R 2 = R 
 
 R r°o 
 
 R 2 = (1 - K) R Q 
 
 V = V - V K + V 2 K - KR (l - K)i 
 
 The quantity V n - V.K -f VJC is the theoretical value of V ^ , 
 11 2 out 
 
 V - V = A V = KRJl - K)± = loading error . (5.9) 
 
 out out 
 
 The smaller R or K is made, the smaller the loading error 
 becomes since the output impedance thus decreases „ 
 With the following values ; 
 
 i = 10 ma 
 R Q = 50 n 
 
 K = 1/10 , 
 
 equation (5.9) becomes 
 
 loading error = ^5 mv 
 
 Equation (5.9) has not considered the effect of an output change 
 on the circuit feedback. Referring to Figure 16,, a load current causes 
 the base of Tq to increase, causing the base of T to decrease^, the 
 collector current of T to increase. The effect through T and T is 
 multiplied by the feedback ratio and added to the above loading error. 
 Experiments have shown that the loading error is roughly twice that 
 predicted by equation (5.9). 
 
-36- 
 
 The difficulty involved in setting V and V of Figure 17 such 
 
 that K = l/lO and the fact that the error due to loading alone will be 
 
 about 90 mv leads to the conclusion that this output must be fed through 
 
 an emitter— follower with feedback as in Figure l6. The potentiometer is 
 
 then centered such that at V. =0 volts the emitter-follower output, V , 
 
 in ' out' 
 
 is also volts. 
 
 The fact that the output is not taken directly from the potentiometer 
 does not affect the usefulness of and necessity for this circuit . The drift 
 of one of the two— stage amplifiers with a similar emitter-follower output 
 and the same feedback but without the constant-current output stage,, was 
 found to be about 150 mv. It is the constant— current output stage which 
 reduces the drift and permits compensation. 
 
 A d-c analysis of a single two-stage amplifier employed in the 
 
 voltage amplifier of Figure l6 will be presented followed by a rigorous 
 
 analysis of the effect of V , and its variations on the gain and on the 
 
 eb 
 
 linearity. This amplifier is shown in Figure l8. 
 
 5,9 D-C Analysis 
 
 In this analysis it is assumed for simplicity that all transistors 
 
 have V , = and a = 1. Such a first order analysis investigates the basic 
 eb 
 
 design equations of the amplifier and the various inequalities to be 
 
 satisfied. 
 
 The input voltage is U, the output voltage is V, and the current 
 
 in T is denoted by i . 
 n n 
 
 The current in is constant 
 
 ■ V 
 
 x l - R^R,, + R ) (5.10) 
 
-37- 
 
 The voltage at the base of T is fV where f is the feedback ratio 
 
 or the fraction of output voltage fed back to To 
 
 R 
 
 f = 
 
 :l. 
 
 R 9 + R io 
 
 (5.11) 
 
 The current i is thus 
 
 u - iy 3 = fv - R u (i x - i 3 ) 
 
 (5.12) 
 
 U - f V + R^i 
 '3 = \ + R 5 
 
 (5.13) 
 
 u o 
 
 + x 
 
 V 
 
 SRli 
 
 Figure l8. Two-Stage V-Amplifier for D-C Analysis 
 
■ 38- 
 
 i, is related to i by 
 
 h'is- (5 - lM 
 
 The current i, determines the output voltage V, 
 
 V = -Z + .R 8 i k 
 
 R/- Rq 
 V = -Z + -^— i from (5.11+) 
 
 R T 3 
 
 R. R ft U - f V + R, i 
 V = -Z + \£ ( R +R k X ) from (5.13) 
 
 V 
 
 = -Z 4 G Q (u - f V + R^ i 1 ) (5.15) 
 
 where G is defined as the open-loop gain. 
 
 R 6 R 8 
 G = R T (R U + R 5 ) ' (5 ' l6) 
 
 Equation (5.16) can be verified by noting that the gain through a difference 
 amplifier with the second base grounded is the ratio of the collector 
 resistor to the sum of the two emitter resistors 
 
 G i - " n~TT^ (5.17) 
 
 The second stage gain through the simple transistor stage is approximately 
 the ratio of collector resistor to emitter resistor. 
 
 G p = -=& (5.18) 
 
 2 R 
 
-39- 
 The total gain is 
 
 G o- G r G 2- ^A ) (5.19) 
 
 which agrees with equation (5.16). Solving equation (5.15) for V, the 
 result is: 
 
 -Z + G Q (U + r u 1^ 
 
 1 + f G 
 
 V = G(U + R^ ^ - |-) (5. SO) 
 
 where G is the closed— loop gain defined as 
 
 G = i-rr^ • (5.2D 
 
 Zero offset is defined as V = when U = 0„ From equations (5.10) and (5.20) 
 the condition for zero offset becomes 
 
 VGo^ ^ 1 ( R 2 + R 3 ) 
 
 Z R p 
 
 (5.22) 
 
 or 
 
 (5.23) 
 
 ( R U + V R T R 2 R U 
 
 R 6 R 8 = -R-lR— TR^T ' 
 
 It is very interesting to note that this offset condition is 
 independent of all supply voltages. If R, = R , the offset condition is 
 
 -1 = 6 8 - - 1 . (5 2k) 
 
 R 2 2R 1 R ? L °^ 
 
-ko~ 
 
 In the final amplifier, this offset is not zero and is adjusted by means 
 of the constant -current source I . 
 
 The condition that the voltage range at the base of the input 
 
 transistor T be larger than the voltage range at the base of the second 
 
 V V 
 
 transistor T is easily verified. The voltage range on T is - — < U < + — 
 
 d j> G — G 
 
 and the voltage range on T is -fV < U < + fV. Thus the first inequality 
 to be satisfied is 
 
 V [| - f ] > (5.25) 
 
 or 
 
 | - f > . (5.26) 
 
 From equation (5.2l) 
 
 1 l+f o 
 
 G " G o 
 
 K*« 
 
 G- f= G7 • (5 - 27) 
 
 
 
 G is the open— loop gain of the amplifier which is greater than zero thus 
 
 pr-f = ^>0 (5.28) 
 
 G G 
 
 and the analysis of Section 5.5 is valid. 
 
 For T, and T to conduct, the emitter supply of T, must be greater than 
 or equal to the collector supply of T . " This is true since the supplies 
 chosen show 
 
-kl- 
 
 v = x . (5.29) 
 
 The output range over which the gain is linear is 
 
 -X < V < +■ X (5.30) 
 
 The corresponding input range is 
 
 - I < U < + § (5.31) 
 
 Now all transistors must conduct over the ranges defined by equations (5.30) 
 and (5.3l) to insure linearity of gain. When U is at its minimum value, 
 -X/Gj the linear operation condition is i > 0., which, from equation (5.13) 
 becomes 
 
 U . - f V . + R, i" > (5.32) 
 
 mm min 4 1 \s ~> i 
 
 or 
 
 G T " n * 
 Equation (5.28) can now be written as 
 
 X (i - f) = X(-^-) 
 
 G G Q 
 
 £+ fX .+ R, i > . (5.33) 
 
 Equation (5.33) thus becomes 
 
 R u i >X (| - f) (5.3^) 
 
 or 
 
 R k i 1 > X (~) (5.35) 
 
-42- 
 The zero offset condition requires 
 
 \ i i = h (5 - 36) 
 
 by which equation (5.35) is 
 
 p->p- (5.37) 
 
 G G 
 
 which satisfies the condition that i > 0. The condition for this is the 
 same as that of equation (5.29) if the collectors of T and T are returned 
 to the same supply voltage. 
 
 If U is at its maximum value the linear operation condition is 
 i < i . T, conducts, thus L i < Y ■ X 
 
 Rx- i < minimum of [Rg i , Y - X] (5.38) 
 
 From equation (5.13) 
 
 R 6 H " 57^ <§ - fX + ^ (5.39) 
 
 and from equation (5.3^) 
 
 Z 
 
 1, = 
 
 1 G o \ ' 
 
 (5.1*0) 
 
 Equation (5.38) now has the form: 
 
 "fcV^H'i-"*^ 
 
 R 6 Z 
 < minimum of [Y - X, - — 5—] 
 
 G \ 
 
 (5.41) 
 
43- 
 
 or 
 
 B, R, Z 
 
 (£-+£-)< minimum of [Y - X, ;^-p-] . (5.^2) 
 
 \ + R 5 G o G o ' G o \ 
 
 Equation (5„U2) requires 
 
 R. 
 
 R 6 (X + Z) < R 6 Z(l + ^-) (5.^3) 
 
 or 
 
 R s 7 
 
 \ 
 
 Equation (5.U2) also requires 
 
 (X + Z )R 6 
 
 < (Y - X)G n (5.^5) 
 
 R, + R^ 
 
 or 
 
 R 7 
 (X + Z) ^ < Y - X . (5.^6) 
 
 As used in the final amplifier design the point V of Figure l8 is 
 
 V Q and the base of T^ is V of Figure l6„ The actual zero offset 
 o 2 out 
 
 condition from Figure l6 is 
 
 8 ebll 2 V R Z2 eb8 ~ 
 
 This simply amounts to decreasing the magnitude of the constant — 
 current source^ T , of Figure l8 c With Y = +10 volts = X the inequalities above 
 do not hold unless V is level— shifted down by four volts, 
 
-kk- 
 
 When this is done the conditions on Figure 18 become 
 
 ~ q <V<— — (5.30a) 
 
 G 
 Z >X - f- k (5.37a) 
 
 Z - k 
 
 11 " \ G o 
 
 (5.^+Oa) 
 
 R 6 X Z R.(z - k) 
 p ^ p Ltt + Uf + — ] < minimum of [Y - X + K, -5—7 ] (5 Ala) 
 
 R k + R 5 . G o R h G o 
 
 R R 
 
 (X + Z + Itf G_) < (Z - 10(1 + s 2 ) (5^3a) 
 
 R^ 
 
 R 7 
 (X + Z + kt G_) s 1 < Y - X + 1+ (5.^6a) 
 
 Rg 
 
 A similar analysis performed on a PNP two-stage amplifier produces 
 similar equations. The values chosen satisfy these inequalities. 
 
 5.10 V , Variations and Gain 
 — eb 
 
 No attempt will be made in this section to consider the effects 
 
 of changes in parameters other than V . The analysis of the input stage 
 
 in Section 5 .k and of the second stage in Section 5.5 considered all major 
 
 variations in the transistor parameters. 
 
 The overall effect of the V , variations on the gain will now be 
 
 eb 
 
 presented. Only V variations due to current level changes will be 
 
 considered. Thermal variations in V , will be discussed in Section 5.13. 
 
 eb 
 
 Following this discussion of the effect of V . variations on "gain, the effect 
 
 eb 
 
 Of these variations on the linearity of the amplifier will be presented. 
 
-4 5 - 
 
 The circuit of Figure l6 is used for this analysis, a, is assumed 
 
 to be one. This is a quite valid assumption if all transistors have a 
 
 6 > 50, The current in T will be designated i , The constant currents 
 K y n n 
 
 I and l r will be designated by capital letters. The |V I of transistor 
 5 o eb 
 
 T will be designated V , , The base of transistor T will be designated 
 n ebn n 
 
 V The bases of T, and T_ will be designated V , , These conventions 
 n 4 2 out 
 
 will apply in the remainder of this thesis. 
 
 By considerable algebraic manipulation, it can be shown that: 
 
 RRI VR V-V V 
 
 9 5 r_l out 20 eb2 e bl in , 
 
 8 = R 10 2 " ( R 1 + R 2 )(R 20 +I W + R l + R 2 + R l + R 2 
 
 R. 
 
 - 2 — V - 25 
 
 R io eb7 
 
 (5.W 
 
 R 12 R 8 M V out R 20 V in V ebU ' V eb3 
 
 9 " R 1X L 2 + I R 3 + V( R 20 + R 2l' " R 3 + «k + R 3 + R U 
 
 R, 
 
 (5.W) 
 
 V 
 
 R eblO 
 
 As V. increases, V' increases, but the increase in V is greater than 
 in ' out m 
 
 the increase in V , . Similarly, as V. decreases, V decreases and the 
 out ' in ' out 
 
 decrease in V. is larger than the decrease in V , . 
 in out 
 
 For a positive input voltage increment i } i , Vq, and V 
 increase and i and i decrease. For a negative voltage increment r , i , 
 
 V Q , and V^ decrease and i_ and i.,_ increase. 
 o' 9 3 10 
 
 Equation (5-^7) is rewritten designating in parenthesis after 
 V the current to which V is directly proportional, 
 
■k6- 
 
 R„ R. I. V 
 
 V in W- 1 ! 5 - W 1 ^ 
 
 v = ? 5 r-5. _ -222* , 
 8 ' R 1Q L 2 2R 1 2R X 2R 
 
 (5.U9) 
 
 5 
 
 V ,JiJ - 25 
 
 R io ebT 
 
 Defining cW as the change in V for a given change in V. , equation (5.^-9) 
 n n m' 
 
 becomes 
 
 R S R Q 
 
 o 2R R n m out eb2 1 ebl 1 
 
 ^- av (i ) . 
 
 R 1Q eb7 7 
 
 (5.50) 
 
 Using the specified resistor values cWo becomes 
 
 dV A - 107 [37. - dV« + cW KO (-i, ) - dV .,(i, )] - lOdV .JiJ (5.5l) 
 o in out eb2 1 ebl 1 eb7 7 
 
 For the case of cW. > 0, 
 
 av K1 > 
 ebl 
 
 (5.52) 
 
 3v < 
 eb2 
 
 cW > 
 eb7 
 
 cW' > 
 out 
 
 av n = 107 [dV. - av + - A] - 10B . (5.53) 
 
 9 m out 
 
 where 
 
 a = -av + av 
 
 eb2 ebl 
 
 and 
 
-U7- 
 
 b = av , _ 
 
 eb7 
 
 are positive numbers since by equation (5.52) 
 
 - av , . > o 
 
 eb2 
 
 + cW , . > 
 ebl 
 
 + av _ > o 
 
 eb7 
 
 Thus as V. increases V increases but the increase is reduced by the 
 mo 
 
 cW values , For the case of cW. < 0, 
 eb m ' 
 
 bV . , < 
 
 ebl 
 
 ^V , > 
 eb2 
 
 cW < 
 eb7 
 
 c*V < 
 out 
 
 where 
 
 cW p = 107 [dV. - cW' + C] + 10D (5.55) 
 
 o m out 
 
 C = cW - av > 
 
 eb2 ebl 
 
 d - -av uv > 
 
 eb7 
 
 (5.5*0 
 
 since by equation (5.5*0 
 
 9V eb2 > 
 - 3V ebT > ° 
 " aV S bl > ° 
 
-1+8- 
 
 As V. decreases V decreases but the effect of the V 
 
 in 8 eb 
 
 variations will be to reduce the decrease. 
 
 The conclusion from these two cases is that the effect of the 
 
 V . parameters on the circuit will be to reduce the gain at V n below its 
 eb 8 
 
 theoretical value which assumes V , = constant. 
 
 eb 
 
 If a similar analysis is carried out for V , a similar result 
 
 will be obtained. The effect of V . variations will thus tend to reduce 
 
 eb 
 
 the overall amplification of the circuit slightly below its theoretical 
 value. 
 
 5.11 V . Variations and Linearity 
 — eb — — iL - 
 
 Such variations in V , will make the amplification of the circuit 
 
 eb B 
 
 difficult to predict although it is ultralinear. But it is not necessary 
 that the gain be within 0.5 per cent of a specified value since the 
 potentiometer settings in the voltage dividers of Figure 8 can be adjusted 
 according to the value of the gain. The important point is that the gain 
 be extremely constant . 
 
 Before investigating the effect of V variations on linearity, 
 the various current levels in the circuit will be determined. It is easily 
 verified that the approximate current levels are as shown in Table 1. 
 The equations for cWq and dV are 
 
 cWo = 107 [dV. - av. + dV KO (-iJ - av ..(ij] 
 
 o in out eb2 1 ebl 1 
 
 (5.56) 
 
 " 10aV eb7 ( V 
 
 av = io T [dv ln - av; ut + av (i ) - dv ebU (-i 2 )] 
 
 + 103T ebl ( 1 10 ) • 
 
 (5.57) 
 
4 9 - 
 
 Table 1. Current Levels for -10 < V < +10 volts 
 
 - out — 
 
 I- - - 
 
 iCurrent 
 
 min, - ma 
 
 max, - ma 
 
 : h 
 
 .25 
 
 .68 
 
 *2 
 
 .32 
 
 .75 
 
 1 
 
 *3 
 
 .25 
 
 ,68 
 
 h 
 
 ,20 
 
 .63 
 
 s 
 
 .955 
 
 .955 
 
 l 6 
 
 .88 
 
 .88 
 
 h 
 
 1.08 
 
 3.08 
 
 ^ 
 
 10 
 
 10 
 
 h 
 
 10 
 
 10 
 
 \o 
 
 1,08 
 
 3.08 
 
 The variation in current in the input stage is quite small as 
 
 is the current level, This portion of the V . versus i curve should 
 
 eb c 
 
 have a rather linear variation in V , and positive increments in V , should 
 
 eb eb 
 
 be nearly the same as negative increments for equal and opposite i 
 
 increments, The V , variations in the difference amplifier stage were seen 
 
 eb 
 
 not to cancel, as the two V . values do, but to add. Due to the low current 
 
 eb 
 
 levels, the V , variations will be quite linear. Since the total current in 
 > eb i • 
 
 both transistors is constant the entire first stage variation will be very- 
 linear. The variation in V , in the second stage transistors should be 
 
 eb 
 
 about the same as in the first stage since the current range is wider but 
 
 the values are higher thus reducing the slope of the V , versus I curve, 
 
 •=> r eb c 
 
 These portions of the V , versus I curve can be linearized and treated 
 
 eb c 
 
 as straight lines such that equal and opposite increments of current 
 produce equal and opposite changes in V . 
 
-50- 
 
 These variations in V . will thus be quite linear and the voltages 
 
 eb to 
 
 at Vq and V should increase linearly; thus, the gain remains rather constant 
 even though V varies and its variation is multiplied by the gains of the 
 various stages . 
 
 5.12 Influence of Thermal Variations 
 
 Figures 19a and 19b show a PNP and a NPN transistor amplifier 
 corresponding to T and T , the second stage amplifiers of Figure l6. 
 
 -f V 
 
 + 2 
 
 O v. 
 
 O u 2 ~d 2 
 
 (a) PNP (b) NPN 
 
 Figure 19 . Transistor Amplifier Stages. 
 
 The power dissipation for the PNP amplifier is determined 
 
 as follows 
 
 v - u i - d i 
 
 l = 
 e 
 
 R 
 
 v. = -z + r i = -v_ + a ~ (v - vl - a ) 
 
 1 c C Z R 11 
 
 e 
 
-51- 
 
 P cl = (U L + d l ' V l } \ 
 
 e e e 
 
 where 
 
 1 eb7 
 
 The pcwer dissipation for the NPN amplifier is similarly determined 
 
 as follows 
 
 1 = 
 
 u 2 - d 2 + .T 
 
 e R 
 
 v 2 = z-R c i c = z-a^(u 2 -a 2+ v) 
 
 e 
 
 P c2 ^ ( " U 2 + d 2 + V 2 ) *c 
 
 p c2 = [ -u 2 + a 2 + z - a f (u 2 - a 2 + v )] r (u 2 - a 2 + v) 
 
 e e 
 
 where 
 
 d 2 = V belO • 
 
 R 
 Denoting CC — = g = gain of the amplifier stage^ the power dissipation can be 
 
 e 
 plotted as in Figure 20a and 20b. The actual values are listed below the 
 
 graph and the initial value of u - ± and u + d, is shown (u at V. - V = 0), 
 
 The voltages vl + d and ul - cL vary by about +0.8 volts from their 
 
 initial value for an output voltage range of +8 < V < -8 volts. Over this 
 
 — out — 
 
 range of operation the P versus u curves can be linearized and approximated 
 
 c 
 
 as straight lines. 
 
■52- 
 
 (a) PNP 
 
 (b) NPN 
 
 Figure 20. Power Dissipation for the Transistor Amplifier 
 Stages of Figure 19'a,b). 
 
-53- 
 
 An V. increases both u. and u_ decrease, and as V. decreases 
 in 1 2 * in 
 
 both u and u increase „ Also, due to the circuit topology u and u 
 
 always change by equal amounts and in the same directions.. As u + d 
 
 increases P . increases, but as u - d^ increases P _ decreases and vice 
 cl 2 2 c2 
 
 versa. Since these portions of the power dissipation curves have been 
 linearized the increases in P equal the corresponding decreases in P , 
 Thus 
 
 du = du 
 
 cip . = ap _ . 
 
 cl c2 
 A similar analysis performed on both first stages yields the 
 
 following results : 
 
 ai 3 = ^i 2 
 ai 1 = di k 
 
 ap . = ap h 
 
 cl c4 
 
 dp = ap _ - -ap , = -ap . . 
 
 c3 c2 cl cU- 
 As power dissipation increases,, junction temperature increases, 
 
 the increase being determined by the thermal resistance of the semiconductor. 
 
 AT = SAP 
 c 
 
 It can be shown that as temperature increases V decreases. The 
 
 emitter current is proportional to the minority carrier density just inside the 
 
 base since the forward current across a FN junction is largely holes. This 
 
 forward current is approximately proportional to this minority carrier 
 
 density divided by the base width. If the emitter current is to remain 
 
 unchanged for two temperatures T and T } the hole density must remain 
 
 constant as temperature varies. Defining p as the minority carrier 
 
 bn 
 
 density just inside the base at temperature T , it follows that: 
 
For E » V. . V r 
 
 R 1 c 
 
 Thus 
 
 -3k- 
 
 c ^ 1 qv„ 
 
 p bi exp - ( ^ } = p b2 exp - ( kT^ 
 
 Pun q. V o V n n -n 
 
 -bl = exp.[ (-£- +)]~^ 
 ^>b2 k T 2 T l "i2 
 
 Pv,-, Ell 
 
 :— - exp.[-q - & (— - =-) 
 
 p d2 k r x i 2 
 
 E - V E - V n 
 
 _S 2 . _g 1 
 
 T T 
 
 2 1 
 
 T AT E V V 
 
 T ^ T!/ V n E E 
 1 1 i JL g g 
 
 E 
 g 
 
 AT ~ AV __ ,ATs 
 T E ' AV - - ( T ) E 
 
 1 R 1 
 
 It has been found experimentally that, for Germanium and Silicon 
 transistors, for currents in the ma range, V decreases by about 2.5 mv for 
 each degree centigrade increase in temperature. 
 
 Hereafter P will denote the collector power dissipation of 
 
 transistor n and T' will denote the junction temperature of transistor n. 
 
 n 
 
-55- 
 
 5-13 Effect of Therma l V , Variations 
 ■ ~> , eb 
 
 As V. increases P . P^, and P^ decrease and P n , P, , and P n ^ 
 in 2' 3 7 1 *+ 10 
 
 increase; thus T', T' and T' decrease and T" , Tt, and T' increase; thus 
 
 V , _, V a nd V , _ increase; and V .'. and V , n ^ decrease. Similarly 
 eb2' eb3 eb7 ebl^ eblO 
 
 as V. decreases P^, P , and P^ increase and P., P, , and P n _ decrease; thus 
 m 2* y 7 1 V 10 ' 
 
 T*. T" and T' increase and T' T,' , and T' decrease; thus V . n3 V ._. and 
 
 2' 3 7 1 *+ 10 eb2' eb3 
 
 V , _ decrease and V , _. V , , . and V , _ . increase 
 eb7 ebl' ebV eblO 
 
 By equations (5.56) and (5° 57) these thermal V variations are 
 observed to cancel since 
 
 cW ._ = -cW 
 
 eb7 eblO 
 
 ebl ebk eb2 eb3 
 
 Similar results are observed if V. decreases „ 
 
 m 
 
 This tends to produce a circuit which is not affected by 
 temperature variations over the desired output range . 
 
 5 „1^ Output Stage Com pensation 
 
 The analyses of the previous sections have produced the following 
 results : 
 
 (1) Parameter variations due to current levels will tend to 
 decrease the gain at Vn and V, and these variations will 
 be approximately linear „ Thus,, Vo will tend to vary by the 
 same amount and in the same direction as V , 
 
 (2) Thermal variations due to temperature tend to cancel at 
 V Q and V^ 
 
 Obviously the linear approximations used are not exact and the 
 variations at Vo and V will not be exactly linear or drift— free. The 
 
-56- 
 
 constant-current output stage will further compensate for any deviations 
 
 present at Vq and V . 
 
 By defining d(v\ - V Q ) as the deviation in (V_ - V D ) from its 
 9 o y o 
 
 initial value at V. = V , = 0, the effect of the output stage may more 
 
 easily be discussed. 
 
 If d(V - Vq) > 0, implying that V has increased by more than 
 
 V n . a large output current would be expected and V would be too large, 
 o' out 
 
 This does happen actually but the error is drastically reduced. 
 For 
 
 3(V 9 - Vg) > , 
 
 \ - \ - v eb9 + v zl + v + v Z£ + v eb8 , 
 
 the modified output stage current increases. Thus, 
 
 3V eb 9 > ° 
 SV eb8 > ° 
 
 av zl >0 
 Sv Z2 >0 
 
 which implies 
 
 * V 9 " V " (dV eb 9 + SV Z1 + 3V Z2 + dV eb 8 ) " 3 \ 2 
 
 The change in V , and V^ is about the same and for 
 eb Zi 
 
 ^(V 9 - Vq) « .3 v , ^ S ^ S 50 mv 
 
-57- 
 
 Therefore cW ~ Q,lv, which shows that much of the nonlinearity 
 
 22 
 
 has been accounted for by V , Q , V . V r71 , and V^ variations The variation, 
 
 J ebo' eb9 Zl' Z2 ' 
 
 cW^ , is reduced further by the fact that cW = KcW where K is 
 
 R 22 1X R 22 
 
 approximately Q5. Thus in the experimental values above, cW ~ 0.05 volts . 
 
 Thermal variations are similarly reduced at V by a factor of about 
 one-fourth. 
 
 The gain of a single two-stage amplifier as used in Figure l6 has 
 
 been found to be constant within two per cent for Germanium and 
 
 2.7 per cent for Silicon transistors. The error of the amplifier of Figure 
 
 l6 is 0.33 per cent. This is one-sixth of the error of a single two-stage 
 
 amplifier. This factor of one-sixth is the same as appeared above in 
 
 the experiment involving variations in the modified constant- current output 
 
 stage parameters . 
 
 As V„ increases, V Q increases thus P „ decreases, and P Q increases, 
 9 o 7 cy ' co ' 
 
 or vice versa. It is easily shown that 
 
 SP 9 " " SP 8 
 since emitter currents are constant, Thus^ 
 
 bl 9 = -dig. 
 
 From which 
 
 eb9 ebo 
 
 Thus the temperature changes in Tq and T are such that they tend to 
 maintain the output voltage at its proper value and the modified output' 
 stage current constant. 
 
-58- 
 
 Similarly, the output stage reduces any thermal drift present at 
 Vq and V by a factor of about one- fourth. Its effect in reducing linearity 
 variations at V and Vn is considerably higher, the factor being about one- 
 sixth. 
 
 Due to the effect that lU and T have in reducing thermal drift 
 and improving the linearity of the gain and the effect that T and T ft have 
 in further reducing these errors, T and T and Tq and T will be designated 
 circuit- compensating transistor pairs since their compensating ability is 
 due to their position in the circuit and not to a match of transistor 
 parameters „ 
 
 5 .15 Experimental Data 
 
 Table 2 contains experimental data on the voltage amplifier of 
 Figure l6. A digital voltmeter, accurate to within 2 mv was used for these 
 measurements. The fact that the digital voltmeter had this error made it 
 necessary to step down a high input voltage in order that readings accurate 
 to below 1 mv could be obtained. An error of 2 mv in the reading of an 
 input voltage would be magnified by 21 and the output voltage would be 
 accurate only to within k-2 mv. This is approximately twice the error of the 
 voltage amplifier . 
 
 For these reasons the input column is headed V! . Column three 
 
 * in 
 
 shows the increments in V for equal increments in V. . All of the 
 
 out in 
 
 output increments are accurate to within 0.8 per cent of the average value, 
 the largest difference being 28 mv. Column four shows the gain of the 
 amplifier calculated to four figures . The gain is seen to be extremely 
 linear, the largest deviation from the value G = 21. 38 is 0.33 per cent. 
 Column five shows the deviation in output voltage caused by a load requiring 
 10 ma at all voltages. The largest error due to loading was observed to be 
 a 15 mv decrease in output voltage. 
 
-59- 
 
 Table 2. Test Data. 
 
 V (volts) 
 in 
 
 V (volts) 
 out 
 
 AV (mv) 
 out 
 
 Gain 
 
 V Loaded 
 out 
 
 (mv) 
 
 0.000 
 
 0.000 
 
 
 
 -8 
 
 
 41,000 
 
 +1.020 
 
 1020 
 
 21 . 42 
 
 -8 
 
 
 +2.000 
 
 +2.036 
 
 1016 
 
 21.38 
 
 -10 
 
 
 +3.000 
 
 +3.060 
 
 1024 
 
 21.1+2 
 
 -10 
 
 
 +4.000 
 
 +4.064 
 
 1004 
 
 21.34 
 
 -10 
 
 
 +5.000 
 
 +5.086 
 
 1022 
 
 21.36 
 
 -12 
 
 
 +6„ooo 
 
 +6.100 
 
 1014 
 
 21.36 
 
 -12 
 
 
 +7.000 
 
 +7.120 
 
 1020 
 
 21.36 
 
 -12 
 
 
 +8 . 000 
 
 +8.135 
 
 1015 
 
 21.36 
 
 -14 
 
 
 +9 . ooo 
 
 +9.166 
 
 1031 
 
 21.38 
 
 -15 
 
 
 o 000 
 
 +0.008 
 
 
 
 
 
 -1.000 
 
 -1.015 
 
 1015 
 
 21.32 
 
 -9 
 
 
 -2.000 
 
 -2.039 
 
 1024 
 
 21. 41 
 
 -8 
 
 
 -3.000 
 
 -3.050 
 
 1011 
 
 21.35 
 
 -9 
 
 
 -4.000 
 
 -4.082 
 
 1032 
 
 21.42 
 
 -9 
 
 
 -5.000 
 
 -5.100 
 
 1018 
 
 21.42 
 
 -8 
 
 
 -6.000 
 
 -6.125 
 
 1025 
 
 21.44 
 
 -8 
 
 
 -7.000 
 
 -7.140 
 
 1015 
 
 21.42 
 
 -8 
 
 
 -8.000 
 
 -8.160 
 
 1020 
 
 21.42 
 
 -8 
 
 
 -9.000 
 
 -9.166 
 
 1006 
 
 21,38 
 
 -8 
 
 
-6o- 
 
 The largest output offset voltage (V , when V = 0) was 
 
 ° out in 
 
 observed when the input was kept at its maximum or minimun value for a 
 while and then grounded. The maximum such offset voltage observed was 
 8 mv. 
 
 The largest drift was observed at the higher voltages when the 
 input was kept at its maximum or minimum level and then the polarity 
 reversed. The largest such drift observed was 8 mv. 
 
 5.l6 Component Replacement 
 
 The resistor values have been chosen so that the potential 
 
 difference across R in Figure l6 is 1.0 volts with the high side being 
 
 +0.6 volts and the low side being -0.U volts. These values assume a V . 
 
 eb 
 
 of 0.1*+ volts for Germanium and O.78 volts for Silicon transistors (Tq, T ). 
 
 The value 1.0 volts is not critical; it is only necessary that the voltage 
 
 be in the neighborhood of 1.0 volts and that the value about O.lU volts be 
 
 somewhere within the 1 volt range at V. =0 for zero offset. The 
 
 D in 
 
 collector resistors R/- and R place an upper limit on the collector current 
 and on the voltage across the potentiometer. This upper limit is found from 
 
 V Z1 + V Z2 + X c + 2V eb + 2V cb " 2(5 ° " I c ) (5 - 58) 
 
 Assuming 
 
 V , = .78 v for Silicon Transistors 
 eb 
 
 V . . = 1 v for Silicon Transistors (5.59) 
 cb min 
 
 V = V = 2.9 v 
 Zl Z2 y 
 
 The maximum collector current is 
 
 I * 19 ma (5.60) 
 
 c 
 
-6l- 
 
 This voltage increment of 1.0 volts will vary somewhat as 
 
 transistors are interchanged but this voltage difference was found sufficient 
 
 to account for most V , and (3 variations between transistors. Naturally, 
 
 eb 
 
 to keep the circuit values as given, Germanium transistors must be replaced 
 
 only by Germanium units, and similarly for Silicon transistors. 
 
 New resistor values could be calculated if it was desired that 
 
 all of the transistors be Germanium or Silicon. The only two resistors 
 
 that would have to be changed would be R s and R which determine the 
 
 magnitude of the constant-current source and sink. 
 
 The V , versus I curve for Germanium is rather linear and the 
 eb c 
 
 knee is not very pronounced. For this reason it is quite easy to find 
 
 replacements for Germanium units since for almost all Germanium transistors 
 
 the I = 0.5 ma point is situated such that the curve of V , versus I can 
 c eb c 
 
 be quite easily linearized in the used region surrounding this operating 
 
 point. 
 
 The knee of the V , versus I curve for Silicon is more pronounced 
 eb c 
 
 than in Germanium units and its position is not nearly the same between 
 
 two different NPN or PNP types. In general it has been observed on a 
 
 curve—tracer that the knee occurs at values as low as I = 0.1 or 0.2 ma 
 
 c 
 
 in Silicon PNP units and as high as I = 0.8 ma in many Silicon NPN units. 
 
 For this reason when using this amplifier with all Silicon transistors 
 
 more care must be given to the choice of current levels in the input 
 
 difference amplifiers. If nonlinearities are observed at the output, data 
 
 can be taken for dV„ and dV" for V. = + 0.2 volts, V. =: + 0.3 volts, 
 
 7 10 in — 'in — ' 
 
 and V. = + O.k volts. It has been found that cW^ or cW. n _ will be 
 in - 7 10 
 
 constant for either positive or negative increments in cW. and not 
 
 to in 
 
 constant for the opposite signed increments. This information will tell 
 whether the I operating point is sufficiently above or below the knee of 
 
the V curve to use a linear approximation or whether the operating 
 
 point is too close to the knee of the curve, thus indicating an increase or 
 
 decrease in the operating point current, I . 
 
 For the two Silicon transistors SM5306(NPN) and 2N3638(PNP), the 
 
 following values were changed to increase the current in the PNP difference 
 
 amplifier by a factor of four. This was necessary since the knee of the 
 
 V curve for the 2N3638 occurs at about 0.5 ma. 
 
 R - U.65 K a R 12 = 1.3 K 
 
 r i8 = 10 a R . = 15 K fl 
 
 R = h K a R 1 = 10 K fl 
 
 R = R^ = 62 n R l6 =2.?Kfi 
 
 All other values are as before. 
 
 It is much easier to obtain an operating current on the V 
 
 versus I curve where the useable portion of the curve may be linearized 
 
 by increasing the currents. Care should be used in increasing these input 
 
 stage currents since the thermal drift increases by about the same factor 
 
 by which the first stage currents are increased. This follows from 
 
 equations (5.5^) and (5.57) and a consideration of the magnitudes of 
 
 AP -. j, 4. and AP , AP ~. . , will be increased 
 c first stage c second stage c first stage 
 
 by approximately the factor by which the input stage currents are 
 
 increased. If the second stage currents are not changed the thermal 
 
 variations in the second stage is not sufficient to cancel the thermal 
 
 variation of the first stage. The 10 K fi and 1 K ft resistors in the second 
 
 stage could be decreased by twice the factor by which the first stage 
 
 currents were increase thus increasing AP -, , , enabling the 
 
 c second stage' ° 
 
 second stage thermal drift to be of sufficient magnitude to cancel the 
 first stage thermal drift. It is thus much better, if the magnitude of I 
 
 at the V , knee allows, to decrease the first stage currents and increase 
 
 eb ' 
 
 the first stage resistors to obtain linearity of operation without a 
 corresponding increase in drift. 
 
-6 3 - 
 
 5.17 Output Range 
 
 An output range of -10 < V < +10 volts was desired. This is 
 
 determined by the circuits which the voltage amplifier must drive. 
 
 An output of -12 < V < +12 volts can be tolerated. The +10 volts 
 
 out 
 
 collector supply of T n insures the upper limit on V . To determine the 
 
 _L± out 
 
 lower limit on V the critical voltages and currents at which the various 
 out 
 
 transistors cut—off is investigated. 
 
 Transistor T 
 
 1-L = ^ + Vln g R V ° Ut = »^TT + A55 V. n (5.6l.) 
 
 The maximum i , 
 
 i = „955 ma = i , (5.62' 
 
 1 max, y y 5 
 
 occurs at 
 
 V. = l o 05 v . (5.63) 
 
 in ' ' 
 
 The minimum i , 
 
 1 __._ = ma^ (5o6U) 
 
 mm, 
 
 occurs at 
 
 V. = -1.05 v . (5.65) 
 
 in 
 
Transistor T, 
 
 ■6k- 
 
 H 
 
 1 3 = 2' 
 
 V. - V 
 in out 
 
 2R„ 
 
 = .kh - .J+55 V 
 
 m 
 
 (5.66) 
 
 The maximum i , 
 
 i = 0.88 ma = \ r , 
 3 max . o ' 
 
 (5.67) 
 
 occurs at 
 
 V. = -0.97 v 
 in 
 
 (5.68) 
 
 The minimum i , 
 
 i = ma , 
 3 min. 
 
 (5.69) 
 
 occurs at 
 
 V. = 0.97 v 
 in 
 
 (5.70) 
 
 As above, for any inputs outside of this range, the value of i_ and i 
 remain at their maximum or minimum, the only limits being on the collector 
 base junctions of the transistors. 
 
 Transistor T, 
 
 7 
 
 The collector base junction of T must also be properly biased, 
 
 that is, 
 
 ■ 25 + -&- • i- - R_ V 
 
 R 
 
 10 
 
 "1 
 
 < 10 - R, i , 
 5 eb7 4 1 
 
 (5.71) 
 
-6 5 - 
 
 Assuming average V . values 
 
 ° eb 
 
 i < .686 ma 
 
 V < ,k6l v 
 in 
 
 (5.72) 
 
 Transistor T 
 
 The collector base junction of T must be properly biased, that is, 
 R i 
 
 25 - (J8-a - V eblQ ) R 8 > -10 + k.n . (5.73) 
 
 11 
 
 Assuming average V , values 
 
 eb 
 
 i- < °655 ma 
 
 V. > - U75 v 
 in 
 
 (5.7*0 
 
 From the critical voltages and currents determined above, the lower 
 
 limit on V can be calculated, 
 out 
 
 V . occurs at 
 out mm. 
 
 V. *, -A75 v . (5.75) 
 
 in 
 
 At this input value 
 
 i- = .655 ma 
 
 (5.76) 
 
 i = .22 ma 
 
 Thus, 
 
 V 9 = -l.k v (5.77) 
 
-66- 
 V 8 . -16.2 v (5.78) 
 
 \ 2 " " TA " V eb 9 " V Z1 " ( - 16 - 2 + V eb8 + V Z2 } = '^ 2 ' ^±] 
 
 = 1.2 v 
 
 (5.79) 
 
 V . . ~ .11.6 - v ... (5.80) 
 
 out mm. ebll 
 
 V , ~ -11.75 v . (5.81) 
 
 out max. w ' 
 
 The experimentally measured value is 
 
 V , . -11.5 v . (5.82) 
 
 out mm. 
 
 This is within the tolerable range and is acceptable. The originally 
 
 desired range could be obtained by inserting a diode from the base of T 
 
 to the -10 volts supply. This is not necessary in this application however. 
 
 The zener diodes Zl and Z2 are necessary to obtain an output 
 
 range of at least -10 < V < +10 volts due to the +10 and -10 volts 
 
 - out - 
 
 supplies on T and T . These supply voltages limit the maximum and 
 
 minimum values of V Q and V\. The range of V Q and V" could easily be 
 
 09 o9 
 
 extended by replacing the +10 and -10 volts supplies by +25 and -25 volts. 
 
 This however requires that T and T be chosen such that the collector-to— 
 
 base breakdown voltage is at least 35 volts. This transistor specification 
 
 is avoided by inserting Zl and Z2 to step down the range of Vq to 
 
 -lU.2 <: Vq < +5.8 volts and to step up the range of V to -5.8 < V < +1^.2 
 o 9 9 
 
 volts, thus enabling T and T to remain conducting throughout the 
 desired output range. 
 
-67- 
 
 5.l8 Input Range 
 
 There are certain limits on the input voltage since for 
 
 V > 0.97 volts the base of T ^ is at -10 volts and for V. < -1.05 
 in — 10 in — 
 
 volts the base of T is at +10 volts. Thus the allowed input range is about 
 
 -9 < V. n < +9 v (5.83) 
 
 to insure the proper collector— to— base bias on T and T 
 
 The maximum value that V can have in its Paramatrix application 
 
 m 
 
 occurs when a point on the edge of the matrix with coordinate voltage +8 volts 
 is magnified by four and shifted right by l6 volts. Thus V. can become 
 
 V. = ~ [8m + a] 
 in max, 
 
 V si- (48) (5.84) 
 
 in max, 20 v ' KJ ' 
 
 V. ~ 2.4 v 
 in max. 
 
 The possible range of V. is thus 
 
 in 
 
 -2,4 < V. < +2,4 v . (5.85) 
 
 in 
 
 Thus, there is no need for bumping diodes at the input to the voltage 
 amplifier since the allowed range of equation (5 083) is not exceeded as 
 shown by equation (5.85)0 
 
 The input impedance of the voltage amplifier is essentially the 
 parallel combination of the collector resistance of R and R 
 
 Z. * 600 K n 
 In 
 
 Since one input transistor is an NFN and the other a FNP, the base 
 current at the input is less than it would be for a single two-stage 
 
-68- 
 amplifier. This reduces any error due to current flowing into or from 
 the summing point of the second stage voltage divider. 
 
 5 .19 frequency Range 
 
 The only limitation on the speed of operation appears to be the 
 choice of transistors. The higher the alpha cut-off frequency of the 
 transistors used, the better the frequency response. Fast zener diodes 
 should also be used. With the transistors listed in Figure ]6, the circuit 
 performs satisfactorily with a 500 kc square-wave input with a rise time of 
 200 ns and a fall time of 100 ns. With Silicon SM5306 and 2N3638 transistors 
 the circuit performs satisfactorily over 1 mc with rise times of 100 ns and 
 fall times of 100 ns. 
 
 5 .20 Single Two-Stage Amplifier Design 
 
 It is possible, although not practical due to component replacement 
 difficulties to build one-half of the amplifier of Figure. l6 with new values 
 and with a loss of accuracy and an increase in drift. 
 
 A matched pair of very high p(p > 100 ) transistors with almost 
 identical characteristics, with |3 extremely constant and with very flat 
 collector characteristics over the desired current range, can be selected 
 on a curve— tracer for use in the input stage. 
 
 Similarly the collector characteristics for various loads can 
 be plotted. A transistor with very good linearity over a wide current and 
 voltage range and with a collector breakdown voltage greater than 35 volts 
 can be selected for the second stage transistor. 
 
 Tests on the second stage transistor with the load used in 
 plotting the collector characteristics can be tested to determine the best 
 combination of gain and current levels that produce the most linear gain. 
 
-6 9 - 
 
 A similar test can be made on the first stage transistors to 
 determine the best current levels for linearity with the stipulation that 
 the product of the first stage gain and the second stage gain is greater 
 than 100 . 
 
 In this manner the single-stage amplifier of Figure 21 was 
 designed. Its thermal drift is much worse than before, about 35 niv. Its 
 offset has increased to about 25 mv and the gain is constant within 
 one per cent. 
 
 5.21 Summary 
 
 This voltage amplifier has many advantages over other designs. 
 It has excellent drift stability and very low offset values,, both below 
 10 mv, Its output range is quite high for so accurate an amplifier. Its 
 linearity is below 0.35 per cent. The compensation techniques used to 
 achieve this unusually good stability are functions of the topology. The 
 ease of replacement of components demonstrates how free this amplifier is 
 from matched transistor pairs and various temperature compensating 
 elements. Temperature compensating diodes and thermistors cannot actually 
 be used due to the large voltage and temperature ranges since junctions 
 which cool off at one output level may heat up at the next output value. 
 The data of Table 2 was taken at d-c» When run at higher frequencies the 
 performance actually increases since input levels are on for only very 
 small fractions of seconds as opposed to fractions of minutes in a d-c test 
 Thus, the junctions will have much less time in which to heat up or cool 
 down, reducing the parameter variations considerably. 
 
 There are certain disadvantages to this amplifier. It actually 
 contains two voltage amplifiers and thus naturally has a rather large 
 number of components and is not as simple an amplifier as is possible. 
 
-70- 
 
 +25v 
 
 I 
 
 20K 
 
 > 20K 
 
 i 
 
 /^- 
 
 SM5334 
 
 3.3 K 
 
 lOOfl 100ft 
 
 4lOK 
 
 |680i2 
 
 S\. 
 
 UK 
 
 18K 
 
 IN 963 
 2 N 1308 
 
 OUT 
 
 ♦ O 
 
 i 10K S6.8K 
 
 1N963 
 
 T 
 
 -25v 
 
 WHEN NOT SPECIFIED 
 
 RESISTORS ±1%,1/2W. 
 TRANSISTORS SM1530 
 
 Figure 21. Single Two-Stage Amplifier. 
 
-71- 
 
 This was found necessary since the drift and linearity compensation desired 
 
 could not be obtained in a single two-stage amplifier. 
 
 A second disadvantage of this amplifier is that the gain which is 
 
 so exact cannot be accurately predicted due to the number of components, the 
 
 number of V . drops and other parameters which must be measured, and the 
 eb ' 
 
 unknown amount of variation which is not compensated for and which subtracts 
 from the gain. The inconvenience of having to measure the gain on a meter 
 and varying one of the feedback resistors until the desired gain is 
 obtained is a small price to pay for the accuracy which such a configuration 
 can produce. The number of components is still less than in many d-c amplifiers 
 which have much less accuracy. 
 
 A diode could be placed in series with R n and R for better 
 temperature stability although it is not really necessary here since the 
 power dissipation is rather constant in T,- and T^<. Also a zener diode 
 could be used in place of R, n and R for a more stable current source or 
 sink. This again is not necessary since P and P /■ are very constant. 
 
6 . CONCLUSION 
 
 This method of transforming line drawings which are displayed on 
 a matrix of light bulbs has many interesting features . 
 
 1. It presents new applications for hybrid analog-digital 
 circuit techniques, 
 
 2. It uses analog voltage levels to determine the matrix 
 coordinates „ 
 
 3o It employs diamond gates to gate analog signals by means 
 
 of digital ones „ 
 k It sequentially scans the matrix by digital counters . 
 5= It contains a highly accurate current amplifier with unity 
 
 voltage gain within 50 mv. 
 6. It involves an ultralinear, low drift, wideband voltage 
 amplifier capable of amplification with an accuracy of 
 0„33 per cent over a wide output range. 
 7<> It is capable of translating, rotating, and magnifying 
 
 this line drawing at high speeds. 
 The desired accuracy of this system is one-half the voltage 
 difference of adjoining coordinates or 250 mv. The accumulative worst - 
 case error of the transformer from the sine-cosine potentiometer to the 
 output of the voltage amplifier is approximately 230 mv which is within 
 the desired accuracy. 
 
 Many of these circuits, notably the ultralinear voltage 
 amplifier, have applications in many areas of engineering research. 
 Various compensation techniques used in this amplifier have produced, over 
 a wide voltage range, accuracies previously unattainable without the use 
 of integrated circuit techniques or extensive chopper and rectifying circuits 
 
 -72- 
 
-73- 
 
 Amplifiers with very high accuracies are normally limited to 
 frequencies below 100 kc. The minimum error of integrated circuit amplifiers 
 is about one per cent and few of these had an output range of 20 volts. 
 The amplifier described herein has an error of 0.33 per cent, a 20 volts 
 output range, and can operate with a 1 mc square-wave input , 
 
 There are many possible applications for this ultralinear voltage 
 amplifier. With a resistive summing network with a variable summing resistor, 
 as an input circuit, the gain of the entire circuit can be varied from 1 
 to 20. If one input to the resistive summing network is connected to a 
 variable power supply, the aforementioned variable gain is possible as well as 
 a level- shifting of the output voltage. 
 
 Other obvious applications for such an amplifier involving 
 different peripheral equipment are possible as the particular application 
 warrants . 
 
BIBLIOGRAPHY 
 
 1. Joyce, M. and K. Clark, Transistor Circuit Analysis , Addi son-Wesley 
 Publishing Company, Massachusetts, I96U. 
 
 2. Korn, G. A. and J. M. Korn, Electronic Analog and Hybrid Computers, 
 McGraw-Hill Book Company, Inc., New York, 196%. 
 
 3. Middlebrook, R. D., Differential Amplifiers, John Wiley and Sons, Inc. 
 New York, 1963. 
 
 k. MilLman, J. and A. Taub, Pulse and Digital Circuits , McGraw-Hill Book 
 Company, Inc , , New York, 1956. 
 
 5. Poppelbaum, W. J. and N. E. Wiseman, "Circuit Design for the New Illinois 
 Computer," Department of Computer Science, University of Illinois, 
 Urbana, Illinois. Report No. 90. August 1959. 
 
 6. "Quarterly Technical Progress Report," (Part l), Department of Computer 
 Science, University of Illinois, Urbana, Illinois. October-December, I96U, 
 
 7„ "Quarterly Technical Progress Report," (Part l), Department of Computer 
 Science, University of Illinois, Urbana, Illinois. January-March, 19^5 . 
 
 8. "Technical Progress Report," (Part 3)> Department of Computer Science, 
 University of Illinois, Urbana, Illinois. June, 196^. 
 
 9. "Technical Progress Report," (Part l), Department of Computer Science, 
 University of Illinois, Urbana, Illinois. July, I96U. 
 
 10. "Technical Progress Report," (Part 2), Department of Computer Science, 
 University of Illinois, Urbana, Illinois. September, I96I. 
 
 11. Texas Instrument, Inc. Transistor Circuit Design, McGraw-Hill Book 
 Company, Inc., New York, 1963. 
 
 -7k- 
 
Unclassified 
 
 Security Classification 
 
 DOCUMENT CONTROL DATA - R&D 
 
 (Security classilication o/ title, body of abstract and indexing annotation must be entered when the overall report ia claaslfied) 
 
 1. ORIGINATING ACTIVITY (Corporate author) 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 61803 
 
 Za REPORT SECURITY CLASSIFICATION 
 
 Unclassified 
 
 2b CROUP 
 
 3 REPORT TITLE 
 
 Graphical Processing Using Hybrid Analog -Digital Circuitry 
 
 4 DESCRIPTIVE NOTES (Type ol report and Inclusive dates) 
 
 Technical Report 
 
 5- AUTKORt'S; (Last name, first name, initial) 
 
 Casasent, David P. 
 
 6 REPO RT DATE 
 
 August 1965 
 
 7« TOTAL NO. OF PACES 
 
 7b- NO. OF REFS 
 
 11 
 
 8«. CONTRACT OR CRANT NO. 
 
 Nonr I83I+ (15) 
 
 6. PROJECT NO. 
 
 9a ONiaiMATOR's REPORT NUMBERi'S) 
 
 • • OTMCR NfPORT NO(S) (Any other numbers that may be assigned 
 mla import) 
 
 None 
 
 10. AVAILABILITY/LIMITATION NOTICES 
 
 11. SUPPLEMENTARY NOTES 
 
 None 
 
 12. SPONSORING MILITARY ACTIVITY 
 
 Office of Naval Research 
 219 South Dearborn Street 
 Chicago, Illinois 6060k 
 
 13- ABSTRACT 
 
 By assigning analog voltages to the coordinates of a graph, drawings can 
 be electrically displayed. By means of a sine-cosine potentiometer, resistance 
 chains, and diamond gates -with appropriate gate signals from digital counters, 
 these drawings can be transformed (i.e., translated, rotated, magnified). 
 Resistive summing networks and compensated current amplifiers provide the 
 translation, while an ultralinear voltage amplifier achieves the magnification. 
 
 This ultralinear voltage amplifier consists essentially of two two-stage 
 amplifiers feeding a constant-current pre-output stage with negative feedback 
 applied to the first stages. 
 
 Thermal and nonthermal parameter variations are compensated for by a 
 linearization of the used portions of the power dissipation and V versus i 
 curves, the constant-current output stage, and circuit compensating transistor 
 pairs . 
 
 This topology produces an amplifier with a gain constant within 0.33 V er 
 cent, a 20 volt output range, a drift and offset voltage of less than 9 Wf an & 
 a frequency response of d-c to 1 mc with a square wave input. It can supply 
 10 ma at all voltage levels with an error of less than l6 mv. Component 
 replacement is possible with no loss of accuracy. 
 
 -75- 
 
 DD 
 
 FORM 
 
 1 JAN 64 
 
 1473 
 
 Unclassified 
 
 Security Classification 
 
TTnnl nasi fi fid 
 
 Security Classification 
 
 -76- 
 
 14- 
 
 KEY WORDS 
 
 LINK A 
 
 ROLE 
 
 LINK B 
 
 ROLE 
 
 LINK C 
 
 Paramatrix 
 
 Constant -current output stage 
 Hybrid analog-digital circuits 
 Ultralinear voltage amplifier 
 Circuit-compensating transistor pairs 
 
 INSTRUCTIONS 
 
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"55s.TYOF.LUNU. J -U..BANA 
 
 ca P002 V m 167(1965) 
 510 64IL6Rno C002JM 
 
 ,„„,.„,.., processor ol vlsuann