Digitized by the Internet Archive in 2013 http://archive.org/details/nornandnetworkde847huja BOCKS- R-77-8U7 J /UK. U M UILU-ENG 77 1702 x NOR (NAND) NETWORK DESIGN: ERROR-COMPENSATION PROCEDURES FOR FAN- IN AND FAN-OUT RESTRICTED NETWORKS (NETTRA-E1-FIFO AND NETTRA-E2-FIF0 ) by Jackson Kwo-Chain Hu taoary 1977 Report No. UTUCDCS-R-77-847 NOR (NAND) NETWORK DESIGN: ERROR-COMPENSATION PROCEDURES FOR FAN- IN AND FAN-OUT RESTRICTED NETWORKS (NETTRA-E1-FIFO AND NETTRA-E2-FIF0) by Jackson Kwo -Chain Hu January 1977 Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 6l801 This work was submitted in partial fulfillment of the requirements for the Jgree of Master of Science in Computer Science and supported in part by the National Science Foundation under Grant No. DCF73-03U21, 1976. Ill ACKNOWLEDGEMENT The author wishes to express his sincere gratitude to his adviser, Professor S. Muroga, for his fuidance and particularly careful reading and constructive criticism of the manuscript. The author also wishes to thank Mr. H.C. Lai for his indispensable assistance in writing this paper throughout the period of this thesis research. The financial support of the Department of Computer Science and the National Science Foundation under Grant No. DCR 73-03^21 is also acknowledged . IV TABLE OF CONTENTS -R PAGE INTRODUCTION 1 ^R- COMPENSATION PROCEDURES AND PROGRAMS 6 2.1 Basic principles of the error-compensation procedures 7 General organization of the original programs and the program modified for fan- in/ fan- out restricted networks 16 2.3 Modifications for fan-in and fan-out restrictions 23 2.3.1 Potential output table and subroutine POT 25 2.3.2 Replacement of connections by error-compensation and subroutine RCEC, CALS1 and RPLCF 36 2.3.3 Subroutines CONECT and FORC 50 . EXPERIMENTAL RESULTS 63 Outline of subroutine MAIN in NETTRA-E1-FIF0 and NETTRA-E2-FIF0 . .63 3.2 Results of computer experiments „ „ 66 Comparisons with some other known design procedures 75 • INHJT DATA SETUP 88 • 1 The title card 88 h.2 The parameter card 88 The function cards 92 5. CONCLUSIONS 93 -IFERENCES .9^ CHAPTER 1 INTRODUCTION The synthesis of a compact NOR or NAND network for a given switching function is important in practice, because basic gates of most integrated 2 circuits (e.g., TTL, I L and VMOS ) realize NOR or NAND functions and usually a compact network will imply smaller chip area in integrated circuits ( consequently economical implementation ). Many different approaches have been known for the design problems of networks with NOR or NAND gates. These approaches can be class ified into the following six groups: 1) Boolean algebra methods [6], [8], [21] 2) Map factoring method [20], [25] 3) Exhaustive method [7] k) Integer programming and branch-and-bound methods [h] , [17] > [22], [23], [2*0, [26], [27] 5) Network transformation methods [5], [10], [17], [18], [28], [29] 6) Network transduction procedures [1], [9], [10], [11], [12], [ik] , [191 Boolean algebra methods yield optional networks under the constraint that the number of levels is at most three. But it is time-consuming. Also does not necessarily yield optimal networks if the constraint does not hold. Map factoring method is easy to use only for functions with small number of external variables and results are not necessarily optimal. The exhaustive method generally gives optimal networks, but it takes cessive calculation time even for small networks, hence this method is not efficient for practical design. The integer programming and branch- and-bound methods can give an optimal network within much shorter time than the exhaustive method. But they are still too time-consuming if the number of gates approximately exceeds nine. The network transformation methods tranform a given network into a simpler one by reducing the number of gates and connections based on algebric properties. Since they employ only simple properties of gates and/or network configurations and usually concern only an individual gate and its connections, they are not very effective if the network to be transformed is complicated and large. The network transduction procedures are recently developed by the research group let by Professor S. Muroga of the Department of Computer Science at the University of Illinois . "Transduction" means "transformation" and "reduction". These transduction procedures transform a given network, but unlike the transformation methods, they use the concept of com- patible set of permissible functions (CSPF) [11], in removing gates and connections from the network. The network transduction procedures can remove gates and/or connections, and they can replace the output (or fan-out) connections from a particular gate to other gates by the output connections of other existing gates and/or external variables in the network. Therefore, a transduction often involves a complete restructuring of the network. Usually, the transduction procedures can be classified into the following three groups according to their characteristics and capabilities. Pruning procedures : They are transduction procedures which only remove redundant connections. But as a result of the removal of redundant • gates may be redundant and may be removed. [1], [15] 3 2) General Procedures: They are of a general type of transduction procedures which either remove or add and then remove connections without making any change in output functions in a network. [2], [12], \lk], [l6] 3) Error-Compensation Procedures: These procedures try to remove gates one at a time and then to compensate for the errors due to the re- moval of gates. This procedure is much more complex and general than the previous (l) ami (2), though much more effective [9], [13]. Nine computer programs for designing NCR-gate networks by the transduction procedures have been implemented [2], [13], [15], [l6]. These programs are known as "transduction programs". The names of these transduction programs begin with NETTRA ( NETwork TRAn sduction). The programs which realize "pruning procedures " are designated "NETTRA-P" (including NETTRA-P1, NETTRA-P2 and NETTRA-PGl). The programs which realize "general procedures" are grouped in "NETTRA-G" type (including NETTRA-PGl, NETTRA -Gl, NETTRA-G2, NETTRA-G3 and NETTRA-G^). Finally, we call those procedures which realize "error-compensation procedures" the" NETTRA-E" type programs (including NETTRA -El, NETTRA-E2, and NETTRA-E3). Although the network-transduction procedures can not guarantee the optimality of the network, they, in general, can produce a network with a reasonably good cost. They also take much less computation time than any other method especially when the networks contains many gates and connec- tions. Hence, from the practical view point, they are very effective and efficient in NOR (NAND) network design. The original network transduction programs mentioned above can only treat problems which do not have any fan-in, fan-out restrictions. But because most of logic gates do have fan-in and fan-out restrictions, several of the network transduction procedures have been modified recently so that they can design under fan-in and fan-out restrictions. In other words, NETTRA-PG1 and NETTRA-G3 were modified by B. Plangsiri. NETTRA-G1 and NETTRA-G2 are modified by K. Hohulin. After modifications, suffix, "-FIFO" is added in the original name of each of these programs, such as NETTRA-PG1- FIFO and NETTRA-G1-FIF0. In this paper, the error-compensation procedures under fan-in, fan-out restrictions will be discussed. The error -compensation programs NETTRA-E1 and NETTRA-E2 which were originally implemented by H. C. Lai and J. N. Culliney are modified. The discussion in this paper will concentrate on the modifications, so readers are assumed to be already familiar with the concept of compatible set of permissible functions (CSPF's), which is the basis of transduction procedures. * The basis of error-compensation procedures are simple. These can be outlined in the following way: For any given network (either single-output or mutliple-output) , we remove a gate which is not an output gate and is selected according to an appropriate order [9]. If the outputs of the network remain the same, the selected gate is obviously redundant and it can be actually removed ; if the outputs do change, then we try connecting some external variables and/or the outputs of other existing gates (based on the concept , reconstructing the remaining network to compensate for changes which are called "errors". If we can do so, the selected !SFF is not used in ] A-EL, P2. gate can be actually removed; otherwise we have to select another gate and do a similar test. After all gates have been selected and tested, we obtain a simplified network, otherwise the network can not be simplified by this procedure. The procedures which are used to implement this idea are heuristic. These will be reviewed in the next chapter in more detail. This paper is organized as follows. In section 2.1, the basic principles of error -compensation procedures will be reviewed in detail. The general organization of programs NETTRA-E1, NETTRA-E2, NETTRA-E1-FIF0 and NETTRA-E2-FIF0 will be discussed in section 2.2. The reader can find in this section how the fan-in, fan-out restricted problems are treated. In sections 2.2 and 2.3, the definitions of several important variables and the functions of some important subroutines which were used in the original NETTRA-E1 and NETTEA-E2 programs will be reviewed. The modifi- cations of those subroutines for fan-in, fan-out restrictions will also be explained in section 2.3. Chapter 3 discusses the experimental results. In section 3.1, subroutine MAIN for NETTRA-E1-FIF0 and. NETTRA-E2-FIF0 will be outlined. In section 3.2, the results of computer experiments will be shown. Finally, in section 3.3, the comparisons of error -compensation programs with other transduction programs will be given. Chapter k provides the description for the input data set-up and. Chapter 5 gives the conclusion. CHAPTER 2 ERROR-COMPENSATION PROCEDURES AND PROGRAMS Error-compensation procedures are the most complicated one among all transduction procedures (i.e., procedures (l), (2) and (3) mentioned in chapter l). Error-compensation programs are most effective programs among all trans- duction programs. In this chapter, the basic principles of the procedures, the organization of error-compensation programs and the modifications for fan-in, fan-out restrictions will be explained one by one. Since the concepts of CSPF (Compatible Set of Permissible Functions) and CSPFE [11] (Compatible Set of Permissible Functions with Errors) are the bases for the error-compensation procedures, their definitions are reviewed first. [Definition 2.1] _ A function f is called a permissible function for I, which is a gate output, a connection or an external variable, if after replacing the function realized at I by f , the outputs of the given net- work do not change. The set of permissible functions for I is denoted by G(l). [Definition 2.2] - The set of all permissible functions for each I is called the maxium set of permissible functions (MSPF) , denoted by G w (l). M In this paper, a connection, which is different from an external variables, means an interconnection between two gates. [Definition 2.3] - All sets G(l) of permissible functions con- cerning to a given network are said to compatible if the following condition is satisfied for all possible selection of subset U of gate outputs and input functions. 1) For each element u in U replace this element by a gate output from a network which realizes one function in G(u). 2) After step (l), we get a new network. In this network any element w which is not contained in U realizes some function contained in G(w). 3) The above condition is satisfied for all combinations of functions we select from sets of permissible functions in step (l). In the CSPF of a gate output or an external variable, if there are some error-components, then this CSPF will be called a CSPFE (Compalible Set of Permissible functions with errors). 2.1 Basic principles of the error-compensation procedures For any given NOR network, the error-compensation procedure selects a gate from that network according to some order (e.g., according to the number of ones a gate has in its CSPF), assumes the selected gate is removed, and/then checks the outputs of the network to see wheather the outputs of the network change or not. If the outputs do not change, then the selected gate is redundant and can be actually removed. If the outputs of the network change, then the restructuring of the network by adding and/or deleting connections from external variables or gates to other gates is attempted to compensate for the changes (i.e., error). The selected gate becomes redundant if the error- components in the output functions of the network can be compensated for. 8 If the error-components can not be compensated for then the selected gate can not be actually removed. Once a gate is actually removed, the compatible set of permissible functions of the network will be recalculated, and the same procedure is applied to the -simplified network. The probability of compensating for the error -components is quite limited if the functions which are used to compensate for the errors are selected from the outputs of gates in the current network. The idea of constructing potential output table is then developed to increase the probability of compensating for the errors. The principles used in con- structing potential output table is the triangular condition in a NOR or NAND network. In a loop-free NOR or NAND network if three gates are connected to one another to form a triangle, as shown in fig. 2.1-1, and the output of gate J is connected to gate K only, then the connection from the highest level gate to the second highest level gate is redundant for realizing the output of the lowest level gate. Conversely, if two gates are both immediate predecessors of another gate, adding a connection between the two will not affect the output of the other gate. Similarly, if three gates are all immediate predecessors of another gate, as shown in Fig. 2.1.3 (a), then adding outputs of two gates to the third gate will not affect the output of the lowest level gate. In Fig. 2.1-2 (b), the output of gate K is the same as that in Fig. 2.1-2 (a). But the out- put of gate J may be different. In Fig. 2.1-3, the output of gate K keeps the same form in any case of (a), (b), (c) or (d), but the outputs of gate J in the four cases may be different. These different outputs are called potential outputs at gate J, and they can be used to try to compensate for error components at other gates. Obviously, by making other connections, ntia] output functions can be obtained. For example, in Fig. Fig. 2.1-1 Triangular condition, the dashed connection is redundant with respect to the output of K. K (a) original network (b) network after connecting gate I to gate J Fig. 2.1-2 The outputs of gate K in (a) and (b) are the same, but the output of gate J after adding the connection in (b) is different from that before adding the connection in (a). 10 (a) original network (b) network after connecting gate I to gate J (c) network after connecting gate Ip to gate J (a) network after connecting gates I 1 and I to gate J. Lg. 2.1- The ouputs of gate K in (a), (b), (c), (d) are all the same but the outputs o • ) may be all different. 11 2.1-3, gate I , can be treated as the potential output gate by connecting gate I and/or gate J to gate I. , and gate I p can be considered as the potential output gate by connecting gate I., and/ or gate J to gate I . Apparently at most 12 possible different functions (including functions of gate I- » I p and J in the original network, Fig 2.1-3(a) ) may be obtained in Fig. 2.1-3. A more general type of triangular condition is shown in Fig. 2.1-H. In this figure, only gate I p can be used to make the potential outputs; more specifically only the dashed connection from gate I to gate I is permitted. If gate I is used to make a potential output, then the output of gate J may change because the triangular condition is not satisfied due to the lack of connection between gates I and J , and the outputs of the network may change, although From other gates and/or external variables Outputs of the network Fig. 2.1-4 General case of triangular condition and potential outputs. the outputs of gates J p and J remain the same. In general, if the out- put of gate I feeds to all immediate sucessors of gate J, then the new connection of gate I to gate J will not alter the outputs of the network, and the new outputs at gate J may be used to compensate for the error- components at other gates in error-compensation procedures. 12 The error-components of a gate usually consist of two types of error: the O-error and the 1-error. In Fig. 2.1-5(a), assume that the output of gate I for some input vector X should be 0. It will be called a 1-error, denoted with 1 (notice that 1 is underlined), if it changes to 1 due to the removal of some gates or connections in the network, Fig. 2.1-5(a* ). In Fig. 2.1-5(b), assume that the output of gate J for some input vector X should be 1. It will be called a 0-error, denoted with (notice that is underlined), if it changes to due to the removal of some gates or connections in the network, Fig. 2.1-5 (b')« In Fig. 2.1-5(a), at least one of the corresponding components in the in- -x- put functions of gate I must be 1 in order to cover the 0-component of the out- put function of gate I. In Fig. 2.1. 5 (a' ), the corresponding components in all {...!...) (... ...) > (... ...) (a) correct output (... ...) • ■ • _L ■ • * > (... o ...) (b) correct output (... ...) (... 1 ...) > ... ...) (a* ) 1-crror (l) (... 1 ...) (... ...) > (... ...) (b') 0-error (0) Fig. 2.1-5 1-crror and 0-error. - omponenl, in the output functions of a gate is said being Input functions have 1-components at the cor- 3 P° ; tion. An 1-component in the output function of a gate is said Lta inputs if all input functions have 0-components at the position. the input functions are and are considered as O-errors. In Fig. 2.1-5(b), the corresponding components of all the input functions of gate J must be in order to cover the 1-component in the output function of gate J. Tn Fig. 2.1-5 !b'), at least one of the corresponding components in the input functions of gate J changes to 1, and this (or these Is) is considered as l-error(s). The 1- error in Fig. 2. 1-5 (a' ) can be compensated for either by changing any of the cor- responding components in the input function to 1 or by adding an input function, ' -h has a 1-component at the corresponding position, to gate I. The O-error ig. 2.1-5(b') can be compensated for either by removing all input functions which have 1-error components in the corresponding position or by changing 1- error components to O-components. But, obviously, all compensations mentioned above should not generate any new O-error or 1-error (We will go through the ail of the metods of compensating for 0- or 1-errors later). Three methods are used in compensating for error -components in the CSPFE of a selected gate: (i). Removing redundant connections. (II). Substituting for input connections (which cover error- components in the CSPFE of a gate) by external variables or the output connections of some other gates. (ill). Adding connections to cover 1-error components. (i) and (II) aim at compensating for O-error components at gate output wheras (ill) aims at compensating for 1-error components at gate output • From now on, whenever we mention "compensate for error components at the gate" we mean that we compensate for error components at the output function of the gate under consideration. Whenever we mention e CSPF (E) of a gate", we mean" the CSPF(E) of the output function of a gate". 11+ Among these three methods, the last two require connecting functions to the selected gate. For substituting for input connections (method II ), a substituting subset of functions must satisfy the following conditions. (i). If a function is realized at a gate output, i.e., not at external variable, then the gate as well as the gates, the connections from which to that gate must be added in order to realize this function, can not be successors of the selected gate. This condition guarantees that the resultant network is free of feed-back loops. (il). These functions can be realized simultaneously,* i.e., they are compatible to one another. (ill). These functions can be connected to the gate under consider- ation, i.e., these functions have O-components corresponding to 1-components in CSPFE of the selected gate. This condition guarantees that the number of O-error components never increases. (IV). These functions must cover all those O-components in CSPFE of the gate under consideration which are originally covered only by the substituted input functions. This condition guarantees that the number of 1-error components never increases. (V). Each function in a substituting subset of function must have at least one 1-component which covers a O-component not covered by functions in this subset or in the subset of the remaining input functions. This condition guarantees that each of the substituting functions is useful. In other words, these functions are not potential outputs which can not be realized simultaneously. 15 The substitution of connections aims at reducing the number of O-error components in CSPFE of the selected gate. As a by-product, the substitution may also reduce 1-error components if the substituting functions cover some 1-error components. For adding connections to cover, 1-error components (method III), the above conditions (l) and (3) must be satisfied. Besides, every function to be added must have at least one 1-component which covers a 1-error component, corresponding to condition (5). This condition guarantees that the added function is useful in compensating for 1-error components. The basic methods of compensating for error-components and the basic properties of the functions for compensating for error-components have been discussed. The detailed explanation of the procedures implementing methods (i) and (II) will be given in section 2.3.2. The error -compensation procedures are explained step by step in the following : Step 1 : Select a gate according to PORDR *. If every gate has been selected, then stop. Otherwise go to Step 2. Step 2 : Assume the selected gate is removed, and then check whether the network outputs change or not. If the outputs do not change, then actually remove this gate and stop. Otherwise go to Step 3. Step 3 : Construct the potential output table (list all potential outputs). Go to Step h. Step h : Try to use potential outputs to compensate for the error components found in Step 2. • The gates are listed according to the number of ones in the CSPFE (or CSPF) of each gate. The gate with the fewest number of ones should be listed first in the array PORDR. 16 Decide whether the error components can be compensated or not. If all error components are compensated, then stop. We have succeeded to compensate for all error-components. If the errors have been propagated to the highest level gates and they still cannot be compensated, then go to step 1 to try another gate. Otherwise repeat this step. The realization of each step is complicated. The subroutines which realize these steps will be detailed in the following sections of this chapter, 2.2 General organization of the original programs and the program modified for fan- in/ fan-out restricted networks The network transduction procedures can simplify a given non- optimal network only, and cannot generate new networks for any given switching function. Any conventional design methods* can be used to generate a non-optimal network, which is named an initial network, for a given switching function. The inital network, in general, contains many redundant gates and connection, though it can be ob- tained in a reasonably short time. After an initial network has been obtained, the network transduction procedures can then be employed. The approaches which were used in programs NETTRA-E1 and NETTRA-E2 are explained below. .versal networks of NAND/NOR gates (pp. 15U-157 of [20]), networks designed branch-and-bound method [27], three-level networks based on the map method to be described elsewhere and networks designed by Tison method [3] are often used. method is sometimes too time-consuming for multiple -output functions or actions with more than 5 external variables. 17 1) For a given switching function (given in row vector form), generate an initial network by calling subroutine UNIVSA, which uses UNIVerSAl network method. 2) Apply the central subroutine PROCCE of error-compensation procedures to simplify the inital network as much as possible. Since the initial network derived by subroutine UNIVSA may not be fan -in/ fan -out restricted , and since the original subroutine PROCCE in (2) does not consider fan-in/fan-out constraints, the above approaches, of NETTRA-E1 and NETTRA-E2 cannot be used to treat fan -in/ fan -out restricted problems. The approaches which are used in NETTRA-E1-FIF0 and NETTRA-E2-FIF0 (modified NETTRA-E1 and NETTRA-E2) are explained in the following four steps. 1) For a given switching function, obtain an initial network by calling subroutine UNIVSA. 2) Apply the central subroutine PROCII of programs NETTRA-G2 to simplify the network obtained in step 1 under no fan -in/ fan -out restrictions. The network obtained in this step may be simplified but may be not fan-in/ fan-out restricted. 3) Call transformation subroutine JEFF [19] 9 to transform the simplified network of Step (2) into fan-in/ fan-out restricted form. The network after transformation may contain many redundant gates and/ or connections, but subroutine JEFF does not try to simplify it. k) Apply the modified subroutine PROCCE to simplify the network obtained in Step (3) while keeping the network still fan-in/ fan -out restricted. 18 Subroutine PROCCE (the acronym of PROCedure of Compensating for Errors) contributes the main efforts for error-compensation. Nine subroutines are called by PROCCE: FORC, CONECT, RPLCF, POT, RCEC, CALS1, MINI2, 0RDRQ2, and SUBNET. The first five subroutines were modified for fan -in/ fan -out restrictions. In order to facilitate the explanation of the modifications, the functions of each of these subroutines and the definitions of several important variables are explained below: 1) Subroutine MINI 2 has two functions: (a) Realize a "pruning" procedure, so it may be able to remove some obviously unnecessary gates and connections, (b) Calculate CSPF vectors for all the gates in the network [10], [15]. 2) Entry INITGS is an entry point of MINI2, it is always called to calculate the CSPFE vectors immediately before calling subroutine RCEC [13], [15]. 3) Subroutine POT constructs the potential output table. k) Subroutine CALS1 calculates the substituted set SI of the specified input functions (S) when a set of candidates S for compensating for errors is given [9], [13]. 5) Subroutine RPLCF selects a subset S3 of S2, which is needed to replace set SI. That is to say, it checks the necessary conditions for substituting functions to decide which of candidates S2 is actually required in substituting for the elements in SI [9], [13]. Subroutine RCEC calls CALS1 and RPLCF to rearrange the network nnection pattern such that all error- components is CSPFE can be pensated for [9l» [13] ■ 19 7) Subroutine CONECT connects the function in POT specified by the pointer PTR to the gate under consideration and it also makes necessary- connections for realizing this potential output function [13]. 8) Subroutine FORC tries to remove the first-order redundant* connections [13]. 9) Subroutine 0RDRQ2 makes the list of predecessors of a selected gate according to order Q2* [9l s [13]. 10) Subroutine SUBNET generates the detailed and updated information on the topology of the network, disconnects certain types of obviously unnecessary connections in the network and calculates the actual truth table for the entire network currently stored in array INC$MX [91. 11) Subroutine OUTPUT assigns mnemonic names to external variables and prints out the truth table of output gates and the network configuration [15 . 12) INC$MX is a two-dimentional array. INC$]V1X (l,j) is equal to 1, if there is a connection from gate I to gate J; otherwise it is equal to [15] 13) NEPMAX is the maximal number of permitted error-components in CSFFE. If the number of error— components exceeds this limit, error compensation is not attempted for the given network [13]. The general organization of NETTRA-E1 and NETTRA-E1-FIF0 (or NETTRA-E2 and NETTRA-E2-FIF0) are shown in Fig. 2.2-2 and Fig. 2.2-3, respectively. An arrow from block A to block B means that the subroutine represented by block A calls the subroutine represented by block B . These •./ill be explained in Section 2.3. 2( START CALL MINI2 TO ELIMINATE EASILY REMOVED GATES AND TO CALCULATE THE CSPF VECTOR FOR EACH GATE. RETURN > YES i pcO = ORDER(PCOUNT) RESTORE ORIG- INAL NETWORK CONNECTION PrTTBBN (I.E. , RESET INC$MX). REMOVE ALL CONNECTIONS TO AND FROM GATE PCO. i i CALCULATE 73DED CSPFE '^RC FOP ": ;ates, 12 1^ UPDATE ALL ARRAYS . CALL : SUBNET, PVALUE, AND UNNECE. 11+ COUNT THE NUMBER gJF ERROR- POSITigfNS, NEP. DETERMINE THE NUMBER OF l'S IN CSPF VECTOR FOR EACH GATE. LIST GATES IN ARRAY PORDEP ACCORDING TO INCREASING NUMBERS 0F l's IN THEIF RESPECTIVE CBPF VECTORS. PCOUNT » PCOUNT ♦ 1 18 INITIALIZE CSPFE VECTORS OF NEW NETWORK: CALL F0RMGO AND CALL INITGS. II I I INITIALIZE COUNTER: PO0UNT - 0. 19 FORM POTENTIAL OUTPUT TABLE: CALL POT. execute error- cOmpensattOn ROUTINE: CALL RCEC. C RETURN D 21 ALL ERRORS SUCCESSFULLY COMPENSATED . PRINT RESULT, Fig. .:-] Generalized flowchart of PROCCE. 1 •H 1 + + t o o o O Ph B Ph p H H 2 6 Ph H Ph Ph OJ P3 l il * * Eh Eh & (£h T3 g G CD ^ Ph Eh b o O Ph H Ph 1 H < ffi Eh £ i B 1 1 w V? t t t t ? S CO ?H bD o H H V | B CO H CO o c Q Ph O Ph O Ph P^ En O E o o K o Ph ft Cm O o ■H -P CO N •H CO ♦ * * * M M O H CO Pi < CO ► CO H pa POT I'an-in and fan-o u t restrictions Tn this section, the consideration of fan- in/ fan- out restrictions in the error-compensation procedures and the corresponding modifications of the transduction programs will be discussed. It was mentioned in Section 2.1 that the fan- in/ fan-out restricted error- compensation procedure tries to simplify the fan-in/ fan-out restricted network derived by subroutine JEFF. If a network originally does not satisfy the given fan -in/ fan -out restrictions then it is not guaranteed to satify fan -in/ fan -out restrictions after applying the modified error-compensation procedure. Hence, we will assume that the networks to be used in the discussions for modifications already satisfy fan-in/ fan-out restrictions. The definitions given below will facilitate later discussions. l) FI is the maximum fan-in for each gate in the network. ) is the maximum fan-out for each gate which is not an output gate. 3) FOX is the maximum fan -out for each external variable. h) FO ) is the maximum fan -out for each output gate. 5) LISUCC (i) denotes the number of immediate successors of gate I. 6) LIFRED (i) denotes the number of immediate predecessors of gate I. 7) =l, (2-2) G E (d) (j)=l, f (d) =l. 11) A gate or an external variable, I, is E-connectable (or effectively E-connectable ) to gate J if (l) f(l) is E-connectable (or effectively E-connectable, respectively) to J and (2) the network obtained after making this connection is loop - free. 12) A gate or an external variable, I is strongly effectively E-connectable to gate J if: (1) I is effectively E-connectable to J and (2) IS(l) c IS(j) is not satisfied (e.g., the triangular condition is not satisfied), where IS(l) and IS(j) are sets of the immediate successors of I and J, respectively. Throughout the rest of this paper, we will use terms "connectable " and "effectively connectable " instead of using terms "E-connectable" and "effectively E-connectable" for the sake of convenience. 13) A primary 0-error component is a 0-error component which is covered by only one input. lU) A secondary 0-error component is a 0-error component which is covered by more than one input. It is considered more difficult to be compensated than primary 0-error components. 25 2.3.1 Potential output table and subroutine POT In Section 2.1, the way of constructing potential output has been discussed. When the fan-in/fan-out constraints are imposed, more conditions should be considered in constructing the potential output table. Fig. 2.3.1-1 shows an example; assume that gates I , I p and I feed to all the immediate successors K. > K , . . .K_ of gate J. According to the triangular condition, gate J can be used as a potential-output gate. If there is no fan-in/ fan-out restrictions, the original output of gate J and the output of gate J after connecting gate I. and/or gate I p and/or gate I_ to J can be put in the 3 potential output table; i.e., there are totally 2 potential outputs which can be constructed at gate J. If there exists fan-out restriction and the number of immediate successors of gate J is already equal to the given limits for fan-out; i.e., if LISUCC (j)= FO then none of the 8 possible outputs can be included in the table. I J : ^-» > To other gates Fig. 2.3.1-1 Example for consideration of fan-in/ fan-out restrictions in constructing potential output table. 26 Similarly, if an external variable u already feeds FOX gates or if an output gate u already feeds F00 gates*, then no potential output realized at u can be put in the potential output table. If the fan-out of gate J is less than the given limit, then the original output of gate J can be put in the table. Any other potential outputs which can be realized at gate J can be included in the table if none of the following conditions is satisfied. 1) The connection of I , I , or I to J will create fan-out problems for I , I , or I . 2) The connection of I and/ or I and/or I to J will violate the maximum fan-in restriction for gate J. (1) can be equivalently expressed as the following: LISUCC (I ) = FO or LI3UCC (i ) = FO * or LISUCC (I )= FO and (2) can be expres sed as LIPRED (J) t t > FI ; t > 1 where LIPRED (j) is the number of current inputs of gate J, and t is the the number of gates and the number of external variables to be connected to gate J. Before discussing the modifications in the subroutine POT, the definitions of some variables and arrays are given below. appen only in the multiple -output case.. The output gate function can be a predecessor of other functions. T !> 2* 0r '" an externa l variable, then replace FO by FOX. r i» t ^n output gate, then replace FO by F00. 27 1) LEVM is the number of levels of the network. 2) PPOTAB (Gl) is a pointer which indicates the first entry in the block of potential outputs realized at gate GI. 3) LPOTAB (Gl) is a pointer which indicates the last entry in the block of potential outputs realized at gate GI. k) POTAB(PTR,K) is a two-dimensional array of 200 x k-2 entries. The first argument of POTAB is the entry number, and each entry contains the following information which is different depending on K: (a) P0TAB(PTR, 1 ^ 32) is the actual function vector of this PTR-th potential output in truth table form (e.g., the output column vector in the truth table). (b) POTAB (PTR, $GT) is the gate name, GI, at which the potential output is realized ($GT=33). (c) P0TAB(PTR, $LTH) is the number of connections to be added to gate GI in order to realize this PTR-th potential output ($LTH=3 1 +). (d) POTAB (PTR, $LTH+1 - $LTH+6) is the list of gates which must be connected to gate GI in order to realize the potential output. The maximal number of gates is restricted to 6. (e) POTAB (PRT, $PW or $N0E) are two words in which the preference weight of this potential output and the number of error components are stored, respectively for the err or -components procedure. As currently programmed, $PW=*+1 and $N0E=i+2. The flowcharts of the subroutine POT before and after the modifications are given in Fig. 2.3.1-2 and Fig. 2.3.1-3, respectively. 28 The following is the detailed explanation of the flowchart in Fig. 2.3.1-3. Step 1 Initialization ; Set PPOTAB(Gl)=o for GI=1,2,..., n+r, where N is the number of external variables and R is the number of gates. Set P0INTR=1, where POINTR is a pointer indicating the next entry in the potential output table. Step 2 Select Gates: According to the level number assigned to each gate and external variable (i.e., higher level gates precede lower level gates), select a gate or an external variable GI, and go to Step 3. If all gates are considered, then stop. Step 3 Check the Fan-out Problem for GI : Step 3a* Check for fan -in/ fan -out considerations Check whether the fan-out of GI is equal to the limit. If not, go to Step 3; otherwise go to Step 2. Step 3 Set First Entry for GI : Set PPOTAB(Gl)= POINTR, and copy the present output function of GI into POTAB as the POINTR -th entry. Set POTAB (POINTR, $GT)=GI and POTAB ( POINTR, $LTH)=0, POINTR= POINTRt-1. Step 3b (For fan-in/ fan-out considerations): If the fan-in of GI is already equal to FI, then there is no way of forming any other potential output at GI, go to Step h. marked with suffix a or b are for fan- in/ fan- out considerations only. are not shown in Fig. 2.3.1-2. 29 Step k Find the simple entries realized at GI: Step k-1 Select a gate or an external variable, GJ , whose level number is not lower than GI's. If all GJ's are considered, go to Step 5. Step U-la (For fan -in/ fan -out considerations) check whether or not the fan-out of GJ equals the limit. If not, go to Step k-2; otherwise go to Step k-1. Step k-2 Check whether or not GJ is connected to all immediate sucessors of GI. If not, go to Step k-1. Step k-3 Check whether or not connecting GJ to GI produces a function which is different from GI or from the functions produced by connecting the previous GJ's to GI. If not, go to Step k-1. Step k-k Make the potential output by connecting GJ to GI as the FOIOTR-th entry of the POTAB and set POTAB (POIMTR, $GT)=GI POTAB(P0INTR, $LTH)=1 POTAB (POINTR, $LTH+l)=GJ POINTR =POINTRfl Go to Step k-1. Step 5 Make composite potential Outputs from GI. Step $-1 . If two or more functions are simple entries for GI , go to Step 5 -la; otherwise go to Step 6. Step 5 -la If the difference between the current fan-in of GI and the given limit FT is less than 2, then go to Step 6*, otherwise go to Step 5-2. (in this case, no composite potential output can be produced). Step 5-2 Select one entry in block GI of POTAB except GI itself. If all entries are considered, go to Step 6; otherwise go to Step 5-3. Step 1 Step 2 Step 3 Step U-l - -NO © ENTRY I SET PPOTAB(GI) = ), FOR GI = 1, 2, ..., N+R. POINTR = 1 I LEV = LEVM, LEVM IS THE NUMBER OF LEVELS IN THE NETWORK. SELECT ONE GATE GI IN LEVEL LEV WHICH IS STILL IN THE NETWORK COPY FUNCTIONS OF GI TO POTAB AS THE POINTR- TH ENTRY. SET PPOTAB(GI) = POINTR POTAB ( POINT R,$GI = GI POTAB (POINTR,$LTH = POINTR = POINTR + 1 SELECT A FUNCTION GJ WHOSE LEVEL IS NOT LOWER THAN LEV. I EXHAUSTED GJ CONNECTED TO ALL IMMEDIATE SUCCESSORS OF GI? fES 6 31 •• ; - Step DOES CONNECTING GJ TO GT MAKE A FUNCTION WHICH IS DIFFERENT FROM ALL ENTRIES IN BLOCK GT OF POTAB YES make this function as a new entry of potab set potab (po int r,$gt) = gi potab(pointr,|lth) = 1 potab( pointr, $lth+1 ) =gj pointr = pointr + 1 d> • p - IS THE NUMBER OF ENTRIES IN BLOCK GI EXCEPT GI ITSELF GREATER THAN ONE? YES SELECT AN ENTRY IN BLOCK GI WHICH IS NOT A COMPOSITE ENTRY. CHECK IF ALL ENTRIES ARE CONSIDERED. NO 1 f'tep 6 SET LPOTAB(GI)=POINTR-1 32 © Step5-3 Step 5-k MAKE COMPOSITE ENTRIES OF PTRl AND EACH OF THE PRECEDING ENTRIES OF BLOCK GI (EXCEPT GI ITSELF) MAKE COMPOSITE ENTRIES OF PTRl AND EACH OF THE COMPOSITE ENTRIES MADE FROM THE PRECEDING ENTRIES OF BLOCK GI. .g. 2.3.1-2 Flowchart of subroutine POT before the modifications for fan-in/ fan-out restrictions. (i.e., POT used in NETTRA-E1 and E2) 33 ■tep 1 Step . Step ^a '- -; ( ENTRY J )T SET PPOTAB(GI) = 0, FOR GI =- 1,2,...,N+H. POINTR --- 1 I LEV = LEVM, LEVM IS THE NUMBER OF LEVELS TN THE NETWORK ► <*- SELECT ONE GATE GI IN LEVEL LEV WHICH IS STILL IN THE NETWORK -- j ,, d> COPY FUNCTIONS OF GI TO POTAB AS THE PTR-TH ENTRY. SET PPOTAB(GI) = POINTR POTAB ( POINT R,$GT) = GI POTAB ( POINTR, $LTH) = POINTR = POINTR 4- 1 ►-* £ THE NUMBER OF GATES OR CONNECTIONS TO BE CONNECTED TO GI. Fig. 2.3.1-3 Flowchart of subroutine POT after the modifications for fan-in/ fan-out restrictions, (i.e., POT used in NETTRA-E1-FIFO and NETTRA-E2-FLF0) 36 Step 5-3 Make composite entries of this entry and each of the entries preceding it. Step 5-k Make composite entries of this entry and each of the composite entries of the entries preceding it if the difference between the fan -in limit FI and the current fan -in of GI is greater than or equal to the number of gates and/or external variables to be connected to GI. If all composite entries are considered, go to Step 5-2. Step 6 Set Last -Entry-Pointer Set LPOTAB(GI) = POINTR-1. Go to Step 2. 2.3.2 Replacement of connections by error-compensation and subroutine RCEC, CALS1 and RPLCF Three methods for compensating for O-error- components or 1-error- components were mentioned in Section 2.1. The detailed procedures of these methods are given below. (l) Remove redundant connections If an input connection of the selected gate has no essential 1-components to cover O-components in CSPFE of the selected gate, then this input connection is redundant. This type of redundant connections are called the first order redundant connections which will be removed in the first place without adding any connections. It should be noticed that the number of O-error components (or the degree of O-error eomponents) in the CSPFE of the selected gate may be reduced by removing first order redundant connections. 2) Substitution for external variable inputs of a gate which cover O-error-components of the selected gate. 37 If an external variable input has 1-component which cover some O-error - components in the CSPFE of the selected gate, these O-error-components can never be compensated for unless this external variable input is replaced by- some connectable functions which have O-components at the corresponding component positions. The connectable external variables without error components or the connectable functions of gates with or without error components, can be used as the candidates for replacing the external variable input. (3) S\ibstitution for input connections which cover primary O-error- components of a gate. If a O-error-component in the CSPFE of the selected gate is covered by only one input function (which is called a primary O-error-component), it is considered easier to be compensated for. In this case, the connectable functions which have O-components can be used as candidates. Once some primary errors are eliminated by substitutions, the candidates for later substitutions should be limited to those functions which have O-components corresponding to the compensated primary error components. (h) Substitution for input connections which cover O-error components of a gate, by functions without error-components. This subprocedure substitutes connectable functions which have no 1-components corresponding to o-error-components in the CSPFE of the selected gate GI for functions which have at least one 1-components corresponding to a O-error-component in the CSPFE of the gate GI. As a result of the substitution the degrees of some O-error may be reduced and this may make the total number of error-components in the input functions smaller. If the degree of an error is reduced to zero, this error of the selected gate has been compensated. (5) Adding connections to compensate for 1-error-components. A 1-error-component in the CSPFE of the selected gate GI is easy to "be compensated for if there is a correctable function whose corre- sponding component is a. 1. Some of the 1-error-components may have been already compensated during the compensation for O-error-components by sub- stitutions. Since earlier subprocedures aimed at compensating for O-error- components, however, there may still be needs for compensating for 1-error- components especially when there is no O-error-components in the CSPFE of gate GI. In this subprocedure, the candidates are those functions which have a O-component corresponding to each 1-component (including the corrected O-error-components if any) in the CSPFE of gate GI. (6) Adding redundant input connections from external variables. This subprocedure does not belong to any of the three types of operations for error-compensation since it does not aim at compensating for error-components in the CSPFE of the selected gate GI, but rather, it does aim at loosening the requirements of the predecessors of gate GI to make error-compensation at later steps easier. Procedures (2), (3) and (k) require formation of a substituting set for compensating for errors, and procedure (5) and (6) require addition of external variables or internal functions (i.e., gate outputs) for compensating for errors. When fa.n-in/fan-out restrictions are imposed on the network, the maximum fan-in restriction on the selected gate or external variables should be considered. For example, in Fig. 2.3.2-1, assume that gate I has an error-component in its CSPFE and input function K cover this err or -component. Also assume that this error -component can be pensated if input function K is substituted by a set of functions. The substitution could be done if the sum of the number of functions in the substituting set and LIPRED(l)-l is less than or equal to the fan-in limit FI and if the fan-out of every function in the substituting set is less than the given limit. Similarly, when a function or a set of functions are connected to the selected gate to compensate for the error-components the number of functions to be connected must be checked in order to con- sider the fan-in restriction for the selected gate; the fan -out of each function to be connected must also be checked. £D(l)'s | predecessors^- Substituting Set { LIPRED(I)-1 's { predecessors .3.2-1 Example for considering the fan- in restriction in substituting input function K of gate I. 1+0 It should be noticed that if the functions to be connected are chosen' from the potential output table, these functions will not violate the fan-out restrictions, since the fan-out condition of each function has already been checked in constructing the potential output table. Since the detailed steps of each of the above six procedures are complicated, it is not easy to see where or how the modifications should be done. The modifications for the fan -in/ fan -out restrictions will be discussed when the detailed steps of subroutine RCEC are to be explained. Subroutine RCEC, which stands for Replacement of Connections for Error- Compensation, and five supporting subroutines CALS1, RPLCF, FORC, 0RDRQ£, and CONECT, are the central part of subroutine PROCCE. Subroutine RCEC needs, as a parameter, a NOR network which does not realize the desired output functions along with the initial CSPFE for each gate. When it is entered, it selects one gate at a time whose CSPFE has been already calculated and tries to compensate for err or -components in the CSPFE of this selected gate. As a result of the error -compensation for this particular gate, if some error-components are compensated for or the output functions of some gates are changed, this subroutine will return to PROCCE, the calling sub- routine. PROCCE will then recalculate the output functions of the net- work to check whether or not this new network realizes the desired functions. If it does, the original network has already been transduced to a desired new network; otherwise PROCCE will recalculate the potential output table • call subroutines RCEC arain to apply the error -compensation procedure to thi.r b] ' modified network. On the other hand, if no error -components in the CSPFE of the selected gate can be compensated for, the CSPFE of the in selected gate will be propagated to its inputs. If all gates have been considered in this manner, it means no error -components can be compensated in this application of RCEC. In this case, subroutine returns to FROCCE i.e., the error-compentation has not been successful). Subroutines CALS1 and RPLCF substitute a subset of candidates for a subset of input functions of the selected gate. Subroutine CALS1 calculates the to-be-replaced subset of certain input functions when a set of candidates are given. Let the functions to be replaced be denoted with S, and the set of candidates to be added with S2. CALS1 will calculate a subset SI of S which can be replaced by S2. For example, let set S contain all external variable inputs which cover some -error -components, and let set S2 contain all connectable functions except the connectable external variables which have 1-eomponents corresponding to some o- error -components in the CSPFE of the selected gate 61. The subroutine CALS1 checks whether or not every 1-component in each function of S can be covered by S2. If all essential ones in a function of S can be covered by set S2, this function is replaceable, and therefore should be in set SI. Along with set SI, the components must be covered by one of the substituting functions stored in set Tl, and these components will be referred to by subroutine RPLCF. Although the modifications for fan -in/ fan -out restrictions have nothing to do with subroutine CALS1, the procedure and the flowchart of CALS1 given below will facilitate the discussion of RPLCF and RCEC. The following is the procedure of subroutine CALS1. k2 Step 1 Selection of functions Take a function GP from set S. If all functions in S have been considered, return to the calling procedure (subroutine RCEC in NETTRA-E1, -E2, : - El-FIFO or -E2-FIF0). Step 2. Check replaceability For each O-component in the CSPFE of GI, the gate under consideration, which is covered only by input function GP, check whether or not set S2 covers it. If not, GP is not replaceable and go to Step 1. Step 3« List essential ones Add the positions of all essential 1-components in the function of GP into set Tl, which is the list of the positions to be covered by the substituting functions » Step k. Update Add GP into set SI. Remove GP from the list of the current input functions of GI. Remove GP from set S. Go to Step 1. The flowchart of subroutine CALS1 is shown in Fig. 2.3.2-2. Subroutine RPLCF is called immediately after CALS1 has been executed. RPLCF selects a subset S3 of S2 which is needed to replace functions in set SI. Therefore, set S3 must satisfy the conditions for substitution described in Section 2.1. Since the selection of S3 is essentially a covering problem and the covering problem is difficult to solve by found algorithms, a heuristic procedure is used. The candidates to replace Gl (i.e.,, set S2) are stored according based primarily on the number of anticipated error-components and secondarily the number of - omponents covering O-components or 1-error-components. The procedure examines each candidate according to this ordering to check if it covers components in Tl which are not covered by any selected candidates. ^3 EXHAUSTED 1 RETURN Fig. 2.3.2-1 Flowchart of subroutine CALS1. kk If it does, the candidate will be added into set S3 which is the set of functions substituting for inputs in set SI. The candidates in set S2 may not be compatible with one another, so each time when a gate is added into set S3, all other candidates which are not compatible with it are pro- hibited, from being selected. Because of the prohibition, the remaining functions in set S2 and the functions in set S3 may no longer cover set Tl. In this case, the functions prohibited by the latest selection are permanently prohibited, and the set S2 is recalculated. The procedure then calls subroutine CALS1 (from RPLCF) and reenter RPLCF to repeat this procedure of substitution. As a final result, a subset of input functions may be replaced by a subset of candidates in set S2. The following is the procedure of subroutine RPLCF after modifications for fan-in/ fan-out restrictions. The parameter JFLAG is used in the procedure to denote temporarily the number of inputs of the selected gate GI. JFLAG is set to the value LIPRED(Gl) in the very beginning of subroutine RCEC after gate GI is selected. Then its value will be increased whenever functions are put into set S3, and will be decreased whenever the functions in set SI are disconnected from gate GI. Step 1 Initialization Set S3=0 (empty set) Step 2 Selection of a candidate Select a function, PTR, from set S2 which is the PTR-th entry of POT and is realized at gate GT. ^5 Step 3 Check usefulness Check whether or not this function covers any components in set Tl which are not covered by any functions already in set S3. If not, go to Step 2. Step k Prohibition Prohibit functions which are realized either at gate GT or at some other gate GX, requiring the addition of the connection from GT to GX. Step 3 Update Temporarily add this function into set S3° Remove components covered by this function from set Tl. If T1=0, go to Step 8. Step 6 Check replaceability Check whether or not remaining functions in set S2 still cover all remaining components in set Tl. If yes, set S3=S3 U {PRT} and go to Step 2. Step 7 Recalculate set SI (7a) Restore set S2 but delete from S2 the function just prohibited in Step k. (7b) Call CALS1 to calculate SI and associated Tl. Go to Step 1. Step 8 Substitution (8a) If JFLAG + (the number of elements in set S3) -(the number of elements in set Si) is greater than FI, then SI cannot be substituted by S3, return to the calling subroutine; other- wise go to Step 8b. (8b) Connect functions in S3 to gate GI. Disconnect the input functions in set SI from gate GI. Update JFLAG. Return to the calling procedure RCEC The flowcharts of subroutine RPLCF before and after the modifications are shown in Fig. 2-3.2-3 and Fig. 2.3.2-U, respectively. ke NO SELECT 0NE FUNCTION, PTR' (AN ENTRY NUMBER IN 3 QT), FROM Si EXHAUSTED I CHECK WHETHER 0R \ N0T PTR COVERS AT \ LEAST 0NE COMPONENT \ IN SET Tl WHICH / IS N0T COVERED BY / FUNCTIONS IN S3 / I YES PROHIBIT FUNCTIONS IN S2 WHICH USE THE GATE REALIZING FUNCTION PTR ION CHECK WHETHER SET S2 STILL COVERS ALL ESSENTIAL COMPONENTS IN SET Tl I NO RESTORE SET S2 BUT REMOVE THE FUNCTIONS JUST PROHIBITED FROM SET S2. CALL CALS1 REPLACE FUNCTIONS IN SET SI BY FUNCTIONS IN SET S3 C RETURN J . . - lowchart of sub routine fore modifications -out restriction. NO hi 1! SELECT 0NE FUNCTION, PTH 1 (AN ENTRY NUMBER IN PflT), FR0M S2 CHECK WHETHER 0R NOT FTR COVERS AT LEAST 0NE C0MP0NENT IN SET Tl WHICH IS NOT COVERED BY FUNCTIONS IN S3 EXHAUSTED REPLACE FUNCTIONS IN SET SI BY FUNCTIONS IN SET S3 c RECOVER JTIAj; RETURN J L YES PROHIBIT FUNCTIONS IN S2 WHICH USE THE GATE REALIZING FUNCTION PTR CHECK WHETHER SET S2 STILL COVERS ALL ESSENTIAL O0MP0NENTS IN SET Tl NO RESTORE SET S2 , BUT REMQTVE THE FUNCTIONS JUST PROHIBITED FR0M SET S2. CALL CALS1 Fig. 2.3.2-4 Flowchart of subroutine RPLCF after modifications for fan-in/ fan-out restrictions. 1+8 A brief description of the procedure realized by subroutine RCEC is presented as follows, along with the modification for the fan -in/ fan -out restrictions. Step 1 Selection of gate Select a gate GI according to the ascending order of the level number assigned to each gate, i.e., a gate in the lowest level is selected first. Set JFIAG to the number of inputs of gate GI before error-compensation. As the procedure goes on, JFIAG will be updated wheneven the fan-in restriction of gate GI is considered. If all gates have been considered, return to the calling subroutine, by the FORTRAN statement RETURN 1. Step 2 Removal of Redundant connections For each immediate predecessor GJ of GI, call subroutine FORC(GJ) to check whether or not the connections from GJ to GI is redundant. If so, remove this connection and update JFIAG. If no error-component is in the CSPFE of GI, go to Step 9. Step 3 Selection of connectable function from POT Select gates or external variables whose number of successors is less than specified maximum fan-out. Select from the potential outputs of these gates or external variables, the strongly effectively E-connectable functions for GI. If there is no such connectable function for GI, go to Step 9« Step k Classification of connectable functions Classify connectable functions for GI into four categories: (l) external variables without error-components (set DIO), (2) gates without anticipated error -components (set BIO), (3) gates with anticipated error- ponents (set BI ) , and (k) external variables with error -components k9 (set Dl). Sort BI according to the number of -error -components the function covers. Step 5 Substituting for external variables with errors Let S2=DI0 U BIO U BI, S = external variable inputs of GI which cover -error -components (these inputs are found and sorted by calling subroutine 0RDRQ2). Call subroutines CALS1 and RPLCF to substitute a subset S3 of S2 for a subset SI of S, if possible. Step 6 Substituting for functions covering primary error-components For each input of GI covering primary error-components (these inputs are found and sorted by calling 0RDRQ2 in Step 5), check whether or not it can be replaced by functions in DIO, BIO and BI with some primary error -component corrected. Call CALS1 and RPLCF to complete this substitution. Step 7 Substituting for functions by functions without error-components Let S be the set of remaining inputs of GI with error -components, and S2 be the set of the remaining functions (exclude already selected and/ or prohibited ones) in sets DIO And BIO. Call CALS1 and RPLCF to replace a subset SI of S by functions in a subset S3 of S2, if possible. Step 8 Compensating for 1-error -components in the CSPFE of GI If some of the remaining functions in DIO, BIO and BI have 1-components corresponding to some 1-error-components in the CSPFE of GI, connect these functions to compensate for 1-error-components, if the connection will not violate the fan-in restriction problem for GI. 50 Step 9 Adding redundant external variables Connect connectable redundant variables to GI without reducing the number of primary error-components in the CSPFE of GI if the connection will not violate the fan-in restriction for gate GI. Step 10 Return to calling subroutine If an error-component in the CSPFE of GI has been corrected or a sub- s'. itution is performed during steps 2, 5? 6, 7, or 8, return to the calling subroutine (PROCCE in NETTRA-E1, -E2, and -E3) to check the outputs of the network, by the FORTRAN statement RETURN 2. Step 11 Propagation of CSPFE Update the intermediate CSPFE for each immediate predecessors of gate GI. Go to Step 1. The detail of propagation of CSPFE is described in [13]. The flowcharts of subroutine RCEC after modifications for the fan-in/ fan-out restrictions is shown in Fig. 2.3.2-5. 2.3.3. Subroutines CONECT and FORC Subroutine CONECT (PRT), which is called by RCEC, connects the function in POTAB specified by pointer PTR to gate GI and makes all other necessary connections. JFIAG will be increased by one whenever a connection is made. Subroutine FORC(GJ) is called by RCEC to remove first order redundant connections, and to check connection from gate GJ to gate GI. The value of I will be decreased by one whenever a connection is removed from the networ. . ;hese two subroutines are simple, the flowcharts will not be wn. 51 Step 1 r Step 2 r ^_ ENTRY 13 SELECT A GATE GI WH0SE CSPFE HAS ALREADY BEEN CALCULATED EXHAUSTED RETURN 1 "\ UNSUCCESSFUL } C0MPENSATI0N)/ JFLAG = LIPRED(GI) I LIST ALL 1, 1, 5 AND 0. C0MP0NENTS IN THE CSPFE 0F GI . LET CI, C1E, CO AND COE BE THE SUBSETS 0F THESE C0MP0NENTS RESPECTIVELY. ~l F0R EACH PREDECESS0R GJ 0F GI CALL F0RC(GJ)* T0 REM0VE REDUNDANT C0NNECTI0NS UPDATE COE L J In this flowchart, those blocks marked with asterisks are modified for the fan-in/ fan-out r sst r: jtion. 52 r SELECT GATES 0R EXTERNAL VARIABLES WH0SE NUMBER 0F SUCCESS0RS IS LESS THAN THE GIVEN LIMIT. SELECT FR0M THE P0TENT IAL 0UTFUTS 0F THESE GATES 0R EXTERNAL VARIABLES, THE STR0NGLY- EFFECTIVELY E-C0NNECTABLE FUNCTI0NS F0R GI. "I Step 3 ARRANGE ECF ACCORDING T0 THE NUMBER 0F 0- AND 1-ERR0R C0M- P0NENTS C0VERED BY EACH FUNCTT0N Step k " CLASSIFY ECF INT0 k SUBSETS 1. DIO: EXTERNAL VARIABLES WHICH C0VER N0 O-O0MP0NENTS 2. DI: EXTERNAL VARIABLES WHICH C0VER AT LEAST 0NE O-C0MP0NENT 3. BIO: GATES WHICH CQfVER N0 0-COMPONENT k. BI: GATES WHICH C0VER AT LEAST 0NE O-C0MP0NENT I_ r Step 5 . :•: ARRANGE BI ACCORDING T0 THE NUMBER 0F O-C0MP0NENTS COVERED SET S2=BI0 U DIO U BI IN THIS 0RDER LET SET S BE THE EXTERNAL VARIABLES CONNECTED T0 GI WHICH C0VER AT LEAST 0NE O-C0MPg)NENT IN THE CSPFE 0F GI J ~1 S=(J) CALL CALS1 T0 CALCULATE A SUBSET SI 0F S WHICH CAN BE REPLACED BY S2 CALL RPLCF T0 SELECT A SUBSET S3 0F S2 WHICH IS NECESSARY F0R REPLACING SI J 5h r ~i CALL 0RDRQ2 T0 CLASSIFY INPUT FUNCTI0NS 0F GI FE0M GATES INT0 TW0 SUBSETS 0NE 0F WHICH CONTAINS FUNCTI0NS COVERING AT LEAST 0NE PRIMARY O.-C0M- P0NENT, THE 0THER C0NTAINS 0THER INPUT FUNCTI0NS COVERING S0ME O.-C0MP0NENTS Step 6 LET S CONTAIN \ THE FUNCTIONS \ IN THE FIRST V SUBSET CALCU- / LATED AB0VE / SELECT 0NE FUNCTI0N, GP FRJ5M SET S LIST ALL PRIMARY 1-C0MP0NENTS IN GP. LET THIS BE SET ES1E. SELECT 0NE C0MP0NENT ES1E(I) FR0M ES1E S=<}> *© E XHAUSTED /T^N IT EXHAUSTED 18 55 © SELECT AS A SUBSET SU 0F S2 THE FUNCTI0NS WH0SE VALUES AT ES1E(I) ARE 0. WHENEVER A FUNCTION IS SELECTED, THE FUNCTIONS IN S2 WHICH USE THE SAME GATE AS THE SELECTED 0NE ARE PR0HIBITED FR0M BEING SELECTED CHECK WHETHER 0R> N0T FUNCTI0NS IN Sk C0VER ALL ESSENTIAL l'S IN GP k N0 YES PUT GP INT0 SI, ADD ESSENTIAL l'S C0VERED BY GP INT0 SET Tl SKT RP=RU ADD INPUT FUNCTIONS (FROM GATES) 07 GI WHICH C0VER S0ME 0-COMPONENTS INT0 SET S REST0RE S2 RESET SU CALL CALS1 T0 FIND ADDITIONAL FUNCTI0NS F#R SI (SUBSET 0F S) WHICH CAN BE REPLACED BY FUNCTIONS OF S2 56 r Step T Step 8 L r CALL RPLCF T0 FIND A SUBSET S3 OF S2 WHICH CAN REPLACE FUNCTIONS IN SI LET S2 CONTAIN THE FUNCTIONS IN BIO AND DIO WHICH ARE NEITHER SELECTED N0R PROH I BIT ED CALL CALS1 T0 CALCULATE A SUBSET SI (^F S WHICH CAN BE REPLACED BY SET S2 CALL RPLCF T0 CALCULATE A SUBSET S3 OF S2 WHICH IS NEEDED FOR REPLACING SI. C0NNECT THESE FUNCTI0NS T0 GI ~l ~l LET S2 C0NTAIN FUNCTI0NS IN BIO, DIO AND BI WHICH ARE NEITHER CONNECTED T0 GI NOR PR0HIBITED FROM CONNECTING TO) GI 19 LIST UNCOVERED 1-CQ(MP0NENTS SELECT 0NE FUNCTION FR0M SET S2 EXHAUSTED /^\ CHECK WHETHER^ 0R N0T THIS FUNCTION COVERS S0ME 1-C0MP0NENTS YES 2ALL C0NECT T0 CONNECT THIS FUNCTION Tj# GATE GI ' IF THE C0NNECTI0N W0N'T VT0LATE THE FAN- IN RESTRICTION F$R GT PROHIBIT THE FUNCTIONS IN S2 WHICH USE THE SAME GATE AS THE 0NE JUST C0NNECTED T0 GI L J 58 r ~i / SELECT 0NE /EXTERNAL VARI- ( ABLE FR0M \ potential \ Output table, EXHAUSTED KS) F0R ALL 1-C0MP0NENTS IN THE CSPF 0F GI, CHECK WHETHER 0R N0T ALL C0RRESP0NDING C0MP0NENTS 0F THIS EXTERNAL VARIABLE ARE ,N0 Step 9 YES F0R PRIMARY O-C0MP0NENTS IN THE CSPF 0F GI , CHECK WHETHER \ 0R N0T ALL C0RRESP0NDLNG C0MP0NENTS 0F THIS EXTERNAL VARIABLE ARE YES 'CHECK WHETHER 0R N0T THIS EX- TERNAL VARIABLE IS EFFECTIVELY CQfNNECTABLE, I.E. WHETHER 0R N0T IT C0VERS AT LEAST 0NE 0- 0R 1-C0MP0NENT NO YES L_ CONNECT THIS EXTERNAL VARIABLE T0 GATE GI IF JFLAG + 1 < FI _J 59 r Step 10 NO NO IS THERE ANY CHANGE r 0F NETW0RK CONNECTIONS DURING THE AB0VE CALCULATION ? YES CALL SUBNET AND UNNECE T0 UPDATE THE INF0RMA- TI0N ABOUT THE NETWORK L r i IS THERE ANY ERROR C0MPONENT IN THE CSPF 0F GI WHICH ARE COM- PENSATED DURING THE AB0VE CALCULATION ? YES < RETURN 2 J ~l SELECT 0NE PREDECESSOR OF GI EXHAUSTED /^N © Step 11 F0R EACH 1-C0MP0NENT IN THE CSPFE 0F GI ASSIGN T0 THE CORRESPONDING C0MP0NENT IN THE CSPFE 0F GP IF IT HAS BEEN ASSIGNED * 0R 6o FOR EACH 1-COMPONENT IN THE CSPFE OF GI ASSIGN TO THE CORRESPONDING COMPONENT IN THE CSPFE OF GP IF IT HAS BEEN ASSIGNED * FOR EACH 0-COMPONENT IN THE CSPFE OF GI ASSIGN 1 TO THE CORRESPONDING COMPONENT IN THE CSPFE OF GP IF THE CORRESPONDING COMPONENT OF THE FUNCTION OF GP IS 1 AND IT HAS BEEN ASSIGNED *; ASSIGN TO THE CORRES- PONDING COMPONENT IN THE CSPFE OF GP IF THE CORRESPONDING COMPONENT IN THE CSPFE OF GP IS AND IT HAS BEEN ASSIGNED * OR © FOR EACH PREDECESSOR GATE GP OF GI CALCULATE THE NUMBER OF 1-COMPONENTS (NOONEE) AND THE NUMBER OF PRIMARY 1-COMPONENTS (N01EES) . ASSIGN AS THE PREFERENCE WEIGHT OF GP THE VALUE 10 - 10 X N01EES - 10 2 X NOONEE + # SUCCESSORS OF GP SELECT ONE -COMPONENT IN THE CSPFE OF GI EXHAUSTED -© CHECK IF THIS COMPONENT \ IS COVERED BY AN EXTERNAL \ VARIABLE OR BY A GATE \ WHOSE CORRESPONDING j COMPONENT HAS ALREADY / BEEN ASS IGNED / YES NO 'CHECK IF THIS COMPONENT IS COVERED ONLY BY OUTPUT GATES WHOSE CORRESPONDING CSPFE COMPONENTS ARE ASSIGNED 1 YEE NO SELECT IMMEDIATE PREDECESSORS OF GI WHOSE CORRESPONDING COMPONENTS ARE AND CORRE- SPONDING CSPFE COMPONENTS ARE *; ASSIGN THESE CSPFE COMPONENTS 15 SELECT AN IMMEDIATE PREDECESSOR OF GI WHICH COVERS THIS COMPONENT AND HAS HIGHEST PREFERENCE WEIGHT 62 23 ASSIGN THE CORRESPONDING CSPFE COMPONENT OF THAT GATE TO BE 1 9 L J Fig. 2.3.2-5 Flowchart of Subroutine RCEC (Dashed blocks are the steps 1, 2, ..., 11 corresponding to those of the error compensa- tion procedure). 63 CHAPTER 3 EXPERIMENTAL RESULTS Error-compensation transduction programs NETTRA-E1-FIF0 and NETTRA-E2- FIFO were combined into one large program. Subroutine MAIN was written to control the calling of either NETTRA-E1-FIF0 or NETTRA-E2-FIF0. The IBM 360/ 75-J at the University of Illinois was used to run experiments on the fan-in/ fan-out restricted versions of error-compensation programs, NETTRA-E1-FIF0 and NETTRA-E2-FIF0. All subroutines were compiled using the FORTRAN H compiler (0PT=2). NETTRA-E1-FIF0 and NETTRA-E2-FIF0 require about 282k bytes of core storage, with about 1^7k bytes used by actual program instructions and about 135k bytes used for stored data. 3.1 Outline of subroutine MAIN in NETTRA-E1-FIF0 and NETTRA-E2-FIF0 Generalized flowcharts of programs NETTRA -El and NETTRA-E1-FIF0 were shown in Fig. 2.2-2 and Fig. 2.2-3, respectively. Those diagrams showed the relationships among subroutines but they do not show the actual flow of the programs and the difference between NETTRA -El -FIFO and NETTRA-E2-FIF0 ( or NETTRA-El and NETTRA-E2). Fig. 3.1-1 provides the order and the number of times each subroutine is called by subroutine MAIN in NETTRA-El- FIFO and NETTRA-E2-FIF0. The functions of Subroutine UNIVSA, JEFF and PROCCE were mentioned in Section 2.1. In Fig. 3.1-1, the loops marked with a single asterisk (*) will be executed repeatedly until there is no further improvement in the cost of the network. The cost of a network is defined as AxR+BxC where A is the cost coefficient for gates, R is the number of gates in the network, B is the cost coefficient for connections and C is the 6k number of connections. For example, if a network has 17 gates and 30 connections and A=1000, B=l, then cost= 17 x 1000 + 30 x 1= 17030. The values of A and B can be specified in input data cards by users. In Fig. 3.1-l(a), subroutine UNIVSA is called first to generate an initial network, and subroutine FR0CTI is then applied to simplify the initial network as much as possible. The network obtained at this stage may not satisfy the maximum fan-in/ fan-out restrictions. So the subroutine JEFF is employed to transform the network into a fan -in/ fan -out restricted network. The subroutine RCEC is applied to simplify the fan -in/ fan -out restricted network. In Fig. 3.1-l(b), after subroutine JEFF has been applied, subroutine PR0CCE will be called repeatedly until there is no further improvement in the cost of network. The loop marked with double asterisks in this figure means that this loop will be executed PR0MAX + 1 times, where PR0MAX is a parameter specified by the user in input data cards. At the end of the PR0MAX + 1st execution of the loop marked with double asterisks, the current cost will be compared with the best cost obtained at the end of the PROMAX-th execution of the same loop. If the current cost is better than the previous "best cost" , set "best cost" to be the current cost and repeat the loop until there is no improvement in the cost; otherwise the "best cost" is the best result that we can get by these combinations of PR0CII, JEFF and PR0CCE. It is clear form Fig. 3.1-1 that in NETTRA-E1-FIF0, we call PR0CCE only once in the PR0CII-JEFF-PR0CCE loop, but in NETTRA-E2- FIF0, we continually apply PR0CCE in each loop until there is no further improvement. This is, in fact, the main difference between NETTRA-E1-FIF0 and NETTRA-E2-FIF0. This means that the network may be simplified further if we continue the execution of this loop, although this loop is already executed PR0MAX + 1 times. 65 (start ) UNIVSA 3 PROC II I JEFF i PROCCE C STOP ) Fig. 3-1-1 (a) The order of the subroutines called by MAIN in NETTRA-E1-FIF0. ( START ) _3_ UNIVSA — *r — PROC II * l JEFF PROCCE i *# ( STOP ) Fig. 3.1-1 (b) The order of the subroutines called b, MAIN in NETTRA-E2-FIFF0. (Loops marked with single asterisk will be executed repeatedly until there is no improvement in the cost of the network. The loop marked with double asterisks will be executed at least ^ROMAX + 1 times. (See Sec. 3«1-)) 66 3.2 Results of computer experiments Thirty l+-variable functions and thirty 5-variable functions were used for the experiments under different maximum fan -in/ fan -out restrictions. Table 3.3-1 through Tabel 3.3-*+ give the results of the experiments. Each table contains several columns. The column entitled FUNCTION (HEXADECIMAL) gives the hexadecimal representation of the output vector for each function. For example, kAFl represents the vector 0100 1010 1111 0001, vertically reading the output column in the truth table. The cost of the network is defines as 1000 x R+C where R is the number of gates and C is the number of connections. The cost of the initial network for each function is given in the column entitled "INITIAL NETWORK". The column entitled "FIFO ALONE" shows the results given in [19 1 , Fig. 3.2-1 shows the flow of the program implemented by J. G. Legge for these results. In program FIFO, subroutine UNIVSA is applied first to get an initial network. Subroutine PR0CII is then called repeatedly until there is no further improvement in the cost of the network. The sim- lified network may not satisfy the maximum fan-in/ fan-out restrictions, so subroutine JEFF is called to transform the network into maximum fan-in/fan- out restricted form. The sequence PR0CII - JEFF is treated the same way as shown in Fig. 3.1-l(b). ( START ) 3z_ UNIVSA *■«- PR0CII JEFF 1 *# ( STOP) Fig. 3.2-1 The order of subroutines called in FIFO. The single asterisk and the double astericks have the same meaning as in Fig. 3.1-1 (b). 67 FUNCTION (HEXADECIMAL) INITIAL NETWORK (UNTVSA) FIFO ALONE NETTRA- El- FIFO NETTRA- E2- FLFO 1. 4afi 2. f6ee 3. ac6e 4. 2d86 5. 9DA5 6. 5F12 7. FIFk 8. 6830 9- 90^8 10. EA9B 11. 68F5 12. U6F8 13. B860 Ik. E139 15. 70CF 17105 17100 17104 17106 17104 17105 17103 17108 17109 17103 17104 17105 17107 17105 17104 19030 12018 20031 34049 22033 11017 14021 26039 28042 15023 21032 25038 26039 33049 14021 19030 11018 22033 39056 21031 11017 14021 20030 23034 23035 20031 16025 25037 30044 14022 11020 11018 10018 14024 9017 11017 14021 14022 19030 12022 14024 14023 11020 15026 13021 Table 3.2-1 Thirty 4-variable functions with FI=F0=F0X=F00=2 68 FUNCTION (HEXADECIMAL) INITIAL NETWORK (UNIVSA) FIFO ALONE NETTRA- El- FLFO NETTRA- E2- FIFO 16. F3DO 17104 11017 11018 11018 17. BC7A 17103 24036 23034 13022 18. F6AE 17102 19029 14023 12019 19. de84 17105 25038 24037 10016 20. 6777 17102 9014 9014 9014 21. C11B 17106 19030 18029 13022 22. 60CF 17105 11+023 14023 14023 23. D379 17103 34049 34051 15025 24. AE1F 17103 12020 16025 10017 25. A8I+9 17107 28042 30045 16027 26. B896 17105 32048 38056 16027 27. 9BCB 17103 13019 17026 9015 28. 5710 17107 11018 11018 11018 29. 6433 17106 12019 11018 8014 30. 9903 17107 10017 10017 10016 Table 3-2-1 (continued) 69 FUNCTION (HEXADECIMAL) INITIAL NFTWORK (UNTVSA) FIFO ALONE NETTRA- El- FIFO NETTRA- E2- FIFO 1. Uafi 17105 10023 10023 10023 2. f6fe 17100 80l4 80l4 8014 3. AC6E 17104 12024 12025 7017 h. 2D86 17106 21038 18035 11023 5. 9DA5 17104 10022 10022 10022 6. 5F12 17105 7013 7013 7013 7. FIFk 17103 70l4 70l4 7014 8. 6830 17108 16032 15030 8019 9. 90I+8 17109 11026 9022 8023 10. EA9B 17103 9022 9022 9022 11. 68F5 17104 11023 10024 8019 12. +6f8 17105 17030 12025 8017 13. B860 17107 12026 12026 9020 14. E139 17105 14029 17033 12025 15. 70CF 17104 6014 60l4 6014 . Table 3-3-2 Thirty 4-variable functions with FI=F0=F0X=F00=3 7C FUNCTION INITIAL FIFO NETTRA- NETTRA- (HEXADECIMAL) NETWORK ALONE El- E2- (UNIVSA) FIFO FIFO 16. F3DO 17104 7013 7014 7014 17. B37A 17103 12025 12025 12025 18. f6ae 17102 10020 8019 7017 19. de84 17105 13026 12025 8021 20. 6777 17102 7012 7012 7012 21. CUB 17106 11024 9021 8019 22. 60CF 17105 6017 6017 6017 23. D379 17103 17035 16030 12025 24. AE3JF 17103 6015 6015 6015 25. A8U9 17107 1430 13029 10024 26. B896 17105 23042 22040 11023 27. 9BCB 17103 11022 9020 6oi4 28. 5710 17107 9016 9016 9016 29. 6433 17106 6014 6oi4 6oi4 30. 9903 17107 6014 6oi4 6014 Table 3-3-2 (continued) 71 FUNCTION (HEXADECIMAL) INITIAL NETWORK (UNIVSA) FIFO ALONE NETTRA- El- FIFO NETTRA- E2- FIFO 1. UFA295F6 33305 31058 28053 16034 2. A6CDDF18 33305 39067 38066 20044 3. FF68A1F3 33303 20041 19041 17034 4. IEE652UO 33310 20038 27046 16035 5. 9E638E7F 33301 24045 27050 17039 6. OA888103 33315 13030 14033 13030 7. U9F363CD 33305 28054 26049 17036 8. 8B5809FO 33310 21041 21042 15032 9. bfd6c6da 33302 28050 30054 17036 10. C6E7103E 33307 27048 24044 15033 11. 7A871D71 33306 34062 35064 17306 12. AEU7BF9F 33301 22043 21042 15033 13. AB9569A2 33307 35065 34068 17038 14. 88B749B4 33308 22040 38064 18038 15. 49C13031 33312 14032 12029 11028 Table 3-2-3 Thirty 5-variable functions with FI=F0=F0X=F00=3 72 FUNCTION (HEXADECIMAL) INITIAL NETWORK (UNIVSA) FIFO ALONE NETTRA- E- FLFO NETTRA- E2- FIFO l6. 96B036A5 33308 30057 30057 18038 17. 686F271E 33305 27050 33060 16035 18. 5B23D763 33305 220UU 210U1 1U031 19. 858ECICB 33308 17032 18036 17033 20. D5 i +2DA86 33308 31057 30058 16036 21. 113E5202 33310 2^0^5 28051 18035 22. 96OD6568 33309 3^061 1+3073 21050 23. 1DUC022D 33311 2201+6 2701+6 27051 2k. A68E9866 33308 30053 280^9 1503^ 25. A8AA5CE8 33308 1803^ 20039 16033 26. BU2A97A8 33308 3606k 39097 190^0 27. D58A9F11 33307 20039 2^6 1.1+030 28. Udi6bUiU 33310 2101+0 30055 lk036 29. DA1825E1 33309 35065 38065 17036 30. 395722CD 33307 31060 32059 18036 Table 3*2-3 (continued) 73 FUNCTION (HEXADECIMAL) INITIAL NETWORK (UNIVSA) FIFO ALONE NETTRA- E- FIFO NETTRA- E2- FIFO 1. UFA295F6 33305 190l*7 l70i+3 160^0 2 . A6CDDF18 33305 22052 2105^ 160U3 3. FF68A1F3 33303 1^039 li+039 1U039 k. IEE652I4O 33310 18038 170142 13031 5. 9E638E7F 33301 15038 170U1 11030 6. OA888103 33315 11033 11033 11033 7- U9F363CD 33305 170^1+ 160U5 1U039 8. 8B5809FO 33310 15036 15039 11029 9. BFD6c6da 33302 I80UU 2201+8 17039 10. C6E7103E 33307 I60UO 160^0 1601+0 11. 7A871D71 33306 23053 21*057 150^2 12 . AEU7BF9F 33301 13036 lUOto 12032 13. AB9569A2 33307 23052 22053 l8ol*3 lU. 88B7^9Bl+ 33308 25053 2U052 1701+5 15. U9C13031 33302 12031 12031 12031 Table 3-2-U Thirty 5-variable functions with FI=F0=F0X=F00=U Ik FUNCTION (HEXADECIMAL) INITIAL NETWORK (UNIVSA) FIFO ALONE NETTRA- El- FIFO NETTRA- E2- FIFO l6. 96B036A5 33308 190l*6 l8ol*6 l60l+l 17. 686F271F 33305 22053 21051 1801*6 18c 5B23D763 33305 16039 150^0 15038 19. 858EC1CB 33308 13031 12029 IIO26 20. D5^2DA86 33308 2101+9 2001*8 15038 21. 113E52C2 33310 170U0 15036 ll*03l* 22. 96OD6568 33309 23050 21*057 170l*6 23. 1I)1*C022D 333H 2001+9 200U8 11*035 2U. A68E9866 33308 1901+3 170U3 170l*0 25. A9AA5CE8 33308 13033 13033 13033 26. BU2A97A8 33308 21050 2 001*9 12031* 27. D58A9FH 33307 15037 1501+0 11+031+ 28. Udi6bUiU 33310 1901+6 1801*6 150l*l 29. DA1825E1 33309 20050 1901*8 180U7 30. 395722CD . 33307 16039 23052 13037 Table 3-2-1+ (continued) 75 Table 3-2-1 through Table 3°2-U imply that NETTRA-El-FIFO gives usually better results than FIFO, and NETTRA-E2-FIF0 is always equal to or better than the other two programs. For example, in Table 3-2-2 for function #U, FIFO ALONE gets a network with 21 gates and 38 connections, NETTRA-El-FIFO gets a network with 18 gates and 35 connections and NETTRA-E2-FIF0 gets a network with 11 gates and 23 connections which is a great improvement. Many other similar situations can also be found in Table 3.2-1 and 3-2-2. It can also be found in these tables that FIFO ALONE can produce better results than NETTRA-E1-FLF0 for some functions. This is because that in NETTRA-El-FIFO the central subroutine PROCCE, which realizes the error-compensation procedures is called only once, whereas in FIFO the subroutine JEFF is repeatedly called. For some functions all three of FIFO, NETTRA-El-FIFO, and NETTRA-E2-FIF0 give the identical costs, though they improve initial networks. 3.3 Comparisons with some other known design procedures In [28], Su and Nam presented an algorithm for synethesizing multiple -output network using NAND gates under fan-in and fan-out restrictions, A set of incompletely specified U-variable output functions used by Su and Nam is also tested by NETTRA-E2-FIF0. Table 3.3-l(a) shows this set of functions. Since our transduction programs are implemented for NOR network design, the dual functions are needed for our programs. This is shown in Table 3o3-l(b). Table 3-3-2 gives the results for this example. The network derived by Su and Nam's algorithm has 6 levels, 25 gates and h2 connections, as shown in Fig. 3*3-1° Obviously, our results are better in cost. 76 OUTPUT FUNCTIONS NAND TRUTH TABLES z i Z 2 Z 3 \ 00000*0000*0*111 1111001100*0*001 111**01111*0*011 0000000101*0*011 Table 3»3-l(a) Su-Nam s ^-variable incompletely specified output functions. OUTPUT FUNCTIONS NOR TRUTH TABLES Z l Z 2 Z 3 \ 000*1*1101*11111 011*1*1100110000 001*1*00001**000 001*1*0101111111 Table 3.3-l(b) The dual of functions in Table 3-3-l(a). 77 H I en on O) H ,0 o5 H C ■H w £ o •H -P O c . <+-i o 0) c\T 42 * 4J CM O o •p •» •H X in O CD Pn U Fm O £ *^ •P H 0) Pm CM I no b0 A A A A OJ oo_h- X X ■x I X - H A H i o «H O • OJ OJ w OJ 3 EH Eh OJ o T3 O 0) (in g OJ P-4 T3 M O on i oo oo bO •H Pn OJ, OO 8l Besides the im completely specified case, nine completely specified functions obtained by setting or 1 for the don't cares in Table 3-3-l(b) are also tested by NETTRA-E2-FIF0. Table 3-3-3 and Table 3-3- 1 * give the functions and the cost of networks, respectively. These completely specified functions can be solutions for the original incompletely specified case. In Table 3-3-^, we got 27 different networks. Among them only four have higher costs than Su and Nam's result, two have same costs and all others have lower costs. The best network in cost derived by NETTRA-E2-FIF0 for Su and Nam's example has 17 gates and 31 connections, as shown in Fig. 3»3 - ^-* after replacing NOR gates by NAND gates. Since several other transduction programs can also treat the maximum fan-in/fan-out restrictions, their effectiveness is compared. Table 3*3-5 provides the comparison of the costs of 30 5 -variable functions by applying Programs NETTRA-PGl-FIFO, NETTRA-G1-FTF0, NETTRA-G2-FTF0, NETTRA-G3-FTF0 and NETTRA-E2-FIF0. The diagrams of the flow of these programs are similar to that in Fig. 3-l-l(b). The general flow diagram for these programs is given in Fig. 3*3-5, where the transduction procedure with the maximum fan-in/fan-out restrictions can be any of the subroutines SUBSTI, PRITFF, GTMERG or PROCCE which is the central subroutine of NETTRA-PGl-FIFO, NETTRA-G1-FIF0 and NETTRA-G2-FIF0, NETTRA-G3-FTF0, or NETTRA-E2-FIF0, respectively. The number of best networks obtained by each program and the average computation time per function are listed in Table 3-3-6. Obviously, NETTRA-E2-FIF0 is the most effective transduction program. But it is also the most time-consuming one. An extension of the programs discussed in this paper yields a better network which has 15 gates and 29 connections. This will be reported elsewhere. oo oo OO OO OO oo oo oo OO -H/ J- -H/ -tf -3- -Hr J- -=f -3- -3- N H H H H H H H H H O O o o O O O o o s o H EH oo OO pq m OO oo pq pq on CO ^ •H Jh II o) then the loops in Fig. 3.1-l(b) which are marked with double asterisks . (**) will be executed i + 1 times as discussed in section 3.1. PROMAX is punched in columns 37 through UO. This field is meaningless if TYPE is specified to 1 (NETTRA-E1- FIFO is called). (g) TYPE TYPE is a two-value integer (either 1 or 2). If TYPE is equal to 1, programs NETTRA-E1-FIF0 will be called. If TYPE equals 2, programs NETTRA-E2- FIFO will be called. TYPE is punched in columns Ul through kk. (h) LMAX LMAX is the allowable maximal number of levels of the network. It is punched in columns ^5 through k&. If its space is blanked or if LMAX = 0, then LMAX will be set to 500 in the program automatically. LMAX = 500 in fact means that there is no restriction on the number of levels. f i ) NEPMAX NEPMAX is the maximal allowable number of error-components in the CSPFE of some gate. If the total number of error-components is greater than 92 NEPMAX, then the programs gives up to compensate for these errors. NEPMAX is specified in columns 4 9 through 52, if the corresponding space is set to zero N-l or is blanked. Then it will be set to 2 automatically. U.S The function cards Subroutine IMEVSA reads the function cards which contain the truth table(s) for the output functions. It reads four cards for each function (IMIVSA is designed to handle functions with up to eight external variables o and 2 = 256 columns are needed for an eight variable truth table ). The truth table for each output function must be punched (one column for each value) beginning in the first column of the first card. If less than four cards are needed for an output function, blank cards must be added so that the total number of cards for each function is four. The truth table values must be punched in the following order (in this case for a three variable function): f(0,0,0) f(0,0,l), ..., f(l,l,0), f(l,l,l). 93 CHAPTER 5 CONCLUSIONS Error-compensation programs, NETTRA-E1-FTF0 and NETTRA-E2-FIF0, can treat fan-in/fan-out restricted, multiple -output and incompletely specified networks. It is observed in Chapter 3 that these two programs are very effective in producting reasonably good networks. Program NETTRA-E2-FIF0, in general, can give better results than any other transduction program, although it is more time-consuming. Existing methods which can find optimal networks are usually too time-consuming* when the number of gates of a network exceeds 9» Su and Nam's algorithm can also yield fan-in/fan-out restricted networks, but the results are much worse than those by the error-compensation programs. Hence, at this time, we can say that error-compensation programs are a very good tool for NOR or NAND network design from the practical point of view. * For example, the integer programming method and the branch-and-bound method require tens of hours, several hours, or more, when the number of gates is 10 or more. 9^ LIST OF REFERENCES [l] Culliney, J. N. , Lai, H. C. and Kambayashi, Y. "Pruning procedures for NOR networks using permissible functions (Principles of NOR network transduction programs NETTRA-PG1, NETTRA-P1, and NETTRA-P2)," Report No. UIUCDCS-R-7I+-69O, Dept. of Computer Science, University of Illinois, November 197*+. [2] Culliney, J. N. , "Program manual: NOR network transduction based on connectable and disconnectable conditions (Reference manual of NOR network transduction programs NETTRA-G1 and NETTRA-G2)," Report No. UIUCDCS-R-7^-698, Dept. of Computer Science, University of Illinois, February 1975. [3] Cutler, R. B. , etal," TISON-VERSON 1: A program to derive a minimal sum of products for a function or set of functions which may not be completely specified," to appear as Report. Department of Computer Science, University of Illinois, Urbana, Illinois. [h] Davidson, E. S., "An Algorithm for NAND Decomposition of Combinational Switching Systems", Ph.D. dissertation, Department of Electrical Engineering and Coordinated Science Laboratory, University of Illinois at Urb ana-Champaign, Urbana, Illinois, 1968. Dietmeyer, D. L. , and Su, Y. H. , "Logic design automation of fan-in limited NAND networks," IEEETC, Vol. C-l8. No. 1 Jan. 1969. [6] Gimpel, J. F. , "The Minimization of TANT Networks," IEEE Transactions on Electronic Computers, Vol. EC-16, pp. 18-38, February, 1967. [7] Hellerman, L. , "A catalog of three-variable OR-INVERT and AND- INVERT logical circuits", IEEE Trans. Electronic Computers , Vol. EC-12, pp. 198-223, June I90T : [8] Hohulin, K. R. , and Muroga, S. "Alternative methods for solving the CC-table in Gimpel 's algorithm for synthesizing optimal three level NAND networks," Report No. 720, Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, Illinois, April 1975. [9] Kambayashi, Y. , Lai, H. C, Culliney, J. N. , and Muroga, S., "NOR network transduction by error -compensation (Principles of NOR network transduction programs NETTRA-E1, NETTRA-E2, and NETTRA-3)", to appear as Report, Department of Computer Science, University of Illinois, Urbana, Illinois. 95 Kambayashi, Y., Lai, H. C, and Muroga, S., "Transformations of NOR networks," to appear as Report. Department of computer Science, University of Illinois at Urbana -Champaign, Urbana, Illinois. Kambayashi, Y., and Muroga, S., "Network transduction based on permissible functions (General principles of NOR network transduction NETTRA programs)," Dept. of Computer Science, University of Illinois, June 1976. Report No. UIUCDCS-R-76-80U. Kambayashi, Y. , and Culliney, J. N. "NOR network transduction procedures based on connectable and disconnectable conditions (Principles of NOR network transduction programs NETTRA-G1 and NETTRA-G2)," to appear as a report, Dept. of Computer Science, University of Illinois. Lai, H. C, and Culliney, J. N., "NOR network transduction based on error-compensation (Reference manual of NOR network transduction (Programs NETTRA -El, NETTRA-E2, and NETTRA-E3), Report No. 732, Department of Computer Science, University of Illinois at Urbana - Champaign, Urbana, Illinois. Lai, H. C, and Kambayashi, Y., "NOR network transduction by generalized gate merging and substitution (Principles of NOR network transduction programs NETTRA-G3 and NETTRA-GV', Report No. 728 Department of Computer Science, University of Illinois, Urbana, Illinois, June 1975. [15] Lai, H. C. , and Culliney, J. N. , "Program manual: NOR network pruning procedures using permissible functions (Reference manual of NOR network transduction programs NETTRA-PGl, NETTRA- PI, and NETTRA-P2) , "Report No. UIUCDCS-R-7 1 +-686, Dept. of Computer Science, University of Illinois, November 197*+. [l6] Lai, H. C. , "Program manual: NOR network transduction by generalized gate merging and substitution (Reference manual of NOR network transduction programs NETTRA-G3 and NETTRA-G*+ ) , " Report No. UIUCDCS-R- 75-71*+, Dept. of Computer Science, University of Illinois, April 1975. [17] Lai, H. C, Nakagawa, T. , and Muroga, S., "Redundancy check technique for designing optimal networks by branch-and -bound method," International Journal of Computer and Information Sciences, Vol. 3, pp. 251-271, 197*+. [18] Lee, H. , and E. S. Davidson, "A transform for NAND network design", IEEE Trans. Comput., Vol. C-21, pp. 12-20, January 1972. [19] Legge, J. G. , "The design of NOR-networks under fan-in and fan-out constraints (A program manual for FIFOTRAN-Gl)", Report No. 66l, Department of Computer Science, University of Illinois, Urbana, Illinois. 96 [20] Maley, G. A., and Earle, J., The Logical Design of Transistor Digital Computers The NOR network constructed in the same manner as the NAND tree network in Fig. 6.U.1, page 156, is called the universal network in the text. Prentice Hall, 19&3 • [21] McCluskey, E. J., "Logical design theory of NOR gate networks with complemented inputs", Proc. Uth Amu Symp. on Switching Circuit Theory and Logical Design , pp. 137-l^Q, 19&3. [22] Muroga, S., Threshold Logic and Its Applications , Wiley-Interscience, John Wiley & Sons, New York, Chapter 14, 1971. [23] Muroga, S., "Logical design of optimal digital networks by integer programming," chapter 5 of book, Advances Information System Science , Vol 3> edited by J. T. Tou, Plenum Press, 1970. [2k] Muroga, S., and Ibaraki, T. , "Design of Optimal Switching Networks by Integer Programming", IEEE TC , Vol. C-21, No. 6, pp. 573-582, June, 1972. Muroga, S., "Switching Theory", class notes for CS 391 course, Department of Computer Science, University of Illinois at Urbana- Champaign, Urbana, Illinois. [25-1 Nakagawa, T. , and Muroga, S., "Comparison of the Implicit Enumeration Method and the Branch-and Bound Method for Logical Design", Report No. ^55, Department of Computer Science, University of Illinois at Urbana- Illinois [26] Nakagawa, T. , and Lai, H. C, "A branch-and-bound algorithm for optimal NOR networks (The algorithm description)," Report No. U38, Dept. of Computer Science, University of Illinois, April 1971. [27] Su, Y. H., and Nam, C. W. "Computer-aided synthesis of multiple output multi-level NAND networks with fan-in and fan-out constraints", IEEE Trans. Comput., Vol. C-20, December 1971. White, B. E., "Efficient realization of Boolean functions by pruning NAND trees," September, 1969, Lincoln lab. Report. \ OGRAPHIC DATA ET 1. Report No. uiucd - - - 2- 3. Recipient*! Accession No. ^c and Sul'l itle h (NAND) NETWORK DESIGN: ERROR-COMPENSATION PROCEDURES FOR 5- Report Date January 1977 K-IN AND FAN-OUT RESTRICTED NETWORKS (NETTRA-E1-FIFO AND - - 6. \ - fckson Kwo-Chain 8- Performing Organization Rept. No - UIUCDCS-R-77-8^7 ■in;; Organization Name and Address Apartment of Computer Science 10. Project/Task/Work Unit No. fevers ity of Illinois at Urbana-Champaign Ibana, Illinois 6l801 11. Contract /Grant No. NSF DCR 73-03^21 MM soring Organization Name and Address Itional Science Foundation DO G Street, N.W. 13. Type of Report & Period Covered Master thesis ngton, D.C. 20550 14. kpplcment.irv Notes 1 1 1> This paper presents the error-compensation procedures which can find near optimal (NAND) networks under fan-in and/or fan-out restrictions by using the concept of patible set of permissible functions with errors (CSPFE). Two computer programs, TRA-E1-FIF0 and NETTRA-E2-FIF0, are implemented to realize the error-compensation jcedures under fan-in and/or fan-out restrictions. Both programs have the capabil- ses in transforming a large non-optimal NOR network under fan-in and/or fan-out tions into a near-optimal one by reducing the number of gates and connections, results of the computer experiments are also included in this paper. jey lords and Document Analysis. 17a. Descriptors Logic design, logic circuits, logical elements, programs (computers). identifiers Open-Ended Terms Computer-aided-design, permissible functions, network transduction, network reformation, NAND gates, NOR gates, error-compensation procedures, CSPFE, 1-error, rror, fan-in, fan-out, NETTRA- El-FIFO, NETTRA-E2-FIF0. ATI 1- ,e Id /(.roup '•ailability Statement Release unlimited 19. ■ < urit y (lass (This Report ) LNC.I.ASSIFIKD 21- No. of Pa, 100 20. Security ( lass (This Page LASSIFIE1 22. Price 15 1' USCOMM-DC «0329-P>7l *A *x 2 1979