LI B RAHY 
 
 OF THE 
 
 UNIVERSITY 
 
 Of ILLINOIS 
 
 510.84 
 It6r 
 
 no. 349-354 
 cop. Z 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/bumbundleprocess353ring 
 
jr <\ v 
 
 REPORT NO. 353 
 
 Til 3S3 
 
 7?L^r~/ 
 
 BUM - BUNDLE PROCESSING MACHINE 
 
 by 
 DAVID RING 
 
 October, 1969 
 
 THE LIBRARY OF THE 
 OCT 28 1969 
 
Report No. 353 
 
 BUM - BUNDLE PROCESSING MACHINE* 
 
 by 
 
 DAVID RING 
 
 October, 1969 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 Supported in part by Contract Number N000 li+-67-A-0305-0007 and submitted 
 in partial fulfillment for the degree of Master of Science in Electrical 
 Engineering, at the University of Illinois, October, I969. 
 
Ill 
 
 ACKNOWLEDGMENT 
 
 The author would like to take this opportunity to publicly 
 thank those who have helped, him in this endeavor. Professor W. J. 
 Poppelbaum, as research advisor, has freely given his support and guidance. 
 The two years that the author has worked for him have been rewarding and 
 memorable. The machine and electronics shops under Frank Serio have 
 assisted in the mechanical design of the machine, and David Chen and 
 Doug Warren assisted in assembling it. Elinor Peterson typed this 
 manuscript. 
 
IV 
 
 TABEL OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. BUNDLE PROCESSING 2 
 
 2.1 General 2 
 
 2.2 Operations with Logic Gates 3 
 
 2.3 Arithmetic Operations ..... 5 
 
 2.k Mapped Representation 6 
 
 2.5 Two Bundles 8 
 
 3. ATTRITION PROBLEM 10 
 
 3.1 Two-input Combinational Circuits 10 
 
 3.2 Multiple -input Combinational Circuits 13 
 
 k. BUM - BUNDLE MACHINE 15 
 
 4.1 General 15 
 
 k.2 Decoder 15 
 
 k.3 Lamp Drivers 20 
 
 k.k Arithmetic Unit .21 
 
 5. CONCLUSION 2k 
 
 LIST OF REFERENCES 25 
 
1. INTRODUCTION 
 
 A system for representing numbers as probabilities has been 
 investigated under the guidance of Professor W. J. Poppelbaum of the 
 Hardware Research Group of the University of Illinois Department of 
 Computer Science. Under this system, called Bundle Processing, a number 
 can be represented by the percentage of wires at one of two logic levels 
 in a group of wires . By operating on all of the wires in a bundle in 
 parallel, fast arithmetic operations can be performed. A machine was 
 built which successfully demonstrated Bundle Processing. 
 
 This work will describe and derive the equations and solutions 
 used in Bundle Processing, and will demonstrate some difficulties. 
 
2. BUNDLE PROCESSING 
 
 2.1 General 
 
 A number in the closed interval [0, l] can be closely approxi- 
 mated by the fraction of wires in a group that is at one of two distinct 
 
 logic levels. If there are N wires in the group, n of which are at the 
 
 n 
 logical "1" level, it may be said that the number — is being represented. 
 
 The group of N wires will be called a "Bundle" and will be the basic unit 
 
 of Bundle Processing. The variable name "X" will be given to the 
 
 fraction — and will be called its "value". The terms "logical '1' level", 
 
 "up", and "ON" are synonymous, and likewise the terms "logical '0' level", 
 
 "down", and "OFF" are synonymous. 
 
 n 
 The ratio — does not depend on which n wires are ON. They may 
 
 be randomly distributed through the bundle . If half of the N wires are 
 
 randomly chosen to form a new, smaller bundle, the new bundle will have 
 
 2 n 
 the ratio — r— = — . Randomly selecting part of a bundle does not change 
 
 2 1 
 
 its value. Since each wire in a bundle is — of the bundle, its ratio 
 
 N n 
 is — — = — . Each wire in a randomly distributed bundle has the same 
 
 N 
 value as the bundle itself. 
 
 The fraction "x" has discrete values with equally spaced steps 
 of — between them. X may approximate any number in the range [0, l] with 
 the maximum error of _+_ -^- . The accuracy with which the value of a 
 bundle approximates a number may be improved by increasing the number 
 of wires in the bundle. 
 
 One property that has been exploited in Bundle Processing is 
 that of being "Failsoft". Since any one wire or component is — of the 
 entire bundle or element, it could fail without causing failure of the 
 
entire system. The resultant X would be incorrect by at most — for each 
 wire that has failed. The failsoft concept guided several decisions as 
 will be seen later. 
 
 The last property is that of speed. Since all arithmetic 
 operations are done in parallel, there is virtually no delay between 
 input changes and output response. In a binary system, many clock 
 pulses must pass before even additions are completed. 
 
 2.2 Operations with Logic Gates 
 
 2.2.1 AMD Gates 
 
 The basic concept of Bundle Processing, and all other stochastic 
 systems, is that if one input to a logical AND gate has a probability X, 
 of being a "1", and the other input has a probability X p of being a "1", 
 then the output has the probability X,X of being a "1" if the inputs 
 are independent. This statement can be written 
 
 VALCX^) = X^ 2.1 
 
 which says that the value of the probability of the output of a two- input 
 AND gate is the product of the values of the probabilities of the inputs. 
 This is an easy way to multiply. 
 
 If two equal size bundles have the values X, and X respective- 
 ly, it has already been shown that each wire in the first bundle also has 
 the value X and those in the second bundle X p . If at random one wire 
 is brought out of each bundle, and those two wires become the inputs 
 to a two- input AND gate, the value of the output of that gate will be 
 the product of the input values. If a second pair of wires is chosen, 
 
and used as the inputs to a second AMD gate, the value of that output is 
 also X.X . If more pairs are selected until every wire has been used 
 exactly once, N AND gates will have been used, and the value of the out- 
 put of each one will be X..X . The N output wires may be called a 
 bundle, and since the value of each wire in the bundle is X-,X_, the value 
 of the bundle is also XX.. 
 
 Multiplication is very easy, but highly parallel. If N is 
 1000, it would take 1000 gates to multiply. A compromise must be made 
 between the desired accuracy and the cost of the system. 
 
 Multiplication is also very fast. The delay between input 
 change and output change is only the delay through the AND gates used. 
 This may be smaller than one microsecond. 
 
 2.2.2 NOT Gates 
 
 The result of inverting the logic level of each wire in a 
 bundle is more easily derived. If the value of the wires in a bundle 
 which are at the "1" level is X, then the value of all of the other wires 
 (which are at the "0" level) is 1 - X. If each wire is converted to a 
 logical NOT circuit, the values are reversed. That is, the value of 
 those wires at the "1" level is now 1 - X. 
 
 VAL(X) = 1 - X 2.2 
 
 2.2.3 OR Gates 
 
 The last basic Boolean function is the logical OR, and even it 
 can be derived from the AND and NOT functions through the use of DeMorgan's 
 theorem . 
 
VALCX^VXg) = VALCX^) 
 
 = 1 - (1 - Xl )(i - x 2 ) 
 
 = X 1 + X 2 - X X X 2 2.3 
 
 All other Boolean functions are complex combinations of AND-, OR, 
 and NOT, and can be evaluated using the values for these three basic 
 functions. 
 
 2. 3 Arithmetic Operations 
 
 As shown earlier, the values of two bundles can be multiplied 
 
 by using AND circuits. The second operation that can be performed is 
 
 n l 
 scaled addition. If there are two bundles having the values -rr and 
 
 n 2 
 
 -tj-, the number of wires at the "1" level is n, + n , but the total 
 
 number of wires is then 2N. If the two bundles are put together as one 
 
 n i f n 2 
 large bundle, its value is — ^ . As seen previously, if half of 
 
 these wires are chosen at random to again make a bundle with N wires, the 
 
 value does not change. The problem of the scale factor of — has never 
 
 been successfully solved, and in a later section it will be shown that 
 
 some types of solutions do not exist. This problem has been called the 
 
 "Attrition Problem". 
 
 Because the only numbers that can be handled are all positive 
 
 and not larger than unity, subtraction and division cannot be done. 
 
 For this reason, other mappings have been investigated. 
 
2.4 Mapped Representation 
 
 2.4.1 General 
 
 In order to be able to subtract, a method must be found to 
 represent negative numbers . The method chosen was to map the range 
 [-1, +1] onto [0, +1]. The transformation is Y = 2X - 1 where "X" is 
 again the value of the bundle, and "Y" is the number being represented. 
 
 One advantage of this mapping is that the negative of a number 
 may be obtained by merely inverting each wire in the bundle. 
 
 Y = 2X - 1 X 1 = 1 - X 
 Y' = 2X* - 1 
 
 = 2(1 - x) - 1 
 
 = -(2X - 1) - Y 
 Y* = -Y (2.4) 
 
 2.4.2 Arithmetic Operations 
 
 Again scaled addition can be performed by combining two bundles 
 and randomly selecting half of the wires . Scaled subtraction involves 
 inverting each wire of the subtrahend bundle and adding as before. 
 
 In checking the results of operations by AND and OR gates, it 
 is found that multiplication is no longer easy. 
 
 Equation 2.1 shows 
 
 VAL(X ] _X 2 ) = X X X 2 (2.1) 
 
if x = i-ti. 
 
 VAL(X.X ) » X m X.X, 
 
 Y + 1 Y l + X Y 2 + X 
 
 H 1 = (-^-5--) (-^r-O 
 
 Y =1^2 + Y x + Y 2 - 1) (2.5) 
 
 Likewise 
 
 VAL(X ] _ V X 2 ) = X = X 1 + X 2 - X X X 2 (2.3) 
 
 Y + l Y l + 1 Y 2 + 1 Y l + \ Y 2 + \ 
 2 2 + 2 \ 2 )\ 2 ' 
 
 Y = |(1 + Y JL + y 2 - y^) (2.6) 
 
 Upon further investigation, it was found that multiplication 
 could be performed with coincidence circuits . 
 
 X l ® X 2 = X 1 X 2 V X 1 X 2 
 
 VAL(X X I X 2 ) = VAL(X 1 X 2 V X^) = X 
 
 x = x ± x 2 + (i - x x )(i - x 2 ) 
 - x 1 x 2 (i - x x )(i - x 2 ) 
 
 Y = Y^Yg (2.7) 
 
 Thus, although the multiplication is more complicated, it is 
 still relatively easy and inexpensive to perform. Section 3-1 shows in 
 greater detail how this solution can be derived. 
 
8 
 
 Because the range of numbers is [-1, I], division is no less 
 difficult than the previous mapping. One form of solution is available 
 however, and is shown in the following section. 
 
 2.5 Two Bundles 
 
 2.5-1 General 
 
 Using the mapping Y = 2X - 1, all real numbers can be approxi- 
 mated. A number can be represented with two bundles, one containing the 
 numerator and the other the demonimator. A number whose magnitude is 
 greater than unity would merely have its numerator greater than its 
 denominator. Performing the four arithmetic operations is again more 
 complicated, but it can be done, and while the attrition problem is still 
 present, the fact that both the numerator and denominator are affected 
 simultaneously compensates for it. 
 
 2.5.2 Arithemtic Operations 
 
 Multiplication of two numbers is done as before but it takes 
 twice as much circuitry. If N and D are the numerator and denominator, 
 respectively, of a bundle, the product Y = Y,Y is 
 
 N = H ± N 2 
 
 and D = D-jD 
 
 where Y = — 
 
Division is multiplication of the dividend and reciprocal of 
 the divisor. 
 
 Y 
 
 N = N X D 2 
 
 D = D 1 N 2 
 
 Addition and subtraction are performed as before except now 
 a common denominator must be found and used, and the denominator must 
 be halved to compensate for the attrition problem. 
 
 Y=Y+Y Y = Y - Y 
 1 ,1 2 1 2 
 
 N D + K„D N D - N D 
 
 N = =-= N = - 1 
 
 The value of the denominator bundle may be halved by adding it 
 to a bundle whose value is zero. 
 
10 
 3. ATTRITION PROBLEM 
 
 3*1 Two- input Combinational Circuits 
 
 The search for a useful solution to the attrition problem natur- 
 ally includes investigating two-input combinational circuits. All Boolean 
 functions of two variables can be written 
 
 C23 
 
 ffr-^Xg) = a^^ v a 2 x i x 2 v a 3 x l x 2 V a *| X l X 2 (3-1) 
 
 The "a" coefficients can have the values or 1, allowing 
 f (x, ,x ) to take on only sixteen different combinations. By evaluating 
 all sixteen values, it can be determined which functions are useful, and 
 if any are solutions to the attrition problem. 
 
 Equation 2. 3 shows that 
 
 VA1(X JL V X 2 ) = X 1 + X 2 - X X X 2 (2.3) 
 
 If X, and X are disjoint, the X X = 0, and 
 1 2 12' 
 
 VAL( Xl V X 2 ) d . s . - Xj_ + X 2 (3-2) 
 
 In the conjunctive normal form of f(x ,x ) (equation 3«l)> the four 
 minterms are disjoint through an AND gate. For example, 
 
 x ± x 2 • x x x 2 = (3-3) 
 
 The result is that 
 
 VAL(X 1 X 2 V X^Xg) = X X 2 + X 1 (l - X 2 ) (3.^) 
 
 Because this property holds for any selection of minterms from equation 
 3.1, the value of a function of two variables is 
 
11 
 
 X = VAL[f(x 1? x 2 )] = a^Xg + a^-Jl - x g ) + a (l - x-^Xg 
 
 + & k (l - Xl )(l - x 2 ) (3.5) 
 
 By using the desired transformation from Y onto X, it can readily be 
 determined if any useful or interesting functions are present. The 
 values for the two mappings are tabulated in Table 1. It can be seen 
 that multiplication is the only arithmetic function present, and in these 
 two mappings, no solution to the attrition problem exists. 
 
12 
 
 TABLE 1 
 
 a l 
 
 a 2 
 
 a 3 
 
 % 
 
 Y = X 
 
 Y = 2X - 1 
 
 
 
 
 
 
 
 
 
 
 
 -1 
 
 
 
 
 
 
 
 1 
 
 i-VV x i x 2 
 
 i(-l-Y 1 -Y 2+ Y 1 Y 2 ) 
 
 
 
 
 
 1 
 
 
 
 X 2 " X 1 X 2 
 
 |(-1-Y 1+ Y 2 -Y 1 Y 2 ) 
 
 
 
 
 
 1 
 
 1 
 
 1-x, 
 
 " Y l 
 
 
 
 1 
 
 
 
 
 
 X l " X 1 X 2 
 
 |(- 1+¥ i-W 2 ) 
 
 
 
 1 
 
 
 
 1 
 
 1 - x 2 
 
 " Y 2 
 
 
 
 1 
 
 1 
 
 
 
 V X 2 " 2X 1 X 2 
 
 -Y Y 
 12 
 
 
 
 1 
 
 1 
 
 1 
 
 1 - x x x 2 
 
 2 (1-Y 1 -Y 2 -Y 1 2 ) 
 
 1 
 
 
 
 
 
 
 
 X 1 X 2 
 
 it-l+Y^Yg+Y^g) 
 
 1 
 
 
 
 
 
 1 
 
 1-X l" X 2 +2x i X 2 
 
 r i Y 2 
 
 1 
 
 
 
 1 
 
 
 
 X 2 
 
 Y 2 
 
 1 
 
 
 
 1 
 
 1 
 
 1 " X 1 +X 1 X 2 
 
 |(1-Y 1+ Y £+ Y 1 Y 2 ) 
 
 1 
 
 1 
 
 
 
 
 
 X l 
 
 Y l 
 
 1 
 
 1 
 
 
 
 1 
 
 l-x 2+Xl x 2 
 
 — fl+Y -Y +Y Y ) 
 2 K X l L 2 1 2 J 
 
 1 
 
 1 
 
 1 
 
 
 
 X 1 +X 2" X 1 X 2 
 
 |(1+Y 1 +Y 2 -Y 1 Y 2 ) 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 +1 
 
 Boolean Function 
 
 Constant "0" 
 OR 
 
 Exclusive OR 
 
 NAM) 
 AND 
 Coincidence 
 
 NOR 
 Constant "1" 
 
13 
 
 3 ■ 2 Multiple -input Combinational Circuits 
 
 The vires in a bundle may be arbitrarily given sequential 
 numbers, and it may be said that the wire numbered n comes "before" the 
 wire numbered n + 1, and wire N comes before wire 1. Combinational 
 circuit number n is the circuit whose output is wire number n in the 
 output bundle, and whose two input wires will also be called n. 
 
 For the moment, only the mapping Y = X will be considered. 
 A full adder in binary arithmetic has three inputs, one each for the 
 addend, angend, and carry in, but it has only two outputs, one for the 
 sum and the other for the carry out. The binary adder works because the 
 carry out has the weight of two inputs. In bundle processing, any circuit 
 that has three input wires must have three output wires or information 
 can be lost. Every wire carries a weight of unity. That implies that 
 any adder that has two inputs and a carry in must have a sum wire and 
 two carry wires out. If all adder stages are to be the same, each must 
 then be able to accept two input carries, which then necessitates three 
 output carries. The number of carries can increase endlessly. 
 
 Two considerations can drastically reduce the number of carries 
 needed to a small finite number. The first is that overflow will not be 
 
 allowed. Out of the 2N wires in both inputs, at most N will be at the 
 
 N 
 
 1" level. The worst case then would be if the same -z wires in a row 
 
 in both bundles were ON. As an example, assume wires numbered from 1 to 
 ■_- in each input bundle were ON. Each circuit from 1 to t would output 
 a "1" and would pass on an additional carry. Circuit number 1 would pass 
 one carry. Circuit number 2 would receive that carry and would pass 
 on two carries. Finally, circuit number •_- would receive (p- - l) carries 
 and would pass on t> carries. Circuit p + 1 would receive the -z carries, 
 
14 
 
 N 
 
 use one, and pass on ^ - 1. Each of the rest of the circuits would use 
 
 one carry and pass on the rest. The maximum number of carries needed 
 m each stage is ^. 
 
 The second consideration about carries concerns the distribution 
 of the N wires. Since only N out of 2N wires can be at the "1" level, it 
 would seem that each wire has, at most, a probability of — of being ON. 
 Each circuit has two inputs, so the number of outputs it will probably have 
 to turn ON is at most 1. In a probabilistic sense, no carries at all are 
 
 needed. 
 
 N 
 The correct number is probably somewhere between none and ^, 
 
 and depends on the distribution of values of the input bundles, the amount 
 
 of circuitry that can be afforded, and the output accuracy that is desired. 
 
 For the mapping Y = 2X - 1 , the problem is more difficult. 
 
 After addition or subtraction, if Y is negative, too many wires are ON, 
 
 while if Y is positive, too few wires are ON. Each of the N combinational 
 
 circuits must decide for itself whether Y is positive or negative, and 
 
 act on that decision. Each circuit could look at all 2N input wires, 
 
 but as before, the number of logic gates required would be astronomical. 
 
 A more practical approach would again be to have each of the N circuits 
 
 look at several preceeding inputs. If the distribution of wires in the 
 
 bundles is random, a small sample of inputs should be the same value as 
 
 the total of the inputs. If each circuit looks at the previous few 
 
 inputs, say five or six, it should be able to tell the sign of the number, 
 
 and its magnitude. The actual number of inputs would depend on the 
 
 accuracy desired and the cost of the circuits. 
 
15 
 
 k. BUM - BUNDLE MACHINE 
 
 h. 1 General 
 
 A machine was built under the .guidance of Professor W. J. 
 Poppelbaum to demonstrate Bundle Processing. The machine has two 
 input bundles and performs the arithmetic operations of addition, 
 subtraction and multiplication. Each number is represented by a single 
 bundle having the mapping Y = 2X - 1. Each input is a matrix of 100 
 switches, and each input and output is displayed by two methods. The 
 logic state of each wire in each bundle is shown by a light bulb neces- 
 sitating five groups of 100 bulbs each. With the second method, the 
 number Y. is shown on a meter. A decoder is used for each bundle to cal- 
 culate Y. 
 
 4.2 Decoder 
 
 The value of a bundle depends only on the number of wires 
 which are at the "1" level. It is not concerned with which wires are 
 at a particular level. The decoder therefore, must find all wires that 
 are ON, no matter which ones they are, and determine the bundle value. 
 
 This kind of decoding problem can be solved through current sum- 
 ming. As shown in figure k.l, each wire in the bundle is terminated in 
 a resistance which in turn is connected to a node common to all other 
 resistors. 
 
16 
 
 N-l 
 
 R 
 N VW 
 
 Figure 4.1 Decoder Current Summing Network 
 
 If there are two logic levels, V and V for the "0" and "1" 
 levels respectively, and if n wires are at V , then N - n wires are at 
 V n and V can easily be found. The equivalent circuit is shown in Figure 
 
 k.2. 
 
 v, 
 
 R 
 n 
 
 -o V 
 
 R 
 N-n 
 
 Figure k.2 Equivalent Decoder Summing Network 
 
Summing currents at the node gives 
 
 17 
 
 v(# ♦ S-=3) = v,§ + v, 
 
 ^R R 
 
 IB R 
 
 V 
 
 n = n(v i - V + v a 
 
 M 
 
 V IT 1 ; C 
 
 V = An + R 
 
 0*.i) 
 
 •which is a linear function of n. An operational amplifier can supply 
 the necessary gain "A" and offset "B" to drive a meter. Figure 4.3 
 shows the type of decoder used in the machine. 
 
 IOK 
 
 100-0- 100 pQ 
 
 Z lA 200pf 
 6800pf 
 
 Figure k.3 Complete Decoder Circuit 
 
18 
 
 Early in the design of the decoder, it was felt that the 
 voltages V n and V must be very accurate in order to assure an accurate 
 decoded voltage. The Hardware Research Group has chosen some standard 
 components which it keeps in stock. Among these components is the Texas 
 Instruments SN 7^4-OON series of integrated circuits. This series was 
 investigated and was found to be adequate for the machine. 
 
 Since the decoding algorithm depends on constant values for 
 V n and V , a number of samples of several of the logic functions were 
 checked. Each output logic level voltage was found to vary as much as 
 one volt over different functions and even over different batch numbers 
 within each function. When a pull-up resistor was added to the outputs, 
 V became accurate to within 1 millivolt, but V still varied as before. 
 Of all the functions tested however, one was significantly more accurate 
 than a ll others. This one was the SN 7^+OlN which is a quad two-input 
 NAM) with open collector outputs. All circuits tested had a V of about 
 .l62v with none more than .02v from this value. For this reason, it was 
 decided that all decoder inputs would be from either the Vcc and ground 
 busses, or from the outputs from SN 7^0i-N' s « There must be one definite 
 level for V n and a different definite level for V . Having two possible 
 values for V,, for instance, would give inaccurate outputs. 
 
 Since the V output from the integrated circuits varies over a 
 range, it is necessary to determine what the effect of those variations 
 will be. Consider the circuit in Figure k.k showing the equivalent 
 circuit for a bundle with N wires, n of which are ON. 
 
19 
 
 R 
 
 V a O— MAr-f— O V 
 
 Figure k.k Equivalent Decoder Circuit 
 
 r( l + a + ■» - ° - 1 ) . T § + Vn i_-^^ + v _ 1 
 
 ^R R 
 
 R 
 
 R R 
 
 a R 
 
 To find the variation in V due to a change in V , the above equation is 
 
 SI 
 
 differentiated with respect to V . 
 
 R dV 
 
 R 
 
 dV 
 dV 
 
 a 
 
 1 
 
 N 
 
 (^3) 
 
 If the voltage on a wire is different from V "by an amount ^V, the output 
 
 aV 
 will be wrong by an amount ^r. It would seem that such accurate levels 
 
 of V, and V were perhaps not necessary after all. 
 
20 
 
 h.2> Lamp Drivers 
 
 For purposes of testing and evaluating, each wire in the five 
 major bundles (two inputs, three outputs) has a light bulb to indicate 
 when it is at the V, level. Because of the restriction that each wire 
 in the three output bundles had to come from the output of an SN 7*+01N 
 circuit, it was less expensive to invert the logic levels of the two 
 inputs. V n was set to about 5 volts while V, was at ground. Multipli- 
 cation uses coincidence circuits, so it was unaffected, while addition and 
 subtraction required inversion of each wire. Because of the difference 
 in logic types, two different bulb drives were used. 
 
 The inverting driver was used for the input bundles , and is 
 shown in Figure U.5. 
 
 INPUT 
 
 5.IK 
 
 Vcc 
 
 2NI309 
 
 (B) 6v 
 
 w 60ma 
 
 Figure k.5 Inverting Driver 
 
 When the voltage on the wire drops to V,, the bulb lights 
 
21 
 
 The noninverting driver is used for all outputs, and is in 
 Figure k.6. 
 
 75K 
 INPUT o-^wv 
 
 2NI309 
 
 60ma 
 
 Figure k.6 Noninverting Driver 
 
 Since the SN 7I+OIN can handle l6ma in the "0" state, but only 
 25ua in the "1" state, it was desired to supply current to the gate in 
 the "0" state. When the gate goes to the "1" level, no current is taken 
 by the driver. 
 
 k.k Arithmetic Unit 
 
 The three operations of addition, subtraction, and multiplication 
 are performed simultaneously by the machine. Because of the restriction 
 on the output wires, the inputs are represented in negative logic while 
 the outputs are in positive logic. 
 
 Since the multiplier uses the coincidence circuits, it is 
 unaffected by the logic change. The coincidence function is 
 
22 
 
 X = Xl x 2 v X;L x 2 
 
 Through the use of DeMorgan's theorem, this can be converted into the 
 NAND and NOR form for which gates are readily available. 
 
 X = (x 1 x 2 )(x 1 x 2 ) 
 
 = (x JL x 2 )(x 1 v x 2 ) 
 
 Figure U.7 shows the resultant circuit which terminates in a SN 71+01N. 
 
 OX 
 
 Figure h.7 Multiplier 
 
 The adder and sub tract or each use about half of the wires from 
 each bundle. Rather than using the appropriate logic on every wire and 
 then choosing half of the wires for the output, the half were selected 
 first and then the proper logic was applied only to those. The 
 remaining half are merely ignored. 
 
23 
 
 Each of the chosen wires of the adder is merely inverted using 
 the SN 7I+OIN to give the proper positive logic levels. 
 
 In the subtractor, each of the wires from the minuend bundle is 
 inverted as in the adder. Each wire from the subtrahend bundle, however, 
 is already at the correct level. Since the wires all need to terminate 
 with an SN 7U0IN gate, however, the wire is inverted twice. The adder 
 and sub tractor circuits are shown in Figure 4.8. 
 
 MINUEND 
 WMCt o- 
 
 7401 
 
 **• H^TV-^ mmmmm 
 
 ADDER SUBTRACTOR 
 
 Figure 4.8 Adder and Subtr actor Circuits 
 
2U 
 
 5- CONCLUSION 
 
 This paper has examined the method of representing numbers 
 called Bundle Processing. The second section described the system and 
 showed how the arithmetic operations of addition, subtraction, multipli- 
 cation, and division may be performed and problems with the various 
 representations. Section three described the Attrition Problem, and 
 showed that it cannot be solved with two- input combinational circuits, 
 but that it can be approximately solved by the use of interconnections 
 among the wires and their associated circuits. The fourth section 
 described BUM, a machine built to demonstrate the principles of Bundle 
 Processing. 
 
 Any electronic device which has bundles of wires would be unde- 
 sirable, particularly in aerospace application. Wires are heavy, take 
 valuable space and are subject to breakage. The development of medium 
 and large scale integrated circuits, however, could allow a practical 
 use of this system in ,at least some applications. 
 
 Further ideas about Bundle Processing are presently under 
 investigation by other members of the group. One idea is to propogate 
 any failure or break along to the result. The bundle representing the 
 result can have all failures eliminated thus assuring that the result 
 is correct. 
 
 These and many other ideas must be investigated to determine 
 Bundle Processing's place in solutions to engineering problems. 
 
25 
 
 LIST OF REFERENCES 
 
 1. Esch, J. W., "RASCEL - A Programmable Analog Computer Based On A 
 Regular Array of Stochastic Computing Element Logic", University 
 of Illinois, June 1969 . 
 
 2. Hohn, F. E., Applied Boolean Algebra , Macmillan Company, New York, 
 1966. 
 
 3. Maley, G. A. and Earle, J., The Logic Design of Transistor Digital 
 Computers, Prentice -Hall, 1963. 
 
 h. Ring, D. A., "Quarterly Technical Progress Reports", Circuit Research 
 Section, Part I, Department of Computer Science, University of 
 Illinois, January 1969 to March I969. 
 
 5. Ring, D. A., "Quarterly Technical Progress Reports", Circuit Research 
 Section, Part I, Department of Computer Science, University of 
 Illinois, April I969 to June I969. 
 
UNCLASSIFIED 
 
 Security Classification 
 
 DOCUMENT CONTROL DATA - R&D 
 
 (Security c laaailication ol title, body ot abstract and indexing annotation muat be entered when the overall report la claaellled) 
 
 I. ORIGINATING ACTIVITY (Corporate author) 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 2a. REPORT IECUHITY CLASSIFICATION 
 
 UNCLASSIFIED 
 
 2b OROUP 
 
 3 REPORT TITLE 
 
 BUM - BUNDLE PROCESSING MACHINE 
 
 4 DESCRIPTIVE NOTES (Type ol report and Inclusive, datea) 
 
 Research Report, Master's Thesis, October 1969 
 
 5 AUTHORfS.) (Last name, first name. Initial) 
 
 David A. Ring 
 
 6 REPO RT DATE 
 
 October, 1969 
 
 7a. TOTAL NO. OF PASES 
 
 27 
 
 7b. NO. OF REF3 
 
 5 
 
 8a. CONTRACT OR GRANT NO. 
 
 N000 14-67-A-0305-0007 
 
 9a. ORIGINATOR'S REPORT NUMSERfSJ 
 
 Department of Computer Science Rpt. 353 
 
 b. PROJECT NO. 
 
 9b. OTHER REPORT NO(S) (Any other numbera that may be ae signed 
 this report) 
 
 10. AVAILABILITY/LIMITATION NOTICES 
 
 Available through the Department of Computer Science, University of Illinois. 
 
 11. SUPPLEMENTARY NOTES 
 
 12- SPONSORING MILITARY ACTIVITY 
 
 Office of Naval Research 
 219 South Dearborn Street 
 Chicago, Illinois 6o60k 
 
 13. ABSTRACT 
 
 A system for representing numbers as probabilities has been investigatec 
 Under this system, called Bundle Processing, a number can be represented by the 
 percentage of wires at one of two logic levels in a group of wires. By operating 
 on all of the wires in a bundle in parallel, fast arithmetic operations can be 
 performed. A machine was built which successfully demonstrated Bundle Processing, 
 
 This work will describe and derive the equations and solution used in 
 Bundle Processing, and will demonstrate some difficulties. 
 
 %J \J 1 JAN 64 
 
 1473 
 
 0101-807-6800 
 
 UNCLASSIFIED 
 
 Security Classification 
 
UNCLASSIFIED 
 
 Security Classification 
 
 14. 
 
 KEY WORDS 
 
 LINK A 
 
 KOLK 
 
 LiNK B 
 
 NOLI 
 
 LINK C 
 
 Bundle Processing 
 Attrition Problem 
 
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 UNCLASSIFIED 
 
 Oas«««»I4-«* P1«»eeifirafiAti 
 
ICT 31 
 
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