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 SYSTEM AND CIRCUIT DESIGN OF THE TRANS FORMATRIX 
 COEFFICIENT PROCESSOR AND OUTPUT DATA CHANNEL 
 
 by 
 
 LAWRENCE D. RYAN 
 
 June, 1971 
 
 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, ILLINOIS 
 
Report No. U35 
 
 SYSTEM AND CIRCUIT DESIGN OF THE TRANS FORMATR IX 
 COEFFICIENT PROCESSOR AND OUTPUT DATA CHANNEL 
 
 by 
 
 LAWRENCE D. RYAN 
 
 June, 1971 
 
 Department of Computer Science 
 
 University of Illinois 
 
 Urbana, Illinois 61801 
 
 
 This work was supported in part by Contract Number U.S. AEC AT(ll-l) 1^+69 
 and was submitted in partial fulfillment of the requirements for the degree 
 of Doctor of Philosophy in Electrical Engineering at the University of 
 Illinois, June, 1971. 
 
SYSTEM AND CIRCUIT DESIGN OF THE TRANS FORMATRIX 
 COEFFICIENT PROCESSOR AND OUTPUT DATA CHANNEL 
 
 Lawrence David Ryan, Ph.D. 
 Department of Electrical Engineering 
 University of Illinois at Urb ana- Champaign, 1971 
 
 Trans formatrix, as originally conceived "by Professor W. J. Poppelbaum, 
 
 is a special purpose graphical processor which transforms an input picture 
 
 represented by 32 x 32 light intensities x. . (i,j = 0,1,., ,,31) into an output 
 
 display of 32 x 32 light intensities y »(k^= 0,1,..., 31) in such a fashion 
 
 that each one of the y k /?'s is equal to a weighted linear combination of all 
 
 the x. .'s. This corresponds to: 
 
 31 
 
 y ]stf "ijjsO b Uij X ij 
 In the preceeding equation the b n. . 's are, in general, complex coefficients 
 which are fixed for a given transformation. If y,„ is complex, then any 
 one of {|y k Jj |Re[y „]|, |lm[y *]|}is displayed on a CRT. 
 
 Three specific applications of the general linear transformation are 
 implemented with hardware in the Trans formatrix system. They are the 
 two-dimensional discrete Fourier Transform of the input picture, an Array 
 Transform in which a 5 x 5 subset of each 32 x 32 coefficient frame is 
 selected under operator control, and the Coordinate Transform which involves 
 translation, magnification, and rotation of the input picture „ The 
 second operation Includes as applications certain types of pattern recognition 
 and image enhancement. 
 
 Each of the operations performed by Transformatrix requires special 
 circuitry to generate the appropriate coefficients. The more important 
 
circuits and design principles are covered in this thesis in addition 
 
 to an analysis of an inexpensive five bit D/A converter. A total of 
 
 1,02U of the D/A converters are used to transform the (digital) coefficients 
 
 a frame at a time into their analog equivalents prior to conversion 
 
 to Synchronous Random Pulse Sequences (SRPS's). 
 
 Following stochastic multiplication of the two sets of 1,024 SRPS's, 
 the product SRPS's are summed in an analog manner, integrated and the 
 result manipulated to form the z-axis drive signal for each output light 
 intensity. This portion of the thesis describes the circuitry required 
 to perform all the analog processing subsequent to the stochastic multiplica- 
 tion. 
 
Ill 
 ACKNOWLEDGMENT 
 
 The author wishes to express his gratitude to Professor 
 W. J. PoppeTbaum for suggesting this thesis topic and for his 
 continued friendship, guidance, and support. He is also grateful 
 to his co-workers, Yiu Wo and Orin Marvel, who designed and built 
 part of the Trans forraatrix system. 
 
 The author is indebted to all the men in the fabrication 
 group and machine shop under Frank Serio for the considerable amount 
 of work they contributed toward the building of Transformatrix. 
 Special mention goes to Jerry Fiscus who did an excellent job on 
 some rather difficult printed circuit board layouts. 
 
 All of the part-time student technicians, Rick rtawachi, 
 Ron Klohr, Craig Luebs, Jerry Menchhoff, and Mike Selander, who 
 worked on the Transformatrix project at various times during 
 the past three years, are thanked for their help. 
 
 Thanks are also due Carla Donaldson for typing the thesis, 
 Fred Hancock and Wes Gibbs for drafting the figures, Art Simons 
 for seeing to the details of the printing of the thesis, and 
 Dennis Reed for the actual printing of the thesis. 
 
 Most importantly, the author thanks his wife, Anne, for 
 typing the first draft of the thesis and for her support and 
 encouragement throughout this project and his daughter, Erin, 
 for making the past year more enjoyable. 
 
IV 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION . 1 
 
 1.1 The Trans formatrix Concept , . . . . 1 
 
 1.2 Scope of Thesis . . . . . . 2 
 
 1.2.1 System and Circuit Design of the 
 
 Coefficient Processor , . , 2 
 
 1.2.2 System and Circuit Design of the 
 
 Output Data Channel 2 
 
 2. SYSTEM CONSIDERATIONS 3 
 
 2.1 Method of Computation . . ............ 3 
 
 2.2 Trans formatrix Block Diagram . . h 
 
 2»3 Generation of the 1?., „. . Coefficients . . . . . 6 
 
 2.k Control Signals for the Coefficient Processor 
 
 and Output Data Channel „ , , . 7 
 
 2.5 Trans formatrix Operations 8 
 
 3. TWO-DIMENSIONAL DISCRETE FOURIER TRANSFORM . . . . 9 
 
 3.1 Fourier Transform Equations 10 
 
 3.2 Generation of the Fourier Coefficients . . . . 13 
 
 3.3 Fourier Transform Logic Design . 16 
 
 3. 3«1 Five Bit Adder and Associated Interface Logic ... 16 
 
 3-3-2 Five Bit Diode Encoder 19 
 
 k. ARRAY TRANSFORM . 23 
 
 k,l Applications of the Array Transform , , , . . 23 
 
 4.1.1 Pattern Recognition 23 
 
 4.1.2 Smoothing High Contrast Input Pictures . . . . . . . 26 
 
 k.2 Array Transform Equations 28 
 
 4.3 Array Transform Block Diagram ......... 29 
 
 k.k Array Transform Logic Deisgn 33 
 
Page 
 
 5. COORDINATE TRANSFORM , . 37 
 
 5.1 Coordinate Transform Equations . 37 
 
 5.2 Coordinate Transform Block Diagram ....... 38 
 
 5.3 General Circuit Considerations 44 
 
 5.3.1 Five Bit Bipolar D/A Converter 44 
 
 5.3*2 Coordinate Transform Circuitry . „ . . „ 46 
 
 5.3.3 Five Bit A/D Converter 49 
 
 6. COEFFICIENT STORAGE AND D/A CONVERSION 52 
 
 6.1 General Design Considerations 52 
 
 6.2 Determination of Weighted Resistor Values , 56 
 
 6.3 Analog Reference Regulator „ . . . 66 
 
 6.h Coefficient QRAS Driver 66 
 
 7. OUTPUT DATA CHANNEL . . . . . 70 
 
 7-1 Output Data Channel Block Diagram . . . . 70 
 
 7»2 Output Data Channel Circuitry ..... 73 
 
 7.2.1 Multiplication and Summation of Coefficient and 
 
 Input Light Intensity SRPS's . . . 73 
 
 7.2.2 Differential Amplifier Buffer 75 
 
 7.2.3 Thirty- Two Input Integrator 75 
 
 7.2.4 Output Circuit-First Stage ....... 77 
 
 7.2.5 Sample and Hold 80 
 
 7.2.6 Output Circuit - Sense Stage 82 
 
 7.2.7 Output Circuit - Second Stage 82 
 
 7.2.8 Output Circuit - Third Stage ............ 85 
 
 8. EXPERIMENTAL RESULTS AND CONCLUSIONS 87 
 
 8. 1 Experimental Results 87 
 
 8.2 Conclusions 90 
 
 APPENDIX 91 
 
 LIST OF REFERENCES 95 
 
 VITA 97 
 
VI 
 
 LIST OF FIGURES 
 
 Figure Page 
 
 2.1 Trans formatrix Block Diagram ........ 5 
 
 3-1 Fourier Transform Block Diagram . „ . 14 
 
 3.2 Five Bit Adder . . . 17 
 
 3.3 Five Bit Adder Interface Logic 18 
 
 3.4 Five Bit Diode Encoder ........ 20 
 
 4.1 Position of 5 x 5 Array of Coefficients Within (k,i) 
 
 Coefficient Frame 24 
 
 4.2(a) Selection of Coefficients for Detecting the Letter 'E' . . . 25 
 
 (b) Output Pattern That Results from Input Pattern and 
 
 Coefficient Array Given in Figure 4.2(a) ... 25 
 
 4.3 One Possible Coefficient Array for 'Smoothing' High Contrast 
 Input Pictures „ . . . . 27 
 
 4.4 Array Transform Block Diagram „ „ 30 
 
 4.5 Wiring of Rotary Switch to Implement Coefficient Mapping . . 34 
 5.1 Pictorial Representation of the Coordinate Transform .... 39 
 5«2 Example of Horizontal and Vertical Translation . 40 
 
 5.3 Coordinate Transform Block Diagram 4l 
 
 5.4 Five Bit Bipolar D/A Converter 45 
 
 5-5 Schematic of Coordinate Transform Circuitry . . 47 
 
 5.6 Five Bit A/D Converter . 50 
 
 6.1 Coefficient Storage Register and D/A Converter 54 
 
 6.2 Physical Layout of Coefficient Storage and 
 
 D/A Conversion Board 57 
 
 6.3 Photograph Showing Coefficient Storage and 
 
 D/A Conversion Board in Its Tester „ . . 58 
 
 6.4 Circuit Used for Determination of Ladder Resistors 59 
 
V1X 
 
 Figure Page 
 
 6.5 First Half of Computer Program Used to Determine 
 
 Ladder Resistors . . . „ 63 
 
 6.6 Second Half of Computer Program Used to Determine 
 
 Ladder Resistors „ „ 6h 
 
 6.7 Printout of Final Results of Ladder Resistor Computer 
 
 Program . ,.,..„...„... 65 
 
 6.8 Analog Reference Regulator for Hex Inverter Buffers ...» 67 
 
 6.9 Coefficient QRAS Driver 68 
 
 7.1 Output Data Channel Block Diagram . „ „ . . . . . „ , . . . 71 
 
 7.2 Multiplication and Summation of Coefficient and 
 
 Input Light Intensity SRPS's . . . 7^ 
 
 7.3 Differential Amplifier Buffer . 76 
 
 "J.k Thirty- Two Input Integrator „ . „ 78 
 
 7.5 Output Circuit - First Stage 79 
 
 7.6 Sample and Hold 8l 
 
 7.7 Output Circuit - Sense Stage 83 
 
 7.8 Output Circuit - Second Stage Qh 
 
 7.9 Output Circuit - Third Stage 86 
 
 8.1 Front View of Trans formatrix System - Panels Removed .... 88 
 
 8.2 Back View of Trans formatrix System 89 
 
1. INTRODUCTION 
 
 1.1 The Transformatrix Concept 
 
 A well known technique for increasing the overall speed of a 
 computing system is to operate simultaneously on more than one set of input 
 data. One method of doing this involves the use of multiple arithmetic 
 units. J ' In this configuration an array of identical arithmetic units 
 
 operates on possibly different pieces of input data at the same time. Parallel 
 computers of this type generally have the property that the sophistication 
 (and thereby cost) of the arithmetic unit is directly related to the variety 
 of problems allowed. The more general the class of input data on which the 
 machine can operate efficiently, the more complex the arithmetic unit has to 
 be. 
 
 The Transformatrix system, as conceived by Professor W. J. 
 Poppelbaum, is a highly parallel (1,024 arithmetic units) graphical 
 processor which operates on a large class of input data (any two-dimensional 
 shade of grey picture) at a reasonably low cost per computational channel 
 (less than $20 worth of components per channel) » The input picture, which 
 may be a commercial TV broadcast, a video tape recording, any picture 
 provided by an external TV camera, or a 35mm slide, is projected by a TV 
 receiver onto an array of 32 x 32 photoconductors. The output of each 
 photoconductor is converted into a Synchronous Random Pulse Sequence (see 
 Appendix)*. The output picture is a 32 x 32 matrix of light intensities 
 displayed on a CRT. Each output light intensity is formed by multiplying 
 
 *The interested reader is directed to reference (5) for a detailed analysis 
 of the TV-photoconductor subsystem and the generation of SRPS's for 
 Transformatrix. 
 
the array of 1,024 input light intensity SRPS's pairwise times a frame of 
 1,024 coefficient SRPS's. The products are summed and normalized to produce 
 a single output light intensity. Different coefficient frames are used for 
 different output points. The type of linear transform desired determines the 
 contents of the 1,024 coefficient frames > Some of the operations encompassed 
 by this general linear transformation are transformation of coordinates, 
 spatial filtering, picture enhancement, cross-correlation, two-dimensional 
 Fourier transform, certain types of pattern recognition, convolution, 
 diffraction pattern form factors, and matrix manipulation » 
 
 1.2 Scope of Thesis 
 
 The research project upon which this thesis is based may be 
 conveniently divided into two parts . 
 
 1.2.1 System and Circuit Design of the Coefficient Processor 
 
 Each of the operations performed by Trans formatrix requires special 
 circuitry to generate the appropriate coefficients. The more important 
 circuits and design principles are covered in this thesis in addition to an 
 analysis of an inexpensive five bit D/A converter. A total of 1,024 of the 
 D/A converters are used to transform the (digital) coefficients a frame at a 
 time into their analog equivalents prior to conversion to SRPS's. 
 
 1.2.2 System and Circuit Design of the Output Data Channel 
 
 Following stochastic multiplication of the two sets of 1,024 SRPS's, 
 the product SRPS's are summed in an analog manner, integrated and the result 
 manipulated to form the z-axis drive signal for each output light intensity. 
 This portion of the thesis describes the circuitry required to perform all the 
 analog processing subsequent to the stochastic multiplication. 
 
2. SYSTEM CONSIDERATIONS 
 
 Trans format rix is a special purpose graphical processor which trans- 
 forms an input picture represented by 32 x 32 light intensities x. . 
 (i,j = 0,1, . . o, 31) into an output display of 32 x 32 light intensities 
 y . (k,i - 0,1, . o ., 31) in such a fashion that each one of the y 's is 
 equal to a weighted linear combination of all the x. .'s. This corresponds 
 to: 
 
 31 
 y „ = Z b. .. .x. . (2.1) 
 
 - 1 - j j — ^ 
 
 In the preceeding equation the b . . .'s are, in general, complex coefficients 
 which are fixed for a given trans formation . Clearly, if y . is complex, then 
 one or more of [|y J, |Re[y „]|, |lm[y ]|} may be displayed (on a CRT). 
 
 2.1 Method of Computation 
 
 In order to have a flicker-free output display, the y 's are 
 calculated at a rate of 30 frames per second. This means that, each y . is 
 determined in approximately 32.51-LSo Referring to equation (2.1) reveals that 
 1,024 separate multiplications must be performed and the resulting products 
 summed in order to form each y Q . The large number of multiplications required 
 to determine each y . is naturally suited to stochastic computing methods 
 (see Appendix). If we represent the input signals x. . and the coefficients 
 b , . . by Synchronous Random Pulse Sequences (SRPS's), then each product 
 b n .x. ., with (k,i) constant, can be formed with a single digital AND gate. 
 Thus, 1,024 AND's are required to form the 1,024 products. 
 
4 
 
 It is not advantageous to sum the 1,024- products in a stochastic 
 manner. The large number of products and dependence among the products would 
 necessitate many summers in addition to high order compensation. Summing the 
 products in an analog manner is the logical alternative. The analog sum of 
 the 1,024 product SRPS's is integrated over 25.5M-S (allowing 7|J.s for the 
 generation of the 1,024 coefficients for that particular output point) and 
 normalized to yield y. g . 
 
 With a clock rate of 10 MHz and an integration interval of 25 . 5M-S , 
 the average 2 a variance of y g is 4.92% of the full scale value. 
 
 2o 2 Transformatrix Block Diagram 
 
 A block diagram of Transformatrix is shown in Figure 2.1. The 
 photo-matrix consists of a 32 x 32 array of photoconductors which senses the 
 light intensity from a 5" TV receiver and produces voltages proportional to 
 the light intensity. The comparators, C . ., compare the voltages produced by 
 the photo-matrix to the random noise levels on bus 1. The comparators output 
 a pulse whenever x. . > random noise level. Thus the output of C . . is the 
 SRPS representing x. .. 
 
 The coefficient matrix is composed of 1,024 five bit storage 
 registers feeding 1,024 five bit D/A converters. For each (k,j2) the 
 
 coefficients, b n „ . ., are entered into the storage registers and converted into 
 
 2 
 analog voltages. A second set of comparators, C . ., compares the voltage 
 
 levels from the coefficient matrix to the random noise levels on bus 2. The 
 
 comparators output a pulse if b, „ . . < random noise level. Then the output of 
 
 kiij 
 
 2 
 C . . is the SRPS representing b . . . . 
 
hS 3 c 
 
 CO 
 
 cO 
 ■H 
 P 
 
 -y 
 o 
 o 
 
 rH 
 
 pq 
 x 
 
 •H 
 
 -P 
 
 CO 
 
 S 
 U 
 
 o 
 a 
 
 cO 
 
 u 
 
 EH 
 
 rH 
 
 a) 
 
 P-4 
 
1 2 
 For all 1,024- values of (i,j), the outputs of C . . and C . are 
 
 ANDed together (their SRPS's are multiplied), the 1,024 product SRPS's are 
 
 summed and then integrated. The normalized result, y , is displayed on the 
 
 output CRT at position (k.,£). 
 
 Once the input light intensities have been converted to SRPS's, it 
 
 is relatively easy to digitally gate individual intensity SRPS's onto a common 
 
 (5) 
 bus with an AND -OR combination. Thus, with a small increase in hardware, 
 
 the input picture, as 'seen' by the photoconductors, can be displayed on a 
 
 second CRT. 
 
 2.3 Generation of the b, „. . Coefficients 
 kjij 
 
 In the Transformatrix system the determination of each output light 
 intensity, y „ , within a j2.5us timing cycle requires that 1,024 coefficients, 
 b n .. . (i,j = 0,1, . . ., 31). be made available to the stochastic multipliers 
 (AND gates) within 7 us of the start of the cycle. Several methods of 
 obtaining these coefficients were investigated. 
 
 Storage of all (32) = 1,048,576 coefficients for each of the three 
 operations was rejected not only because memory access time for a frame of 
 1,024 coefficients is short but in addition the maximum number of unique 
 coefficients describing the three operations is only 17 (Fourier Transform). 
 It seemed likely that use could be made of the redundancy among the 
 coefficients. One approach along these lines would be to have all the unique 
 coefficients available (either as digital words or their corresponding SRPS's) 
 and direct them to the appropriate stochastic multipliers by combinatorial 
 circuitry. This method is suitable for the Coordinate Transform and Array 
 Transform (where a maximum of 25 coefficients per output point is non-zero) 
 but cumbersome for the Fourier Transform (where most of the coefficients are 
 
7 
 
 non-zero). However, by making use of some of the properties of the Fourier 
 Transform, it is possible to generate the Fourier coefficients on-line as 
 they are needed. Thus by a combination of selection circuitry (Coordinate 
 Transform and Array Transform) and on-line special purpose calculators 
 (Fourier Transform), the appropriate coefficients are presented to the 
 stochastic multipliers within the required time and at reasonable cost. 
 
 2.k Control Signals for the Coefficient Processor and Output Data Channel 
 Most of the circuits in the Coefficient Processor and the Output 
 Data Channel which require timing pulses for control purposes do so during 
 either the first or last several microseconds of each 32.5M-S cycle. A 
 convenient way of obtaining the necessary control signals is to have the 
 appropriate outputs of the nine bit 32. 5 US synchronous counter feed a series 
 of decoders . 
 
 With a 32.5M-S basic computational cycle and a 10 MHz system clock, 
 the 100ns clock periods may be numbered from to 32^. Using ten Fair child 
 9311 one out of sixteen decoders, the clock cycles from through 79 and 256 
 through 32^4 are decoded and made available for use as control signals. To 
 prevent glitches from appearing in the decoder outputs the 9311 ' s are strobed 
 by the system clock resulting in ~50ns wide control signals. 
 
 Generating the timing pulses in this manner makes for a flexible 
 system design. The time relationships among any group of control signals used 
 in the Coefficient Processor and Output Data Channel may be easily changed by 
 a small amount of rewiring. 
 
2.5 Trans format rix Operations 
 
 Three specific applications of the general linear transformation 
 are implemented with hardware in the Trans formatrix system. They are the 
 two-dimensional discrete Fourier Transform of the input picture, an Array 
 Transform in which a 5 x 5 subset of each 32 x 32 coefficient frame is 
 selected under operator control, and the Coordinate Transform which involves 
 translation, magnification, and rotation of the input picture. The second 
 operation includes as applications certain types of pattern recognition and 
 image enhancement. 
 
 In addition to the three basic operations listed above, it is also 
 possible to perform any one of four mathematical operations on each output 
 light intensity. The operator may select from among the following modes: 
 linear, log, square, and square root. In each of these modes, Trans formatrix 
 is additionally capable of producing the negative of the output picture. 
 
 It should be emphasized at this point that all of the operations 
 described above are performed on-line with respect to the data rate of a 
 standard television input picture. 
 
 The system and circuit design pertinent to the three Transformatrix 
 operations and the output data channel are covered in the following chapters. 
 
 
3. TWO-DIMENSIONAL DISCRETE FOURIER TRANSFORM 
 
 The two-dimensional Fourier Transform has found numerous applications 
 in the area of picture processing. Based on the idea that some noise in 
 television picture transmission is periodic, some authors have used the 
 
 properties of the two-dimensional Fourier Transform to filter the periodic 
 
 (7) 
 noise out of the incoming picture. Another avenue of interest involves the 
 
 use of the two-dimensional Fourier Transform to compress the bandwidth required 
 
 / O \ 
 
 to transmit television pictures. A more direct application of the two- 
 dimensional Fourier Transform is to detect periodicities in a picture 
 (periodicities which in the unaltered original picture may not be apparent to 
 the eye). Because of the wide variety of applications of the two-dimensional 
 (on-line) Fourier Transform and since it would push the capabilities of the 
 Trans formatrix system to the ultimate (most of the b, „. . Fourier coefficients 
 are non-zero), it was decided to implement the two-dimensional discrete Fourier 
 Transform in Trans formatrix. 
 
 Several authors '' have described special purpose digital FFT 
 (Fast Fourier Transform) processors specificly designed to take advantage of 
 certain properties of the Fourier Transform. In this way the time required to 
 calculate Fourier Transforms has been reduced considerably. However, the 
 structure of the Trans formatrix system, a hardware implementation of the 
 general linear transformation, precludes special hardware modifications 
 designed to enhance the speed of the Fourier Transform operation. In the 
 Trans formatrix system the 10 to 100- fold increase in speed of the Fourier 
 Transform operation over conventional digital computers is due solely to the 
 high degree of parallelism employed (1,02^4 arithmetic units). 
 
10 
 
 To better understand the system design of the Fourier coefficient 
 generator, it is helpful to develop some of the mathematical properties of 
 the two-dimensional discrete Fourier Transform. 
 
 3.1 Fourier Transform Equations 
 
 Let f(ijj) be the doubly periodic extension of a discrete input 
 pattern, x. ., such that: 
 
 f(i,j) = x ± . } i,j =0,1, . . ., N-l (3-1) 
 
 f(i + pN, j + qN) = x i,j = 0,1, . . ., N-l (3.2) 
 
 x v p,q integers 
 
 We may then define a truncated Fourier series for the two-dimensional discrete 
 function f(i,j) in the following manner: ' 
 
 N-l 
 f(i,j) =7; 2 F(kJ) exp[2*i(ki +ij)/N], i,j =0,1, . . ., N-l (3-3) 
 ^ k,i=0 
 N-l 
 F(M) = - Z f(i,j) exp[-2fii(ki + ij)/N], kj = 0,1, . . ., N-l (3.*0 
 i/j=0 
 
 That expressions (3*3) and (3.^-) do indeed form a Fourier Transform pair can 
 be readily verified with the aid of the orthogonality relationships for the 
 exponential function. 
 
 Transformatrix is capable of realizing equation (3«^)j a two- 
 dimensional discrete Fourier Transform, with N = 32 » Since F(k,i) is in 
 general a complex quantity, Transformatrix displays any one of the three 
 functions [F(k,i)|, |Re[F(k,i ) ] I , I Im[F(k,i ) ] I . 
 
11 
 
 A closer examination of equation (3«^+) proves useful in generating 
 the Fourier coefficients. Through direct use of (3»*0 we see that: 
 
 F(k,i)* = F(32 - k, 32 - i) (3.5) 
 
 where F(k,i)* is the complex conjugate of F(k,i). Thus, for each output frame 
 
 1 2 
 of F(k,i) values that are to be calculated, only —[(32) + k] - 51^ unique 
 
 values need be determined with the other 510 values obtained through the use 
 
 of (3»5)« This reduces the computation time by almost one-half. 
 
 From equation (3.^) "we have for Re[F(k,^)] and Im[F(k,i)]: 
 
 31 
 
 Re[F(k,i)] =4 2 x..cos2 J t( ki _ + p ij ) (3.6) 
 
 id i,j=0 1J ^ 
 
 Im[F(k,i)] = - i Z * Binat f 1 ^ ) (3.7) 
 
 32 ijJ=0 xj 32 
 
 In order to obtain |F(k,i)|, |Re[F(k,^)] | , and |lm[F(k,i)]| for each (k,i), 
 the Transformatrix Coefficient Processor must be able to provide the SRPS's 
 
 which represent cos2jt( tx — ~) and -sin2jt( r-p — -). Since the cosine and sine 
 
 functions vary between -1 and +1, a mapping is required. The type of mapping 
 that is used is: 
 
 P cos (ki + id) - |[1 - cos2«(^ii)] (3.8) 
 
 where < P (ki + ij ) < 1 
 — cos — 
 
12 
 
 p . (ki + Ij) is obtained by incrementing the argument of cos2rt( J 
 
 '-sin 
 it/2 
 
 32 
 
 by 
 
 P_ sin (ki + ij) = |[1 - cos2 J t( ki + 3g ij + 8 )] 
 
 where < P . (ki + i/j ) < 1 
 
 (3.9) 
 
 Multiplying the SRPS which represents x. . by the SRPS's which 
 
 represent P (ki + £ j ) and P . (ki + ij ) and summing (in an analog manner 
 -c- cos -sm^ 
 
 over all (i,j) we obtain: 
 
 31 
 Re[P'(M)] = -h z ^i^ 1 " cos2rt( ki + ij )]} 
 ^ 1,3*0 1J J 
 
 = \ F(0,0) - I He[F(M)] 
 
 (3.10: 
 
 Im[F'(k,i)] 
 
 31 
 - 4 2 x. {i[l + sin2,t( ki + ij )]} 
 
 « I F(0,0) - I Im[F(k,i)] 
 
 (3.11) 
 
 The quantity F(0,0) represents the average intensity of the input pattern. 
 Thus, for each (k,i) we have the result: 
 
 Re[F(k,i)] = 2{F(0,0)/2 - Re[F'(k,i)]} 
 Im[F(k,i)] = 2{F(0,0)/2 - Im[F'(k,i)]} 
 
 (3.12) 
 (3.13) 
 
13 
 
 When computing |F(k,i)| or | Im[F(k,i)] | , F(0,0)/2 is determined on 
 the (k,i) = (0,0) cycle from the relation: 
 
 F(0,0)/2 = Im[F'(0,0)] (3.IU) 
 
 The calculation of |Re[F(k,i)]| requires that all the b n .. . coefficients be set 
 equal to 11111 on the (k,i) = (0,0) cycle. The resulting integral of the sum 
 of products b . . .x. . is sampled half-way through the (0,0) cycle to yield 
 F(0,0)/2. 
 
 The quantity F(0,0)/2 is recalculated every output frame 
 (approximately 33kis per frame), stored for that frame, and subtracted from 
 each succeeding calculation (Re[F'(k,^)] and/or Im[F'(k,^)]) to yield the 
 desired result (|F(k,i)|, |Re [F(k,i ) ] | , or | Im[F(k,i ) ] | ) . 
 
 3.2 Generation of the Fourier Coefficients 
 
 Reviewing the equations in section 3»1 it is seen that the crux of 
 
 the problem is the generation of the coefficients, P (ki + ij ) and 
 
 P . (ki + Hi ) , as SRPS's. A block diagram of the subsystem which generates 
 -sin ' 
 
 the Fourier coefficients is found in Figure 3-«l« As indicated in Figure 3«1 5 
 there is one five bit adder for each column of coefficients. Because of the 
 periodicity of the cosine and sine functions, we are only interested in 
 (ki + ij) modulo 32 . 
 
 For a particular output point and a fixed column of coefficients, 
 
 the indices k, i, and i are constant. Assume that (ki) is entered into the 
 
 th 
 R. input register of the i adder „ The encoder converts (ki + £j)^ Q into 
 
 P (ki + £ j ) . Thus P (ki) is entered into the j = five bit register 
 cos ' cos 
 
 of column i(R. _). The number (ki)^^ remains as one of the inputs to the 
 
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 O 
 
 -I 
 < 
 
 o 
 
 z 
 
 UJ 
 
 3 
 
 o 
 a: 
 
 < 
 
 ro 
 
 ii ^ 
 
 o 
 
 TT 
 
 I | 
 
 *•■"■* 
 
 M» « 
 
 
 *< 
 
 N 
 
 + 
 
 K> 
 
 2 
 
 
 a. 
 
 «— ^ 
 
 3 
 
 N 
 
 1 
 
 CM 
 
 ^ 
 
 
 O 
 
 to 
 
 o 
 
 O 
 
 _l 
 
 t 
 
 J 
 
 >»v. 
 
 en 
 
 UJ 
 
 ui _ 
 
 JU. 
 
 o 
 
 <r 
 
 C\JO 
 
 rou. 
 
 UJ 
 
 -I 
 CD 
 < 
 
 I- 
 
 -|M 
 
 l-O 
 
 OC 
 UJ 
 
 I- 
 
 tO 
 
 e> 
 ui 
 
 a: 
 
 OD 
 
 I 
 
 m 
 
 CM 
 
 o 
 
 CC 
 
 PI 
 
 t; 
 
 IX) 
 
 L 
 
 IX) 
 
 o 
 cc 
 
 ^ 
 
 |XJ 
 
 C/> 
 
 oc 
 
 o 
 o 
 
 CO 
 
 I 
 
 m 
 
 CVJ 
 
 o 
 
 to 
 CC 
 
 IX) 
 
 m 
 CC 
 
 r. 
 
 IX) 
 
 o 
 or 
 
 T- 
 
 IX) 
 
 bO 
 erf 
 •H 
 P 
 
 ^ 
 o 
 
 o 
 
 rH 
 
 d 
 
 o 
 
 H 
 
 EH 
 
 fH 
 CO 
 
 ■H 
 
 
 
 (in 
 
 a) 
 
 u 
 3 
 
 ■H 
 
15 
 
 adder. The common register contains &. Thus the output of the adder is 
 
 (ki + |) and this number is clocked into the register R. . The encoder 
 
 generates P (ki + i) which is entered into register R. n . This process 
 cos 1,1 
 
 continues (with one input to the adder equal to $, and the other input equal 
 to the previous output) up to j = 31 for all 32 columns. The resulting five 
 bit binary numbers stored in the 1,024 registers feed 1,024 D/A converters. 
 The output of each D/A is compared with a Quantized Random Analog Signal 
 
 (ORAS) which is generated by putting five bits of a feedback shift register 
 
 (5) 
 into a D/A converter. ' The output of each comparator is a SRPS representing 
 
 P (ki + i). Recall that P . (ki + ij ) is obtained by initializing the R. 
 cos v ' -sm^ **' J & 1 
 
 input registers of all the adders with a binary 8. 
 
 P (ki + id) = P(ki + Jj + 8) (3.15) 
 
 While the product SRPS's corresponding to output point (k,i) are 
 being summed and integrated, a separate five bit adder is used to generate 
 the j = row of cosine arguments 0, kl, k2, . . „, ki, . . ., k30, k31 (add 
 8 for sine arguments). These five bit words are gated into the input 
 register of the appropriate adder (ki -» R. , etc.) prior to the start of a new 
 cycle. 
 
 To allow for differences in logic delay times in the 32 Fourier 
 coefficient calculators and in the row addressing circuitry, a full 200ns is 
 allowed for the calculation and gating into the storage registers of one row 
 of coefficients. For the Fourier Transform this results in a time of 6.h[xs 
 for the calculation and storage of 1,024 five bit coefficients. Including 
 100ns for resetting the storage registers each cycle and . 500ns for the D/A 
 converters to settle to within + - LSB, 7us out of each 32.5us period is used 
 in generating the Fourier SRPS coefficients. 
 
16 
 
 Since almost — of the output values of the Re[F(k,i)] and Im[F(k,i)] 
 are redundant, by using equation (3*5) the cycle time can be doubled to 65 us 
 when performing either of these two operations. This gives more than double 
 the integration time and hence a more accurate result. 
 
 3.3 Fourier Transform Logic Design 
 
 The details of the logic which is reproduced 32 times to implement 
 the Fourier Transform coefficient generator are given in the folio-wing two 
 sections . 
 
 3«3»1 Five Bit Adder and Associated Interface Logic 
 
 The complete logic diagram of the five bit adder is given in 
 Figure 3-2. The adder features a look-ahead carry design and a worse case 
 input to output delay of 3Ctos. Since the adders operate in the system at 
 5 MHz their speed is more than adequate. 
 
 The interface logic of the five bit adder is shown in complete detail 
 in Figure 3«3» The Clock, Set and Inhibit signals are common to all 32 adders. 
 The g. and Clear, signals are unique to each adder. Since the subsequent 
 circuitry (the five bit diode encoder) is fed by the five bit adder register, 
 it is convenient to leave the Inhibit tied to a logical for all operations. 
 In the Fourier Transform mode of operation the Set inputs originate 
 from the outputs of the separate adder which generates the j = row of 
 cosine arguments 0, kl, k2, . . ., ki, . . ., k30, k31 (add 8 for sine 
 arguments). The values {ki} or {ki +8} are entered into the correct adder 
 register by pulsing the g. lines in synchronism with the clock which toggles 
 the separate adder register. 
 
 
17 
 
 a- T ^ 9 a. 
 i " i i i 
 
 8i lig 
 
 I X I I g 
 
 *3" Tj" ^t t O 
 
 P. p £ S n 
 z z z z u 
 
 to u) in <n 2 
 
 !n — — S <m 
 
 0) 
 
 < 
 
 -P 
 •H 
 
 PQ 
 
 (P 
 !> 
 
 •H 
 
 CM 
 CD 
 
 •H 
 
 l< O- 
 
 l-3> 
 
££> 
 
 i^> 
 
 x=o 
 
 ^> 
 
 fcO 
 
 £ 
 
 n>Hit 
 
 ^t> 
 
 ^CHS 
 
 (O 
 
 ^O 
 
 ^> 
 
 € S>0 
 
 i< 
 
 ^=o 
 
 aA6 
 
 i* 
 
 i< 
 
 las 
 
 l< 
 
 H 
 
 lea 
 
 ICO 
 
 
 o 
 
 o_j Si 
 
 18 
 
 ■a-** 
 
 - j"otJ > V 
 
 ce 
 a id 
 
 z a. 5 
 
 22 
 
 z z 
 
 Q _l 
 
 o 5 
 
 z z 
 
 in vt 
 
 ♦ — ro 
 
 O 
 ■H 
 
 M 
 
 i-5 
 
 0) 
 
 u 
 
 erf 
 
 In 
 CD 
 
 OJ 
 
 < 
 •H 
 
 pq 
 
 > 
 •H 
 
 no 
 
 •H 
 
19 
 
 The remaining 1,024 - 32 - 992 coefficients are subsequently 
 obtained a row at a time by having the Adder Clock under go 31 -* 1 
 transitions. The 32 row gating lines are sequentially pulsed in synchronism 
 with the Adder Clock signal. 
 
 3.3.2 Five Bit Diode Encoder 
 
 A critical part of the Fourier Transform coefficient generation is 
 the implementation of the mapping given by equation (3»8). This type of 
 operation is tailor made for a ROM (Read Only Memory). Although ROM's on a 
 single chip with fast enough access time (of the order of 75ns) are becoming 
 available, they could not be obtained when this portion of the system was 
 being designed. For this reason the five bit diode encoder illustrated in 
 Figure 3.4 was designed to implement equation (3.8). 
 
 For any stable five bit input, A, one out of the 32 decoder outputs 
 is a logical and the other 31 are logical l's. The input of each of the 
 SN74H40N NAM) drivers which is connected to the logical decoder output 
 through a diode acts as a logical to that NAM) causing its output to go to 
 a logical 1. If none of the inputs of a NAND driver is connected to the 
 logical decoder output through a diode then these inputs are a logical 1 and 
 the NAM) output is a logical 0. It is clear that any arbitrary many-to-one 
 mapping may be obtained by the appropriate arrangement of the diodes. To 
 obtain the Fourier Transform coefficients, equation (3«8) was implemented with 
 the diodes. 
 
 Table 3.1 summarizes the steps required to determine the placement 
 of the diodes on the encoder card. The desired coefficients, as a function 
 of the argument, A, are determined from equation (3.8) (where A = (ki + £j). 
 
 32' 
 
 Since the calculated coefficients are five bits wide, the nearest available 
 
A 
 
 A 
 
 AAAAAi 
 
 20 
 
 
 AAA 
 
 <HD- 
 
 «>-«r 
 
 <?>- 
 
 10 \__ m 
 < /^ < 
 
 ! tt> 
 
 a i * 
 
 ■AAA 
 
 i— W— ■ I — KH 
 
 r— W— • 
 
 N N ~ 
 AAA 
 
 f— W-'f— W—' [— W-.i r— W- r— |fr-«. 
 
 AAA 
 
 i— W-> r— «-<> i— W— i— «-' 
 
 i— W— > r— KH' r— W— 
 
 9 S * 
 
 if 
 
 Jla 
 
 -J 5? 
 
 + 
 
 > if 
 
 r— «— ■ 
 
 
 i— «— ■ I — W-" 
 
 2* 5 -♦ IS 
 
 | — H— j — KJ-" I — <H' 
 
 u^j^:: 
 
 |— W—' | — W~" I — «J— r— W— • 
 
 *♦ 
 
 2# 
 
 J*" 
 
 j— W— ■ 
 r— W— ■ 
 
 O 03 
 
 m * 
 
 < r 
 
 °T 
 
 2 o 
 
 „ o 
 
 IT S 
 
 CD 
 O 
 
 u 
 
 a 
 
 w 
 
 o 
 
 •H 
 
 Q 
 
 +3 
 
 •H 
 
 PQ 
 
 CD 
 
 > 
 •H 
 
 -3" 
 CO 
 
 •H 
 
TABLE 3.1 
 
 21 
 
 ARGUMENT 
 
 Desired 
 Coefficient 
 
 Nearest Available 
 Coefficient 
 
 Error 
 
 1/2[1-C0S(||A)] 
 
 Gesired- 
 earest 
 
 X 100 
 
 
 Degrees 
 
 
 00000 
 
 0.0 
 
 .0000 
 
 00001 
 
 11.25 
 
 .0096 
 
 00010 
 
 22.5 
 
 .0381 
 
 00011 
 
 33-75 
 
 .0843 
 
 00100 
 
 45.0 
 
 .1465 
 
 00101 
 
 56.25 
 
 .2222 
 
 00110 
 
 67.5 
 
 .3087 
 
 00111 
 
 78.75 
 
 .4025 
 
 01000 
 
 90.0 
 
 .5000 
 
 01001 
 
 101.25 
 
 .5976 
 
 01010 
 
 112.5 
 
 .6914 
 
 01011 
 
 123.75 
 
 .7778 
 
 01100 
 
 135.0 
 
 .8536 
 
 01101 
 
 146.25 
 
 .9158 
 
 oiiio 
 
 157.50 
 
 .9620 
 
 01111 
 
 168.75 
 
 .9904 
 
 10000 
 
 180.00 
 
 1.0000 
 
 10001 
 
 191.25 
 
 .9904 
 
 10010 
 
 202.50 
 
 .9620 
 
 10011 
 
 213.75 
 
 .9158 
 
 10100 
 
 225.00 
 
 .8536 
 
 10101 
 
 236.25 
 
 .7778 
 
 10110 
 
 2*17.50 
 
 .6914 
 
 10111 
 
 258.75 
 
 .5976 
 
 11000 
 
 270.00 
 
 .5000 
 
 11001 
 
 281.25 
 
 .4025 
 
 11010 
 
 292.50 
 
 .3087 
 
 11011 
 
 303.75 
 
 .2222 
 
 11100 
 
 315.00 
 
 .1465 
 
 11101 
 
 326 . 25 
 
 .0843 
 
 11110 
 
 337.50 
 
 .0381 
 
 11111 
 
 348.75 
 
 .0096 
 
 43210 
 
 Percent 
 
 0/31 
 
 00000 
 
 .0000 
 
 0/31 
 
 00000 
 
 .0000 
 
 1/31 
 
 00001 
 
 .0323 
 
 3/31 
 
 00011 
 
 .0968 
 
 5/31 
 
 00101 
 
 .1613 
 
 7/31 
 
 00111 
 
 .2258 
 
 10/31 
 
 01010 
 
 .3226 
 
 12/31 
 
 01100 
 
 .3871 
 
 16/31 
 
 10000 
 
 .5161 
 
 19/31 
 
 10011 
 
 .6129 
 
 21/31 
 
 10101 
 
 •677^ 
 
 24/31 
 
 11000 
 
 .7742 
 
 26/31 
 
 11010 
 
 .8387 
 
 28/31 
 
 11100 
 
 .9032 
 
 30/31 
 
 11110 
 
 .9677 
 
 31/31 
 
 11111 
 
 1.0000 
 
 31/31 
 
 11111 
 
 1.0000 
 
 31/31 
 
 11111 
 
 1.0000 
 
 30/31 
 
 11110 
 
 .9677 
 
 28/31 
 
 11100 
 
 .9032 
 
 26/31 
 
 11010 
 
 .8387 
 
 24/31 
 
 11000 
 
 .7742 
 
 21/31 
 
 10101 
 
 .677^ 
 
 19/31 
 
 10011 
 
 .6129 
 
 16/31 
 
 10000 
 
 .5161 
 
 12/31 
 
 01100 
 
 .3871 
 
 10/31 
 
 01010 
 
 .3226 
 
 7/31 
 
 00111 
 
 .2258 
 
 5/31 
 
 00101 
 
 .1613 
 
 3/31 
 
 00011 
 
 .0968 
 
 1/31 
 
 00001 
 
 .0323 
 
 0/31 
 
 00000 
 
 .0000 
 
 0.00 
 
 +0.96 
 +0.58 
 -1.25 
 
 -1.48 
 -0.36 
 -1.39 
 +1.54 
 -1.61 
 -1.53 
 +1.4o 
 +O.36 
 +1.49 
 +1.26 
 
 -0.57 
 
 -O.96 
 
 0.00 
 
 -0.96 
 
 -0.57 
 
 +1.26 
 +1.49 
 +0.36 
 +i.4o 
 -1.53 
 -1.61 
 +1.54 
 -1.39 
 -O.36 
 -1.48 
 -1.25 
 +O.58 
 +O.96 
 
22 
 
 coefficient is chosen from among the 32 possible values ranging in equal 
 increments from to 1. Referring to Figure 3»*+ note that the output of the 
 encoder is h, „. . (not h „. .). Therefore, a diode is placed at each argument- 
 bit line intersection at which a appears in the binary numbers of the third 
 grouping in Table 3»1« A 1 in the third grouping indicates that no diode is 
 to be placed at that argument-bit line intersection. The last column in 
 Table 3«1 lists the error due to the finite width of the five bit coefficient 
 storage registers. It is seen that the maximum absolute error due to this 
 cause is only 1.61$. 
 
 The entire circuit of Figure 3«^ is contained on a single printed 
 circuit board. Since the card was layed out to accept diodes at any argument- 
 bit line intersection and the F-93H decoders are in sockets, it is possible 
 to have another set of encoder cards with a different arrangement of diodes 
 giving rise to a different kernel in equation (3«*0 and hence a different 
 Transform. However, the argument of the kernel would still have to be 
 (ki + i j ) and the kernel itself would have to have a cycle length of 32. 
 
23 
 k. ARRAY TRANSFORM 
 
 In designing a system capable of performing the general linear 
 transform of an input picture, it is natural to want to incorporate into the 
 machine a method of selecting some coefficients in each of the 1,024 
 coefficient frames under direct operator control. As shown in Figure 4.1, 
 this is accomplished in Transformatrix by having a 5 x 5 array of coefficients 
 chosen by the operator entered into the (k,i) coefficient frame symmetric 
 about column k and row £. 
 
 4.1 Applications of the Array Transform 
 
 4.1.1 Pattern Recognition 
 
 An application of the Array Transform is a type of pattern 
 recognition in which Transformatrix is programmed to recognize any 5x5 
 subsection of the 32 x 32 input pattern (grey scale = 2) and to indicate its 
 spatial location within the input pattern. 
 
 This is accomplished by having a 5 x 5 array of rotary switches on 
 
 the computer console each of which can be set to any one of the coefficients 
 
 (-1, -.8, -.6, . . ., 0, . . ., .6, .8, 1). For each output point (k,£), the 
 
 Coefficient Processor enters the 5x5 coefficient array that has been 
 
 selected symmetrically about column k and row £ of the b. n . . coefficient frame, 
 
 kiij 
 
 All other b, B . . coefficients are set equal to - (the reason for this is given 
 in section 4.2) . 
 
 The values of the coefficients in the 5x5 array are chosen such 
 that the sum of the products of the 5x5 coefficient array times the 5x5 
 subsection of the input pattern that is to be recognized is maximum. The 
 selection of appropriate coefficients is illustrated in Figure 4.2(a) for the 
 
2 
 
 2k 
 
 O v? 
 
 U. * 
 
 UJ < 
 
 < 
 
 Ul 
 
 UJ 
 
 O 
 
 ti- 
 ll- 
 UJ 
 O 
 O 
 
 O 
 0. 
 
 a: 
 
 < 
 
 UJ 
 
 o 
 
 u. 
 u. 
 
 UJ 
 
 o 
 o 
 
 m 
 
 x 
 IO 
 
 poooq 
 
 OOOOOt 
 
 .OOOOOf« 
 
 'oOOOOi 
 
 ooooo 
 
 2 
 
 -J 
 
 8 
 
 - 
 
 a: 
 o 
 
 < 
 
 a: 
 
 UJ 
 
 CL 
 
 o 
 
 GD 
 
 UJ 
 
 en 
 
 CO 
 UJ 
 
 -J 
 
 2 
 
 w 
 
 -p 
 d 
 
 <D 
 
 •H 
 O 
 
 •H 
 
 Ch 
 
 <H 
 
 a; a) 
 ° £ 
 
 o 
 
 -p 
 
 >? c 
 ce a; 
 
 3 3 
 
 LT\ Ch 
 
 <D 
 
 X O 
 O 
 
 o « 
 
 a 
 o 
 
 •H 
 43 
 
 •H 
 
 CO 
 
 & 
 
 0) 
 
 •H 
 P-4 
 
INPUT PATTERN 
 
 25 
 
 •••• 
 
 ••• 
 
 •••• 
 
 • ••• 
 
 • •• 
 
 5x5 COEFFICIENT ARRAY 
 
 i ii- 
 
 ziziziz 
 zlziziz 
 
 III. 
 
 FOR DETECTING THE LETTER 'E' 
 
 Figure 4.2(a). Selection of Coefficients for Detecting the Letter 'E' 
 
 OUTPUT PATTERN 
 
 
 
 
 
 
 
 
 
 ' i 
 j i 
 
 
 
 
 
 
 
 b 
 
 
 
 
 3 
 
 1 
 
 
 
 3 
 
 13 
 
 8 
 
 5 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 2 
 
 6 
 
 5 
 
 3 
 
 
 
 i • 
 i i 
 
 ~ 
 
 
 
 
 2 
 
 6 
 
 5 
 
 3 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 2 
 
 10 
 
 5 
 
 3 
 
 
 
 
 
 2 
 
 
 
 1 
 
 1 
 
 3 
 
 5 
 
 2 
 
 1 
 
 
 
 
 
 
 
 Figure 4.2(b). Output Pattern That Results from Input Pattern and Coefficient 
 
 Array Given in Figure 4.2(a) 
 
26 
 
 letter 'E'. The coefficients corresponding to light dots in the 'E' are 
 set = 1 and the coefficients corresponding to dark (no light) dots are set 
 = -1 . The negative coefficient is determined from the condition Z 
 coefficients « 0. This insures that light dots which make up the 'E' 
 and spurious light dots will be given weights in proportion to the number of 
 light and dark dots in the pattern to be recognized. The output pattern that 
 results from an 'E' and 'F' in the input pattern and a 5 x 5 coefficient array 
 as described above is shown in Figure 4»2(b). All negative z-axis values are 
 set equal to zero in the output pattern. 
 
 It is seen that the maximum light intensity appears in the output 
 pattern at the same coordinates as those of the center of the 'E' in the input 
 pattern. An examination of the output pattern also reveals a second light 
 dot, which corresponds to the letter 'F' in the input pattern, of slightly 
 lower intensity than the maximum. The difference in light intensity in the 
 output pattern between the maximum and any other light intensity indicates how 
 close the corresponding 5x5 subsection in the input pattern resembles the 
 selected 5x5 figure. A threshold control is provided on the control panel 
 which allows the display of only those z-axis values > the value set by the 
 threshold control. This enables one to easily distinguish between light 
 intensities of nearly equal brightness. 
 
 4.1.2 Smoothing High Contrast Input Pictures 
 
 A second application of the Array Transform is the 'smoothing' of 
 high contrast input pictures. A coefficient array which performs this 
 function appears in Figure 4.3* The type of 'smoothing' function obtained can 
 clearly be varied by appropriate selection of the coefficients. 
 
 
27 
 
 .2 
 
 .4 .6 .4 
 
 .2 .6 I .6 .2 
 
 .4 .6 A 
 
 .2 
 
 Figure ^.3. One Possible Coefficient Array for 
 
 'Smoothing' High Contrast Input Pictures 
 
28 
 
 k-,2 Array Transform Equations 
 
 Let A(kji) represent the light intensity at point (k,i) in the out- 
 put pattern under the Array Transform operation. From equation (2.1) 
 
 A ^ - i5 | WlJ (U - X) 
 
 As was encountered under the Fourier Transform, the Array Transform uses 
 negative coefficients. The Fourier Transform mapping (see section 3*1) is 
 also employed for the Array Transform to implement the negative coefficients 
 as SRPS's. 
 
 
 where A is the input to the five hit diode encoder. The generation of the 
 Array Transform coefficients, b g . ., must take into account the passing of 
 the Array Transform arguments, A, through the five bit diode encoder and 
 hence the mapping given by equation (4.3) • This topic is taken up in section 
 k.h. 
 
 From the definition of the Array Transform operation, for every 
 point (k,i) in the output pattern there is at most 25 coefficients c . ^ 0. 
 Using this fact and substituting equation {h.2) into equation (h.l) we have 
 
 31 25 
 
 A(k,i) = Z x. .12 - Z c. ,. .x. .12 (k.k) 
 
 x j j — u 
 
Rewriting equation (^.^-) gives 
 
 29 
 
 " Z C kli3 X io '" 2[A(k '^ - . E n X ij /2] (U - 5) 
 
 1 j J — U 
 
 25 
 
 To obtain the desired output, - Z c, „..x. ., a special 32.5M-S cycle 
 
 kjjij ij' 
 
 is set aside every output frame in which c„„. . =0, V i,j (b „„ , . = — ). The 
 
 resulting sum of products, L x. ./2, is integrated, stored, and subtracted 
 
 i,j=0 1J 25 
 
 from each succeeding computation, A(k,i), yielding - Z c n „. .x. ., 
 
 kiij ij 
 
 U.3 Array Transform Block Diagram 
 
 A block diagram of the logic involved in the generation of the Array 
 Transform coefficients is shown in Figure k.k. The primary signals which are 
 to be generated consist of: the 32 five bit adder register inputs Clear., 
 g. , and D , . . . , D (see page 18 for drawing of adder interface logic) and 
 the coefficient row address signals G , G , . . . , G , . Note that the Array 
 Transform coefficients are entered into the coefficient storage registers 
 through the five bit adder input registers and the five bit diode encoders. 
 That is, the data lines to the coefficient storage registers are used in 
 common by all three operations. The mapping performed by the encoder (given 
 by equations (^+.2) and (4<>3)) must be taken into account in the generation 
 of the Array Transform coefficients » This area is covered in section k.k. 
 
 * The particular choice of the inverse mapping given in section k.k results 
 
 in the negative values of cos(-r^ A) (-• c '. .) corresponding to positive 
 
 'dialed-in' coefficients and vice- versa. So, the desired output (with the 
 
 25 
 proper sign) is Z (-a, „ . . )x. . . 
 
1 
 
 A 
 
 3 
 
 2 
 
 -oo 
 
 30 
 
 -►j 
 
 -o- >■ 
 
 r* e* 
 
 !S!= 
 
 i 5 Hi 
 
 t s 
 
 hO 
 otf 
 
 •H 
 
 Q 
 
 J« 
 o 
 o 
 
 H 
 pq 
 
 S 
 
 o 
 
 Ch 
 w 
 (3 
 BJ 
 
 Jh 
 
 >> 
 
 0) 
 
 •H 
 
 •1 * 
 
 :-J 
 
31 
 
 In the following discussion assume that neither of (k,j5) is = 0, 1, 
 30 or 31* Under these conditions the entire 5x5 coefficient array will fit 
 within the 32 x 32 coefficient frame for all allowed values of (k,i). 
 
 The Clear, signals are prepared first. The contents of the 
 k-counter are fed into an adder which has 11101 as the second input resulting 
 in k-3 at the output. The quantity k-3 is gated into the set inputs of a 
 five hit counter. As the counter clock makes five -* 1 transitions the 
 counter advances through the five states: k-2, . . ., k+2. The 1/32 decoder 
 strobe pulses the decoder in synchronism with the counter clock causing five 
 of the decoder output lines to go sequentially to a logical 0. The five 
 decoder lines going to a logical cause five of the 32 flip-flops in the 
 Clear, register to go to a logical 1. The other 27 flip-flops remain at 
 logical 0. The Clear, signals do not affect the 32 five bit adder registers 
 until they are strobed. 
 
 The G. signals are set up in the same way as the Clear, signals. 
 
 J 
 
 The only difference is that 27 G.'s are a logical 1 while five are a logical 0. 
 
 J 
 
 During the last half of each computational cycle the number 11000 
 
 is entered into all 32 five bit adder registers by successively pulsing all the 
 
 g. lines. This number is encoded into a coefficient (b n . . . ) = — . Recall 
 1 kiij 2 
 
 from section 4.2 that all but at most 25 coefficients = — in each (k,^) cycle. 
 
 At the beginning of each cycle, immediately after the preceeding 
 frame of coefficients has been reset, the G. register is strobed and the 
 coefficient = — is entered into 27 rows of coefficient storage registers. Each 
 of the remaining five rows of coefficients is accessed one at a time. First 
 the Clear, register is strobed and five adder registers are cleared „ Then 
 the g. counter is toggled five times in synchronism with. the g. decoder strobe. 
 The process enters the first group of five Array Transform coefficients into 
 
32 
 
 the proper five bit adder registers through their set inputs. (The number Ak, 
 
 used in the generation of the g. signals, is equal to k delayed one cycle. 
 
 This is necessary because the Clear, signals are set up in one cycle and the 
 
 g. signals are generated in the next cycle.) The 27 remaining adder registers 
 
 still contain 11000 which when encoded gives a coefficient = — . G. „ is 
 
 2 j-2 
 
 pulsed and the encoded version of the contents of the adder registers is 
 
 entered into the corresponding coefficient registers of row j-2. This 
 
 procedure continues until the fifth group of Array Transform coefficients is 
 
 entered into the j+2 row of coefficient registers. 
 
 If either or both of (k,i) = 0, 1, 30, or 31, part of the 5x5 
 
 coefficient array falls outside of the 32 x 32 coefficient frame. When this 
 
 occurs the coefficients which correspond to locations not in the 32 x 32 
 
 coefficient frame should be ignored. However, under these conditions either 
 
 or both of the (k,^) counters would underflow or overflow causing the 
 
 coefficients to be entered into storage registers within the 32 x 32 coefficient 
 
 frame. To prevent this from happening the (k,j/) counters are allowed to 
 
 underflow or overflow but the proper (k,i) 1/32 decoder strobe pulses are 
 
 inhibited. For example, (k,i) = (1,31) would result in the 1st k decoder 
 
 strobe pulse and the 4th and 5th £ decoder strobe pulses to be inhibited. 
 
 During the special averaging cycle all the G . flip-flops are set to 
 
 J 
 
 a logical 1 and immediately after the preceeding frame of coefficients has 
 been reset the G. register is strobed causing the coefficient = — to be entered 
 
 J 
 
 into all 1,024 storage registers. The Clear, signals are inhibited during 
 this cycle. 
 
33 
 
 4.4 Array Transform Logic Design 
 
 The logic design of the functional blocks which make up the Array- 
 Transform subsystem shown in Figure 4.4 is rather straightforward and will 
 not be described in detail here. However, it is of interest to explore 
 further the manner in which the 25 'dialed- in' Array Transform coefficients 
 are presented to the four 25/1 multiplexers. 
 
 Recall from section 4.3 that the multiplexer outputs are gated into 
 the appropriate five bit adder registers and from there pass through the five 
 bit diode encoders to the coefficient storage registers. The encoders perform 
 the cosine mapping given by equations (4.2) - (4.3). Therefore, the function 
 of the rotary switches on the control panel is to implement the inverse 
 cosine mapping so that the correct coefficients are entered into the storage 
 registers. Figure 4.5 illustrates how 4 bits of one coefficient are generated 
 via an 11 position - 4 section rotary switch. It will be seen shortly that 
 the most significant bit of the 'dialed-in' coefficient is constant and may be 
 hardwired into the adder registers. 
 
 The rotor tab on each section is connected to 5v - a logical 1. 
 As the coefficient dial on the control panel is turned clockwise from -1.0 to 
 +1.0, the rotor tab on each section sequentially makes contact with each 
 stator tab on that section. For a fixed position of the dial, if there is a 
 wire jumper leading from the stator that is in contact with the rotor to the 
 output line, then the output of that bit line is a logical 1, Conversely, 
 if there is no jumper at the rotor-stator contact, the 470 ohm resistor to 
 ground acts as a logical to the following TTL gate. In this manner any 
 arbitrary many-to-one mapping may be implemented with the rotary switches. 
 The diode in each output line is used to provide current surge protection for 
 the following TTL gate in the event of a transient spike on the 5v supply line. 
 
3^ 
 
 CLOCKWISE 
 
 >» 
 
 5V >- 
 
 + 5V p 1 1 
 
 paioeeooeee 
 
 66 6 66 OOOO OO 
 
 ■M t > D 
 
 >A70Sl 
 
 9 9 
 
 00000000 
 
 470X1 
 
 o o 9 o o 9 9 e 9 o 
 
 60060066060 
 
 ■ a t > d, 
 
 < 470 ft 
 
 9 9 < 1 
 
 09090990 
 
 "O-OOOOOOOOO 0f- 
 
 -1.0 -.8 -.6 -.4 -.2 .2 .4 .6 8 1.0 
 
 -t > D c 
 
 ?470X1 
 
 ALL RESISTORS ARE CARBON, 5W, 5% 
 DIODES- IN4I48 
 
 Figure U.5. Wiring of Rotary Switch to Implement Coefficient Mapping 
 
 
35 
 
 The object of this arrangement is to perform the inverse of the 
 mapping given by equations (4„2) - (4.3). Table 4.1 summarizes the steps 
 taken in determining the location of the jumpers on the rotary switches. The 
 first column lists the desired coefficients which are dialed-in on the computer 
 console. The corresponding mapped coefficient (b) is given in column two. The 
 nearest available coefficient is noted in the third grouping. The related 
 argument, A, is obtained by referring to Table 3«1« A 1 in the argument 
 column indicates that a jumper is placed at the corresponding section- stator 
 location on the rotary switches. There is no jumper at those section-stator 
 intersections where a appears in the argument column. The resulting error 
 is tabulated in the last column with a maximum absolute error of 2.58^. 
 
 Note that bit h of the argument, A, is a logical 1 for all 
 coefficients. Thus only k instead of 5 sections per rotary switch are 
 required with bit k being set equal to a logical 1 directly at the adder 
 registers. 
 
TABLE k.l 
 
 36 
 
 Dialed-In 
 Coefficient 
 
 Mapped 
 Coefficient 
 
 Nearest Available 
 Coefficient 
 
 Corresponding 
 Argument 
 
 Error 
 
 c 
 
 l/2[l-(- 
 
 •c)] 
 
 " 
 
 
 
 
 A 
 
 Mapped x la 
 Nearest 
 
 — 
 
 
 
 
 — 
 
 
 
 — 
 
 ^3210 
 
 Percent 
 
 -1.0 
 
 
 
 
 0/31 
 
 0.0000 
 
 31 
 
 11111 
 
 0.00 
 
 -. .8 
 
 .1 
 
 
 3/31 
 
 .0968 
 
 29 
 
 11101 
 
 +0.32 
 
 - .6 
 
 .2 
 
 
 7/31 
 
 .2258 
 
 27 
 
 11011 
 
 -2.58 
 
 - .k 
 
 .3 
 
 
 10/31 
 
 .3226 
 
 26 
 
 11010 
 
 +2.26 
 
 - .2 
 
 .k 
 
 
 12/31 
 
 .3871 
 
 25 
 
 11001 
 
 +1.61 
 
 
 
 .5 
 
 
 16/31 
 
 .5161 
 
 2k 
 
 11000 
 
 -1.29 
 
 .2 
 
 .6 
 
 
 19/31 
 
 .6129 
 
 23 
 
 10111 
 
 -1.29 
 
37 
 
 5. COORDINATE TRANSFORM 
 
 It is frequently desirable to normalize an input picture with 
 respect to translation of the input pattern in the horizontal and vertical 
 directions, magnification in the horizontal and vertical directions, and 
 rotation of the input pattern about the geometric center of the output 
 display. The Coordinate Transform comprises the above operations. 
 
 5.1 Coordinate Transform Equations 
 
 Let (u,v) represent the quantized coordinates of a point in the 
 input pattern. Under the Coordinate Transform the light intensity at this 
 point is mapped onto a point (U,V) in the output pattern given by: 
 
 U = m(u + a)cos0 + n(v + b)sinQ (5.1) 
 
 V = -m(u + a)sin0 + n(v + b)cos6 (5«2) 
 
 In the above equations a and b are the amounts of translation in the hori- 
 zontal and vertical directions, respectively, m and n are the magnification 
 factors in the horizontal and vertical directions, respectively, and 6 is 
 the angle of (clockwise) rotation. 
 
 As it stands the Coordinate Transform defined by equations (5.1) - 
 (5.2) is ambiguous, since for certain transformations the quantized nature 
 of the coordinates makes it possible to map more than one input light 
 intensity onto the same output point. This ambiguity may be alleviated by 
 performing the inverse transformation defined by the equations : 
 
38 
 
 u = (l/m)[Ucos8 - Vsine] - a (5.3) 
 
 v = (l/n)[Usin9 + VcosS] - b (5.U) 
 
 In practice U and V are normalized voltages obtained by feeding the 
 contents of k and I output display counters into D/A converters. As shown 
 in Figure 5-l> u and v are converted into digital signals which are used in 
 a 32 x 32 selection matrix to set the appropriate coefficient (if there is 
 one) equal to 1 and all others equal to 0. An example of horizontal and 
 vertical translation using 3x3 input and output patterns is given in 
 Figure 5-2. 
 
 Transformatrix also has the capability of taking the average of 
 the input light intensities surrounding point (u,v) and displaying the 
 average at output point (U,V) . The 'averaging window' in the input pattern 
 may be selected to be any one of the following sizes : horizontal points x 
 vertical points =1x1, 3x1, 5x1, 1x3, 3x3? 5 x 3 3 1 x 5 5 3 x 5 5 
 and 5x5- 
 
 5.2 Coordinate Transform Block Diagram 
 
 Refer to the block diagram given in Figure 5«3 to obtain a more 
 detailed picture of how the proper b .. . coefficient (s ) is (are) selected 
 and set = 11111 under the Coordinate Transform mode of operation. Note that 
 the logic following the two subtractors is used in common with the Array 
 Transform operation (compare with Figure 4.U). It was convenient to design 
 this logic to be compatible since under the Coordinate Transform the maximum 
 horizontal and vertical sensitivity settings result in a 5 x 5 array of 
 coefficients being set = 11111. This clearly has much in common with the 
 Array Transform coefficient selection. 
 
39 
 
 jQ 
 
 u 
 o 
 
 w 
 
 -p 
 a 
 
 ■<-\ 
 
 ^ 
 o 
 o 
 o 
 
 0) 
 
 XI 
 
 -P 
 <H 
 
 o 
 o 
 
 •H 
 -P 
 
 -p 
 
 (D 
 
 0) 
 
 ft 
 d) 
 « 
 
 H 
 erf 
 •H 
 
 ^H 
 
 o 
 -p 
 
 O 
 
 51 
 
 > > 
 
 Q O 
 
 LPi 
 (L) 
 
 bfl 
 •H 
 P-4 
 
ko 
 
 og 
 
 •Q 
 
 CO 
 
 O 
 
 «: 
 
 h: 
 
 o 
 
 o 
 
 O 
 
 o 
 
 A 
 
 N«*- 
 
 UJ 
 
 < 
 u. 
 
 ooo ooo ooo 
 
 o — o oo— ooo 
 
 ooo ooo ooo 
 
 a 
 o 
 
 •H 
 
 H 
 w 
 
 ■d 
 
 o 
 
 •H 
 -P 
 U 
 
 > 
 
 UJ 
 
 o 
 
 u. 
 u. 
 
 UJ 
 
 o 
 o 
 
 o_ C^^ ooo ooo 
 ooo ooo ooo 
 o — o oo— ooo 
 
 o o ^ o o^ ooo 
 ooo ooo ooo 
 ooo ooo ooo 
 
 3 
 
 -p 
 o 
 
 N 
 •H 
 
 o 
 o 
 9 
 
 3 
 
 ^-«- 
 
 3 UJ 
 (Lt- 
 
 Zh 
 
 — < 
 
 ro 
 
 <9 
 
 0} 
 
 CVI 
 
 in 
 
 op 
 
 — . 
 
 « 
 
 fs 
 
 in 
 
 •rl 
 
K COUNTER 
 
 g * g p 2, 
 
 FIVE BIT O/A CONVERTER 
 
 m> 
 
 sinfl y~ 
 cosfl ^- 
 
 1 ' 1 
 
 COORDINATE 
 TRANSFORM 
 
 u»±[ucoi0-V8in0]-o 
 
 FIVE BIT A/O CONVERTER 
 
 2 g g 7 7 
 
 SUBTRACT 3 
 
 K" T CLOCK >■ 
 
 P P P ft P 
 
 FIVE BIT COUNTER 
 
 K' T STROBE >- 
 
 2 4 2 2 2. 
 
 I OUT OF 32 
 DECODER 
 
 7 7 
 
 Oo 9 
 
 7 7 
 
 Qso 9si 
 
 L COUNTER 
 
 7 7 2 2 2 
 
 FIVE BIT D/A CONVERTER 
 
 co»e^— 
 
 COORDINATE 
 TRANSFORM 
 
 v»i[usiNe+Vcos8]-b 
 
 FIVE BIT A/D CONVERTER 
 
 S S 2 7 J 
 
 SUBTRACT 3 
 
 L" T CLOCK >- 
 
 2 2 2 2 2 
 
 FIVE BIT COUNTER 
 
 L" T STROBE | >- 
 
 2 2 2 2 2 
 
 I OUT OF 32 
 DECODER 
 
 L" T STROBE 2 >" 
 
 P"~U 
 
 7 . ,7 
 
 32 BIT 
 
 REGISTER 
 
 U~T? 
 
 7 . 7 
 
 7 7 
 
 G G, 
 
 7 7 
 
 kl 
 
 Figure 5.3. Coordinate Transform Block Diagram 
 
h2 
 
 The two primary sets of signals that must be generated during each 
 
 (k,i) cycle are the 32 five bit adder register set gate signals, g. , and the 
 
 32 row addressing signals, G.. 
 
 J 
 
 The analog voltages (u,v) corresponding to the horizontal and 
 vertical coordinates of the desired point in the input pattern are obtained 
 
 through analog circuitry described in detail in sections 5.3.1 and 5.3.2. 
 
 -T -T 
 They are converted into five bit digital words, denoted (k ,£ ), with two 
 
 A/D converters (section 5*3.3) • The digital horizontal and vertical input 
 
 -T -T 
 coordinates, k "" and i , are then processed by the remaining logic in a 
 
 manner similar to that described in section k.3 for the Array Transform. 
 
 Assume that the horizontal and vertical sensitivity controls are 
 
 -T -T 
 set to maximum (a 5 x 5 window) and that neither of (k } £ ) = 0, 1, 30, or 31 
 
 Also allow the set inputs of the 32 five bit adder registers to be fixed at 
 
 10000 (10000 encoded = 11111, see Table 3.1). Under these conditions a 
 
 5x5 array of coefficients (all = 11111) is entered into the (k,i) 
 
 -T -T 
 
 coefficient frame symmetric about column k and row £ by manipulating 
 
 -T -T 
 (k ,£ ) in exactly the same manner as (k,i) under the Array Transform. 
 
 However, the remaining 1,024 - 25 = 999 coefficients are left untouched in 
 
 their reset state of 00000. This is because the Coordinate Transform requires 
 
 only non-negative coefficients (namely and 1) and hence mappings such as 
 
 equation (3-8) and (h.2) are not needed. Of course, as indicated above, the 
 
 mapping of the five bit diode encoder must be taken into account in selecting 
 
 the set inputs of the five bit adder registers „ 
 
 There are three different factors which may alter the size of 
 
 the coefficient array which is set = 11111 from that just described (5 x 5). 
 
^3 
 
 1. Horizontal and vertical sensitivity settings . As was mentioned in section 
 5.1 the size of the 'averaging window' can be varied from a maximum of 
 
 5 x 5 to a minimum of 1 x 1. The nine different coefficient array sizes 
 are obtained by inhibiting the appropriate strobe pulses of the k -T and £~^ 
 decoders. For the 5x5 coefficient array none of the strobe pulses are 
 inhibited. The 1x3 coefficient array, however, requires that the 1st, 
 2nd, Uth, and 5th k~T strobe pulses and the 1st and 5th £~^ strobe pulses 
 be inhibited. The other coefficient arrays are obtained in a similar 
 manner. 
 
 2. Counter underflow and overflow . For certain combinations of sensitivity 
 settings and (k-T^-'J-') values, it is possible for part of the coefficient 
 array to fall outside the 32 x 32 coefficient frame „ In this case either 
 or both of the (k"T ? ^"T) counters will underflow or overflow. This 
 condition is detected and the proper k-T and/or i-T decoder strobe pulse (s) 
 is (are) inhibited. For example, if the coefficient array is chosen to be 
 3x5 and (k" T ,i" T ) = (31,1), then the 1st, 4th, and 5th k _T strobe pulses 
 and the 1st i - T strobe pulse are inhibited. 
 
 3. (u,v) out of range . If either or both of (|u|,|v|) is > 5v (see section 
 5.3)5 "the point of interest is outside the periphery of the input pattern. 
 In this case it is desired to set all coefficients = 0. This condition 
 
 is detected (see section 5-3-3) and all five k~^ and jJ~T decoder strobe 
 pulses are inhibited. 
 
 Since the Coordinate Transform requires only non-negative 
 coefficients (0 and 1), there is no need for a special 'averaging' cycle 
 in which all coefficients are set = — (as in the Array Transform) with the 
 resulting sums of products to be integrated, stored, and subtracted from 
 each succeeding calculation. However, there are good reasons for setting 
 aside a special cycle for the Coordinate Transform with all coefficients = 0. 
 Integration, storing, and subtracting the sums of products of such a cycle 
 from each succeeding computation has the effect of cancelling out any noise, 
 ripple, pickup, etc. which have periods equal to or shorter than one cycle 
 (32.5M-S ). In addition, if there were a fault In one of the 1,024 parallel 
 processing circuits which resulted in a cycle-periodic output from the related 
 SRPS multiplier (independent of the coefficient) then subtracting the special 
 cycle output from all other outputs would have the effect of removing the 
 faulty circuit from the system. 
 
kk 
 
 For all the reasons stated above it was decided to implement a 
 special cycle for the Coordinate Transform with all coefficients set = 0. 
 
 5. 3 General Circuit Considerations 
 
 The overall speed at which the Coordinate Transform circuitry has 
 to operate is not very high; the final outputs (u,v) have most of each 
 32.5M.S cycle in which to settle. Since analog multipliers and summing 
 operational amplifiers which operate at this speed are available at low 
 cost, and since it is quite easy to generate sin0 and cos0 in analog form with 
 a sine/cosine potentiometer, it was decided that the Coordinate Transform 
 circuitry should be implemented in an analog fashion. 
 
 It is clear from equations (5.3) - (5°^+) that the circuit design 
 would be simplified if the coordinates of the input and output pictures were 
 made to coincide with discrete voltages in the range of +V volts. Because 
 of the differential input range of the op amp used in the A/D converter (see 
 section 5 • 3 • 3 ) , the voltages corresponding to the edges of the input and 
 output patterns are set equal to +5v. Thus, the first circuit required for 
 the Coordinate Transform subsection is a five bit bipolar D/A converter. 
 
 5.3.1 Five Bit Bipolar D/A Converter 
 
 The circuit schematic of the five bit bipolar D/A converter is 
 given in Figure 5.^-. The +5v analog references are individually regulated 
 with integrated circuit regulators and their outputs can be finely adjusted 
 to within lmv of the desired value over a lv range centered at their nominal 
 voltages. The measured drift over several hours is no greater than 5mv for 
 both references . 
 
^5 
 
 iQr® 
 
 
 X 
 
 I (M 
 
 I CD 
 
 X 
 
 X 
 
 le? 
 
 CD 
 -P 
 
 CD 
 > 
 
 O 
 
 o 
 
 <c 
 o 
 
 O 
 ft 
 •H 
 
 PQ 
 -p 
 
 •H 
 
 m 
 
 CD 
 •H 
 
 LT\ 
 0) 
 
 •H 
 P>4 
 
K6 
 
 A complementary transistor output stage is used to switch the bi- 
 polar analog references to the weighted resistor ladder inputs. The output 
 transistors are operated as overdriven emitter followers to obtain low 
 
 collector-emitter saturation voltages (of the order of 25mv) without 
 
 (15) 
 sacrificing speed. The 200 ohm pots in the two most significant bits of 
 
 the weighted resistor ladder allow for tuning the overall accuracy of the 
 
 D/A converter to better than +1/2$ full scale. 
 
 The five bit input (B . . . B, ) originates from TTL logic. The 
 
 two transistor input stage changes the Ov to +3v TTL input levels to the 
 
 -9.lv to +9.1v levels required to overdrive the output transistors. Since 
 
 unequal turn-on and turn-off times of the output transistors would cause 
 
 glitches in the output waveform, the output transistors are chosen to have 
 
 comparable turn-on and turn-off times. The settling time to +1/2 LSB for a 
 
 worse case input change ( 00000 -» 11111 or 11111 -* 00000 ) is approximately 
 
 l[is . Higher speeds could be obtained by replacing the 715 with a faster op 
 
 amp. 
 
 5.3.2 Coordinate Transform Circuitry 
 
 Once the contents of the (k,i) output display counter have been 
 converted into analog voltages (U, V) , the next step is to transform (U,V) 
 according to equations (5. 3) - (5.^). The analog circuitry which produces 
 the horizontal input picture coordinate, u, according to equation (5«3) is 
 shown in Figure 5*5. 
 
 The voltages, 5cos9 and 5sin0, are generated by a sine-cosine 
 potentiometer using the same + 5v analog references as the D/A converter 
 (see section 5.3.1). The LM302 voltage followers act as high input impedance 
 buffers (maximum bias current = 30nA) for the sine-cosine potentiometer 
 
 
5 COS 
 
 " H ^f°f~l 
 
 \+ -/ 
 
 U LM30 
 
 5 SIN 8 
 ATpt 
 
 <£30K 
 
 in 
 
 i+ -j 
 
 V 
 
 LM302 
 
 x Y 
 
 HYBRID - SYSTEMS 
 
 I07C 
 
 MULTIPLIER 
 
 2 OUT 
 
 X Y 
 
 HYBRID -SYSTEMS 
 
 I07C 
 
 MULTIPLIER 
 
 2 OUT 
 
 IOK 
 
 20K 
 V«« TT <DALE MFF 
 50 °P F f I/4W, 1%, T-2 
 
 MAGNIFICATION > 
 
 VACTEC 
 VTL2C3 
 
 .47 M F=; =Z 
 
 -Lt I80mF 
 
 TANTALUM 
 
 82K 
 
 3K 
 
 TRANSLATION 
 
 20K 
 
 6.8K: 
 
 .002 M F 
 
 !20K 
 
 .OOl/iF 
 
 * i 
 
 IN754A 
 6.8V 
 
 A IN4I48 
 
 4 7 
 
 note: 
 
 all resistors are carbon, i/4w, 5% 
 unless otherwise specified 
 except iok -dale mff, i/4w, 1%, t-2 
 
 Figure 5.5. Schematic of Coordinate Transform Circuitry 
 
hd 
 
 outputs. The Hybrid Systems 107C multipliers produce the products Ucose/2 
 and Vsin0/2. The following 715 op amp performs the necessary subtraction 
 and amplifies the remainder by a factor of 2 resulting in [UcosQ - VsinG]. 
 
 Multiplication of the quantity [Ucos0 - Vsin8] by the magnification 
 factor 1/m is accomplished by varying the input summing resistor of the 
 second 715* To eliminate the capacitive loading effects of a remotely 
 located pot, a Vactec VTL2C3 photo-coupler is used to control the input summing 
 resistance. The VTL2C3 consists of a light -emitting diode and a photo-resistor 
 encapsulated in a TO- 5 can. By varying the magnification input from Ov to +5v, 
 the VTL2C3 photo-resistor changes from ~ 10 Mfi to ~ 1 Kfi. This results in a 
 magnification range of better than 1/k to k. The translation input varies 
 between + 15v, allowing the input picture to be translated to the extremes 
 of the output display under most combinations of the coordinate transform input 
 parameters. The 6.8v zener diodes in the feedback loop of the output 715 op 
 amp threshold the output within the range of approximately + 7«5 V preventing 
 damage to the op amp in the following A/D converter. 
 
 An identical printed circuit board is used to generate the vertical 
 input picture coordinate, v, according to equation (5.^-). The 5cos0 and 
 5sin0 inputs are interchanged and the appropriate magnification and trans- 
 lation controls are used. The subtraction circuit is altered to an addition 
 circuit by removing the jumper between points b-c and adding a jumper between 
 points a-b. The 10 KX> resistor from point c to ground is changed to 3«3 Kfi to 
 equalize the voltage offsets due to the input bias currents. 
 
 The settling time of the Coordinate Transform subsection outputs 
 (u,v) to within + 1/2 LSB for a worse case combination of input controls 
 (a,b,m,n,0) and (U,V) transitions is approximately lOfis. 
 
h 9 
 
 5-3. 3 Five Bit A/D Converter 
 
 Since the access circuitry to the b „ . . storage registers is 
 completely digital, the analog outputs of the Coordinate Transfor sub- 
 section (u,v) must be converted into digital form (each five bits wide). 
 With over half of each 32.5|as cycle in which to perform the two A/D 
 conversions, it was decided to employ successive approximation as the 
 conversion technique. ' Although this is by far not the fastest method of 
 converting from analog to digital, it is fast enough for this application. 
 It has the additional advantages of complexity which depends linearly on the 
 number of bits involved, and a structure which can utilize the D/A converter 
 already designed for the front end of the Coordinate Transform subsection. 
 
 A circuit drawing of the five bit A/D converter is shown in Figure 
 5.6. The timing pulses are denoted by the particular clock cycle during which 
 they occur. Five D-type flip-flops make up the A/D converter output register. 
 With each Data input tied to a logical 0, the flip-flops are reset at the 
 -» 1 transition of the clock (count 50). At count 60 the output register is 
 initialized to 10000. This number is fed into a D/A converter whose output is 
 connected to the non-inverting input of a 715 op amp. The 715 is used open 
 loop as a comparator because of its high differential input range (+ 15v). If 
 the unknown analog input > reference D/A output, then the comparator output is 
 a logical 0, and at count 256 bit Q, remains a logical 1. However, if the 
 unknown analog input < reference D/A output then the comparator output is a 
 logical 1, and at count 256 bit Q, is reset to a logical 0. In both of the 
 previous two cases bit Q, is set to a logical 1 at count 256 in preparation for 
 the next approximation. This process continues until at count 30U bit Qq either 
 remains a logical 1 or is reset to a logical depending on whether the unknown 
 analog input > or < reference D/A output. As can be seen from the control 
 
50 
 
 3 
 
 lO 
 
 t=o 
 
 @—2 
 
 ICC 
 
 IO 
 
 -> in 
 
 co 
 
 z 
 
 3— Kh-i 
 
 ■ww — •— • 
 
 I— «— |l> 
 
 
 ICO 
 
 ZJ 
 
 CM 
 
 o 
 
 ICC 
 
 ( WAr 
 
 CD 
 
 
 |C0 
 
 IO 
 
 IO 
 
 o 
 
 IO 
 
 I CD 
 
 I* I 
 
 Iai *"^ 
 
 fcO 
 
 (SM^ 
 
 o 
 
 Ico 
 
 >J 
 
 £^> 
 
 @H- 
 
 l<r 
 
 lio 
 
 >-J 
 
 IO 
 
 @— c? 
 
 3§ 
 
 Icj 
 
 a 
 co 
 
 > 
 u. 
 
 ICO 
 
 o 
 
 IO 
 
 U 
 CD 
 
 -p 
 
 0) 
 
 o 
 o 
 
 ■p 
 
 •H 
 
 PQ 
 
 CD 
 > 
 •H 
 
 LPv 
 0) 
 
 •H 
 
51 
 
 pulses given in Figure 5.6, the time allowed for settling between the successive 
 approximations is quite liberal. 
 
 For an analog input either < -5v or > +5v it is easily seen that 
 the A/D converter will produce the outputs 00000 or 11111, respectively. 
 Since values of u or v satisfying either of these inequalities correspond to 
 coordinates of points off the 32 x 32 input pattern, under these circumstances 
 it is desired to have all b n . . . coefficients remain equal to 0. In order to 
 accomplish this analog comparators are used to detect whenever u or v go 
 'out of range' (|u| or |v| > 5v). When the 'out of range' condition occurs 
 the appropriate coefficient accessing circuitry is inhibited (see section 5*2) 
 preventing points on the periphery of the output display from being 
 erroneously lighted. 
 
52 
 
 6. COEFFICIENT STORAGE AND D/A CONVERSION 
 
 Once the basic system design of Transformatrix has been decided 
 upon, it is clear that a potential problem area is the (digital) co- 
 efficient storage and D/A conversion subsystem. The large number of identical 
 circuits required, 1,02^, places severe restrictions on both the circuit design 
 itself and the method of packaging the circuits in the Transformatrix system. 
 This chapter deals with the design and fabrication of the storage register and 
 D/A converter together with two auxiliary circuits : an analog reference 
 regulator and the coefficient Quantized Random Analog Signal (QRAS) driver. 
 
 6.1 General Design Considerations 
 
 In order to convert each frame of 1,02^ stored (digital) coefficients 
 into SRPS's, all the coefficients must be made available for a full 25 • 5M-S out 
 of each 32.5M-S cycle. This requirement precludes the use of standard 
 'scratchpad' type memories which are capable of having the contents of only 
 one storage cell read out at a time. Under these circumstances the least 
 expensive method of storage was found to be R-S flip-flops made up of inter- 
 connected NAND gates. 
 
 Before going into detail about the design of the D/A converter, a 
 few words should be said concerning the alternative: completely digital 
 conversion from binary to SRPS representation. Instead of a five bit D/A 
 converter and analog comparator as the binary to SRPS conversion circuit, 
 there could be a five bit digital comparator with the (digital) coefficient 
 as one input and five bits of a pseudo-random shift register as the other input 
 Although the all digital route has the advantages of a single power supply, 
 inherently higher reliability, and little or no temperature problems, in this 
 
53 
 
 particular application it also has some striking disadvantages. Basically, a 
 parallel five bit comparator would involve enough gates to be too expensive 
 and take up too much space while a serial comparator would be too slow (the 
 pseudo-random five bit words would be changing at 10 MHz). 
 
 If a five bit D/A converter can be made cheaply enough, then an 
 analog comparator, contained in a single lk pin package and with a maximum 
 delay time of ^Ons, can be used to convert the (analog) coefficient to a 
 
 SRPS. It should also be noted that the input image light intensity is con- 
 
 (5) 
 verted directly into an analog voltage which makes use of the analog 
 
 comparator natural for the light intensity to SRPS conversion. Thus, the 
 
 power supplies needed for the coefficient analog comparators are already 
 
 required for the light intensity analog comparators and need only be increased 
 
 in size. 
 
 Once it has been decided to use a D/A converter-analog comparator 
 combination, the problem has been reduced to the design of a D/A converter „ 
 
 The complete schematic of the storage register and D/A converter 
 is shown in Figure 6.1. The Hex Inverter acts as a buffer for the binary 
 weighted resistor ladder. The saturation voltage of the transistors in the 
 Hex Inverter varies very little within any one package (less than 5mv) but 
 the variation from package to package can be as. much as lOOmv. For this 
 reason the Hex Inverters were tested and selected into nine different groups 
 according to saturation voltage, with the spread within each of the groups 
 equal to lOmv. The difference in the logical Hex Inverter output from group 
 to group is compensated for by having individually adjustable logical 1 
 reference supplies for each group (see section 6.3) and by incorporating a 
 variable DC offset into the QRAS circuits which drive the other input of the 
 analog comparators (see section 6.h). 
 
«»4> 
 
 ;=o 
 
 •>!>■ 
 
 H> 
 
 bi> 
 
 ;=0 
 
 ^^> 
 
 V.2 4 
 
 R©/2 1 
 
 Ro/2* 
 
 VV . I 
 
 E^> 
 
 Ro/2 
 
 /2 1 
 
 E>r£> 
 
 Rp/2° 
 
 +5V 
 :640fi* 
 
 450fl* 
 
 $ 
 
 5^ 
 
 ' bkiii 
 
 * NOMINAL VALUES 
 
 (COMMON TO 
 32 CIRCUITS) COEFFICIENT RESET ( COMMON TO 1024 CIRCUITS ) 
 
 4 DM8000N NATIONAL SEMICONDUCTOR TTL QUAD 2 in NAND 
 
 I MC889P MOTOROLA RTL HEX INVERTER (5 INVERTERS USED) 
 
 I LM302 NATIONAL SEMICONDUCTOR VOLTAGE FOLLOWER 
 
 5 MFF-l/4 DALE .1%, T-2 RESISTOR 
 
 Figure 6.1. Coefficient Storage Register and D/A Converter 
 
55 
 
 The binary weighted resistor ladder was chosen over the more widely 
 used R-2R resistor ladder because it uses fewer resistors (five versus eleven) 
 
 and the advantages normally associated with R-2R resistor ladders are of little 
 
 (17) 
 or no consequence in this particular application. That is, the 16:1 
 
 variation in summing currents of the binary weighted resistor ladder does not 
 
 cause any problems since the weighted resistors are all chosen rather large 
 
 (R = 800 Kfi). At the same time, the resistors are not so large that they 
 
 tend to slow down the conversion speed. Since the resistors are discrete and 
 
 not packaged on the same substrate (too expensive), the advantage with the 
 
 R-2R ladder of having matched temperature coefficients cannot be easily 
 
 realized. In addition, the temperature coefficient itself can be chosen small 
 
 enough so that the change in resistance with temperature is small enough to 
 
 be ignored. 
 
 The weighted resistor ladder feeding a high input impedance voltage 
 
 follower was chosen over the more conventional weighted resistor ladder tied 
 
 to the virtual ground of an op amp, for the following reasons. Compared with 
 
 op amps of equivalent cost : 
 
 1. The voltage follower is at least ten times faster. For the configuration 
 in Figure 6.1 and Rq = 800 Kfi, the voltage follower has an actual full 
 scale slew rate of lOv/us with no overshoot. 
 
 2. The input current, 30nA maximum, is less than or equal to most op amps' 
 offset current. 
 
 3. The offset voltage is selected comparable to that of op amps (-10mv < 
 Output- Input < +5mv). 
 
 h. The accuracy of the voltage follower (.15$ DC) is not dependent on the 
 accuracy of an external feedback resistor. 
 
 5. The output impedance of the voltage follower is extremely low, 2.5 ohms 
 maximum. 
 
 6. No external frequency compensation is required for the voltage follower. 
 
% 
 
 Thirty-two of the circuits shown in Figure 6.1, together with data 
 and reset drivers, are contained on a single printed circuit board measuring 
 20" x 12.15". Thirty- two of these large boards hold all 1,024 coefficient 
 storage registers and D/A converters. Use of these boards has the advantage 
 of reducing backpanel wiring, decreasing the parasitic capacitance and 
 inductance the voltage followers have to drive, increasing reliability, and 
 conserving space. The physical layout of the board is given in Figure 6.2. 
 A photograph of one of the actual boards in its tester is shown in Figure 6.3. 
 The small board attached to its lower right hand side is the adjustable 
 analog reference supply (covered in section 6.3) • 
 
 6. 2 Determination of Weighted Resistor Values 
 
 If the collector resistors of the Hex Inverter in Figure 6.1 were 
 a fixed value, say R ohms, and the ladder resistors were also fixed, it would 
 be quite easy to determine the optimum ladder resistor values. In this case 
 they would be: Rq/2° - R/2, Rq/2 1 - R/2, . . ., R /2 - R/2. However, the 
 collector resistors of the Hex Inverter do vary from package to package (they 
 are within a few ohms of each other in the same package) and the ladder 
 resistors have a finite tolerance. The Hex Inverters were chosen such that 
 565 ohms < R < 800 ohms. The ladder resistors have a tolerance of + .1%. It 
 is not necessary to include the variation of the ladder resistors with 
 temperature since by choosing low temperature coefficient resistors (50 PPM/ C 
 for ~55 C < T <: + 17 5 C) the change in resistance over the operating temper- 
 ature range of the system is negligible. 
 
 The basic equation used in determining the ladder resistors is 
 derived from the circuit shown in Figure 6.h. The 5. 's (i = 0, 1, . . ., 4) 
 include the effects of variation in the collector resistor values from unit 
 to unit and the tolerance of the ladder resistors. 
 
57 
 
 RESISTORS 
 
 ACTUAL SIZE 
 
 t>Mij 
 OUTPUTS 
 TO 32 
 COMPARATORS 
 
 A. 
 
 OM8000N 
 
 _! 
 
 PM800ON 
 
 u 
 
 z 
 
 o 
 
 z 
 
 o 
 
 CD 
 
 /I 
 
 0M8O0ON 
 
 DDDDDD 
 
 DRIVERS 
 
 1 
 
 1.1' 
 
 hi 
 
 Z 
 
 o 
 
 z 
 
 o 
 
 CO 
 
 POWER G — G 2 8G30b4— boR3|— G29G31 POWER 
 1 12.15" 
 
 20' 
 
 TO/FROM 
 REGULATOR 
 ^ BOARD FOR 
 V(HEX INVERTER) 
 
 i 
 
 J 
 
 Figure 6.2. Physical Layout of Coefficient Storage and D/A Conversion Board 
 
58 
 
 Figure 6.3. Photograph Showing Coefficient Storage 
 and D/A Conversion Board in Its Tester 
 
59 
 
 V 4 O- 
 
 V3 O- 
 
 V 2 O- 
 
 V, O- 
 
 V o- 
 
 R /2 4 +8 4 V$ 
 
 — AAAr— 
 
 R /2 3 +8 5 
 vw— - 
 
 R /2 2 +8 2 
 wa, — 
 
 Ro/2'+S, 
 — aaa* — 
 
 R /2°+8 
 __wa, — 
 
 *— -*D/A OUTPUT 
 
 LM302 
 
 v.= { 
 
 V(l) FOR A LOGICAL I INVERTER OUTPUT 
 V(0) FOR A LOGICAL INVERTER OUTPUT 
 
 •..{ 
 
 8 j(|) FOR A LOGICAL I INVERTER OUTPUT 
 8 ; (0) FOR A LOGICAL INVERTER OUTPUT 
 
 I = BIAS CURRENT FOR LM302 VOLTAGE FOLLOWER 
 
 Figure 6.U Circuit Used for Determination of Ladder Resistors 
 
60 
 
 Summing currents at node V g : 
 
 V - Vi v-v v-v 
 
 S ]k , S V 3 , S 2 
 
 (R /16 ; 0j+ ) (R /8 + 5 3 ) (R Q A + 5 2 ) 
 
 V-V v-v 
 
 (R / 2 + 6l ) + tr^t + J ■ ° (6a) 
 
 Rearranging terms and multiplying through by R yields 
 
 V S { (1 ; & Q /R ) + (1 + 2 &1 /R ) + (1 + It6 2 /H ) + (1 + 85 3 /R ) + (1 * 16^/R^ 
 " V [ (l ; & Q /R ) ] + V(l + 2 &1 /R ) ] + V 2 [ (l ♦ te 2 /R ) ] + V 3 [ (l + 88 3 /R ) ] + 
 
 V a ; i6 6 ,/R ) ] - V (6 - 2) 
 
 Using a first- order approximation for the denominators in the above 
 expression (if o-/R n is small enough this will introduce negligible error) 
 we obtain: 
 
 & n 5, S p &-. S> 
 
 V q {31 - (■* + k =± + 16 =S + 64 J + 25 6 =it)J = 
 
 S R Q R Q R Q R Q R Q 
 
 Cr c; ft * Si 
 
 V (l - =2) + 2V,(l , 2 =i) + 4V (1- U-2) + 8v (1 - 8 -2) + 
 
 R Q 1 R Q 2 R Q 3 R Q 
 
 16V^(1 - 16 ~) - R Q I (6.3) 
 
 Dividing through by the term which multiplies V and using a first- 
 fa 
 
 order approximation again we have : 
 
61 
 V S "SI [V + 2V 1 + UV 2 + 8V 3 + l6 V + 7^2 t[V + 2V 1 + kV 2 + 8V 3 + l6 V 
 
 c _2 + k i + l6 ^ + 6J+ ^ + 256 Jt ]} i [v o + h 1 + 
 
 R o R o R o R o R o 31 ° R o 1 R o 
 
 5 p b Sk R n I -I 5 n S-, 
 
 i6v £ 5; + ^ 3 ^ + 256 \ ^ ] - £ { x + £ [ ^ + k i * 
 
 &o 8~, 5l 
 
 1 6 2 + 6U ^ + 256^]} (G.k) 
 
 R o R o R o 
 
 For R = 800 KJ2 (design value) and I = 30nA maximum, -rr- = .775 mv « 
 Thus the last term in equation (6.4) may be neglected as it is small and 
 varies little for small changes in the 5. 's. The equation for determining 
 the ladder resistor values now becomes: 
 
 V S = 31 [V + 2V 1 + kY 2 + 8V 3 + l6 V + ~^~2 {[V + 2V 1 + kY 2 + 8V 3 + l6 \ ] 
 5 B. 5 p S„ B. , 8 5-, 
 
 Using equation (6.5) it is seen that 
 
 V a (00000) = ~ [V(0) + 2V(0) + i+V(0) + 8V(0) + 16V(0)] = V(0) 
 V a ( 11111) = i [V(l) + 2V(1) + Uv(i) + 8v(i) + i6v(i)] = V(l) 
 
 exactly, as would be expected for a binary weighted resistor ladder feeding 
 an infinite impedance voltage follower. 
 
62 
 
 For each set of potential ladder resistors, R(0), R(l), . . ., R( J +), 
 one can calculate from equation (6.5) a. set of 31 voltage spreads or windows 
 "by subtracting [V (binary input a - l)] MAY from [V (binary input a)] for 
 a = 1, 2, . . . , 31. That is 
 
 w(a) - [VgCa)^ - [V s (a - l)^, a =1, 2, . . ., 31 (6.6) 
 
 From equation (6.5) it is seen that [V_(a - 1 )].,._, occurs for 
 
 R C = C VmIN and R(i) * [R ^ i)] MIN f ° r lo S ical 1 in P uts and R (i) = ^^^MAX 
 for logical inputs (i = 0, 1, . . . , h) . Conversely, [V (a)] occurs for 
 
 o IVLL1M 
 
 R C = [R C ] MAX ^ R(i) = [R(i) W f ° r lo § ical 1 in P uts ^ d R (i) = P^l^ 
 for logical inputs. 
 
 The criterion for obtaining the optimum set of ladder resistor 
 
 values is to maximize the set of numbers [W(oO]„,., T as a function of the ladder 
 
 ' MIN 
 
 resistor values. Although this becomes quite complicated mathematically, it 
 can be done in a quite straightforward manner using an iterative scheme on a 
 digital computer. One simply determines the [W(cc)] 's for a suitable range 
 of ladder resistors about the design value of R = 800 YSl. The range around 
 the resistor values giving the maximum [W(a)J can then be split up into a 
 finer mesh on a succeeding computer run. The computer program used to 
 accomplish this is listed in Figures 6.5 and 6.6. The printout of the values 
 [V (a)] , [V (a - l)] MAY j and W(a) for the optimum set of ladder resistors 
 is given in Figure 6.7. 
 
 For V(0) = Ov and V(l) ~ 5v, the MAX[W(a)] = 151.H35mv which 
 compares with l6l.l29mv for an ideal five bit D/A converter. Including UOmv 
 of ripple on the analog reference supply line and a DC drop of 30mv along the 
 etch that supplies the analog reference to the Hex Inverters, the minimum 
 
63 
 
 I 
 
 _2. 
 
 3 
 
 4 
 
 5 
 
 6 
 
 L 
 
 8 
 
 9 
 10 
 11 
 12 
 13 
 14 
 15 
 16 
 
 id 
 
 19 
 20 
 21 
 72 
 22 
 24 
 
 25 
 2b 
 71 
 
 28 
 
 2 9 
 30 
 31 
 
 32 
 
 33 
 34 
 
 35 
 36 
 3/ 
 
 3 6 
 39 
 
 40 
 
 VJUfl PAG-ES=Z5-. 
 
 REAL*8 R(5) 
 
 DI Hfc :NSIQN_ D( 5.2 .2 ) . V (2 ) . V L ( 32 ) . VH ( 32) .DEL t 32 ) . 
 
 CI NCI (32). INC2(32),TJL(5),0tLTAR(2) 
 REAO ( 5,1) R 
 I FGRMATIC10.3) 
 READ(5,1J TGL 
 WRITE (6.2) (R(I).rOL(I ).1=1.5) 
 
 RCL=565. 
 RCH=80C. 
 V(1)=C. 
 V(2)=5. 
 VHU ) = V(1 ) 
 
 ...._ _ . y.jLi.a2JL= \au 
 
 F=l./3l. 
 
 F=E/R0 
 DtL(l )=C. 
 C DELTA* IS THE AMCJNT dY WHICH tACH RESISTOR. R(I), IS 
 
 C DECREMENTED AT THE oTART OF tACH M 00 LuUP 
 
 ._ DELTA RI l)=.l 
 
 DO 30 M=l.3i 
 CO 40 L = h) 
 40 R(L)=R(L)-DELT AR( i) 
 DO 10 1=1.5 
 A = ( l.-ICL< I) ) *R( I) 
 B? (1 *t TGL IUUl*B (U 
 C=Ru/( 2.**( 1-1) ) 
 C O(I.J.K) I =3 IT POSITION J=l LOGICAL . 
 
 C J=2 LCGICAL I K=l LOW RESISTANCE VALUt, 
 
 C K=2 HIGH RESISTANCE VALUE 
 
 D( I. 1. 1)=A-C 
 
 0(1 .l,2)=ii-C ._ 
 
 U( 1.2. 1) = l( I. 1,1) +RCL 
 10 OH ,2.2)=DU,l,2)-t-RCH 
 K = 
 SCM=0. 
 
 CC 20 J 5= 1.2 
 DD 2 J 4 = 1. 2 
 J 3= 1.2 
 J2=l,2 
 Jl= 1.2 
 
 20 
 
 20 
 20 
 
 CC 
 
 DO 
 
 LL 
 
 G=E*(V(Jl)*2.*V(J2)+4.*>/(J3) + 3.*V(J4)+16.*V(J5)) 
 
 h = 4.*C( <:. J2. J2) 
 
 P = 16.*QI3,J3_..J3J.. ... 
 
 C=c4.*D(4.J4,J4) 
 
 S=25u.*C( 5. J5, J5) 
 
 Figure 6.5o First Half of Computer Program Used 
 to Determine Ladder Resistors 
 
6k 
 
 C K IS THE NUMBER OF THE OUTPUT VOLTAGE LEVEL* FROM I TO 1? 
 41 K = K*1 _ 
 
 C VL(K) IS THE WORSE CASE LOW OUTPUT VOLTAGE AT LEVEL K 
 
 42 VL m = G*il.±£*LDtl.Jl.Jli ±il±P_t fltS) l-F »(V tJll« J J I j J J i.4 1_ J 
 
 C*V{J2)*H*V{J3)*P*V(J4)*0*VU5)*S) 
 
 43 L1=3-J1 
 
 44 L2=3-J2 
 
 45 L3=3-J3 
 4o L4=3-J4 
 
 4 7- _.L5=3_-_*L5 
 
 48 H=4.*D(2, J2.L2) 
 
 49 P=16^*D(3.JJ,L3J 
 
 50 = 64. *C<4, J4.L4) 
 
 t>l S=256.*C(5.J5.L5.T 
 
 C VH(K) IS THE WORSE CASE HIGH OUTPUT VOLTAGE AT LEVEL K 
 
 52 VhlKlrG*(l,±f *IDilj.J.LtJ^LlJiHtJPtfltS_i)-JL*iy(.jn*Jl( ltJliLl ) 
 
 C+V(J2)*H+VIJ3)*P+V( J4)*0+V( Jb)*S) 
 
 53 INCUK)=K-l 
 
 54 INC2(K)=K-2 
 
 55 IF(K-l)20, 20, 15 
 
 56 15 0ELIK)=(VLIK)-VH<K-1))*1000. 
 
 57 SU* = SUM*VL<is)-VH(K-U 
 
 58 20 CCMTINLE 
 
 59 WRITEI6.2) (R II ) . TOL ( I ) . I = 1* 5 ) 
 
 60 2 FLRMATt 1H1,/, 10X, 15HKES1;>T0R VALOt S.2X .9HT0LERANCE » 1 » 1 t>X, 
 
 C4HUHMS.//. (11X.F12.4,4X,F7.4>) 
 ol WRITEI6.3) (INCUI ).VL(I).VH< I ),INC2(I), INCHl > ,0cL(I) , 
 
 CI=2»32) . .._.... .. . ._ 
 
 62 3 FORMAT!//. 5X.3HBIT, 5X, 10H V-OUTI LOW ) , 3X , 1 3HV-GUT ( H I oH ) *. 
 
 C4X.4HB1 rS,4X,6HWlNU0w./,l5X.5HV0LTS,9X,5H\/0LTS,4X, LH*, 
 C13X,4HM.V..//, (5X, 12. F 14. 5, F14. 5. 3X,1H*,3X .12.1H-, 12, Fl 1 . 4 
 C) ) 
 
 63 WRITEI6.4J SUM 
 
 64 4 FCRMATt //// , 5X . 16H SUM OF WINDOWS =,F7.4, 
 
 L34H VOLTS OUT UF 5.0000 VOLTS MAXIMOM) 
 
 65 30 CUNTIiMLfc 
 
 66 SILP 
 t>7 ti\0 
 
 Figure 6.6c Second Half of Computer Program Used 
 to Determine Ladder Resistors 
 
65 
 
 
 RESISTCR VALUES 
 
 TOLERANCE 
 
 
 
 
 
 CHHS 
 
 
 
 
 
 
 _ 799494,QCCC 
 
 QtOQIO 
 
 
 
 399o96.000G 
 
 g.goic 
 
 
 
 
 
 JlS9.696_.CCGC 
 
 ...... Q .00.10 
 
 
 
 
 
 99696. COCC 
 
 0.0010 
 
 
 
 
 
 49696. CCOO 
 
 0.0010 
 
 * 
 
 BITS 
 
 
 BIT 
 
 V-GUULCWl 
 
 V-OUT(HIGH) 
 
 WINDOW 
 
 
 VOLTS 
 
 __.VOLIS_ 
 
 _ * 
 
 
 M.V. 
 
 .1 
 
 C_,_L6_2_U 
 
 C. 32027 
 
 0.16038 
 0.32165 
 
 * 
 
 0- 1 
 
 160.2098 
 
 2 
 
 * 
 
 1- 2 
 
 159.3935 
 
 3 
 
 C.46C55 
 
 0.48251 
 
 * 
 
 2- 3 
 
 158.9017 
 
 4 
 
 0.64CC8 
 
 0.642 9 8 
 
 * 
 
 3- 4 
 
 157.5654 
 
 5 
 
 0.80047 
 
 0.80385 
 
 * 
 
 4- 5 
 
 157.4964 
 
 6 
 
 C.96C77 
 
 0.96464 
 
 * 
 
 5- 6 
 
 156.9186 
 
 L_ 
 
 1«-L2i2_ 
 
 1.27929 
 
 1 .12549 
 
 * 
 
 6- 7 
 
 7- 8 
 
 156. 5939 
 
 a 
 
 1.28535 
 
 * 
 
 153.79 52 
 
 9 
 
 1 .44004 
 
 1.44633 
 
 * 
 
 3- 9 
 
 154.6869 
 
 10 
 
 1.60C72 
 
 1.60 726 
 
 * 
 
 9-10 
 
 154.3961 
 
 11 
 
 1,76155 
 
 1 .768 21 
 
 * 
 
 10-11 
 
 154.2 8 83 
 
 12 
 
 1.92202 
 
 1.92907 
 
 * 
 
 11-12 
 
 153.8095 
 
 13 
 
 ._2.0 8 29b 
 
 .2.0_9CC4.._.. 
 
 * 
 
 ...1.2-1 3 _ 
 
 .....1.53.38 96 
 
 14 
 
 2.24388 
 
 2.25099 
 
 * 
 
 13-14 
 
 153.8362 
 
 15 
 
 2.4C469 
 
 2.41194 
 
 * 
 
 14-15 
 
 153.8963 
 
 16 
 
 2.563CC 
 
 2.5 739 2 
 
 * 
 
 15-16 
 
 151.1402 
 
 17 
 
 2.72504 
 
 2.73547 
 
 * 
 
 16-1 J 
 
 151.1135 
 
 18 
 
 2.88701 
 
 2.89 703 
 
 * 
 
 17-18 
 
 151.5446 
 
 19 
 
 3.G4 90.4._ 
 
 .3__0 5_5 5... 
 
 *... 
 
 13-19 _ 
 
 __. .152. 01.57 
 
 20 
 
 3.21114 
 
 3.22028 
 
 * 
 
 19-20 
 
 152.5 8 79 
 
 21 
 
 3.37329 
 
 3.38 18 1 
 
 * 
 
 20-21 
 
 153.0113 
 
 22 
 
 3.5 3549 
 
 3.54339 
 
 ♦ 
 
 21-22 
 
 153.O806 
 
 23 
 
 3.69771 
 
 3. 7C4 91 
 
 * 
 
 22-23 
 
 154.3179 
 
 24 
 
 3.86100 
 
 3.86791 
 
 * 
 
 23-24 
 
 156.0883 
 
 25 
 
 4...C2JLi>4) _ 
 
 ._.4_. 02 95 5. 
 
 * 
 
 _24-25 
 
 L5 5.5_9.2 
 
 26 
 
 4.18610 
 
 4.19127 
 
 * 
 
 2^-26 
 
 156.5456 
 
 27 
 
 4.34867 
 
 4. 3 5289 
 
 * 
 
 26-27 
 
 157.3963 
 
 28 
 
 4.51172 
 
 4.51501 
 
 * 
 
 2 7-2 8 
 
 158.3297 
 
 2 9 
 
 4.67441 
 
 4.676o5 
 
 * 
 
 2 8-29 
 
 159.4038 
 
 30 
 
 4.83724 
 
 4.83838 
 
 * 
 
 29-30 
 
 160.5930 
 
 31 
 
 4.99999 
 
 4.91.9.99 
 
 .*_ 
 
 ... 30-31. 
 
 J 6.1 -_6 J, 2 5 
 
 SUM OF wilNDUkS = 4.8251 VOLTS JUT JF 5.0000 VOLTb MAXIMUM 
 
 Figure 6.7. Printout of Final Results of Ladder Resistor Computer Program 
 
66 
 
 window is still greater than - LSBo The individually adjustable levels of 
 the coefficient QRAS driver (see section 6.k and reference (5)) are set at 
 the midpoint of each D/A converter window. 
 
 6.3 Analog Reference Regulator 
 
 Since the Hex Inverters are separated into groups according to their 
 saturation voltage, the difference between the logical 1 voltage level and the 
 logical voltage level is kept constant at 5v by having a Hex Inverter 
 reference supply that is adjustable for each of the 32 large coefficient 
 storage and D/A conversion boards. A schematic of the circuit used is given 
 in Figure 6.8. It is composed of an integrated circuit regulator and a 
 resistor divider with potentiometer to set the output voltage at any value 
 between k.^v and 6v. The circuit has excellent temperature characteristics 
 and a drift over several hours of less than 5mv at full load (1.3 A). 
 
 To protect the "J 10 comparators which are fed by the output of the 
 D/A converters, the regulator is fused at its input and also has a current 
 limiting resistor, 4.7 ohms, at its output. 
 
 6.k Coefficient QRAS Driver 
 
 In order to compensate for the DC offset caused by the different 
 saturation voltages of the Hex Inverter transistors, the QRAS drivers have 
 their DC levels adjustable over a + 300mv range. The schematic for one QRAS 
 driver board (8 circuits to drive a total of 8 x 2 x 32 = 512 comparators) is 
 shown in Figure 6.9. The DC component is added with a simple resistive summing 
 network. 
 
 Each QRAS driver is terminated in 50 ohms to eliminate reflections. 
 The .^7uF capacitors attached to pins 2 and -6 of the NH0002C current buffer 
 are used to filter the .voltages at those pins to values below the supply 
 
67 
 
 '3 
 
 > (9 
 
 in w 
 
 I 
 
 + 2 
 
 n6 
 
 
 to Ul 
 
 «5 y 
 
 -VA ( |- 
 
 a 
 
 (0 
 
 pq 
 
 0) 
 
 -p 
 
 > 
 
 H 
 
 X! 
 
 
 W 
 
 o 
 
 Ph 
 O 
 
 a5 
 
 a> 
 
 0) 
 
 o 
 a) 
 
 CD 
 
 <& 
 
 M 
 O 
 
 5- 
 
 00 
 
 vo 
 
 bo 
 
 s<? 
 
 A 
 
 > 
 
 o 
 
 
< UJ 
 
 Z K 
 
 *r < <r 
 
 M) UJ 
 
 U1 > 
 
 (O « g 
 
 > ° ° 
 
 o Q- 
 
 </) 
 
 </l 
 
 I g g 
 
 o 5 uj 
 
 x I ? 
 
 o I It 
 
 < o o 
 
 UJ o > 
 
 68 
 
 
 
 ■H 
 En 
 
69 
 
 voltages. This reduces the power dissipation of the NH0002C. The constant 
 current source at the output also helps to keep the NH0002C dissipation at a 
 safe level. 
 
70 
 
 7. OUTPUT DATA CHANNEL 
 
 7.1 Output Data Channel Block Diagram 
 
 Once one of the three basic Trans formatrix modes of operation has 
 been selected by the computer operator (Fourier Transform, Array Transform, or 
 Coordinate Transform ) and the proper (b . . .) coefficients are being produced 
 as SRPS's, there still remains a sizeable amount of computation to be done 
 before a z-axis drive signal can be applied to the output CRT.* First, for 
 each output point (k,i) the 1,02^4- coefficient SRPS's multiply the 1,02*4- input 
 light intensity SRPS's pair-wise using digital AND gates. Then a resistive 
 network performs the required summing of the AND gate outputs. The analog 
 (input light intensity and coefficient) voltage to SRPS converters (710 analog 
 
 comparators) and the multiplication and summation circuitry are contained on 
 
 (5) 
 32 large printed circuit boards . A block diagram of the output data 
 
 channel, showing the processing which takes place subsequent to the multi- 
 plication and summation, is given in Figure "J. 2.. 
 
 The outputs of the 32 SRPS multiplication and summation boards, 
 
 A. (i = 0,1, . . ., 31) ? are fed into a 32 input integrator in order to obtain 
 
 1 31 
 
 a voltage -which is proportional to the quantity, Z D v «- - x - •• The integrator 
 
 i,j=0 k ^ 1J 1J 
 output, -V, is manipulated by the following circuitry to obtain the desired 
 
 z-axis drive signal. 
 
 The first stage of the output circuitry inverts -V and subtracts 
 
 from V the average voltage (stored with a sample and hold circuit) computed 
 
 * A complete discussion of the generation of the horizontal and vertical 
 deflection amplifier signals and the blanking circuitry for the output 
 display CRT can be found in reference (12). 
 
f UJ 
 
 > 
 
 71 
 
 
 
 
 
 
 
 < 
 
 
 
 s 
 
 1 
 
 
 
 
 _l 
 
 £E 
 UJ 
 
 > 
 
 UJ 
 
 > 
 O 
 
 
 O 
 
 (T 
 
 
 
 <r 
 
 O 
 
 Z 
 
 Ld 
 
 IT 
 O 
 
 * 
 
 U. 
 
 _J 
 
 Z 
 1 
 
 a. 
 
 UJ 
 
 m 
 
 5 
 
 z 
 
 z 
 
 < 
 
 3 
 
 3 
 O 
 
 O 
 
 
 
 en 
 
 t- 
 
 a. 
 
 t- 
 
 O 
 
 Ld 
 
 to 
 Z 
 UJ 
 CO 
 
 -e 
 
 o >— D 
 
 UJ 
 
 -I o 
 
 0- ° _l 
 
 2 « O 
 
 < z 
 
 CO 
 
 V Q. 
 
 I- z 
 cc — 
 
 p 2 
 
 t — r 
 
 T~T 
 
 
 >"* 
 
 I o I 
 
 3 r 1- 
 
 H 
 
 •H 
 
 BWiL. 
 
72 
 
 on the special averaging cycle used for all three operations. Since in many 
 cases the average is quite close to the succeeding inverted integrator outputs, 
 V, a stage of gain, G, is provided. This result, G(V - AVG), is then squared. 
 A sensing stage follows the first stage. If the integrator output, 
 
 -V, is < -lOv, the Integrator Overload output goes to a logical and an 
 indicator on the control panel is turned on. Similarly, if |G(V - AVG) I > 10v. 
 
 the Amplifier Overload output goes to a logical and another indicator on the 
 control panel is turned on. The Unblanking output goes to a logical when- 
 ever the Z-Axis Drive < Threshold. 
 
 p 
 The final output of the first stage, [G(V - AVG)] , feeds the second 
 
 stage. Under the Array Transform and Coordinate Transform, the input itself 
 
 and the square root of the input are made available at the output. Under 
 
 the Fourier Transform, the |Re[F(k,i)]| and |lm[F(k,i)]| are treated the same 
 
 as the Array Transform and Coordinate Transform except that the computational 
 
 cycle is twice as long. The |F(k,i)| however calls for additional processing. 
 
 2 
 On one 32o5|is cycle, Im [F(k,i)] is calculated and stored by the sample and 
 
 2 
 hold circuit at the input to the second stage. On the next cycle Re [F(k,i)] 
 
 2 2 
 
 is calculated and the outputs of the second stage are {Re [F(k,i)J + Im [F(k,i)] 
 
 A' 
 
 and VRe [F(k,i)] + Im [F(k,i)J. 
 
 The third stage consists of a log amplifier, a square root module 
 and two relays. The third stage output is any of: linear, log, square, or 
 square root depending on the output mode selected by the computer operator. 
 At the end of each computational cycle this output is sampled and held for 
 the length of the next cycle, providing the desired Z-Axis Drive for the 
 output CRT. 
 
73 
 
 7-2 Output Data Channel Circuitry 
 
 In order to present as clear a picture as possible of the output 
 data channel the details of all the circuits mentioned in the preceeding 
 section are covered in the next eight sections. 
 
 7.2.1 Multiplication and Summation of Coefficient and 
 Input Light Intensity SRPS ' s 
 
 Figure 7*2 illustrates the approach taken to perform the multi- 
 plication and summation of 32 pairs of coefficient and input light intensity 
 SRPS's. A high speed TTL AND driver, the MC3026, is used as the stochastic 
 multiplier. In order to obtain a standardized output from each of the 32 AM) 
 gates contained on a single printed circuit board, the AMD's are selected on 
 a per board basis according to their logical 1 and logical output voltages 
 with a 510 ohm load. The voltage spreads are: 
 
 V. (l): 12mv spread maximum on each board; a total 
 of eight groups 
 
 V (0) : 50mv spread over all 32 boards 
 
 As a result of the fast rise and fall times of the AND's (< 5ns) 
 and the length of etch driven by the output of each AND (up to 18 inches), it 
 is necessary to terminate the end of the sum line in 510 ohms/32 ~ 16 ohms. 
 
 It is easy to show that the input to the differential amplifier 
 is given by: 
 
kHi30> 
 x i30> 
 
 bkfci28>- 
 x i28> 
 
 t> kfii2 >- 
 x i2 > 
 
 bk<uo>- 
 
 x iO> 
 
 MC3026 
 
 o 
 
 o 
 
 o 
 
 R 
 ■AA/\r 
 
 R 
 ■A/VNr 
 
 R 
 
 R 
 -VNAr 
 
 /77 
 
 R 
 
 R 
 
 R 
 ■AAV 
 
 MC3026 
 
 •&> — r~\ — ^ k * i31 
 
 V_J < X '3I 
 
 CK 
 
 <3 
 
 DIFFERENTIAL 
 AMPLIFIER 
 
 I 
 
 Ai = Klb k «iiXi 
 
 kk2i29 
 x i29 
 
 <b k4 
 
 <Xi3 
 
 13 
 
 bkfi.il 
 
 < x il 
 
 j=o 
 
 IJ A,j 
 
 bklij = COEFFICIENT SRPS 
 X ij = LIGHT INTENSITY SRPS 
 R=DALE MFF, 5I0&, 1/4 W, .1%, T~2 
 R, = DALE MFF, 16X2, I/4W, 1%, T~0 
 
 7 h 
 
 Figure 7.2. Multiplication and Summation of Coefficient 
 and Input Light Intensity SRPS's 
 
75 
 
 31 RR.. 
 
 V = Z V [-= ± ], i = o,l, . • ., 31 (7.1) 
 
 j=0 J R + 32 • RR 
 
 1 31 
 \*6k z V ij (7.2) 
 
 -where V. . is the output of the (i,j) AND gate and R ~ R/32. 
 
 7.2.2 Differential Amplifier Buffer 
 
 A buffer is needed between the output of the resistive summing net- 
 work shown in Figure 7-2 and the input to the 32 input integrator. The 
 differential amplifier configuration illustrated in Figure 7„3 was chosen to 
 facilitate the adjustment of the analog sum output voltage, A. 
 (i = 0,1, . . . j 31), of each board to a single standard value. 
 
 The 200 ohm pot in the emitter leg of the constant current sink 
 transistor varies the DC level of the output voltage over a 2v range. The 
 5 Kft pot placed between the emitters of the differential transistors is used 
 to adjust the gain of the amplifier from approximately 1.25 to 2 giving an 
 AC output swing of 2v to 3v. 
 
 In practice the balance and gain pots are both set to give a 6v to 
 8.5v full scale output voltage swing for each board. This voltage range 
 represents approximately one-half of the full scale balance and gain 
 adjustments . 
 
 7.2.3 Thirty- Two Input Integrator 
 
 Each one of the 32 SRPS multiplication and summation boards produces 
 
 an output, A. , which must be summed, integrated, and normalized over a 32.5M-S 
 
 (or 65u-s for |Re[F(k,i)]| and j Im[F(k,i) ] | ) cycle to produce each point of the 
 32 x 32 output display. 
 
76 
 
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77 
 The circuit which sums and integrates the A. 's is shown in Figure "J.h, 
 It is an integrator of textbook design with a multiple capacitor feedback 
 network. Any combination of capacitors may be switched into the feedback path 
 of the integrator, under operator control, depending on the operation being 
 performed and the average brightness of the input picture. The resulting 
 variation in gain is over 500:1. At the end of each cycle the integrator is 
 reset to the saturation voltage of the 2N28°AA by a positive pulse at the 
 reset input. 
 
 The A. 's have a DC component of about 6v. This is offset by the 
 270 ohm resistor in series with the 200 ohm pot to -15v. The pot is adjusted 
 to obtain zero integrator output with [A.] = 0. The 510 ohms to ground at 
 the input of each A. was experimentally found to be the best AC termination 
 
 for the A. 's. 
 
 1 
 
 7.2.4 Output Circuit-First Stage 
 
 The first stage of the output circuit is shown in Figure 7*5. 
 The integrator output, -V (Ov to -ikv) , is inverted by the first 715 op 
 amp and limited to a Ov to +12.75v output swing by the zener diode in the 
 feedback loop. This protects the comparator in the sense stage „ The second 
 715 op amp subtracts, at unity gain, the average inverted integrator output 
 calculated on the special averaging cycle from the output of the first 715 • 
 The third 715 supplies the required gain. A 10 turn pot located on the 
 control panel varies the voltage at the Gain input from Ov to +5v causing the 
 Vactec VTL2C3 photo- coupler 's resistance to vary from ~ 10 Mfi to ~ 1 Kfi. This 
 provides a gain variation of about 60 to 1, which is necessary since the 
 difference between the inverted integrator output, V, and the average input 
 light intensity, AVG, calculated on the special cycle, can vary anywhere 
 
RESET >—^VW 
 
 A > 
 
 A. > 
 
 5K 
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 78 
 
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 NOTE: 
 
 ALL RESISTORS CARBON, I/4W, 5% UNLESS 
 
 OTHERWISE SPECIFIED 
 
 EXCEPT 5K-DALE MFF, 1/4 W, 1%, T-2 
 
 POT-HELITRIM MODEL 79P 
 
 RELAYS -MAGNACRAFT IOIMPCX-1 
 
 (NORMALLY OPEN CONTACTS) 
 
 47 M F 
 
 -I5V 
 
 Figure 7.U. Thirty-Two Input Integrator 
 
79 
 
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 between 150mv to lOv. A Hybrid Systems IO7C Multiplier/Divider module 
 performs the squaring function on the output of the third 715. 
 
 7.2.5 Sample and Hold 
 
 Three sample and hold circuits are used in the output data channel 
 of Transformatrix. They perform the following functions: 
 
 1. Store a voltage corresponding to the average light intensity of the 
 input picture for an entire frame (33ms). 
 
 2. As an intermediate step in the (Fourier Transform) generation of |F(k,i)|, 
 a sample and hold stores Im2[F(k,i)J for one cycle (32. 5M-S ) . 
 
 3. Store the final CRT Z-Axis Drive signal for approximately 30us. 
 
 The configuration of the sample and hold is illustrated in Figure 7.6 
 The first LM302 voltage follower buffers the input signal. Upon application 
 of a +3v sample pulse the 2W5638 FET is switched into its low IL region and 
 the .OOlnF capacitor (.01|1F capacitor for 33ms sample and hold) is charged 
 (or discharged) to the input voltage » The 100 ohm resistor from pin 5 of 
 the input LM302 to -15v provides the LM302 with extra drive capability for 
 large input changes. The acquisition time is 2.5us maximum for a lOv input 
 change (.OOluF capacitor sample and hold circuits). When the sample pulse re turi 
 to Ov, the FET is switched off with a maximum leakage of InA. The 200pF 
 capacitor in parallel with the 39 Kfl current limiting resistor speeds up the 
 turn-on and turn-off times of the FET switch. The second IM302 acts as a 
 high input impedance isolator for the output voltage. The 30 Kfl input 
 resistors of both IM302's prevent the IM302's from oscillating when driven 
 with fast (> 10v/p.s) rise and fall time signals. The 30 KQ, in parallel with 
 the 3pF input capacitance of the LM302 slows down the input signal enough so 
 the 10v/p,s output slew rate of the IM302 is not exceeded at the input. 
 
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 The accuracy of the circuit is 1% full scale for both an abruptly- 
 changing input with a 32. 5M-S hold time and a slowly changing input with a 
 33ms hold time. 
 
 7.2.6 Output Circuit - Sense Stage 
 
 Because of the vast difference in coefficients generated under the 
 three operations and the variety of possible input patterns, a wide range of 
 gains had to be incorporated into the integrator and the first stage of the 
 output circuitry. In order for the operator to be aware of when either or 
 both of these two circuits is operating in the non-linear region as a result 
 of too much gain, the appropriate voltages are sensed by this stage and 
 indicators on the control panel display the result. The first 710 in Figure 
 7.7 detects whenever the integrator output < -lOv. The second pair of 710' s 
 detect whenever |G(V - AVG) | > lOv. The Unblanking output goes to a logical 
 (-» blank Z-Axis Drive) for G(V - AVG) < Ov (except under the Fourier 
 Transform when it is desired to display the absolute value of negative 
 spectral coefficients) and for Z-Axis Drive < Threshold. 
 
 It was mentioned in Chapter k that the Threshold front panel control 
 can be used under the Array Transform to differentiate between nearly equal 
 light intensities in the output pattern. Additionally, it is also useful 
 in preventing low level noise on the Z-Axis Drive signal from being displayed. 
 
 7.2.7 Output Circuit - Second Stage 
 
 For the Array Transform, Coordinate Transform, |Re[F(k,i)] | , and 
 |lm[F(k,i)] I , the relay in Figure 7.8 is closed. The Hybrid Systems IO7C 
 Multiplier /Divider is hooked up to provide the square root function, 
 output = - i/lO • Z, and so the linear output is available, with correct 
 polarity, at the output of the second 715 °P amp. 
 
 
83 
 
 INTEGRATOR £ * 
 
 OUTPUT > W- 
 
 SUM -AVERAGE > » 
 
 H-AXIS DRIVE > 
 THRESHOLD 
 (+IV TO -6V) 
 
 MC3026 
 
 . UNBLANKING 
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 ALL RESISTORS CARBON, I/4W, 5% UNLESS OTHERWISE 
 
 SPECIFIED 
 
 ALL SWITCHING DIODES - IN4I48. 
 
 Figure 7.7. Output Circuit - Sense Stage 
 
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 p 
 In the F(kji) mode the relay is open. During one cycle Im [F(k,i)] 
 
 is computed and stored with a sample and hold. The next cycle generates 
 
 2 
 Re [F(k,i)] and the first 715 adds these two voltages. The output of the 
 
 / 2 p 
 
 second 715 then gives the desired result, VRe [F(k,i)] + Im [F(k,i)]. 
 
 The square root module must be trimmed with the 20 Kfi pot such that 
 Ov in gives Ov out. 
 
 7.2.8 Output Circuit - Third Stage 
 
 The third stage, illustrated in Figure 7*9? is comprised of the final 
 two Trans formatrix output operations: the log and square root of the linear 
 output. The log is performed with a Philbrick-Nexus ^350 log amplifier which 
 gives a Ov to -kv output for a +.lv to +10v input. The following 715 inverts 
 the log output and normalizes the signal swing to Ov to +10v„ The diode in 
 the 715 feedback loop prevents the 715 from going negative when the log 
 amplifier output goes positive (for linear inputs < ,lv). The square root 
 operation is implemented in exactly the same manner as in the second stage 
 of the output circuitry. 
 
 Application of the four combinations of inputs (+5v and floating) 
 to the two relays results in the four output modes of Trans formatrix: linear, 
 log, square and square root. The three modes in addition to the linear mode 
 were chosen as representative of the types of mathematical operations that 
 can be performed on the linear output signal, Y,g» Once y „ is computed, it 
 is obviously quite easy to insert a module to perform any arbitrary mapping 
 
 of y ki- 
 
 Experimentally it was found that the squaring operation acts as anon- 
 linear noise suppressor, giving relatively less gain to small signals and more 
 gain to large signals. Conversely, the log and square root operations tend 
 to enhance the lower level signals. 
 
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 8. EXPERIMENTAL RESULTS AND CONCLUSIONS 
 
 8.1 Experimental Results 
 
 The Trans formatrix system, as described in this thesis, has been 
 fully operational since February, 1971? thus placing at our disposal the 
 world's most parallel computing device, establishing by its existence new 
 levels of speed and performance: over 60 million operations per second. 
 Photographs of the front and back of Trans formatrix are presented in 
 Figures 8.1 and 8.2. 
 
 All three operations implemented in Transformatrix and described in 
 Chapters 3> ^, and 5 fully realize the original design goals. As surmised, 
 the quality of the output picture display is best for the Fourier Transform. 
 This is because points of interest in the output picture correspond to many 
 coefficients being equal or close to 1 (-1) multiplying light areas in the 
 input picture. Under these circumstances the signal to noise ratio in the 
 summing of the product SRPS's is quite good. This is to be contrasted with 
 the Coordinate Transform in which only one coefficient = 1 and the other 
 1,023 coefficients = 0. In this case the signal to noise ratio in summing 
 the product SRPS's is not quite as good as for the Fourier Transform. For 
 this reason there is some noise in the Coordinate Transform output picture. 
 The effect can be muted by proper balance of the threshold and gain controls 
 and by using the squaring mode of operation. The Array Transform falls some- 
 where between the Fourier Transform and Coordinate Transform in performance. 
 The output picture is realtively noise free and a 5 x 5 subsection of the 
 input pattern can be recognized even when there are other 5x5 subsections in 
 the input pattern which differ from the one in question by only a small 
 amount „ 
 
Figure 8.1. Front View of Trans format rix System - Panels Removed 
 
89 
 
 Figure 8.2. Back View of Trans formatrix System 
 
90 
 
 8.2 Conclusions 
 
 The design and construction of a working Trans formatrix system has 
 demonstrated the feasibility of using the SRPS scheme of number representation 
 in a large scale machine. In the Trans formatrix system the advantage of using . 
 SRPS's as information carriers is the extremely inexpensive arithmetic element 
 (multiplier -* AND gate) which is used in 1,02U parallel computational channels. 
 It is hoped that the future designers of parallel systems with relatively in- 
 variant and simple operations in each channel will give due consideration to 
 the possible advantages of substituting stochastic ideas for the more classical 
 purely digital or purely analog techniques. In some sense stochastic 
 processing allows us to enjoy the best of both the analog and the digital 
 world. 
 
91 
 
 APPENDIX 
 
92 
 
 Al. Computing Using Stochastic Sequences 
 
 A Synchronous Random Pulse Sequence (SRPS) is a sequence of 
 
 standardized pulses, each of which has the same height and the same width 
 
 (= clock period for Transformatrix) such that the pulse repetition rate 
 
 changes at random about the average value f and the instant of occurrence 
 
 of each pulse, if it occurs, is controlled by a central clock for the whole 
 (3), (18), (19) 
 
 system. 
 
 A typical SRPS is shown in Figure Al.l. 
 
 V - | 1 | 1 | 1 
 
 o 1 , » 
 
 h — H 
 
 CLOCK 
 PERIOD 
 
 Figure Al.l. Synchronous Random Pulse Sequence 
 
 The probability of occurrence of a pulse in a time slot represents 
 the machine variable. The machine variable is related to the original 
 analog variable input in the following way: 
 
 mapping 
 analog variable input * machine, variable 
 
 < machine variable < 1 
 
 If f is the clock frequency and f the average repetition rate of a SRPS. 
 the machine variable is given by: 
 
 u = Probability (v(t) has a pulse in a time slot} 
 f 
 
 u = 
 
 "0 
 
 
93 
 
 If the pulse train shown in Figure Al.l is typical of the entire sequence. 
 
 then the machine variable it represents = — . 
 
 Multiplication using SRPS's is especially simple. In Figure A1.2 
 the product of the machine variables represented by SRPS's v (t) and v At) 
 is obtained by feeding v, (t) and v (t) into a 2 input AND gate. 
 
 v,(t) >- 
 v t (t): 
 
 =r> 
 
 -* v,(t) 
 
 v,(t) 
 
 
 > 
 
 
 
 
 
 
 V - 
 
 
 
 
 
 
 
 ■"■ 
 
 
 
 1 
 
 1 
 
 
 1 
 
 U,= f 
 
 v,(t) 
 
 v °~ I 1 I 
 
 p 1 1 1 * 
 
 v s (t> 
 
 v o- I 
 
 1 1 1 1 1 1 * 
 
 J s= S 
 
 Figure A1.2. Multiplication of SRPS's 
 
 u = P {v„(t) has a pulse in a time slot) 
 o 5 
 
 - P {v (t) and v (t) both have a pulse in a time slot} 
 
 Assuming that v (t) and v (t) are mutually independent 
 
 u„ = P {v, (t) has a pulse in a time slot) x 
 P ( v p(t) has a pulse in a time slot) 
 
 = u x • u 2 
 
9h 
 
 To recover the machine variable (as a voltage in the range 0-1 volV 
 represented by a SRPS, one integrates the SRPS over an interval T = nTo 
 and normalizes the result. 
 
 u = 
 
 nT V 
 o o " o 
 
 nT 
 
 v(t)dt. 
 
 T = clock period 
 o 
 
 V = pulse height 
 o 
 
 As n -» oo, u approaches the number which is represented by the SRPS v(t). 
 For finite n, the distribution of the number is described by a binomial 
 distribution, if the occurrence of a pulse in a time slot is independent 
 of any other occurrence. 
 
 The standard deviation from the average number of pulses for a 
 given averaging time T = nT is given by 
 
 o = Vnu(l-u) 
 
 The 2a variance "with respect to the full scale value of u is 
 
 A 
 
 = J^ik^l x 200% 
 
 For n = 255, A is graphed in Figure A1.3- 
 
 A (%) 
 
 u - PROBABILITY 
 
 Figure Al.3. A vs. u 
 
95 
 
 LIST OF REFERENCES 
 
 1. Barnes, G. H. , et al., "The ILLIAC IV Computer," IEEE Transactions on 
 
 Computers , Vol. C-17, August 1968, pp. 7^6-757- 
 
 2. Chen, Tien Chi, "Parallelism, Pipelining, and Computer Efficiency," 
 
 Computer Design , January 1971? PP« 69-7^ • 
 
 3. Poppelbaum, W. J., Afuso, C. and Esch, J. W. , "Stochastic Computing 
 
 Elements and Systems," AFIPS Proceedings , 1967 FJCC, Vol. 31, 
 pp. 635-6kk. 
 
 k. Ryan, L. D., "TRANSFORMATRIX, A Stochastic Image Processor" (abstract), 
 a paper presented orally at an IEEE Computer Group Symposium on 
 Uncommon Forms of Information Processing, Northwestern University 
 Evans ton, Illinois, May 1, 1969* 
 
 5. Marvel, 0. E., "Transformatrix - An Image Processor - Input and Stochastic 
 
 Processor Sections," Report No. 393 5 Department of Computer Science, 
 University of Illinois, Urbana, Illinois, April 1970« 
 
 6. Ryan, L. D., "Quarterly Technical Progress Report," Hardware Systems 
 
 Research, Section 2, Department of Computer Science, University of 
 Illinois, Urbana, Illinois, January 1968 to December 1970 • 
 
 7. Poppelbaum, W. J., et al. , "On-Line Fourier Transform of Video Images," 
 
 Proceedings of the IEEE , October 1968, pp. 1744-17^6. 
 
 8. Andrews, H. C, "Fourier Coding of Images," USCEE Report No. 271, 
 
 Electronic Sciences Laboratory, University of Southern California, 
 Los Angeles, California, June I968. 
 
 9. Shively, R. R., "A Digital Processor to Generate Spectra in Real Time," 
 
 IEEE Transactions on Computers , Vol. C-I7, May 1968, pp. U85-U9I. 
 
 10. Dere, W. Y. and Sakrison, D. J., "Berkeley Array Processor," IEEE 
 
 Transactions on Computers , Vol. C-19, May 197 0, PP« hkk-kh'J . 
 
 11. Tolstov, G. Po , Fourier Series (translated from Russian by R. A. Silverman) 
 
 Prentice-Hall, Englewood Cliffs, N. J., 1962. 
 
 12. Wo, Y. K., "The Output Display of Transformatrix," Report No. 381, 
 
 Department of Computer Science, University of Illinois, Urbana, 
 Illinois, February 1970* 
 
 13. Deutsch, Sid, "A Technique for Feature Extraction in Visual Pattern 
 
 Recognition," Pertinent Concepts in Computer Graphics (Proceedings 
 of the Second University of Illinois Conference on Computer 
 Graphics) edited by M. Faiman and J. Nievergelt, University of 
 Illinois Press, Urbana, 19^9? PP« ^-8-66. 
 
96 
 
 15. 
 16. 
 
 17. 
 18. 
 
 Schroeder, Manfred R., "Images from Computers," IEEE Spectrum , March 1969, 
 pp. 66-78. 
 
 Applications Engineering Department of Hybrid Systems Corporation, 
 Digital- to-Analog Converter Handbook , First Edition, 1970. 
 
 Stephenson, B. W., Analog - Digital Conversion Handbook . Digital 
 Equipment Corporation, 1964. 
 
 Schmid, Hermann, "An Electronic Design Practical Guide to D/A Conversion" 
 (edited by Frank Egan), Electronic Design , October 24, 1968, 
 pp. 49-88. 
 
 Afuso, C, "Analog Computation With Random-Pulse Sequences," Report No. 
 255, Department of Computer Science, University of Illinois, 
 Urbana, Illinois, February 1968. 
 
 19. Esch, J. W., "Rascel - A Programmable Analog Computer Based on a Regular 
 Array of Stochastic Computing Element Logic," Report No. 332, 
 Department of Computer Science, University of Illinois, Urbana, 
 Illinois, June 1969. 
 
97 
 
 VITA 
 
 Lawrence David Ryan was born in Syracuse, New York on 
 July 1, 19^3* He graduated from Christian Brothers Academy, 
 Syracuse, New York in 1961. In 1965 he received his B.S. in 
 Electrical Engineering from the University of Notre Dame. 
 Mr. Ryan continued his education at the University of Illinois 
 in September of 1965 under a NSF Traineeship and joined the 
 Circuit and Hardware Systems Research Group of the Department 
 of Computer Science under Professor W. J. Poppelbaum in February 
 of 1966. He has been employed by the Department of Computer 
 Science as a Research Assistant in that group since February 
 of 1967. He received his M.S. in Electrical Engineering in 
 October of 19^7 and since then has continued to work under 
 Professor W. J. Poppelbaum toward a Ph.D. degree. 
 
 He is a member of Tau Beta Pi, Eta ivappa Nu, and the 
 IEEE. 
 
jrmAEC-427 U.S. ATOMIC ENERGY COMMISSION 
 
 fSIi^oi UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR 
 
 DISPOSITION OF SCIENTIFSC AND TECHNICAL DOCUMENT 
 
 ( Sm Instructions on Rwtna Side ) 
 
 AEC REPORT NO. 
 
 coo 1^69-0179 
 
 2. title SYSTEM AMD CIRCUIT DESIGN OF THE TRANSFORMATRIX 
 COEFFICIENT PROCESSOR AND OUTPUT DATA CHANNEL 
 
 TYPE OF DOCUMENT (Check one): 
 
 f~1 a. Scientific and technical report 
 
 r~l b. Conference paper not to be published in a journal: 
 
 Title of conference 
 
 Date of conference 
 
 Exact location of conference. 
 Sponsoring organization 
 
 E]c. Other (Specify) Ph.D. Thesis 
 
 RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): 
 
 KM a. AEC's normal announcement and distribution procedures may be followed. 
 
 I I b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. 
 
 [~1 c. Make no announcement or distrubution. 
 
 REASON FOR RECOMMENDED RESTRICTIONS: 
 
 SUBMITTED BY: NAME AND POSITION (Please print or type) 
 
 Lawrence David Ryan, Research Assistant 
 
 Organization 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 Signature 
 
 jpCtfAArtJ^A^ , 1Y Vn(kv^. 
 
 March 3, 1971 
 
 FOR AEC USE ONLY 
 
 AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION 
 
 RECOMMENDATION: 
 
 PATENT CLEARANCE: 
 
 LJ a. AEC patent clearance has been granted by responsible AEC patent group. 
 LJ b. Report has been sent to responsible AEC patent group for clearance. 
 LJ c. Patent clearance not required. 
 


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