510.84 no. 629-630 cop. 2 ILLINOIS— UNIVERSITY AT URBANA- CHAMPAIGN-' DEPT. OF COMPUTER SCIENCE REPORT ii hivrj CENTRAL CIRCULATION BOOKSTACKS The person charging this material is re- sponsible for its renewal or its return to the library from which it was borrowed on or before the Latest Date stamped below. You may be charged a minimum fee of $75.00 for each lost book. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result In dismissal from the University. TO RENEW CAll TELEPHONE CENTER, 333-8400 UNIVERSITY OF IUINOIS tIBRARY AT URBANA-CHAMPAION SEP 2 ? 1996 DUL 3 2001 When renewing by phone, write new due date below previous due date. L162 UIUCDCS-R-TU-630 yr^ti ERGODIC: COMPUTING WITH A COMBINATION OF STOCHASTIC AND BUNDLE PROCESSING by JAMES R. CUTLER March, 197^ THE LIBRARY OF THE f 5 197M DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS i Digitized by the Internet Archive in 2013 http://archive.org/details/ergodiccomputing630cutl UIUCDCS-R-J^-foO ERGODIC*: COMPUTING WITH A COMBINATION OF STOCHASTIC AND BUNDLE PROCESSING by JAMES R. CUTLER March, 197^ Department of Computer Science University of Illinois at Urban a- Champaign Urbana, Illinois 6l801 Supported in part by the Office of Naval Research (ONR) under grant No. N000 1U-6T-A-0305-OOOT. ACKNOWLEDGMENT The author wishes to thank his advisor, Professor W. J. Poppelbaum, for suggesting this topic and for his support and guidance. He will also like to thank Frank Serio and his staff for fabricating the circuit cards, Bert Seimnelink for his technical skills, Evelyn Huxhold for typing the rough drafts, Mark Goebel and his staff for the drawings in this report, and Dennis Reed for the publication of this report. Special thanks is due to his wife, Joyce, for her encouragement and perseverance. Ill TABLE OF CONTENTS Page I. INTRODUCTION 1 II. BACKGROUND OF STOCHASTIC PROCESSING 2 III. BASICS OF ERGODIC 1+ A. Overall View of ERGODIC U B. Number Representation ----------------- 1+ C. Generation of an Ergodic Bundle ------------ 1+ D. Arithmetic Operations ----------------- 7 E. Processing of Ergodic Bundles --_-_--______ 10 IV. IMPLEMENTATION OF ERGODIC 12 A. The Ergodic Generator Unit -------------- 12 B. The Arithmetic Unit -13 C. Processing Unit --------------------22 D. Overall View 27 V. IMPROVEMENTS AND SUGGESTIONS 28 LIST OF REFERENCES 32 APPENDIX 33 IV LIST OF FIGURES Figure Page 1 ERGODIC Block Diagram - 5 2 Plot of the function, f(x) 6 3 Block Diagram of the Arithmetic Unit ------------ 8 k Circuit Diagram of an Arithmetic Sub-unit --------- 9 5 Block Diagram of an Ergodic Generation ----------- ±k 6 Block Diagram of Arithmetic Unit -------------- 15 T Block Diagram of a Randomizer --------------- 16 8 Loading Direction of the Sorter Stage of the Randomizer ----------------------- 18 9 Timing Diagram of a Randomizer ---------------20 10 Space Average of the Result Bundle for Multiplication - - - 23 11 Block Diagram of the Processor ------------- --2^ 12 Block Diagram of Revised Ergodic Generator ---------29 13 Block Diagram of the Interconnections of many Arithmetic Units (A.U. ) 31 LIST OF TABLES Table Page I. List of Arithmetic Operations -----_---______ 21 I. INTRODUCTION This paper describes a stochastic computer called ERGODIC proposed by Professor Poppelbaum. In ERGODIC numbers are represented in a bundle of wires (called an ergodic bundle) by two methods. First, a number is represented by the number of wires in the bundle that are energized at any instant of time. (A wire in the bundle may be in one of two states: energized or de-energized). Also, the same number is represented by the number of times any particular wire is energized over a certain period of time: This redundancy allows one to check a bundle for errors . ERGODIC is made up of three units: the generators, the arithmetic unit, and the processor. A generator converts a number into an ergodic bundle. Two ergodic bundles are then inputted into the arithmetic unit, which performs an arithmetic operation (multiplication, addition or subtraction). The output of the arithmetic unit is also an ergodic bundle. This bundle then goes to a pro- cessor which determines the number represented, and checks each wire in the bundle for any discrepancies from this answer. II. BACKGROUND OF STOCHASTIC PROCESSING The "basis for all stochastic processing is quite simple: Numbers are represented as probabilities of appearance in a random sequence. Two such sequences are then "multiplied" by merely inputting them into an AND gate. Stochastic processing, as developed at the Information Engineering Laboratory at the University of Illinois under the guidance of Professor Poppelbaum, progressed through several stages. The RPS ( Random Pulse Sequence )- System was the first attempt at stochastic processing. In this system the sequence con- sists of pulses occurring at random times and having random length and random height. The average duty cycle of this sequence is measured to obtain the data. Some digital logic was used but overlapping pulses cause problems. The SRPS ( Synchronous Random Pulse Sequence )- System immediately followed. In this scheme the pulses of the sequence occur (or do not occur) during prede- termined time slots and have fixed length and height. The data is obtained by counting the number of pulses in a given number of time slots. Digital logic is used exclusively. The next design resolved the difficulty of representing numbers other than those from to 1 (the range of numbers that can be directly interpreted as probabilities): The Remapped SRPS-System accomplished the representation of numbers in the range of -1 to +1 by mapping them into the range for proha- bilities (0 to l). Then followed the Two Wire Remapped SRPS-System , which is able to represent all numbers: Each number is expressed as the ratio of a numerator and a denominator, the range for both the numerator and the denomi- nator being from -1 to +1. The numerator and the denominator are both mapped into probabilities (0 to l) as above. A new flavor of probabilistic processing came in when the concept of bundle processing was suggested: A number of wires made up a bundle and each 2 6 wire could be in one of two states. ' Probabilities can now be assessed by taking the number of wires in a given state, divided by the total number of wires in the bundle. The advantage of this concept is that it is f ailsoft ; i.e. if a wire is cut or broken, the number that is represented is still approximately the same. In a final step, the marriage of bundle processing and stochastic processing has led to ERGODIC. The property of an ergodic bundle is that each wire in the bundle has a sequence of pulses with a probability (time average!) identical to that of the bundle at any given instant (space average!) Comparing time and space averages now obviously leads to conclusions about the validity of the representation. III. BASICS OF ERGODIC A. Overall View of ERGODIC There are three major parts of ERGODIC: l) the ergodic generators, 2) the arithmetic unit and 3) the processor. Figure 1 shows the block diagram of these units. An ergodic generator takes a number within a certain range (-1 to +1 in steps of — ) and represents this number in the ergodic bundle. The arithmetic unit takes two such bundles and performs arithmetic operations (addi- tion, subtraction, and multiplication). The processor obtains a result from the resultant bundle of the arithmetic unit and also checks the bundle for any defective wires. A further description of each of these parts follows. B. Number Representation An ergodic bundle consists of 6h wires (this choice seems arbitrary but it turns out that implementation of the system is simplified. See section on implementation of ERGODIC). It is obvious that every number in the form: •7T- where N = 0,1,..., 6k may be represented in the bundle. But since the arithmetic operation of subtrac- tion is going to be performed, it seems logical to be able to represent negative numbers by remapping; i.e. y = f(x) where < x < 1 and y includes negative num- bers. The range of y and the definition of the function, f , are determined by the arithmetic unit; the criterion being to keep the circuitry of the arithmetic k unit as simple as possible. The range of y was chosen to be from -1 to +1 and the function, f , was given by: y = f(x) = 2x -1. Figure 2 shows the plot of the function, f. C. Generation of an Ergodic Bundle As stated before, an ergodic bundle is one in which the average number of pulses which occur over a certain period of time (time average) is equal to the 52 5 OO gST tf)UJ tf)Q UlO oo OUJ (TO a.— W-, LlJ -I o f(x)=y Fieure 2. Plot of the function, f(x) average number of wires within the bundle which are energized at any instant of time (space average). The requirements necessary for this part of the system are : 1) the two ergodic generators should be independent of each other. This property is necessary in order to obtain the correct answer from the arithmetic unit: It can be shown that the time sequences must not be correlated! 2) the circuitry of a generator should be as simple as possible. The actual method of generating the ergodic bundle is described in a later section. D. Arithmetic Operations The basic concept for the arithmetic unit is that one wire from each bundle goes into a sub-arithmetic unit which performs a particular arithmetic operation. Thus, the arithmetic unit requires as many arithmetic sub-units as there are wires in a bundle. The outputs of all of the arithmetic sub-units then make up the resultant bundle. The block diagram of this unit is shown in Figure 3. The most important requirement for the arithmetic sub-unit is that it should be kept as simple as possible. An advantage to stochastic computing is that the arithmetic unit is simplified and requires only a single gate for each arithmetic k S operation. ' Because of the number representation chosen, an OR gate is used for addition, an Exclusive OR gate is used for subtraction, and an Exclusive OR gate is used for multiplication (assuming that positive numbers are inputted). An AND gate is also needed; for example, when two negative numbers are added. Figure h shows the circuit diagram of an arithmetic sub-unit. Note that if all of the wires of the bundle go through inverters and the space average is x, the result is (l-x). This corresponds, of course, to taking LU _) Q Z => CD h z < Z> V) cr -I o 3 CD m LU _i o z ffi a d o •H -P 0) " — ' £3 (U rj H -P T3 •H £ Z ^> 0) cd ,G -P a •H Si crt . * » 3 1 => ne o o u p l- 2 UJ < 2 to »- 5 K 5 ° < 5 10). 12 IV. IMPLEMENTATION OF ERGODIC A. The ERGODIC Generator Unit This unit receives a 7-bit digital number and represents this in the ergodic bundle. This digital number uses the signed absolute value system to represent numbers between -1 to +1; i.e. b 6 b 5 \ b 3 b 2 b l b * '- 1 ' .l b i 2 1 " 5 (Note that it is possible to represent numbers less than -1 and greater than +1 but the circuitry merely interprets those numbers as -1 and +1, respectively). After inputting the desired number, it is transformed into a fraction between to 1 by the mapping shown in Figure 2. This fraction then determines how many wires are energized in the ergodic bundle. For example: Let Y be the number to be represented, X be the fraction represented in the bundle and N be the number of wires to be energized. Suppose Y = - 5/32 then X = -|(Y+l) = 27/6U and N = 6U X = 27 Now the question arises: How does one transform the bundle into an ergodic bundle , i.e. a bundle where the time average equals the space average? Obviously, if each wire has an identical pulse sequence, the bundle is not ergodic. The trick is to redistribute the energized wires from time slot to time slot: This guarantees that the time average of the pulse sequence is constantly equal to the number represented by the bundle! Practically we use an N-bit shift regis- ter, with n bits at 1. If the shift register is connected so that it is circu- lar, the number of bits at 1 will remain at n. Thus, the space average at any instant is — . If any bit of the shift register is considered, the time average of that bit being at 1 is — , if the sample period is Nx or a multiple of Nt 13 (— is the frequency of the shift register-shifts/sec). Thus, a N-bit circular shift register is a simple ergodic generator! The problem with an N-bit circular shift register is that the sequence re- peats itself after Ntime slots. Thus the randomness of the sequence is determined by how many wires there are in a bundle. This problem is resolved in the arith- metic unit. Since the N-bit circular shift register is by far the simplest ergodic en- coder, the decision was made to use it in ERGODIC. The block diagram showing this arrangement for generator is shown in Figure 5. A discussion about ergodic generators follows this section. B. The Arithmetic Unit This unit performs the arithmetic operations of addition, subtraction and multiplication. This section will describe the methods and circuitry needed to complete the above operations. First., addition and subtraction will be described and then multiplication. In bundle processing, addition is accomplished by ORing two wires — each coming from the two different input bundles — together: The proper result will be obtained providing that both wires are not energized together. In other words, the two bundles must be disjoint . Subtraction is accomplished by EXCLUSIVE ORing two wires together: The result is correct if the energized wires of the sub- tracted bundle overlaps the energized wires of the other bundle. These two con- ditions are contradictory, and it appears that subtraction and addition cannot both occur in the same system... This problem is solved by a unit called a randomizer . The block diagram of the arithmetic unit with the randomizers included is shown in Figure 6. A detailed diagram of a randomizer is shown in Figure 7- The randomizers essen- tially rearrange the data of the bundle according to information of the bundle Ik a o •h Id o o •H O bO U W o w •H Q a o H pq 0) , IE no 15 en Ll) x o to oe UJ a. o 5 £ -p a) -p •H E 3 O u bO aJ •H Q M o O H W U •H P>4 3 CD Ui _l o z CD 16 w z p I I §5? r A. CD a CO cc< CO *" t (- (- Q CD If- (fl (t P> co uj ° DC CO — =H CD h- 1- 1- Q m U. co IX i I CD < K"> CO CC r CM 0- < Z K — CO '_ I- (- <-> m u. co cc w I o n cc L to cc I- l_ w t f- J- Q CD If- CO CC CVJ X C9 < ro CO lu ° CC 1 CD n •H g Cfj O bO Cfj •H Q >! o o H pq 0) bD •H IT and the arithmetic operation to be performed. Thus, during subtraction the ran- domizers causes the "bundles to overlap and during addition it causes the bundles to be disjoint. The signal names, A. and B. where 1 < i < 6U , indicate where these wires are connected with respect to the corresponding lines in the arith- metic sub-unit shown in Figure h. The essential pieces of information are the signs of the two numbers repre- sented that are being inputted into the arithmetic unit. The randomizer makes it possible to look at just one bit to determine the sign! In Figure 7 the input stage stores a particular space average (which is identical to the time average) of the ergodic bundle. The sorter stage then arranges the l's and O's of this stored space average so that all of the l's are together at one end and the O's are together at the other end. Since the 32nd bit determines a space average of greater than or equal to 1/2 (32/6*0 [which represents the number, 0; Y = 2X-1 = 2(— ) -1=0], the 32nd bit determines whether the represented number, Y, is positive or negative. Now by knowing the signs of the represented numbers and the arithmetic operation, it may be determined whether the two bundle should be disjoint or overlapping. The loading of the sorting register is now determined: For bundle A the l's are loaded from top to bottom, i.e. the l's are located from A to A and the O's are located A , to A^, , where x is the number of l's. For bundle B and the x+1 04 ' arithmetic operation of addition, the l's are loaded starting at B and going toward B . If these bits become filled, then B^, through B__ are used. For the operation of subtraction, bundle B is loaded so that B _ through B^, is filled first, and then B through B . These loading directions are shown in Figure 8. It should be mentioned that the rearranged l's and O's of the sorter stage take on a new significance. Suppose the bundle A is taken as an example. If the represented number is positive, the first 32 bits (A - A ) will be l's and the next 32 bits may or may not be l's depending on the number. Then the first 32 bits A) A, A 2 A S3 A J4 A 6 4 18 / / J B, B 33 B 34 • • • B 6 4 >-\ V v B, B„ B 3 4 • • • B 6 4 B) C) Figure 8. Loading Direction of the Sorter Stage of the Randomizer a) shows loading direction of "bundle A, b) & c) shows loading direction of bundle B for addition and subtraction operations, respectively 19 may be considered the sign portion of the bundle and the last 32 bits may be considered the number portion . That is, if two positive numbers are being added, the sign portion of the result bundle should be kept intact but the number portion should show the sum of the two number portions of the input bundles. On the other hand, if the represented number is negative, the first 32 bits (A - A ) may or may not be 1' s, depending on the number. The last 32 bits will be O's. Thus the last 32 bits now indicate the sign portion and the first 32 bits repre- sent the number portion. This reversal makes it necessary to change the loading direction of the sorter stage of bundle B. After the sorting stages impress the proper configuration onto the bundle, it is necessary to load the sign portion of the bundles with the proper level, so that the result bundle has the proper sign and the overflow circuitry works pro- perly. For example, in the case of adding two positive numbers, one of the sign portions of the bundles must return to 0, since the overflow circuitry would indicate a false overflow. Figure 9 shows the timing diagram of the entire cycle of a randomizer. Table I indicates this loading procedure as well as the gate necessary and overflow enable controls for given signs of the represented numbers and the arithmetic operation. All that is necessary to make the resulting bundle ergodic is that the two sorter stages be connected in a circular fashion and move in synchronism. The arithmetic operation of multiplication is a different story: The necessary condition for this operation is that each bundle must be independent of one another. Note that rearranging is not necessary (as in the subtraction and addition operations). Suppose that the two sorter stages are loaded inde- pendently of one another (these stages are moving at the same shifting speed). This independence is not enough, since — once loaded — one bit of the sorter stage of one randomizer will forever look at the same bit of the sorter stage of 20 i t- x ^ ^** "S * vt u Q Ct O uj H < z er < uj z CO LU < o Z K W o i_ co _ _ * 3 Q. Z UJ < UJ 1- I co (- cr z UJ 1- QC z O o to < 2 IT LU I t- O U. o z h- — z LlI X Q h- LU 1- X ct o o — (0 X * to z LU 111 O 2 <1 1- 1- to i n lll H < X u. o i 1- X X o to LU LU CE X O z < to cr. LU III 1- 1- to 2 a to z LU cr LU tr Q e LU LU z 2 i- d 3 Z 2 to qj m 2 w 5 «/> < kQ < _l 2 t— o tc CO 17) o Q tr (/) o Q tr as 21 TABLE I. List of Arithmetic Operations Subtraction Multiplication Addition A - B B - A A & B both R. = A. + B. R. = A. © B. R. = A. € B. — ill ill ill positive R. = A. $ B. 111 Overflow if Overflow dis- Overflow dis- A. -B. = 1 abled (last 32 abled (first 32 Overflow i i (first 32 bits of A bits of B are bits of A are disables first loaded first loaded with O's). with O's). are first (One sorter loaded with O's). stage is mov- ing 6k shifts A negative R. = A. § B. R. = A. -B. R. = A. + B. faster than ill l 11 ill & B pos- the other). Overflow dis- Overflow if Overflow if itive abled (last A. -B. = 1 A". -B. = 1 32 bits of A i l (last 32 bits l l (last 32 bits are first loaded with l's). of B are first of A are first loaded with O's). loaded with l's). _ — A positive R. = A. € B. R. = A. + B. R. = A. -B. ill ill l 11 & B neg- Overflow dis- Overflow if Overflow if ative abled (last A. -B. = 1 A. -B. = 1 32 bits of B are first l l (first 32 bits of B are l l (first 32 bits of A are loaded with l's). first loaded first loaded with l's). with O's). A 8e B both R. = A. -B. R. = A. € B. R. = A, 9 B\ negative l 11 ill ill Overflow if Overflow dis- Overflow dis- A. -B. = 1 i l (last 32 abled (last abled (first 32 bits of A 32 bits of B bits of A are first are first loaded with loaded with are first l's). l's). loaded _ _ - 1 with l's). (The subscript, i, indicates the respective bits of the inputs and the output. 1 < i < 6k). 22 the other randomizer. Thus, the result bundle will indicate a fraction anywhere between 1-x -x and min (x ,x ) where x and x are the fractions indicated in the input bundles and min (*,') is the minimum value of the two numbers. The corresponding represented numbers are y and y (y = 2x -l) and, therefore, the desired result bundle should indicate y i y 2 = (2x i -l) ( 2x 2 -l) = Ux i x 2 " 2(x i +X 2 ) + 1 It may be shown that y y lies between 1-x -x and min (x ,x ) . Thus, by chance the appropriate result may be obtained. The answer to this problem is to shift one sorter stage Gh_ times faster than the other, instead of moving them in unison. This difference in shifting speeds results in each bit in one sorter stage being able to respond to each of the bits of the other sorter stage. Now the result bundle obtains the proper time average answer, x, where x = x 1 x 2 + (l-x ) (l-x 2 ) = 2x ± x 2 - (x^Xg) + 1 and y = 2x-l = hx x - 2(x +x ) + 1 (This answer is obtained after 6hx6h shifts). Unfortunately, this shift dif- ferential does not solve the problem completely. The space average now does not remain constantly equal to the time average . But the average of the space average is equal to the time average. This phenomenon is shown in Figure 10. C. Processing Unit This unit has two functions. First, it receives the result bundle and determines the represented number of that bundle. Second, it compares each wire's time average with an overall average. The overall average will determine the represented number and may be determined by a number of methods. The purpose of all checks is to see if a wire of the bundle has been destroyed or if an arithmetic sub-unit associated with that wire is not functioning properly. 23 SPACE AVERAGE l-(x+y) 64y 64(l-x) 64(l-x+y) 64 65 TIME (ASSUMING THAT x>y, x+y o to u UJ u (9 o z IE a. z k o o m < o o ■H. ■<». < 00 U o W w 0) o o PM £1 -P Ch O U bD oj •H Q M o o H PQ r-\ 3, •H P>4 26 the problem of the space average of the result bundle vhen the arithmetic unit is multiplying. The actual circuitry of ERGODIC has four time average processors. The multiplexer shown in Figure 11 is formed of four 16- to -1 multiplexers. By using this arrangement, we save one-fourth of the time required to check the time averages of all of the wires in the bundle. This amount of time, T, (to check all of the wires) is: T = l6nx where n = number of shifts that each counter looks at one particu- lar wire and t = time period of one count pulse In this case, n = 6k x 6k = 1+096 and x = 1+00 ns , then T - 26.2 ms. The average time, t, to determine the time average of a wire is: JL 6k t = -7T- T - 1+10 ys. Note that n may be made smaller but the result obtained when the arithmetic opera- tion of multiplication is being performed will be inaccurate. The processing unit may be speeded up only by increasing the counter speed (decreasing x). The minimum value for x is approximately 1+0 ns. Thus, the minimum values for T and t with the accuracy being retained are: T - 2.6 ms. and t - 1+1 ys. Of course, if speed is more vital than accuracy, these times, T and t, may be decreased more. Note here that when the arithmetic operations of addi- tion and subtraction are being performed, the accuracy is maintained when n = 61+. Thus, the values for T and t are (assuming that x = 1+00 ns.): T - 1+10 ys. and t = 6.1+ ys. 27 D. Overall View One thing that has not been pointed out so far is that all three units — the Generators, Arithmetic Unit, and the Processor — are independent of each other and connected only by the bundles which are the transmitters of the in- formation. As a consequence, these units may be located wherever it is con- venient or necessary. Since this information is redundant throughout the bun- dle, there is no problem with losing this information by the destruction or cutting of part of the bundle. Thus, this system would be ideal for a dangerous environment where space is at a minimum; i.e., a submarine or a space ship. 28 V. IMPROVEMENTS AND SUGGESTIONS There are several improvements one could think of: l) the elimination of the randomizers in the arithmetic unit by making the ergodic generators more random, 2) the increase of the number of types of arithmetic operations per- formed by the arithmetic unit, 3) the improvement of ability of the system to do complicated calculations by increasing the number of arithmetic units and the introduction of a memory. By using an ergodic generator that is more random (one that repeats only after a large number time slots), it is possible to eliminate the randomizers located in the arithmetic unit. Suppose that there exists a random sequence generator for each of the N wires in the bundle: If each of the N generators presents the same time average, and the space average is approximately equal to the time average, the bundle will be ergodic. [By approximately we mean the space average, S, to be within a small range, A, of the time average, T: S = T + E where |e| < A < l]. It is speculated that the randomness of this generator is directly related to the magnitude of the range, A. The circuitry should still be kept at a minimum and thus, N-random generators would not be feasible and probably not necessary since they are not independent. (Because of the space average, these generators must be dependent upon one another). A more reasonable solution would be to have a random generator for a time average and a random generator that would then determine the space average. Suppose that one random generator fills an N-bit shift register, so that the last N outputs of this generator are stored in the shift register. The other genera- tor could now determine how many shifts the shift register will take in the next n shifts (n < N). An N-bit buffer is connected to the shift register and is loaded every t sec. Thus, the speed of this "ergodic generator" is — shifts/sec, x Figure 12 shows the block diagram of this generator. 29 2 O 2 o: 5 o < t- o •H o !h W 0) K ■ 2 SW1 > 4 SW2 >- 8 SW3 >■ 10 SW4 > 9 SW5 > 39 SW6 > 47 yn>— in> :*H> :3E> ^>oi-l SI> ^E>^=iG> — ; -Ji> : =0 ;dtU>^ 10 G> tSQ> ^ >§* iifSw. io is> 13 Is* 1 i£> -> IN 1 3 ->IN2,3 5,6 ->IN4-7 11-14 "• y 15-2 5 22 16-23 23-30 -> IN24-31 31-38 ■> IN32-39 40-46,48 ■> IN40-47 49-56 ■> IN48-55 57-64 -> IN56-63 65-72 -> IN64 1 Figure A-2. Input Card 36 oo -VW- <2> 4. r-l O If) < r-l (VI CVJ 2 CVJ HW-" ©Is oo r-l K— ■<§> H iHs) — WN^o) <3 o T3 o o H O Jh 0) -p CO cd S I < 3 ■H ^(~<2) -VW- a. oo CO 4. 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Expanded Display Control Card 51 4 B > 6 C > 8 > 10 OFT > TMOO Figure A-l8. Lamp Driver Card 52 Figure A-19 . Front View of ERGODIC UNCLASSIFIED Security Classification DOCUMENT CONTROL DATA • R&D (Security classification of title, body ol abstract and indexing annotation must be entered when the overall report is classilied) 1 ORIGINATIN G ACTIVITY (Corporate author) Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 6l801 2a. REPORT SECURITY CLASSIFICATION Unclassified 2b GROUP 3 REPORT TITLE ERGODIC: COMPUTING WITH A COMBINATION OF STOCHASTIC AND BUNDLE PROCESSING 4 DESCRIPTIVE NOTES (Type ol report and inclusive dates) Technical Report March, 197*+ 5 AUTHORfS.) (Last name, first name, initial) Cutler, James R. 6 RFPORT DATE March, 197 h 7« TOTAL NO. OF PAGES 60 7 b NO. OF REPS 6 8a. CONTRACT OR GRANT NO. N000 14-67-A-0305-0007 b. PROJECT NO. 9a- ORIGINATOR'S REPORT HUMBBR(S) 96. OTHER REPORT NO(S) (A ny other numbers that may be assigned this report) 10 AVAILABILITY/LIMITATION NOTICES 11 SUPPLEMENTARY NOTES 12 SPONSORING MILITARY ACTIVITY Office of Naval Research 219 South Dearborn Street Chicago, Illinois 6060U 13 ABSTRACT A system called Ergodic which combines stochastic processing and bundle processing is described. Its background, theory, implementation are discussed in full as well as several suggestions for the improvement of this system. An appendix is included which shows all of the circuit cards used to implement Ergodic. The system generates Ergodic bundles, performs arithmetic operations (multiplication, addition, and subtraction) on Ergodic bundles and then deter- mines the information in the Ergodic bundle and also checks for failures in the system. DD FORM 1 JAN 64 1473 UNCLASSIFIED Security Classification BIBLIOGRAPHIC DATA SHEET 1. Report No. UIUCDCS-R-7U-630 3. Recipient's Accession No. 4. Title and Subtitle ERGODIC: COMPUTING WITH A COMBINATION OF STOCHASTIC AND BUNDLE PROCESSING 5. Report Date March, 197I+ 7. Author(s) James R. Cutler 8. Performing Organization Rept. °' UIUCDCS-R-7U-6^Q 9. Performing Organization Name and Address Department of Computer Science University of Illinois at Urban a- Champaign Urbana, Illinois 6l801 10. Project/Task/Work Unit No. 11. Contract /Grant No. N000 114-67-A-0305-007 12. Sponsoring Organization Name and Address Office of Naval Research 219 South Dearborn Street Chicago, Illinois 6060U 13. Type of Report & Period Covered Technical 14. 15. Supplementary Notes 16. Abstracts A system called Ergodic which combines stochastic processing and bundle processing is described. Its background, theory, implementation are discussed in full as well as several suggestions for the improvement of this system. An appendix is included which shows all of the circuit cards used to implement Ergodic. The system generates Ergodic bundles, performs arithmetic operations (multiplication, addition, and subtraction) on Ergodic bundles and then deter- mines the information in the Ergodic bundle and also checks for failures in the system. 17. Key Words and Document Analysis. 17a. Descriptors Stochastic processing Bundle processing Ergodic bundle Space average Time average 17b. Identifiers/Open-Ended Terms 17c. COSATI Field/Group 18. Availability Statement 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED FORM NTIS-35 (10-70) 21. No. of Pages 22. Price USCOMM-DC 40329-P71 tffc Z<) fll* n >. s UNIVfBSITY OF ILLIHOI8URBAMA 3 0112 002541370