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 - ^ ^ DIGITAL COMPUTER lABORATORY 
 
 14-5' 
 
 '^-^ UN.TVERSITY OF ILLINOIS 
 
 ^' URBANA^ ILLINOIS 
 
 REPORT NO, 145 
 
 THE TRANSFER MEMORY 
 by - 
 S. R, Ray 
 
 August l6p 1963 
 
 This work was supported in part "by 
 Contract NOo AT(11-1)-1018 of the Atomic Energy CoKmission 
 
lo Introduction 
 
 The design of the ILLIAC III; a general-purpose Information processing 
 computer_^ calls for a specialized memory unit to mediate -che flow of 
 information from the primary processing logic (the "stalactite" array) to 
 the control and hulk storage areas (the "control computer" )o One opera- 
 tional function of this specialized niemory unit;, called the Transfer 
 Mem.ory (TM);, is based on xne disparity in word length between control 
 computer words (32 bits) and stalactite words (102^ blts)„ The TM affords 
 a high-speed means of word length conversion by allowing information to be 
 rea.d or written as either short words (32 bits) or long words (1024 bits). 
 Bi-directional operation is the phrase used here to describe this property » 
 
 It is also necessary that the TM be addressable on an information- 
 content basis o This requirement^, which is described in Section VI^ arises 
 from the need for rapid access to the typically few words in the TM proper 
 which contain vital Information. The addresses of such word.s can be 
 deterrrilned only by Infonnatlon content;, however. 
 
 The device which enables content addressibility^ the Pyramidal Readout 
 
 Encoder (PRE); is functionally distinct from the ^'Transfer Memory proper" 
 
 and iS; therefore^ discussed separately. At the circuitry level; however^ 
 
 the PRE and TM partially merge, 
 
 II, General Design 
 
 A, Specifications 
 
 The general specifications of the Transfer Memory are as follows:. 
 
 1, Size, 32.,768 bits arranged in a 32 x 102^4- matrix, 
 
 2, Operating Modes: Random Access^ F'arallel Read and Write Modes 
 in either of two subrnodes „ 
 
 (a) Long Word Submode--the 32^768 bits arranged as 32 lG24-bit 
 words o 
 
 (b) Short Word, Submode--the 32; 7^8 bits arranged as 1024 words 
 of 32~bit length. 
 
 Tbe phrase '90 buffer'' is also in occasional use with regard to row-column 
 interchanges of information; especially with respect to punr'hed cards, 
 
 -1- 
 
It is necessary that the information in the Transfer Memory be 
 readable in either submode independent of the submode in which 
 the inform_ation was written. Briefly^, the submodes must be 
 compatible o 
 
 It is convenient to consider the TM "normal" configuration 
 as 1024 32-bit wordS; in which case the short -word submode 
 corresponds to a "parallel -by-word'' operation while the long-word 
 submode is a "parallel-by-bif' operationo 
 
 B. Basic Considerations 
 
 Magnetic cores were chosen as the basic storage elements of the 
 TMo Their general availability^ adiAantages for bi-directional operation^, 
 and ease of driving clearly overshadow the virtues of other components. 
 
 Operation in the long word subm.ode for wb_ich 102^ bits must be 
 handled is a particularly influential factor in establishing the design 
 outlines . Tb.e 102^ sense amplifiers and digit drivers required, by the 
 long words constitute more electronics than a large _, standard -variety 
 computer memory. It is therefore proper to r>oncentrate special effort 
 on economy and reliability of these circuits » 
 
 For example,, the number of turns of the sense windings is two 
 rather than one in order to decrease the required sense amplifier gain 
 and the digit current. The unusual shortness of the sense windings 
 (32 bits) is also a substantial advantage in minimiizing tb.e recovery 
 time of the lines^ although it does not simplify the sense amplifier 
 much. Destructive m,ode switching of the cores also provides relatively 
 easily amplified signals at the cost of cycle tiirxe^, of course, 
 
 Ix is possible to economize by using som^e drivers in two roles^ 
 either as "digit drivers" or as "write drivers" depending upon the 
 submode , 
 
 C. Core Mode 
 
 The magnetic cores are operated, in a nearly com^plete switching 
 mode;, that is 8C to 9O per cent of the fliox is switched. This mode 
 is attractive in a numiber of respects. An 80~90 jier cent setting 
 provides maximum, signal amplitude per unit drive current (83 per cent 
 
 -2- 
 
p 
 
 setting In some Mg-Mn cores). The time for switching is substantially 
 less than that required for complete switching (about 2/3) and the 
 stability of the flux state approaches that of a completely switched 
 core. 
 
 Ill, Organization 
 A. General 
 
 The general organization of the TM is recognizable as an 
 elaboration of word-organized core mem.ory techniques. Bi-directional 
 operation complicates the terminology to the extent that a brief 
 explanation is necessary. 
 
 Referring to Fig. III.l;, during the READ portion of a memory 
 cycle ^ the read drive is produced by the simultaneous operation of 
 one of n read "source '" drivers and one of m read "sink." drivers j, 
 where n ■■ m > the number of words. The sense signals from the 
 selected word are amplified and gated to the register or "buffer" 
 flipflops. Rewriting of the buffer information occurs during the 
 "write" portion of the mem.ory cycle. A "write driver" delivers 
 current to the word which was previously read out. Simultaneous ly^ 
 the "digit drivers" (one driver per bit) are either turned on or 
 remain of,f depending upon the state of their associated flipflop^ i.e. 
 upon the information just delivered from, the cores in the case of a 
 cycle for reading the stored information. 
 
 Note that the term ''digit driver" is used in the sense of "the 
 driver which is controlled by the buffer register during the writing 
 portion of the cycle"' and that the term ''write driver" mieans "the 
 driver which selects the w ord into which information is written." 
 Specifically^ these terms refer to the operational use of a driver 
 during a given memory cycle^ not to a particular physical circuit. 
 
 2 
 
 Ray^ S. R._, "Engineering Model of a Partial Switching Effect in Ferrites_," 
 University of Illinois^ Digital Computer Laboratory_, Report Wo. 111^ 
 September I96I. 
 
 -3- 
 
LRS 
 LRK 
 
 SRS 
 
 SRK 
 
 LWD 
 
 SWD 
 
 LS 
 
 SS 
 
 LB 
 
 SB 
 
 LA 
 
 SA 
 
 Long Word Read Source Driver 
 Long Word Read Sink Driver 
 Short Word Read Source Driver 
 Short Word Read Sink Driver 
 Long Word Write Driver 
 Short Word Write Driver 
 Long Word Sense Amplifier 
 Short Word Sense Amplifier 
 Long Word Buffer Register 
 Short Word Buffer Register 
 Long Word Address Register 
 Short Word Address Register 
 
 WL - Word Line Long 
 WS - Word Line Short 
 RL - Read Line Long 
 RS - Read Line Short 
 
 LB (102^) 
 
 r 
 
 Address (A) 
 
 Gate 
 
 SWD 
 (IO2U) 
 
 Gate 
 (A) 
 
 r 
 
 1024 
 bits 
 
 Core 
 Array 
 
 LA 
 (5) 
 
 D 
 e 
 
 n 
 O 
 
 d 
 
 e 
 
 r 
 
 k lines 
 a»- 
 
 8 lines 
 
 LRS 
 
 LRK 
 (8) 
 
 ms 
 
 WL 
 
 RL 
 
 RS 
 
 Select 1 of 32 Drivers 
 per Sector for 
 Write Long Word 
 (8 sectors ) 
 
 Select 1 of 1024 Drivers 
 for Write Short Word 
 
 32 bits 
 
 SB 
 (32) 
 
 LWD 
 1 (32) 
 
 SRS I SRK 
 (32) I (32) 
 
 L 
 
 32 
 
 Lines 
 
 I <i 
 
 32 
 Lines 
 
 Decoder 
 1 
 
 SA (10) 
 
 (Z) 
 
 Gate 
 
 Address (Z) 
 Figure IIl.l. Conjiection of Drivers and Amplifiers to Core Array 
 
 -k- 
 
B. Core Matrix 
 
 The core matrix for the TM. is arranged as eight planes of 
 32 X 128 cores per plane. Each core is linked by four windings as 
 indicated in Fig. III.l and nam.ed as follows: 
 
 lo Read Long Word Winding (RL)--I turn- -conducts the read current 
 in long word suhmode , 
 
 2. Read Short Word Winding (RS)--I turn--conducts the read current 
 in short word suhmode „ 
 
 3. Write Long Word Winding (WL)--I turn 
 
 (a) Conducts write current in long word submode. 
 
 (b) Conducts sense signal in short word submode. 
 
 (c) Conducts digit current in short word submodeo 
 k. Write Short Word Winding (WS)--2 turns 
 
 (a) Conducts write current in short word submode. 
 
 (b) Conducts sense signal in long word submode . 
 
 (c) Conducts digit current in long word submode. 
 
 C. Read Operations 
 
 The reading of long words is accom.plished by selection of one of 
 a set of four source drivers (an LRS-Long Word Read Source) and one 
 of a set of eight sink drivers (an LRK-Long Word Read Sink) for each 
 plane of the core matrix (see Fig. III.l). Each LRS driver delivers 
 current through isolation diodes zo the plus ends of eight RL windings, 
 Each LRK driver absorbs current from the m.inus ends of one of four 
 RL windings. This arrangement exists in parallel for each of the 
 eight matrix planes j, fiat is, eight separate but parallel-operated 
 LRS and LRK driver sets exist^, one set for each core plane^ resulting 
 in a total complement of 32 LP,S drivers and 6k LRX drivers. 
 
 From this point of view^ therefore^ a 102^-bit-long word is 
 operated as eight 128-bit words in parallel which appear concatenated 
 at the system level. 
 
 The read mmf is 350-UOO m,a-t for some 300 nsec duration. 
 
 -5- 
 
For short words,, the read operation is performed by a source-sink 
 arrangement as discussed above. Thirty-two SRS (Short Word Read 
 Source) and 32 SRK (Short Word Read Sink) drivers are employed to 
 select one of the 1024 short words. 
 
 The LRS and LRK drivers are identical in design to the SRS and 
 SRK drivers^ respectively. 
 
 Total requirements for read drivers are;, therefore^ 6h LRS-SRS 
 circuits and 96 LRK- SRK. 
 
 D. Write Operations 
 
 The long word, write windings (WL) are attached to the long word 
 write drivers (LWD)„ Each, sector of each long word is driven by a 
 separate driver j therefore _, there are 32 words x 8 sectors - 256 LWD's 
 The driver to be used in a write operation (actually eight drivers 
 in parallel) are selected by a diode OR- AND circuit complex which is 
 an extension of the long address decoder. The LWD delivers 120 ma 
 into the one-turn WL winding. During short word operations ;, t.he 
 LWD's operate as digit drivers under control of the short word buffer 
 f lipf lops . Since the same amount of current is used for both write 
 and digit drivers_^ no current selection network is required. 
 
 The short word write windings (WS) are similarly connected to the 
 short word write drivers (SWD) which differ from LWD's only in the 
 value of the output-current-determining resistor. The SWD current is 
 60 ma which produces an mmf of 120 ma-t; the same value delivered by 
 LWD's^ since the WS lines are two-turn windings. 
 
 One SWD is connected to each short word write winding for a total 
 of 102^ SWD's. These also double as digit drivers in the long word 
 submode . 
 
 E. Sensing 
 
 The sense signal peak amplitude has a nominal value of 30-3'^ mv 
 per turn (for logical "l")^ with a width of 16O-I8O nanoseconds. 
 Hence^ for long word, operations where the two-turn WS winding delivers 
 the sense signal^ a GO-'JO mv signal is expected as input to the Long 
 Word Sense Amplifiers (LS). 
 
 -6- 
 
The LS amplifiers have only one (two-wire) input each and deliver 
 an amplified and strobed (gated) signal via 90-ohm coax to the M 
 register. 
 
 The Short Word Sense Amplifiers (SS) are organized as eight 
 preamplif ication sections followed by a common output circuit o For 
 these amplifiers^ the input signals which are delivered by the one- 
 turn WL windings^ are 30-35 mv peak amplitude o 
 
 The physical packaging of a large part of the sense amplifier 
 circuitry is expected to be of the mlcropackaged "chip style" in which 
 the elements lie on an insulating substrate. 
 
 rv. Some Circuit Matters 
 
 The logic circuitry for the TM is^, in many respects^ standard and 
 therefore will not be discussed in detail. 
 
 The diagrams for the circuits discussed in the following sections are 
 to be found in the appendix, of this report. 
 
 A. Read Source Drivers (LRS-SR S) 
 
 The LRS and SRS drivers are required to pull up one end of a set 
 of read windings. An NPN driver transistor is operated in the em.itter- 
 follower mode for this purpose. It is turned on by injecting base 
 current from the secondary of the pulse transformer. Thus^ the trans- 
 former secondary and the transistor base and emitter are all raised 
 from -6 V to +30 V. Saturation is assured throughout most of the 
 drive period in order to limit power dissipation in the transistor. 
 Since only relatively few current sources are required^ their power 
 dissipation can be high without econom.ic difficulty. 
 
 The read drivers are capable of delivering up to 400 ma for 
 i^-00 nsec with a 1 '^isec repetition time. 
 
 B. Read Sink Drivers (LRK-SRK) 
 
 The read sinks clamp down the negative ends of the read windings. 
 When not selected^ the 2N2219 collector is at +12 v. Upon turn -on 
 of the 2N967^ a current of about ^00 ma is delivered by the 2N2219 
 which brings the collector to approximately +5 v. Since more current 
 
 -7- 
 
is available from the sink than from the source, the collector will 
 be solidly maintained at +5 v^ and in a low- impedance condition. 
 
 Ant i- saturation circuits are arranged for the 2N2219 so that 
 cut-off will be relatively fast and yet the peak dissipation will not 
 exceed one watt, 
 
 C. Write Drivers (SWD-LWP) 
 
 This is the driver circuit which appears in large quantity (l280) 
 in the TM, 
 
 Basically^ it can be seen that when the 2N967 turns on^ the base 
 current injected into the 2N2221 will cause the write winding (WS or 
 WL) to be pulled down to about -30 v„ The resistor marked R estab- 
 lishes the output current. 
 
 One compromise for economy is that no constant current source is 
 provided. Therefore, the delivered current is a function cf the non- 
 linear reverse voltage of the write windings, that is, a function of 
 the information being written. Tests indicate that this economy is 
 feasible at the cost of extended write time. The substantial 
 variations in writing current, it should be noted, make it imperative 
 that the operating mode of the cores be stable in this respect, 
 
 A second compromise is also made in the cut-off of the 2N2221, It 
 
 can be seen that statically, the V, =0 which is not as desirable 
 
 ^ be 
 
 ■ i 
 
 generally, as a small reversal of the base-emitter path. However, the 
 backshoot of the transformer, during turn-off, assures fast action of 
 2N2221 while the steady-state external resistance in the V, path, 
 namely the transformer secondary, allows high V voltages. 
 
 The input diode configuration is used to select the driver either 
 as a digit driver (the a,b pair) or a write driver (the c,d,e triplet), 
 The entire diode network is, therefore, an '"AND-OR complex," 
 
 D, Sense Amplifiers 
 
 The final choice of the sense amplifier circuit configuration has 
 not yet been made. The problems in this choice are decidedly severe 
 due to: 
 
 -8- 
 
1. the large number of components involved^ 
 
 2. space limitation^ 
 
 3. the problems of uniformity of the required number of circuits^ 
 
 and 
 
 k, all of the usual drift and gain control problems inherent in 
 Class A amplification „ 
 
 In order to reduce the volume of the circuitry as veil as the labor 
 in assembly^ the possibility of micropackaging is currently being 
 investigated. This style of packaging leads to further restrictions;, 
 especially of transistor polarity (NPN only) and number of pin con- 
 nections. AlsOj there is a significant problem in establishing 
 reliable information concerning the manufacturing limitations and 
 controls. The costs imz-olved are also more uncertain than for well- 
 established construction techniques, 
 
 Nevertheless_, the sense amplifier circuit specified as Mark II 
 (see appendix) was evolved for micropackaging. Visibly^ the circuit 
 consists of two cascaded stages of direct-coupled differential 
 amplification followed by an emitter-follower power amplification 
 stage and strobing circuit. Signal polarity is such that "l" corres- 
 ponds to a negative transition at the base of T_ . A special supply 
 voltage is provided at point (b) in order to control the quiescent 
 level of T 's base. Point (b) is supplied by a special regulator 
 whose output voltage tracks the +6 and -6 voltages ^ thus compensating 
 for long term drift of the power supplies o 
 
 The high-frequency gain is controlled (+ 30 per cent) by the 20-ohm. 
 emitter resistors in the two initial stages^ while the common mode gain 
 is minimized by the relatively large emitter resistors (2 and 2.7 k). 
 
 The mid-range minimum differential voltage gain is approx.im.ately 
 100 which allows full output for a 25-mv signal. Upper frequency cut- 
 off is in the vicinity of 3 mcps using 2N2222's. 
 
 A sense amplifier circuit which was used for test purposes is 
 also given (Mark l). Other circuits suitable for micropackaging are 
 being investigated. 
 
 -9- 
 
V. Tests 
 
 A test model of the TM will be described in this section. The test 
 model includes the following arrangements: 
 
 (1) h LRS;, 8 LRK^ and 32 LWD drivers to operate 32 long 
 words of 128 bits lengthy effect ively, 
 
 (2) 1 SRS^ 32 SRK, and 32 SWD drivers to operate 32 short 
 words . 
 
 (3) Associated counter^ control logic and logic drivers. 
 
 Briefly^ the model fully operates 32 bits of the 32 long words plus 
 dummy operation of an additional 96 bits per word; also^, 32 short words 
 of 32 bits each are fully operated 
 
 The core matrix which is used has 32 x 256 bits available ^ The cores 
 are Electronic Mem.ories Type 31-105^ a- 29-niil O.D=j 20-mil I.D.^ 6.5-mil- 
 high high-speed core. 
 
 The electronics described above occupies approximately 100 etched- 
 wiring boards , 
 
 The described equipment provides adequate versatility to simulate 
 worst conditions of the more troublesome sort. For example ;, variations 
 in sense signal arrival time as a function of information pattern can be 
 tested. 
 
 Some typical signals from the test model are illustrated in Fig, V.l, 
 The sense amplifier in use was the Mark I version, 
 
 VI. The Pyramidal Readout Encoder 
 
 A. Functional Description 
 
 Consider the TM in the "normal" form of 1024 words of 32 bits each. 
 A read operation in the long word submode then corresponds to a 
 parallel-by-bit readout^ after which one bit of all 102^ words exists 
 in the M register of the PAU, 
 
 A bit containing ' O" shall be said to be "marked" or that such 
 
 3 
 a bit has a "'jot" in it. Given the M register as input^ it is the 
 
 3 
 
 A jot may represent a vertex point or road intersection point in pictorial 
 information, for example, 
 
 -10- 
 
Upper Photo 
 
 Horizontal: 
 Upper Trace: 
 
 Center Trace 
 Lower Trace : 
 
 Center Photo 
 
 Horizontal: 
 Upper Trace : 
 Center Trace : 
 Lower Trace : 
 
 200 nsec/cm 
 
 Digit Current in WS 
 
 winding at 100 ma/ cm 
 
 Strobe 
 
 "l" output of sense 
 
 amplifier 
 
 200 msec/ cm 
 
 Same as above 
 
 SaJii.e as above 
 
 "l" single at base 
 
 of penultimate 
 
 sense amplifier 
 
 transistor at 2 v/cm 
 
 Lower Photo 
 
 Same as center photo except 
 horizontal scale is 100 nsec/cm 
 
 Figure V.lo Sample Signals from Test Version of TM 
 Long Word Readout 
 
 -11- 
 
 UNIVERSITY OF 
 JLLINOJS LIBRAM 
 
task of the PRE to deliver an output -which uniquely describes the 
 minimum bit number containing a jot^ i.e.^ bit 2 in Fig. VI. 1. 
 
 Bit Number : 1023 1022 
 
 M-Register Contents ; 1 1 
 
 5 
 
 k 
 
 3 
 
 2 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 Figure VI. 1 
 
 This PRE output must be in an encoded form suitable for communication 
 to the TM address decoder^, for example^ a ten-bit address. The 
 information thus encoded is the address (the "Z address") of the 
 minimum word number in the TM which contains a jot in the particular 
 bit under consideration. Upon signal from PAU control^ it is then 
 desired to read out the indicated word in TM for use by the control 
 computer and to erase (i.e.^ set to "l" ) the jot in the M- register 
 bit which was effective. 
 
 The foregoing description can be summarized as follows: 
 
 For the M-register flipflop outputs 
 
 M. = or 1, 
 1 ' 
 
 i = 0^ 1, 2 J . . .^ 1023 
 
 Encode 
 
 generate fZ.}, 
 
 J = 0, 1, 
 
 such that E Z. • 2"^ = k where 
 j-0 J 
 
 k = rain(i) for which M. = 0. 
 
 1 
 
 Read 
 
 Marked 
 
 Word 
 
 Then^ read word number k from the TM and 
 
 Erase 
 Jot 
 
 set 
 
 \ 
 
 = 1, 
 
 -12- 
 
In addition to these requirements _;, it also is desirable that the 
 PRE operate with sufficient speed that the readout of successive 
 short words^ indicated by more than one jot in the M- register^ proceed 
 at the maximum cycle time of the TM, This requirement would be 
 satisfied by a jot erasure and encode tim.e no greater than 9OO nano- 
 seconds assuming a cycle time of lo5 j-isec, 
 
 B= Logical Design of the PRE Unit 
 
 The complete task of the PRE unit can be considered as the three 
 independent operations^ encoding^ reading the marked word;, and jot 
 erasure as indicated in the preceding section. Since the "read 
 marked (short) word'" is a normal operation of the TM^ however^ only 
 the encoding and jot erasure need special attention „ 
 
 lo The Encoder 
 
 The most economical design of the encoder which has been found 
 so far will be described. 
 
 We consider the problem of generating a set of signals^ 
 
 ix. ,y . 1 
 
 i^j = 0,1< 
 
 31 
 
 such that a unique x^ x and a unique y^, y are true^ and represent 
 the minimum jot location in the familiar form k = 32q + p where 
 M is the minimum m.arked flipflop„ It is then a straightforward 
 matter to produce a ten-bit address. 
 
 Consider the simpler case of I6 M-register fllpflops and 
 arrange these in a U x 4 array as in Fig, VI ,1, 
 
 »12 
 
 "13 
 
 \k 
 
 "15 
 
 «8 
 
 «9 
 
 \o 
 
 «11 
 
 \ 
 
 ^ 
 
 "-6 
 
 ^ 
 
 % 
 
 \ 
 
 *2 
 
 M3 
 
 Figure VI, 1 
 
 ■13' 
 
An example case is shown in Figo VIo2 with M^^ M ^ and IL 
 having jots. 
 
 Jr 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 Xq x^ x^ x^ 
 
 Figure VI. 2 
 
 In this case we should arrive at true signals for y and x 
 
 since k = 6. Some examination will show that the solution (in 
 
 general) may be described diagramatically as follows: find the 
 
 row nearest the bottom which contains at least one zeroj then 
 
 for the elements of that row^ find the left -most column which 
 
 contains zero. 
 
 k 
 Drawing C-3095 is the diagram, of the logic which would 
 
 accomplish the task described^ the z signals being the encoded 
 address. When extrapolated to the case of 102^ inputs^ the only 
 difficulty which arises is the time required to propagate a "carry"' 
 in the priority circuits. The standard technique of breaking the 
 carry chain into shorter segments can be applied^ resulting in 
 an encoding time of 20 circuit transitions or less^ that is 
 800 nsec at UO nsec per circuit. This time can be reduced by 
 25 per cent or more with negligible increase in cost^ by special- 
 izing the circuit design and using the ultimate minimum, carry 
 chain. 
 
 The existence or nonexistence of a jot in the M- register is 
 indicated by the "some miark" signal. 
 
 See Appendix, 
 
 -Ik- 
 
The diode-transistor cost of the encoder is roughly 4^500 
 diodes and 600 transistors. The relatively low transistor count 
 is accomplished by maxira.um. use of diode logic which^ however^ 
 corresponds to a load of perhaps 12 ma on the M. signals. 
 
 Erasure Circuits 
 
 The erasure circuits generate a full decoding of a 10-bit 
 addresS;, that is_j one of the 1024 outputs is "l»" The address 
 will always be the contents of the short word address register 
 (SA) of the TM;, which must be decoded in any case. ThuS;, the erase 
 circuits coexist^ in part^ with, the short address decoder of the 
 TM^ delivering their output to the M register. The arrangement 
 described;, diagramm.ed in Figo VI-, 3;. allows the following basic 
 variants of addressing^ reading^ and erasing: 
 
 1, a. Gate Address (Z) from PRE to Short Address Register^ 
 
 or 
 
 b. Gate Address (Z) from Control to Short Address 
 Register 
 
 2. For either address of part 1: 
 
 a. Read the indicated short word only^, or 
 
 bo Read the indicated short word and erase the 
 corresponding M-register bit;, or 
 
 Co Erase the M-register bit only. 
 
 Successive la^ 2b micro-operations, for example;, would 
 correspond to reading sequentially all short words corresponding 
 to jots in the M register. The Ib^ 2c micro-operations ;, followed 
 by complementing the M register^ could establish a jot at the 
 address specified by an instruction address. 
 
 The diode-transistor count chargeable to erasure circuits is 
 1;,300 transistors and 3;, 100 diodes. It is conceivable that these 
 figures can be improved. The total time required for operations 
 la or lb and 2c is estimated at 200 nsec. 
 
 5 
 
 This operation would be used;, typically;, to set up the starting point of a 
 path readout in pictorial information. 
 
 -15- 
 
Shorted Word Address 
 from PAU Control 
 
 Short Word Address Register f 
 (10 bits) '■ 
 
 Short 
 Word 
 to PAU 
 
 Control 
 
 M register 
 
 1023J |"l022M'\02lh -. >t^ I Ml I l\ 
 
 PRE Encoder 
 
 SOME MARK 
 
 To PAU Control 
 
 Z Address (lO bits) 
 
 Figure VI»3. PRE Encoder and Eras« 
 
 -16- 
 
3. Content-Addressable Operations 
 
 Assume a specified set of "bits of all 32-blt -words Is 
 considered to constitute a tag. These bits may be read from the 
 TM into the PAU in the parallel-by-blt (or long word) submode. 
 In the PAU^ any desired logical operations may be performed^ with 
 programmed control^ on the tag bits. The set of words whose tags 
 meet the programmed criterion could then be read from the TM or, 
 alternatively, only the addresses of such words. The case of a 
 vacuous set would be indicated by falsity of the "some mark" 
 signal. 
 
 The mechanism described, therefore, allows tags of 1 to 32 
 bits to be employed. It is also interesting to note that since 
 any singlet, pair, triplet, etc, of bits may be used as tag, the 
 number of possible tag arrangements is: 
 
 32 
 Z 
 k=l 
 
 ^ ^ k!(32 - k): 
 
 If this statement appears to defy information theoretic laws, 
 it is because part of the information, namely, the knowledge of 
 which bits are to be taken as the tag, does not exist in the 
 transfer memory but in the programmer's memory. 
 
 The combination of transfer memory, pyramidal readout encoder, 
 PAU and associated control may be considered as a versatile, if 
 somewhat bulky, associative memory of 102^ words. 
 
 -17- 
 
APPENDIX 
 
 1, Drawing: SRS-LRS 
 
 2, Drawing: SRK-LRK 
 
 3, Drawing: SWD-LWD 
 
 k. Drawing: Sense Amplifier- -Mark 1 
 5. Drawing: Sense Amplifier- -Mark 2 
 6„ Drawing C-3095 (PRE: Pyramidal 
 Readout Encoder) 
 
 I 
 
 -18- 
 

 a 
 O 
 
 h 
 
 
 
 i 
 
 P»E:S\STAP7S i: 5"^ 
 T = S»TAN:>DAVa,o ' 
 
 
 1 
 
 XfOPOT SltKOAl 
 
 vv 
 
 CCiiOC 
 
 F^¥2, uPtS> 
 
 
 UNIVERSITY of ^ aTQRY 
 
 FOR S.R. BY K.C.u- CH 
 APP. & I 
 
a 
 Q 
 
 T 
 
 I 
 
 Z.ZK 
 
 
 ^ 
 
 l(0 74-q 
 
 P)ESlSTAPjS i S% 
 
 Dl^DE^ TI-2.S2. 
 
 T = STAKODAVaiO T R AtO S t-^Rt-^e FS 
 
 fOCiTELS. 
 
 2(M2 2-.q 
 
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