»■'•< *, -- L I B RAHY OF THE UNIVER.5 ITY OF ILLI NOIS 510.84 K6r no. 30 1 -307 cop. 2 The person charging this material is re- sponsible for its return on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS UBRAR^ATJJRBAN^A^^ tfS OEC t 3 ItfT .. rri) m 6 RE FEB 1 A, L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/potentiomatrixno307stei \U.6T qj ., REPORT NO. 307 /tul-tc, coo-ii+69-110 POTENTIOMATRIX - A NOVEL DISPLAY SYSTEM POSSESSING "INNATE INTELLIGENCE" by William George Steiner February, 1969 iij rets 5 1969 Report No. 307 POTENTIOMATRIX - A NOVEL DISPLAY SYSTEM POSSESSING "INNATE INTELLIGENCE"* by William George Steiner February, 1969 Department of Computer Science University of Illinois Urbana, Illinois 6l801 Submitted in partial fulfillment for the Doctor of Philosophy in Electrical Engineering, at the University of Illinois, February, 1969- POTENTIOMATRIX - A NOVEL DISPLAY SYSTEM POSSESSING "INNATE INTELLIGENCE" William George Steiner, Ph.D. Department of Electrical Engineering University of Illinois, 19&9 The purpose of the Potentiomatrix project is to devise a system, highly parallel in nature, which can display a desired general curved line on the basis of some simple implicit information. It is felt that success in this area may very well reduce the lengthy delays felt in the output channels of computer systems by providing a display system which does part of the "thinking" usually required of the computer. Additionally, this system which by nature displays in- formation coded in a minimal fashion is ideally suited for use in interstellar communication where narrow bandwidths and large signal- to-noise ratios are prime considerations. The technique involves representing the implicit information as fixed voltage regions in a grid of resistors which imitates the action in an infinite continuous conducting plane. The desired general curve then is represented as an equipotential line in the plane. Such curves are governed by the two dimensional Laplace's equation and experience has shown that many of the common curves such as straight lines, circles, ellipses, parab- olas, etc., may be generated with extremely simple boundary conditions. Electronic circuitry is employed to display the equipotential lines on a matrix of lamps . iii ACKNOWLEDGEMENT The author is very grateful to Professor W. J. Poppelbaum for suggesting this problem and for his continued support and guidance In addition, he would also like to express appreciation to Miss Carla Donaldson and Mrs. Jane Russo for the typing, and to all the members of the fabrication group under Mr. Frank Serio for their individual contributions . iv TABLE OF CONTENTS Page 1. INTRODUCTION . . . l 2. THEORETICAL ASPECTS OF POTENTIOMATRIX 2 2.1 Boundary Conditions for Common Shapes . 2 2.1.1 Circle 2 2.1.2 Straight Line k 2.1.3 Ellipse h 2.1.1+ Hyperbola 1+ 2.1.5 Parabola k 2. 2 Grid Approximation to Continuous Sheet 5 2.3 Influence of Resistor Tolerance on Grid Accuracy 10 2.1+ Influence of Detector Circuits on Grid Accuracy . . . . . 16 2.5 A Technique to Simplify the Grid Design 22 3. POTENTIOMATRIX 28 3.1 Introduction to Potentiomatrix 28 3.2 Potentiomatrix Circuitry 31 3.2.1 Write Circuit 31 3.2.2 Detector Circuit 33 3.2.3 Control Logic .0 . 33 3.2.4 Reference Generator 36 3.2.5 Reset Driver 36 3.2.6 Gate Driver 36 3.2.7 Width Drivers 1+0 3.2.8 R+ and R- Drivers 1+0 3« 3 The Potentiomatrix Resistive Grid 1+0 3*1+ Potentiomatrix Operating Instructions 1+8 k. SUMMARY . . . c 1+9 BIBLIOGRAPHY . . 50 VITA 51 V LIST OF FIGURES Figure Page 1. Boundary Conditions for Conic Sections . 3 2. Portion of Conductive Sheet 6 3. Typical Node Point in Resistive Grid 7 h. Typical Resistive Grid 12 5« Distribution of Resistors . 15 6. Input Characteristics of Detector Circuits 17 7« Resistor Chains 19 8. Node Voltage Deviations 21 9. Portion of Conductive Sheet . . . . <> 23 10. Typical Transition Mesh . 26 11. Functional Diagram . . • 30 12. Circuit Elements 32 13. Node Point Circuitry 3^- 1^. Logic Circuitry 35 15» Timing Diagram „ 37 16. Reference Generator 38 17. Gate Driver and Reset Driver Circuitry 39 18. Width Drivers kl 19. R+ and R- Drivers ........ k-2 20. Circuit for Determining R , kh mesh 21. One Quarter of Outer Resistive Grid k6 22. Transition Meshes h'J 1. INTRODUCTION The purpose of the Potentiomatrix project is to devise a system, highly parallel in nature, which can display a desired general curved line on the basis of some simple implicit information. It is felt that success in this area may very well reduce the lengthy delays felt in the output channels of computer systems by providing a display system which does part of the "thinking" usually required of the computer. Additionally, this system which by nature displays in- formation coded in a minimal fashion is ideally suited for use in interstellar communication where narrow bandwidths and large signal- to-noise ratios are prime considerations. The technique suggested by Professor W. J. Poppelbaum involves representing the implicit infor- mation as fixed voltage regions in a grid of resistors which imitates the action in an infinite continuous conducting plane. The desired general curve then is represented as an equipotential line in the plane. Such curves are governed by the two dimensional Laplace's equation and experience has shown that many of the common curves such as straight lines, circles, ellipses, parabolas, etc., may be generated with extremely simple boundary conditions. Electronic circuitry is employed to display the equipotential lines on a matrix of lamps. 2. THEORETICAL ASPECTS OF POTENT IOMA.TR EC 2.1 Boundary Conditions for Common Shapes The usefulness of the Potentiomatrix system depends on the ease with which the shape of curved lines may be transmitted. Although no attempt is made to catalog a complete set of curves, a few of the more obvious ones must be listed so that the simplicity behind this technique becomes evident. In order to demonstrate the simple conditions needed to specify a desired curve, the complete set of conic sections is considered in these examples. The available voltages to which points in the con- ductive sheet may be fixed are V R1 , a positive boundary voltage, and V 2 , a negative boundary voltage of the same magnitude as V , . The curves generated by these arbitrary boundary voltages and the fixed boundary voltage at infinity are formed as equipotential lines in a conductive plane and are governed by Laplace's two-dimensional differential equation. Figure 1 accompanies the following examples <> 2.1.1 Circle Circles are generated by a single boundary point at V R , » Using this input point as a center, concentric circles of all radii are formed for voltages between V^, and ground. Circles are also generated by two separate boundary points, one at V_,, the other at V . In this case, the circles are not con- BJ. Di- centric and are formed for voltages between V_. and V^-,. Circles are generated in still a third way by a straight line at V R , and a non-colinear point at V . In this case, the point forms an electrostatic image on the other side of the line. The circles are not concentric but are formed for voltages between V-, and V" B p. \ (V 1 / f - Noneoncentrle Circle* K>necne«ntrl<~ CI r*- l -v/VNA- o VSA/- ^ A Figure 3« Typical Node Point in Resistive Grid 8 V(x, y) . V Q + g| (x - x Q ) + Mny - y Q ) 1 o^Vi / n2 1 d V, / s2 + 2 7^l n (x " X ) + ' ' ' 2T2l n (y - V dx dy - a^| (x - x ) J + . . . — — *| (y - y ) im dx J U dg d y J U - t-t S_ ( x - x n ) + . . . j-T — t-I (y - yj . (2) oy o dy o Therefore evaluating at points P., P , P_, P. , V i = V o + ^ d + ?^ d + ^^'o d +5T ^o d (3) v 2 = v o + fi d+ l4i d2+ F% d3+ ^^ dU — « ^ o 2 dy^ o 5 ' ^ o 4 ' ay o V 3 = V 0-^ d+ ^l d -3T^ d + ^T^ d (5) \ = v o-|i d + i4i d2 -F% d3 + ^4i d ' < 6 > 67 2 Sy 2 3 ' dy J 4 ' dy Adding (3) to (5) and {k) to (6) respectively and solving for the second order derivative , iLI _ -L (y + v - 2V ) - e ' 7 . 2' .2 v 1 3 CT w; ^x d gl -t(t 8 + %-»o>-«o" (8) dy d where 2 h h 6 € ~ 12 ( 7T } + TT ( 7T ) (9) dx dx „ „ cT ,a Vs 2d 4 , d V , N dy dy Adding (7) and (8) gives: v 2 v = \ (v 1 + v 2 + v + v^ - Uv ) - e = (11) where € = €' + . d 2 r 9 U v, . s\, , . 2d 4 r S 6 v, , A, t u. rO_V| , O V I i ^u rU Vi O VI 1 , 12^0 ^'J "^" [ ^L r^'J- (12; dx dy dx: dy In principle, if d is made sufficiently small, the truncation error e 2 which is of order d can be ignored and (11) becomes: V 2 V =\ (V 1 + V 2 + V 3 + Y k - UV Q ) = (1 3 ; or simply V l + V 2 + V 3 + \ ' kY = °* (l4) If each side of (l^) is divided by R, whose value may at this point be arbitrary, the resulting equation, Kirchhoff's current law, describes the network around point P . 10 v-v V-V V-V V, - V If a 32 x 32 node array as used in Potent iomatrix is the area selected to display the potential distribution, then d = 1/31 (31 spaces between 32 points), and the leading term in the truncation error e becomes : . s 10-5 ( a\ + jSr, , (16) c^x dy It is evident that if V(x, y) is reasonably well behaved, as it must be in order to be represented on a 32 x 32 node array, then the truncation error € is negligibly small and can be ignored. 2.3 Influence of Resistor Tolerance on Grid Accuracy The second fundamental source of error in the use of a resistor network stems from the influence of the resistor tolerance on the obtainable accuracy. Although the maximum error conceivable (worst case) is on the order of the resistor tolerances themselves (usually 1%) , the actual error is several orders of magnitude smaller because the resistor network possesses certain averaging properties which tend to cancel larger errors. In 19^9, Liebmann studied these averaging effects and showed that for resistors possessing a normal .;tribution, the network error was on the order of the resistor tolerance divided by the number of meshes along one linear dimension. 11 A variation of Liebmann's analysis is now used to estimate the order of the error for a 32 x 32 node network as used in Potentiomatrix. Let us assume that deviations &R = pR of the actual resistance values from their normal values R are randomly distributed and that this distribution is given by a normal curve with a standard deviation a- The actual distribution of resistors used in the net- work is given later in this section and although it is not exactly a normal curve, it is a good enough approximation for the purpose of this discussion. Consider, in Figure h, all resistors to be of exactly the same value, R, with the number of components in the x and y directions each being 31? corresponding to a 32 x 32 node array. If all points on the left edge and all points on the right edge are connected and a V, _0 voltage V n is applied between them, then a voltage drop of AV = -^ is developed across each resistor in the x direction whereas all points along vertical lines have the same potential. Now assume that one resistor, between points P and P .is changed by BR to R + &R = R(l + p). The voltage difference between P and P remains essentially AV since the deviation 6R causes little change in the current flowing horizontally. However, the voltage difference between P and P , increases to AV + 5V, causing a change in potential at the point P . Consequently, currents flow vertically G. Liebmann, "Solution of Partial Differential Equations with a Resistance Network Analogue," British Journal of Applied Physics , Vol. 1, April, 1950, p. 9k. 12 >°l CV1 -3- J" PL, I I Figure h. Typical Resistive Grid 13 and new voltage deviations 6V and 6V" are formed between P and P and P Q and P. . Depending on the position in the network and how the current divides, 6V and 6V" lie between 6V and — . The four branch currents flowing into P are then _ AV + 5V 6V _ AV . 6V n „v 1 " R + 6R 2 " R 3 "" " R \ ~ K ' { ' ' Assume 6V and 6V" may be approximated by jf6V, an average value, and apply Kirchhoff 's current law, | [(AV + &V)(1 - p) + 2SV - AV] = (l8) which reduces approximately to 6V = |p AV (19) or V Q 5 x 31 { } To obtain the local error of the potential at the point P due to the presence of tolerance errors in all four resistors at point P , it is necessary to superimpose vectorially the voltage due to each of the four resistors. lit V p i=l V 5 x 31 Next, the effect of the statistical accumulation of the local errors, an average error of the field distribution which is superimposed on the local error, must be considered. Leibmann found that this accumulation error at each point is on the order of the average of the local errors. Superimposing these errors vec tori ally, the total error becomes (BV) = [I (SV) V kT2p ml23 JL (22 ) W J total ili^Q^Q J 5 x 31 " 1,1J 31 Kd } Measurements on a group of 973 1% resistors used in Potentiomatrix gave the distribution shown in Figure 5. Using standard statistical techniques, the mean value was found to be U02.3 ohms and the standard deviation was 1.29 ohms. A normal curve corresponding to this mean and standard deviation is shown as a dotted line. It is evident that the distribution is sufficiently normal to yield useful results. It is a simple matter to calculate p. p=f = M| = - 003 (23) and insert this value into (22) 15 Figure 5. Distribution of Resistors 16 (M)_ = i . !. 13 £ . 1 - 13 --° 03 = .OOOU (2k) L V'tabal corresponding to an error on the order of about one part in ten thousand. It should he emphasized that these calculations lead only to a rough estimate of the error and are intended only to give order of magnitude results. In addition, it should be observed that if the forcing voltages are applied at distances smaller than 31 units the error increases, but it never exceeds the tolerance of the individual resistors. 2.k Influence of Detector Circuits on Grid Accuracy The detector circuit at each node draws a small current which influences that node voltage slightly and establishes a third source of error. The input characteristics shown in Figure 6 indicate that the circuit draws zero current in the neighborhood of a region where a comparison is being made. This means that the neighborhood is least affected where the most exacting part of the comparison is being made. Minimizing the loading effects on the resistive grid caused by these detector circuits requires that the detector circuit have a maximum input resistance consistent with other design considerations and that the resistive grid have minimum resistance consistent with its design considerations. In Potentiomatrix, this condition results 17 H IW ho o H II 100K 100K 100K 100K 100K 100K 100K 100K 100 K 100K 100K 100K 201 V l 201 V 2 201 7 3 201 v i+ 201 201 V 6 201 V 7 201 V 8 201 V 9 201 V 10 201 V ll 201 V 12 201 7 13 201 V ll+ 201 ►100K ■ 100K >100K ■ 100K ]U-K 100K 100K 100K 100K 100K 100 K 100K 100K 100K ZL 100K 15 100.5 I Case I Case II Figure 7. Resistor Chains 20 represents a value which is never really attained and the resulting node voltage deviations will be artifically small. The actual deviations, of course, lie within the bounds established in Case I and Case II. The values for Case I and Case II have been calculated and the results are shown in Figure 8. It is seen that the deviation values are roughly proportional to the grid resistor value and roughly inversely proportional to the detector input impedance . In addition it is seen that the deviation at a node increases with distance from a node of fixed voltage. If the two fixed points were separated by a distance of fewer than 31 mesh units, the deviations would be appropriately reduced. Although the actual deviations vary with each particular display, the magnitude of the deviations should not be greater than several percent and in most cases is much smaller. This value is quite acceptable in Potentiomatrix for two reasons. First, the 32 x 32 array used in Potentiomatrix is inherently limited by the discreteness of its output to display information to no greater accuracy than 3%. Secondly, in the case of conic sections, for in- stance, these deviations result only in shapes which are not exactly the true conic sections but are however predictable and repeatable shapes which may be just as useful for display purposes as the true conic sections themselves. 21 LT\ -3- H > OO - > H ~ > - > ON - > CO > > > w -p a •H 01 O - > > on > OJ > > on OJ 0) 0) CO -P H w O •H •P 03 •H > 0) Q Figure 8. Node Voltage Deviations 22 2.5 A Technique to Simplify the Grid Design Many problems have open boundaries so that the field region extends to infinity. To cope with this, the area covered by the net- work is made as large as possible. Although the size of the network 2 required varies with each display, Vine points out that in many cases if the entire field region represented covers an area about ten times that of the region of interest (i.e. about three times the linear dimension), then the effect of termination can be ignored. In Potentiomatrix the area ratio is actually about sixty-four (i.e. about eight times the linear dimension) which should be sufficient for any display. In order to conserve resistors, which must all be precision, the large area required is covered by a coarse mesh surrounding a central fine mesh region in which the desired portion of the equipotential lines appear. The design of the transition mesh between fine and coarse 3 mesh area is quite interesting and Gair has given the following "cell principle" which makes the design seem "natural" and "obvious" from a geometrical point of view. Consider the area of a portion of a conducting sheet to be subdivided into rectangular cells as shown in Figure 9* A 2 J. Vine, "Impedance Networks," Field Analysis , Edited by D. Vitkovitch (London: D. Van Nostrand Company Ltd., 1955), p. 299. F. C. Gair, "Unifying Design Principles for the Resistance Network Analogue," British Journal of Applied Physics , Vol. 10, April, >, p. 167. 23 1 1 i 1 1 1 1 1 1 t Pl+»--Vv <; i l I p o 1 1 1 ?> *,* • P 2 6s 2 1 1 1 3 1 1 1 #P 3 1 1 1 Figure 9. Portion of Conductive Sheet 2k voltage corresponding to each cell is represented at a mesh point P. and the mesh points are chosen such that the cell boundaries bi- sect the line segments P n P. between neighboring cells. Consider a typical cell C with representative point P and area 6S . Cell C has perimeter 6s from sides 6s- , 6s , 6s_, 6s> and has cells C, , C , C , C, as adjacent neighbors. Laplace's equation for a cell C n , = V ' VV (25) may be integrated over the area 6S n and transformed by Gauss's theorem to get = f (y • V V) • dS = f V V • ds = f |J[ ' ds (26) where -— is the magnitude of the gradient in the direction n, the outward normal to 6S n . Considering that 6s n = Z 6s.. , (26) may be written as k - „ ±i i=l '6 6s. l The following approximation is now made 6V. 6V r ^w ov - ov - / S ds Zt-± 6s. -— ±- (28) U„ da 6n. i 6n. ( 6iT ) 1 25 where SV. = V. - \f , 8n. = the distance between P. and P_. A 1 1 1 l feeling for the degree of approximation can be gained by considering the geometry involved. Combining (27) and (28), it is seen that h SV. .\ "857- = ° (29) 1=1 (— ) 8n. reduces to Kirchhoff's current law where the (- — ) 's are proportional 6n i to mesh resistances , R. « - — which connect between points P. and P.. ' l 8s. l Applying this "cell principle" to the design of a transition mesh between fine and coarse areas leads quickly to a suitable design whose accuracy may be assessed by intuitive geometrical considerations, One possible design is shown in Figure 10 where R a 2 R, ■ oc 2 R 2 « 2 R 5 « 2 (30) R_ a 1 R, a 1. 3 6 By choosing slightly different cell structures, other networks can be designed. Two other designs, those actually used in Potentiomatrix, are considered in a later chapter. Treating transition meshes mathematically, Liebmann and Vine have found that although certain small errors do arise along the boundary between the coarse and fine mesh, that these errors are localized to the vicinity of the junction. That is, there is a small 2 2 error of the kind y^ -T -s at a point on the inner edge of the coarse 26 Figure 10. Typical Transition Mesh 27 2 2 net, and a compensating error of - -^r 3 \ at the adjacent point on the outer edge of the fine net. Liebmann constructed such transition networks and determined through tests that the errors due to the tran- sition meshes were of the order of about one part in 10,000. 28 3- POTENT IOMA.TR IX Introduction to Potent iomatrix Potentioraatrix is an electronic system utilizing hybrid digital- analog circuitry for displaying an arbitrary family of equi- potential lines. It uses the principle that certain areas clamped to fixed voltages in an infinite conducting plane give rise to a family of equipotential lines which are governed by the two dimensional La- place' s differential equation with appropriate boundary conditions. It is somewhat helpful to think of the Potent iomatrix panel as representing a section of a grid of resistors which imitates the action in an infinite conducting plane. The panel lamps then repre- sent nodes in the grid where four resistors are connected. Each of the 32 x 32 (102U) nodes in the central portion of the grid is con- nected to a pair of electronic circuits which are in turn connected respectively to a lamp in the panel and to a metal lamp socket which appears on the panel as a conducting ring around the lamp» The circuits which are connected to the conducting rings through their inputs are the write circuits and they are used to clamp the appropriate nodes to the proper voltage values (+10v = V^,, -10v= V r(0 ). The use of the write circuits corresponds to Bl Did applying boundary conditions to Laplace's differential equation. Touching the brush pen to the conducting ring applies -+10v (through 510 ohms) to the input of the write circuit which applies V B1 or V B2 pectively to the node in the grid. Touching Ov, which corresponds to a selective erase, resets the circuit and allows the node to float. 29 In addition to these individual controls, there are two common busses, R+ and R-, which perform master erase functions by resetting all of the write circuits. The circuits whose outputs are connected to the lamps are the detector circuits and they are used to compare the voltages at their nodes in the grid with a common reference signal, V , which goes to all the detector circuits. If a node voltage is equal to the reference, V , o within a preset tolerance E, the detector circuit, in conjunction with a clocking signal G, gates on the lamp for that node- It is evident that the lamps correspond to nodes in the grid which are each approxi- mately at the value of the reference voltage, V_, and therefore display an e qui potential line. The reference voltage, V , takes on successively the analog o values V^, Y^, V F1 , V p2 , V^, V ? ^ and V . This is pictured in Figure 11. V -. and V are the voltage levels (+ lOv) which generate the equi- potential lines corresponding to boundary conditions and V through V are arbitrary voltage levels between V™ and v"„ which are selected by the operator and which correspond to the five intermediate members of the equipotential family. As the reference voltage, V , proceeds through its seven values, the lamps remain on so that each new equipo- tential line is displayed along with the old ones. After the seven lines have been displayed for a short time, a buss signal R resets all of the detector circuits thereby turning the lamps off and the cycle repeats. 30 -p OJ m OJ on o .* ' o X H VO O -(-> t-i •H 0) A +-> i r— o CO -p o l-c O, J- Pi -w- Ph 7TT PL, « T3 C as + w W > > + w S 7 7? Ph ^ ' ^iSj tt I., o « o 1-. •p c o o o •H Figure 11. Functional Diagram 31 3»2 Potentiomatrix Circuitry Potent iomatrix requires a number of types of circuits and the details of these circuits are discussed in the following paragraphs. 3.2.1 Write Circuit The write circuits are used to clamp the appropriate nodes to the proper boundary voltages values. Each write circuit contains two of the electronic storage elements shown in Figure 12. These elements have the property that they draw zero current in off state because both tran- sistors are off, and, in the on state, they have quite low impedance drive capabilities, limited primarily by the maximum collector current of the output transistor. The schematic of one write circuit is shown in Figure 13 « It is evident that touching +10v (or -lOv) (through 5 10 ohms) to the conducting ring sets the proper storage element to the correct state to apply V-, (V T , n )o The common collectors of T, and T„ and the BJ- tic. A. d common bases of T~ and T. provide independent interlocks which assure that both storage elements cannot be on simultaneouslyo The write cir- cuit can be reset in two ways. All circuits storing V.... (V ) are re- B-L tic set simultaneously by changing R+ (R-) from its normal value of +10v (-10v) to Ov which simply amounts to removing a supply voltage from the set of Bl (B2) storage elements. This serves as a master reset for complete erasure of the panel. In addition, individual circuits may be reset by touching Ov to the control ring, and this provides a se- lective erase capability. 32 I V e i + > A >° A > W A >" i VI .c u7 Vi Ul + > /L; + A c Figure 12. Circuit Elements 33 3.2.2 Detector Circuit The detector circuit shown in Figure 13 compares its node voltage with the reference voltage, V . If the node voltage is equal to the reference, V" s , within a preset tolerance E, the lamp for that node is gated on. All of the supply voltages used "by the detector circuit are referenced to V c . Therefore, in the read circuit, V , b b is equivalent to ( n-rm ) which is the common for +12v, +5v, and also for signals +E, G, and R. The heart of the circuit lies in the use of a bridge mounted differential amplifier to drive a storage element. Figure 12 indicates how an output of the proper polarity is produced for various ranges of input voltage. Note that R indicates the reverse resistance (leakage current) of the diode and that reverse biased diodes are shown by dashed lines. The desired output of the differential amplifier is -12v if the input voltage is between +E and -E, and is +12v otherwise. The differ- ential amplifier has a gain exceeding 8,000 so that even a slight volt- age difference on the inputs is sufficient to cause saturation at +12v. The differential amplifier drives a storage element which turns on the lamp. This storage element, like that in Figure 12, draws zero current in the off state. The signal G gates the amplifier output to set the storage element and the signal R resets the storage element. Diode D8 along with resistor R15 provides isolation to protect the storage element from being reset at its output by spurious pulses. 3»2.3 Control Logic The control logic shown in Figure Ik is composed primarily of 3h O-e c * o - c Z < o 1 +> | g •H O _ m ^ u I ■p Figure 13. Node Point Circuitry 35 N1308 1 - 7 SN 7I+7ON 8 - 9 SN 7410N 10 SN 7^00N 11-12 SN 7U3ON X .k x k B2 Fl F2 F3 W F5 Reset Figure 14. Logic Circuitry 36 integrated circuits and generates the pulse trains shown in the timing diagram, Figure 15 • The clock runs at approximately 6KHz and the com- plete logic recycles every 128 counts. All signals are generated in- ternally except F which is +5v (logical l) if the FAMILY button on the control panel is down and Ov otherwise. 3.2.4 Reference Generator The reference generator, Figure 16, produces the reference voltage, V , that is fed to all the detector circuits. All of the in- o puts come from the control logic except P,, P p , P^., P^ and P which are d.c. levels between +10v and -lOv selected at Fl, F2, F3, F4 and F5 re- spectively on the control panel by the operator. 3.2.5 Reset Driver The reset driver, Figure 17, is a buffer circuit which also interfaces between the control logic and the 1024 detector circuits. The reset signal R, on the 128th count of the control logic, resets the storage elements of the 1024 detector circuits in preparation for the next cycle. The reset signal R is pulsed to +12v from -12v. 3.2.6 Gate Driver The gate driver, Figure 17, is a buffer circuit which inter- faces between the control logic and the 1024 detector circuits. The gate signal G occurs either 2 or 7 times (depending on the position of the FAMILY button) in a machine cycle and allows the reference voltage, • to settle at each level before the comparison is actually made. D 37 dh I L c r i i i K W I I I m j- ir\ ^o X H H X l I l I I I I m" pet Pa t** En h m m IO cc Figure 15 • Timing Diagram xj- 38 Figure 16. Reference Generator 39 Figure 17 . Gate Driver and Reset Driver Circuitry 1+0 The gate signal is pulsed to -12v from +12v. 3.2.7 Width Drivers The width drivers, Figure 18, are buffer circuits which pro- duce levels +E and -E, the two threshold levels required by the 102*4- read circuits. The WIDTH knob on the control panel, set by the opera- tor, produces a d.c. voltage W. -E corresponds approximately to W and +E corresponds approximately to -W. 3.2.8 R+ and R- Drivers The R+ (or R-) driver, Figure 19, supplies the common reset signal for the Bl (B2) storage elements of the write circuit. The input to this circuit, which comes from the ERASE Bl (ERASE B2) but- ton on the control panel, is normally open circuited but goes to ground when the button is pushed. When the ERASE Bl (ERASE B2) button is pushed, R+ (R-) is changed quickly from +10v (-10v) to ground but when the button is released, R+ (R-) returns slowly by exponential decay to +10v (-10v). 3.3 The Potentiomatrix Resistive Grid The design of the resistive grid appears somewhat complex be- cause of its size but is rather straight forward. It uses a variation of the "cell principle" presented in an earlier section. The central 32 x 32 node portion of the grid is made of 198^ 402 ohm 1% resistors which have a power rating of 1 watt each. The choice of U02 ohms was made through several considera- tions. Due to the loading of the detector circuits at each point on 1+1 +12 W -12 +12 Figure 18. Width Drivers k2 Erase Bl Erase B2 ■j • R- Driver Figure 19. R+ and R- Drivers 1+3 grid, the resistor value had to be chosen as low as possible consistent with two other requirements. The first condition required that the current drawn from any write circuit must be less than 300ma, the col- lector rating of the output transistor. The worst case, shown in Figure 20, results when one point is clamped to +10v and its four neighboring adjacent points are all clamped to -lOv. This effectively connects the four mesh resistors in parallel across 20v. Consequently, one condition is 300ma > / , s " H vA (3 1} mesh' or R , > 266 ohms. (32) mesh — ' The second condition requires that the power dissipated in any resistor must be less than lwt. The worst case results when +10v is applied to one terminal of the resistor and -lOv is applied to the other terminal. Consequently the other condition is iwt > isi! (33) mesh or R , > ^00 ohms. (3*0 mesh — ' kh -10 ■10 -10 Figure 20. Circuit for Determining R esh' h5 1+02 ohms is the first standard MIL-OHM value above 400 ohms. The 992 resistors connected horizontally between nodes are mounted on a printed circuit board which also serves as a connector racko The 992 resistors connected vertically between nodes are mounted on the 32 circuit boards which plug into the connector racko The outer portion of the grid which surrounds the central portion uses only a few more resistors, 2336, but covers an effective area approximately 63 times greater. Mounted on two printed circuit boards, these resistors are also 1% but have only l/Wt or l/2wt power rating. A quarter section of the outer portion of the grid is shown in Figure 21. The outer portion uses five transistion meshes each of which doubles the mesh size and decreases the number of resistors required. A grid using no transistion meshes which covers the same area would require approximately 125,000 resistors. The details of these tran- sistion meshes are shown in Figure 22. The cell boundaries are indi- cated by dotten lines. With the help of the "cell principle", which states that a resistance value is proportional to the physical dis- tance between the node points divided by the length of the cell wall it intersects, the resistance values may be calculated easily, if not by inspection. The relative values of these resistances is indicated by numbers near the resistors on the figure. The values used in Po- tent iomatrix then are these values multiplied by 1+02 ohms. U6 1 V — 3 • r L * I in i i i | i III III I I Figure 21. One Quarter of Outer Resistive Grid hi — i- I t" ■vV- -v4*- -vU- VjA- I *.__!__4i ' _i__i__i_. 1 -4—1-4 -vi*- 4—1-4 I f Figure 22. Transition Meshes 48 3.4 Potentiomatrix Operating Instructions In normal operation, the operator writes the appropriate voltage lines by drawing the brush pen across the panel and by suc- cessively pushing the Bl and B2 buttons corresponding to the two boundary voltages. Small on-line corrections can be made at any time by touching the small button on the side of the brush pen and "erasing" the undesired portions of the boundary voltage lines. Pressing the FAMILY button displays the family of equipotential lines related to the boundary voltage lines. A total of 5 members (plus the two bound- ary lines) are displayed and the position of each line may be indepen- dently chosen at will by the knobs marked Fl and F5» If fewer than 5 lines are desired, some lines may be hidden behind a boundary voltage line. Either boundary voltage line may be completely erased by means of ERASE Bl or ERASE B2 without affecting the other; or both may be erased by pushing both buttons simultaneously. The WIDTH knob controls the thickness of the displayed lines. h9 k. SUMMARY The Potentiomatrix system proved itself to be a quite suc- cessful investigation. In the first section, possible trouble spots which might inherently limit size or accuracy were investigated on a theoretical basis and, although a number of such areas were encountered, it was found that each could be eliminated or reduced using present-day technology. This established the feasibility for both this system and for larger and more complex systems which may follow. The second section describes a working Potentiomatrix system implemented at a reasonable cost. This section presents the details of the actual circuits and the methods used in building the resistive grid. The section closes with a short discussion of operating procedures. 50 BIBLIOGRAPHY Gair, F. C. "Unifying Design Principle for the Resistance Network Analogue, " British Journal of Applied Physics, Vol. 10 (1959), 166-172. G. £. Transistor Manual . 7th edition. Syracuse: G. E. Semiconductor Products Division, 1964. Hayt, W. H. Engineering Electromagnetics . New York: McGraw - Hill Book Company, Inc., 195&. Jordan, E. C. Electromagnetic Waves and Radiating Systems . Englewood Cliff si Prentice - Hall, Inc., 1962. Liebmann, G. "Resistance - Network Analogues with Unequal Meshes or Subdivided Meshes, " British Journal of Applied Physics, Vol. 5 (195*0, 362-3^ Liebmann, G. "Solution of Partial Differential Equations with a Resistance Network Analogue, " British Journal of Applied Physics, Vol. 1 (1950), 92-103. Millman, J. and Taub, H. Pulse, Digital, and Switching Waveforms . New York: McGraw - Hill Book Company, Inc., 1965* Moroney, M. J. Facts from Figures . Baltimore; Penquin Books, 1965* Morse, P. M. and Feshbach, H. Methods of Theoretical Physics . New York: McGraw - Hill Book Company, Inc., 1953» Smythe, W. R. Static and Dynamic Electricity . New York: McGraw - Hill Book Company, Inc., 1950. Vine, J. Field Analysis . Edited by D. Vitkovitch. London: D. Van Nostrand Company Ltd., 1955* 51 VITA. William George Steiner was born in Alton, Illinois, on March 9, 194l. After graduating from high school in 1959, he began undergraduate work in Electrical Engineering at the University of Illinois under the Co-Op Engineering Plan with McDonnell Aircraft Corporation in St. Louis, Missouri. In 1964, he received his B. S. in Electrical Engineering. Mr. Steiner continued his education at the University of Illinois while doing research at the Radio Direc- tion Finding Laboratory and in 1965 received his M. S. in Electrical Engineering. He then transfered to the Hardware Research Group of the Computer Science Department of the University of Illinois where he has worked toward a Ph.D. in Electrical Engineering.