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 Report No. Ul7 
 
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 COO-2118-0001 
 
 ILLIAC III COMPUTER SYSTEM MANUAL: 
 TAXICRINIC PROCESSOR 
 
 VOLUME 1 
 
 by 
 
 Bernard J. Nordmann, Jr. 
 
 November 2k , 1970 
 
 THE LIBRARY DEiTHE 
 
 NOV 9 1972 
 
 UNIVERSITY OF ILLINOIS 
 AT URBANA-CHAMPAIGN 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, ILLINOIS 
 
COO-2118-0001 
 
 Report No. klf 
 
 ILLIAC III COMPUTER SYSTEM MANUAL: 
 TAXICRINIC PROCESSOR* 
 
 VOLUME 1 
 
 by 
 
 Bernard J. Nordmann, Jr, 
 
 November 2k, 1970 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 This report replaces Report No. 3^1 
 
 ^Supported by Contract AT(ll-l )-21l8 with the U.S. Atomic Energy 
 Commission. 
 
ACKNOWLEDGMENT 
 
 The conceptual design of the Taxicrinic Processor of the 
 Illiac III Computer System is largely the work of three individuals: 
 Roger E. Wiegel, Bruce H. McCormick and the author. Dr. R. M. Lansford 
 emphasized the importance of the associative addressing scheme wherein 
 the processor can automatically enter the Segment Name Table for addi- 
 tional base descriptors, as needed. This facility, central to an 
 effective Operating System, has been incorporated into the design of 
 the Taxicrinic Processor. 
 
 Familiarity with the Illiac III Programming Manual, edited by 
 B. H. McCormick and R. M. Lansford, March 1968 is assumed. Where dis- 
 crepancies exist, they should be resolved in favor of the present manual 
 as the more authorative document. 
 
 Section III, which discusses the coupling of the Taxicrinic 
 Processor to the Exchange Net, rests heavily upon File No. 790 by Paul 
 S. Krabbe entitled "A Discussion of Illiac III Processor-Unit Communica- 
 tion Via the Exchange Net". Dan E. Atkins also read this section for 
 consistency with the Arithmetic Unit design. 
 
 Bruce H. McCormick and Mary Ann Hagen assisted in the arduous 
 task of editing this volume of the TP Manual. Mrs. Donna J. Stutz 
 labored over the many revisions and rewrites to type the document. The 
 illustrations were prepared by John Otten, Eric Storm and Ron Morrison. 
 
 The corrections and additions for the second edition were 
 edited by John O'Donnell and typed by Mrs. Betty Gunsalus. The supplementary 
 illustrations were drawn by Stan Zundo and Bill Giblin. 
 
OUTLINE 
 
 1. GENERAL INFORMATION 
 
 1.1 Report Conventions 
 
 1.1.1 Report Organization 
 
 1.1.2 Signal Name Conventions 
 
 1.2 Brief Overview of Illiac III Computer System 
 
 1.3 General Description of the Taxicrinic Processor 
 
 1.3.1 Basic Purpose of the Taxicrinic Processors 
 
 1.3.2 The General Organization of the Taxicrinic Processor 
 
 1.3.2.1 The TP Registers 
 
 1.3.2.2 The TP Subprocessors 
 
 2. SUBPROCESSOR DESCRIPTIONS 
 2.1 Permuter 
 
 2.1.1 Permuter-Functional Description 
 
 2.1.1.1 Permut er Input 
 
 2.1.1.2 Permuter Control Logic 
 
 2.1.1.3 Permutation Decoding 
 2.1.1.U Permuter Output 
 
 2.1.1.5 Inhibit Generation Logic 
 
 2.1.1.6 Gate Inhibits for the LR and IR 
 
 2.1.1.7 Permuter Register Gate Drivers 
 
 2.1.2 Signal Name Lists for the Permuter 
 
 2.1.2.1 Control Signals 
 
 2.1.2.2 Internal Signals Used by the Permuter 
 
2.1.3 Permuter - PL/l Description 
 
 2.1.4 Permuter - Logic Description 
 
 2.1.4.1 The Basic Permuter Card 
 
 2.1.4.2 Inhibit Generator 
 
 2.1.4.3 Permutation Control Logic 
 
 2.2 Nine Bit /Byte Buffer Storage Blocks 
 
 2.2.1 Buffer Storage - Functional Description 
 
 2.2.2 Signal Name List for Buffer Storage 
 
 2.2.3 Buffer Storage - PL/l Description 
 
 2.2.4 Buffer Storage - Logical Description 
 
 2.3 Operand Stack 
 
 2.3.1 Operand Stack - Functional Description 
 
 2.3.1.1 Operand Stack Control Registers 
 
 2.3.1.2 The Constant Generator 
 
 2.3.1.3 Byte Selection Logic 
 
 2.3.1.4 Overflow-Underflow Sensing Logic 
 
 2.3.1.5 5-Bit Adder - Functional Description 
 
 2.3.2 Signal Name Lists for the Operand Stack 
 
 2.3.2.1 Control Signals 
 
 2.3.2.2 Internal Signals Used by the Operand Stack 
 
 2.3.3 Operand Stack - PL/l Description 
 
 2.3.4 Operand Stack - Logical Description 
 
 2.3.4.1 Operand Stack Storage 
 
 2.3.4.2 Overflow-Underflow - Logical Description 
 
 2.3.4.3 5-Bit Adder - Logical Description 
 
 2.4 The Pointer Registers 
 
 2.4.1 Pointer Register Formats 
 
 2.1+. 1.1 Pointer Stack Format 
 
 2.4.1.2 List Processing Format 
 
 2.4.1.3 Available Space Format 
 
2.U.2 Pointer Registers - Functional Description 
 
 2.U.2.1 Pointer Register Storage 
 
 2.J+.2.2 Pointer Register Control Registers 
 
 2.U.2.3 Pointer Register Selection Process 
 
 2.U.2.U Tag Setting and Sensing 
 
 2 . U . 3 Signal Name Lists for the Pointer Registers 
 
 2.1+.3.1 Control Signals 
 
 2.U.3.2 Internal Signals Used by the Pointer Registers 
 
 2.h.k Pointer Registers - PL/1 Description 
 
 2.5 Base Registers 
 
 2.5.1 Base Registers - Function Description 
 
 2.5.1.1 Base Register Storage 
 
 2.5.1.2 Associative Register Storage 
 
 2.5.1.3 Queue Counters 
 
 2.5.1.*+ Association Logic and Associative Registers 
 2.5.1.5 Base Register Read/Write Selection 
 
 2.5.2 Signal Name Lists for the Base Registers 
 
 2.5.2.1 Control Signals 
 
 2.5.2.2 Internal Signals Used by the Base Registers 
 
 2.5.3 Base Registers - PL/1 Description 
 
 c 
 
 2.o Instruction Buffer Register 
 
 2.6.1 Instruction Buffer Register - Functional Description 
 
 2.6.1.1 Instruction Buffer Register Storage 
 
 2.6.1.2 The Instruction Counter and Selection Logic 
 
2.6.2 Signal Name Lists for the Instruction Buffer Register 
 
 2.6.2.1 Control Names 
 
 2.6.2.2 Internal Names Used by the Instruction Buffer Register 
 
 2.6.3 Instruction Buffer Register - PL/1 Description 
 2.6.U Instruction Buffer Register - Logical Description 
 
 2.6.U.1 Instruction Counter Logic 
 
 2.7 The 32 Bit Adder 
 
 2.7.1 32 Bit Adder - Functional Description 
 
 2.7.1.1 Block Diagram Description 
 
 2.7.1.2 Adder Timing 
 
 2.7.1.3 Adder Overflow 
 
 2.7.2 Signal Name Lists for the Adder 
 
 2.7.2.1 Control Signals 
 
 2.7.2.2 Internal Signals Used by the Adder 
 
 2.7.3 32 Bit Adder - PL/1 Description 
 
 2.8 Boolean/Shift Logic 
 
 2.8.1 Boolean/Shift Logic - Functional Description 
 
 2.8.1.1 Boolean Logic 
 
 2.8.1.2 Shift Logic 
 
 2.8.1.3 The M-Counter 
 
 2.8.2 Signal Name Lists for the Boolean/Shift Logic 
 
 2.8.2.1 Control Signals 
 
 2.8.2.2 Internal Signals Used by the Boolean/Shift Logic 
 
 2.8.3 Boolean/Shift Logic - PL/1 Description 
 
 2.8.1+ Boolean/Shift Logic - Logical Description 
 
 2.8.U.1 Boolean/Shift Logic 
 2.8.U.2 M-Counter Logic 
 
2.9 Algebraic/Logical Compare Logic 
 
 2.9.1 A/L Compare Logic - Functional Description 
 
 2.9.2 Signal Name Lists for the A/L Compare Logic 
 
 2.9.2.1 Control Signals 
 
 2.9.2.2 Internal Signals Used by the A/L Compare Logic 
 
 2.9.3 A/L Compare Logic - PL/1 Description 
 
 2.10 Cell Size Generator 
 
 2.10.1 Cell Size Generator - Functional Description 
 
 2.10.2 Signal Name Lists for Cell Size Generator 
 
 2.10.2.1 Control Signals 
 
 2.10.2.2 Internal Signals Used by the Cell Size Generator 
 
 2.10.3 Cell Size Generator - PL/1 Description 
 
3. INTERFACE TO THE OTHER SUBSYSTEMS 
 
 3.1 The Exchange Net 
 
 3.1.1 INBUS and 0UTBUS 
 
 3.1.2 Principal Parts of the Exchange Net 
 
 3.1.3 Standard Signals Used in the Control Bytes of all 
 Processors and Units 
 
 3.1.1+ Standard Signal Sequencing (Control Byte) 
 3.1.5 Exchange Net - TP Interface - General 
 
 3.2 The Core Storage Units 
 
 3.2.1 Requirements for Processors and the Core Storage Units 
 
 3.2.2 Input to the Storage Units 
 
 3.2.3 Output from the Storage Units 
 
 3.2.U Processor-Core Storage Unit Signal Sequencing 
 
 3.2.5 Individual Differences in the Types of Units 
 
 3.2.6 Exchange Net - TP Interface for the Memory Units 
 
 3.3 The Arithmetic Units 
 
 3.3.1 Input to the Arithmetic Units 
 
 3.3.2 Output from the Arithmetic Units 
 
 3.^ The Pattern Articulation Unit 
 
 3.5 The Interrupt Unit 
 
 3.6 The I/O Processors 
 
1. GENEEAL INFORMATION 
 
 1.1 Report Conventions 
 1.1.1 Report Organization 
 
 This manual serves as a general information source on the Taxi- 
 crinic Processor. The manual will eventually contain all necessary informa- 
 tion to enable a person to understand the TP in adequate detail to check 
 out and diagnose the hardware. 
 
 Since this manual contains much detailed information, it has 
 been necessary to organize it in a manner such that the reader can obtain 
 needed information with minimum lost time and effort due to reading non- 
 essential information. To this end the manual has been divided into five 
 sections: Introduction, Sub-processor Descriptions, Interface Information, 
 Control Sequence Descriptions and the Logic Directory. 
 
 The first section describes the Illiac III System in a general 
 manner and gives a brief description of the Taxicrinic Processor. 
 
 The second section gives a detailed description of each sub- 
 processing section in the TP. For each section there is first a summary, 
 then a detailed functional description. Next the input and output signals 
 from and to the other subprocessors are described. Finally for each section 
 there is a detailed logic description complete with normal signal states, 
 detailed boolean descriptions and explanations of unusual design choices. 
 
 The third section describes the interface between the TP and the 
 other processors and units in the Illiac III system. A short description of 
 the operation of the Exchange Net and each attached processor and unit is 
 given. The necessary interface signals which must travel back and forth 
 between the processors/units and the TP are then described. 
 
 The fourth section describes the control unit sequences. Each 
 sequence is described as to its function and then a detailed description of 
 its flow chart is given. Finally the description of the actual logic is 
 presented. Again, anything unusual in the way of logic is explained in 
 
 5/16/69 , Section 1.1.1 - 1/2 
 
detail. A discussion of the control logic philosophy is presented as an 
 appendix to this section. 
 
 The fifth section, the Logic Directory, summarizes various 
 details of the TP Logic. It contains a complete listing of all signal 
 names used in the TP along with their definitions and places of occurence. 
 There is also a list of load currents, a list of board counts and similar 
 information. 
 
 5/16/69 Secti ° n 1 - 1 - 1 ■ 2/2 
 
1.1.2 Signal Name Conventions 
 
 The signal names used in the Taxicrinic Processor follow a 
 variety of signal name conventions. There are two corresponding 
 sets of signal names: the logic names , which are used in the logical 
 design, and the simulation names , which are used in the PL/l logical 
 simulation of the TP. 
 
 Every logic name, S, can "be expressed in two ways, S or S. 
 The S signal name represents the true state (also known as '+' or '1') 
 of the assertion or statement associated with S. The S signal name 
 represents the false state (also known as *-' or '0*) of the assertion 
 or statement associated with S. When a line labeled S is in the true 
 state, i.e. it is "on", any lines labeled S must, by definition, be in 
 the false state, i.e. they are "off". 
 
 On the logic drawings themselves the fact that a signal is 
 barred or unbarred indicates the normal resting state of the signal line. 
 In other words a signal labeled S will normally be '-', '0', or 'false' 
 and will only become '+' , '1', or 'true' when the assertion represented 
 by S becomes true. In the same manner, a signal labeled S will normally 
 be '+', '1', or 'true', and will only go to '-', '0', or 'false' when S 
 becomes true (i.e. S becomes false). 
 
 In discussing logic signals the "barred" signal names will be 
 expressed using either an overbar, as in S, or a terminal slash as in S/. 
 These two variants are equivalent. The slash is generally used in computer 
 listings while the overbar is generally used in the text of the TP Manual 
 and in the logic drawings . 
 
 Whenever a signal moves from its normal resting state it is said 
 to be active. Thus, to say that S is activated is to imply that all S sig- 
 nals become '0' and all S signals become '1'. This terminology is often 
 used when both versions of the signal appear in the same section of logic. 
 
 7/8/69 Section 1.1.2 - l/U 
 
Two signals are said to be logically equivalent if the activation 
 of either signal implies that the other signal will he active. This is a 
 DC definition, i.e. the states may not exactly coincide in time since there 
 may he a delay between the time of activation of the two signals. Thus 
 DB, DBB and DBP are all logically equivalent signals although there will 
 he 'several tens of nanoseconds between the time when DBP turns on and 
 the time when DBB turns on. 
 
 Some signal names are classified into one of four classes: 
 inhibits, gates, enables or selects. The classifications are in some 
 cases rather arbitrary but in general they follow certain broad outlines. 
 Inhibits generally keep something from happening. Gates, transmit waiting 
 data from one bus or register to another, tables generally activate some 
 group of logic. Selects usually choose one of several possible actions or 
 blocks of logic to be operated. 
 
 As can be seen, these definitions overlap considerably and in 
 many specific instances can be quite arbitrary. At any rate, signal names 
 which have been assigned to one of these classes are designated at the end 
 with a slash followed by one of the letters N (inhibit), G (gate), E (enable), 
 or S (select). This slash and letter appear after the main body of the sig- 
 nal name but before any slash indicating a barred signal. Thus, examples 
 of these signals are DLRl/N/, inhibit DR to LR gate - byte 1, DRP/G, DR to 
 Permuter input gate, ADD/E, 32 bit adder enable, and PR2/S/, Pointer Register 
 2 select. 
 
 The signal names themselves usually contain up to 8 letters 
 counting any slash and N, G, E, or S, but not counting the terminal 
 slash. Signal names in general may not end in the letters I ox f. This is 
 to avoid confusion with subscripted signal names with subscripts of one or 
 zero. Unfortunately, this convention is not rigorously followed. In most 
 cases the exceptions have not been changed simply because of historical 
 precedent. One example of th is is the FBI bus. The signal PBI17 is often 
 confused as FB „ instead of FBI^ . 
 
 Section 1.1.2 - 2/k 
 
 7/8/69 
 
 
As shown above, logic signal names are subscripted by adding 
 numbers at the end of the name. If the signal name is classified using 
 the slash and letter convention, the subscript appears before the slash 
 (i.e DLR1/N). Double subscripts cannot be handled by the current wiring 
 list generating program and are therefore frowned upon. However, they 
 can be used by inserting the first subscript in the body of the signal 
 name, i.e. T2R1 is temporary register 2, bit 1 and N6R3 is name register 
 6, bit 3- This allows the wiring program to assume that there are 15 
 signal names, NORi through NlURi , and it treats them as any other single 
 subscript signal name. There are two exceptions to the double subscript 
 rule in the TP logic, IBPL13 and IBPL21. These are, once again, historical 
 exceptions and stand for 2 operations each, i.e. inhibit byte 1 permute 
 left 3, and inhibit byte 2, permute left 1. 
 
 In some cases the loading on a given signal name is too large even 
 for a logic driver circuit. In such cases one alternative is to use two 
 drivers with identical inputs and to send the output of one driver to half 
 of the loads and the output of the other driver to the other half. However, 
 since these signals are not electrically identical they need to have dif- 
 ferent names. One way to do this is to add different numbers at the end 
 of each name. Thus PSNW5/S1 and PSNW5/S2 both indicate that PR Segment 
 Name Register #5 has been selected for writing. 
 
 The PL/1 logic simulator for the TP generally uses the same sig- 
 nal names as the TP logic. However, there are several modifications due 
 to the nature of the simulation and the allowable names in PL/l. 
 
 First of all, since slashes are not allowed in PL/l names, all 
 of the slashes in the names in the TP simulation are omitted. Thus DRP/G 
 becomes DRPG in the simulation. 
 
 Secondly, subscripted logic names in the TP logic are represented 
 using the standard subscript notation in PL/l. This means that DB17 becomes 
 
 9/17/69 Section 1.1.2 - 3A 
 
DB (IT) in PL/1, and DBD2/G "becomes DBDG(2). Double subscripts may be 
 expressed either as a whole block of related names with single sub- 
 scripts (i.e. T1R1 and T2R1 become TlR(l) and T2R(l)) or as doubly sub- 
 scripted PL/1 variables (i.e. N6R3 becomes NR(6, 3)). The type of repre- 
 sentation chosen depends on how much it simplifies the PL/1 code. 
 
 Probably the most important difference between the logic signal 
 names and the simulator signal names is the lack of barred control signals 
 in the simulator. The simulator always uses the unbarred version of con- 
 trol signals. Thus if a barred signal is to be simulated the simulator 
 will use an unbarred signal and test for it being '1' instead of using a 
 barred signal and testing for '0'. This distinction can be maintained if 
 it is always remembered that when a simulation signal name is '1' the cor- 
 responding logic signal names are activated and thus the unbarred forms of 
 the signal are '!' and the barred forms of the signal are '0'. 
 
 9/17/69 
 
 Section 1.1.2 - k/k 
 
1.2 Brief Overview of t he Illiac III Computer System 
 
 The Illinois Pattern Recognition Computer, Illiac III, is a 
 digital processor for visual information. It is primarily designed for 
 automatic scanning and analysis of massive amounts of relatively homo- 
 geneous visual data. In particular the design is an outgrowth of studies 
 at this laboratory of a computer system capable of scanning, measuring 
 and analyzing in excess of 3 x 10 bubble chamber negatives per year. 
 
 Illiac III, though specifically designed to process visual 
 information, also provides complete facilities for standard general- 
 purpose computation. Both the picture processing and general-purpose 
 computation facilities of Illiac III will be available to users on a 
 time-sharing basis. 
 
 As can be seen in Figure 1.2, Illiac III is a multi-processor 
 computer system. Six processors (k Taxicrinic Processors and 2 Input/ 
 Output Processors) access in parallel the computational /storage units 
 consisting of 2 Arithmetic Units, 1 Interrupt Unit, 1 Pattern Articulation 
 Unit, and 1+ Storage Units. Each computational /storage unit of the computer 
 system specializes in a particular activity. Thus, for example, all 
 floating-point computation is done in the Arithmetic Units, while picture 
 processing is performed primarily by the Pattern Articulation Unit. Proces- 
 sors, on the other hand, analyze user jobs and route their constituent 
 tasks to the appropriate specialized processing units. The individual proces- 
 sors of the system can operate simultaneously and independently (within the 
 limits imposed by the Operating System ) with a consequent increase in over- 
 all efficiency. 
 
 The Input /Out put Processors (I0P) are attached via Channel Inter- 
 face Units and Device Controllers to various input and output devices. 
 Among facilities important for the ingestion of visual information are 8 CRT 
 
 5/2/69 Section 1.2 - l/k 
 
flying spot scanners: two for TO mm film, two for h6 mm film, two for 
 microfilm/microfiche, and two for microscope slides. These scanners can 
 also operate as film cameras and thus serve as both input and output 
 devices. Monitor stations have also been attached to the Input /Output 
 system. These each consist of a CRT display, a typewriter, and a magnetic 
 tape unit; and are provided to assist human control of the analysis. 
 
 The duty of the Pattern Articulation Unit (PAU) is to perform 
 local preprocessing on the input from the scanners, such as track thinning 
 gap filling, line element recognition, etc. The logical design of this 
 all-digital processor has been optimized for the idealization of the input 
 image to a line drawing. Nodes representing end points, points of inflection, 
 points of intersection, etc. are labeled in parallel by appropriate pro- 
 gramming under overall control of the Taxicrinic Processor. The abstract 
 graph describing the interconnection of labeled nodes is then extracted 
 as a list structure, which comprises the normal output of the Pattern 
 Articulation Unit. 
 
 This output is then operated on by a Taxicrinic Processor (TP), 
 which assembles such graphs into coherent list structures subject to a 
 recognition grammar and then syntactically categorizes them to complete 
 the visual recognition process. The Taxicrinic Processors are primarily 
 responsible for the execution of user programs, that is, to oversee the 
 operations of the Pattern Articulation Unit, the Arithmetic Unit and to 
 initiate input /output operations in the I0P's by making requests to the 
 Interrupt Unit. 
 
 The Arithmetic Unit (AU) is used exclusively for performing arith- 
 metic operations for the TP. Although there are a few simple arithmetic 
 operations which can be done in a TP (e.g., integer addition) the more 
 complicated operations are done in the AU. The AU has been optimized for 
 double-word floating point arithmetic. 
 
 5/2/69 Section 1 * 2 " 2/k 
 
 
The Interrupt Unit (IU) handles all the interrupt requests from 
 the TP and I0P. When an interrupt is requested it notifies the proper 
 processors which then take appropriate action. 
 
 All of the Illiac III processors and units communicate with each 
 other through the Exchange Net (XN) as shown in Figure 1.2. The Exchange 
 Net is responsible for all the necessary queueing and priority checking. 
 
 As noted above, there is indeed a reason for calling one piece 
 of equipment a processor and another a unit , even though the type of opera- 
 tions they perform may both appear to be "processing" operations. In the 
 Illiac III system all major modules are designated as either "processors" 
 or "units" according to their position in the Exchange Net. In Figure 1.2, 
 the processors are shown at the top and bottom and the units are shown on 
 the right. The effect of this division is that processors may communicate 
 directly with units and vice versa but may not communicate directly with 
 each other. If a processor needs to communicate with another processor it 
 must get help from a unit (normally the Interrupt Unit) and if a unit (say 
 the PAU) wants to communicate with another unit (say a storage unit) the 
 information must be transferred through a processor (the TP in this case). 
 
 5/2/69 Section 1.2 - 3 A 
 
*r— **— *<: *C— 7 C 7* 
 
 **— >*— *5 ^ 7 C 
 
 \ \ \ \ ; <—? c 
 
 K \ \ \ / > C 
 
 \ \ \ \ / > L 
 
 ^c— ^<r- ^ \ / > L 
 
 T 
 
 FC(O) 
 
 X__} 
 
 SC(O) 
 
 DC(O) 
 
 ^ ^ ^ 
 
 FC(I) 
 
 SC(I ) 
 
 DC(I) 
 
 T 
 
 FC(2) 
 
 2 
 
 SC(2) 
 
 A 
 
 DC(2) 
 
 } . ) . ) 
 
 FC(3) 
 
 SCO) 
 
 DC (3) 
 
 T 
 
 AU(O) 
 
 TTl 
 
 AU(I) 
 
 A 
 
 u 
 
 ^ ^ 
 
 PAU 
 
 <* EXCHANGE NET- 
 
 J. 
 
 1 
 
 I/O PROCESSORS 
 I , 
 
 r 
 
 I 
 
 CENTRAL UNITS- 
 
 ttt.tj.^ r ^ *> VV n ,^ 
 
 CHANNEL INTERFACE UNITS 
 4|5|6|7l8|9|l0l 
 
 II 
 
 SECONDARY STORAGE 
 
 12 
 
 SCAN/DISPLAY 
 
 13 
 
 14 
 
 INTER- 
 MACHINE 
 LINKS 
 
 15 
 
 LOW 
 SPEED 
 TERM. 
 
 FIGURE 1.2 SCHEMATIC OF ILLIAC IE COMPUTER 
 
 6/16/69 
 
 Section 1.2 - h/k 
 
1.3 General Description of the Taxicrinic Processors 
 1.3.1 Basic Purpose of the Taxicrinic Processors 
 
 The Taxicrinic Processors are the central control units of 
 Illiac III. Their principal activites are the manipulation, search and 
 systemization of abstract graphs (bilateral list structures) which have 
 been produced from the pictorial input to the Pattern Articulation Unit. 
 In addition to this they also issue commands to the other Illiac III 
 processors (e.g., Arithmetic Units) whenever they are needed to perform 
 specialized operations. The name "Taxicrinic" comes from two Greek words: 
 x q E,\Q meaning "arrangement" or "pattern", and ro^ia meaning to "judge", thus 
 indicating the TP's general purpose, which is to syntactically analyze 
 digitized pictures and other material which can be cast into the form of a 
 directed, labeled graph. 
 
 Because the main purpose of a TP is to process list structures, 
 its main operations are centered around this type of operation. A certain 
 number of simple arithmetic instructions can be performed, but, in general, 
 whenever a complicated arithmetic computation must be performed, an Arith- 
 metic Unit (AU) is utilized. This is done by giving an AU a command via 
 the Exchange Net (XN). 
 
 The TP also has the ability to initiate input-output operations 
 by giving commands to the Input/Output Processor (I0P) via the Interrupt 
 Unit (IU) and to control the jobs performed by the Pattern Articulation 
 Unit (PAU). The commands necessary to exercise this control are given to 
 the various units concerned through the Exchange Net system which sets up 
 the necessary priority schemes. The Exchange Net also controls the communi- 
 cation between all the processors (including the TP's) and the various 
 storage modules. 
 
 It should be kept in mind that all four TP's are exactly the 
 same. Each is equipped with its own private fast registers and operates 
 completely independently of the other TP's. 
 
 5/2/69 Section 1.3.1 - 1/2 
 
CABLE DRIVERS 
 
 POINTER REGISTERS 
 
 AND 
 
 SPARE BUFFER REGISTER 
 
 4 CABLE TERMINATORS 
 
 ii ► 
 
 SEGMENT NAME 
 REGISTERS 
 
 PRSNB 
 
 .I ► 
 
 ASSOCIATIVE REGISTERS 
 AND 
 ASSOCIATION LOGIC 
 
 BASE/BOUNDS REGISTERS 
 AND 
 INSTRUCTION REGISTER 
 
 DB 
 
 BROS 
 
 OPERAND STACK 
 REGISTERS 
 
 W V ,r " 1 ! V. I 
 
 INPUT SIGNALS 
 
 PERMUTER 
 
 OUTPUT 
 
 T 
 
 INSTRUCTION REGISTER 
 
 IR 
 
 LOGIC REGISTER f 
 
 L R 
 
 DISTRIBUTION REGISTER ► 
 
 DR 
 
 ADDER 
 
 A 
 
 ARITHMETIC REGISTER ftR f 
 
 EXCHANGE 
 NET 
 
 
 Figure 1.3.1 - Major TP Registers and Data Paths 
 
 11/20/70 
 
 Section 1.3.1 - 2/2 
 
1-3.2 General O rganization of the Taxicrinic Processor 
 1.3.2.1 The Taxicrinic Processor 
 
 Figure 1.3.1 shows the main registers and subprocessors of the 
 TP, exclusive of the main control, together with the various data paths 
 between them. The main "active" registers are the Instruction Register 
 (IR), the Logic Register (LR), the Distribution Register (DR),the Arith- 
 metic Register (AR), and the Spare Buffer Register (SBR). These are all 
 36 bits long (h bytes of 8 bits and 1 flag each) and are used to hold data 
 temporarily as various instructions are being processed. None of these 
 are directly accessible to the programmer. 
 
 The main "storage" registers are the Base Registers 
 (8 registers of 27 bits or 3 bytes), the Associative Registers (7 registers 
 of 16 bits), the Pointer Registers (15 registers of 36 bits or k bytes), 
 the PR Segment Name Registers, (16 registers of 16 bits), the Operand 
 Stack (one continuous register of 32 bytes) and the Instruction Buffer 
 Register (one double word 8 bytes). These registers contain data which 
 may be used by the programmer during the execution of his program. They 
 are all accessible by programming except for the Associative Registers and 
 the Instruction Buffer Register, although the Base Register may 
 only be changed by "privileged" instructions. 
 
 There are other registers in the TP which are not accessible to 
 the programmer and which are used during special operations. These will be 
 fully explained in their respective sections in this manual. 
 
 Finally in connection with Figure 1.3.1 it should be noted that 
 the output from the Permuter, the Distribution Bus ( DB) , is not a register. 
 It consists of 36 lines which serve as inputs to nearly all of the registers 
 and control sections in the TP. The DB is the main avenue of information 
 transfer in the TP. 
 
 6/10/69 Section 1.3.2.1 - 1/1 
 
1-3.2.2 The TP Subprocessors 
 
 The general structure of the TP is divided up into various sub- 
 processors which are in turn controlled by the TP main control sequencing. 
 These subprocessors communicate with the main control by means of "con- 
 trol lines" which give commands to the subprocessors and "output lines" 
 which give the main control information about the status of the subprocess. 
 The subprocessors are in general fairly independent and need only receive a 
 small number of control line inputs to perform rather complex operations. 
 
 The main subprocessor groups are the Permuter, the Operand Stack 
 and Operand Stack Control, the Pointer Registers and Pointer Register 
 Control, the Base Registers and Base Register Control, the Instruction 
 Buffer Register, the 32 Bit Adder, the Boolean/Shift Logic, 
 Algebraic /Logical Compare Logic, and the Cell Size Generator. 
 
 The permuter is a system of gates and drivers which is central 
 to the transfer of information in the Taxicrinic Processor. As can be 
 seen in Figure 1.3.1 it is capable of transferring information to and 
 from all the subprocessors of the TP and essentially all of the fast storage 
 registers. One of the reasons that the permuter is required is that 
 operands are not constrained to be on "natural boundaries". For example, a 
 double word operand may have 3 bytes in one double word of core and 5 bytes 
 in the next double word of core. The permuter is used to assemble 
 these bytes into a single double word operand in the TP fast memory. 
 
 The name "permuter" is derived from the fact that an input cell 
 may be permuted to make its boundaries coincide with its destination bound- 
 aries. The permutation may be likened to a circular left shift on a byte 
 basis. The position of the four bytes is changed, but the position of one 
 relative to the other is not. For example, the cell: A B C D appears 
 as B C D A when permuted left one byte and as D A B C when 
 
 6/10/69 Section 1.3.2.2 - l/ 3 
 
permuted left three bytes. Cells smaller than k hytes (bytes or halfwords) 
 are assumed to have garbage in the non-data bytes while double words must be 
 permuted one word at a time. 
 
 In addition to permuting the input cell, the permuter has the 
 capability to inhibit all of the output bytes in any combination, or any 
 combination of bits in the rightmost output byte (byte 3). This facility 
 enables the permuter, among other things, to generate constants to put on the 
 distribution line (+32, +8, +2 and +1 are provided for) and to mask in bits 
 to the low order positions of, say the Pointer Registers, as they are gated 
 through the permuter. 
 
 The actual Permuter logic cards are also used to construct the 
 storage space for the LR, IR, AR and DR. The Permuter is described in 
 Section 2.1. 
 
 The Subprocessors for the Operand Stack, the Pointer Register 
 and the Base Register all require a more detailed description than could 
 possibly be given at this time; their complete description will be deferred 
 until Section 2. 
 
 The Instruction Buffer Register (IBR) is an eight byte (double 
 word) register used to store that portion of the instruction code which has 
 yet to be processed. It may also be used to store successive instructions 
 which will be executed after the present one. 
 
 The 32 bit Adder in the Taxicrinic Processor is used to perform 
 binary addition within the TP. It is also used to generate the outputs for 
 the Boolean operations, EQV and XOR. The adder uses 2's complement number 
 representation and employs two levels of carry lookahead to hasten carry 
 propagation.* The adder is broken down into eight four-bit sum groups with 
 full carry lookahead within the groups. The second level of lookahead occurs 
 between groups, with lookahead between groups 1, 2 and 3 and between groups 
 k through 8. The final carry between these two second level groups is a 
 "ripple" carry. 
 
 *For a more complete discussion of carry lookahead adders, see Wiegel, 
 Roger I , "Methods of Binary Addition", DCS Report No. 195, February 1 9 66. 
 
 6/10/69 Section 1.3.2.2 -2/3 
 
The Boolean logic performs the Boolean functions "AND", "OR", 
 "XOR" and "EQV". The "XOR" and "EQV" functions are generated using part 
 of the 32 bit adder. 
 
 The Shift logic employs the permuter to make shifts in multiples 
 of 8 bits. The shift control first makes the highest multiple-of-8 bit 
 shift that it can without exceeding the desired shift. This is done using 
 the permuter and inhibiting the necessary bytes. After this has been done 
 the shift control shifts one bit at a time until the proper number of addi- 
 tional bits have been shifted. Since the flags are not touched in the bit 
 shifting, the shift control only -will shift flags in multiples of 8 (i.e. , 
 when the permuter is used). 
 
 The Algebraic/Logical Compare Logic is used to accomplish alge- 
 braic and logical compares (greater, equal and less), the AR equal to zero 
 test, and flag match compares. The instructions realized are CPRA, CPRL, 
 TEST(M), SCAN(M), and TA.Operands are compared by subtracting one from 
 another; then signs are compared and appropriate indicators are set. The 
 logic discussed here can only be used with long or short fixed point numbers; 
 decimal and floating point numbers are routed to the floating point arith- 
 metic unit. 
 
 6/10/69 Section 1.3.2.2 - 3/3 
 
2. SUBPROCESSOR DESCRIPTIONS 
 
 2.1 Permuter 
 
 The Permuter is a system of gates and drivers which are 
 central to the transfer of information in the Taxicrinic Processor. 
 As can be seen in Figure 1.3.1, it is capable of transferring informa- 
 tion to and from all the subprocessors of the TP and almost all fast 
 storage registers. 
 
 The name "permuter" derives from the fact that an input cell 
 may be permuted to make its boundaries coincide with its destination 
 boundaries. A permutation begins with a circular left shift on a 
 byte basis. The position of the four bytes is changed, but the cyclic 
 ordering of the bytes is preserved. For example, the cell: 
 
 A 
 
 BCD 
 
 appears as 
 
 B 
 
 C ' D I A 
 
 when permuted left one byte and as 
 
 D 
 
 i 
 
 A : B 
 1 
 
 — — — 
 C 
 
 when permuted left three bytes. Cells smaller than k bytes (that is, 
 bytes and half-words) are assumed to have garbage in the non-data posi- 
 tions, while double words must be permuted one word at a time. 
 
 In addition to permuting the input cell, the permuter has the 
 capability to inhibit all of the output bytes in any combination, or in 
 the rightmost output byte (byte 3) to inhibit any combination of bits. This 
 
 3/5/69 
 
 Section 2.1 - 1/2 
 
facility enables the permuter, among other things, to generate con- 
 stants to put on the distribution bus (+32, +8, and +2 are provided 
 for) and to mask in bits to the low order positions of (for example) 
 the pointer registers as they are gated through the permuter. The SCR 
 (Stack Control Register) and OSTR (Operand Stack Top Register) of the 
 Operand Stack and the ICTR (instruction Counter) are the registers which 
 may be masked in. 
 
 Finally it should be noted that the permuter logic cards also 
 physically contain the registers for the LR, DR, AR and IR. Although 
 these registers are not directly used by the permuter to execute its 
 permutation operations, these registers are commonly used as sources or 
 destinations for data (see Figure 1.3.1 ) For example, the permuter 
 boards are used in data transfers from the LR and DR even though this 
 data path is not shown as going through the permuting mechanism. As a 
 matter of fact, since data going from the LR to the DR is not always permu- 
 ted, the LR can be simply gated directly to the DR whenever this is 
 desired - thus saving time. 
 
 U/U/69 Section 2.1 - 2/2 
 
2.1.1 Permuter - Functional Description 
 2.1.1.1 Permuter Input 
 
 follows 
 
 The logic used to realize the permuter input gating is as 
 
 inputs from ith 
 position of all inputs 
 to Permuter 
 
 i+27 i+18 i+9 
 
 PL3/E 
 
 PL2/E 
 
 W 
 
 PL1/E 
 
 PLO/E 
 
 input driver 
 
 W 
 
 W 
 
 *all arithmetic 
 is Mod(36) 
 
 U 
 
 i output also goes to i-9 
 
 i-18 
 i-27 
 
 Figure 2.1.1.1/1 - Permuter Schematic 
 The PLi/E are the permutation selection gate signals. PL3/E, 
 for example, enables the left 3 permutation. PLO/E is the straight -through 
 (left zero) gate. 
 
 3/5/69 
 
 Section 2.1.0.1- 1/2 
 
Every possible input to the permuter has a gated line which 
 is an input to the input driver (see figure above). Thus each bit in 
 any input byte will go to one of the 36 input drivers depending on which 
 byte it is in and its position in that byte. The outputs of these input 
 drivers go to the corresponding bit positions in each of the four byte 
 positions. Here they are gated with the corresponding permute signal. 
 
 As an example, input driver 36 will have as inputs the 36th 
 bit of all permuter input registers. This is the 9th position (flag) 
 in the 3rd byte (bytes are numbered from the left to 3). Thus the 
 output of input driver 36 is gated to position 36 by the PLO/E signal, to 
 position 27 by the PLl/E signal, to position 18 by the PL2/E signal and 
 to position 9 by the PL3/E signal (i.e., the 9th bit position of each 
 byte). At the same time position 36 of the permuter will be receiving 
 the outputs of input drivers 9, 18 and 27 which will be gated with PLl/E, 
 PL2/E and PL3/E, respectively. Thus the output (pin P in the diagram 
 above) for the 36th bit position will depend on which of the h permute 
 signals is activated. 
 
 /69 Section 2.1.1.1 - 2/2 
 
2.1.1.2 Permutation Control Logic 
 
 Once the input has been selected by enabling the gate from 
 the desired register to the input drivers, the Permutation Control Logic 
 ensures that the proper permutation takes place. This logic has 3 
 inputs: a source bit-pair, a destination bit-pair and a reversing bit. 
 
 To determine the permutation which is desired, the position 
 of the first byte of the cell must be known for both the source and 
 destination registers. These positions are given by the bit-pair 
 "addresses" as shown in the figure below. Here an address of "00" 
 indicates that a cell is to be left-justified in its source (destination) 
 register. This address code is also just the low order two bits of a 
 memory address or the low order two bits of the Stack Control Register 
 in the Operand Stack logic or the Instruction Byte Counter. 
 
 00 01 
 
 10 
 
 11 
 
 Bit-Pair Address Convention 
 
 In summary then, the source bit-pair indicates the position 
 of the left-most byte of the cell in its source register. In like manner 
 the destination bit pair gives the position the left-most byte 
 is to occupy in the destination register. 
 
 The reversing bit is used to specify the direction in which 
 the data is to flow. In the permuter the paths which must be provided 
 with permutation are: 
 
 1. Memory to registers (LR, DR, AR, IR) - left justified 
 
 2. Operand Stack to registers - left or right justified 
 
 9/26/69 Section 2.1.1.2 -1/3 
 
3. Base Registers to registers - left justified 
 k. Instruction Buffer to registers - left justified 
 or justified on "byte 1. 
 
 The "natural" flow of information is taken to be from the 
 various types of storage (memory, stack, buffer, etc.) to the working 
 registers (IB, DR, AR, IR). For this direction the reversing bit is 
 considered off (0). When the reversing bit is on (l), the data flows 
 in the reverse direction and the permutation is changed accordingly. 
 
 Gating signals from main control select the permuter input and 
 signify left or right justification (if required). The Permutation Control 
 Logic then works by feeding the proper bit-pairs into the source and 
 destination pair buses. After the two bit-pairs have been loaded, the 
 reversing bit (RSD/E) is used to gate them to the decoding circuits (see 
 Section 2.1.1.3). If the data flow is in the "natural" direction the 
 source bit-pair and destination bit-pairs are gated straight through to 
 the X and Y busses respectively (as they are called in Section 2.1.1.3). 
 While if the data flow is in the "reverse" direction the source bit-pair 
 is gated to the Y lines while the destination bit-pair is gated to the 
 X lines. 
 
 When none of the four "natural" or "reverse" data paths are 
 being evoked, the source and destination inputs to the decoder are in 
 the rest state, 00/00 which decodes as "gate straight through", i.e. 
 without permutation. Thus if a data path other than one of these four 
 is used, and no permutation is necessary, the data transfer can be 
 carried out without concern for the permuter control inputs. One specxal 
 case does arise: right and left shifting in steps of 9 bits; in this case 
 all the internal permutation signals of the permutation control logxc 
 are disabled using the LRS/E signal. The proper permutation for the shift 
 required is decoded (along with inhibit signals - see Section 2.8.1.2 in 
 the Shift Control Logic) and is routed directly to the permutation gate 
 drivers (output signals PLO, PL1, etc.) to effect the permutation. 
 
 7/19/69 Secti ° n 2 - 1 ' 1 - 2 ' 2/3 
 
The LRS/E signal is also turned on automatically 
 whenever one of the direct permutation control lines from the main 
 control logic is turned on. This inhibits the normal operation of 
 the permutation control and allows the main control logic to determine 
 the permutation. 
 
 9/17/69 Section 2.1.1.2 - 3/3 
 
2.1.1.3 Permutation Decoding 
 
 If we let )^X be the source byte "address" bit-pair and 
 Y Y be the destination bit-pair, then these can be considered a 
 four-bit binary number which can be decoded to give the proper permuta- 
 tion. If the four permutation control signals are designated PLO , PL1 , 
 PL2 and PL3 , they can be expressed in terms of XX and Y Y as: 
 
 Left 0: PLO: = X^Y^ v X^Y^ v X^Y^ v X^Y^ 
 
 5 10 15 
 
 Left 1: PLI: = \^-J 2 v X^Y^ v X^Y^ v X^Y^ 
 
 h 9 ik 3 
 
 Left 2: PL2 : = X^Y^ v X^Y^ v X^Y^ v X^Y^ 
 
 8 13 2 7 
 
 Left 3: PL 3 : = X^Y^ v X lX2 Y lY2 v X^Y^ v Xl X 2 Y lY2 
 
 12 1 6 11 
 
 The PLi signals are then used to drive the four groups of (36 
 each) permutation gates. 
 
 There are also "direct" inputs to the PLi drivers. In this case 
 the desired permutation can be selected directly without decoding from 
 X , etc. An example of this is the shift control logic. If a "direct" 
 input is used, the decoder is inhibited by the LRS/E signal input. The 
 direct inputs go directly to the PLi drivers in complement form. 
 
 3/5/69 Section 2.1.1.3 - 1/1 
 
2.1.1. U Permuter Output 
 
 The basic output of the Permuter is the Distribution Bus (DB). 
 This bus is a k byte (36 bit) bus and serves as an input to all the major 
 registers and storage areas in the Taxicrinic Processor. 
 
 Although not shown in Figure 1.3.1, the DB is, in reality, 
 made up of two separate busses which are arranged as shown below: 
 
 Permuter Output 
 
 to DR, IR, 0S 
 
 PR, BR, IBR, SBR 
 
 to AR, LR, etc. 
 
 Figure 2.1.1.U/1 - Distribution Bus 
 The DBP bus specifically drives the DR, IR, 0S, the PR's, the BR's, 
 the IBR and the SBR. The DB bus drives the AR, LR , the NR » s , the 0S control 
 logic, the BR name storage flip-flops, the instruction byte counter, the 
 shift boolean logic, the adder input gates, the bounds check logic, and 
 the cable drivers to the Exchange Net. 
 
 In this manual, reference to the Distribution Bus (or DB) will 
 mean either of these two busses since their contents are logically equivalent 
 Reference to DBP however will specifically mean the DBP part of the 
 Distribution Bus. 
 
 U/8/69 
 
 Section 2.1.1.U - l/l 
 
2.1.1.5 Inhibit Generation Logic 
 
 In Figure 2.1.1.5/1 we give a more complete version of the 
 logic circuit shown in Figure 2.1.1.1/1. As can be seen, several masking 
 options have been dot-or'ed with the input driver and an inhibit signal 
 has been added to the output. The purpose of this section is to describe 
 the effects which can be achieved using these supplementary features. 
 
 First, however, we shall run through a general description of the 
 
 circuit with particular attention to inhibit conditions. Note that due to the 
 
 dot-orjm the FBI line, if any of the masking option lines are selected, 
 
 the FBI will be forced to "0" . This in turn v-m fo W /. a + *, 
 
 -Liixb ±n T,urn will force the corresponding 
 
 DBP bit position to "1" (assume for the moment that only PLO/E is "l"). 
 
 It should be noted that the inhibit line will force the DBP to "0" if it 
 
 is turned on, independent of the FBI signal. Thus we have two methods 
 
 for changing the DBP: We can force the DBP to "l" by turning on one of 
 
 the masking options, or we can force the DBP to "0" by turning on the inhibit. 
 
 Now we can begin to consider the various effects that can be 
 accomplished using these two methods. The permuter is capable of inhibiting 
 any combination of bytes in the output using the IBO/E, IB1/E, IB2/E, and 
 IB3/E signals. Each of these signals is hooked up to the 9 corresponding 
 bit position inhibit signals on the output of the Permuter. In addition 
 any combination of bits in the rightmost byte of the Permuter Output 
 (byte 3) may be inhibited since the bit inhibit lines for this byte are 
 made so they can be controlled individually if desired (see TP logic 
 drawings 04-5 and 0U-3). 
 
 It is also possible to construct constants using the Permuter. 
 If all of the input gates are turned off (referring again to Figure 2.1.1.5/1), 
 the FBI lines will all be "l" which will cause the DBP bus to contain all 
 zeroes. Then in order to make positive constants, the corresponding FBI 
 lines need only have one of their "masking options" turned on. The positive 
 constants which are provided are + 1 , +2 , + 8 and +3 2 (all 2's complement). 
 
 V25/69 
 
 Section 2.1.1. 5 - 1/5 
 
MASKING 
 OPTIONS 
 
 INPUTS 
 
 at most only 
 I on 
 
 > 
 > 
 
 INPUT 
 DRIVER 
 
 PLO/E 
 
 INHIBIT 
 
 = I, if mask bit =0 
 
 U 
 
 FBI 
 
 
 DBP OUTPl, 
 BUS 
 
 FIGURE 2.1. 1. 5/1 INHIBIT GENERATION LOGIC. 
 
 5/2/69 
 
 Section 2.1.1.5 - 2/5 
 
 
In order to generate negative constants all l's are put on the 
 output bus by inhibiting the PLO/E signal with LRS/E. If no other PLi/E 
 signals are on, the DBP will become all ones. Then a one's complement 
 number can be produced by inhibiting the proper output position. This 
 number is changed to two's complement in the adder by injecting a low-order 
 carry. The negative constants which are produced in this manner are -1, -2, 
 -8 and -32 (all l's complement). 
 
 The final effect which can be produced is masking. In many cases 
 it is desired to mask the SCR, 0STR, or ICT into the lower order bits of 
 a pointer register. Here the FBI lines corresponding to the positions 
 which are to be masked in, are set to zero by one of the masking option 
 signals. This causes the corresponding output bit position to become "l". 
 The actual contents of the register to be masked is used to set the 
 inhibit lines. If a given bit position in the register is "0", the 
 corresponding inhibit line is set, thus causing the Permuter output to be 
 "0" in that position. 
 
 In two of the masking cases given above (ICT and SCR) the masking 
 is done automatically. Whenever PR#0 is used as the input to the Permuter 
 the ICT is automatically masked into the lowest 3 bits. Whenever PR#13 is 
 the input, the SCR is masked into the lowest 5 bits. During Operand Stack 
 overflow or underflow (see Sections 2.2.2.5 and 4.2.2.8) the 0STR (2 bits) 
 must be masked into the Vth and 5th lowest order bits with zeros in the 
 lowest 3 bits of PR#13. Since the SCR is normally masked into PR#13 there 
 must be an inhibit to SCR masking when the 0STR is being used instead. 
 
 With this in mind the control logic necessary for the automatic 
 masking of the ICT and SCR are given in Figure 2.1.1.5/2 and /3 respectively. 
 The signal definitions are given below: 
 
 PRP/G = 1 if a PR is the permuter input 
 
 N13S = 1 if the TGR = 13 
 
 NOS = 1 if the TGR = 
 
 NPR13/S = 1 if control selects PR#13 
 
 NPRO/S = 1 if control selects PR#0 
 
 OSTP/G = 1 if the OSTR is to be masked into PR#13 
 
 OSR = data bus to the inhibit signals 
 
 SCRP/G, ICTP/G = mask select signals 
 
 V25/69 Section 2.1.1.5 -3/5 
 
ICT 
 
 PRP/G — { 
 TNB/G 
 NOS 
 
 PRP/G — 
 NPRO/S — 
 
 DBP 
 
 IC LO'GIC IN DRIVER FROM K " 
 
 
 CONTROL CONTROL LOGIC DTL LOGIC IN LOWER BAY 
 
 FIGURE 2.1.1.5/2 ICT MASKING CONTROL LOGIC 
 
 5/16/69 
 
 Section 
 
 2.1.1.5 - U /5 
 
OSTP/G 
 
 OST R 
 
 SCR 
 
 16 
 
 lH 
 
 PRP/G 
 
 OSTP/G 
 NI3S 
 
 16-1 \> 
 
 SCRP/6 
 
 PRP/G 
 
 OSTP/G 
 
 NPRI3/S 
 
 OSTP/G 
 
 16-1 p 16-1 D 
 
 y SCRP/G \ \ r 
 
 OSR 
 
 04- 5V 
 
 B3i 
 
 DBP 
 
 FIGURE 2.1.1.5/3 SCR MASKING CONTROL LOGIC 
 
 5/2/69 
 
 Section 2.1.1.5 - 5-/5 
 
2.1.1.6 Gate Inhibits for the LR and IR 
 
 As mentioned previously in Section 2.1.1, the Permuter cards 
 physically contain the LR, AR, IR and DR flip-flop storage. These 
 registers are built up from a "latch" type flip-flop which is shown and 
 described in Figure 2.1.1.6/1. In order to load a new value into the 
 latch flip-flop, the gate must be on and the latch signal must be off. 
 
 The gating inputs for each of these h registers are organized 
 on a byte basis, i.e. each gating signal is used to activate the h gate 
 and k latch lines to the appropriate register. In this process it is 
 quite simple to impose gate inhibits on the individual bytes of a register, 
 and this is exactly what was done in the case of the DR and the IR. 
 
 The rest of this section will describe the LR gate inhibit logic. 
 The IR logic is quite similar and may be found in the TP Logic Book in the 
 Series-OU drawings. The LR gate which is inhibited is the DR-to-LR gate. 
 The logic for this inhibition is shown in Figure 2.1.1.6/2. DLR/G is 
 the main gating signal from the control logic. It is NAND'ed with 
 
 DLRi/N (i = 1, 2, 3, k) , one of Ij- inhibit lines. Thus if DLRi/N = "l" , 
 the gate signal will be inhibited and the gating and latching signals to 
 the ith byte of the LR will not be activated. Note that other signals 
 such as the right shift enable, RS/E, the AND enable, AND/E, or others 
 can also set the LR latch signal to and the gate signal to 1. 
 
 This facility is used mainly in the merging operations in the 
 memory access sequencing. It is also used in other control sequences 
 where it is desired to replace part of the contents of a register and 
 leave the remaining contents unmodified. 
 
 h/Q/69 Section 2.1.1.6 - 1/3 
 
GATE 
 "A 
 
 LATCH 
 
 OUT 
 
 n 
 
 i>o 
 
 *OUT 
 
 where n = 0,l,2," • additional gates 
 
 Gate: enables A to be transmitted to the NOR 
 
 Latch: when off, allows the output of the gate AND's to deter- 
 mine the state of the flip-flop. When ON maintains 
 state of the flip-flop so, that gates will not affect it 
 
 Figure 2.1.1.6/1 - Latch Logic Circuits 
 
 H/8/69 
 
 Section 2.1.1.6 - 2/3 
 
RS/E 
 
 AND/E 
 
 DLRO/N 
 DLR/G 
 
 DLRI/N 
 
 DLR2/N 
 
 DLR3/N 
 
 5/16/69 
 
 > 
 
 > 
 > 
 
 > 
 
 > 
 > 
 
 -Z> 
 
 r> 
 
 >-o 
 
 > 
 > 
 
 > 
 
 ■o 
 
 ~> 
 
 -~> 
 
 LRLO 
 
 LRO/G 
 
 LRLI 
 LRI/G 
 
 LRL2 
 LR2/G 
 
 LRL3 
 
 LR3/G 
 
 L R Li = LATCH 
 LRi/G=GATE 
 
 FIGURE 2.1.1.6/2 GATE INHIBIT CIRCUIT 
 
 Section 2.1.1.6 
 
 - 3/3 
 
2.1.1.7 Permuter Register Gate Drivers 
 
 These gate drivers are used to drive the various flip-flop 
 (latch) register and permuter input gates. The various gating lines 
 can be found on the 237-00 card schematic in the circuit book or in the 
 TP Logic Book. Each -237 card contains one bit position of the permuter 
 as well as the LR, DR, AR, IR registers. 
 
 There is only a single input to the LR, AE and IR; all the various 
 gating signals are combined in the control gating logic, and the single 
 gate and latch signal needed is sent to the register on a per byte basis. 
 The data inputs are combined in a dot-or (see, for example, the SHIFT/ 
 BOOLEAN logic). Note that the LR and AR are loaded with the complement 
 of the desired output. 
 
 The gating signals are formed on a byte basis; there is a 
 group of drivers for each register byte (9 bits). 
 
 Provision is made to inhibit bytes on certain transfers, these 
 being: DR to LR; adder to AR, and DB to IR. In this case, the inhibit 
 implies that the byte inhibited is not transferred into the register in 
 question. The original register contents remain unchanged however — 
 nothing is set to zero. This feature allows bytes to be masked into a 
 common register (c.f. PR transfer logic). 
 
 U/8/69 
 
 Section 2.1.1.7 - l/l 
 
2.1.2 Signal Name Lists for the Permuter 
 2.1.2.1 Control Signals 
 
 Input Select Gates : 
 
 ARP/G/ - AE is the permuter input storage block 
 
 BR/S - Select BR from BR-IBR 
 
 BRSP/G/ - BR-IBR Storage Block output bus (BR0Si) is the permuter 
 
 input 
 CTP/G/ - Cable terminators is the permuter input 
 DRP/G/ - DR is the permuter input 
 IBR/S - Select IBR from BR-IBR Storage Block 
 ICTP/G - Mask ICT into low-order 3 bits of DB 
 IRP/G/ - IR is the permuter input 
 LRP/G/ - LR is the permuter input 
 
 OSP/G/ - Operand stack output bus (BR0Si) is the permuter input 
 PRP/G/ - Pointer register output bus (PRBi) is the permuter input 
 SCRP/G/ - Mask SCR into low-order 5 bits of DB via OSR bus and 
 
 permuter 
 Constant Generator Enable Signals : 
 
 Ml/E/ 
 M2/E/ 
 MU/E/ 
 M8/E/ 
 M32/E/ 
 
 Generate -1 
 Generate -2 
 Generate -h 
 Generate -8 
 Generate -32 
 
 Pl/E 
 P2/E 
 PU/E 
 P8/E 
 P32/E 
 
 Generate +1 
 Generate +2 
 Generate +h 
 Generate +8 
 Generate +32 
 
 6/17/69 
 
 Section 2.1.2.1 - 1/3 
 
Reg 
 
 ister Transfer Gate Signals 
 
 ADR/G/ 
 BAR/G/ 
 BDR/G/ 
 BIR/G/ 
 BLR/G/ 
 CDR/E/ 
 DLR/G/ 
 LDR/G/ 
 
 Gate AR to DR - direct 
 
 Gate DB to AR 
 
 Gate DBP to DR 
 
 Gate DBP to IR 
 
 Gate DB to LR 
 
 Gate DB + spares to cable driver 
 
 Gate DR to LR - direct 
 
 Gate LR to DR - direct 
 
 Register Transfer Byte Inhibit Signals 
 
 ADDO/N/ 
 ADD1/N/ 
 ADD2/N/ 
 ADD3/N/ 
 
 Inhibit adder output byte i 
 
 BIRO/N/ 
 BIR1/N/ 
 BIR2/N/ 
 BIR3/N/ 
 
 Inhibit byte i on DBP to IR gate 
 
 DLRO/N/ 
 DLR1/N/ 
 DLR2/N/ 
 DLR3/N/ 
 
 Inhibit byte i on DR to LR gate 
 
 6/17/69 
 
 Section 2.1.2.1 - 2/3 
 
Permutation Control Signals: 
 
 BNR/G 
 
 CRRL/G 
 
 LJI/E 
 LRS/E 
 
 OPJ/E 
 
 OSRL/G 
 OSRR/G 
 OSS/S 
 
 RJI/E 
 RSD/E 
 
 Base name register gate. Uses contents of base 
 
 name register to control permutation of data into 
 
 or out of (depending on RSD/E) "base register 
 
 storage. 
 
 Gate "core" to registers (DR, LR, etc.) left 
 
 justified 
 
 Left justify 
 
 Inhibits normal operation of permutation control 
 
 logic. 
 
 This signal is used by the shift control logic 
 
 to perform shifts in byte multiples using the 
 PLi and/or IBPLij signals. It must also be used 
 when the PLCi signals are used by the main control 
 
 logic to generate a permutation. Note! One of 
 
 the above mentioned signals must be on when 
 
 LRS/E is on in order for the permuter to work 
 
 properly. (See Section 2.1. U. 3) . 
 
 Used if IBRP/G is also on. Justifies opcode on 
 
 byte 3 instead of byte 0. 
 
 Gate OS to registers right justified 
 
 Gate OS to registers left justified 
 
 Select OS. Turns on when either DBOS/S or 
 
 DSP/G is 'on'. 
 
 Right justify 
 
 Reverses role of source and destination bits in 
 
 permutation control 
 
 9/17/69 
 
 Section 2.1.2.1 - 3/3 
 
2.1.2.2 "Internal" Signals Used by the Permuter 
 
 Logic Book Name 
 
 ARi 
 
 ARi/G 
 
 ARGi/G 
 
 ARLi 
 
 ARNi/ 
 
 BRSP/G 
 
 CSB 
 
 CSBH 
 
 CSH 
 
 CTi 
 
 DBi 
 
 DBDi/G 
 
 DBPi 
 
 DRi 
 
 DRLi 
 
 FBIi 
 
 IBi/E 
 
 IBPL13 
 
 IBPL21 
 
 IBi/ 
 
 ICTi 
 IRi 
 IRi/G 
 IRLi 
 
 Description 
 
 Arithmetic Register - bit i 
 
 AR input gating signal, ARN — >AR - byte i 
 
 Gate signal, AR-^DR, byte i 
 
 AR latch, always = ARi/G- byte i 
 
 Adder output bus = AR input - bit i 
 
 Permuter in gate signal, BR0Si— ^FBIi, = 
 
 OSP/G v BRS 
 
 Cell size = byte 
 
 Cell size = byte or halfword 
 
 Cell size = halfword 
 
 Cable Terminators - bit i 
 
 Distribution Bus, bit i = DBPi 
 
 Gate signal, DB— > DR - byte i 
 
 Distribution Bus directly from permuter - bit i 
 
 Distribution Register -bit i 
 
 DR latch, byte i = whenever something— *DR - 
 bit i 
 
 Output from permuter input gate - bit i 
 
 Inhibit Enable - byte i 
 
 Inhibit byte 1 - permute left 3 
 
 Inhibit byte 2 - permute left 1 
 
 Inhibit signal for byte i - from shift 
 
 control 
 
 Instruction byte counter - bit i 
 
 Instruction register - "bit i 
 
 IR input gating signal DB-^IR - byte i 
 
 IR latch, always = IRi/G - byte i 
 
 5/16/69 
 
 Section 2.1.2.2 - 1/2 
 
Logic Book Name 
 
 LRi 
 
 LRDi/G 
 
 LRi/G 
 
 LRLi 
 
 LRNi 
 
 OSRi 
 
 OSTRi 
 PLi 
 
 PLi/E 
 PRBi 
 SCRi 
 T2Ri 
 
 Description 
 
 Logic Register ~ bit i 
 
 Gate signal, LR-> DR - byte i 
 
 LR input gating signal LRN— > LR - byte i 
 
 LR latch, = LRi/G - byte i 
 
 In-bus to LR - comes from SHIFT/BOOLEAN and 
 
 PACK-UNPACK, etc. _ byte i 
 
 Bus used to insert 0STR, SCR and ICT onto 
 
 permuter output (last 5 bits) 
 
 Operand Stack Top register 
 
 Permute left i bytes - output from shift 
 
 control 
 
 Enable permute left i bytes 
 
 Pointer Register Bus - bit i 
 
 Stack Control Register - bit i 
 
 Temporary Register 2 in Operand Stack - bit 
 
 5/16/69 
 
 Section 2.1.2.2 - 2/2 
 
iiii/» iib, ibL, hl) (0:3) BIT(l); 
 
 ,RROS,CT,DB,DBB,DBP,DR,IR,LR,PRB) (36) ♦ (BNR, ICT ) (3) , 
 ,CCT)(4), (SCR,T2R) (5) , 0STR(2), BRS(0:7)) 
 
 RITI1 \ CVTCDMAI • 
 
 2.1.3 Permuter - PL/I Description 
 
 FXFC PL1 
 
 ■Ll.SYSPUNCH nn SYSOUT=B 
 
 PL 1. SYS IN DO * 
 
 PFR_IN: PROCURPG, BNRG,BRGS, BRSBPG, CRRLGt CSR, 
 
 CSBH, CSH, CTPG, DBRJ, DRPG, IBPL13, 
 
 IBPL21, IBRSt ICTPG, IRPG, LJIE, LJOPE, 
 
 LRPG, LRSEt M16E, MIEt M2E, M32E, 
 
 M^E. M8Et MRSETG, OPJE, OSPG, OSTPG, 
 
 P16E, PIE, P2E, • P32E, P4E, PRE, 
 
 PLC1, ?LC2, PLC3, PRPG, RJIF, RSOE, 
 
 SCRPG, LRSF1, IB, IBC, PL, HSSS, 
 nsPTG, nsPFG); 
 
 OCL (OSPTG,nSPFG) BIT(l); 
 HCL LRSE1 BIT(l); 
 
 dcl nsss bit ( 1 ) ; 
 
 DCL( ARPG,BNRG, BRGS, BRSBPG, CPRLG, CSB, 
 
 CSRH, CSH, CTPG, DBRJ, DRPG, IBPL13, 
 
 IBPL21, IBRS, ICTPG, IRPG, LJIF, LJOPF, 
 
 LRPG, LRSE, M16E, M1E, M2E, M32E, 
 
 M 4F, MRE, NRSFTG, OPJF, OSPG, OSTPG, 
 
 P16F, PIE, P2E, P32E, P4E, PRE, 
 
 PLC1, PLC2, PLC3, PRPG, RJIF, RSDF, 
 
 SCRPG) BIT(l), (IB, IBC, PL) (0:3) BIT(l) 
 nCL( (AR 
 (ACT 
 
 BIT(l) external; 
 
 OCL 
 
 OCL FBK36) BIT( 1 ) , I BE ( : 2 ) B I T ( 1) ,IBE3(1 :9)BIT( 1 ) , 
 (S 
 P 
 ( I ,J ) 
 DSPG=()SPTG I DSPFG; 
 I* DFTFRMINE LFNGTH OF SHIFT FROM SOURCE AND DESTI- 
 NATION POSITIONS, S AND 0. IF LRSE IS ON INHIBIT 
 NORMAL COVTROL.*/ 
 
 LRSF = MIE|M2E|M4E|MRE|M16E|M32E|LRSF1 I PLC1 I PLC2 I PLC3 ; 
 
 IF LRSF THFM DO; 
 
 PLI0F,PLI1E,PLI2E,PLI3E=»0'B; 
 GO TO SKIPSD; 
 FND; 
 
 S(0),S(1),D(0),D(1)='0'B; 
 
 IF BRGS THEN DO; 
 
 S(0)=BRS( 1 ) |BRS(2) |BRS(5) |BRS(6) ; 
 
 S(1)=BRS(1)|BRS(3)|BRS(5)|BRS(7); 
 
 END; 
 
 if dbrj then do; 
 
 d(0)=csh; 
 
 0(1 )=CSB; 
 
 END; 
 IF OSSS THEN DO; 
 
 S(0 )=T2R(4) ; 
 
 S(l )=T2R(5) ; 
 
 END; 
 
 Bl I ( 1 ) EXTERNAL ; 
 (PLI0F,PLI1F,PLI2E,PLI3F) BIT(l); 
 BI (36 ) BIT(l),IBE(0:2)BIT(l),IBE3(l: 
 S,D) (0:1 )BU( 1 ) ,OSR( 1:5) BIT(1 ), 
 PLOF,PLlF t PL2E,PL3E,BRSPG) BIT( 1 ), 
 I , J ) FIXED BIN; 
 
 HA/70 
 
 Section 2.1.3 - 1/9 
 
IF BNRG THEN DO; 
 S (1 )=BNR(3) ; 
 S(0)=BNR(2)£(-BNR(3) ) 
 
 |BNR(3)£(-BNR(2) ) 5 
 
 END; 
 
 IF CRRLG THEN DO; 
 S(0)=AR(3A); 
 S(l )=AR(35) ; 
 END; 
 
 IF IBRS THEN DO; 
 
 S(0)=ICT(2 ) ; 
 S(l ) = ICT(3) ; 
 D(l )=GPJE; 
 
 END; 
 
 IF LJGPE THEN n(l)='0 , B; 
 IF RSDE THEN 
 
 BEGIN; 
 
 DCL TEMP(0: 1 ) BIT( 1 ) ; 
 TEMP=S; 
 
 S = d; 
 
 D=TEMP; 
 
 end; 
 
 no 
 
 PLI0F= -S(0)£-S( 1)£-D(0)£-D( 1 
 |-,S(0)£ S( 1)£-.D(0)S D(l 
 | S(0)£-S( 1)£ D(0)£-D(1 
 | S ( ) & S ( 1 ) £ D ( ) 6 D(l 
 
 PLI1E- -S(0)£ S( 1 )£--D(0) &-.D( 1 
 | S(0)6-«S(1>£'-D(0)6 D(l 
 | S(0)£ S(l)£ D(0)£-D(1 
 |-.S(0)£-'S( 1)£ D(0)£ D( 1 
 
 PLI?F= S(0)£-S( 1)£-D(0)£-D(1 
 | S(O) £ S( 1)£^D(0)£ D(l 
 |-.S(0)£-S(1>£ 0(0) £-.&(! 
 |-.S(0)£ S< 1)£ D(0)£ 0(1 
 
 PI I3E= S(0)£ S(1)£-D(0)£-D(1) 
 |-.S(0)£-^S(1)£-*D(0)£ 0(1 
 |-,S(0)£ S( 1)£ 0(0) £-0(1 
 I S(0)£->S( 1 )£ 0(0)£ 0(1 
 
 end; 
 skipso: pl0f=pli0e |pl(0) ; 
 
 PL1F=PLI1E|PL( 1) I IBPL21IPLC1; 
 
 PL2F = PLI2E|PL(2) |PLC2; 
 
 PI 3E=PLI3F|PL(3)|IBPL13|PLC3; 
 
 /* SELECT PRGPFR INPUT TO BE GATED*/ 
 
 F B I = ' ' B ; 
 
 brspg='0'b; 
 
 IF ORPG THEN FBI=DR; 
 
 ll/H/TO 
 
 Section 2.1.3 - 2/9 
 
IF IRPG THFM FB I = I R ; 
 
 IF LRPG THFN FBI=LR; 
 
 IF ARPG THFN FBI=AR; 
 
 IF PRPG THEN FBI=PRB; 
 
 IF CTPG THFM FBI=CT; 
 
 IF HSPTGI OSPFGI BRSBPG THEN DO; 
 
 BRSPG=«1»B; FBI=BRnS; END; 
 
 /* CHFCK FOR MASKING */ 
 
 IF nSTPG | SCRPG THFN DO 1=31 TO 35; 
 FB I ( I ) = • 1 • B ; 
 END; 
 IF ICTPG THFN OH 1=33 TO 35; 
 FBI ( I )=' 1 «B; 
 END; 
 IF MRSETG THEN 00 1=1 TO 4; 
 FBI ( I+27)=ACT( I ) ; 
 FBI ( 1+31 )=CCT( I ) ; 
 fnd; 
 /* DFTERMINE INPUTS TO INHIBIT ENABLF NETWORK FROM 
 OPERAND STACK.-/ 
 
 nSR= '1 "B; 
 
 IF OSTPG THFM 00; 
 
 OSR( 1 )=OSTR( 1 ) ; 
 
 gsr(2 )=nsTR(2 ) ; 
 
 0SR(3) ,0SR(4) ,0SR(5)='0'B; 
 
 END; 
 
 IF SCRPG THEM OSR=SCR; 
 
 /* DFTFRMINE INPUTS TO INHIBIT ENABLE NETWORK FROM 
 INSTRUCTION BYTE COUNTER.*/ 
 
 IF ICTPG THEN 00; 
 
 OSR( 1 ) T OSR( 2)='0'B; 
 DO 1=1 TO 3; 
 
 OSR( I+2) = ICT( I ) ; 
 
 END; 
 
 FND; 
 
 /* CALCULATE INHIBITS.*/ 
 
 IBE=»0'B; 
 
 00 1 = 1 TO 3; IBE3( I ) = '0'R; end; 
 
 00 1=1 TO 5; IBE3( I+3)=-»0SR(I ); END; 
 
 IF RJIE THFN 00; 
 
 IF CSBH THEN IBE(0)= I 1 'B; 
 
 IF CSH THEN IBE( 1 ) = • 1 «B; 
 
 IF CSB THEN I BE ( 1 ) t I BE ( 2 ) = ' 1 • B ; 
 
 END; 
 IF LJIF THFN DO; 
 
 IF CSBH THEN IBE3=« 1 «B; 
 
 IF CSH THEN IBE(2)=' l'B; 
 
 11/14/70 Section 2.1.3 - 3/9 
 
IF 
 IF 
 IF 
 IF 
 IF 
 IF 
 
 IF CSR THEN IBE(l) , I BE ( 2 ) = ' 1 ' B ; 
 
 END; 
 
 IBPL13 THEN I3E(1)='1'B; 
 IBP121 THEN IBE(2)='1'B; 
 IB(O) I IBC(O) THEN IBE(0)='1'B; 
 18(1)1 IBC(l) THEN IBE(1)»'1'B; 
 IB ( 2 ) I IBC(2) THEN IBE(2)='1'B; 
 IB(3) I IBC(3) THEN' IBE3='1'B; 
 
 /* CHECK FOR INHIBITS FROM CONSTANT GENERATOR.*/ 
 
 IF M1E THEN IBE3(8)=« l'B; 
 
 IF M2E THEN I BE3 ( 7 ) = ' 1 ' B ; 
 
 IF M4E THEM I BE3 ( 6 ) = ' 1 ' B ; 
 
 IF M8F THEM I B E3 ( 5 ) = ' 1 ' B ; 
 
 IF M16E THEN IBE3(4)=« l'B; 
 
 IF M32E THEN IBF3(3)=' l'B; 
 
 IF P1F THEN FBI (35) = ' 1 'B 
 
 IF 
 IF 
 IF 
 IF 
 
 IF 
 
 P2E 
 
 P4E 
 
 P8F 
 
 P16F 
 
 P32E 
 
 THEN 
 THEN 
 THEN 
 THEN 
 THFM 
 
 FBI (34) = ' l'B 
 FBI (33)=' l'B 
 FBI (32 )=' l'B 
 FBI (31 ) = ' 1 'B 
 FBI (30)=' 1 'B 
 
 DBP=' l'B; 
 
 /* SFLFCT ANO PERFORM SHIFTS.*/ 
 
 IF PLOF THEN OBP=FBI ; 
 IF PL1F THEN 00; 
 
 DO 1=1 TO 27; 
 
 DBP( I )=FBI ( 1+9) ; 
 
 end; 
 
 DO 1=1 TO 9; 
 
 DBP( I+27)=FBI ( I ) ; 
 
 END; 
 
 end; 
 
 IF PL?F THEN DO 1=1 TO 18; 
 
 DBP( I )=FBI ( 1 + 18) ; 
 DBP( I+18)=FBI ( I ) 5 
 END; 
 
 IF PL3F THEN DO; 
 
 DO 1=1 TO 9; 
 
 DBP( I ) = FBI ( 1+27) ; 
 
 END; 
 
 DO 1=1 TO 27; 
 
 DBP( I + 9)=FBI ( I ) 5 
 
 end; 
 END; 
 
 /* CHECK IB INHIBITS.*/ 
 
 IF IBF(O) THEN DO 1=1 TO 9; 
 DBP( I ) = '0'B; 
 
 li/U/TO 
 
 Section 2.1.3 - U/9 
 
FNO; 
 IF I HF( 1 ) THEN OH 1=1 TO 9 ; 
 
 ORP( I+9)=»0'B; 
 FNO; 
 IF IRF(? ) THFM 00 1 = 1 TO 9; 
 
 DBP( I+18)=»0'R; 
 
 END; 
 
 on i=] to 9: 
 
 IF IBF3(I) THEN DBP ( 1 +27 J ■ • « R • 
 
 ENO; 
 
 /* MAKF OR OUTPUTS EQUAL TO OBP OUTPUTS.*/ 
 
 OR t OBR=OBP; 
 FMO PFR_IN; 
 
 HA/70 « *. 
 
 Section 2.1.3 - 5/9 
 
PER OUT 
 
 PROCUDDE, 
 BIRG, 
 DBPRG, 
 LDRG, 
 WRBRE, 
 XORE, 
 ADDN, 
 DBDG, 
 LRDG, 
 
 ARF33, 
 A ORG, 
 B I R G , 
 DBPRG* 
 L DR G , 
 WRBRE, 
 XORE, 
 (ADDN, 
 DBDGr 
 LRDG, 
 
 OCL( AODE, 
 
 ADRG, 
 
 BLRG* 
 
 DBSTG, 
 
 LSE, . 
 
 WRPRLE, 
 
 XRVE, 
 
 ARG, 
 DLRN, 
 
 LRG, 
 
 ARE34, 
 
 ANDE, 
 
 BLRGt 
 
 DBSTG, 
 
 LSE, 
 
 WRPRLE, 
 
 XRVE, 
 
 ARG, 
 
 DLRN, 
 
 LRG, 
 
 ASRWE, 
 BRGSt 
 DLRG, 
 RSEt 
 WRPRVE, 
 ANDE, 
 ARGG, 
 DRL, 
 LRL, 
 ARF35, 
 ASRWE, 
 
 BRGS, 
 
 DLRG, 
 
 RSE, 
 
 WRPRVE, 
 
 DBDSG, 
 
 ARGG, 
 
 DRL, 
 
 LRL) (0:3) 
 BIT(l) 
 
 BARG, 
 
 BSR1G, 
 
 EOVE, 
 
 RWBGE, 
 
 WSBLE, 
 
 ARL, 
 IRG, 
 DBOSG, 
 
 ARARFG) 
 BARG, 
 BSR1G, 
 EOVE, 
 RWBGE, 
 WSBLE, 
 CORE) 
 ARL, 
 IRG, 
 BIT( 1 ) 
 
 BORG, 
 
 BSR2G, 
 
 FLPRN, 
 
 SBRS, 
 
 WSBVE, 
 
 BIRN, 
 
 IRL, 
 
 CDREf 
 
 BORG, 
 BSR2G, 
 FLPRM» 
 SBRS, 
 WSBVE, 
 BIT(l) , 
 
 BIRN, 
 IRL, 
 
 SCR (5), (ASRWE1,ASRWE2,RBRS)(7), 
 PRS(i:14), (PSMWS1,PSNWS2) (0:15 ), 
 
 rr(0:7,36) , 
 PRSNR (0: 15, IB ) , 
 
 fxtermal; 
 
 OCI (ARB,LRB,DRB) (36) BIT(l) EXTERNAL? 
 OCL 00(36) BIT(l) extfrnal; 
 IF CORE THEN CD=DB? 
 
 BRS(0:7) , 
 0SS(0:31 ) , 
 SMR(0:1A,A), PR(0:14,36) 
 0S(0:31,9), ASRG(7,18)) 
 
 BIT( 1) 
 
 /* TRAMSFFR T TO LRN 
 X R\/P = XORE I EOVE; 
 IF XRVE THEN 00; 
 LRM=^T ; 
 
 OH 1=9 TO 36 BY 9; 
 IF 0B( I )=0R( I ) 
 
 end; 
 
 OR AW IMG 07-1 */ 
 
 THEN LRNU )='1'B; 
 
 E N 
 
 TO PROPER REGISTFRS.*/ 
 
 SEND OUTPUT 
 
 DRL=' 1 'B; 
 
 DBDG, ARGG, LRDG='0'B; 
 
 IF BORG I A ORG I L ORG THEN ORL='0'B; 
 
 IF BORG THEN DO; 
 
 DBDG=' l'B; 
 
 or=obp; 
 eno; 
 if a org then 00; 
 
 ARGG=' l'B; 
 
 or=ar; 
 eno; 
 
 IF LORG THEN 00; 
 
 LROG=» 1 «b; 
 
 ll/U/70 
 
 Section 2.1.3 - 6/9 
 
DR=LR; 
 END; 
 IF BLRG THEN LRN < * ) =DB ( * ) | LR N ( * ) ; 
 IF DLRG THEN LRN ( * ) =DR ( * ) I LRN ( * ) ; 
 
 /* CALCULATE LR GATE AND LATCH SIGNALS DRAWING 04-4 */ 
 DO 1=0 TO 3; 
 LRG( I )=RSE|LSE|-*DLRN( I ) £OLRG | BLRG | ANDE I XR VE ; 
 
 END; 
 LRL=-^LRG; 
 
 nn i=o to 3; 
 
 IF LRG(I) THEN DO J=I*9+1 TO 1*9+9; 
 LR( J )=LRN( J) ; 
 
 END; 
 END; 
 
 IF BIRG THEM DO 1=0 TO 3; 
 
 IF -.BIRN( I ) THEN DO; 
 
 IRL( I ) = '0'B; 
 IRG( I ) = • 1 • B; 
 DO J=l*9+1 TO 1*9+9; 
 I R ( J ) = DB P ( J ) ; 
 END; 
 END; 
 END; 
 IF BARG THEM ARN=ARN|DB; 
 DO 1=0 TO 3; 
 
 ARG( I )=BARG I ADDE^ADDN( I ) ; 
 END; 
 
 ARG(0)=ARG(0) IRWBGE; 
 ARL=^ARG; 
 DO 1=0 TO 3; 
 
 IF ARG(I) THEM 0(1 J=I*9+1 TO 1*9 + 9; 
 
 AR (J )=ARM( J ) ; 
 END; 
 END; 
 IF ARARFG THEM Of); 
 
 ARF33=AR(33) ; 
 ARF34=AR ( 34 ) ; 
 ARF35 = AR( 35) ; 
 END; 
 /* CHECK FOR INITIALIZATION OF STACK */ 
 /* DBSTG WILL BE OM IE THE OSTR AND SCR ARE TO BE RFLOADED 
 WITH A MEW OPERAND STACK POINTER ADDRESS */ 
 
 IF DBSTG THEN DO; 
 DO 1=1 TO 2; 
 
 OSTR( I )=DB( 1+30) ; 
 
 END; 
 
 DO 1=1 TO 5; 
 
 SCR( I )=DB( 1+30) ; 
 FMD; 
 FMD; 
 
 11A/70 Section 2.1.3 - 7/9 
 
/* LOAD OS FROM OB */ 
 IF DBOSG THFN DO 1=0 TO 31 1 
 
 if nssu ) then nn; 
 l=mod( 1,4); 
 DO J = l TO 9; 
 
 ns( i tJ)«DBU*9+j); 
 
 end; 
 fnd; 
 fno; 
 
 WRITE ON SELECT POINTER OR SBR IE DESIRED */ 
 IF DBPRG THEN DO; 
 IF WRPRLE THEN DO 1=0 TO 14; 
 
 IF PRS( I ) THEN DO; 
 IF FLPRN THEN DO; 
 DO J=l TO 8; 
 
 PR( I ,J)=DBP( J) ; 
 END; 
 no j =10 to 17; 
 
 PR( I t J)=OBP( J) ; 
 END; 
 END; 
 
 ELSE DO J=l TO 18; 
 
 PR( I, J)=DBP( J) ; 
 
 end; 
 end; 
 end; 
 
 IF WRPRVE THEM DO 1=0 TO 14; 
 IF PRSU ) THEM DO: 
 IF FLPRN THFN DO; 
 
 00 J=19 TO 26; 
 
 Pkd,j )=dbp(J) ; 
 fno; 
 
 no J=28 TO 35; 
 
 PR( I ,J)=DBP( J) ; 
 
 end: 
 
 END; 
 
 FLSE DO J=19 TO 36; 
 PR( I ,J)=DBP( J) ; 
 
 end; 
 end; 
 ENn; 
 
 IF WSBLE&SBRS THEN 
 
 do 1=1 to ib; 
 
 SBR( I )=DBP( I ) ; 
 
 end; 
 
 IF WSBVF f> SBRS THEM 
 no 1=19 TO 36; 
 
 SBR( I )=DBP( I ) ; 
 END? 
 
 end; 
 
 /* IMTERROPT RECOVERY FOR SHADOW NAME REGISTER */ 
 IF BSR1G THFN DO 1=0 TO 2; 
 
 DO J=l TO 4; 
 
 SNR(2*I+8 r J)=DB(I*9+J) ; 
 
 H/W70 Section 2.1.3 - 8/9 
 
SNR(2*I+9, J )=DR( I*9+J+4) ; 
 END; 
 DO J=l TO 4; 
 
 SNR( 14,J)=DB(27+J ) ; 
 
 end; 
 end; 
 IF BSR2G THEN DO 1=0 TO 3; 
 
 DO J=l TO 4; 
 • SNR(2*ItJ)=DB( I*9+J ) ; 
 SNR( 2*1+1 »J)=DB( I*9+J+4) ; 
 END; 
 END; 
 
 /* CHFCK FDR WRITING INTO THE POINTER REGISTER SEGMENT NAME 
 REGISTER PRSNR */ 
 /* DEFINE PRSNR(0:15,18) AS THE INTERNAL REGISTERS ON 
 DRAWINGS 22-4 TO 22-19 IN THE LOGIC BOOK */ 
 DO 1=0 TO 15; 
 
 IF PSNWSl(I) THEN DO J=l TO 8; 
 
 PRSNR( I t J)=DBB( J) ; 
 END; 
 END; 
 DO 1=0 TO 15; 
 
 IF PSNWS2(I) THEN DO J=10 TO 17; 
 
 PRSNR( I, J)=DBB( J) ; 
 END; 
 END; 
 
 /■* ASSOCIATIVE REGISTER WRITE SIGNAL DRIVERS */ 
 
 IF ASRWE THEN DO 1=1 TO 7; 
 IF RBRS( I ) THEN DO; 
 
 ASRWEK I), ASRWE2< I ) = • l'B; 
 
 DO J = l TO 17 WHILE ( J-^ = 9) ; 
 ASRG( I» J)=DBB( J ) ; 
 
 END; 
 END; 
 END; 
 FLSF ASRWE1»ASRWE2=» O'B; 
 
 /* WRITF INTO BASE REGISTER */ 
 
 IF BRGSfcWRBRE THEN DO 1=0 TO 7; 
 
 IF BRS(I) THEN BR ( I ,* ) =DBP ( * ) ; 
 END; 
 LRB=LR; 
 ARB=AR; 
 DRB=DR; 
 END PER_OUT; 
 
 ll/U/70 Section 2.1.3 - 9/9 
 
2.1. h Permuter - Logic Description 
 2.1.4.1 The Basic Permuter Card 
 
 The heart of the Permuter logic is the -237 card shown in 
 Figure 2.1.4.1. This card consists of four latch flip-flops plus two 
 NOR's, each driven by several AND circuits. 
 
 The flip-flops are designated LR, AR, IR, and DR. The first 
 two are independent of any direct action taken by the rest of the card 
 circuitry (i.e. there are no direct connections to the LR and AR flip- 
 flops from the other circuits). 
 
 In the LR flip-flop note that the complement of the input (LRNi) is 
 stored when the gate signal, LRi/G, is logically "l" (+6v) and the latch 
 signal, LRLi, is logically "0" (Ov). After the data has been stored in 
 the flip-flop, the latch signal must be "l" and the gate must be "0". In 
 order to maintain the new state reliabily the latch must become "l" before 
 the gate becomes "0". Otherwise the input signal may be cut off before 
 the new state is "locked in". 
 
 The AR flip-flop works in exactly the same manner as the LR 
 flip-flop. The IR flip-flop is also similar except that the data input 
 is from the second of the 2 NOR's on the -237 card. Since this input 
 (DBPi) is not in complemented form the output definitions are reversed. 
 In effect, by connecting the input of the IR flip-flop internally to the 
 card we are restricting its input so that it can only be loaded directly 
 from the Distribution Bus (DBP). 
 
 The DR flip-flop is like the IR flip-flop, in that its output 
 definitions are reversed. However, in addition it has three inputs 
 instead of the usual one. One of the inputs is from the DBP as in the IR. 
 The other two are from the LR and AR. Each input has its own separate 
 
 4/7/69 
 
 Section 2.1.4.1 - 1/3 
 
gate. Note that in order to store data from one of the three inputs the 
 latching signal (DRLi) must be logically "0" and one of the three gating 
 signals must be "l". If more than one gate is on, the result in the DR 
 will be the OR function of the data on the lines with the gate signals 
 on. Once again, when the data is stored the latch signal should be 
 turned on before the gate signal is turned off. 
 
 The first NOR on the -237 card is what has been called the Permuter 
 input driver (see Section 2.1.1,1 and Figure 2.1.1.5/1). All of the 
 possible inputs to the permuter are AND'ed with their respective gating 
 signals and then NOR'ed together to produce the FBIi signal. This signal 
 is, in effect, the complement of the desired input to the Permuter. As 
 mentioned in Section 2.1,1.5, various signals from other cards may be 
 dot- OR'ed with this line to cause masking on certain parts of the input. 
 The final NOR circuit on the -237 card controls the output from 
 the permuter. The first four inputs to this NOR are gated by the Permuta- 
 tion Control signals, PLO/E, PLl/E, PL2/E and PL3/E. At most only one of 
 these will be on at any given time. The data which is gated by these 
 signals comes from an FBI line on one of four of the Permuter cards. PLO/E 
 gates in the FBI signal from the same card. PLl/E gates in the signal from 
 9 bit positions to the right of the present positions (i.e. i + 9), PL2/E 
 gates the FBI from 18 positions to the right, etc 
 
 The last of the inputs to the final NOR is the inhibit signal 
 which causes the DBP to become "0" if it is turned on. It should be noted 
 again that DBP and DB are logically equivalent (see Section 2.1.1.U). 
 
 Section 2.1.U.1 - 2/3 
 U/7/69 
 
3 d 
 
 In a 
 
 TJ 
 
 -P 
 3 
 
 <L> 
 
 Ah 
 
 CVJ 
 0) 
 
 
 
 tsD 
 
 f> w 
 
 5 fe « JOT «h to 
 
 ft* 
 
 (9 
 
 * (E 
 
 6/25/69 
 
 <9 J 
 
 3 i 
 
 y * w ; 
 
 £ ot 5 a. « £ - e „ > - «m 
 
 S a Be. Q.o oat 
 
 * Is) + yj 
 
 - s 
 
 Section 2.1. U.l - 3/3 
 
2.1.4.2 Inhibit Generator 
 
 The Inhibit Generator for the Permuter is contained in Drawing 
 OU-5 in the TP Logic Book. It is used to determine the inhibit signals 
 sent to pin V on the -237 cards. It should be noted that in bytes 0, 1 
 and 2 of the Permuter output, the whole byte is inhibited by the same 
 signal, i.e. IBO/E, IB1/E, or IB2/E, whereas in byte 3 of the Permuter 
 output each of the nine bits can be inhibited individually (see Section 
 2.1.1.5). 
 
 As shown in Figure 2.1.4.2 the inhibit signals can be used for 
 right and left justification of data and for shifting data on a byte basis. 
 A series of five NAND's decode the right and left justification control 
 signals and the cell size signals to determine which inhibit signals should 
 be turned on. The outputs of these NAND's become "0" if the inhibit signal 
 to which they eventually lead must be turned on. In addition to these 
 decoders there are six signals which come from the Boolean/Shift circuits : 
 IBO, IB1, IB2, IB3, IBPL21 and IBPL13. These signals are produced by the 
 Boolean/Shift logic and therefore their generation will be explained in 
 detail in Section 2.8. 
 
 The first h of these 6 signals are obvious in their meaning and 
 are fed directly to the inhibit signal drivers. The last two actually serve 
 two purposes. IBPL21 indicates that byte two should be inhibited and also 
 that there should be a left permutation of 1 byte. The permutation will 
 be discussed later. For now it should be noted that this signal is treated 
 the same as IB2. The IBPL13 is the same type of signal and indicates that 
 byte number 1 is to be inhibited and that' a left permutation of 3 bytes is 
 to take place. This signal is treated similarly to IB1. 
 
 11/25/69 , Section 2.1.4.2 _ 1/3 
 
IBO/E 
 
 IB1/E 
 
 IB2/E 
 
 
 -INHIBIT ALL BITS 
 IN 3RD BYTE 
 POSITION 
 
 FIGURE 2.I.4.2 INHIBIT GENERATION LOGIC 
 
 5/16/69 
 
 Section 2.1. U. 2 - 2/3 
 
There are 3 NMD circuits which act as drivers for IBO/E 
 IB1/E and IB2/E. If one of these is to be turned on, one of the 
 inputs to its respective driver will turn to "0". m the case of byte 
 number 3, however, there are actually nine separate drivers, one for 
 each bit in the byte. If the whole byte is to be inhibited one input 
 in each bit driver is set to "0". otherwise the input rests at "1" and 
 each driver output w thus be controlled individually by the other 
 driver inputs. These individual inhibit signals ffi ay be used as explained 
 in Section 2.1.1. 5 
 
 V25/69 
 
 Section 2.1. k. 2 - 3/3 
 
2.1.U.3 Permutation Control Logic 
 
 The permutation control signals, PLO/E, PLl/E, PL2/E, 
 and PL3/E, are obtained either directly from a set of control signals 
 or indirectly by decoding the contents of the 2 bit source and 
 destination busses. The set of control signals originates from the 
 shift control logic in drawing 17-1 of the TP Logic Book or from the 
 main control logic drivers. The permutation control logic itself is 
 on drawing OU-7. 
 
 If the set of control signals is used to generate the 
 permutation control signals, the decoding network must be disabled. 
 This job is performed by the LRS/E 1 signal which is inverted and 
 used to drive the enabling input of the decoding logic. 
 
 It should be noted that when PLC1, PLC2, or PLC3 is used 
 to control the permutation, the Main Control logic is responsible 
 for turning LRS/E on. This is done at the final driver stage in 
 the control logic just before the signals are sent to the Permuter 
 itself. 
 
 It is also important to notice that if LRS/E is turned on and 
 none of the permutation control signals are activated, none of the 
 input data will get through the Permuter. Instead, the output will 
 be all l's since all of the permutation signals (even PLO/E) will be 
 off. It is exactly this situation that is taken advantage of in the 
 generation of negative constants (see section 2.1.15). The above 
 mentioned logic in the Main Control section is also responsible in 
 this instance to make sure that LRS/E is turned on if Ml/E, M2/E, 
 M1+/E, M8/E, M16/E, or M32/E is turned on. 
 
 The name of this signal derives from the fact that when originally 
 conceived, it was used to allow the Left /Right Shift logic to control 
 the permutation. 
 
 8 /22/69 Section 2. l.U. 3 - lA 
 
Whenever the source and destination busses are used to 
 determine the permutation, the set of control signals must he off 
 and LRS/E must he off. This latter condition enables the 236-15, h 
 bit decoding diode matrix board (see figure 2.1.U.3/D to drive 16, 
 228-05 circuits. These circuits in turn are dot-or'ed and fed to the 
 h NAM) circuits driving the PLi/E signals according to the equations 
 given in section 2.1.1.3. 
 
 The inputs to the decoding circuit consist of the true and 
 complement signals from two, 2-bit busses. These two busses are 
 loaded from the source and destination busses by the Reverse Source 
 and Destination enable signal, -RStTF. When E3B71T = 1. the source bus 
 is gated to the first 2 bit input bus to the decoder (ItiAl and INA2 
 in figure 2.1.U.3/D and the destination bus is gated to the second 
 input bus (INB1 and INB2 in figure 2.1.H.3/1). When W= 0, the 
 gating is reversed and the source bus goes to XHB and the destination 
 bus goes to INA. 
 
 It should be noted that KSHTF is normally automatically 
 activated by special logic in the Main control logic final driver 
 stage where it is turned on by any signal which indicates that there 
 will be a write in one of the storage areas. 
 
 The source and destination busses themselves are generated 
 hy dot-or'ing various types of information onto them depending on the 
 type of registers involved in the transfer and the type of data 
 justification desired. Note that in drawing 0U-7, the source and 
 destination busses are in complemented form as they go into the 
 RSD/E and RSD/E gates . 
 
 The key point to remember when trying to understand the 
 operation of the logic attached to these busses is that the normal 
 flow of data is considered to be from storage areas (ie.memory or the 
 storage blocks) to the "working" registers (ie.AR, DR, IR, LR). Thus 
 
 Section 2.1.U.3 - 2/U 
 8/22/69 
 
when expressing the data justification used by a given storage block, 
 the source bus is always used, even if the data is being loaded into 
 the storage block i nstead of being read out of it . In the case of 
 loading a storage block the RSD/E signal will be set to by the 
 control logic and the source bus will then act as the destination 
 input to the decoding logic. 
 
 With this in mind we can discuss the various inputs to the 
 source and destination busses. 
 
 The DBRJ signal is used when the data is to be right justified 
 in the working registers. In this case, if the cell is a halfword, the 
 "destination" cell will be on the 10 byte boundary and therefore 
 Dl must be forced to '0». If the cell size is a byte the destination 
 address is 01 and D2 must be set to »0'. Note that for word and 
 doubleword cell sizes no action need be taken since the data will begin 
 at the 00 byte address. In doubleword cells this is due to the fact 
 that the doubleword cell is treated as two word size cells in the 
 Permuter. 
 
 When OSS/S is turned on, data is either coming from the 
 OS or going to the OS via the Permuter. The address within the OS, 
 of the cell being accessed is contained in the 5 bit Operand Stack 
 Temporary Register, T2R. In particular, the last two bits of the 
 register, T2RU and T2R5 , indicate the byte boundary address of the 
 cell. Thus, considering the "normal" flow of data through the 
 Permuter, the two source lines must be set equal to the last two 
 T2R bits, ie. SI = T2RT and S2 = T2R?. 
 
 When BRG/S is on, the base. register storage block is being 
 accessed. As is explained in section 2.5.1.1, the storage for the 
 base registers is rather mixed up since each register is only 3 bytes 
 long while the storage blocks are based on 8 byte double words. This 
 causes the beginning byte address to vary according to the base 
 register number. Referring to figure 2.5.1.1, it can be seen that 
 
 8/22/69 
 
 Section 2.1.4.3 - 3/k 
 
the equations for the two source hits can he written as: 
 
 51 = BR1/S v BR2/S v BR5/S v BR6/S 
 
 52 = BR1/S v BR3/S v BR5/S v BRT/S 
 
 Two NATO's utilizing inverted input sjxe used to produce these 
 signals which are then gated to the SI and S2 lines by the BRG/S 
 signal. 
 
 The CRRL/G signal is used when accesses are being made to 
 core. In this case the last two hits of the core address determine 
 the source hit settings. These two hits are stored in ARF3U and 
 ARF35 which are part of a 3 hit register specifically used for storing 
 the low order 3 hits of the core address. 
 
 The IBR/S signal indicates that the IBR part of the BR-IBR 
 storage block is to be accessed. The initial address of the word cell 
 to he accessed is determined by the ICT. Thus ICT2 and ICT3 are 
 gated to the SI and S2 lines respectively. In addition if both 
 IBR/S and OPJ/E are on the 52 line will be activated. This option 
 is used when it is desired to justify the data from the IBR on the 
 01 byte position of the destination. 
 
 8/22/69 Section 2 - 1 - U - 3 " ^ 
 
2 ' 2 Nine Bit/Byte Buffer Storage Blocks 
 
 Nine bit/byte storage blocks are used by the Taxicrinic 
 Processor to buffer data for which fast access is required. The 
 basic storage element is the Smith flip-flop 1 , eight of which are 
 contained on one -20U card. By driving nine of these -20U cards 
 with two -205 cards, a storage block containing eight bytes of 
 nine bits each (8 data bits and 1 flag bit), complete with gates 
 and drivers, is formed. These blocks are then used in groups to 
 build up the various data registers in the TP. 
 
 Storage blocks are used to form 25 registers in the TP 
 in addition to the fast storage in the Operand Stack. Four blocks 
 are required to form the 32 bytes of the Operand Stack maintained 
 in the TP. Eight blocks form the 15 pointer registers (h bytes 
 each) and the Spare Buffer Register (k bytes). And finally k 
 blocks are used to form the 8 Base Registers (3 bytes each) and 
 the Instruction Buffer Register (8 bytes). 
 
 Designed by Professor K. C. Smith 
 
 h/k/69 
 
 Section 2.2 - l/l 
 
2.2.1 Buffer Storage - Functional Description 
 
 The organization of the Buffer Storage Blocks is shown 
 in Drawing 01-0 in the TP Logic Book. Each block is made up of 
 two -205 cards which provide the gating and driving logic, and 
 nine -20h cards which provide the actual storage. Each -20*+ card 
 supplies 1 bit position for each of 8 bytes. 
 
 This section defines the data and control signal inputs to 
 a storage block. Operation of the storage block is then described. 
 
 The two -205 cards together supply 8 Byte Select Drivers 
 (BSD), 2 Input Gate Drivers (IGD), 2 Output Gate Drivers (OGD) and 
 6 spare NMD circuits. All inputs to all drivers rest in the 
 logical "1" state. 
 
 The BSD's set the proper voltage level on the emitters of 
 the flip-flops in the -204 cards. Each BSD drives one flip-flop on 
 each -20U card, these flip-flops then represent the byte designated 
 by their corresponding BSD. As shown in Figure 2.2.1/1 there are 3 
 output levels, which determine the "sensitivity" of the 9 driven 
 flip-flops. A "high" output level (+3.5 volts) enables the flip- 
 flop to receive data or to be written into; the "intermediate" 
 level (+1 volt) is the "holding" level at which the flip-flop can 
 neither be written into or read out of. The "low" output level of 
 the BSD (-2.5 volts) causes the flip-flops to be read out via the 
 Output Gates. 
 
 The signal levels on the two input control lines to the 
 BSD uniquely determine the state of the output line. One input, 
 
 k/k/69 
 
 Section 2.2.1 - 1/6 
 
BYTE SELECT > 
 
 READ/WRITE 
 
 + 6.0 
 
 + 6.0 
 
 BYTE SELECT 
 DRIVER 
 
 (BSD) 
 
 ♦ TO FLIP-FLOPS 
 
 + 3.5/ + I.0/-2.5 
 
 FIGURE 2.2.1/1 BYTE SELECT DRIVER 
 
 
 5/16/69 
 
 Section 2.2.1 - 2/6 
 
the Byte Select line, overrides the effects of the second, the 
 Read/Write line. When the Byte Select line is "l", the BSD 
 output is at the intermediate level (+1 volt). If the Byte Select 
 line is "0" the output will be determined by the Read/Write input 
 signal. When this is "l" the output is at -2.5 volts, the "read 
 out" level. A "0" Read/Write signal sets the BSD output to +3.5 
 volts, or the "write in" state, again only when the Byte Select 
 signal is "0". 
 
 As shown in the TP Logic Book Drawing 01-0 the Byte Select 
 lines come from input pins D,H,L, and P on the two -205 cards. The 
 Read/Write input lines come from pins B,E,J, and M. 
 
 The Input Gate Drivers, as shown in Figure 2.2.1/2, gate 
 in the data line to the 2 input gates of the flip-flops. The inputs 
 to the IGD's are normally resting at logical "l" (+6 volts) causing 
 the outputs to normally rest at "0" (0 volts). The drivers are 
 operated together in the normal method of operation: for a "gate 
 both in" effect, both inputs to the flip-flop are activated with 
 complementary signals. If only the "gate true in" signal on the 
 IGD is activated, only the "true" input to the flip-flops will be 
 activated and the result in the flip-flop will be an OR of the old 
 and new data. It must be remembered that in order for a "write in" 
 to occur, the BSD must also be in the "write in" state. 
 
 On the -205 cards, the IGD's are simply 2 input NAND's 
 which drive NAND circuits on the -20U cards. Each IGD drives 9 
 NAND circuits, (one byte) one from each -20^ card in the block. 
 These NANDS then drive the inputs to the flip-flops. As shown in 
 
 k/k / 6 9 Section 2.2.1 - 3/6 
 
GATE 
 TRUE INTe^" 
 
 u 
 
 17 
 
 GATE 
 BOTH IN+g/o 
 
 INPUT GATE 
 
 DRIVER 
 # 1 (IGD) 
 
 Li 
 
 INPUT GATE 
 DRIVER 
 -#2 (IGD) 
 
 IN DATA 
 
 INHIBIT +6/0 
 
 205 CARDS 
 
 TO FLIP-FLOP 
 INPUTS 
 
 -H6/0 
 
 TO 8 
 OTHER 
 204 CAF 
 
 204 CARD 
 
 FIGURE 2.2.I/2 INPUT GATE DRIVER 
 
 5/16/69 
 
 Section 2.2.1 - U/6 
 
the TP Logic Book Drawing 01-1, the "gate true in" signal to the 
 IGD comes from pin U of the first -205 card. The "gate both in" 
 signal comes from pin 17 of the first -205 card and is tied, intern- 
 ally to the card, to both IGD's. 
 
 The In Data Inhibit signal shown in Figure 2.2.1/2 is used 
 in some of the storage blocks (i.e. the Operand Stack) to inhibit the 
 loading of certain bit positions (notably the flags). If the inhibit 
 signal is set to the logical "0" state, the data will not be trans- 
 mitted to the flip-flops even though the in gates and the select 
 signals are on. 
 
 The Output Gate Drivers on the -205 card drive the output 
 gates on the -20^ cards. They are shown in Figure 2.2.1/3. The 
 voltage level outputs from the driver are +0.7 and -2.9 volts. Inputs 
 to the driver rest at logical "l", the outputs at logical "0". One 
 0GD is used to drive the true gate from the flip-flop; the other, the 
 false gate. The drivers can be operated either simultaneously for a 
 double-gate effect, or singly, for a gate true (false) out effect. 
 If they are only operated singly, the outputs of the output gates 
 (not the gate drivers) may be tied together (dot OR) to yield a true 
 or complement output from the registers onto a single output line. 
 (This has been done in the Operand Stack buffer storage). 
 
 The gating signals into the 0GD must be operated when the 
 BSD is set for the "read out" state. Otherwise the outputs from 
 the output gates will both be "0" (0 volts). 
 
 The OGD's on the -205 cards consist of a 2 input NAKD 
 followed by a driver circuit. There is one OGD on each -205 card. 
 For simultaneous operation, two of the input pins, one from each 
 OGD, are tied together. Pin 20 on the second -205 card connects to 
 the "gate true out". 
 
 k/k / 69 Section 2.2.1 - 5/6 
 
DATA OUT 
 
 GATE 20 
 
 TRUE OUT +6/0 I 
 
 GATE 
 
 BOTH OUT +6/0 
 
 GATE 
 
 OUTPUT GATE 
 DRIVER 
 * 2 (OGD) 
 
 + 0.7/-2.9 
 
 20 
 
 FALSE OUT +6/0 
 
 OUTPUT GATE 
 DRIVER 
 # I (OGD) 
 
 +0.7-2.9 
 
 205 CARDS 
 
 TRUE OUT 
 
 + 6/0 
 
 CD 
 
 FALSE 
 
 FALSE OUT 
 
 +6/0 
 
 OUTPU 
 GATES 
 
 TO 8 
 OTHEf 
 
 204 1 
 
 TRUE 
 
 FROM FLIP-FLOPS 
 
 204 CARDS 
 
 FIGURE 2.2.1/3 OUTPUT GATE DRIVERS 
 
 5/16/69 
 
 Section 2.2.1 - 6/6 
 
2.2.2 Signal Name List for Buffer Storage - Control Signals 
 
 Buffer Storage 
 Name 
 
 Base 
 
 Byte Select 
 
 Read/Write 
 
 Gate Both In 
 
 Data In 
 
 Gate True Out 
 
 Gate False Out 
 
 Data Out 
 
 In Data Inhibit 
 
 Actual Names Used* 
 
 , Spare 
 Inst. Pointer i Buffer 
 Buf. Reg. ] Reg. ) Register 
 
 BRI/S i IBRI/S 
 
 PRi/S 
 
 SBR/S 
 
 WRBR/E ' WRIB/E 
 
 'DBBRS/G- 
 
 BRSBP/G 
 
 BROSi 
 
 *«- 
 
 DBPi 
 
 ■*♦ 
 
 WPRL/E I WSBL/E 
 WPRV/E WSBV/E 
 
 -DBPRS/G- 
 l 
 
 PRTG/S I PR8G/S 
 PR8G/S ! 
 PRBi 
 
 Operand 
 Stack 
 
 OSi/S 
 DBOS/G 
 
 DBOS/G 
 
 OSPF/G ** 
 
 OSPT/G ** 
 BROSi 
 
 FLOS/N 
 
 *Gate True In and Gate Both Out are provided in the storage blocks 
 but not used. 
 
 **Since the outputs from the Operand Stack Storage Blocks are inverted 
 the Output Gates are the reverse of what would be expected. 
 
 11/5/70 
 
 Section 2.2.2 - l/l 
 
2.2.U Buffer Storage - Logical Description 
 
 The purpose of this section is to describe the operation of 
 the buffer storage from a detailed logical and electrical point of 
 view. The description repeats some of the information in Section 2.2.1 
 but extends to a much more detailed level. 
 
 A buffer storage block generally consists of 9, 20k storage 
 boards and 2, 205 driver boards. The 20*+ board as shown in Figure 2.2.U/1 
 contains eight flip-flops and some associated circuitry. These eight 
 flip-flops are internally wired to form a "vertical" stack, and in normal 
 operation the nine 20U boards are wired side by side (horizontally) to 
 form an 8 x 9 or 72 bit array. The two 205 boards are needed to drive 
 the 72 bit array. 
 
 During a read or write operation the contents of one of the 
 eight flip-flops will account for one and only one bit of the output 
 register. The nine 20*+ boards together will account for nine bits, i.e. 
 a byte. During the operation of this storage block one byte will be 
 operated on at a time. A typical operation might be sensing the contents 
 of the third flip-flop in each of the nine boards. 
 
 In order to be able to work on nine flip-flops at a time, 
 some sort of gating signal must be applied. This is the function of the 
 205 driver boards. Each of these boards contains four circuits which 
 will gate information into and out of the flip-flops. Thus, for a 
 vertical stack of eight flip-flops two such boards are necessary. The 
 remaining circuits on these 205 boards are used for controlling the 
 input and output buffers of the entire array. 
 
 The key to the operation of this memory is in the type of 
 gating signal supplied by the 205 boards. This signal has three distinct 
 levels, and each of these levels puts the flip-flops into a different 
 mode of operation. The different voltages corresponding to these levels 
 are approximately +3-5, +1.0, and -3.0. 
 
 The description in this section is the work of H. Magusky. 
 
 2 
 The design of this board is an outgrowth of the flow gating memory described 
 
 by Guckel, Kunihiro , and Crow in DCL Report No. 106, March 196l. 
 11/5/70 Section 2. 2A - 1/9 
 
FF SELECT 
 
 FF SELECT 
 
 FF SELECT 
 
 FF SELECT 
 
 FF SELECT 
 
 FF 
 TLC 
 
 0/OUT 
 
 w (DJ 
 
 FF SELECT 
 
 FF SELECT 
 
 SBDI OUT 
 
 B E 
 
 SBD2 LOGIC OUT 
 
 10/8/69 
 
 Figure 2.2.U/1 Logic for 20H Board 
 
 Section 2.2.U/1 - 2/9 
 
c 
 
 F E 
 
 K (S 
 
 n E 
 
 x [y] 
 
 R 
 14 
 
 S |M) 
 
 15 
 16 
 
 T m 
 
 U 
 17 
 
 18 
 
 V (£] 
 
 w m 
 
 Figure 2.2.U/2 Logic for 205 Board 
 
 11/7/69 
 
 Section 2.2.U - 3/9 
 
NOTES 
 
 I, UNLESS OTHERWISE SPECIFIED, 
 
 RESISTANCE VALUES ARE IN 
 
 OHMS. 1/4 WATT, 2%, 
 I JNLESS OTHERWISE SPECIFIED, 
 
 DIODES ARE USD3. 
 3, UNLESS OTHERWISE SPECIFIED, 
 
 TRANSISTORS ARE USN3. 
 a, UNLESS OTHERWISE SPECIFIED, 
 
 CAPACITANCE VALUES ARE 
 
 IN MICROFARADS. 
 &TEST POINTS ARE INDICATED 
 
 BY ®, WITH TEST PINS 
 
 INDICATED BY Q 
 
 6 UNUSED PINS 
 
 TEST PLUG— B. H, J, K, 
 L, S, T. 
 
 7 POWER SUPPLY COMMON TO 
 4 CIRCUITS (SIGNAL GOES 
 TO NEGATIVE VOLTAGE 
 LEVEL) 
 
 8- COMMON TO 2 CIRCUITS. 
 
 9, OUTPUT FROM C, E «. N 
 IS SPECIAL 3 LEVEL SIGNAL 
 USED TO DRIVE 204 CARD. ' 
 
 10 OUTPUT FROM X, S. T. V, W 
 ARE USED TO DRIVE 204 CARD 
 
 E.E. 
 
 S, T, V, W 
 
 Bl.Sl.E.E 
 
 igure 2.2.U/3 Electrical Schematic for 205 Board 
 
 Fig 
 
 11/7/69 
 
 Section 2.2.U - U/9 
 
Once the 205 boards have generated the proper voltage levels 
 the 204 board can take then and convert them to read and write operations. 
 Referring to Figure 2.2.4/4 notice that the second circuit from the top 
 has connections to pins J through S, and 8 through 15. These eight 
 circuits are the flip-flops that store the information, and the lines 
 connecting to the above pins are known as the "FF Select" lines (see 
 Figure 2.2.4/1). These FF Select lines have the three levels mentioned 
 above . 
 
 Each of these lines connects to the common emitter connection 
 of the flip-flop. These flip-flops were designed so that they will keep 
 their state even if the common emitter voltage varies over a range of 
 + 4 volts from ground. Due to some external connections to the flip- 
 flop, however, the mode of operation of the flip-flop changes as the 
 voltage is varied over this range. Specifically, the flip-flops are at 
 rest when the voltage is +1 volt, they are ready to accept new information 
 when the voltage is +3-5, and their internal states are sensed at -3.0 
 volts. 
 
 The reason why they act in this manner is not too difficult 
 to understand. Take first the case of new information coming into the 
 flip-flop. When the write gating signal comes along the FF Select lines 
 are placed at +3-5 volts, and the flip-flops will be forced into a raw 
 state if any of the base connected diodes (D5 to D8) are grounded or 
 near ground. If D5 or D6 is grounded, the flip-flop will set to "0", and 
 if D7 or D8 is grounded, the flip-flop stores a "l." A "l" state is 
 defined when the signal at the output test point resistor (R22) is 
 positive. 
 
 Diodes D5 and D7 on all flip-flops are connected internally 
 to the IN 1 and IN lines respectively. These two lines are normally 
 the complements of each other, and can never be grounded at the same 
 time. The status of these two lines depends on the inputs to the Storage 
 Bus Drivers (SBD1 & SBD2), and since both SBD gates can be controlled 
 by the inputs to SBD1, complete control over setting a or 1 is possible 
 
 10/8/69 
 
 Section 2.2.4. - 5/9 
 
D® 
 
 lj© 
 
 
 
 
 
 -J 
 
 B 
 
 
 
 
 @ 
 
 -,-« 
 
 
 
 
 
 3 
 
 
 
 @ 
 
 10 
 
 a 
 
 CO 
 
 * 3 r-i 
 
 = - 
 
 
 
 @ 
 
 Q 
 
 
 
 
 
 0>" 
 
 
 
 
 
 <o 
 
 11/7/69 
 
 Figure 2.2.U/U Electrical Schematic for 20U Board 
 
 Section 2.2.U - 6/9 
 
by using only one input line (SBD1 IN 1, say). A closer look at the 
 output of one of the SBD units shows that these lines actually rest 
 slightly above ground, due to the action of the level shifter Dl8 & 
 D19 or D21 & D22. These diodes are necessary to decouple the IN 1, 
 IN lines from the SBD outputs while the flip-flops are in their rest 
 states. 
 
 The Set 1 and Set lines are similar in function to the IN 1 
 and IN except that they must be controlled by external logical circuitry, 
 As before, a "l" will be stored when there is a positive signal on Set 1 
 and a grounded signal on Set 0. When not in use the 12 volt bias 
 resistor assures that these lines are up and out of harm's way at all 
 times. If these lines are controlled by external circuitry, then this 
 circuitry must insure that these lines are positive except during a write 
 command. Otherwise loss of information might occur. These two lines can 
 also be used to override the normal write command and clear the memory of 
 all information. This is accomplished by pulling the Set 1 line down to 
 about -3 volts and leaving the Set positive. 
 
 As was mentioned before the SBD gates control the setting of 
 l's and 0's. It might appear, after a quick glance at the schematic 
 drawing, that these two units are independent of each other and can be 
 wired at will. This is not the case, for both are internally wired to 
 pin D, and consequently to each other. This connection is evident in 
 the logic drawing. This series connection is one reason for the use of 
 a codistor in SBD2. This codistor speeds up the response of T5 to a 
 change in state of T^. 
 
 Although not absolutely necessary, it is good practice to 
 supply the IN and INI lines with a gating signal. This can be easily 
 accomplished by wiring a pair of the SBD inputs together, say SBD1 IN 3 
 and SBD2 IN 3. When this combined line is grounded, the outputs from 
 both SBD's will be positive, and IN and INI will be up and out of the 
 way. Drivers for this operation are provided on the 205 board. 
 
 10/8/69 Section 2.2.U. - 1/9 
 
Nov let us consider the case in which information leaves 
 the flip-flops. The easiest way to understand the read operation is 
 to start at the output inverter and work towards the flip-flop. Notice 
 first that if any of the signals appearing on terminals IT, 18, 19, of 
 20 is below ground, then Tl is unconditionally off, and the output 
 signal will be positive. When Tl is unconditionally off signals appearing 
 at X and U have no effect whatever on the output of the transistor. 
 Thus, lines 17-20 serve as gating lines controlling the output buffer. 
 The 205 card supplies these negative going gating signals. 
 
 If none of the above lines are at or below ground, then the 
 state of Tl depends on the signals present at U or X. The normal resting 
 voltage for these lines is about +.8 volts, and this also is the maximum 
 voltage possible due to the forward bias across Dl. When these lines 
 are pulled down below ground Tl again turns off, and the output is positive 
 Finally we can see why pulling down on the FF Select lines causes these 
 flip-flops to be read. One of the two transistors in the flip-flop will 
 be saturated, causing one of the output diodes D2U or D2 5 to pull down 
 lines X or U. This completes the chain of events. 
 
 Simultaneous Read-Write is possible because the flip-flop in 
 the read mode will not interfere with the flip-flop in the write mode. 
 
 The initials TLC on the flip-flop (Figure 2.2.4/D indicate 
 that this input is for Three-Level-Cpnversion as opposed to a trigger 
 input for the flip-flop. 
 
 With proper timing relations it should be possible to complete 
 a read or write within 100 nsec. 
 
 10/8/69 Section 2.2.U. - 8/9 
 
Summary: Rack Plug Signal Descriptions 
 
 Pins Name Normal Use 
 
 B IN Check status of IN bus. 
 
 C SBD2 Out Checks collector of T5 
 
 D SBD1 Out Checks status of SBD1 transistor, input to SBD2 
 
 E IN 1 Check status of IN 1 bus 
 
 H SET Input connection for setting 1 or setting all l's* 
 
 J-S, 8-15 FF Select Three level input lines to FF. 
 
 Note: Normal -wiring of these boards will have 8 
 of A going to J of B, 8 of B going to J of C, and 
 so on for adjacent boards A, B, C. 
 
 U Out 1 Checks status of Out bus. 
 
 V 1/Out Output connection from buffer 
 
 W 0/Out Output connection from buffer 
 
 X Out Checks status of Out bus 
 
 2,3,U SBD1 IN's 1,2,3 Input connection for 1/0 set, gating 
 
 5,6 SBD2 IN's 2,3 Input connection for gating only 
 
 7 SET 1 Input connection for clearing or setting 0* 
 
 IT ,18 1/Gate Input gate connections for output buffer 
 
 19,20 0/Gate Input gate connections for output buffer 
 
 * 
 
 This apparent confusion in terminologv arises from the fact that these 
 these gates are positive logic AND's used as negative logic OR's. 
 
 10/8/69 Section 2.2.1+ . - 9/9 
 
2.3 Operand Stack 
 
 The Operand Stack (OS) is a specially designated file in 
 the main store defined by pointer register #13. It gains its dis- 
 tinction by virtue of having its topmost bytes (up to a maximum of 
 32) located in fast access storage registers internal to the Taxi- 
 crinic Processor. For this reason the Operand Stack can be used 
 as a scratch pad for evaluating arithmetic and boolean expressions 
 with a minimum access to core storage. Many TP instructions obtain 
 operands from or operate directly on the OS. Some instructions, 
 such as LD or P0P, merely transfer data cells into or out of the OS. 
 Others, like ADD, pop out two cells, operate upon these operands 
 and then return a single result. 
 
 Programming conventions established for the OS make it 
 appear that the stack is at all times entirely in core. It can be 
 visualized as a continuous string of bytes. The Operand Stack 
 Pointer (Pointer Register #13) can be considered to contain the 16 
 bit file address a of the first (leftmost) unfilled byte in the 
 stack, relative to its associated base. 
 
 at. 
 
 p 7 : 
 
 Id 
 
 Filled Bytes 
 
 Top of OS-' 
 
 increasing byte address 
 
 Unfilled Bytes 
 
 An operand can be pushed into the stack by assigning it to the 
 field starting at location a, and then incrementing the OS pointer by the 
 field (or cell) size. In like manner, an operand may be popped from 
 the stack by decrementing the OS pointer by the field length (i.e. 1, 
 2, k or 8 bytes). Operand boundaries are by no means sacred: for 
 
 3/11/69 
 
 Section 2.3 - lA 
 
example, fields pushed into the stack as hytes may be popped out 
 a word at a time . 
 
 To add or delete from the top of the stack we must: 
 
 1) specify the field length of the operand hy giving 
 
 a "cell size" parameter as part of the instruction. 
 The cell size parameter consists of two hits and 
 identifies the operand as a byte (00 ), halfword 
 (01), word (10) or double word (ll). 
 
 2) distinguish whether the operand is to be pushed into 
 the stack (at the address = the top of the stack) or 
 popped from the stack (at the address = the top of 
 the stack minus the cell size). 
 
 Although the top bytes of the Operand Stack are located in 
 fast registers in the TP, any operand in the stack may be accessed 
 by using PR #13 as a file address and suitably modifying it to get 
 the desired byte within the stack. As will be seen in Section H.2.1.2, 
 this request necessitates emptying the contents of the TP fast regis- 
 ters into core first. The complete stack will then indeed be in 
 core, as the programmer expects. Of course this process involves 
 time; however it is not anticipated that this method of accessing 
 the Operand Stack will be used often, so this slowdown should not 
 be significant. 
 
 Each byte of the Operand Stack has been assigned a unique 
 "wired in" address, through 31 (00000 through lllll). A five bit 
 register, the Stack Control Register (SCR), holds the address of 
 the top of the stack: the top is defined as the first empty byte. 
 This register is changed whenever a new operand is added to the OS. 
 Since it would take excessive time to always access PR #13 to find 
 
 . ir Section 2.3 - 2 A 
 
 3/11/69 
 
out the top of the stack, PR #13 is not kept current.' What is done 
 is the following: Whenever PR #13 is accessed, the SCR is masked 
 into its 5 lower order bit positions, thus giving the true top 
 position. Thus the only time the OS control must change PR #13 is 
 when there is overflow or underflow in the highest order bit of the 
 SCR. This situation is called "stack wraparound" since it occurs 
 when the SCR "moves" across the 31-0 boundary. 
 
 As described above, the topmost bytes of the OS are 
 located in up to 32 bytes of fast storage in the TP. These 32 bytes 
 of fast storage are equivalent to four double words. A unique address 
 for each byte position can be determined from five bits. The high- 
 order two bits define which of the four double words contains the 
 top of the OS. The four double words can hence be assigned the 
 "addresses" 00000, 01000, 10000, and 11000. 
 
 The Operand Stack Top Register (0STR), a 2-bit register, 
 contains the double word address (00, 01, 10, 11) of the boundary 
 double word, i.e. the double word which has been in the stack for 
 the longest time. Expressed in a different manner, the 0STR marks 
 the boundary between the part of the OS contained in the TP hardware 
 and the part of the OS contained in main memory. The use of the SCR 
 and 0STR registers is shown in Figure 2.3. 
 
 3/ll/6 9 Section 2.3 - 3/U 
 
OSTR 
 
 SCR, 
 
 n ■ i i i i i 
 
 1 
 
 _J 
 
 OSTR 
 
 10110 
 
 _J I L_l 
 
 SCR 
 
 In this example the shaded bytes contain useful data. The 
 second double word (Ol) has been in the stack the longest time. Additions 
 or deletions to the stack are made beginning at the location specified by 
 the SCR. 
 
 Figure 2.3 Organization of the Operand Stack 
 
 U/18/69 
 
 Section 2.3 - k/k 
 
 
2.3.1 Operand Stack - Functional Description 
 2.3.1.1 Operand Stack Control Registers 
 
 The hardware organization of the OS components is shown 
 in Figure 2.3.1.1. There are four registers associated with the 
 operand stack: the Operand Stack Top Register OSTR and the Stack 
 Control Register SCR mentioned above and the temporary registers 
 T1R and T2R. All registers except the OSTR are five bits long. 
 
 The OSTR (Operand stack Top Register) holds the double- 
 word address - one of four - of the "bottom" of the OS in the TP's 
 hardware storage. Referring to Figure 2.3 this boundary may alternately 
 be considered the upper bound of the stack in the hardware registers, 
 since the TP treats the hardware stack storage in a "circular" manner, 
 e.g., if the 31st byte is filled and more storage is needed, the Oth 
 byte is used. Beyond this bound, information will be overwritten 
 and destroyed unless cells are first taken from the "bottom" of the 
 hardware stack and stored in main memory. 
 
 The SCR (Stack Control Register) contains the address (one 
 of 32) of the first unfilled byte beyond the top of the OS. The 
 contents of the SCR are incremented and decremented by the appropriate 
 cell size whenever a cell is accessed or loaded into the OS. The SCR 
 itself is loaded anytime PR#13 is loaded*, and when the contents of 
 PR#13 are gated out, SCR's contents are masked into the five low 
 order bits of the PR in order to give the complete address of the 
 top of the OS. If and when SCR overflows (from PUSH's) or under- 
 flows (due to POP's), PR#13 is incremented(or decremented )by 32 to 
 absorb the over/underflow. 
 
 9A7/69 Section 2.3.1 - 1/2 
 
INPUTS FROM 
 5 BIT ADDER 
 CARRY LOGIC 
 
 DB 30.3i 0NLY 
 
 FROM 
 
 DISTRIBUTION 
 
 BUS 
 
 • DB 30 DB 34 
 
 1 
 
 0SF 
 
 (2) 
 
 (2) 
 
 0STR 
 
 ( |) 2 BITS IN LINE 
 
 ill 
 
 CELL 
 SIZE 
 
 3 
 
 m 
 
 SCR 
 
 (5) 
 
 0S 0V/UF IND. 
 GEN. 
 
 TO 
 PERMUTER 
 
 'a inputs 
 
 5 BIT 
 ADDER 
 
 I 
 N 
 
 'B' p 
 8 u 
 
 T 
 
 S 
 
 (I) 
 
 A50V 
 
 ADDER 
 OVERFLOW 
 
 I 
 
 z: 
 
 TIR 
 
 OS OVERFLOW/ 
 UNDERFLOW SIGNALS 
 
 1 
 
 T2R 
 
 (5) 
 
 OP STACK TOP BYTE DECODE 
 
 I 
 
 TTTTTT 
 
 • : : : 
 
 31 
 
 NEXT BYTE SELECT 
 
 mil ran i 
 
 TO 9 BIT/ BYTE STORAGE 
 SELECT INPUTS 
 
 CS 
 
 ADD/SUB 
 
 LLi 
 
 (5) 
 
 CONSTANT 
 GEN. 
 
 OPERAND STACK CONTROL LOGIC SYSTEM 
 FIGURE 2.3.1.1 
 
 5/2/69 
 
 Section 2.3.1 - 2/2 
 
2.3.1.2 The Constant Generator 
 
 One of the »B» inputs to the adder, as stated above, is the 
 5 bit constant generator output bus, Ki . The constant generator has as 
 inputs 1) the cell size (CS) signals, 2) the add/subtract signal, 3) a 
 single/double or multiply signal, and 1+) several control lines used for 
 generating specific constants. It has as an output, a 2's complement 
 number, which appears on the output bus, and which equals + one or two 
 times the number of bytes in the input cell size. The outputs are +1, 
 +2, +1+, +8 and +16, depending on the inputs. If, for example, the 
 add/subtract input = 1 (add), the multiplicity signal = 1 (multiply by 
 1), and CSH = 1, the output is +2. If the multiply line = (multiply 
 by 2), the output is +k. 
 
 The constant generator operates using an intermediate 5 bit 
 
 bus, CGBi, on which the magnitude of the desired number is generated. 
 The number is in its complemented form at this point. The CGBi bus is 
 then gated to the output bus either with or without first being comple- 
 mented depending on whether the positive or negative form of the con- 
 stant is desired. 
 
 Referring to the truth table in Figure 2.3.1.2, the following 
 equations can be written for the intermediate bus: 
 
 CGBI = X2 • 
 
 CSD 
 
 • 0SC16/E 
 
 
 CGB2 = XI • 
 
 CSD 
 
 • X2 • CSW 
 
 • 0SC8/E 
 
 CGB3 = XI . 
 
 CSW 
 
 • X2 • CSH 
 
 • OSC^/E 
 
 CGBi; = XI • 
 
 CSH 
 
 • X2 • CSB 
 
 • 0SC2/E 
 
 CGB5 = XI . CSB • 0SC1/E 
 
 6/18/69 
 
 Section 2.3-1.2 - 1/3 
 
where the OSCi/E signals are the control lines used for generating 
 specific constants which were mentioned earlier and XI and X2 are 
 the multiply hy 1 and multiply by 2 signals, respectively. 
 
 The final stage in the generator consists of gating this 
 
 signal to the output bus, Ki. If the number is to be negative, theCGBi 
 signals are gated directly. If the number is to be positive, the CGBi 
 signals are first inverted and then gated to the Ki bus. 
 The actual control signals act as follows: 
 
 X2 = multiply by 2 (i.e. X2 = l) 
 
 X2 = l multiply by 1 (i.e. XI = l) 
 
 sTE = negative number 
 
 sTe = 1 positive number 
 
 In order to generate constants nsing the special control sig- 
 nals, both XI and X2 must he set to zero (see previous equations). Thrs 
 is accomplished hy setting X2 to "0" and setting a special control sxgnal, 
 
 ■p rtQrWF is dot-or'ed to the inverse 
 0SCG/E, to "1". Since the inverse of 0SCG/E is dot 
 
 ■-n v>« "n" and onlv the control signals 
 of X2, both the XI and X2 gates will be , and only 
 
 OSCi/E will be able to determine the state of CGBi. 
 
 Section 2.3-1.2 - 2/3 
 6/18/69 
 

 CGB 1 
 
 CGB 2 
 
 CGB 
 
 CGB^ 
 
 CGB 
 
 CGBj^ 
 
 CGB 2 
 
 CGB 
 
 CGB^ 
 
 CGB 
 
 CSB 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 CSH 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 CSW 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 CSD 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 XI (multiply by l) X2 (multiply by 2) 
 
 
 CGB 
 
 CGB 2 
 
 CGB 
 
 CG B]+ 
 
 CG 
 
 0SC16/E 
 
 1 
 
 
 
 
 
 
 
 
 
 0SC8/E 
 
 
 
 1 
 
 
 
 
 
 
 
 OSC&/E 
 
 
 
 
 
 1 
 
 
 
 
 
 0SC2/E 
 
 
 
 
 
 
 
 1 
 
 
 
 OSC1/E 
 
 
 
 
 
 
 
 
 
 1 
 
 Note: Only one of CSB, CSH, CSW and CSD can be on at one time. 
 
 Figure 2.3.1.2 
 
 6/18/69 
 
 Section 2.3.1.2 - 3/3 
 
2.3.1-3 Byte Selection Logic 
 
 In order to know where a cell is to be stored or read from in 
 the 32 byte buffer storage of the operand stack, a method is needed to 
 select the bytes desired for any current action. This is the purpose of 
 the byte selection logic. The basic idea involved is that the bytes con- 
 cerned should first be chosen on the basis of the single byte address in 
 register T2R and then this byte and the necessary bytes after it can be 
 either read out of or written into the 0S. 
 
 The four different cell sizes cause a problem of picking out the 
 right number of bytes. However all data lines are built for four bytes 
 therefore it was decided that four bytes would be selected regardless of cell 
 size. For word or double-word cell size (a double word size needs two 
 "accesses" to the stack anyway because of the size of the data lines) this 
 procedure is optimal. The half-word and byte cell sizes also usually work 
 because only the top of the stack is ever accessed and if the cell desired 
 is only 1 or 2 bytes long, the other 3 or 2 bytes will contain garbage which 
 can be ignored. The only exception to this rule occurs when the 0STR 
 boundary occurs within 3 or 2 bytes of the last byte which needs to be 
 accessed. Referring to Figure 2. 3. 1.3, for example, if the rightmost half 
 word in the 00 double word were the cell being written on, and the selection 
 logic picked out four bytes, the first two bytes in the 01 double word 
 would be overwritten and destroyed. For this reason the byte selection 
 logic does not allow four bytes to be chosen in such a manner that the 
 0STR boundary will be "crossed". 
 
 With this in mind the byte decoding and selection logic is rela- 
 tively straightforward. The byte address in T2R is decoded to give one of 
 32 outputs. Each output represents a particular byte in the hardware 0S. 
 In the next-byte-selection logic the next three bytes in increasing order 
 are selected along with the original byte and selection signals are generated 
 
 3/12/69 Section 2.3.1.3 - 1/2 
 
00 
 
 01 
 
 ■I I I I *- 
 
 t t 
 
 SCR OSTR 
 
 ' ■ ' I — I — u 
 
 10 
 
 L II I III 
 
 11 
 
 I I I I) I ■ ' ' ' ' ' ' 
 
 Figure 2.3-1-3 
 
 to be dallied to the actual hardware 0S. These selection signals m ay 
 
 I the "11111" - "00000" boundary or cross any other double word 
 
 wrap around tne -LJ~i~i~l ^ 
 
 wx p , . .v,_ m^tr In this case the 
 
 boundary except the boundary defined by the 0STR. 
 
 selection of bytes past the boundary is inhibited. 
 
 The boundary inhibit gates are inserted every eight 
 Dy tes. The one (of four) boundary gates which inhibits propagation 
 
 . +0 .nf qeipfted hv the (decoded) 
 of select-next signals is itself selected oy m \ "natural" 
 
 contents of the 0STR. Boundaries are located at the our n u ^1 
 wlred - in aouble-word addresses. The inhibit gates allow c lis 
 loa ded into the 0S right up to, but never beyond, the boundary. 
 
 Section 
 
 2.3-1-3 - 2/2 
 
 9/17/69 
 
2.3.1.1+ Stack Overflow-Underflow Sensing Logic 
 
 The stack overflow/underflow sensing logic determines the 
 position of the top of the stack within the 32 bytes in OS hardware 
 buffers relative to the boundary between the TP and Main Storage 
 portion of the stack. Inputs to the OV/UF logic come from the OSTR, 
 the SCR, the adder overflow flip-flop A50V and the cell size decoder. 
 
 The philosophy of the OV/UF logic is first to discover which 
 double word the top of the stack (SCR) is in relative to the boundary 
 (OSTR): the first or second double-word above the boundary or the first 
 or second below the boundary. Then, on the basis of the input cell 
 size and the position of the top of the stack within the double-word (as 
 given by the low-order bits of the SCR) the appropriate output signal is 
 activated: 0V1, 0V2, UF1 , or UF2. 0V1 indicates that there is inadequate 
 room in the hardware stack to insert one cell of the indicated size. 0V2 
 indicates that there is not room for two of the given cells. UF1 states 
 that there remains less than one of the cell of the indicated size in 
 the hardware stack. And UF2 shows there is less than two cells remaining. 
 
 The equations for the position of the top of the OS relative 
 to the boundary are: 
 
 3/12/69 Section 2. 3.1 A - 1/U 
 
E01 = X^Yg v WW v X 1 X 2 Y 1 Y 2 v X^Yg 
 
 = «i« if the top of the OS is in the D-word immediately 
 preceding the boundary. 
 E02 = ljgj 2 ▼ ^VA v ^y^ ▼ X i X 2 Y l Y 2 
 = '1' if the top of the OS is in the second D-word 
 preceding the boundary. 
 
 EU1 = I^Y^ V V2V2 V X 1 7 2 Y 1 Y 2 V X 1 X 2 Y 1 Y 2 
 = •!' if the top of the OS is in the same D-word as 
 
 the "boundary. 
 
 EU2 = WW v X l X 2 Y l Y 2 V X A Y 1 Y 2 V X 1 X 2 Y 1 Y 2 
 = «i« if the top is in the second D-word above the 
 
 boundary . 
 
 y and Y are defined as SCR n and SCR and Y 
 In the above equations, X ± and X g are aenneu ± 21 
 
 and Y are OSTR x and 0STR 2 respectively. 
 
 The above overflow/underflow enable signals are then combined 
 
 with the cell size and SRO inputs to generate the true OV/UF signals. 
 
 The "region of effect" of the E-signals may be shown by the followxng 
 
 diagram: 
 
 Bottom limit 
 
 E02 E01 |/eU1 ■ EU2 
 
 I 1 \ " I ^ 
 
 /* boundary as defined by OSTR 
 
 Top Limit 
 
 3/12/69 
 
 Section 2.3.1^ " 2 A 
 
In the case where the SCR points to the boundary defined by 
 the 0STR we have a problem of knowing whether the stack is completely 
 empty or completely full. For this situation EU1 = 1 , while EU2, E01 
 and E02 = 0. What we really want to know, is where the SCR was pointing 
 just before it moved to the 0STR boundary. If it was in the EU1 region, 
 the stack is now empty, while if it was previously in the E01 region 
 it is now full. 
 
 To determine this, a stack full flip-flop (0SF) is used. When- 
 ever the SCR is modified using the SCR M0D control sequence, a signal 
 sets 0SF to 1 if the following conditions are satisfied: 
 
 a) the first two bits of the new value of the SCR (which 
 at this time will be in the adder output register, TRl) 
 are equal to the 0STR , 
 
 b) the low order 3 bits of the SCR are zero, 
 
 c) the E01 signal was activated by the old value of the SCR. 
 
 This assures that when the SCR "approaches" the 0STR from region E01 , 
 the stack will be declared to be full. Once 0SF has been turned on, it 
 is used to keep both 0U1 and 0U2 turned on. 
 
 0SF is reset by the main control using the R0SF signal when- 
 ever the SCR is modified. This is necessary as a preliminary to checking 
 for a possible "stack full" condition at the new SCR position. 0SF 
 is also reset whenever the 0STR is moved. 
 
 The actual over flow /under flow signals may now be defined: 
 0V1 = 0SF v E01 • CSD • (X, v X, v X _) v E01 • CSW • X ■ (X, v I ) 
 
 v E01 • CSH ■ X • X, • X c 
 0V2 = 0V1 v E02 • CSD • (X 3 v X^ v X ? ) v E01 ■ CSW«(X v X^ v X ) 
 
 v E01 • CSH • X • (X, vX,)t E01 • CSB • X, . X, -X 
 
 UF1 = EU1 • CSD v EU1 • CSW • X_ v EU1 • CSH • X • X, v EU1 • CSB'X ■ X, • X 
 
 J 3 4 3 k 5 
 
 UF2 = UF1 v EU2 • CSD v EU1 • CSW v EU1 • CSH • x" v EU1 * CSB • X • X, 
 
 3 3 4 
 
 where once again the X's refer to the SCR bit positions. 
 
 11 /5/T0 Section 2.3.1. U-3/U 
 
• a i s are used in the OS sequencing control to control 
 These signals are usea iu 
 
 fl ..dating and to control the time of transfer of 
 
 ::r,;r;rr:r.rr. ...... - — . - - — 
 
 of the OS. 
 
 mi (WR) as the name implies, is used to 
 Temporary Register #1 (T1R), as t-ne + + „ om the 
 
 • nv a five -bit stack address. TIE has the output from the 
 hold temporarily a five dim receive 
 
 «„ Mt adder as its only input. Its primary function is to receive 
 five-bit aaaer Qther reglsters . 
 
 a sum from the adder before passing it on on fussed 
 
 j ,-v, +>,<= nvprf low/underflow logic, u-l&v,^ 
 Bits 1 and 2 are also employed m the overflow/ 
 
 above . 
 
 Temporary Register #2 (T2R) is, again, used to temporarily hold 
 yZesL However, TSR's functions are less transient than 
 five . tlt stack addresses ^ ^^ ^ 
 
 those of TR1. The purpose of T2R is , g 
 
 dri .e the decoding and hyte-seleotion logic, which turn 
 wo rd select inputs. T2R has as inputs the outputs of TIB 
 T2R-S outputs are also fed to the SCR. 
 
 Asters are not essential for the proper opera- 
 Two temporary registers are 
 
 , \ , loalc They do offer a speed increase over one- 
 tion of the «, contro lo ^ ^ ^ ^ ^^ ^ 
 
 agister ^^^^^^ first may he constructed in the five- 
 qu ich succes sion th d ^^ ^ ^ ^ ^ 
 
 hit adder and gated into 12K v address of the 
 
 ., 4.x, «™+ cell is being accessed, the anaress 
 SCR. Then, while the first cell i B as Eoon 
 
 second is computed and placed into T1R ready to be gated 
 as the access of the first cell is complete. 
 
 The adder itself uses full carry loohahead to speed addition. 
 „ adds in fewer than 6 «» delays (^ reader err ^ ^ ^ 
 „ rit eup of the 32 hit adder in Sec 10 . fo ^ ^ 
 Xoohahead principle and equations.) Its input a 
 
 .„, • += The sum is obtained from one 'A plus one 
 aad -B- inputs. Th sum ^ ^ ^ Mnstant 
 
 'A' inputs are the SCR, 0bK, an . 
 
 output of the adder goes to T1R. 
 
 If an overflow (or underflow), condition is detected, the five- 
 
 « Ustfv) is set. When this occurs, Pointer 
 
 Mt adder overflow flip- OP ^ ^ determlned 
 Register #13 is incremented (decrement 
 
 by the main control. &&!<* 2.3.1.U - U/U 
 
 11/5/70 
 
2.3.1.5 5-Bit Adder-Functional Description 
 
 The 5-bit Adder is the small full carry lookahead adder used 
 by the Operand Stack logic to perform any additions which may be needed 
 in its operation. This adder is totally independent and completely 
 separate from the Main TP 32-bit Adder. 
 
 The 5 bit Adder has two 5 bit input busses. The A input bus 
 has 3 possible sources: temporary register T2R, the Stack Control 
 Register, SCR, or the Operand Stack Top Register, OSTR. Note that in 
 the latter case only the two highest order bits are used. The B input 
 bus has two possible sources: the Constant Generator (see Section 
 2.3.1.2) or the tenporary register T2R. 
 
 The output of the 5-bit Adder is sent to temporary register 
 T1R. If an illegal result is obtained due to an overflow on either 
 an addition or a subtraction, the A50V flip-flop is set. 
 
 The 5 bit Adder is generally used to add or subtract numbers 
 from the SCR or 0STR when these registers are "moving" one of the 
 Operand Stack boundries. The Constant Generator can generate l's 
 complement numbers and if a low order carry is injected into the 
 adder (C5IN J) at the same time, a subtraction will result. 
 
 9/30/69 Section 2.3.1.5 - 1/1 
 
2.3.2 Signal Name Lists for the Operand Stack 
 2.3.2.1 Control Signals 
 
 Operand Stack: 
 
 CK0F/E 
 DB0S/G 
 DBST/G/ 
 
 FL0S/N 
 
 0SPF/G/ 
 0SPT/G/ 
 OSTP/G 
 0V1, 0V1/ 
 
 0V2 
 
 R0SF/ 
 
 SCRP/G 
 
 SCT2/G/ 
 
 T1R2/G/ 
 
 T1SC/G/ 
 
 T1ST/G/ 
 
 T2SC/G/ 
 
 UF1 
 
 UF2 
 
 ZSCR 
 
 Enable 0S overflow/underflow check 
 
 Gate the DBP— >0S according to 0S select lines 
 
 Gate DB-4SCR and DB-% 0STR (part of stack 
 
 initialization) 
 
 Inhibit flags of DBP from being gated into 0S 
 
 storage 
 
 Gate 0S-4 permuter (using 0S select) l's complement 
 
 Gate 0S -^permuter (using 0S select) true 
 
 Mask OSTR into permuter via 0SR 
 
 Output - indicates no room in 0S for cell of 
 
 current size 
 
 Output - indicates no room in 0S for 2 cells of 
 
 current size 
 
 Reset "0S full" flip-flop 
 
 Mask SCR into permuter via 0SR 
 
 Gate SCR-*T2R 
 
 Gate T1R -» T2R 
 
 Gate T1R -* SCR 
 
 Gate T1R-*0STR 
 
 Gate T2R -% SCR 
 
 Output - indicates 0S does not contain 1 cell 
 
 the size of CS 
 
 Output - indicates 0S does not contain 2 cells 
 
 the size of CS. 
 
 Output - SCR(3), SCR(U) and SCR(5) are 
 
 6/17/69 
 
 Section 2.3-2.1 - 1/2 
 
5 Bit Adder: 
 
 ADD5/E/ 
 KB/G 
 
 0TA/G 
 RSYS/ 
 SCA/G 
 T2A/G 
 T2B/G 
 
 Enable the 5 hit adder 
 
 gate output of const, gen. to B input of 
 
 5 bit adder 
 
 gate 0STR-* A input of the 5 hit adder 
 
 reset system 
 
 gate SCR -> A input of the 5 hit adder 
 
 gate T2R-*A input of the 5 hit adder 
 
 gate T2R -* B input of the 5 hit adder 
 
 Constant Generator; 
 
 X2/ 
 
 S/E 
 
 CGBi/ 
 
 0SCG/E/ 
 
 0SCG1/E 
 
 0SCG2/E 
 
 0SCGU/E 
 
 0SCG8/E 
 
 0SCG16/E 
 
 if "0", multiply output of constant generator 
 
 hy 2 
 
 subtract enable - if = 1, generate negative 
 
 const . 
 
 constant generator intermediate bus - hit i 
 
 enable generation of a const, from control 
 
 generate 1 on constant bus 
 
 generate 2 on constant bus 
 
 generate h on constant bus 
 
 generate 8 on constant bus 
 
 generate l6 on constant bus 
 
 5/16/69 
 
 Section 
 
 2.3-2.1 - 2/2 
 
2.3.2.2 Internal Signals Used by the Operand Stack 
 Operand Stack 
 
 BROSi 
 
 BYi 
 
 E01 
 
 E02 
 
 EU1 
 
 EU2 
 
 0SF 
 0Si/S/ 
 
 0STPi 
 
 SCRi 
 TIRi 
 T2Ri 
 
 Input bus to permuter from Base Register and 
 
 OS storage - bit i 
 
 First byte select from 0S, byte i on if it 
 
 is first byte selected decoded from T2R. 
 
 = 1 if top of 0S is in DW immediately preceding 
 
 0STR boundary. 
 
 = 1 if top of 0S is in second DW immediately 
 
 preceding 0STR boundary. 
 
 = 1 if top of 0S is in same DW as 0STR 
 
 boundary . 
 
 = 1 if top of 0S is in second DW above 0STR 
 
 boundary . 
 
 Operand Stack Full 
 
 0S select; if on indicates ith byte has been 
 
 selected (l to h signals will be on at one 
 
 time ) 
 
 Operand Stack Top Register (indicates the 
 
 double "word at the boundary between the 
 
 hardware OS stack and core memory) - bit i 
 
 Stack Control Register (gives current entry 
 
 point to OS) - bit i 
 
 Temporary Register #1 = output from 5 bit 
 
 adder - bit i 
 
 Temporary Register #2 = output from T1R or 
 
 SCR - bit i 
 
 9/17/69 
 
 Section 2.3.2.2 - 1/2 
 
5 Bit Adder: 
 
 Ai 
 
 A50V 
 
 Bi 
 
 Ki 
 
 OSTRi 
 
 SCRi 
 
 TIRi 
 T2Ri 
 
 "A" input to Adder (= 0STR, SCR, T2R) - bit i 
 if on, 5 bit adder overflowed 
 "B" input to Adder (= T2R, K) - bit i 
 output of const, generator- bit i 
 
 "Operand Stack Top" register - bit i 
 
 Stack Control Register - gives current entry point 
 
 to OS - bit i 
 
 w Rp^ster #1-5 bit adder output - bit i 
 Temporary Register n± j 
 
 Temporary Register #2 - bit l 
 
 Constant Generator: 
 
 CSB 
 
 CSD 
 
 CSH 
 
 CSW 
 
 Ki 
 
 Cell size is byte 
 
 Cell size is double word 
 
 Cell size is halfword 
 
 Cell size is word 
 
 Output of const, generator 
 
 - bit i 
 
 5/16/69 
 
 Section 2.3-2.2 -2/2 
 
2.3.3 Operand Stack - PL/1 Description 
 
 // FXFC PL1 
 
 //PL1.SYSPUNCH DD SYSniJT = R 
 
 //PL1.SYSIN DD * 
 
 OPSTKIN: PROC(CKOFE, CSB, CSO, CSH, CSW, 
 
 dbosg, osf, dspfg, nsPTGt osss, 
 
 nvi, ov2 t rosf, ufi, uf?, 
 ZSCR) ; 
 
 DCL(CKDEE,CSB, CSD, CSH t CSW, OBOSGt 
 
 osf, ospfg, osPTGt nssst nvi, ov2, 
 
 KOSF, UFI, UF2, ZSCR) BIT(l); 
 
 DCL( BR0S(36), BY(0:31), 0S(0:31,9), nSS(0:31), OSTR(2), 
 SCR(5), T1R(0:5) ,T2R (5) ) BIT(l) EXTFRNAL; 
 
 OCL 
 
 (X(5), 
 Y(2) 
 
 ) BIT < 1 ) t 
 
 ( I , J,L ) FIXFD BIN, 
 (EDI , 
 E02, 
 EU1 , 
 EU2 
 
 ) BIT ( 1 ) ; 
 DCL T2RVAL FIXED BIN; 
 DCL GSTRVAL FIXFD BIN; 
 
 /* USE BYTE DECODER*/ 
 /* USE THE CONTENTS OF T2R TO SELFCT THE CORRESPONDING 
 BY( I ) SIGNAL */ 
 
 OSS= »0 »B ; 
 
 B Y = » • B ; 
 
 OSS S= DBOSG IOSPTG IOSPFG; 
 
 IF -.OSSS THEN GO TO CKSCRZ; 
 
 T2RVAL=0? 
 DO 1=1 TO 5; 
 
 IF T2R ( I ) THEN 
 
 T2RVAL = T2RVAL + 2**( e >-I ); 
 
 END; 
 
 BY( T2RVAL )=• 1 ■ B; 
 
 /* NEXT 3 BYTE SELFCT. 
 
 USE THE BY(I) SIGNALS TO SELECT AN OSS(I) SIGNAL AND UP TO 
 3 SUCCESSIVE OSS(I) SIGNALS */ 
 
 IE T2RVAL<=28 THEN 
 
 DO I=T2RVAL TO (T2RVAL+3); 
 OSS( I )=• i»b; 
 END; 
 
 ELSE DO; 
 
 DO I=T2RVAL TO 31; 
 OSS( I ) = '1 , B; 
 END; 
 
 11/5/70 
 
 Section 2.3.3 - 1/6 
 
On 1=0 TO (T2RVAL-28); 
 
 nss( I )= , i , b; 
 end; 
 
 fnr; 
 
 OSTRVAL=0; 
 
 IF nSTR(l) THFN OSTR VAL = OSTR VAL +16, 
 
 IF 0STR(2) THEN OSTR VAL=OSTR VAL +8; 
 
 ' F "T^V^HBV.roilBVO!, THB. OSS < > , OSS < ! , . OSS < 2 , = ' • B; 
 
 END; 
 flsf no; 
 
 i =nsTRVAi_; 
 
 IF BY( 1-1 ) I BY ( 1-2) !BY( 1-3) 
 
 THEN nSS(I),0SS(I+l>,0SS(I+2)='0'B; 
 
 end; 
 
 /* LOAD BRDS FROM OS */ 
 
 IF (OSPTG|OSPFG)S-DBOSG THEN DO; 
 
 on 1=0 to 31 ; 
 
 IF OSSU ) THEN DO; 
 /; , : L IS TH F = BYT^PHSITION OF THE BROS TO WHICH THE 
 SFLFCTFD BYTE OF THE OS IS GATED */ 
 00 J=l TO 9; 
 
 BRGS(L*9+J)=nS( I tJ) ; 
 
 FND; 
 END; 
 end; 
 
 IF nSPFG THEN BRnS =^BROS; 
 
 fmd; 
 
 /♦CHECK FOR 
 
 BITS =0 */ 
 
 SCR ON DOUBLE WORD BOUNDARY, I.E. LOW ORDER 3 
 
 CKSCRZ: ZSCR = -SCR(3)&-'SCR(4)&-iSCR(5); 
 
 /;;: C hfCK FOR OVERFLOW*/ 
 1F kqSF THFN OSF ='0'B; 
 
 nn 1=1 to 5; 
 
 x ( i )=scr( i ) ; 
 END; 
 
 no 1=1 to 2; 
 
 y(I)=ostr(I); 
 END; 
 
 E01- ^X(l)fi-X(2)fi-.Y(l)fi Y(2)hX(l)£ X(2 >fi Y ( 1)6-Y( 2 > 
 |X(1)^X(2)G Y(1)G Y(2)l X(l)6 X ( 2 > £-Y ( 1 > &-Y < 2 > , 
 
 11/5/70 
 
 Section 2.3.3 - 2/6 
 
ED2 = X( 1 }£-.X(2)£-.Y( 1)£-Y<2) I X(l)£ X(2)£-«Y(1)£ Y(2) 
 l-XU )£-X(2)£ Y(l)£-Y(2) |-X(1)£ X(2J6 Y(l)£ Y(2) 
 
 EU1« ^X(l)£-.X(2)G-»Y(l)fi-,Y(2)|-.X(l)E X(2)£-Y<1)£ y(2) 
 I X(1)C-X(2)C Y(1)£-,Y(2)| X(l)£ X(2)£ Y(l)£ Y(2) 
 
 EU2 = -.X(l)£iX<2)£ Y(l)£ V(2)hX(ll( X (2 >6«-Y< 1 ) 6-,Y<2 ) 
 
 I X(1)£-.X(2)£-Y(1)£ Y(2)| X(l)£ X(2)£ Y(l)£-Y{2) 
 
 nvi= OSF |Eni£CSD£(X(3) |X(4) |X(5) ) 
 |FD1£CSW£X(3)£(X(4) |X(5) ) 
 lEni£CSH£X(3)£ X(4)£ X(5) ; 
 
 0V2= nvi |E02£CSD£(X(3) |X(4) |Xt5) ) 
 
 |E01£CSD£-.X(3)£-.X( A)£-.X (5 ) 
 
 |E01£CSW£(X(3) I X ( A ) | X ( 5 ) ) 
 
 |E01£CSH£X(3)£(X(4) | X ( 5 ) ) 
 
 |E01£CSB£X(3)£X(4)£X(5) ; 
 
 UF1= FIJ1£-.DSF£CSD 
 
 I EUl£-.nSF£CSW£-.X(3) 
 
 I FI)1£-.0SF£CSH£-.X( 3) £-.X(4) 
 
 I EUl£-.nSF£CSB£-.X(3)£-.X(A)£-.X (5 ) ; 
 
 UF2= IJF1 
 
 I EU2£CS0 
 
 I EW1£-.0SF£CSW 
 
 I EUl£--nSF£CSH£-.X (3) 
 
 I FUl£-.nSF£CSB£-»X(3 )£-X(4) ; 
 
 IF CKOFF THEM 
 
 IF OV2 THEN 
 
 IF OSTR( 1 )=T1R( 1 ) THEN 
 
 IF DSTR(2)=T1R(2) THEN DO; 
 
 nsF=«i«B; 
 nvi=« 1«B; 
 END; 
 END DPSTKIN; 
 
 n /5/TO Section 2.3.3 -3/6 
 
A ODER 5 
 
 PRQC ( 
 
 OCL ( 
 
 DCL 
 
 OCL 
 
 OCL 
 
 IF 
 
 IF 
 
 /* 
 
 A,B 
 
 A50V T 
 
 RSYSt 
 
 TISTGt 
 
 A50V, 
 
 RSYSt 
 
 T1STG, 
 
 ADD5E, 
 
 SCAGt 
 
 T2AG, 
 
 AOD5E t 
 
 SCAG, 
 
 T2AG, 
 
 IF 
 
 (HSTR(2), (K,SCR,T2R)(5)t 
 
 ( A , B ) ( : 5 ) R I T ( 1 ) ; 
 I FIXED bin; 
 T2SCG THEN DO 1=1 TO 5; 
 SCR( I )=T2R( I ) ; 
 fnd; 
 
 SCT2G THEN DO 1=1 TO 5; 
 
 T2R( I ) = SCR( I ) ; 
 
 END; 
 LOAD A AND B INPUTS */ 
 
 = «o ' b; 
 
 IF OTAG THEN BEGIN; 
 /* GATE HSTR TO A */ 
 
 mi )=nsTR( l ) ; 
 
 A(2 )=GSTR(2) ; 
 
 A ( 3 ) , A ( 4 ) , A ( 5 ) = ' ' B ; 
 
 end; 
 
 SCAG THFN DO I = 1 TO 5 ; 
 
 a( i ) = scr( i ) ; 
 END; 
 
 C5INJ, 
 SCT2Gt 
 T2BG, 
 C5INJ* 
 SCT2G» 
 T2BG, 
 T1R(0:5> ) 
 
 KBG, OTAG, 
 
 T1R2G, T1SCG. 
 T2SCG) ; 
 
 KBGt OTAG, 
 
 T1R2G, T1SCG, 
 T2SCG) BIT(l); 
 BIT(l) external; 
 
 1F J2AG THFN DO 1=1 TO 5; 
 A( I )=T2R( I ) ; 
 ENO; 
 IF T2BG THFN 00 1=1 TO 5; 
 B( I )=T2R( 1 ) ? 
 ENO; 
 IE KBG THFN 00 1=1 TO 5; 
 
 b( I )=k ( I ) ; 
 ENO; 
 
 /.; PERFORM ADDITION */ 
 IF AODSE THEN 
 
 f ai I AonssoB ; 
 
 /; . C HECK FOR OVERFLOW */ 
 
 AS0V = AD0SFM^C5INjr,TlR(0)|CSINJ^TlR(0)); 
 
 J* CHECK FOR TRANSFERS INVOLVING T1R,T2R,SCR, 
 
 OR THE OSTR */ 
 
 [F T1STG THEN DO 1=1 TO 2; 
 USTR ( I )=T1R( I ) ? 
 
 end; 
 
 I F T1SCG THEM DO I =1 TO 5 5 
 
 scr( i ) = tir( i ) ; 
 
 end; 
 
 IF T1R2G THEN DO 1=1 TO 5; 
 T2R( I )=T1R( I ) ; 
 
 11/5/70 
 
 Section 2,3.3 - k/6 
 
FND: 
 /* RESFT SYSTEM */ 
 IF RSYS THEN 
 
 A50V=«0«B; 
 
 ADD5SUB: PROC; 
 
 DCL (I, ONE) FIXFD BIN, C BIT (6), X FIXED BIN(6,0>; 
 ONE=l ; 
 x=o; 
 
 no I = o to 5; 
 
 IF A(I) THEN X=X+2**( 5-1 ) ; 
 IF B(I) THEN X=X+2**<5-I ) ; 
 END; 
 IF C5INJ THEN X=X+1; 
 C = BIT( X,M; 
 DO I =1 TO 6; 
 T1R( 1-1 )=SUBSTR(C, I ,OME) ; 
 END; 
 END ADD5SUB; 
 END ADDER 5; 
 /* 
 
 11/5/70 Section 2.3.3 - 5/6 
 
CHNSGEN: PRDC (C5INJ, 
 
 0SCG16E, 
 DSCGE, 
 DCL(C5INJ»CSB, 
 
 0SCG1E, 
 SEt 
 
 CSB» 
 
 0SCG1E, 
 
 SE, 
 
 CSD, 
 
 nSCG2F T 
 
 CSD» 
 OSCG2E, 
 X2) ; 
 CSHt 
 nSCG^Et 
 
 CSH, 
 OSCG^E, 
 
 csw, 
 
 DSCGRE, 
 
 CSWt 
 OSCGBFt 
 
 0SCG16E, 
 
 nscGF* 
 
 X 2 ) B I T ( 1 ) ; 
 
 L K (5) BIT(1) EXTERNAL*, 
 
 ^"^AN^^e'dEEINE^ CONVENIENCE TO S.MPLIP, THE 
 
 FOUATinNS. */ 
 
 ocl 
 
 CGB(5) BIT (l)t (T1,T2) BIT (1); 
 
 T2=-OSCGE£X2; 
 Tl=-X2? 
 
 CGBd )=T2fXSD|nSCG16E; 
 CGB ( 2 > =T1 £CSD I T2RCSW I DSCG8E ? 
 C GB ( 3 ) =T 1 PXSW I T 2 RC SH | 0SCG4E ; 
 C( ; H ( 4 ) =T 1 T.CSH I T2 &C SB | OSCG2E ; 
 
 rirxsB inscGlE; rrR'S TO THE K ( I ) • s 
 
 MUMRER IS TO BE NEGATIVE, GATE THE ( » S ^ PjB(I) J 
 IRECTLY, HTHFR^ISE* FOR POSITIVE niimh.. 
 
 CGR(5)=T1£CSB lOSCGlF; 
 / * I F M 
 1 ) 
 j I ^sf THEN DO*, 
 
 k=cgb; 
 
 csinj^'o 1 b; 
 
 else on; 
 
 k=-CGb; 
 C5INJ=' i'b; 
 
 ENo; 
 !-MF) r iwsgfn; 
 
 /* 
 
 11/5/70 
 
 Section 2.3.3 - 6/6 
 
2.3.^ Operand Stack - Logical Description 
 2.3.1+.1 Operand Stack Storage 
 
 The storage used for the fast storage of the Operand Stack 
 consists of k storage blocks of the type described in Section 2.2. Each 
 block provides 8 bytes of 9 bit storage for a total of 32 bytes of fast 
 storage. 
 
 The actual byte positions are arranged so that the first block 
 contains bytes 0, U, 8, ..., 28, the second block contains 1, 5, 9, ... 29, 
 and so on. 
 
 The input to the OS storage consists of 32 select lines, OSi/S, 
 the Distribution Bus (DBP) from the Permuter and k data control lines: 
 
 DBOS/G, FLOS/N, OSPT/G and OSPF/G. Figure 2.3.U is an exerpt from the 
 01-U drawing in the TP Logic Book. It shows a diagram of the fourth 
 storage block in the OS fast storage and indicates the various inputs and 
 outputs to the block. 
 
 The DBOS/G control signal is used to gate the DB through the In- 
 put Gate Drivers into the four storage blocks. Since there is only one 
 type of storage in these four blocks (as opposed to, s a y, the PR storage 
 which also contains the Spare Buffer Register ), all of the read/write 
 enable signals to the Byte Select Drivers (BSD's) can be activated by the 
 same signal. Thus the DBOS/G signal is fed to 9 inverters. One of these 
 drives the four IGD's. The other 8 each drive four read/write enable inputs 
 to the BSD's. Thus all 32 read/write enable lines are activated more or 
 less in unison with the IGD gate signals. Only the "Gate Both In" option 
 is used on the IGD's. 
 
 The FLOS/N signal is used by the OS storage blocks to inhibit 
 writing in the flag positions. FLOS/N drives an inverter which then 
 feeds the In Data Inhibit signal to the Input Gates on the flag bit 
 
 11/5/70 Section 2.3-U - 1/3 
 

 TO THE REMAINING OS 
 STORAGE BLOCKS 
 
 04_3 0BP28 
 
 J 
 04-3 DBP36 
 
 C 
 16-5 
 
 FLOS/N 
 
 OSPT/G 
 
 OSPF/G 
 0S3/S 
 
 0S7/S 
 
 OSII/S 
 
 0SI5/S 
 
 0SI9/S 
 
 0S23/S 
 
 0S27/S 
 
 16-3 0S3I/S 
 
 C DBOS/G 
 
 1-5 
 x44 203-00 
 
 X44 
 X44 
 
 X44 
 X44 
 
 X43 
 
 BSGI6 
 
 BR0S28 04-3 
 
 I 1 
 
 BR0S36 04-3 
 
 5/2/69 
 
 FIGURE 2.3.4 
 
 Section 2.3-U - 2 / 3 
 
position of every byte in the OS fast storage (see Figure 2.2.1/2). 
 
 The OSPT/G and OSPF/G control signals are connected to the 
 "Gate False Out" and "Gate True Out" inputs of the Output Gate Drivers, 
 respectively (see Figure 2.2.1/3). This seemingly reversal of the gate 
 signals is brought about because it is necessary to dot-or the outputs 
 of the Operand Stack Storage Blocks and thus the inverted values must 
 be sent out. The output from the OS fast storage is the Base Register- 
 Operand Stack Bus (BROS). When either the OSPT/G or OSPF/G control 
 lines are set to "0", the true or l's complement representation of the 
 selected bytes in the OS fast storage are dot-ored to the BROS. Note 
 
 that if both OSPT/G and OSPF/G are set to logical "0" at the same time, 
 logical "0" would result in all positions. 
 
 Each block (representing 8 interleaved bytes) is gated to a 
 separate byte of the BROS. When one of the output control lines is 
 activated the selected bytes are gated to the bus. As explained in 
 Section 2.3.1.3., no more than four bytes are ever gated out at one 
 time from the OS storage. Since the blocks are permanently connected 
 to the BROS, the OS bytes always come out in the same position on the 
 BROS regardless of where the cell boundaries happen to be. Therefore, 
 the Permuter is used to justify the boundaries of the BROS bytes when 
 the information is transferred to the DB. 
 
 11/5/70 Section 2.3.U - 3/3 
 

2.3.U.2 Overflow-Underflow- Logical Description 
 
 As explained in Section 2.3.1.1+ the OS overflow/underflow 
 logic can be broken up, conceptually, into several sections. First 
 there are the equations for the position of the SCR relative to the 
 OSTR, i.e. E01, E02 , EU1, and EU2. Secondly, there are the equations 
 for the overflow and underflow signals themselves, i.e. 0V1 , 0V2, UF1 
 and UF2. Finally there is the logic involved in setting and using the 
 OS Full flip-flop, OSF. All three sections of logic are shown in Drawing 
 16-6 of the TP Logic Book and will now be explained. 
 
 The equations for E01 , E02 , EU1 and EU2 as given previously in 
 Section 2.3.1.*+ are fairly straightforward to implement. The diode matrix 
 board, 236-01, which is shown in Figure 2. 3- h. 2/1 as a logical circuit and 
 in Figure 2. 3. h. 2/2 as a schematic, is used to calculate the equations. 
 This board is simply a four-bit decoder which decodes all possible combina- 
 tions of the two high order SCR and OSTR bits. The inputs to the diode 
 matrix are driven by 228-07 circuits. The 16 individual outputs of the 
 diode matrix are sent to 228-05 circuits, the outputs of which are dot-or'ed 
 to generate the four signals according to the equations in Section 2.3.1.4. 
 These signals are inverted by k 228-07 circuits for use in the 0V1, 0V2, 
 UF1 and UF2 equations. 
 
 The equations for 0V1 , 0V2, UF1, and UF2 are considerably more 
 difficult to implement. As shown in Section 2.3.1.1+ they are as follows: 
 
 0V1 = 0SF v E01-CSD-(X v X, v X ) 
 
 *J T" J 
 
 v E01-CSW-X 3 - (X^ v X ) v E01-CSH-X • X^ X 
 
 V2 = 0V1 v E02-CSD-(X v X, v X ) 
 
 v E0LCSD v E01-CSW-(X v X.VX ) 
 
 v E01-CSH-X 3 -(X 1+ v X 5 ) v E01.CSB-X-X 1+ -X 
 
 8/12/69 
 
 Section 2.3.4.2 - 1/j 
 
r 
 
 
 
 
 
 
 
 
 
 otnl t 
 
 3 f . 
 
 
 ~"\ A i 
 
 SCR2 r 
 
 ("VCTDI 
 
 7 . 
 
 
 
 
 
 
 
 
 
 0STR2 | 
 
 T 
 
 15 • 
 
 
 1 1 
 
 <>■ 
 
 
 N B ' 
 
 
 
 
 
 
 
 
 
 
 
 
 0STR2 1 
 
 9 
 
 1 
 
 
 I 
 
 II 
 
 ^\ 
 
 \ C i 
 
 
 
 
 
 
 
 
 
 
 OSTRI 
 
 
 
 
 
 1 
 
 I' 
 
 — 1 
 
 ^ E ' 
 
 
 
 
 
 _J ; 
 
 
 
 
 
 
 
 ■ 
 
 
 l 5 
 
 
 < 
 
 1 
 
 
 1 
 
 -i 
 
 ^\ fi 
 
 
 
 
 
 _>^- 
 
 
 
 
 
 
 SCR2 
 
 l < 
 
 1 
 2 
 
 
 1 
 
 
 1 
 
 
 
 
 A H 
 
 
 
 
 
 
 
 
 
 
 
 ►— 1 
 
 
 
 i 
 
 
 1 
 
 
 
 1 
 
 ^ jj 
 
 
 
 
 
 
 _J : 
 
 
 
 
 
 
 
 
 
 i 
 
 
 
 
 
 
 Lh 
 
 A L 1 
 
 
 
 
 
 
 — 
 
 _>^- 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 SCRI 
 
 ; 
 
 
 
 
 
 
 > 
 
 
 "\ Pi 
 
 
 
 
 _J ! 
 
 
 
 
 
 
 
 
 I 
 
 ►— — 
 
 > \ r 1 
 
 
 
 
 — ^T 
 
 
 
 
 
 
 
 
 
 
 » — 
 
 *\ Ti 
 
 
 
 
 jT 
 
 
 
 
 
 
 y i 
 
 
 
 
 
 
 
 i>— 
 
 "\ u 1 
 
 
 
 
 
 Pr 
 
 
 
 
 
 
 y , 
 
 
 
 
 
 
 n— 
 
 ""N V| 
 
 
 
 
 
 
 
 
 
 ' 
 
 
 
 
 
 
 
 ii— 
 
 *\ Ul 1 
 
 
 
 
 
 1 w 
 
 
 
 J ' 
 
 
 
 
 
 y , 
 
 
 
 
 
 
 ii — 
 
 "\ Yi 
 
 
 
 
 
 - It 
 
 
 
 
 
 y i 
 
 
 i V— 
 
 
 
 
 A z 1 
 
 
 
 
 >Ht~ 
 
 
 
 
 
 y 
 
 
 
 
 
 
 
 
 
 j 
 
 Figure 2. 3. U. 2/1 - SCR-0STR Decoder for 
 E01, E02, EU1, EU2 Signals Logic Representation 
 
 9/10/69 
 
 Section 2.3.U.2 - 2/7 
 
IV 
 
 ' J 
 
 :i i : 
 
 )[ 
 
 
 
 
 go 
 
 > 
 
 3 
 
 1 
 
 IJL 11. 
 
 
 
 
 
 i^ 
 
 1 
 
 M 
 
 w 
 
 
 
 
 CD 
 
 > 
 
 
 n , 
 
 
 
 
 
 to 
 
 D 
 
 -\ 
 
 : i : 
 
 [ 
 
 
 
 
 5; 
 
 h- 
 
 .. 
 
 M 
 
 
 
 
 
 ro 
 
 
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 — •- 
 
 \ 
 
 
 
 
 OJ 
 
 Q_ 
 
 . L 
 
 — * 
 
 
 
 
 
 — 
 
 Z 
 
 
 
 
 
 
 
 O 
 
 5 
 
 
 
 
 
 
 
 en 
 
 _J 
 
 • ■ 
 
 """"? T"~ 1 
 
 11 11 1 
 
 [ 
 
 
 
 
 CD 
 
 "3 
 
 
 \[ ll 11 
 
 
 
 
 
 i^ 
 
 X 
 
 
 — •— — • , 
 
 ii y. ] 
 
 
 
 
 
 CD 
 
 Ll. 
 
 -• 
 
 — •— — • 1 
 
 
 
 
 
 m 
 
 LlJ 
 
 . . 
 
 — •— 
 
 W 1 
 
 
 
 
 
 «- 
 
 Q ' 
 
 .. 
 
 El 
 
 
 
 
 
 ro 
 
 OQ 
 
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 — — • 
 
 
 
 
 
 CM 
 
 * 
 
 I " 
 
 I JL 
 
 
 
 
 
 — 
 
 Q 
 
 h 
 
 C 
 
 ;o - cm 3 
 
 ^ cq. -. - a 
 
 io r*- (j) k5" u 
 
 d co 
 
 o 
 
 CM 
 
 Oi 
 
 CJ 
 
 OJ 
 CM 
 
 -2i 
 
 J 2 
 
 t— i 
 
 _ 
 
 CV) 
 
 CVJ 
 
 oc 
 
 1— 1 
 
 a: 
 
 tr 
 
 QC 
 
 LL 
 
 q: 
 
 h- 
 
 H 
 
 o 
 
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 C7) 
 
 CO 
 
 U) 
 
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 CM 
 
 a: 
 
 CV) c/> 
 
 o o 
 
 Figure 2. 3.^.2/2 - 
 
 SCR-0STR Decoder for E01, E02, EU1, EU2 Signals 
 Diode Matrix Representation 
 
 9/10/69 
 
 Section 2.3.U.2 - 3/7 
 
UF1 = EUl> OSF- CSD v EU1- OSF- CSW- X 3 
 
 v EUl'OSF-CSH-X 3 - X^ v EULOSF-CSB-X^ X^^ 
 
 UF2 = UF1 _ 
 
 v EU1-OSF-CSW v EU1-OSF.CSH X 3 
 
 v EUl-OSF-CSB-X 3 « I h 
 
 where, as before, X. represents SCRi. 
 
 When implemented by the logic in Drawing l6-6, however, these 
 equations look considerably different. For 0V1 we have: 
 
 0V1 = OSF v (E01-CSD'(X 3 v X H v X^) 
 v E01-CSW-(X • U k v X 5 )) 
 v E01-CSH-(X 3 « X u -X 5 ) ) 
 
 Note that 0V1 consists essentially of two terms which are inputs to a 
 21 U-03 driver going to the control logic. The first term comes directly 
 fr om the output of the OSF flip-flop. The second term is produced by 
 dot-oring 3 NAND circuits together. Each of these NAND's has as inputs 
 the E01 signal, a cell si.e signal, and some function of the 3 low-order 
 bits of the SCR. 
 
 The equation for 0Y2 as implemented by the logic can be written 
 
 as follows : 
 
 0V2 = OSF v (E01-CSD-(X 3 v X u v X 5 ) 
 V E01-CSW-CX • U h v X 5 )) 
 VE01- CSH-(X 3 ' X h - X 5 ) ) 
 v (E02-CSD-(X 3 v X^ v X ? ) 
 
 v E01 • CSD 
 
 v E01-CSW-(X 3 v X^ v X 5 ) 
 
 v E01-CSH-(X - (X u v X 5 )) 
 
 v E01-CSB-(X 3 « X u - X 5 ) ) 
 
 Section 2.3.^-2 -V7 
 Q /1 -3 /£n 
 
This equation consists of three terms all of which are inputs to a 21U-03 
 driver going to the control logic. The first two terms are identical to 
 the ones used for 0V1 . These replace the 0V1 term in the original 0V2 
 equation and eliminate the need to invert the 0V1 output and use it as an 
 input to 0V2, thus saving 2 collector delays. The third term has the same 
 format as the last term in 0V1 . It consists of 5 NAM) circuits dot-or'ed 
 together. Each NAND circuit has as inputs either E01 or E02, a cell size 
 signal, and a function of the low-order 3 bits of the SCR. Note that 
 three of these SCR terms are functions which were also used in 0V1, 
 except that in that case they were associated with different cell size 
 signals. 
 
 The logic implementation for UF1 and UF2 are somewhat confusing. 
 This is due, in part because they are partially implemented on the l6-6 
 drawing using DTL logic and partially implemented in the main control 
 logic using IC's. Because of several changes which were necessary after 
 the initial wiring of this logic, the structure is somewhat haphazard. 
 The actual implementation equations for UF1 and UF2 are as follows: 
 
 UF1 = (OSF • (EU1-CSD 
 
 v EU1- CSW-X, 
 
 v EU1- CSH-U • X, ) 
 
 v EU1-CSB-(X - X 2 - X))) 
 
 UF2 = (EU2-CSD) 
 
 v (0SF-(EU1-CSW 
 
 v EU1-CSH-X, 
 
 v EU1-CSB-X • X, )) 
 3 k 
 
 v (0SF.(EU1-CSD 
 
 v EU1- CSW-X. 
 
 v EU1- CSH-U -• X, ) 
 
 v EU1'CSB-(X ■ X.-X ))) 
 
 8/13/69 
 
 Section 2.3.U.2 - 5/7 
 
Note that UF1 consists of one term and UF2 consists of three terms, the 
 last of which is identical to the term for UF1 . This is done for the same 
 reasons as "before with 0V2 and 0V1. 
 
 In the case of UF1 and UF2, the final signals are formed by IC 
 
 NAND circuits in the control logic section of the TP. Thus the singly 
 
 term for UF1 (which is also the last term of UF2) is given the name UF12C 
 and is formed by a 21^-03 circuit using two inputs. The first input is 
 5sF and the second is the inverted output of a dot-or connection between 
 four NAND circuits. Each of these four NAND's has as an input the EU1 
 signal, a cell size signal and some function of the 3 low-order bits of 
 the SCR. 
 
 In addition to the UF12C signal, the UF2 signal has two other 
 
 terms which have been given the names UF2A and UF2B. The first term, U F2A, 
 consists of the output of one 21U-03 NAND which forms the term EU2-CSD. 
 The second term also comes from a 21H-03 circuit but uses two inputs. 
 The first is OSF. The second is the inverted output of a dot-or connection 
 between h NAND circuits. Each of these NAND circuits has as an input the 
 EU1 signal, a cell size signal, and some function of the 3 low-order bits 
 of the SCR. The 2 NAND circuits which form UF1 and UF2 in the TP Control 
 section are shown in Figure 2. 3. ^.2/3. 
 
 The final section of logic in the OS overflow/underflow logic 
 is the OSF flip-flop itself. As discussed in Section 2.3-l.U, the setting 
 and resetting of the OSF flip-flop is determined by the Main Control Logic, 
 specifically the OS ENTRY and SCR MOD sequences. 
 
 The OSF flip-flop will be set to "l" whenever the CKOF/E signal 
 goes to "1" and at the same time the two high order bits of the SCR are 
 equal to the OSTR, the three low-order bits of the SCR are "0", and the EU1 
 signal is on. In this situation the SCR is moving to the OSTR boundary from 
 the "full" side of the hardware registers. 
 
 OSF is reset by Main Control using the ROSF control line. 
 
 .. ,, Section 2.3. U. 2 - 6/7 
 
 8/13/69 
 
UFT2C 
 
 UFI 
 
 UF2A 
 UF2B 
 
 UF2 
 
 Figure 2. 3. U. 2/3 - UFI and UF2 IC Logic Implementation 
 
 9/10/69 
 
 Section 2.3.U.2 - 7/7 
 

2.3.^.3 3-Bit Adder-Logical Description 
 
 The 5-Bit Adder is a full carry lookahead adder generally 
 used for adding or subtracting constants from various operand stack 
 control registers. In basic construction it is somewhat similar to 
 the 32-Bit Adder (Section 2.7) except, of course, it is much simpler 
 since it has much fewer bit positions. The two 5 bit input busses 
 are the A bus and the B bus. The A bus is usually loaded with one of 
 the Operand Stack Registers and the B bus is usually loaded with a 
 + constant from the Constant Generator. The results of the addition 
 are stored in temporary Register TlR. 
 
 At each input bit position of the 5-bit Adder there are k 
 NAND gates. These NAND's are all activated by the ADD5/E signal and 
 produce for each bit position, i, a generate signal, GENi , and a transfer 
 signal, TRANi. 
 
 When a generate signal is on, it indicates that for the 
 particular bit position, i, a carry will be produced out of it independently 
 of whether or not a carry was made into the position. This can be 
 expressed as a function of the two input data bits for that position 
 by the equation: 
 
 GENi = Ai • Bi 
 
 When a transfer signal is on, it indicates that for the 
 particular position, i, a carry will be produced out of it only if a 
 carry is made into it. This can be expressed as a function of the two 
 input data bits for that position by the equation: 
 
 TRANi = Ai- m" v Ai 'Bi 
 
 Note that if a GENi signal is on for a given bit position the 
 TRANi signal for that bit position cannot be on and if the TRANi signal 
 is on, the GENi signal cannot be on. However, it is possible for both 
 signals to be off at the same time. 
 
 As can be seen in Drawing 16-3 of the TP Logic Book, these 
 two signals are actually each generated by "dot-oring" 2 NAND circuits 
 together. Figure 2. 3. U. 3/1 shows the GENi and TRANi logic for one bit 
 
 11/5/70 Section 2. 3.U. 3 - 1/5 
 
position of the 5-bit Adder. The so called "dot-ors" must really he 
 considered as MD circuits in the sense that if either input xs 
 forced to zero, the output will_be forced to zero. Thus we have: 
 
 GENi = (Ai) • (Bi) 
 = Ai * Bi 
 
 TRAM = (Ai • Bi) • (AT • "Bi ) 
 = (Ai • Bi) v 55 •"51) 
 = (Ai « Bi) v (Ai • Bi) 
 Once these two signals have been generated, they can be used 
 to calculate the carrys into every bit position of the adder by using 
 the following equations: 
 
 C5DI5 = C5MJ 
 
 C5Ilrt = G5 v 15 ' C51HJ 
 
 C5IN3 = Qlt v TU • G5 v TU • T5 • C5MJ 
 
 C5IN2 = G3 r T3 • Oh v 13 • A • G5 t T3 • TU • T 5 ■ C5IHJ 
 
 C5IH1 = G2 v T2 • G3 v T2 • T3 • Gl, v T2 • T3 • Tl, • G5 
 
 = Y T2 • T3 ' TU • T5 - C5MJ 
 C50V = Gl Y Tl • G2 T Tl • T2 • G3 v Tl • T2 • T3 • GU Y 
 
 = V Tl . T2 ■ T3 • T^ • G 5 Y Tl • 12 • T3 • TU • T5 • C 5 INJ 
 
 where Gi and Ti represent GESi and TRAHi respectiYely, C5IM is the 
 input carry into hit position i, C5H.J is an injected carry into the 
 low order hit (used in subtraction to conYert a Vs complement constant 
 to 2-s complement), and the adder hit positions are numhered heginnmg 
 with 1 at the highest order position. 
 
 The last k equations are implemented using the 236-00 Loohahead 
 Carry Generator diode matrix hoard shown in Figure 2.3.U.3/2. The two 
 initial ones are implemented using MB circuits. The outputs are sent 
 
 «* +h P S-bit Adder and the overflow indicator, 
 to the 5 output positions of the 5-bit Aaaer 
 
 The Adder outputs are determined by the equation: 
 
 Section 2.3.U.3 - 2/5 
 11/5/70 
 
Ai 
 Bi 
 
 Ai 
 Bi 
 
 Ai 
 
 Bi 
 ADD5/E 
 
 TRAN 
 
 — GEN 
 
 Figure 2. 3. h. 3/1 
 Generation of GENi and TRANi in the 5-Bit Adder 
 
 10/22/69 
 
 Section 2.3.^.3 - 3/5 
 
f 
 
 „ -*■ 1! S 
 
 
 >. — !! !! t 
 
 d 
 
 ^^ II 1 " 
 
 
 
 
 M i 1 1 * 
 
 3 !! !! !! y y- 
 
 U 
 
 -*j[i I jl I jl ; 
 
 2- 1 
 
 
 *■*■][! Ill 
 
 1 
 
 -H 1 — T T " 2 
 
 z ][ )[ j !1 
 
 
 -rtJ -T- ~ 0> 
 
 2 j ! 1 j : 
 
 >. 
 
 _H« 00 
 
 _j !! !! 
 
 > 
 
 
 
 y y y ± 
 
 10S 
 o 
 
 — W 1 1 1 lO 
 
 > 
 
 .-11 1 
 
 8^ 1 H 
 
 ro 
 
 1 
 
 *~II JL 
 
 s. 
 
 «~ : l! l_ _L 
 
 z 
 
 m m 't 
 z z z 
 
 «■ ro ro oj w = ^ 
 z z z z z § uj 
 
 LU < UJ < W 
 
 ^ I— i- r- H 
 
 Figure 2. 3. U.3/2 
 5-Bit Adder Lookahead Carry Generator - Diode Matrix - 236-00 
 
 10/22/69 Section 2 - 3 - k - 3 ~ k/5 
 
TIRi = TRANi ■ C5INi v TRANi ■ C5INi 
 The overflow bit is determined by: 
 
 A50V = C5INJ C50V v C5INJ C50V 
 
 This merely means that if an addition sum (C5INJ = 0) is greater than 
 31 or if a subtraction difference (C5INJ = l) is less than 0, the 
 A50V flip-flop will be set. This does not necessarily indicate a fatal 
 error. As is explained in Sections 2.3.1.U and k.^.l.k, this condition 
 is used to indicate stack wraparound. 
 
 Note that in the logic in Drawing 16-3 of the TP Logic Book 
 the inputs to the temporary register T1R and the 5-bit Adder Overflow 
 Flip-Flop, A50V, are enabled by the ADD51E signal. 
 
 10 /9/69 Section 2.3.U.3 - 5/5 
 

2.4 The Pointer Registers 
 
 There are 15 Pointer Registers (PR's) in the Taxicrinic 
 Processor. These registers are in some ways similar to the index 
 registers of more conventional machines, although they are much 
 more powerful. As with conventional index registers, the PR's may 
 be incremented, modified and tested. Thus they can be used in any 
 of the ways that an index register might be used, except that these 
 operations usually appear quite different in the TP because of the 
 unusual machine organization. 
 
 Primarily, however, the PR's are a means of addressing 
 storage. All storage accessing is performed "through" the PR's, by 
 indicating the name of the PR which contains the address desired instead 
 of requesting the actual address (the contents of the PR can be modified 
 as noted above). The indicated PR will contain a segment name and an 
 address in that segment relative to the segment base address. By 
 loading the PR's beforehand, the programmer can refer to any address in 
 memory by using only a 4-bit tag to indicate the name of the PR to be 
 chosen. (For a more detailed description of memory accessing, see 
 Section 4.1) . 
 
 In order to be able to choose a particular PR, each PR has 
 associated with it a 4-bit Name Register (NR). Each NR holds the 
 current "name" assigned to its associated PR. These names are unique 
 but not permanent, i.e., the name of the PR (which is a number for to 
 Ik) can be changed, but only one PR has any given name at any given time. 
 The process whereby the PR names are changed is called "name permutation" 
 and is described in detail in Section 4.2.4.3. 
 
 3/10/69 Section 2.4 - 1/2 
 
Since the PR's axe the onlv_ means hy which memory may he 
 accessed, the address of a variahle must he assigned to its particular 
 PR prior to its first call. Provisions are provided in the instruc- 
 tion set to initialize all designated PR's either one-at-a-time or hy 
 multiple assignment (using an imprimitive instruction, see Section U.2.U). 
 
 Section 2.U - 2/2 
 3/10/69 
 
2.U.1 Pointer Register Formats 
 
 There are three formats for the pointer registers. The 
 "normal" format is used in connection with the pointer stacks as 
 shown in Figure 2.U.1.1 of Section 2.U.I.I. 
 
 The "list processing format" is used with the list processing 
 instructions and does not utilize pointer stacking. Instead the pointer 
 is divided into two half-word link fields which are identical to the 
 contents in the cell currently being "looked at" by the pointer register. 
 
 The third format for pointer registers is the "available space" 
 format. This format is used whenever a PR is utilized to control the 
 assignment of list processing cells. In particular PRlU , which controls 
 the storage of the pointer registers in the pointer stacks, is in this 
 format . 
 
 3/10/69 Section 2.1+.1 - l/l 
 

2.4.1.1 Pointer Stack Format 
 
 Reflecting the nested nature of operand calls, pointer 
 stacks are provided into which the current value of a PR can be 
 pushed for safekeeping. When this value is again required, the 
 stack can be popped and the value reloaded into the PR. The pointer 
 stacks are maintained in main storage under the control of PRlU , which 
 is in the "available space" format (see Section 2.4.1.3). 
 
 The pointer stacks themselves are ordinary unidirectional 
 linked lists. The pointer stack cells take up two words of storage, 
 but only the first 6 bytes are currently being used. As shown in 
 Figure 2.4.1.1, the first two bytes are used to hold the 16 bit address 
 of the previous entry in the stack, while the next two bytes contain 
 the relative address within the segment. The final 2 bytes contain 
 the segment name. 
 
 □ D 
 
 □ D 
 
 □ □ 
 
 LINK 
 
 VALUE 
 
 NAME 
 
 Figure 2.4.1.1 Pointer Stack Cell 
 
 The physical Pointer Registers in the TP actually consist of 
 2 registers, a 4 byte register containing the link and value fields and 
 a 2 byte register containing the name field. This configuration of the 
 pointer register is referred to as the "normal" or "pointer stack" format 
 It should be noted that all flag bits are always pushed into the pointer 
 stacks along with the link, value and name fields. 
 
 6/17/69 
 
 Section 2.4.1.1 - l/l 
 

 
2.4.1.2 List Processing Format 
 
 The List Processing format for the pointer registers 
 differs from the normal PR format. As shown in Figure 2.4.1.2 it 
 consists of a left and right link instead of a link and value field. 
 The name field remains the same and indicates the name of the segment 
 being used as the base for the two links. There are no stacks con- 
 nected with PR's in this format. 
 
 □ 
 
 a 
 
 □ 
 
 □ 
 
 a 
 
 LEFT LINK 
 
 RIGHT LINK NAME 
 
 Figure 2.4.1.2 List Processing Format 
 
 In the list processing format, a PR can be considered to be 
 a "bug" which moves along a list structure in core. At any given 
 time the PR contains an image of the first four bytes of the cell cur- 
 rently being "looked at". These first four bytes will usually be inter- 
 preted as two separate pointers. It should be noted that the PR does 
 not contain a pointer to the cell being looked at. It only contains the 
 contents of the first 4 bytes of that cell. In the conventional method 
 of using the Illiac III list processing instructions (specifically SL 
 and SR), the address of the current cell will be available at the top 
 of the OS. 
 
 In use the PR can be used to sequence through a list structure. 
 At any given point, cells may be added or deleted to the "right" or "left" 
 of the current cell. Links in the structure may also be changed by using 
 the ASSIGN statement to load the contents of some PR into a cell in the 
 structure. Instructions such as POP and PUSH can also be used to load 
 and unload links from the OS. 
 
 3/10/69 
 
 Section 2.4.1.2 - l/l 
 
2.^.1.3 Available Space Format 
 
 The Available Space format la used whenever a PR is utilized 
 to control the assignment of list processing cells. nll U , which controls 
 
 11 r T of rointer resisters ln the polnter stackE - is *^ * «*. 
 
 iormat. As snown in Figure ? k i -z/i +i 
 
 qnp , «, g 2.4.1.3/1 the pointer register in the available 
 
 space format consists of a link f-i-i/i n ^ 
 
 ±lnk fleld and a co ^t field. The name field 
 
 L 6 rin^r 1 : T interPretati °" - fOT «» ~ -d list processing formats, 
 and lndl cates the n m e of the segnent being used as the base for the li„ k 
 
 and count relative addresses. 
 
 r 
 
 LINK 
 
 D 9 D D n 
 
 COUNT 
 
 NAME 
 
 Figure 2.4.1.3/1 Available Space Format 
 
 1116 baSlC "^ beMnd tMs f °™ at <OT« is to set aside an avail- 
 able space file in memory to be used in the construction and destruction of 
 list structures. Automatic allocation features of this file - when using 
 t e ava.lable space" format for the associated PR _ allov the progran J 
 to obtam empty cells and to discard unneeded cells. 
 
 An available space file may be divided up into two parts- a 
 section of list storage occupying the low address end of the file and a 
 sectxon of consecutive storage located in the high address end of the file 
 The l ls t storage part consists of a se q uence of cells; here the first 2 bytes 
 Of each cell contain the lin* to the next cell ^ ^ ^ ^ ^ 
 eventually contain data. The size of these two areas changes dynamically as 
 e fUe xs used. At the very beginning of use the file is completely made up 
 consecutive storage, but as more storage is needed for the linhed lists, 
 
 3/10/69 
 
 Section 2.4.1.3 - 1/h 
 
this area 
 
 is absorbed into the list storage area. Figure 2. U. 1.3/2 gives 
 
 an example of the appearance of the 
 
 list storage 
 
 file after it has been in use awhile. 
 
 consecutive storage 
 
 PR(NB): 
 
 (in "available space 
 format ) 
 
 Figure 2. U. 1.3/2 Available Space File 
 
 Referring to Figure 2. h. 1.3/2 whenever a list cell presently 
 assigned to a user is no longer needed bv the user (i.e. it is "popped" 
 off the user's list), it is placed on a special list (in the list storage 
 area) called the "free list". This list contains all the cells in the 
 list storage area which have been "freed" to be used as storage for other 
 UBtB The Pointer Register (in "available space" format) contains a 
 link to the top cell on this list so that all access to the free list is 
 m ade through the available space PR. In the example of Fxgure 2 U. .3/2 
 the free list link would equal the address of cell 5- Cells 5, 2, 1 
 7 are on the "free list". 
 
 Whenever data needs to be stored on one of the user lists in 
 the list storage area, the available space PR is modified so that xt xs 
 
 3/10/69 
 
 Section 
 
 2.U.1.3 - 2/U 
 
linked to the second available free list cell, and the top cell on the 
 free list can then be used to store the new data and its link. For 
 example in Figure 2.4.1.3/2 if a cell were needed by one of the user 
 lists, the free list link of the available space PR would be loaded 
 with the link portion of cell 5i i.e. the address of cell 2 in this case. 
 Then cell 5 could be used by the list which needed a new cell. 
 
 Only cells of one size may be placed in any given available 
 space file. The size of the cells in a given file is determined by a numb 
 initially placed in the leftmost halfword of the zeroth cell in the 
 file. (When using PRlU, the cell size is known to be k, so this latter 
 procedure is ignored. ) In general any even integer < 2% may be used 
 for the cell size (for other than PRlU) . This zeroth cell is never dis- 
 tributed since its address would conflict with the symbol for the end of 
 a list (i.e. link field of zero). Accordingly an available space pointer 
 is normally initiated with LINK = COUNT = cell size > 0. 
 
 But what happens if the free list is empty? To solve this 
 problem the last cell in the free list (# 7 in the illustration) has its 
 link pointing to the lowest addressed cell in consecutive storage. The 
 second two bytes of the available space PR (called the COUNT) also con- 
 tains this address, so that whenever the LINK equals the COUNT, the 
 free list has been exhausted. When this happens and a request for 
 another cell is received, the first cell of consecutive storage is used 
 and both the count and link are incremented by the number of bytes in the 
 cell. (However, if the assigned cell crosses or exceeds the segment 
 boundary, an Available Space Empty interrupt is generated. In this 
 latter case the count and link are not incremented, and therefore reflect 
 the arrangement of the available space at the time of the illicit memory 
 access . ) 
 
 3/10/69 
 
 Section 2.U.1.3 - 3/k 
 
As an example, in Figure 2. U. 1.3/2 if the free list became 
 exhausted, the LINK and COUNT would both be equal to the address of 
 cell 10. If a request for a cell were then made, cell 10 would be 
 given out and both LINK and COUNT would be incremented by the value 
 stored in the first half word of the zeroth cell. LINK and COUNT would 
 then point to the address of cell 11. 
 
 The count receives its name from the fact that it is the 
 number of cells (times the cell size) in the list storage area. When 
 the count equals the cell size, all storage is consecutive. (The zeroth 
 cell is dedicated to the cell size.) When the high order byte of the 
 count equals the address bounds of the segment all storage in the segment 
 is of the list type. 
 
 One precaution should he noted. Since a PR in available space 
 m0 de does not have a pointer stack of its own, it cannot he pushed into 
 one as a result a programmer must he extremely careful to avoid pushing 
 an available space format PB or drastic confusion may result. In general 
 there is nothing in the hardware to prevent this. However in the case of 
 PR#lH, an interrupt will be initiated. 
 
 Section 2.U.1.3 - h/k 
 U/18/69 
 
2.U.2 Pointer Registers - Functional Description 
 2.!+. 2.1 Pointer Register Storage 
 
 The Pointer Register contents, consisting of a link field, a 
 value field, and a segment name field (or link, count and segment name 
 fields in the available space format), are stored in two separate areas 
 of the TP mainframe. This is mainly because the use of segment names was 
 not developed until after the rest of the PR logic had been designed. 
 
 The first two PR fields are stored in storage blocks whose design 
 is explained in Section 2.2. Each PR has k storage bytes consisting of 8 
 data bits and 1 flag bit each. This PR storage is divided into two groups, 
 PRO through PR7 and PR8 through PRlU. Also contained in the second group 
 is the Spare Buffer Register (SBR), which is physically exactly like the 
 first k bytes of a PR. It is not treated as a PR, however. Instead it is 
 intended to be an additional storage register to be used by the TP control 
 unit. It is not accessible to the programmer. 
 
 As shown in diagrams 01-0, 01-2 and 01-3 of the TP Logic Book, 
 each group of PR storage is made up of k of the 9 bit/byte storage blocks 
 described in Section 2.2. Each of these blocks represents 1 byte position 
 of a PR. Since each 20^-00 circuit board contains 8 fast register flip-flops, 
 this allows 8 registers in each group. 
 
 The data input to the PR storage blocks consists of the Distribu- 
 tion Bus from the Permuter (DBP). The selection lines from the Pointer 
 Register Selection Logic operate the byte select lines to the byte select 
 drivers (BSD) in the blocks. For writing data into the PR's only the 
 "Gate Both In" option is used by the Input Gate Drivers (see Section 2.2.1). 
 This signal is controlled by DBPR/G and gates the Distribution Bus into the 
 PR storage flip-flops selected by the PR Selection Logic. The DBPR/G signal 
 is common to all 15 Pointer Registers. 
 
 5/15/69 Section 2.4.2.1 - 1/5 
 
The other control inputs to the PR storage blocks are WRPRL/E , 
 the write PR link field enable signal, and WRPRV/E , the write value field 
 enable signal. These signals are inverted and then become the Read/Write 
 input to the BSD's as described in Section 2.2.1. The WRPRL/E and WRPRV/E 
 are common to all 15 Pointer Registers in the two storage groups. 
 
 The data outputs of the two PR storage groups are dot or'ed 
 together to give a single output line in each position, called PRBAi . 
 This presents a minor problem since if both output gates in a given posi- 
 tion are activated with a read/write input of "0" , the group which does 
 not have a select signal activated will have as its output all zeros and 
 this will "erase" the output of the group desired. Therefore a means to 
 gate out only that group which has a word selected in it must be provided. 
 
 This means is provided by the PRTG/S and PR8G/S signals. They 
 arise in the PR Selection Logic. If one of the PR's to 7 is selected, 
 the PRTG/S is "1", enabling the proper group to be gated out. PR8G/S is 
 always the inverse of PR7G/S, so if one group is not in a "selected" state, 
 the other is. This selection need not be made for input gating since the 
 PR actually written into is controlled by the PR select input. 
 
 Only the "Gate False Out" signal is used in the PR storage blocks, 
 since an inverted signal is desired at the output. The method of choosing 
 the select lines is explained in Section 2.14.2.3. 
 
 The final PR field, the segment name, is stored in a special 
 block of IC storage. This storage block consists of l6 registers, each 
 16 bits long and is made up of SN?U75N quadruple bistable latch chips. 
 The storage itself is organized into subgroups of 8 registers x 2 bits, 
 as shown in Figure 2. k. 2.1/1. 
 
 The data input lines come from the IC driver extension of the 
 DB. The output of the segment name storage is the PR Segment Name Bus, 
 PRSNB, which leads to the association logic and can also be gated to the 
 PRB input to the permuter. 
 
 11/12/70 Sectl0n 2 - U - 2 - 1 " 2/5 
 
DATA OUT A 
 
 DATA OUT B 
 
 A 
 
 Mill 
 
 o 
 m 
 
 cr. 
 
 r 
 
 DATA 
 IN A 
 
 DATA 
 IN B 
 
 FOUR ITERATIONS 
 PER BLOCK 
 
 AAAAi 
 
 5o" 
 
 o 
 
 o 
 
 on 
 
 "1 
 
 o 
 
 o 
 
 _l 
 o 
 
 ZT 
 
 o 
 
 _l 
 o 
 
 o 
 
 c 
 
 c 
 
 _ 
 
 IT 
 N 
 <* 
 
 N 
 
 Z 
 
 ,9 
 
 WRITE 
 SELECT 
 
 READ 
 SELECT 
 
 Figure 2.U.2.1/1-PR Segment Name Storage Registers 
 
 (Block Includes 8 Registers x 2 Bits 
 and Read/Write Logic) 
 
 Section 2.4.2.1 - 3/5 
 
To select the desired register, the logic shown in Figure 
 2. k. 2.1/2 is used. When the PR Selection Logic determines the PR which 
 which is to he accessed (see Section 2.U.2.3), the proper selection line, 
 PRiTs, will be activated and can he gated into the PR Segment Name Register 
 Selector Logic by activating SNsTg. Then in order to read out the selected 
 Segment Name, SNRD/E must be set to 0. As shown in Figures 2. k. 2.1/1 and 
 2. U. 2. 1/2 this will activate one of the PSNRi/S lines which in turn will 
 cause the selected PR Segment Name Register to appear on the PRSNB. A 
 write can be performed by activating SNWT/E. 
 
 Note that tie selector is not attached to PR Segment Name Register 
 #15. Since there is no PR#15, this segment name register is used as temporary 
 storage by the Memory Sequence. It has independent read and write control 
 lines so that it can be operated without affecting the selector logic. 
 
 . ., Section 2.U.2.1 - U/5 
 
 5/12/69 
 
 
PSNRO/Sl 
 
 PSNRO/S2 
 
 PSNRW15 
 
 Figure 2.4.2.1/2 - PR Segment Name Register Selector Logic 
 
 Section 2.4.2.1 - 5/5 
 
2,1*. 2. 2 Pointer Register Control Registers 
 
 In using the Pointer Registers several additional control 
 registers are necessary: 15 Name Registers (NR's), 15 Shadow Name 
 Registers (SNR's), 15 one-bit Name Flag Registers (NFR's), the Tag 
 Register (TGR), and two counters (CCT and ACT). They are arranged as 
 shown in Figure 2.H.2.2 along with the Name Bus (NB) and the Shadow 
 Name Bus (SNB). All the registers (except for the NFR's), counters and 
 buses are h bits in length 
 
 The SNR's, NFR's, CCT, ACT and the SNB are used in the process 
 of name permutation whose explanation is deferred until Section U.2.4.3. 
 
 As mentioned previously, the Name Registers are used to hold the 
 current name for each PR. The PR's themselves each have a fixed, "wired-in" 
 name (0 through Ik) corresponding to the PR's position in the hardware. 
 Each physical position however, can be assigned, via the name registers, 
 any distinct name from to Ik by loading this name into the appropriate NR. 
 
 The Tag Register is used to store the tag portion of an operand 
 phrase. This gives the name which is to be searched for in the Name Registers, 
 
 The Name Bus is in reality the input to the compare circuit. The 
 
 compare circuit compares whatever is on the Name Bus with the contents of 
 
 the Name Registers and produces an output on one of 15 output lines corres- 
 ponding to the Name Register which matches the input. 
 
 5/19/69 Section 2.H.2.2 - 1/2 
 
TAG 
 REGISTER 
 
 (TGR) 
 
 4 bits 
 
 •- )SNB- 
 
 15 
 SHADOW 
 
 NAME 
 
 REGISTERS 
 
 (SNR) 
 
 15 
 NAME 
 REGISTERS 
 (NR) 
 
 13 
 
 n 
 
 13 • 
 
 NAME REGISTER 
 
 VS 
 NAME BUS 
 
 COMPARE LOGIC 
 
 13 
 
 
 FIGURE 2.4.2. 2 POINTER REGISTER CONTROL REGISTERS 
 
 5/16/69 
 
 Section 2.4.2.2 - 2/2 
 
2.1*. 2. 3 Pointer Register Selection Process 
 
 When a Pointer Register must be accessed, its name is to be 
 found in the tag portion of the operand phrase currently being decoded. 
 Therefore the first step in the PR selection process is to gate the tag 
 portion of the IR into the TGR where it is stored for possible later use. 
 
 The TGR is subsequently gated onto the Name Bus which is con- 
 nected to the NR/NB Compare Logic. This logic has as inputs the Name Bus 
 and the 15 NR's, and has as outputs, 15 select lines. The NB is com- 
 pared with the NR's and the matching register activates an output on the 
 select line corresponding to the physical PR with that name. For example, 
 suppose the operand wants the PR currently named #3. This value is gated 
 through to the NB and compared with all of the NR's. The NR with 3 as its 
 contents then indicates which PR is #3 at the present time by activating 
 the output line corresponding to that PR. If a match is obtained in none 
 or more than one NR, a malfunction has occurred since the names in the NR's 
 are supposed to be unique. 
 
 After the selected output line from the NR/NB Compare Logic is 
 activated it is then used to activate the proper PR select line which is 
 sent to the storage blocks and the segment name register selector and also 
 to indicate which of the two storage groups (0 through 7 or 8 through lU)PR is 
 in. This latter indication is of no importance when data is to be written into 
 the storage group, since the writing process depends only on the word selected 
 to be written into. On a read out, however, the output gates of the byte 
 storage group which does not contain the selected word must be inhibited; 
 otherwise, all zeros are output from this group. These zeros will in turn 
 override any data output from the other group containing the selected cell. 
 
 5//19 ^ 69 Section 2.4.2.3 - 1/2 
 
The logic here senses for a select signal to one of the 
 (physical) PR's 8 through lU and enables the output select gate from 
 that group. If one of PR's 8-lU is not selected, it is assumed that 
 one of through 7 is selected and that group's output gate is enabled. 
 The group selection signals are PR7G/S and PR8G/S which select registers 
 0-7 and 8-lU, respectively. In the rest, or inhibit, state, the PR8G/S 
 rests '1', or in the select mode. This corresponds to the group containing 
 the SBR. The select signal, when up, enables the output gates of the PR 
 group selected. If no word internal to the 9 bit /byte storage group is 
 also selected, the data output lines from the storage group will all 
 rest '0'. 
 
 When the Spare Buffer Register (SBR) is to be used, the output 
 selection signals from the NR/NB Compare Logic are inhibited so that no PR 
 select lines are chosen. Therefore PR8G/S is on and PR7G/S is off. This 
 causes the group containing the SBR to be chosen. The select signal for 
 the SBR is given by the TP Control. 
 
 
 . ,. Section 2.U.2.3 - 2/2 
 
 5/19/69 
 
2.U.2.U Tag Setting and Sensing 
 
 Sense logic driven by the TGR is used to sense the contents of the 
 TGR for PR#13. If PR#13 is selected (PR#13 corresponds to the Operand 
 Stack Pointer), it may be necessary to clear out or initialize the hard- 
 ware portion of the OS. This signal, N13S is routed back to the control 
 logic;when N13S goes to *1*, it indicates that PR#13 is being (or is to 
 be) selected. 
 
 When the TGR, or either of the counters for that matter, is not 
 selected to be gated onto the NB, the NB contains the number (name) 0000 
 (zero). This name corresponds to the instruction pointer register. Whenever 
 it becomes necessary to access the instruction pointer, it is only necessary 
 to inhibit the TGR to NB gating in order to select the PR named zero. Two 
 other control signals NPR13/S and NPRlU/S are used to force the names '1101' 
 (PR#13) and '1110* (PR#lU) onto the NB. Again in these cases, the TGR to 
 NB gate is inhibited when the names are forced on to the NB. This allows 
 PR#13, the OS pointer, or PR#lU, the Available Space Pointer, to be selected 
 without explicitly gating it into the TGR. 
 
 5/19/69 Section 2.U.2.U - l/l 
 

2.1+.3 Signal Name Lists for Pointer Registers 
 2.U.3.1 Control Signals 
 
 ACT/E/ 
 
 ANB/G 
 
 ASB/G 
 
 BSR1/G/ 
 
 BSR2/G/ 
 
 CCT/E/ 
 
 CEQA 
 
 CNB/G 
 
 CTSB/G 
 
 DBDR/G 
 
 INB1/G/ 
 
 INB2/G/ 
 
 IRTGO/G/ 
 
 IRTG1/G/ 
 
 IRTG2/G/ 
 
 NFCK/E/ 
 
 NFONE 
 
 NFR/G/ 
 
 NOS 
 
 N13S 
 
 NPR13/S 
 
 NPRlU/S 
 
 ACT enable count (ACT = ACT +1) 
 
 ACT-» NB gate 
 
 ACT -* SNB gate 
 
 interrupt recovery - load higher SNR's from DB 
 
 interrupt recovery - load lower SNR's from DB 
 
 CCT enable count (CCT = CCT + l) 
 
 output - value of CCT = value of ACT 
 
 CCT -♦NB gate 
 
 CCT -» SNB gate 
 
 DB -¥ PR storage blocks 
 
 interrupt save - gate lower SNR's onto BR0S 
 
 interrupt save - gate higher NR's onto BR0S 
 
 interrupt save - tag field in byte 
 
 gate the IR->TGR, tag field in byte 1 
 
 gate the IR -» TGR, tag field in byte 2 
 
 name flag check enable 
 
 output - name flag of SNR indicated by NB is = 1 
 
 gate name flag register, i.e. set name flag register 
 
 indicated by NCE. 
 
 Output - set to 1 if TGR = (i.e. if instruction 
 
 pointer is selected) 
 
 Output - set to 1 if TGR =13 (i.e. if 0S pointer 
 
 is selected) 
 
 Load NB with +13 (i.e. the operand stack pointer 
 
 number) 
 
 Load NB with +lU (i.e. the available space pointer 
 
 number) 
 
 1/1/69 
 
 Section 2.U.3.1 - 1/2 
 
PSNRi/Sl - 
 PSNRi/S2 - 
 
 PSNRR15/ - 
 PSNRW15/ - 
 PSNWi/Sl - 
 
 PSNWi/S2 - 
 
 RACT 
 
 RCT 
 
 RNFR 
 
 RSNR/ 
 
 SBR/S 
 
 SBSR/G/ - 
 
 SNNR/G/ - 
 SNRD/E/ - 
 SNS/G/ 
 
 SNWT/E/ ■ 
 
 TNB/G 
 
 TSB/G 
 
 WRPRL/E 
 
 WRPRV/E 
 
 WSBV/E 
 
 PR Segment Name Register - Read Select Register i, 
 
 Signal 1 
 
 PR Segment Name Register - Read Select Register i, 
 
 Signal 2 
 
 PR Segment Name Register #15 - Read 
 
 PR Segment Name Register #15 - Write 
 
 PR Segment Name Register - Write Select Register i, 
 
 Signal 1 
 
 PR Segment Name Register - Write Select Register i, 
 
 Signal 2 
 
 Reset auxiliary k bit counter (ACT) 
 
 Reset k bit counter (CCT) 
 
 Reset all name flag registers 
 
 Reset all Shadow Name Registers to 
 
 Spare "buffer register select 
 
 Gate SNB-» SNR(i) where i is given by NCE which 
 
 is on 
 
 SNR-»NR gate - (all registers whose name flags = l) 
 
 Enable PR Segment Name Register Read 
 
 Gate PR Select Signals, PRi/S/ , into PR Segment 
 
 Name Selector Logic 
 
 Enable PR Segment Name Register Write 
 
 Gate the TGR -» NB 
 
 Gate the TGR -* SNB 
 
 DBP-* pointer link field selected by PRS's 
 
 DBP-*SBR link field if SBR/S is on 
 
 DBP-* SBR value field if SBR/S is on 
 
 7/7/69 
 
 Section 
 
 2.1+.3-1 - 2/2 
 
2.U.3.2 Internal Signals Used by Pointer Registers 
 
 ACTi 
 BR0Si 
 
 CCTi 
 
 DBi 
 
 DBPi 
 
 NBi 
 
 NCEi 
 
 NFRi 
 
 NjRi 
 
 PRBi 
 
 PRi/S/ 
 
 PR7G/S 
 
 PR8G/S 
 
 PRSNBi 
 
 PSNAi 
 
 PSNbi 
 
 SNBi 
 
 TGRi 
 
 Auxiliary h bit counter - bit i 
 
 Base register - Operand Stack bus bit i - to 
 
 empty NR's 
 
 h bit counter - bit i 
 
 Permuter Output Bus - from DBP - ith bit 
 
 Permuter Output Bus - directly from Permuter - bit i 
 
 Name Bus - bit i 
 
 Name Compare Equal for ith register - i.e. NB = value 
 
 in ith NR 
 
 Name Flag Register - bit i 
 
 jth name register - ith bit 
 
 Pointer Register Bus output - bit i 
 
 Pri has been selected 
 
 PR selected belongs to PR's through 7 
 
 PR selected belongs to PR's 8 through lU or SBR 
 
 PR Segment Name Register Output Bus, bit i 
 
 PR Segment Name Register, Out bus A, bit i 
 
 PR Segment Name Register, Outbus B, bit i 
 
 Shadow Name Bus - bit i 
 
 Tag Register, holds tag from IR - bit i 
 
 6/18/69 
 
 Section 2.U.3.2 - l/l 
 

2.U.U Pointer Registers - PL/I Description 
 
 // FXFC PL1 
 
 //(■'L 1 .SYSPDNCH mi SYSOUT*ft 
 
 //PL 1. SYS I M no * 
 
 pregin: ppoci 
 
 actf, anbg, asrgt cctf, ceqa» cmbg, 
 ctsbg, imm, inr1g, inb2g, n13sf nfckf, 
 
 NFflMF, NFRG, NPR13S, MPR14S» RACT, RCT, 
 RN'FR, RSNR, SBRS, SBSRG, S^NRG, TGIM, 
 TNBG, TSBG, IRTGG, PSMPRBG): 
 
 OCL( ACTF, ANBG, ASBG, CCTF, CFOA, 
 CNBG» CTSHGt IMM, INB1G, INB2G, M 13 S , 
 MFCKF, MFOMF, NFRG, MPR13S, NPR14S, RACT, 
 RCT, RNFR, RSNR, SBRS, SBSRG, SMMRG, 
 TGIM, TNBG, TSBG) B I T ( 1 ) , I R TGG ( : 2 ) RIT(l); 
 
 OCL PSMPRBG HIT ( 1 ) ; 
 OCL AOOl FNTRY( (4)RIT( 1 ) ) EXTERNAL; 
 
 OCL( (ACT,CCT,TGR) (4), NFR(0:14), ( BROS , I R t PRB , SBR ) ( 36 
 PRS(0:14), (NR,SNR) (0:14,4) , PR(0:14,36)) BIT(l) 
 
 external; 
 
 OCL MCE (0:14) BIT(l), 
 (MB, 
 SMB 
 
 ) (4) BIT( 1 ) , 
 ( PR7GS, 
 PR8GS 
 
 ) BIT ( 1) , 
 ( I , J ) FIXFO BIN; 
 
 /* SFT U P CniJMTFRS */ 
 
 IF RCT THEN CCT='0'B; 
 
 IF PACT THFM ACT='0'B; 
 
 IF ACTF THEM CALL AOOl (ACT); 
 
 IF CCTF THEM CALL AODKCCT); 
 
 nn i=i. in 4; 
 
 IF ACT( I )i=CCT( I ) THFM GO TO SKI PI; 
 
 F N ; 
 CFOA= • 1 • B; 
 
 .-■;-. i _,-ian MAMF BUS AND/OR SHAOOW MAMF BUS */ 
 C K i pi :mh , SNB=' O'B; 
 IF IRTGG(O) THEN 
 
 00 1=1 TO 4; 
 TGR( I ) = IR( I ) ; 
 TGIM=IR(8) 6 1 MM; 
 ENO; 
 I F IRTGG( 1 ) THFM 
 
 nn I = 1 TO 4; 
 TGR( I ) = IR( 1+9 ) ; 
 TGIM=IR( 17) SIMM; 
 END; 
 IF IRTGG(2) THEN 
 
 nn i= i tu 4; 
 
 TGR( I)=IR(I+18); 
 TGIM=IR( 26 )RIMM; 
 
 END; 
 IF TNBG THFM MR=TGR; 
 IF ANBG THEN NB=ACT; 
 
 II/5/7O Section' 2 . U, 4 - 1/3 
 
IF CM8G THEM NB=CCT; 
 IF TSBG THEN SNB=TGR; 
 IF ASBG THEN SNB=ACT; 
 IF CTSBG THEM SNB=CCT; 
 IF NPR13S THEN DO; 
 
 NB='l • B; 
 
 MB( 3)= , , B; 
 
 END; 
 IF MPR1AS THEN DO; 
 
 nn 1=1 to 3; 
 
 MB( I ) = • l'B; 
 end; 
 
 MB ( 4 ) = • ' B : 
 
 IF fr,*(l)RTGR(2)B-»Tr,R(3)GTGR(4) THEN N13S='l'B; 
 
 ELSE N 1 3 S = ' • B ; 
 
 /* COMPARE NAME BUS *IITH EACH REGISTER */ 
 
 nn i=o to ia; 
 
 NCF( I ) = •()' B; 
 nn j=i Tn 4; 
 
 IF MR(I,J)-=NB(J) THEM GO TO N0TF0; 
 
 E n n ; 
 
 MCF( I ) = ' 1 'b; 
 NOTEO : END ; 
 
 /:■, SFT up POINTER SFI.FCT SIGNALS */ 
 II- SBKSIPSNPRBG THEN PRS='0'B; 
 
 ELSE PRS=MCF; 
 
 />. qhFCK FOR MAMF FLAG RESETS */ 
 IF KNFR THEN NFR='0'B; 
 
 /:;; chFCK FOR GATING IN NAME FLAG REGISTER */ 
 j F MPRr-, thfm nn 1=0 TO 14; 
 
 IF MCF ( I ) THEN MFR ( I )= ' 1 ' B; 
 
 E\in; 
 
 / •-;= C H F C K MAMF FLA G * / 
 
 N F M F = • 1 ' B ; 
 
 IF MFCKF THFM 110 1=0 TO 14; 
 
 IF NCF ( I )f.MFR( I ) THEN NEONE='0'B; 
 
 FMO; 
 /:;: SFT up GROUP SFLFCT SIGNALS */ 
 PRRGS= ' O'B ; 
 \y) \=H TO 14; 
 
 I F MCF( I ) THEM PRBGS=' 1 'B; 
 
 f n o ; 
 IP SBRS THFM prsgs='1 , b; 
 PK7GS = -«(PRHGS ) ; 
 
 /* GATF POINTER TO POINTER BUS AS OUTPUT */ 
 if PR7GS them nn 1=0 TO 7; 
 
 IF PRS(I) THEM PRB(*)sPR( It *) S 
 
 F m n ; 
 
 IF PR8GS THFM 00; 
 
 nn i=b to 14; 
 H/5/70 Section 2.k.h- 2/3 
 
IF PRS( I ) THEM PRB(*)=PR (I,*); 
 FNin; 
 I F SBRS THEN PRR = SBR ; 
 END; 
 
 /* INTFRRIIPT RliS */ 
 
 IF IN81G then nn 1=0 TO 3; 
 
 on j=i to 4; 
 
 8R0S( I#9 + J )=NR (2*1 , J ) ; 
 
 bros(i*9+j+4)=nr(2*i+i t j); 
 
 EMO? 
 
 ENO; 
 IF INR2G THFN 00 1=0 TO 2; 
 
 DO J=l TO 4; 
 
 BRITS ( 1*9 + J )=NR (2*1+8, J ) ; 
 BRnS(I*9+J+4)=NR(2*I+9,J); 
 END; 
 
 DO J=l TO 4; 
 3R0S(27+J)=NR< 14, J ) ; 
 BRnS(31+J)=«0 , B; 
 END; 
 FND; 
 
 /* CHECK FOR RFSFT DF SNR */ 
 IF KSMR THEM SMR='0'B; 
 
 /•: CHFCK FOR GATIMG(SMB TO SNR)'*/ 
 It- SBSRG THEM OH 1=0 TCI 14; 
 
 IF MCE(I) THEN SNR ( I , * ) =SNB ; 
 
 FNO; 
 
 /■ CHFCK FOR SMR TO MR * / 
 
 if snmrg thfm nn i=n Tn 14; 
 
 IF MFR(I) THFM MR ( I , * ) =SNR ( I , * ) ; 
 END? 
 
 F • '■' P^FGI N : 
 
 11/5/70 
 
 Section 2.k.k - 3/3 
 

 
 
2. 5 Base Registers 
 
 The Base Registers (BR's) are used as a part of the memory 
 
 accessing scheme to contain information about the segments of the 
 
 Ik 
 
 current process. Up to 2 segments are allowed the programmer. But 
 
 as there are only 7 usable base registers, only the data on the 7 most 
 recently used segments is held within the TP. The remaining segment 
 base information is retained in memory in the Segment Name Table of the 
 current process. BR's 1 through 7 are used to address recent data. BR#0 
 is used to indicate the Segment Name Table. 
 
 To identify which segments have their bases in the TP, each 
 base register (other than BR#0) has an associative register assigned to 
 it which contains the name of the segment currently in that base register. 
 When a PR is selected as an address of a cell to be accessed from memory, 
 its segment name register is associatively compared with the associative 
 registers for each base register. If a match is found, the matching base 
 register will be used. If there is no match, the required base data will 
 be accessed from the Segment Name Table. 
 
 In order to completely determine a file, the base register must 
 
 1) a base address which indicates where the file storage 
 begins. (in Partitioned Mode the base address is the 
 address of the page map - see Section k. 1.3.2). 
 
 2) a bounds, which indicates how many pages have been assigned 
 
 3) a code bit to indicate the Data Access Mode (Contiguous or 
 Partitioned), and 
 
 h) two other code bits to determine the level of Accessing 
 Privilege (read-write, read only, trap, or no access). 
 
 contain : 
 
 3/12/69 
 
 Section 2.5 - 1/2 
 

 The base address uses a 16 bit page address which represents 
 the upper 16 bits of a normal 2k bit address. The rightmost 8 bits of 
 the corresponding absolute address are always taken to be zeros. The 
 bounds is an 8 bit quantity allotting the user a specified number (up 
 to 256) of pages of memory for this file. These two quantities are 
 placed in a 3 byte BR with the bounds in the leftmost byte, the base 
 address in the rightmost 2 bytes, as shown in Figure 2.5/1- The Data 
 Access Mode bit is in the flag position of the leftmost byte and the 
 Accessing Privilege bits are in the flag positions of the 2 rightmost 
 bits. How these various quantities are used is explained in Section k.l 
 on Memory Accessing. 
 
 Since the base information controls where and how a user may 
 access the memory, users must he prevented from changing the contents of 
 any BR. For this reason instructions which change the value of any portion 
 of a BR are considered "privileged" and may only he used hy the supervisor 
 routine. 
 
 Data Access 
 Mode Bit 
 
 Accessing Privi- 
 lege Bits 
 
 D 
 
 bounds 
 
 
 
 page address 
 
 D 
 
 n 
 
 Figure 2.5/1 - Base Register Format 
 
 
 5/16/69 
 
 Section 2.5 - 2/2 
 
2.5-1 Base Register Functional Description 
 
 The Base Register Logic is shown in block diagram form in Figure 
 2.5-1. In a memory access a pointer register will be selected and one 
 of the segment name registers will be gated out to the PRSN bus. This 
 is then associatively compared with all of the Associative Registers. 
 If there is a match, the corresponding BR select line will be activated 
 and the proper Base Register will be read out onto the BROS bus. If 
 there is no match, a special control sequence will be entered to access 
 the Segment Name Table for the proper base information. This data is 
 then stored in the base register which has been "inactive" for the longest 
 amount of time. This choice of BR is made by the Queue Counter Logic 
 (Section 2.5-1.2). 
 
 3/12/69 Section 2.5-1 - 1/2 
 
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2.5.1.1 Base Register Storage 
 
 The Base Register storage is made up of the same type of 
 storage blocks as the Operand Stack and the Pointer Register, i.e. 9, 
 201+-00 circuit boards driven by 2, 205-00 circuit boards. The BR 
 storage consists of k blocks arranged as shown in Drawing Number 01-1 
 of the TP Logic Book. (For a detailed description of these blocks - 
 see Section 2.2). 
 
 Because of the fact that the BR's are only 3 bytes long, they 
 are staggered in their arrangement in the k subgroups. This arrangement 
 is shown in Figure 2. 5 .1.1, where BRij indicates the position of the jth 
 byte of the ith Base Register. Each Base/Bounds register is a 3 byte unit 
 and the Byte Select inputs are common in 3 byte groups. Note that in this 
 arrangement, there are 8 bytes of storage which remain unused. As will be 
 explained later (in Section 2.6), these are used for the Instruction Buffer 
 Register (IBR). 
 
 The inputs to the Base Register storage group consist of the 
 Distribution Bus from the Permuter (DBP), the Base Register select lines, 
 and read/write control lines. The Base Register select lines are connected 
 to the word select inputs of the storage block Byte Select Drivers (BSD). 
 The write operation takes two control lines ,DBBRS/G/ to gate the DBP to the 
 inputs of the flip-flops and WRBR/E which puts the selected flip-flops in 
 the "write in" state so that they will accept the data gated in. The 
 WRBR/E signal connects by means of an inverter to the read/write input of 
 the BSD while the DBBRS/G/connects directly to the "Gate Both In" line of 
 the Input Gate Drivers. 
 
 Previous to gating the data into the flip-flops, the Permuter is 
 used to shift the data so that when it is placed on the DBP, its boundaries 
 will coincide with those of Figure 2.5.1.1. 
 
 3/12/69 Section 2.5-1.1 - 1/2 
 
Group 
 
 BR01 
 BR12 
 BR23 
 BRUl 
 BR52 
 BR63 
 
 Group 1 
 
 BR02 
 BR13 
 BR31 
 BRU2 
 BR53 
 BRT1 
 
 Group 2 
 
 BR03 
 BR21 
 BR32 
 BRU3 
 BR6l 
 BRT2 
 
 Group 3 
 
 BR11 
 BR22 
 BR33 
 BR51 
 BR62 
 BRT3 
 
 RESERVED FOR INSTRUCTION BUFFER 
 
 REG. 
 
 Figure 2.5-1.1 Arrangement of Base Registers 
 
 The output of the BR Storage Group is the Base Register-Operand 
 Stack Bus (BROS). When the BRBSP/G signal, which is connected directly to 
 the "Gate False Out" input of the Output Gate JDrivers , is activated, the inverte 
 contents of the selected BR is gated to the BROS. The data, at this point, 
 is still in the position given in Figure 2.5-1.1. The Permuter can then 
 be used to shift it so that it is delivered to the DB, left justified. 
 
 11/5/70 
 
 Section 
 
 2.5-1.1 - 2/2 
 
2.5.1.2 Associative Register Storage 
 
 The Associative Register Storage "block is completely made 
 up of IC chips. It consists of 7 registers each containing 16 bits, 
 along with the appropriate input and output gating. An example of one 
 register is shown in Figure 2.5.1.2/1. 
 
 Each Associative Register itself is made up of four SN7I+75 
 quad bistable latch chips. The input data comes from the DBB bus which 
 is merely an extension of the DB bus into the IC logic part of the 
 machine. The input gating signals are generated by 2 NOR circuits 
 whose outputs go to 1 when the inputs, ASRW/E and RBRi /S , go to zero. 
 ASRwZe is the main signal for writing data into an Associative Register. 
 RBRi /S is a select signal generated by the Queue Counter logic (see 
 Section 2.5.1.3). It selects the particular Associative Register to be 
 written into. 
 
 Under normal program control there is never any need to read 
 out the contents of an associative register since these registers are 
 only used in comparisons with the PR Segment Name Bus. When a task is 
 removed from a TP the Associative Register contents are simply abandoned 
 by setting all of the OK bits to zero. 
 
 It is necessary, however, for the Engineering Console (see 
 Section k.T) to be able to display the contents of these registers. For 
 this reason the Associative Registers have output gates which allow a 
 selected register to be gated on to the PRSNB bus and from there to the 
 PRB bus and the Permuter input gate. 
 
 11/5/70 Section 2.5.1.2 - l/l 
 
2.5.1.3 Queue Counters 
 
 The Queue Counters are used to keep track of which base 
 register has not been used for the longest length of time. The queue 
 counter logic provides a series of output signals (REPLACE SELECT i) 
 which indicate which associative register has not been in use for the 
 longest period. 
 
 The overall idea is to use 3 bit counters to indicate a base 
 register position in a service queue from to 6. The register labeled 
 is that register most recently accessed, while the register labeled 6 
 was used least recently. Each time a memory access is performed (and 
 the segment name is among those currently in the associative registers), 
 the counter corresponding to the associative register is set to zero, 
 and all the counters with counts less than the previous contents of the 
 selected counter are incremented by one. This ensures that the order in 
 the queue will always be in the order of most recent usage. Therefore 
 the least recently used associative register will always have a counter 
 containing a 6. 
 
 11/5/70 Section 2.5.1.3 - l/k 
 
The detailed logic of the Queue Counters is shown in Figure 
 2. 5.1. 3. /I. Operation is as follows. 
 
 Each counter has an overflow detector in the form of a flip- 
 flop. After a base register-associative register combination has been 
 selected, all of the 3 bit queue counters are incremented one count at 
 a time until the counter corresponding to the selected register overflows. 
 At this point an extra count is added to all counters whose overflow flip- 
 flops are still off. Then the count pulses are continued until the total 
 number of pulses, not counting the extra pulse, is 8. All counters with 
 numbers . the count in the selected base register have now returned to 
 their initial value, while those with initial counts the selected count 
 have been incremented by 1. Also all overflow flip-flops are now on. 
 The overflow flip-flops are now reset by inserting a common 
 count pulse into each overflow flip-flop. Finally the selected counter 
 is reset to zero. An example of the counting is shown in Figure 2.5-1.3/2. 
 
 For the queue counters to function properly each counter must 
 initially contain a distinct number from to 6 inclusive. Therefore at 
 turn-on a special sequence must be performed to ensure that this condx- 
 tion is met. Once the counters have been set up, however, they will 
 continue to operate properly as long as no hardware error occurs. 
 
 The setup process is quite simple. It consists of using the 
 cycle counter to select each queue counter in turn to be reset. Between 
 each reset, all the queue counters are incremented once. Thus after 7 
 cycles there will be one counter with each number from to 6. The 
 logic is given in TP Logic Book, Drawing No. 23-3. 
 
 , , Section 2.5.1-3 - 2/U 
 
 11/5/70 
 
:nt/e qcnt/e 
 
 SOCTOV 
 
 RSCTR/S 
 
 RQOVF/S 
 
 BR7/S 
 
 Figure 2. 5.1. 3 A - Queue Counters 
 
 11/5/70 
 
 Section 2.5-1.3 - 3/k 
 
Contents 
 
 of 
 Counters 
 
 
 
 Counter of 
 Selected — * 3 
 Associa- 
 tive h 
 Register 
 
 5 
 
 1 
 2 
 3 
 
 k 
 
 5 
 6 
 
 Count Cycles 
 3 U 5 X 6 7 8 
 
 h 5 6 7 0* 1 
 
 5 6 T 0* 1 2 
 
 6 7 0* 1 2 3 
 T 0* 1 2 © 
 
 2 3 
 
 3 h 
 h 5 
 5 6 
 
 67 0* 1123^ 
 7 0* 1223^5 
 
 This is then reset to 0, 
 * = overflow 
 X = extra count 
 
 7 0* 1 
 
 3 U 
 
 Figure 2.5.1.3/2 Operation of the Queue 
 
 Counters : An Example 
 
 11/5/70 
 
 Section 2.5.1. 3 " ^ /U 
 
2.5.1.1* Association Logic and Associative Registers 
 
 The Association Logic compares the contents of the PRSNB bus 
 with each of the Associative Registers "connected" to the BR's. It is 
 conceptually similar to the comparison logic for matching the Name Bus 
 with the Name Registers in the Pointer Register logic. The Associative 
 Registers however are 16 bits long while the Name Registers are only k 
 bits in length. 
 
 The association logic is shown in Figure 2.5.1.3/1. The OKn 
 signal comes from a flip-flop attached to the particular association 
 register which indicates that the data in the register is valid. Thus 
 all that is needed to "empty" the registers is to set the seven OK flip- 
 flops to 0. 
 
 11/13/70 Section 2.5-l.U - 1/2 
 
figure 2.5.1.V1 
 
 ASSOCIATION LOGIC FOR ASSOCIATION REGISTER i 
 
 11/13/70 
 
 Section 2.5-l. 1+ - 2/2 
 
2.5.2 Signal Name Lists for the Base Registers 
 2.5.2.1 Control Signals 
 
 ASRiW/El 
 ASRiW/E2 
 ASRW/E 
 
 BRG/S 
 
 BRi/S/ 
 
 BRRi/S/ 
 
 BRQi/S 
 
 BRSBP/G/ 
 
 BRSS/G 
 
 CYC6 
 
 CYC^V 
 
 CYCT/E 
 
 DA 
 
 NYET 
 
 QCNT/E 
 
 QSETUP 
 
 RBRi/s/ 
 
 RCYCT/S 
 
 RPBR/E 
 
 RQ0VF/S 
 
 RSCTR/S 
 SNS/G 
 SQCT0V 
 XQCNT/E 
 
 Associative Register i, write enable 1 
 11 if 11 11 11 o 
 
 Associative Register write enable. Enables Associative 
 
 Register selected by RBRi/S signals. 
 
 Select BR portion of BR-IBR storage block. 
 
 Select BRi in BR-IBR storage block. 
 
 BRi was selected by association logic 
 
 Select BR Queue counter i 
 
 Gate base register storage to BROSi according to BRi/S signals 
 
 Gate BRNi/S signals to BR Queue counter select register. 
 
 Output Signal - cycle counter equals 6. 
 
 Output Signal - cycle counter overflow 
 
 Enable count of +1 on cycle counter. 
 
 Output signal - a match between PRSNB and an associative 
 
 register has been made. 
 
 Output signal - no match between PRSNB and an associative register 
 
 Enable count of +1 on all Queue counters 
 
 Turned on during initial Queue counter set up procedure. 
 
 Select BRi for reloading 
 
 Reset cycle counter 
 
 Enable the replacement of the BR selected by the RBRi/S signals 
 
 Reset overflow bit on Q counters. This signal only works if 
 
 all overflow bits are on. 
 
 Reset selected Q counter 
 
 Gate PR Select Signals into select register 
 
 Overflow by counter selected by BRi/S 
 
 Enable extra count of +1 for all Queue counters with their 
 
 overflow bit off 
 
 11/5/70 
 
 Section 2.5-2.1 - 1/1 
 

 
 
2.5.2.2 Base Register Control - Internal Signals Used by the Base Regi:;t'jr:; 
 
 CMAi/ 
 
 CMBi/ 
 
 CMCi/ 
 
 CMDi/ 
 
 BR/Si 
 
 DBBi 
 
 DBPi 
 
 OKi 
 
 PRSNBi 
 
 Compare result of first quarter of associative register i with 
 PRSNB. Set to if equal. 
 
 Compare result of second quarter of associative register i with 
 PRSNB. Set to if equal. 
 
 Compare result of third quarter of associative register i with 
 PRSNB. Set to if equal. 
 
 Compare result of fourth quarter of associative register i 
 with PRSNB. Set to if equal. 
 
 Output bus for Base Registers and Operand Stack. 
 
 Permuter Output Bus used by control logic. Logically equivalent 
 to DB, but produced by IC drivers, bit i 
 
 Permuter Output bus direct from Permuter. 
 Associative Register i contains valid data. 
 PR Segment Name Bus - bit i. 
 
 11/5/70 
 
 Section 2.5.2.2 - l/l 
 
2.5.3 Base Registers - PL/1 Description 
 E X 6 C P L 1 
 
 [■ACL CI. I 
 
 Ptl .SYSPUNCH DD SYSniJT = B 
 PL1. SYSIN DD * 
 
 BRFGIN: PROC(BRGS, BRSSG, CYC6, CYCOV, CYCTF, 
 DA, NYFT, PSNRR15, PSNRW15, QCNTF, 
 OSETUP, RCYCTSr RDBRF, RPBRF, RODVFSt 
 SNRDE, SNSG, SNWTF, SOTOV, WRRRF, 
 XOCNTF, BR S» PSNPRBG); 
 OCL(BRGS, BRSSGt CYC6, CYCOV, CYCTF, DA, 
 
 NYET, PSNRR15t PSNRW15, QCNTF, OSETI)P t 
 RCYCTS, RDBRE, RPBRFt RQOVFS, SNRDF, 
 SNSG, SNWTE, SQTOVt WRBRE, XQCN1 F ) 
 B I T { 1 ) ; 
 DCL PSNPRBG BIT ( 1 ) ; 
 OCL AOD1 EIMTRY( (4) BIT(l)) EXTERNAL; 
 OCL PRB(l:36) BIT(l) EXTERNAL; 
 
 DCU ASRG(7,18), BR<0:7,36), BROS(36), CYCTR(4), 
 QC0UNT(7,4) ,PRSNB( 1 : 36 ) ,PRSNR(0: 15, 18 ) , 
 ( PR S,PSNRS1,PSNRS2,PSNWS1,PSNWS2, SNSRG) (0:15), 
 (RRCS,BROS ,BRRS,BRWS,CMA,CMB,CMC,CMD,OK,RBRS ) 
 
 (0:7)) BIT ( 1 ) EXTERNAL; 
 DCL BRS(0:7 ) BIT ( 1 ) ; 
 PCL ( PSNA,PSNB) ( 1 : 17) BIT(l), 
 C00NTFR(4) BIT ( 1 ) , 
 (X,I,J) FI XFD bin; 
 DCL BRSRFG(0:7) RIT(l) EXTERNAL; 
 
 /* TORN ON ASSOC IATIVF LOGIC CONTROL SIGNALS */ 
 
 RPBRE=BRGSGWRBRE; 
 RDBRE = BRGSG-.WRBRF; 
 
 BRSSG=RDBRE ; 
 
 /* GATE PR SELECT SIGNALS INTO SELFCT REGISTFR SNSRG */ 
 
 IF SNSG THFN SNSRG=PRS; 
 
 IF SNRDE THFN 00 1=0 TO 14; 
 
 PSNRS1 ( I ) ,PSNRS2( I )= SNSRG ( I ) ; 
 END; 
 IF SNWTE THEN 00 1=0 TO 14; 
 
 PSNWS1(I),PSNWS2(I )= SNSRG ( I ) ; 
 END; 
 PSNRS1 ( 15) ,PSNRS2 ( 15)=PSNRR15; 
 PSNWS1(15),PSNWS2(15)=PSNRW15; 
 
 PSNA ,PSNB= ' O'B ; 
 
 00 J=l TO 8; 
 
 DO 1=0 TO 7; 
 
 PSNA( J )=PSNA( J) | (PSMRSK I ) EPRSNR ( I , J ) ) ; 
 END; 
 DO 1=8 TO IS; 
 
 PSNB(J)=PSNB(J) | (PSNRS1 ( I )£PRSNR< I , J ) ); 
 END; 
 END; 
 
 H/5/70 Section 2.5.3 - lA 
 
nn j =10 to 17; 
 
 ~PSNA(J)=PSNA(J) I <PSNRS2(I)£PRSNR(I»J)> ; 
 
 END; 
 
 D ° I= PSNB(J)=PSNB(J)I (PSNRS2U ) f.PRSNR ( I , J ) ) ; 
 
 end; 
 end; 
 
 /* PR SEGMENT NAME REG OUTPUT BUS */ 
 
 Dfl 1 = 1 TO 17; 
 
 PRSNB( I )=PSNA( I ) |PSNB( I ) ; 
 
 end; 
 
 IF PSNPRBG THEN PRB=PRSNB; 
 
 /* fDMRARE THE A QUARTERS OF EACH ASSOCIATIVE REGISTER WITH 
 THE RESPECTIVE QUARTERS OF PRSMB. IE THE QUARTERS MATCH, SET 
 THF RESPECTIVE CM SIGNALS TO 1 */ 
 
 CMA,CMB,CMC,CMD=« l'B; 
 
 DO 1=1 TO 7; 
 
 DO J =1 TO A; 
 
 IF PRSNR(J)-. = ASRG(I,J) THEN CMA(I) = , 0'B; 
 
 end; 
 
 nn j=s to 8; 
 
 IF PRSNB(J)-=ASRG( I, J) THEN CMB(I)='0«B; 
 
 END; 
 
 DO J = 1 TO 13; 
 
 IF PRSNB(J)-=ASRG(I,J) THEM CMC(I)='0'B; 
 
 END; 
 
 DO J = 14 TO 17; 
 
 IF PRSNB(J)-=ASRG(ItJ) THEN CMD(I)='0'B; 
 
 END; 
 E N D ; 
 
 /* BASF REGISTER SELECT SIGNAL DRIVERS */ 
 
 brp-s=' O'B; 
 B R W S = ' ' B ; 
 IF rpbRE THEN DO I = 1 TO 7; 
 
 BRWSt I )=RBRS( I ) ; 
 
 end; 
 if rorpf thfn do 1=1 to 7; 
 
 BRRS(I)=OK(I )6CMA( I )&CMB( I KCMCd )6CMD(I )? 
 
 END; 
 /^--CALCULATE BRCS WHEN IMPLEMENTFD *l 
 
 B R S = ' ' B ; 
 IF BRGS THEM DO 1=1 TO 7; 
 
 BRS( I )=BRRS( I ) |BRWS( I ) ; 
 
 end; 
 
 /* BRSREG IS THE REGISTER ON DRAWING 23-3 */ 
 IF BRSSG THFN BRSRFG=BRRS; 
 
 
 11/5/70 
 
 Se 
 
 ction 2.5.3 - 2/h 
 
/* CYCTR IS THE 4 BIT COUNTFR (IN DRAWING 23-3 */ 
 
 IF CYCTF THEN CALL ADD 1 ( CYC TR ) ; 
 IF KCYCTS THFN CYCTR='0'B; 
 CYCOV= '0' ft; 
 IF CYCTR(l) THEN CYC0V='1'B; 
 
 /* nECnOF VALUE IN CYCTR-*/ 
 
 x = o; 
 
 IF CYCTR (2 ) THEM X=X+4; 
 
 IF CYCTR(3) THEN X=X+2; 
 
 IF CYCTR(4) THEM X=X+1; 
 
 CYC6= 'O'B; 
 
 IF X = 6 THEN CYC<S= • 1 ' B; 
 
 IF QSETUP THEN BRQS( X+l ) = • 1 • B; 
 C LSF DO 1=1 TO 7; 
 
 BROS( I )=BRSREG( I ) ; 
 END; 
 
 /* (JCniJNT ( I ♦ J ) IS THE ITH COUNTER JTH BIT UF THE IMTFRNAL 
 COUNTFRS f IN DRAWINGS 23-1,2 */ 
 
 IF ROOVES THEN DO 1=1 TD 7; 
 
 OCOUNT( I , 1 )=-.OCOtJNT< 1,1) ; 
 
 END; 
 
 /* INCREMENT COUNTERS AMD CALCULATE RBRS(I) SIGNALS */ 
 
 DO 1=1 TO 7; 
 
 IF (QCNTE I ( XOCNTEE-.OCOUNT( I ,1 ) ) ) THEN DO; 
 
 COONTER=OCODNT( I , * ) ; 
 
 CALL ADD1 (COUNTER ) ; 
 OCOUMT( I f * )=COUNTER ; 
 END; 
 
 RBRS ( I )=-iQCOUNT( 1,4) GOCOUNK I ,3 ISOCOUNT ( 1,2 ) ; 
 
 END; 
 
 /* CHECK IF COUNTER SELECTED BY BRS(I) HAS OVERFLOWED */ 
 
 SQTOV= 'O'B; 
 DO 1=1 TO 7; 
 
 SOTOV=SQTOV| ( BROS( I ) S OCOUNT ( I , 1 ) ) ; 
 END; 
 
 1 a = • ' B ; 
 
 nil 1 = 1 to 7; 
 
 n>A = DA |BRRS( I ) ; 
 
 END; 
 
 NYET = -.DA ; 
 
 IE BRGSE-iWRBRF THEN DO; 
 
 H/5/70 
 
 Section 2.5.3 - 3/U 
 
BRns= , o , B; 
 
 DO 1=0 TO 7; 
 
 IF BRS(I) THEN BROS ( * ) = BROS ( * ) I BR ( I , *) ; 
 
 END; 
 
 END; 
 
 emo bregin; 
 
 /* 
 
 U/5/70 
 
 Section 2.5.3- hfi 
 
2.6 Instruction Buffer Register 
 
 The Instruction Buffer Register (IBR) is an eight byte (double 
 word) register used to store the instructions as they are obtained from 
 core. The Instruction Register (IR) is used to hold that part of the 
 instruction which is currently being processed and is loaded from the 
 IBR. In the case of Primitive Instructions the IR usually contains the 
 complete instruction. 
 
 The IR is loaded from the IBR according to the count in the 3 
 bit Instruction Counter (ICT). This counter indicates the first byte of 
 the next phrase to be worked on. When a new phrase is to be interpreted 
 the byte designated by the ICT and the three succeeding bytes are read out 
 on to the BROS bus from the fast registers. 
 
 In the next section a more detailed description of the operation 
 of the IBR and ICT will be given. 
 
 U/7/69 Section 2.6 - 1/1 
 

2 - 6 ' 1 Instruction Buffer Register-Functional Description 
 2.6.1.1 Instruction Buffer Register Storage 
 
 The Instruction Buffer Register is contained in the same 9 
 bit/byte storage blocks as the Base Registers (see Section 2.5.1.1). 
 As can be seen in Drawing 01- 1 of th e TP Logic Book, each byte of the 
 IBR has its own select line, IBRO/S, IBRlTs etc. which is connected to 
 the byte select input of the Byte Select Driver (BSD). The WRIB/E line 
 is used to indicate whether the selected byte should be read or written 
 
 over. 
 
 In order to write, WRIB/E must be "0",DBBRS/G must be "0" in 
 order to gate the data from the permuter to the flip-flop inputs, and 
 the proper select lines must be "0". 
 
 The output of the IBR is connected to the BROS bus. When the 
 BRSBPTg signal, which is connected directly to the "Gate True Out" input 
 of the Output Gate Drivers is activated, the four IBR bytes selected by 
 the ICT are gated to the BROS. The permuter is then used to place them 
 in sequential positions in the IR. 
 
 k/7/69 
 
 y Section 2.6.1.1 - 1/1 
 
.1.2 The Instruction Counter and Selection Logic 
 
 The Instruction Counter (ICT) is a three bit double-rank 
 counter which is capable of being counted up by ones or twos (refer 
 to TP Logic Book Drawing lU-2). It has a special added bit to indicate 
 overflow. The purpose of the ICT is to keep track of the initial byte 
 position of the instruction currently being executed by the TP. For 
 this reason it really represents the low order 3 bits of PR#0. 
 
 The ICT is used to drive the Instruction Buffer Register 
 selection logic so that whenever the IR is loaded from the IBR the 
 proper h bytes will be selected. The selection is done with a 23U-0U 
 diode matrix card, the same type as used in the Operand Stack selection 
 logic (see Section 2.3.1-3). As shown in the TP Logic Book Drawing lU-1, 
 the three output lines from the ICT can be gated to the input bus where 
 they are decoded using eight 3-input NANDS from a 2U1-00 board. These 
 eight outputs are then used as inputs into the 23^-OU. The diode matrix 
 card acrivates the four desired select signals. Note that the 23^-OU 
 utilizes a wrap-around feature so that h bytes are always selected no 
 matter what the value of ICT. 
 
 As can be seen in TP Logic Book Drawing 14-1, there is a pro- 
 vision for gating the last 3 bits of the DB into the ICT if the DBCT/G 
 line is on. Tnis is used whenever PR#0 is loaded with a new value field. 
 Whenever PR#0 is read out of storage, the 3 bits of the ICT are masked into 
 the 3 low-order bit positions. This masking is performed using the ICTP/G 
 signal and the OSR bus into the Permuter. 
 
 The overflow bit is used during instruction scanning. If it 
 turns on, PR#0 must be incremented by 8. 
 
 V7/69 Section 2.6.1.2 - l/l 
 
2.6.2 Signal Name Lists for the Instruction Buffer Register 
 2.6.2.1 Control Signals 
 
 BRSBP/G/ - BR Storage Block -» Permuter Input 
 
 DBBRS/G/ - Gate DB -4 BR-IBR Storage Block 
 
 DBCT/G/ - Gate DB-4 ICT 
 
 IBR/S/ - Selection IBR portion of BR-IRB storage 
 
 ICT1/E - Enable counter, ICT = ICT + 1 
 
 ICT2/E - Enable counter, ICT = ICT + 2 
 
 ICTP/G - Mask ICT into permuter output 
 
 WRIB/E/ - Load instruction storage buffer read-write 
 
 7/7/69 
 
 Section 2.6.2,1 - l/l 
 
2.6.2.2 Internal Signals Used by the Instruction Buffer Register 
 
 DBi 
 DBPi 
 ICTi 
 IBRi/S/ 
 
 IRi 
 0SRi 
 
 Output bus from DBP - bit i 
 
 Output bus directly from permuter - bit i 
 
 Instruction Counter - bit i 
 
 Instruction Buffer - select byte i (U chosen at 
 
 a time) 
 
 Instruction Register - bit. i 
 
 Bus from 0S registers to Permuter - bit i 
 
 6/18/69 
 
 Section 2.6.2.2 - l/l 
 

■• •*'' ■'-' '•"- '■'!' i-ui'i-.T !:, r ,i:-.t..T - Logical Degcrigtion 
 2.6. k.l Instruction Counter Logic 
 
 The Instruction Counter (lCT),as shown in Drawing lU-2 of 
 the TP Logic Book, is a three bit double rank counter which can count 
 by one's or two's and which has a special overflow flip-flop to indicate 
 when it has exceeded a count of 7. It can be set to a predetermined 
 number by gating the true and complement values of the 3 low order data 
 bits of the DB (DB33, DB 3 U , and DB35) to the true and complement output 
 lines of the upper rank of the counter. This causes the upper rank 
 flip-flops to be forced to the value which appears on the 3 low order 
 DB bit positions. 
 
 The ICT itself is a normal double rank counter in that the 
 upper rank, which contains the current state of the counter, is gated 
 into the lower rank during the time that the ICT is not counting (i.e. 
 both ICT1/E and ICT2/E are '0'). The output of the lower rank, in turn 
 is sent to the carry propagation logic which decides what the state of 
 the ICT will be the next time that one of the count signals is activated. 
 However since neither ICT1 or ICT2 is active at this time the actual 
 value of the next state cannot be gated into the upper rank. When this 
 does happen the gates which send the data from the upper rank to the 
 lower rank will close. This ensures that the data inputs to the carry 
 logic will not change. Then, depending on which signal was activated, 
 the proper new state will be gated into the upper rank. When enough 
 time has passed for the new count to be stable in the upper rank the 
 count enable signal can be deactivated. 
 
 The carry generation logic is complicated by the fact that the 
 ICT can be incremented by either one or two. In an incrementation by 
 one, the low order ICT bit position, ICT3 , will change state and the 
 ICT2, ICT1 and ICTOV bit positions will change state if the previous 
 state generated a carry. 
 
 In an incrementation by two, the second lowest order ICT bit 
 position, ICT2, will change state and ICT1 and ICTOV will change state 
 if the previous state generates a carry. In the count-by-two case ICT3 
 does not change state. 
 
 11/12/69 Section 2.6.1k! - 1/2 
 
Thus what we have, in effect, is two sets of carry generation 
 l06 ic - one set to increment the counter by 1 and the other set to 
 increment the counter by 2. Since the counter is oniy 3 hits long, full 
 carry looKahead is used since it adds almost no extra logic rn thrs 
 case All this means is that at any given hit position in the counter 
 that'position will change state if every previous position in the counter 
 ls a •!' (for the case of indention hy l) of if every prevxous posrtxon 
 with the possible exception of the lowest order position is a '1' (an 
 the case of incrementation by 2). 
 
 Thus for the lowest order position, ICT3, all that is necessary 
 ls to change state when I0T1/E = 1 and to do nothing when ICT2/E - 1. 
 For the second lowest order position, ICT2, the upper rank flip-flop 
 changes state every ti»e ICT2/E - 1 hut if ICTl/E - 1 it only changes I 
 state if 1CT3 was also a 1. This process of changing state is accomplrshed 
 hy double gating the signals of the lower rank flip-flop into the upper 
 rank flip-flop in such a manner as to reverse its setting. Cray one 
 of the gates will actually operate each time, one being used when the 
 flip-flop is set to 1, the other when the flip-flop is set to 0. 
 
 The highest order position ICT1 is the most complicated of the 
 
 ■ i~ t-p TPTP/E = 1, it will change 
 three, hut it is still fairly simple. If ICT2/h ±, 
 
 state if ICT2 and ICT3 were both previously 1. 
 
 v+ Tr^nv is set when ICT1 goes from a 1 
 The ICT overflow bit, ICIOV, is sex 
 
 ■111. to '000'. The set signal is determined from the proper gatxng 
 circuit for the ICT1 position. 
 
 It should be noted that in order to speed up the setting of 
 the ICTOV flip-flop, the count signals ICTl/E and 1CT2/E were used 
 cirectly instead of using a doubly inverted gate signal as an th b 
 ICT positions. This will not cause timing problems however sance ICTOV 
 o s ot feed back into a lower rank. It will enable a faster operation 
 siace the signals which indicate overflow will he valid at the tame the 
 count enable signals are activated. 
 
 Section 2.6.U.1 - 2/2 
 11/12/69 
 
 
2.7 The 32 Bit Adder 
 
 The 32 bit adder in the Taxicrinic Processor is used to perform 
 binary addition within the TP. It is also used to generate the outputs 
 for the boolean operations, EQV and XOR. The adder uses 2's complement 
 number representation and employs two levels of carry lookahead to hasten 
 carry propagation.* 
 
 The inputs to the adder are obtained from the Distribution Register 
 (DR) and the Permuter Distribution Bus (DB). These two inputs can be gated 
 to the adder only in "true" form. To calculate the difference of two 
 numbers, the subtrahend must be gated from the 9 bit /byte storage (Operand 
 Stack, Pointer Registers, etc.) in l's complement form (see Section 2.2). 
 In this case a carry is injected at the low-order end of the adder to obtain 
 the true 2's complement difference. 
 
 The adder itself is broken down into eight four-bit sum groups 
 with full carry lookahead within the groups. The second level of lookahead 
 occurs between groups, with lookahead between the leftmost groups 1, 2 and 3 
 
 and also between the rightmost groups k through 8. The final carry between 
 
 these two, second level groups is a "ripple" carry. 
 
 The adder output is the ARN bus. This is the input bus to the AR 
 and must be latched into the Arithmetic Register (see Section 2.1.2.5 for a 
 short description of a latch flip-flop). The ARN is in complemented form, 
 but converts to "true" form when it is latched into the AR. 
 
 *For a more complete discussion of carry lookahead adders see Wiegel, Roger E. , 
 "Methods of Binary Addition", DCS Report No. 195, February 1966. 
 
 11/5/70 Section 2.7 - 1/1 
 
2.7-1 32 Bit Adder-Functional Description 
 
 2.7«1»1 Block Diagram Description 
 
 As can be seen from the block diagram in Figure 2.7-1.1/1 the 
 32 bit Adder consists of the following sections: Input Gates, Carry- 
 Generators, Propagation Generators, Group Carry Generators, and Output 
 Gates. Each of these sections are represented by blocks in the diagram. 
 Note that the 32 bit Adder is divided into eight 4-bit groups. The 
 lines leaving the various sections are labeled with the number of signals 
 they represent, either 1 or k. 
 
 The purpose of the 8 Input Gates is to produce the carry trans- 
 mit and carry generate signal for each bit position in a 4-bit group, i.e. 
 
 Ti = Xi ' Yi v Xi * Yi = Xi 9 Yi 
 
 Gi = Xi • Yi 
 
 where Xi and Yi are the ith bits of the DR and DB , respectively. If 
 Gi = 0, the ith bit position will generate a carry into the next (left) 
 position, i-1. If Ti = 0, the ith bit will not generate a carry, but it 
 will transmit a carry if it receives one from the i + 1 th position. 
 
 Each Input Gate generates k Ti and k Gi signals. The Ti signals 
 are sent to the Carry Generator, Propagate Generator and the Output Gates. 
 The Gi signals are only sent to the Carry Generator. 
 
 The Carry Generator and Propagate Generator comprise the first 
 level of lookahead. The Carry Generator is used to generate the carry 
 signals for each position in each four bit group. The Boolean expressions 
 for the jth group are as follows: 
 
 CkGj = CINj 
 
 C3Gj = G4 v Tk • 
 
 CINj 
 
 
 
 C2Gj = G3 v T3 ' 
 
 G4 v T3 * 
 
 t4 • 
 
 CINj 
 
 CIGj = G2 v T2 • 
 
 G3 v T2 • 
 
 T3 * 
 
 G4 v T2 
 
 COUTj = GI v TI 
 
 • G2 v TI 
 
 . T2 
 
 • G3 v TI 
 
 T3 • Th ■ CINj 
 ■ T2 • T3 ' G4 
 
 where TI through ih and GI through G4 represent the Ti and Gi signals 
 for the first through fourth bit positions in the jth group, respectively, 
 CINj represents the carry into the jth group from the next lower order 
 group, and COUTj represents the carry out of the jth group into the next 
 
 higher order group. 
 
 11/4/70 Section 2.7-1.1 - 1/6 
 
DR.DR 
 BITS 32-35 
 
 1st LEVEL LOOKAHEAD 
 
 2nd LEVEL LOOKAHEAD 
 
 Figure 2.7.1.1/1 - TP - 32 Bit Adder 
 
 11/17/70 
 
 Section 2.7-1.1 - 2/6 
 
Note that the carries are produced by a carry generate signal 
 in some position to the right of the position of interest with an 
 unbroken series of carry transmit signals between the two positions. 
 Note also that except for the last signal, which is actually a carry 
 generate signal for the four bit group, all of the expressions depend 
 on the input carry which will come from the previous group and which will 
 not be known until later . However, at the first level of lookahead, we 
 are really only interested in finding out if this group will generate a 
 carry by itself, so only the last equation is important at this stage. 
 
 These carry signals are produced by using a diode matrix board. 
 In order to facilitate the hardware realization and to speed up the adder, 
 De Morgan's theorem was used to rewrite them in the following form: 
 
 Cl+.i = 
 
 CINj 
 
 C3j = Gk-Tk v GU.CINj 
 
 C2j = G3 • T3 v G3 • GU . TU v G3 • GU . CINj 
 
 Clj = G2 • T2 v G2 • G3 • T3 v G2 • G3 • GU • TU v G2 • G3 • Gl+ • CINj 
 
 COUTj = G1.T1 v G1»G2*T2 v G1«G2»G3*T3 v G1»G2«G3«GU 
 
 The logical drawing for the diode matrix is shown in Figure 
 2.7.1.1/2 while the diode layout is shown in Figure 2.7-1.1/3. 
 
 The Propagate Generator produces a propagate signal which 
 indicates if the particular four -bit group will conduct an input carry all 
 the way through the group. It is calculated from the Ti signals of the 
 four-bit group, i.e. 
 
 Pj = Tl • T2 • T3 • TU = Tl v T2 v T3 v T^ 
 
 Once the Pj and COUTj signals have been produced, the first 
 level of lookahead is completed. Note that the production of these 
 signals only depends on the Ti and Gi signals which were produced by the 
 Input Gates. 
 
 llA/70 Section 2.7.1.1 - 3/6 
 
T, 
 
 L7, L8 
 
 15,16 
 
 = 13,14 
 '2 
 
 G 2 
 
 9,10 
 
 T 3 
 
 G 3 
 
 7,8 
 
 5,6 
 
 T 3 ' 4 
 
 G 4 i— 
 
 c J— 
 
 'N 
 
 OUTPUT 
 SIGNAL 
 
 \ 
 
 R,S 
 
 ► COUTj 
 
 N 
 
 M 
 
 J,K 
 
 H 
 
 C,D 
 
 B 
 
 A 
 
 Figure 2. 7. 1.1/2 - Lookahead Carry Generator for Group j 
 
 CIG 
 
 
 C2G; 
 
 C3G; 
 
 9/18/69 
 
 bee 
 
 tion 2.7-1-1 - W6 
 

 ISI 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 00 
 
 
 >- 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 £- 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 co 
 
 
 > 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 in 
 
 
 z> 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 ^ 
 
 c 
 
 H 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 ro 
 
 
 
 
 
 
 
 
 
 
 * 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 CJ 
 
 
 
 
 
 
 
 
 !! 
 
 1 
 
 I 
 
 a. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 — 
 
 O 
 
 
 
 
 
 J 
 
 3 
 
 [ 
 
 3 
 
 ! 
 
 
 * 
 
 
 2 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 o 
 
 > 
 
 
 
 j 
 
 [ 
 
 
 ? 
 
 
 ? 
 
 
 * 
 
 z 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 o> 
 
 
 
 
 
 
 
 
 i 
 
 * 
 
 
 _) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 CO 
 
 H 
 
 
 
 
 
 ? 
 
 ] 
 
 [ 
 
 3 
 
 ; 
 
 ~3 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 I s - 
 
 
 
 
 \ 
 
 : 
 
 E 
 
 3 
 
 ! 
 
 
 3 
 
 ; 
 
 
 X 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 (D 
 
 < 
 
 
 ; 
 
 [ 
 
 1 
 
 
 3 
 
 [ 
 
 
 3 
 
 » 
 
 U_ 
 
 
 
 
 
 
 
 
 ! 
 
 
 
 
 
 
 
 
 lO 
 
 
 
 
 
 
 3 
 
 ; 
 
 ' 
 
 .IT* ; 
 
 ID 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 <fr 
 
 
 
 
 \ 
 
 \ 
 
 j 
 
 ; 
 
 
 Q 
 
 
 
 
 
 
 
 ' 
 
 
 
 
 
 
 
 
 
 ro 
 
 > 
 
 
 | 
 
 : 
 
 ) 
 
 
 ' 
 
 
 CD 
 
 
 
 
 
 
 ' 
 
 
 
 
 
 
 
 
 
 
 CVJ 
 
 J 
 
 
 
 2 
 
 ! 
 
 ' 
 
 n 1 
 
 < 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 — 
 
 ^_ 
 
 
 ; 
 
 [ 
 
 3 
 
 ! 
 
 
 
 =>UJ 
 
 i-o 
 
 OO 
 
 — 
 
 CJ 
 
 ro" 
 
 CO 
 
 » 
 
 O 
 
 of 
 
 rO 
 
 CO 
 lO 
 
 GO 
 
 05 
 
 CJ 
 
 CJ 
 
 •-CE 
 
 o 2 
 
 _ <3" 'J'rOroOJcvi — — 
 
 O lO |l- lO |l- |o |l- IO It- 
 
 Figure- 2.7.1.1/3 - 1st Level Lookahead Carry Generator - 236-1^ 
 
 9/26/69 
 
 Section 2.7.1.1 - 5/6 
 
The second stage of lookahead involves the Group Carry 
 Generators. We want to calculate the CINJ signals for each group so 
 that we can complete the calculation of the carry signals in the equations 
 given above. Taking the low order Group Carry Generator first, we have 
 the following equations : 
 CIN8 = CINJ 
 CINT = C08 vP8* CINJ 
 CIN6 = COT v PT ♦ C08 v PT • P8 * CINJ 
 CIN5 = C06 v P6*C07 v P6-PT-C08 v P6-P7 «P8 -CINJ 
 
 CINU = C05 v P5«C06 v P5-P6-COT v P5-P6-P7-C08 v P5-P6-P7-P8-CINJ 
 CIN3 = COU v PU-C05 v PH.P5-C06 v pU«P5'P6'COT v Pl+-P5'P6'PT*C08 
 v pU*P5'P6'PT-P8'CINJ 
 
 where CINJ is the low-order injected carry to the adder, and the CO j ' s 
 are the COUTj signals from the Carry Generators. Note that the form of 
 the equations is the same as in the equations for the Carry Generator 
 hut in this case the COj signals represent a carry generated hy the 
 
 group and the Pj signals represent a carry transmitted by the group. 
 The 0-3 Group Carry Generator has to wait for CIN3 to be 
 
 formed before it can "start" since in its equations CIN3 takes the 
 
 place of CINJ, i.e. : 
 
 CIN2 = C03 v P3 • CIN3 
 
 CIN1 = C02 v P2 • C03 v P2 • P3 • CIN3 
 
 This wait is what is referred to as the "ripple" carry in the 
 adder. 
 
 Finally, with all the input carries to the groups determined, 
 the carry generators can now generate the proper individual carries for 
 each bit simultaneously and the Output Gates can use these carries and 
 the Ti signals previously calculated, to determine the adder output. 
 These output signals are calculated for each bit position i, as follows: 
 
 ARN i = T i * C i ▼ T^" • C^. 
 
 Overflow-Underflow signals are formed using sign bit and output 
 information. This is explained in greater detail in Section 2.7-1.3- 
 
 iiA/70 Section 2 ' 1 ' 1 ' 1 ' 6/6 
 
2.7-1.2 Adder Timing 
 
 Figure 2.T-1-2 gives a timing chart for the adder. Time is given 
 in delay units in the left-hand column: 1 delay unit per NAND and 1/2 delay 
 unit per AND-OR diode matrix. The event column is subdivided into sum groups 
 1 and 2 and groups 3-8, (where group 8 contains bits 32-35)- The Sum in 
 groups 1 and 2 takes 2 delays more to form than the sum in 3-8 due to the 
 ripple-carry between second level lookahead units. . 
 
 5/5/69 Section 2.7-1.2 - 1/2 
 
EVENT 
 
 Time in 
 Delays 
 
 
 Sum Group: 
 1 2 
 
 
 
 X 
 
 and Y appear at inputs j 
 
 1/2 
 
 
 
 1 
 
 <Ji 
 
 1 s, Gi's appear 
 
 1-1/2 ! 
 
 
 2 !*-3 
 
 appear 
 
 2-1/2 f- — COUT's appear 
 
 3 
 
 
 3-1/2 
 
 
 1+ 
 
 CIN3 back 
 
 1+-1/2 
 
 
 5 
 
 CIN3 to level 2 
 
 5-1/2 
 
 
 6 
 
 CIN1, CIN2 to S.G. 
 
 6-1/2 
 
 ! 
 
 T 
 
 
 7-1/2 
 
 C. , in S.G. 
 i's i 
 
 8 
 
 
 j 
 
 Sum Group: 
 
 3, U, 5, 6, 7, 8 
 
 CINJ appears 
 
 (To level 2) 
 
 ) 
 
 (Sum in S.G. 8 only) 
 CTN7 back 
 
 CIN3 OT^ BacktoS . G .. s 
 
 C 's formed in S.G. 
 
 l 
 
 C. 's in S.G. 
 
 i 
 
 ^ 
 
 _ Sum output to AE 
 
 "> 
 
 8-1/2 C., s in S.G, 
 
 9-1/2 SUM output 
 
 Groups 1 and 2 
 
 + 2 delays to set AR + k to 
 set 0V/UF 
 
 Figure 2.7.1.2 Lookahead Adder Timing 
 
 9/30/69 
 
 Section 2.7-1.2 - 2/2 
 
2.7-1.3 Adder Overflow 
 
 In considering the overflow conditions of the adder there are 
 eight possible sign configurations which can occur: 
 
 B: 
 
 Augend : 
 
 + 
 
 * 
 
 + 
 
 * 
 
 - 
 
 - 
 
 D: 
 
 Addend : 
 
 + 
 
 + 
 
 - 
 
 - 
 
 - 
 
 - 
 
 A: 
 
 Sum: 
 
 + 
 
 - 
 
 + 
 
 - 
 
 + 
 
 - 
 
 
 
 00 
 
 01 
 
 10 
 
 01 
 
 10 
 
 11 
 
 *2 cases each 
 
 The second and fifth cases are the error conditions. Overflow and underflow 
 may be illustrated by two examples, respectively: 
 
 +5 0101 
 
 +h_ 0100 
 
 -7 1001 
 
 -5 1011 
 
 -k 1100 
 
 +7 0111 
 
 An overflow (or underflow) signal is given by: 
 
 0V = D«B.AvD.B.A 
 as determined by the sign bits of the Augend (B) , Addend (j)} and Sum (A) 
 
 5/5/69 Section 2.7-1.3 - 1/1 
 

2-7.2 Signal Name Lists for the 32 Bit Adder Logic 
 2.7-2.1 32 Bit Adder Control Signals 
 
 ADD/E - Enable 32 bit adder 
 
 BAR/G - Gates DB to AR through ARN 
 
 7/8/69 
 
 Section 2.7.2.1 - 1/1 
 

2.7-2.2 32 Bit Adder Internal Signals 
 
 ARNi 
 
 CINi/ 
 
 CINJ 
 COUTi 
 
 PRi 
 
 Ti/ 
 
 AR input bus - bit i. Output of 32 bit adder is 
 loaded onto this bus . 
 
 Carry into ith adder group, i = 3, . . ., 7 
 
 Inject carry into low order bit of 32 bit adder 
 
 Carry generated within ith adder group, i = 2..., 8 
 In adder this represents ability of a given bit 
 position to transmit an incomming carry. 
 
 If on, indicates a carry will propagate through ith 
 adder group, i = 3, ..., 8 
 
 Equivalence function (NOT - XOR) between DBi and DRi, 
 Used by both adder and Boolean logic. 
 
 7/8/69 
 
 Section 2.7-2.2 - l/l 
 

2.7.3 32 Bit Adder - PL/1 Description 
 
 // EXEC PL1 
 //PL 1 .SYSPUNCH 
 //PL1 .SYSIN i)D 
 ADD32: PR 
 nCL ( AO 
 OCL AO 
 nCL (AR 
 OCL G 
 Gl 
 G2 
 G3 
 G4 
 G5 
 G6 
 G7 
 G8 
 G9 
 G10 
 Gil 
 G12 
 G13 
 G14 
 G15 
 G16 
 G17 
 G19 
 G2 
 G21 
 G2 2 
 G23 
 G2 4 
 G2 5 
 G2 6 
 G28 
 G29 
 G30 
 G31 
 G32 
 G33 
 G34 
 G35 
 Tl 
 T2 
 T3 
 T4 
 T5 
 T6 
 T7 
 TB 
 T10 
 Til 
 T12 
 T13 
 T14 
 T15 
 T16 
 T17 
 
 on SYsnuT=R 
 
 nc ( AnnF»c iMJt E 
 
 DF, CINJt FOVE, 
 
 nouT bit ( l ) ; 
 
 N,OB,DR,T ) (36 ) 
 
 OVE, XDREt AonnuT) 
 XORF ) B I T ( 1 ) ; 
 
 (36) B 
 B I T ( 1 
 BIT( 1 
 BITd 
 B I T ( 1 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BIT(1 
 BITd 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BITd 
 BIT(1 
 BITd 
 BIT( 1 
 
 T( 1 ) EXT 
 
 E F I M F 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 OFFIMFD 
 OFF I NED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEF INED 
 DEFINED 
 OFF INED 
 DEFINED 
 F F I N E D 
 DFFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 D F F I N E 
 D E F I N F D 
 OFF I NED 
 DEFINED 
 OFF INED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEF INED 
 DEFINED 
 DFFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 DFFINED 
 
 BITd ) 
 ERNAL, 
 
 ■G pdsi 
 pnsi 
 
 PDSI 
 
 posi 
 
 POSI 
 
 PDSI 
 POSI 
 POSI 
 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 POSI 
 
 FXTERNAL ; 
 
 G 
 G 
 
 G 
 G 
 G 
 G 
 
 G 
 G 
 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 G 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 T 
 
 TION( 1 
 TION(2 
 TI0N(3 
 TI0N(4 
 TION(5 
 TI0N(6 
 TION(7 
 TION(8 
 TI0N(9 
 TION( 10) 
 TI0N( 1 1 ) 
 TI0N( 12 ) 
 TI0N( 13) 
 TION( 14) 
 TION( 15) 
 TION( 16 ) 
 TI0N( 17) 
 TI0N( 19 ) 
 TI0N(20) 
 TION(21 ) 
 T I ON (22) 
 TION(23) 
 TION(24) 
 TION(25 ) 
 TI0N(26) 
 TI0NK2R ) 
 TI0N(29) 
 TION(30) 
 TI0N(31 ) 
 T I ON (32 ) 
 TI0N(33) 
 T I ON (34) 
 TION(35) 
 T I ON ( 1 ) 
 TI0N(2 ) 
 TI0N(3 ) 
 TI0N(4 ) 
 TION(5 ) 
 TI0N(6 ) 
 TI0N(7 ) 
 TION(8 ) 
 TION( 10) 
 TION( 11 ) 
 T I ON (12 ) 
 TION( 13) 
 TION( 14) 
 TION( 15) 
 TION( 16) 
 TION( 17) 
 
 11/5/70 
 
 Section 2.7.3 - 1/6 
 
T19 
 T20 
 T21 
 T22 
 T23 
 T24 
 T2S 
 T26 
 T28 
 T29 
 T30 
 T31 
 T32 
 T33 
 T34 
 T35 
 DCL ( 
 I 
 
 BIT(1 ) 
 BIT(l) 
 BITd) 
 BITd) 
 BIT(1 ) 
 BIT(l) 
 BIT(1 ) 
 BIT(l) 
 BIT(1 ) 
 BIT(l) 
 BIT(1 ) 
 BIT(l) 
 BIT(1 ) 
 BITd) 
 BlTd ) 
 BIT( 1) 
 
 DEFINED 
 DEFINED 
 DEFINED 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 DEFINED 
 
 T P0SITI0N(19 ) t 
 T PnSITI0N(20) » 
 T P0SITI0N(21 )t 
 T POSITION (22) , 
 T POSITION(23), 
 T POSITION(2^) t 
 T POSITION(25), 
 T POSITION(26>) » 
 T POSITION(2B ), 
 T POSITinN(29) » 
 T POSITION(30), 
 T POSITION(31) t 
 T POSITION(32 )t 
 T PGSITI0N(33) t 
 T POSITinN(3A)» 
 T POSITION(35) ; 
 
 
 DFFINED 
 /^INTERNAL VARIABLES,*/ 
 
 CARRY PROPAGATF SIGNALS*/ 
 Pl t P2,P3,P4,P5,P6,P7,P8, 
 
 CARRY INTO ITH ADDER 
 
 
 GROUP */ 
 
 r ari (-3G2tC3G3tC3G4,C3G5,C3G6tC3G7,C3G8, 
 
 /"JrYI^O FOURTH POSITION OF ITH ADDER 
 C4GltC4G2 f C4G3,C4G4,C4G5,C4G6tC4G7,C4G8 
 
 GROUP*/ 
 
 ) BITd); 
 PUT LlSTt ■ ADD32 ENTERED' ) ; 
 /* CALCULATE THE CARRY TRANSMI 
 
 SIGNALS (G) */ 
 
 if fovFI ADDFIXORE THEM 
 
 nn i=j*9+l to j-9+b; 
 
 T(I)=DB( I)6-DR( I) !-DB( I )f.DR( I); 
 Gd )=DB(I )&DR( I )? 
 
 END; 
 
 SIGNALS (T) AND CARRY GENERATE 
 
 DO J=0 TO 3; 
 
 THROUGH THF GROUP */ 
 Pl = Tlf.T2&T3f,TA; 
 P2=T5F,T6&T7£T8; 
 P3 = T10f>Tll£T12£T13; 
 P4 = T14&TlSf,T16&T17; 
 P5=T19&T20&T21&T22; 
 
 11/5/70 
 
 Section 2.T.3 - 2/6 
 
P6»T23£T24£T256T26 
 
 P7=T28£T29£T30£T31 
 P8=T32£T33£T34£T35 
 CIN3= C0UT4 
 
 lCniJT5f.P4 
 
 I CmiTft£P4£P5 
 
 |CniJT7£P4£P5£P6 
 
 lcnuT8£P4£P5£P6 
 
 ICINJ £P4£P5£P6£P'7£P8; 
 CIN4 = C0UT5 
 
 ! cm iT6 cp s 
 
 |CniJT7£P5£P6 
 ICC11JT8£P5£P6£P7 
 
 ICINJ £P5£P6£P7£P8; 
 CIM5= C0MT6 
 
 |C0UT7£P6 
 
 |CGUT8£P6£P7 
 ICINJ £P6£P7£P8; 
 CIN6= C0IJT7 
 
 |C0UT8£P7 
 
 ICINJ £P7£P8; 
 CIN7= C0JT8 
 
 ICINJ&P8; 
 CIMH=CINJ ; 
 
 /-CALCULATE RIPPLE CARRY */ 
 CIN2= COUT3|CIN3£P3; 
 CINla CCHJT2 lCriUT3£P2|CIN3£P2£P3; 
 
 C1G1=G2|T2£G3|T2£T3£G4|T2£T3£T4£CIN1; 
 C2G1=G3|T3£G4|T3£T4£CINI1; 
 C3G1=G4| T4£CIN1; 
 C4.G1=CIN1 ; 
 
 C1G2=G6|T6£G7|T6£T7£G8|T6£T7£T8£CIN2; 
 C2G2=G7|T7£G8|T7£T8£CIN2; 
 
 C3G2=G8 I T86CIN2 ; 
 C4G2=CIN2; 
 
 C1^3 = G11|T11£G12|T11£T12£G13|T11£T12£T13£CINI3; 
 
 C2G3=G12|T12£G13|T12£T13£CIN3; 
 
 C3G3=G13 I T13SCIN3; 
 
 C4G3=CIN3; 
 
 ClG4*G15|T15£G16|T15fiT16fiG17|T15£T166T17fiCIN4: 
 
 C2u4=G16|T16£G17|T16£T17£CIN4; 
 
 C3G4=G17 | T17£CIM4; 
 
 C4G4=CIN4; 
 
 C2G5=G21 I T21£G22 I T2 1£T22£C IN5 ; 
 C3G5=G22 |T22£CIN5; 
 C4G5=C IM5; 
 
 C1^ = G24|T24£G25|T24£T25£G26|T24£T25£T26£CIN6; 
 C2G6=G25|T25£G2^|T25£T26£CIN6; 
 C3G6=G26|T26£CIN6; 
 C«*G6 = C IN6 ; 
 
 ^r7 = r^! T29r ' G3 ° |T29&T30r ' G31,T29&T3 °ST31£CIN7; 
 
 C?G7=G30|T30£G31|T30£T31£CIN7; 
 
 C3G7=G31 I T31&CIN7; 
 
 C4G7=CIN7; 
 
 riro = ^ 3 ! T33&G34,T33&T34SG35 ' T33 ^34£T35£CIN8; 
 C2G8 = G34|T34£G35|T35£CIN8; ^i<n«, 
 
 11/5/70 
 
 Section 2.7.3 - 3/6 
 
C3G8=G35lT356CIN8i 
 
 ^CALCULATE THE OUTPUT SIGNALS*/ 
 
 /*FIRST GROUP-/ 
 
 ARN(1 )=T1£-X1G1 I-.T16C1G1; 
 
 ARN(2)=T2&-X2G1 HT2&C2G1; 
 ARN(3)=T3&-C3G1 I-T3&C3G1; 
 AKN (4)=T4F,-C4G1 |-iT46C4Gl;. 
 
 /* GROUP # ?*/ 
 ARN(5)=T5&-C1G2 |iT5£ClG2; 
 ARN(6)=T6£-C2G2l-T6£C2G2; 
 ARN(7)=T7C-.C3G2 I-T7FX3G2; 
 ARM(8>=TB&-C4G2|-T8&CAG2; 
 &RN(10)3T106-C1G3[-.T106C1G3; 
 ARN(11)=T11£^C2G3HT11£C2G3, 
 ARM(12)=T12&-C3G3|-T12&C3G3; 
 ARN(13)=T13R-C4G3|-«T136C^G3; 
 
 /*GR0UP#4*/ 
 ARN(14)=T14&-XlG4|-T14fXlG4; 
 
 ARN(15)=T156-.C2G4|--T15fX2G^; 
 ARN(16)=T16&-X3G4|-.T16fX3G4; 
 
 ARN117)=T17£-.C4G4|-.T17£C4G4; 
 
 /*GROUP#5 */ 
 ARN(19)=T19C-C1G5|-T19&C1G5; 
 
 ARN(?0)=T20£r.C2G5|-.T20£C2G5; 
 
 ARN(21)=T216-C3G5j-.T21CC3G5; 
 
 ARN(22)=T22 6-C4G5|-.T22£C4G5, 
 
 /*GROUP >*6 */ 
 ARN(23)=T23R-.C1G6|-.T23 6C.1G6; 
 
 ARN ( ? 4)=T24&-C2G6|-T24FX2G6; 
 
 ARN(25)=T2"'5R-«C3G6l-T25fiC3G6; 
 
 ARN(26)=T26K-X4G6|-T26fX4G6; 
 
 /*GROUP #7 */ 
 ARN(28)=T2MRiClG7l-T28£ClG7; 
 
 ARN(29)=T29&-.C2G7|-»T296C2G7; 
 
 ARN(30)=T30&-C3G7|-T30&C3G7; 
 
 ARM (31 )=.T31.&-«C4G7|-.T31£C4G7; 
 
 /*GROUP *8*/ 
 ARM 32 )=T32f^ClG8l-T32£ClG8, 
 ARM(33)=T33r.-C2G8l-T33fX2G8; 
 APN(34)=T34&-C3G8|--T34CC3G8; 
 ARN(35)=T35f.-.C4G8|r.T35 6C4G8; 
 IF AOnOUT THFN DO; 
 PUT SKIP(^); 
 CALL PRINT1 (DB, ' DB ' ) ? 
 CALL PRINTKORt'DR ' ) 5 
 CALL PR I NT 1 (Gt ' G ' ) » 
 
 CAI L PRlMTKTf 'T ' ) ; 
 
 CALL PRIMT1(ARN,'ARN »); 
 p l)T Fi)ITCGROUP','l'T'2«t'3',«4','5 
 
 ,.. T F rnif.c™.TSili! , .couTi i cmiT2 f cnuT3 f coiiT4 f cnuT5.couT6. 
 cnuT7,cnuT«) „,,,,,. 
 
 (SKIP, AllO), 8 (X(2),B<1>>). 
 PUT EOITCPm-.Pl,P2.P3;i;*.«,P6,P7.P8) 
 
 PUTE0IT ,.irNi.;:!:c !;!.«ii^«t«i*,ciH 9 .c.-6,c™T,c,-., 
 
 11/5/70 Section 2.7.3 _ ^/o 
 
PUT 
 
 PUT 
 
 PUT 
 
 PUT 
 
 END; 
 FMD AD032 
 
 (SKIP, A 
 
 EDI T( 'C1G( I )= 
 
 (SKIP, A 
 EDIT( 'C2G( I )= 
 
 (SKIP, A 
 EDIT( 'C3G( I ) = 
 
 (SKIP, A 
 EDIT( «C4G( I )= 
 
 (SKIP, A 
 
 10) tfl (X(2) ,B( 1 
 ,C1G1,C1G2,C1G3 
 1 ) , 8 ( X ( 2 ) , B ( 1 
 ,C2G1,C2G2,C2G3 
 10) ,8 (X( 2) ,B( 1 
 
 ) ) ; 
 C1G4,C1G5,C1G6,C1G7,C1G8 ) 
 
 ) ) ; 
 
 C2G4,C2G5,C2G6,C2G7,C2G8) 
 
 ) ) ; 
 
 ,C3G1,C3G2,C3G3,C3G4,C3G5,C3G6,C3G7,C3G8 ) 
 
 10) ,8 (X(2) ,B( 1 
 ,C4G1,C4G2,C4G3 
 10) ,8 (X( 2) ,B( 1 
 
 ) ) ; 
 C4G4,C4G5,C4G6,C4G7,OG8 ) 
 
 ) ) ; 
 
 /* 
 
 11/5/70 
 
 Section 2.7.3 - 5/6 
 
/* 
 
 ADDOVF: PROCUDDE, aov, aucg, csb, csh, 
 
 csw, RSYS); 
 DCLUDDE, AOV, AUCG, CSB, CSH, CSW, 
 
 RSYS ) BIT! 1 ) ? 
 DCL ( AR, DB, DR, LR ) ( 36 ) BIT(l) EXTERNAL; 
 PUT LISK'ADDOVF ENTERED'); 
 /* CHECK FOR ADDER OVERFLOW */ 
 AOV= 'O'B; 
 IF LR(9)£AUCG THEN AOV='l'B; 
 
 F t S E DO * 
 
 IF CSW THEN AOV = ADDE&(DR(l)&DB(l )£-ARU ) 
 
 | DR ( 1 )£-*DB( 1 )&AR( 1 ) ) 5 
 IF CSH THEN AO V = ADDE £ ( DR ( 19 ) &DB ( 19 ) &-AR ( 19 ) 
 
 |-,DR(19)&-DB(19)&AR(1) ) 5 
 
 IF CSB THEN AOV=ADDE£(DR(28)£DB(28 )£-AR(28) 
 
 |-,DR(28)&-DB(28 )f.AR(28) ) ; 
 
 end; 
 
 IF RSYS THEN AOV='0'B; 
 FND ADDOVF; 
 
 11/5/70 Section 2.7.3 - 6/6 
 
2.8 Boolean/Shift Logic 
 
 The boolean logic accepts operands from the Distribution Regis- 
 ter (DR) and the Distribution Bus (DB), performs one of the boolean func- 
 tions, "AND", "OR", "XOR" or "EQU" on them, and gates the result into the 
 Logic Register (LR). The "OR" function is a combination of a data transfer 
 from the DB to the LR and from the DR to the LR. 
 
 The "XOR" and "EQU' functions are generated using parts of the 32 
 bit adder. The appropriate outputs are then gated from the adder to the LR. 
 
 The shift logic employs the permuter to make shifts in multiples 
 of 8 bits. The shift control first makes the highest multiple-of-8 bit 
 shift that it can without exceeding the desired shift. This is done using 
 the permuter and inhibiting the necessary bytes. After this has been done 
 the shift control shifts the DR to the LR shifting one bit at a time and 
 then returning the LR to the DR until the proper number of additional bits 
 have been shifted and the properly shifted result is in the LR. Since the 
 flags are not touched in the bit shifting, the shift control only will 
 shift flags in multiples of 8 (i.e. when the permuter is used). 
 
 6/18/69 Section 2.8 - l/l 
 
■ 1 Boolean/Shirt Logic-Functional Description 
 2.8.1.1 Boolean Logic 
 
 As stated previously the "OR" function is a combination of a 
 data transfer from the DB and DR to the LR. The DR and DB are simultaneously- 
 gated in complemented form to the LR "in bus" (LRN) where they are dot-ored 
 and then gated into the LR. 
 
 The "AND" function is realized by a NAND gate, with a DR and a 
 DB input, in each position. The NAND outputs are dot-ored to the respec- 
 tive bit positions on the LRN. The LRN at this point is in complemented 
 form but this is compensated for in the output definitions of the LR. 
 
 Exclusive or's, "XOR" , and equivalences "EQV" are actually 
 generated in the 32 bit adder. The input gates generate the function 
 
 T. = DB. • DR. v DB. • DR. 
 ill 11 
 
 in every bit position. These T. signals are then routed to the boolean 
 logic as well as to the inner portions of the adder itself. In the 
 boolean logic, the T. signals are gated to the LRN inputs whenever the 
 XOR or EQV function is selected. The function that is formed is determined 
 as follows: If both operands are gated from the Operand Stack in 'true' 
 form, the EQV function is formed. If one of the operands is complemented 
 when it is gated from the OS, the XOR function is generated, since 
 X.YvX-Y = X.YvX»Y( alternately , X © Y = X ® Y ) . 
 
 Flag bits are treated the same way as the data bits in all 
 boolean operations. Extra logic is employed to generate the XOR and EQV 
 functions for the flags since none is provided in the adder. 
 
 U/T/69 Section 2.8.1.1 - l/l 
 
1.1.2 Shift Logic 
 
 Logical left and right shifts take place between the DR and the 
 LR. Gates are provided to allow an operand in the DR to be shifted one bit 
 position to either the right or the left while being transferred from the 
 DR to the LR. During these shifts the positions of the flags are not 
 changed. Shifts of more than one bit are effected by gating the LR directly 
 back to the DR, then shifting another bit position. The TP control uses the 
 M counter to keep track of the number of shifts still to be performed. 
 
 For shifts of 8 bits or more the Permuter Logic is also used. 
 Before single bit shifting is performed, the DR is shifted the highest 
 number of bytes possible without exceeding the bit shift count in the M 
 counter. The flags are shifted along with the data bits. By using the 
 permuter for large shifts, the one-bit -at-a-time shifter never has to make 
 more than 7 shifts to complete a given shift command. If a shift of more 
 than 31 positions is specified, the cell is set to all zeros. 
 
 The multiple-of-8 shift by the Permuter is made in one permuta- 
 tion regardless of how many byte places are being shifted. Since the 
 permuter does not shift bytes "off the end" the shift logic must provide 
 the proper inhibit signals to the Permuter so that these bytes will be 
 masked out. Figure 2.8.1.2 gives a table showing how far to permute and 
 which bytes must be inhibited as a function of the shift direction and the 
 high-order two bits of the M counter (these bits give the number of bytes 
 to be shifted). Using this table the following equations can be developed: 
 
 1+/T/69 Section 2.8.1.2 - l/k 
 

 
 Left 
 
 Sh 
 
 ift 
 
 Right 
 
 Shift 
 
 
 
 Permute 
 
 
 Inhibit 
 
 Permute 
 
 Inhibit 
 
 MCT 
 
 MCT 
 
 Signal 
 
 
 Bytes 
 
 Signal 
 
 Bytes 
 
 
 
 
 
 PLO 
 
 
 - 
 
 PLO 
 
 - 
 
 
 
 1 
 
 PL1 
 
 
 3 
 
 PL3 
 
 
 
 1 
 
 
 
 PL2 
 
 
 2,3 
 
 PL2 
 
 0,1 
 
 1 
 
 1 
 
 PL3 
 
 
 1,2,3 
 
 PL1 
 
 0,1,2 
 
 Figure 2.8.1.2 - Permuter Control Signals for Byte Shifting 
 
 , , „ Section 2.8.1.2 - 2/k 
 
 U/T/69 
 
PLO = LSP • M • M v RSP'M • M g 
 
 I BO = RSP • (M v M ) 
 
 PL1 = LSP • M • M v RSP-M 1 • M g 
 
 PL2 = LSP * M • M v RSP*M • M 2 
 PL3 = LSP • M • M v RSP-I^ • M 2 
 
 IB1 = RSP • M v LSP • M • M 
 
 IB2 = LSP * M v RSP ' M ■ M 
 IB3 = LSP * (M v M ) 
 
 where PLi = permuter left i bytes; RSP = right shift; LSP = left shift 
 
 However, referring to the equations for PLI and IB2, and PL3 
 and IB1 some simplification can take place if we let 
 
 IBPL21 = RSP • M 
 
 1 
 
 IBPL13 = LSP 
 
 M„ 
 
 M, 
 
 M, 
 
 1 2 
 
 where IBPLij = is a control line to the permuter which inhibits byte i 
 and also permutes left j bytes. 
 
 These signals go directly to the Permutation Control 
 Logic and turn on the appropriate permute and inhibit signals. This 
 means that the remaining parts of the shift equations can be written 
 as follows : 
 
 PLO = LSP 
 
 M 
 
 1 
 
 PLI = LSP • M 
 
 1 
 
 PL2 = LSP • M 
 
 1 
 
 M v RSP.M 
 
 M 2 v RSP»M 
 
 M, 
 
 M, 
 
 IBO = RSP • (M v M ) 
 
 IB1 = RSP 
 
 M, 
 
 PL3 = RSP • M 
 
 1 
 
 M, 
 
 IB2 = LSP • M, 
 
 IB3 = LSP • (M v M ) 
 
 Using these equations the permutation and inhibit signals are 
 decoded from the M-counter and the inputs from the TP control and are 
 then routed to the permuter. The rest state of the permuter is disabled 
 during this cycle when the operand is being shifted in steps of 8. 
 
 Double words are not shifted, primarily because of the problems 
 involved in masking bits shifted out of one half of the double word 
 into the proper positions in the other half. 
 
 11/16/70 
 
 Section 2.8.1.2 - 3/U 
 
When bytes or half-words are to he shifted they are initially 
 loaded into the DR by the Permuter, right or left justified depending 
 on the direction of the shift. The cell is placed so that the bits will 
 be shifted "off the end" of the DR and not into the "unused" portion. 
 During these loadings the "unused" portion of the DR is set to zero by 
 inhibiting the proper permuter bytes. 
 
 The Shift Logic contains several sections of "testing" logic 
 to detect certain conditions of which the TP control must be aware. MZER 
 
 is "one" if the M counter and all the high order bits of the shift count 
 
 (which is in the right-most bytes of the IR) are zero. 
 
 
 
 Section 2.8.1.2 - k/k 
 h/1/69 
 
 
2.8.2 Signal Name Lists for the Boolean/Shift Logic 
 2.8.2.1 Control Signals 
 
 AND/E/ 
 
 BLR/G/ 
 
 CTD/E/ 
 
 CTMHZ 
 
 CTMLZ 
 
 CTU/E/ 
 
 DLR/G/ 
 
 EQV/E/ 
 
 LS/E/ 
 
 LSP/E 
 
 MCT/E/ 
 
 MZER 
 
 0R/E/ 
 
 RMCT/ 
 
 RS/E/ 
 
 RSP/E 
 
 X0R/E/ 
 
 AND enable DB • DR -* LR 
 
 Gate DB -♦ LR 
 
 Enable count down for M counter (MCT) 
 
 Output Signal - High Order 2 bits of the MCT = 
 
 Output Signal - Low Order 3 bits of the MCT = 
 
 Enable count up for M counter (MCT) 
 
 Gate DR-^LR 
 
 Enable equivalence 
 
 Enable - left shift 
 
 "left shift" to be made by shift control using permuter 
 
 Enable M- counter 
 
 Output - M-counter and high order bits of IR all = 0. 
 
 0R enable DB v DR -^ LR 
 
 Reset M-counter 
 
 Enable - right shift 
 
 "right shift" to be made by shift control using 
 
 permuter 
 
 Exclusive 0R unable DB $ DR -f LR 
 
 6/18/69 
 
 Section 2.8.2.1 - 1/1 
 

 
2.8.2.2 Internal Signals Used by the Boolean/Shift Logic 
 CTD 
 
 CTU 
 DBi 
 DRi 
 
 IBi/ 
 
 IBPL13 
 
 IBPL21 
 
 IRi 
 
 LRi 
 
 LRi/G 
 
 LRLi 
 
 LRNi 
 
 MCTi 
 
 PLi/ 
 
 Ti/ 
 
 XRV/E 
 
 When on, M counter counts down 
 
 When on, M counter counts up 
 
 Distribution bus - bit i 
 
 Distribution register - one of the inputs for 
 
 shift - bit i 
 
 Inhibit signal for byte i in permuter output 
 
 Inhibit byte 1 - permute left 3 
 
 Inhibit byte 2 - permute left 1 
 
 Instruction Register - bit i 
 
 Logic register - output of shift/boolean - bit i 
 
 LR input gating signal: LRN -* LR - byte i 
 
 LR latch, must be for LRN -^ LR - byte i 
 
 Input bus to logic register - bit i 
 
 M counter - bit i 
 
 Permute left i bytes 
 
 Adder Output - equals EQV of DR and DB - bit i 
 
 Exclusive or or equivalence enable (goes to permuter) 
 
 11/5/70 
 
 Section 2.8.2.2 - l/l 
 
2.8.3 Boolean/Shift Logic - PL/l Description 
 
 / / E X F C P L 1 
 I//PL 1 .SYSPUNCH 
 //PL I. SYS IN do 
 KOULSHFT : 
 ANDF, 
 IBPL13, 
 orf, 
 IB, 
 DCL 
 
 no SYsni)T = R 
 
 PROC ( 
 
 CTDF, 
 IBPL21 , 
 RMCT, 
 PL) ; 
 ( ANDF,CTDE, 
 IBPL13, 
 MCTF, 
 
 CTMH2 , 
 
 LRMCTG, 
 
 RSF, 
 
 CTMHZ, 
 IBPL21, 
 
 ORE 
 
 DCL 
 
 DCL 
 
 CTMLZt 
 
 LSF, 
 
 RSPEt 
 
 CTMLZ» 
 
 LRMCTG, 
 RMCT, 
 
 CTUE, 
 
 LSPF, 
 
 CTUE, 
 
 LSE, 
 
 RSE, 
 
 (IB, PL ) (0:3 ) B I T ( 
 
 (DB,DR,LR,LRN) (36) BIT( 1 ) 
 
 (CTU,CTD) STATIC BIT( 1 ) , 
 
 MCT( 1:5) B I T ( 1 ) STATIC; 
 
 BI T ( 1 ) ; 
 
 EXTERNAL ; 
 (CTLZ,CTHZ,CTZ )BIT( 1 ) , 
 
 DLRG, 
 
 MCTE, 
 
 DLRG, 
 LSPE, 
 RSPF) 
 
 BIT( 1 
 
 LRN-'O'B; 
 
 /* 
 
 IF RSF T H F M 
 
 on 1=0 to 3; 
 
 ORAW ING 
 
 oo; 
 
 07-1*/ 
 
 00 J=I*9+1 TO 1*9+8; 
 
 end; 
 
 END; 
 
 LRN( J + l )=LRN( J + l ) | OR ( J ) ; 
 
 00 1=9 TO 36 BY 9; 
 LRN( I )=0R ( I ) ; 
 
 LRN(1)='0'B; 
 
 END; 
 
 E N ; 
 
 IF LSF THEN 00; 
 
 00 1=0 TO 3; 
 
 on j=i*9+i Tn 1*9+8; 
 
 LRM( J-l )=LRM( J-l ) I 0R( J ) ; 
 
 FND; 
 FNO; 
 00 1=9 TU 36 BY 9; 
 
 LRN( I )=0R ( I ) ; 
 
 C 
 END; 
 IF ANOE T 
 
 END; 
 
 LRN(35 )= '0' B; 
 
 "ALL PR INT1 (LRN, » LRN ' ) ; 
 
 /PRESET COUNTER, SELECT COUNT UP n 
 
 / :!: nuAIJTMr. 1 7 _ O ;i 
 
 */ 
 
 iHEN LRN( *)=0R( *) 8DB( *) ; 
 /- :: CALCULATE CONTROL INFORMATION DRAWING 17-1 
 CTMHZ=-.MCT( 5 )£^MCT(4) ; 
 CTMLZ=-.MCT(3) f.-.MCT( 2) £-.MCT( 1 ) ; 
 
 /* LOAD M-COUNTFR FROM THE LR DRAWING 17-1 *, 
 IF LRMCTG THEN DO 1=1 TU 5; 
 
 MCT ( I )=LR ( 1+30) ; 
 END; 
 
 T COUNT UP OR DOWN, AND COUNT */ 
 /* DRAWING 17-2 */ 
 
 */ 
 
 IF RMCT THEN MCT='0'B; 
 IF CTUE THEN 00; 
 
 CTU=« 1 'B; 
 
 CTD= 'O'B; 
 END; 
 
 11/5/70 
 
 Section 2.8.3 - 1/2 
 
IF CTDE THEN DO; 
 CTD=' l'B; 
 
 ctu= , o , b; 
 
 END; 
 
 IF MCTE THEN CALL 
 
 mctr; 
 
 /* nETFRMINE BYTF SHIFTING 
 
 /* DRAWING 
 
 FOR PERMUTER 
 17-1*/ 
 
 */ 
 
 IBPL21=RSPE6MCT(1 )£MCT(2) ; 
 IBPL13 = LSPEf.MCT(l)f»MCT(2) ; 
 PL(0)=-MCT(1 )£-,MCT(2)£(LSPE|RSPE); 
 PL (1 )=LSPE&-MCT( 1)£MCT(2) ; 
 PL(2)=(MCT(1 )&^MCT(2) ) £ ( LSPE I RSPE ) ; 
 PL(3)=RSPEC-.MCT(1)F.MCT(2) ; 
 IB(0)=RSPE&(MCT(1) |MCT(2) >! 
 18(1 )=RSPEf,MCT( 1 ) ; 
 IB(2)=LSPFCMCT(1 ) ; 
 IB(3)=LSPEf>(MCT(l) |MCT(2) ) ? 
 
 DLRG = DLRGlORE"; 
 u i — r p • p k ( ) C * 
 
 DCL (M-tl) FIXFD BIN (5,0), MS BIT(5),0NE FIXED BIN; 
 
 PUT LIST( 'MCTR ENTERED' ) ; 
 
 DNE = 1 ; 
 
 DO 1=1 Tn 5; 
 
 if mct(i) then *m*m+2**(5-i ) » 
 
 end; 
 
 IF CT.U THEN M = M + l; 
 
 IF CTD THEN M=M-1; 
 
 IF M<0 THEN MCT='1'B; 
 FLSE on; , 
 MS = M; 
 
 on 1=1 to 5; 
 
 MCT( I )=SDBSTR(MS,I ,DNE) *, 
 
 END; 
 END; 
 END mctr; 
 
 END BOOLSHFT; 
 
 
 /* 
 
 11/5/70 
 
 Section 2.8.3- 2/2 
 
2 ' Q ' k Boolean/Shi ft Logic - Logical Descrip t.i nn 
 2 ' 8 - I+ - 1 Basic Boolean/Shift Logic 
 
 The basic Boolean/Shift Logic is used to perform the actual 
 boolean and shifting operations on data. This logic is really cuite 
 straight forward. It consists of various sets of gates each of which 
 can be operated separately. Each set has 32 bit positions and the 
 corresponding bit positions of each set are dot-ored together to form 
 a 32 bit input bus (LRNi) to the Logic Register (LR). The flag 
 positions of the input data are handled separately and are also gated 
 to their corresponding positions in the LRNi. 
 
 The various boolean operations are accomplished as explained 
 a Section 2.8.1.1 and are activated by turning on the necessary gate 
 Signals, i.e. XOR/E, EQV/E, AND/E, and OR/E. The shifting operations 
 are performed between the DR and the LR by using a simple gate, but 
 gating each input bit position to the corresponding output bit position 
 which is one place to the right or left. In the case of a right or 
 left shift by one bit, the flags are gated straight through from the 
 DR to the LR without changing position. 
 
 11/17/69 Section 2.8.1..1 - 1/! 
 
2.8.14.2 M-Counter Logic 
 
 The M- Count er , as shown in the TP Logic Book, drawing 17-2, 
 is a double rank, up-down counter with a combination of ripple and 
 lookahead carry logic. The information is stored in the upper rank and 
 can be retrieved in true or complement form. The choice of up or down 
 counting is made by setting the direction flip-flop to either CTU or 
 
 CTD by means of the CTU/E or CTD/E control signals, respectively. 
 
 As in a normal double rank counter, the upper rank, which 
 contains the current state of the counter, is gated into the lower rank 
 of the counter during the time that the M Counter is not counting (i.e. 
 
 MCT/E = l). The output of the lower rank, in turn, is sent to the 
 carry propagation logic which in turn decides what the state of the 
 
 M-Counter will be the next time that MCT/E is activated. However, since 
 
 MCT/E is not active at this time, this result sits at the input of the 
 upper rank until such time as MCT/E goes to (i.e. MCT/E = l). As 
 soon as this happens, the gates to the lower rank close. This ensures 
 that the inputs (and thus the outputs also) of the carry propagation 
 logic will not change. One collector delay later, the output of the 
 carry propagation logic is gated into the upper rank. Thus, provided 
 that there is a sufficient length of time for the carry propagation logic 
 to have settled down after the previous count, a new count value will 
 appear at the output of the "M-Counter 1 collector delay time plus 1, 
 
 260 flip-flop storage time after MCT/E goes to 0. 
 
 The most complicated part of the M-Counter logic is the carry 
 propagation logic. It is also the key to the whole M-Counter operation. 
 Its inputs consist of the 5 data signals from the lower rank of the 
 counter (in both true and complement form), the CTU and CTD signals which 
 
 determine whether we will add 1 or subtract 1, and the MCT/E signal which 
 is inverted and then used to gate the output of the carry propagation 
 logic into the M-Counter' s upper rank. 
 
 As mentioned earlier, the carry propagation logic uses both 
 ripple and lookahead carry propagation techniques. The lookahead is 
 used between bits 1 and 2 and between bits 3, 1+, and 5 where bit 1 is 
 
 10/30/69 Section 2.8.U.2 - 1/7 
 
the high order bit and bit 5 is the low order bit. A ripple carry 
 
 i 
 is performed between bits 2 and 3. 
 
 The carry propagation logic itself can be thought of as two 
 sets of gates which if both are turned on, cause the corresponding bit 
 of the counter to change state.' A simplified logic diagram is shown in 
 Figure 2. 8. h. 2/1. The second gate is activated when the count enable 
 pulse is activated while the first gate is activated by a carry (or 
 borrow) from the previous lower order stage. Note that the inputs to 
 the gate system are arranged so that if either gate is off, the bit 
 represented by the upper rank flip-flop will not change. As can be 
 seen, therefore, the new state will be determined by what appears on 
 the second gate line at each position of the counter. 
 
 In actual fact, the "carry gates" at each counter position 
 are determined by 2 NAND circuits which are dot-ored together, one 
 NAND being activated when the M-Counter is counting up (CTU = l) 
 and the other NAND being activated when.the M-Counter is counting down 
 (CTD =1). The single exception to this scheme is the low order bit 
 position, MCT5, which always changes state when the MCT/E signal goes 
 to regardless of whether CTU or CTD is 1. 
 
 As an example, in the case of a count up, MCTU will change 
 state only if the next lower order position, MCT5, was a 1 during the 
 previous counter state. This is due to the fact that if a 1 is added 
 to the MCT5 position when it is already 1, a carry into position MCTU 
 will result which in turn will cause MCTH to change state. On the 
 other hand in the case of a count down, MCTU will change state only if 
 the next lower order position, MCT5, was a during the previous counter 
 state. This is due to the fact that if a 1 is subtracted from the MCT5 
 position when it is in the state, it will have to borrow from the 
 MCTU position which in turn causes MCTU to change state. The logic used 
 to generate the "carry gate" for position k is shown in Figure 2.8.U.2/2. 
 Note that in Drawing 17-2 of the TP Logic Book the MCT 5 and MCT5 signals ar 
 actually taken from the lower rank flip-flops of the M-Counter. 
 
 For the MCT3 position things become slightly more complicated. 
 In the first place the conditions which determine whether or not MCT3 
 changes state depend on both of the two lower order positions, MCTU and 
 MCT5. In a count up they must both be 1 and in a count down they must 
 
 10/30/69 
 
 Section 2.8.U.2 - 2/7 
 
MCTi 
 
 MCTi 
 
 MCTi MCTi 
 
 Figure 2. 8, k, 2/1 - Simplified Logic for One Position of the M-Counter 
 
 12/16/69 
 
 Section 2.Q.U.2 - 3/7 
 
CTU 
 
 MCT5 
 
 CTD- 
 MCT5 
 
 lt CARRY GATE 
 
 FOR POSITION 4 
 
 Figure 2 
 
 U.2/2 - Carry Gate Logic for Position MCTU 
 
 12/10/69 
 
 Se 
 
 ction 2.8A.2 - U/7 
 
both be in order to produce either a carry into or a borrow from the 
 third position. In Figure 2.8. k. 2/3 the logic used to generate the 
 3rd position "carry gate" is shown. Note that there are actually 2 
 "carry gates", one for each previous position, and that both must be on 
 in order to cause a change of state. Each of these "carry gates" is 
 produced in the same way as the "carry gate" for position MCTU. In fact 
 one of them is actually the same signal as was used in the MCTU position. 
 
 It can be seen from the above description, that if we wanted 
 to use full iookahead, each higher order position of the counter could 
 be constructed by adding an additional "carry gate" and AND'ing it along 
 with all of the previous gates. However this method would create the 
 need for NAND circuits with more and more inputs and since there is no 
 need for the high speed which can be achieved with a full Iookahead counter, 
 it was decided to save logic by using a ripple carry between the 2nd 
 and 3rd positions. 
 
 Using a ripple carry simply means that in the 2nd M-Counter 
 position, instead of looking at the contents of all 3 lower order 
 positions we will simply sit around and wait until the previous logic 
 has decided whether or not the immediately preceding position, MCT3, 
 will have to change state. It is called a ripple carry because if 
 every counter position acted this way we could only find out the new 
 count one bit position at a time beginning at the low order end of the 
 counter, and the new count would "ripple" through to the high order 
 end one bit position at a time. 
 
 If it turns out that the MCT3 position does change state 
 then one of the outputs from the "carry gate" circuits (labelled A 
 and B in Figure 2.8.U.2/1) will be '1' and the other will be '0'. 
 B will be *1' if MCT3 is going from 1 to and A will be '1' if 
 MCT3 is going from to 1. If no change in MCT3 is to occur, both 
 A and B will be 0. Thus the generation of the carry gate for the MCT2 
 position can be accomplished by the logic shown in Figure 2.8.U.2/H. 
 
 Finally the two carry gates for M-Counter position 1 can be 
 generated exactly the same way as for position 3 except that this time 
 the results from position 2 and the ripple results from position 3 are used. 
 
 10/30/69 Section 2.8.U.2 - 5/7 
 
MCT3 
 
 > 
 
 MCT3 
 
 > 
 
 CTU 
 
 MCT4 
 
 CTD 1 
 
 MCT4 
 
 MCT5 
 
 > 
 
 r> 
 
 MCT5 
 
 r> 
 
 Figure 2.8. U. 2/3 - Carry Gate Logic for Position MCT3 
 
 12/10/69 
 
 Section 2. 8.U. 2 - 6/7 
 
CTU 
 A 
 
 O 
 
 CTD 
 B 
 
 CARRY GATE 
 FOR MCT2 
 
 Note: the A and B inputs come from the positions indicated 
 in Figure 2. 8. h. 2/1. 
 
 Figure 2. 8. k. 2/h - Carry Gate Logic for "Ripple Carry" 
 to Position MCT2 
 
 12/10/69 
 
 Section 2.8.U.2 - 7/7 
 

2.9 Algebraic /Logical Compare Logic 
 
 The algebraic/logical compare logic in the TP is used to make 
 comparisons between byte, halfword or word size cells. If it is neces- 
 sary to compare two floating point or BCD numbers, this is done using 
 the Arithmetic Unit. 
 
 Generally speaking the comparisons are made by subtracting and 
 then comparing the result with zero. Therefore the hardware is set up to 
 test the AR for zero. Various groups of bits are tested depending on the 
 cell size and the type of comparison. The sign is also checked to set 
 the "greater" and "less" flip-flops. 
 
 The compare is usually done in two cycles. During the first 
 the "greater" or "less" flip-flops are set according to the signs and 
 the EQ is set to 1 if the AR is zero. In the second cycle, both the 
 "greater" and "less" flip-flops are reset to zero if the EQ flip-flop 
 was previously set to one. 
 
 In the following section the various hardware descriptions are 
 given. The actual sequencing of the various kinds of comparisons is 
 given in Section U.3.2.1. 
 
 I+/7/69 Section 2.9 - l/l 
 

2-9.1 A/L Compare Logic - Functional Description 
 
 The A/L Compare Logic is used to perform algebraic and logical 
 comparisons between two numbers. In an algebraic compare, the numbers 
 are treated as 2's complement numbers with the highest order bit being 
 the sign bit. In a logical compare, the numbers are treated as unsigned 
 positive numbers. 
 
 The logic for the A/L compare is shown in the 05-series of 
 drawings in the TP Logic Book. In order to understand this logic, it is 
 necessary to know how the control logic uses it. The basic comparison 
 method, as previously mentioned in Section 2.9, uses a subtraction. In 
 certain cases this is not necessary since the results of the comparison 
 can be determined directly from the high order bits of the two numbers when 
 these are different. When the sign bits are the same , however , the subtraction must 
 be performed and the proper indicator settings determined from the sign 
 bit of the result. 
 
 Since the cells are right justified and may be either bytes, half- 
 words, or words, the actual sign positions which are used will depend on 
 the cell size. Only the position corresponding to the highest order bit 
 of the present cell size cell is used. 
 
 Figure 2.9-1/1 shows a table giving the algebraic and logical 
 interpretation of the various bit strings in the set of ii-bit binary 
 numbers. Note that if two numbers are interpreted as algebraic they can 
 always be compared by 2 ' s complement subtraction and observation of the 
 sign of the result. This will also hold for logical numbers if both numbers 
 have the same first bit . It will not work if the numbers have opposite 
 high order bits. However, it is exactly this situation which can be pre- 
 dicted without subtraction. In the case of logical numbers the 
 operand with the '1' in the first bit position is larger while in the case 
 of algebraic numbers the operand with the '0* in the first bit is larger. 
 Figure 2.9.1/2 gives the indicator settings for the situation in which 
 both operands have the same high order bit. 
 
 11 A/TO Section 2.9-1 - lA 
 
. Bit Logical 
 
 Algebraic String Interpretation 
 
 Interpretation coring 
 
 -1 
 -2 
 -3 
 
 -5 
 
 -7 
 
 -8 
 
 7 
 
 5 
 
 3 
 
 2 
 1 
 
 
 1110 
 1101 
 
 _u iioo 
 
 _6 1° 10 
 
 1001 
 
 1000 
 
 mi 15 
 
 ik 
 
 13 
 12 
 11 
 10 
 
 1011 
 
 0111 
 
 g 0110 
 
 0101 
 
 li 0100 
 
 0011 
 0010 
 0001 
 0000 
 
 9 
 8 
 7 
 
 Figure 2.9.1/1 - Algebraic and Logical Interpretation 
 of U-Bit Numbers 
 
 Section 2.9-1 - 2 A 
 
Operand Stack: 
 
 ^TOP 
 Compare: A — B 
 
 First gate B -> DR (true); gate A - DB (complemented) 
 Second Form B - A; gate result into AR 
 
 Result in 
 
 AR 
 
 A 
 
 B 
 
 Compa 
 
 y-p A 1 cr 
 
 
 AR >0 (+) 
 
 
 small + 
 
 large + 
 
 < 
 
 Compare I 
 < 
 
 >0 ( + ) 
 
 
 large - 
 
 small - 
 
 
 < 
 
 < 
 
 =0 ( + ) 
 
 
 
 (B=A) 
 
 
 = 
 
 
 <0 (-) 
 
 
 large + 
 
 small + 
 
 
 > 
 
 > 
 
 <0 (-) 
 
 
 small - 
 
 large - 
 
 
 > 
 
 > 
 
 Figure 2.9.1/2 - Setting the GT and LT Flip-Flops When the First 
 Bit of Both Operands is the Same 
 
 7/8/69 
 
 Section 2.9.1 - 3/I4. 
 

 The 05-2 drawing shows the equality compare circuit. After 
 the subtraction this circuit checks for zero in the AE. Note that the 
 cell size signal is used to control which bits are checked. If all of 
 the applicable bits are zero, the EQ flip-flop is set. 
 
 Note that even if the EQ flip-flop is set, one of the GT or LT 
 flip-flops will still be set on the basis of the contents of the AR and 
 DR sign positions. Therefore in this case the RGL/E signal can be turned 
 on and if EQ is on, the GT and LT flip-flops will be reset. 
 
 The flag match logic is shown in Drawing 05-3- It is very 
 simple and merely compares the flags on the DR and DB before the sub- 
 traction takes place. 
 
 The match checking is effected by a gated "equivalence" between 
 the flags of the top and next-to-top operands in the OS. However, since 
 the second from the top operand was gated out in complement form, an 
 "exclusive or" is performed rather than an equivalence; the results are 
 the same, though, since: 
 
 FM = A ¥ B = A B v A B and if C is substituted for A: 
 FM = CB v CB 
 
 If any pair of flags do not match, the FM indicator is not set.^ The final 
 
 step for the main control in these instruction sequences is to "pop" the 
 top cell out of the OS. 
 
 Section 2.9-1 - **A 
 7/8/69 
 
2.9-2 Signal Name Lists for the A/L Compare Logic 
 2.9-2.1 Control Signals 
 
 AUC/G 
 CPA/E/ 
 CPH/E/ 
 CPL/E/ 
 
 FLM/E/ 
 RGL/E 
 RSYS/ 
 TZ/E/ 
 
 Gate AU condition code 
 Algebraic compare enable 
 Hollerith compare enable 
 Logical compare enable 
 Flag match enable 
 Reset GT and LT if EQ = 1 
 Reset system 
 Test zero enable 
 
 6/18/69 
 
 Section 2.9-2.1 - l/l 
 

 
 
2.9.2.2 Internal Signals Used by the A/L Compare Logic 
 
 ARi - Arithmetic Register - bit i 
 
 CSB - Cell size is byte 
 
 CSH - Cell size is halfvrord 
 
 CSW - Cell size is word 
 
 DBi - Distribution bus, from the permuter - bit i 
 
 DRi - Distribution Register 
 
 EQ - Equality flip-flop 
 
 FM - Flags of cells in DR and DB match 
 
 GT - Greater than flip-flop 
 
 LT - Less than flip-flop 
 
 6/18/69 Section 2.9-2.2 - l/l 
 
2.9.3 A/L Compare Logic - 1'L/j Description 
 EXFC PL 1 
 ML 1 .SYSPUMCH HO SYSnilT=H 
 
 •■I i . sys in do * 
 
 Compare: prdu aucg, cpae, cphf, cplf 
 CSB * csh, C sw, eo, GTf 
 
 IT, RCOMFF, RFOS, ROLF, SGTSvSLTS, 
 
 I C t I | 
 
 DCLUUCG, CPAF, CPHF, CPLF, csh, C SH 
 
 ""! E °' GT ' LT, RCOMFF, 
 
 RFOS,RGLF,SGTS,SLTS,TZF) BIT(l) ; 
 DCL( AR,I)K,LK ) ( 36) BIT(l) FXTFRNAl; 
 DC I (I»ZFR0)FIXFD KIN ; 
 IF RCDMFF THEM LT,GT=»0«R; 
 IF FQRRGLE THFN GT= ' 1 ' B; 
 IF I_R(27)£AUCG|SLTS THFN LT='1'B; 
 IF DR(9)f.AlJCG|SGTS THFN GT=»l'ft; 
 IF ( AR (28 I&CSB&CPLE 
 
 I AR( I )f,CSWf.(CPLF ICPAE) 
 I AR( 19)r.CSH£(CPLE ICPAE) 
 I A R ( 3 5 ) £C P H F ) 
 
 THEN GT=« 1«B; 
 
 IF (-AR(28 )SCSBSCPLF 
 
 l-AR( l >fi(CPLE|CPAE)6CSW 
 l-AR( 19)fv(CPLE|CPAE )£CSH 
 I -«AR ( 35 )SCPHE ) 
 
 THEN LT= • 1 • B; 
 
 IF RCOMFFIRFOS THEN FO='l'B; 
 IF -iLR ( 3.6 )-£ AUCG THEN EO= , l , B; 
 IF (CPLEICPAEITZE) THEN DO; 
 
 ZFRO='0'B; 
 
 IF (CSB ICSHICSW) THEM DO 1=28 TO 35; 
 ZFRO=ZERO|AR( I ) ; 
 
 END; 
 
 IF (CSHICSW) THEN 00 1=19 TO 26; 
 
 ZFRO=ZERO| AR( I ) ; 
 END; 
 
 IF CSW THEN DO 1 = 1 TO 17 WHILF (I-, = 9); 
 
 ZFRO = ZFRO | AR ( I ) ; 
 END; 
 
 I F -iZFRO THFN F0= • 1 ' B; 
 END; 
 
 FND COMPARE; 
 
 11/5/70 Section 2.9.3 - l/l 
 
2.10 Cell Size Generator 
 
 The cell size generator is used to drive the cell size sig- 
 nals for the various logic and control groups. These output signals 
 consist of true and complement forms of CSB, CSH, CSW and CSD which 
 indicate byte, halfword, word and double word cell sizes, and CSBH 
 which indicates that the cell size is either a byte or a halfword. 
 Only one of the first four signals will be active at any one time and 
 it is possible that none of them may be on. 
 
 There are four possible determinants for the cell size to be 
 activated: 
 
 1) the field designator bits when interpreted as a cell 
 
 size or immediate address field selector (selector state 00) , 
 
 2) the field designator bits when interpreted as a number type 
 (selector state 01), 
 
 3) the contents of the control cell size flip-flops 
 (selector state 10), or 
 
 h) the four individual cell size control signals (selector 
 state 11 ). 
 
 At any given time the decoding method actually chosen is deter- 
 mined by a four state selector. If the control cell size signals are 
 chosen, and no control cell size signal is turned on, none of the signals 
 will be activated. At most only one of the control cell size signals will 
 be on at any one time. 
 
 In addition to the cell size signals, this block of logic also 
 produces the signals which indicate the number type for arithmetic instruc- 
 tions. The rest of this section gives a more detailed explanation of the 
 various parts of the cell size generator. 
 
 6/19/69 Section 2.10 - l/l 
 
2.10.1 Cell Size Generator-Functional Description 
 
 The main output bus of the Cell Size Generator consists of five 
 signals obtained by dot-or'ing the outputs of several input gating 
 circuits. Each gating circuit transmits data from a different source 
 which is decoded to activate the proper signal(s). The gate signals 
 for the gating circuits are generated by means of decoding logic 
 attached to a selector (see Figure 2.10.1). Two flip-flops are set to 
 one of four possible states by four different control signals. The 
 state is then decoded by a group of NAND's. If the fourth state is 
 set (ll), all of the gates are turned off. 
 
 Note that the 00 state of the selector is actually used to 
 
 activate three possible signals, IMCSS/E, NICSS/E, and CSS/E. These 
 three signals distinguish two possible decodings of the IRT and IR8 bit 
 positions which contain the field designator code. In the 00 state, 
 if there is an immediate address option for the instruction and this 
 
 option is used, then IMM = 1, IMCSS/E = and the following decoding 
 is used: 
 
 IRT 
 
 IR8 
 
 Cell Size 
 
 Immediate Field 
 
 
 
 
 
 halfword 
 
 value field 
 
 
 
 1 
 
 halfword 
 
 link field 
 
 1 
 
 
 
 word 
 
 link-value field 
 
 1 
 
 1 
 
 halfword 
 
 segment name field 
 
 If IMM = then NICSS/E = and the decoding is strictly 
 according to cell size and is as follows: 
 
 RT 
 
 IR8 
 
 Cell Size 
 
 
 
 
 
 byte 
 
 
 
 1 
 
 halfword 
 
 1 
 
 
 
 word 
 
 1 
 
 1 
 
 double word 
 
 11/5/70 Section 2.10.1 - 1/3 
 
MM 
 
 IMM 
 
 > 
 
 IMCSS/E=OCMMM 
 
 NICSS/E =00* IMM 
 
 CSS/E = 00 
 
 r> 
 
 CSF/G = 10 
 
 :3 
 
 NCS/E = 01 
 
 SNCS/S 
 
 NOTE: THE 11 STATE CAUSES ALL GATES TO BE INACTIVE 
 
 FIGURE 2.10.1 
 CELL SIZE GENERATOR GATE SELECTOR 
 
 5/22/69 
 
 Section 2.10.1 - 2/3 
 
Note that 01 and 10 codes are the same whether I MM is on or off. 
 
 Therefore these decoders are driven by the CSS/E signal. IMCSS/E 
 
 and NICSS/E are used to drive the proper cell size signals when IMM = 1 
 and IMM = 0, respectively. 
 
 If the NCS/E signal is turned on, (i.e. the selector state 
 is 01) the cell size signals are determined by the IR7 and IR8 bits 
 which contain a field designator indicating a number type. One of 
 the number type signals will also be turned on in this case. The code 
 is as follows : 
 
 IRT 
 
 IR8 
 
 Number Type 
 
 Cell Size 
 
 
 
 
 
 short fixed 
 
 halfword 
 
 
 
 1 
 
 long fixed 
 
 word 
 
 1 
 
 
 
 floating point 
 
 doubleword 
 
 1 
 
 1 
 
 hollerith 
 
 doubleword 
 
 If the CSF/G signal is turned on, (i.e. the selector state 
 is 10) the cell size signals are determined by the control cell size 
 flip-flops. The coding is the same as that used for the cell size 
 field designator case (lMM=0) except that two control flip-flops 
 take the place of IR7 and IR8. These flip-flops are set in a manner 
 similar to the selector used in the gating signals. 
 
 If the selector is in the fourth state where the three 
 gating signals are off, the cell size signals may be set by using one 
 of the control cell size signals CCSB/E, CCSH/E, CCSW/E, or CCSD/E 
 which will activate the proper cell size signals. 
 
 11/10/70 Section 2.10.1 - 3/3 
 
2.10.2 Signal Name Lists for Cell Size Generator 
 2.10.2.1 Control Signals 
 
 CCSB/E Enable byte output line 
 
 Enable double word output line 
 
 Enable halfword output line 
 
 Enable word output line 
 
 Set cell size control flip-flop to byte 
 
 Set cell size control flip-flop to double word 
 
 Gate control flip-flops to CS generator 
 
 Set cell size control flip-flop to halfword 
 
 Enable decoding of field designator bits as a cell 
 
 size independent of immediate option 
 
 Set cell size control flip-flop to word 
 
 Immediate operand - cell size option 
 
 Control FF indicates instruction uses immediate 
 
 option 
 
 Enable decoding of field designator bits as a 
 
 number type 
 
 No immediate operand - cell size option 
 
 Set CS gate selector off for control signal select 
 
 Set CS gate selector for CSF/G 
 
 Set CS gate selector for CSS/E 
 
 Set CS gate selector for NCS/E 
 
 CCSD/E 
 
 CCSH/E 
 
 CCSW/E 
 
 CSBF/E 
 
 CSDF/E 
 
 CSF/G 
 
 CSHF/E 
 
 CSS/E 
 
 CSWF/E 
 IMCSS/E/ - 
 IMM 
 
 NCS/E 
 
 NICSS/E/ - 
 
 SCSC/S 
 
 SCSF/S 
 
 SCSS/S 
 
 SNCS/S 
 
 7/7/69 
 
 Section 2.10.2.1 - l/l 
 
2.10.2.2 Internal Signals Used by Cell Size Generator 
 
 CSB 
 CSBH 
 CSD 
 CSH 
 
 csw 
 
 FPT/ 
 H0L/ 
 IRi 
 
 LFX/ 
 SFX/ 
 
 Cell size is byte 
 
 Cell size is byte or half word 
 
 Cell size is double vord 
 
 Cell size is half word 
 
 Cell size is word 
 
 Floating point (CSD) 
 
 Hollerith ( CSD ) 
 
 Instruction Register, bit i 
 
 Long fixed (CSW) 
 
 Short fixed (CSH) 
 
 6/19/69 
 
 Section 2.10.2.2 - 1/1 
 
2.10.3 Cell Size Generator - PL/1 Description 
 
 / FXFC PL1 
 
 /PL 1 .SYSPUNCH DO SYSOUT=B 
 
 /PL1.SYSIN DO * 
 
 CSGFM: PROC( CCSBF, CCSDE, CCSHE, CCSWE, CSB, 
 
 CSBEE, CSBH, CSD, CSDEE, CSFG, 
 
 CSH, CSHFE, CSSE, CSW, CSWFF, 
 
 FPT, HDL, IMM, LFX, NCSE, 
 
 SCSCS, SCSFS, SCSSS, SFX t SNCSS); 
 
 OCL (CCSRE, CCSDE, CCSHE, CCSWE, CSB» CSBFEt 
 
 CSBH, CSO t CSDFE, CSFGt CSH, 
 
 CSHFE, CSSE, CSW, CSWFE, FPT, 
 
 HDL , IMM, LFX, NCSE, SCSCS, 
 
 SCSFS, SCSSS, SFX, SNCSS) RIT(l); 
 nCL IR(36) BIT < 1 ) external; 
 OCL (GSEF, /* GATE SELECTOR FLIP-FLOP OUTPUT */ 
 
 CSCEE) /* CELL SIZE CONTROL FLIP-FLOP OUTPUT */ 
 
 (1:2) BIT( 1 ) STATIC, 
 
 (IMCSSE, /* CELL SIZE DETERMINED BY IMM OPTION */ 
 
 NICSSE) /* CELL SIZE DETERMINED WITH IMM OPTION OFF */ 
 
 BITU) ; 
 
 /-RESFT CELL SIZE SIGNALS TO ZERO-/ 
 CSB, CSBH, CSH, CSW, CSD ='0'B; 
 SFT_SELECTOR: 
 
 /* SET CELL SIZE GATE SELECTOR FLIP-FLOP STATES */ 
 
 /* SET GATE SELECTOR FOR CSSE */ 
 
 IF SCSSS THEN DO; 
 GSFF( 1 )='0'B; 
 GSFF(2 )= 'O'B; 
 
 END; 
 
 /* SET GATE SELECTOR FOR NCSE */ 
 
 IF SNCSS THEN DO; 
 
 GSFF( 1 )='0'B; 
 
 GSFF(2)='1»B; 
 END; 
 
 /* SET GATF SELECTOR FOR CSFG */ 
 
 IE SCSFS THEN DO; 
 GSFFd ) = • l'B; 
 
 GSEF (2 )= 'O'B; 
 
 END; 
 
 /* SET GATE SELECTOR OFF FOR CONTROL SIGNAL SELECT */ 
 
 IF SCSCS THEN 00; 
 
 GSFF( 1 )=• 1 «B; 
 
 GSEF (2 )= ' 1 »B; 
 END; 
 
 11/5/70 Section 2.10.3 - lA 
 
FCnr)F 7* F CHEjK R iF FIELD DESIGNATOR BITS ARE TO BE DECODED AS 'A CELL 
 SIZE INDEPENDENT OF IMMEDIATE OPTION */ 
 
 CSSE = -.GSFF(1 )&-GSFF(2) ? 
 
 NICSSE=CSSF&-IMM; 
 IMCSSF = CSSEf.IMM; 
 
 /* CHECK IF CONTROL FLIP-FLOPS ARE TO BE GATED TO CELL 
 GENERATOR */ 
 
 CSFG=GSFF(1 )G-.GSFF(2) ; 
 
 /-CHECK IF FIELD DESIGNATOR BITS ARE TO BE DECODED AS A 
 NUMBFR TYPE */ 
 
 NCSE = -GSFFU )&GSFF(2) ; 
 
 cct fSCFFs 
 
 "/-SET CELL SIZE CONTROL FI IP-FLOP STATES *./ 
 
 /* ENABLE BYTE HOTPOT LINE */ 
 
 IF CSBFE THEN DO; 
 CSCFF( 1 ) = '0«B; 
 
 CSCFF(2)='0'B; 
 
 END; 
 
 /♦.ENABLE HALFWORD OUTPUT LINE */ 
 
 IF CSHFE THEN DO; 
 
 CSCFF( 1 ) = '0'B; 
 CSCFF(2)= , 1'B; 
 
 end; 
 
 /* ENABLE WORD OUTPUT LINE */ 
 
 IF CSWFE THFN DO; 
 
 CSCFFd ) = ' l'B; 
 
 CSCFF(2 )='o«b; 
 END; 
 
 /* EMABLF DOUBLE WORD OUTPUT LINE */ 
 
 IF CSDFE THEN DO; 
 
 CSCFFd ) = »1'B; 
 
 CSCFF(2 ) = • 1 'B; 
 END J 
 
 11/5/TO 
 
 section 2.10.3- 2 A 
 
SET_CFLL_SIZES: 
 
 /* SET CELL SIZES */ 
 
 /* CHECK IF CELL SIZE IS TO BE DETERMINED INDEPENDENTLY 
 OF THE IMMEDIATE OPTION */ 
 
 IF CSSE THEN DO; 
 
 CSH = -»IR(7)£IR(8) ; 
 CSBH = -IR(7) ; 
 CSW=IR( 7)fi-IR(8) ; 
 
 end; 
 
 /* CHECK IF CELL SIZE TO BE DETERMINED BY THE IMMFDIATE 
 OPTION ON #/ 
 
 IF IMCSSF THEN DO; 
 
 CSH = MR(7)&-.IR(8) |CSH; 
 CSW= IR(7)6 IR(8) ICSW; 
 
 END; 
 
 /* CHECK IF CELL SIZE IS DETERMINED BY IMMEDIATE OPTION OFF*/ 
 
 IF NICSSE THEN DO; 
 
 CSB=iIR(7)S-iIR(8) ICSB; 
 CSD= IR(7)S IR(8) ICSD; 
 
 END; 
 
 /* CHECK IF CELL SIZE IS TO BE DETERMINED BY CFLL SIZE CONTROL 
 FLIP-FLOPS */ 
 
 IF CSFG THEN DO; 
 
 CSB = -.CSCFF(1)&-CSCFF(2)|CSB; 
 
 CSH = -.CSCFF( 1 )6 CSCFF(2) ICSH; 
 CSBH= CSCFFd ) ICSBH; 
 
 CSW= CSCFF( 1 )S-.CSCFF(2) ICSW; 
 
 CSD= CSCFF(1)G CSCFF(2) ICSD; 
 END; 
 
 /* CHECK IF FIELD DESIGNATOR BITS ARE TO BE DECODED AS A 
 NUMBER TYPE #/ 
 
 IF MCSF THEN DO ; 
 
 CSH = -iIR(7)GIR(8) |CSH; 
 CSBH = -.IR ( 7)S-»1R(8) ICSBH; 
 CSD= IR (7) ICSD; 
 
 FPT= IR(7)G-.IR(8); 
 HOL= IR(7)G IR(8) ; 
 SFX = MR.(7)G-IR(8) ; 
 LFX = -.IR(7)fi IR(8) ; 
 
 END; 
 
 ELSE FPT,HOL,SFX,LFX='0'B; 
 
 11/5/70 Section 2.10.3 -3 A 
 
/* CHECK IF CELL SIZE IS DETERMINED BY CONTROL */ 
 
 csb=csb!ccsbe; 
 csh=csh|ccshe; 
 
 CSBH=CSBH|CCSHE|CCSBE; 
 
 csw=csw|ccswe; 
 csd=csdjccsde; 
 
 END CSGEN? 
 
 /* 
 
 11/5/70 
 
 Section 2.10.3- *+A 
 
3. INTERFACE TO THE OTHER SUBSYSTEMS 
 
 The purpose of this section of the manual is to briefly describe 
 the other subsystems in Illiac III with which the Taxicrinic Processor 
 comes in contact and to explain in detail the nature of the interactions 
 between these units and the TP. 
 
 There are six other subsystems with which the TP interacts: the 
 Exchange Net , the Storage Units, the Arithmetic Unit, the Input-Output 
 Processor, the Pattern Articulation Unit and the Interrupt Unit. The TP 
 is directly connected to only the Exchange Net and certain lines in the 
 Interrupt Unit. All other communication with processors and units is done 
 through the Exchange Net. 
 
 5/15/69 Section 3 - l/l 
 
3.1 The Exchange Net 
 
 The Exchange Net is depicted in Figure 3.1 as having six Processor 
 ports and eighteen Unit ports. The purpose of the Exchange Net is to pro- 
 vide a 50 bit Processor-to-Unit information path and a 50 bit Unit-to-Processor 
 information path, for every possible Processor-Unit pair. 
 
 5/15/69 Section 3.1 - 1/2 
 

 
 
 
 
 K 
 
 
 
 
 
 
 5 
 
 
 
 
 
 
 
 
 
 in 
 
 
 
 in 
 
 z 
 
 
 UJ 
 
 t 2 i 
 
 
 o o z H 
 
 
 
 
 H <_> UJ wtWHOZ 
 
 
 EFINtTIONS 
 EXCHANGE NET 
 PROCESSOR POR 
 INPUT -OUTPUT 
 TAXICRINC PRO 
 LOCAL EXCHANG 
 UNIT PORT 
 UNIT ADDRESS 
 FAST CORE UNI 
 SLOW CORE UN 
 DICTIONARY COR 
 INTERRUPT UN 
 PATTERN ARTIC 
 ; ARITHMETIC U 
 = NOT ASSIGNED 
 
 
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 Section 3-1 - 2A 
 
3.1.1 INBUS and 0UTBUS 
 
 The fifty bit communication path from any Processor to any Unit 
 is called an INBUS. The fifty bit communication path from any Unit to any 
 Processor is called an 0UTBUS. Each fifty bit INBUS and 0UTBUS word path 
 is divided into bytes and bits as follows: 
 
 
 
 10 
 
 19 
 
 20 
 
 29 
 
 30 
 
 39 
 
 1+0 
 
 1*9 
 
 Byte 
 
 Byte 1 
 
 Byte 2 
 
 Byte 3 
 
 Byte k 
 
 INBUS or 0UTBUS Word 
 
 1 INBUS or 0UTBUS word = 5 Bytes = 50 bits named and ordered as shown. Parity 
 (odd) bits are 19, 29, 39 and ^9; flag bits are 18, 28, 38 and U8 when used. 
 Byte (no flag or parity bits) is called the control byte or control field. 
 Bytes 1, 2, 3 and k are called the data bytes or data field. 
 
 5/15/69 
 
 Section 3.1.1 - 1/1 
 
3.1.2 Principal Parts of the Exchange Net 
 
 The Exchange Net consists of the following parts (see Figures 
 3.1.2/1 and 3-1.2/2: 
 
 1) Six Directors - Each Director, one for each Processor, is 
 actually a Unit Address Decoder. When requesting an INBUS 
 path to a Unit, a Processor must present a request and a 
 Unit Address to the Exchange Net in its INBUS control byte. 
 The Director decodes and stores, in its Unit Address Regis- 
 ter, the Unit Address at request time and sends a request 
 to the selector servicing the Unit specified. 
 
 2) Six Selectors - Each Selector services three units and con- 
 tains a Request Interlock and Processor Priority Logic. In 
 general each Interlock determines which Director requests 
 will be forwarded to the Processor Priority Logic. The Inter- 
 lock scans all the requests sent by the different Directors. 
 It checks for the Unit not busy (Unit Busy = 0) condition for 
 each Unit requested. It is only when this condition, Unit 
 Busy = 0, is satisfied that a request may enter the Processor 
 Priority Logic. The Processor Priority Logic decides which 
 Processor gets an INBUS path to a requested Unit. 
 
 3) Six Select Replies - Each Select Reply area is associated with 
 a particular Processor. It monitors all outputs of the Proces- 
 sor Priority Logic that are associated with a particular Proces- 
 sor. Whenever a Processor secures an INBUS path the Reply 
 logic notes this fact and sends a reply back to the Processor. 
 
 h) Six Local Exchanges - The Units are divided into six groups of 
 three Units each. Each group of three Units is serviced by 
 one Local Exchange. Only one Unit in each group of three may 
 be connected to the INBUS at any particular time and only one 
 Unit in each group of three may be connected to the 0UTBUS, at 
 any particular time. 
 
 7/11/69 Section 3.1.2 - l/k 
 
Each Local Exchange contains three Processor Identifica- 
 tion Registers, i.e. one for each of the three Units it 
 services. When a Processor wins the competition for an 
 INBUS path to a Unit, its identification number is copied 
 into the Unit's Processor Identification Register. When 
 it responds to the Processor, the Unit uses this informa- 
 tion to address the Processor. Each Local Exchange also 
 contains Unit Priority Logic. This logic guarantees that 
 only one of the three Units will be attached to the 0UTBUS 
 at any particular time. 
 
 5) One Inward Crosspoint - Provides a six by six access net 
 of INBUS communications from Processors to Local Exchanges. 
 Gates controlling this crosspoint originate in the Selectors. 
 
 6) One Outward Crosspoint - Provides a six by six access net of 
 0UTBUS communication from Local Exchanges to Processors. 
 Gates controlling this crosspoint originate in the Local 
 Exchanges . 
 
 
 7/11/69 
 
 Section 3.1.2 - 2/U 
 
U ■ UNIT 
 SR ■ SELECT REPLY 
 
 NOTE h THE WMER U ACCOMPANIED BY 2 DOTS 
 BETWEEN 2 LINES OR BOXES INDICATE 
 U SIMILAR LINES OR BOXES NOT f—\. 
 
 show. LiLr 
 
 & 
 
 -_Uft 
 
 LOCAL exchange 
 
 DATA 
 
 #-* 
 
 <J3 
 
 x O 
 
 uj ■< 
 
 era: 
 O uj 
 tot- 
 coz 
 
 UJ — 
 
 u 
 o 
 
 oa 
 
 «. 
 
 J 
 
 M. 
 
 .U. 
 
 INWARD 
 CROSSPOINT 
 
 m 
 
 DIRECTOR 
 
 DIRECTOR 
 
 IGURE S 
 
 .1.2/2 
 
 1 
 
 SELECTOR 
 
 GATE 
 
 .U. 
 
 SR 
 
 .U. 
 
 SR 
 
 UNIT 
 
 EXCHANGE -UNIT 
 INTERFACE 
 
 DATA 
 
 GATE 
 
 REQUEST 
 
 REQUEST 
 
 REPLY 
 
 UNIT BUSY 
 
 Figure 3.1.2/1 - 
 
 Processor to Unit Communication 
 ( INBUS ) 
 
 6/25/69 
 
 Section 3.1.2 - 3/I1 
 
B- 
 
 13 
 
 !Zo 
 
 — go 
 zee o 
 
 ii _ it 
 
 ii 
 
 Stat * 
 I 5 ? 
 
 PBw) 
 
 lf> 
 
 CO 
 
 I 
 
 viva 
 
 31V9^ 
 
 00 
 
 viva 
 
 4f 
 
 o 
 
 lO 
 
 viva 
 
 3 
 
 , 
 
 o 
 
 •H 
 
 o 
 
 •H 
 
 O 
 
 o 
 
 u 
 o 
 
 CO 
 
 en 
 
 a> 
 a 
 o 
 
 o '— 
 
 -p W 
 P 
 
 -p m 
 
 •H EH 
 
 fl p 
 
 P o 
 
 CM 
 CM 
 
 00 
 
 0) 
 U 
 
 I 
 
 •H 
 P>4 
 
 S3<7> 
 
 bfl H 
 
 •H \ 
 Pn CM 
 
 0) H 
 0) • 
 CO OO 
 
 lOViMliM! 
 
 39NVH3X3 - WKS100M 
 
 6/25/69 
 
 Section 3.1.2 - h/h 
 
3.1.3 Standard Signals Used in the Control Bytes of all Processors and Units 
 
 ■;nal Name 
 PREN 
 
 UA1 
 
 UA2 
 
 UA3 
 
 UAU 
 
 ENRP 
 
 Til 
 
 UCO 
 
 UC1 
 
 UC2 
 
 UC3 
 
 UCU 
 
 UC5 
 
 UREN 
 
 ENRU 
 
 TI0 
 
 USO 
 
 US1 
 
 US2 
 
 US 3 
 
 usU 
 
 US 5 
 
 Signal Assertion 
 
 Processor Requests Exchange Net 
 
 Unit Address bit (most significant) 
 " n ii -| 
 
 ti it ii p 
 
 II II II o 
 
 ii it ii ^ 
 
 Exchange Net Reply to Processor 
 
 Transfer Information In 
 
 Unit Command bit 
 " it tt -j 
 
 ti ti tt p 
 
 II tt tt q 
 
 II II tt ^ 
 
 tl tt II q 
 
 Unit Requests Exchange Net 
 Exchange Net Reply to Unit 
 Transfer Information Out 
 Unit Status bit = UB = Unit Busy 
 Unit Status bit 1 = UM = Unit 
 
 Malfunction 
 Unit Status bit 2 = UPE = Unit Parity 
 
 Error 
 Unit Status bit 3 
 Unit Status bit h 
 Unit Status Bit 5 
 
 Signal Type 
 Access 
 
 Transfer 
 Unit Command 
 
 Access 
 Access 
 Transfer 
 Unit Status 
 
 Unit Status 
 
 Unit Status 
 Unit Status 
 Unit Status 
 Unit Status 
 
 Standard signals are assigned to lines of the control bytes as shown in 
 Figure 3.1.3. 
 
 5/15/69 
 
 Section 3.1,3 - 1/2 
 
p 
 
 R 
 
 
 C 
 
 E 
 
 S 
 S 
 
 R 
 
 PROCESSOR-EXCHANGE EXCHANGE 
 
 NET INTERFACE 
 
 PREN 
 
 Til 
 
 NET 
 
 INBUS BIT 
 
 ► 
 
 * I * 
 
 uco 
 
 UNIT-EXCHANGE 
 NET INTERFACE 
 
 PREN 
 
 ENRU 
 
 Til 
 
 UC 
 
 UAO 
 
 UC2 
 
 UA 
 
 UC3 
 
 UA2 
 
 UC4 
 
 UA3 
 
 UC5 
 
 UA4 
 
 8 
 
 * 9 * 
 
 0UTBUS BIT 
 
 « L 
 
 UREN 
 
 ENRP 
 
 TI0 
 
 UB 
 
 = USO 
 
 UM = US I 
 
 UPE 
 
 US2 
 
 UCO 
 
 UCI 
 
 UC2 
 UC3 
 
 UC4 
 
 UC5 
 
 u 
 
 N 
 
 |! 
 T 
 
 
 
 * I* 
 
 UREN 
 
 TI0 
 
 USO = UB 
 
 US3 
 
 US4 
 
 US5 
 
 8 
 
 * 9 * 
 
 USI = UM 
 
 US2=JJPE 
 
 US3 
 
 US4 
 
 US5 
 
 VINDICATES THAT THIS LINE DOES NOT GO THROUGH THE 
 EXCHANGE NET, ie: IS BROKEN. 
 
 Figure 3.1.3 
 
 c t^,,- IC< 
 
 Section 3-1.3 - 2/2 
 
3.1. k Standard Signal Sequencing (Control Byte) 
 
 PREN is a Processor's request for an INBUS path, via the Exchange 
 Net, to a Unit specified in the Unit Address bits UAO-U . The unit address 
 bits must be valid before and 100 nsec. after PREN = 1. Then 100 nsec. after 
 PREN = 1, but before any Til signals are generated, the Unit Address lines 
 may be changed to contain other information, i.e. part of the Unit command 
 field. 
 
 Within the Exchange Net, the requesting Processor must compete 
 
 2 
 with other Processors that may be requesting the use of the same INBUS. 
 
 If the requesting Processor wins the priority competition, its identification 
 
 number is copied into the requested Unit's Processor Identification Register, 
 
 contained within the Exchange Net. The contents of this register are used 
 
 by the requested Unit to specify the address of the requesting Processor 
 
 when the Unit desires to respond. 
 
 When the INBUS path has been secured, the Exchange Net sends a 
 reply, ENRP = 1, back to the requesting Processor. Once ENRP = 1, the 
 Processor may transfer information to a Unit any time it desires to do so. 
 
 When the Processor desires to transfer information, it does so 
 by generating a sequence of Til signals: TIIO, Till, TII2, etc. on the Til 
 line. Associated with each Til signal, there is a discrete amount of informa- 
 tion on the INBUS which must be valid during the time each Til signal is valid. 
 The number and duration of Til signals generated, and the nature of the cor- 
 responding information on the INBUS, when the Til signals occur, is Unit 
 dependent . 
 
 When the last Til signal goes to "0", the Processor releases the 
 INBUS by setting PREN = 0. After the requesting Processor releases the 
 INBUS, the Exchange Net will set the Processor's ENRP = 0. 
 
 1. Processors cannot enter into Priority competition for a requested Unit if 
 that Unit is busy, i.e. UB = 1. 
 
 2. That portion of an INBUS that lies within the Exchange Net is used to service 
 a maximum of 3 Units. An INBUS may be requested by a maximum of 6 Processors, 
 
 5/15/69 Section 3.1.1+ - 1/3 
 
UREN is a Unit's request for an 0UTBUS path, via the Exchange 
 Net, to a Processor specified in the Unit's Processor Identification 
 Register. Except for the IU, this register always contains the identifica- 
 tion number of the Processor that last accessed the Unit via the INBUS. 
 The Processor Identification Registers, for all Units except the IU, are 
 set by the Exchange Net when ENRP goes to »l". The IU has the capability 
 of setting its own Processor Identification Register. 
 
 Within the Exchange Net, the requesting Unit must compete with 
 other Units that may be requesting the use of the same 3 0UTBUS. When the 
 0UTBUS has been secured, the Exchange Net sends a reply, ENRU, back to the 
 requesting Unit. Once ENRU = 1, the Unit may send information to the 
 Processor any time it desires to do so. When the Unit desires to transfer 
 information, it does so by generating a sequence of TI0 signals TI0O, TI01 
 etc. on the TI0 line. Associated with each TI0 signal, there is a discrete 
 amount of information on the 0UTBUS which must be valid during the time 
 each TI0 signal is valid. The number and duration of TI0 signals generated, 
 and the nature of the corresponding information on the 0UTBUS, when the 
 TI0 signals occur, is Unit operation dependent. 
 
 When the last TI0 signal goes to "0", the Unit releases the 0UTBUS 
 by setting UREN = . After the Unit releases the 0UTBUS, the Exchange Net 
 will set the Unit's ENRU = 0. Units holds the 0UTBUS (UREN = l) at 
 least until PREN = UB = . 
 
 UB is a Unit status line. UB = 1 during the Unit cycle time, i.e. 
 from the time the first Til signal goes to "l" until the last TI0 signal goes 
 to "0". Unit operation time begins when the last Til signal goes to "0" and 
 ends when the Unit sets UREN = 1 . The unit operation occurs as a result of a 
 Unit's receiving a Unit command. 
 
 UM is a Unit status line. UM = 1 whenever a condition, associated 
 with the Unit threatens or impairs reliable Unit operation. 
 
 3. That portion of an 0UTBUS that lies within the Exchange Net is used to 
 service a maximum of 6 Processors. An 0UTBUS may be requested by a 
 maximum of 3 Units. 
 
 . ., Section 3.1.U - 2 / 3 
 
 5/15/69 
 
UPE is a Unit status line. All Units will check all INBUS bytes, 
 except byte 0, for correct parity (odd) and set UPE = 1 if an error should 
 occur. All storage Units, drums, disks, tapes, core memories, etc. will 
 also set UPE = 1 should a Parity Error occur during a read operation. 
 
 The remaining sets of signals are peculiar to any Processor and 
 a particular Unit. INBUS bit lines 3-8 are the Unit Status field US0-US5 
 respectively. US0-US2 are the standard Unit Status lines UB, UM and UPE 
 respectively. US3-US5 are optional status lines. 
 
 5/15/69 Section 3-lJ* - 3/3 
 

3.1.5 Exchange Net - TF Interface - General 
 
 The main purpose of the Exchange Net - TP Interface Logic 
 is to provide a smooth transition between the TP control sequence logic 
 and the functions required by the Exchange Net. This logic allows the 
 TP control logic to access the Exchange Net using the same basic prin- 
 ciples that it uses when activating a subsequence, namely initiating an 
 action with a task signal and then waiting for either a normal return 
 or an interrupt return. The Exchange Net-TP Interface logic takes care 
 of generating all of the needed control byte signals and of checking for 
 invalid data or malfunctioning units. 
 
 The EN-TP Interface presently can handle requests for the core 
 units, the AU, the PAU, and the Interrupt Unit. The detailed logic for 
 these various requests will be explained in the relevant subsections of 
 Sections 3.2, 3-3, 3-5 and 3.6, respectively. 
 
 The first set of main input control signals are the Exchange Net 
 Control Byte Enable signals, ENMCB/E, ENACB/E, ENPCB/E and ENICB/E. These 
 signals enable the proper logic to generate the unit addresses as shown in 
 Figure 3.1.6. Note that in the case of the core units, the high order bits 
 of the core address must be decoded to determine the unit address. The 
 ENiCB/E signals also turn on the Processor Request for the Exchange Net 
 signal once the unit address has been generated, and also the logic which 
 keeps track of the length of time that the request has been active. An 
 interrupt will be generated if the TP is not answered within a sufficient 
 length of time. If a valid reply is made by the Exchange Net a proper 
 return signal will be generated by the interface logic. 
 
 The second set of input signals to the EN-TP Interface logic are 
 the unit activate enable signals. Only the Interrupt Unit and the AU 
 make use of these signals at the present time. Their purpose is to gen- 
 erate a unit command on certain bit lines in the INBUS control byte. 
 After this has been done the Til line is turned on to indicate to the 
 unit that a valid command is on the lines and that the unit is to begin 
 
 6/23/69 Section 3.1-5 - 1/3 
 

 Starting Core 
 
 Unit Address Bits 
 
 TTni t 
 
 Address 
 
 0123U 
 
 FC (0) 
 
 0101100 
 
 00000 
 
 FC (1) 
 
 0101101 
 
 00001 
 
 FC (2) 
 
 0101110 
 
 00010 
 
 FC (3) 
 
 0101111 
 
 00011 
 
 SC (0) 
 
 01100 
 
 00100 
 
 SC (1) 
 
 01101 
 
 00101 
 
 SC (2) 
 
 oino 
 
 00110 
 
 SC (3) 
 
 01111 
 
 00111 
 
 DC (0) 
 
 100 
 
 01000 
 
 DC (1) 
 
 101 
 
 01001 
 
 DC (2) 
 
 110 
 
 01010 
 
 DC (3) 
 
 111 
 
 01011 
 01100 
 
 IU 
 
 
 
 
 
 01101 
 
 PAU 
 
 
 OHIO 
 
 (not assigned J 
 
 
 01111 
 
 AUO, AU1 
 
 
 10000 
 
 (not used) 
 
 
 10001 
 
 (not assigned) 
 
 
 
 L INBUS bit 20. INDUS bit hk is the least sign fi ^jt f 3 Zl k 
 addresses. All core addresses are contained in INDUS bytes ,3d 
 Fla* bit positions are not used by the core address field. The most 
 significant bit of a FC address (lU bits is bit 27, of a SC address 
 (16 bits), bit 25, and of a DC address (l8 bits), bit 23- 
 
 Figure 3.1-5 - Unit Address Listing 
 
 6/23/69 
 
 Section 3.1-5 " 2 /3 
 
operation. The replies which might come back are unit dependent and 
 are explained in detail in the respective sections for each unit. 
 
 The EN-TP Interface also nas provision for independent setting 
 of the Til lines for those control sequences wnich send long strings of 
 data over the data lines once the accessing of tne unit has been completed, 
 
 As mentioned previously, the EN-TP interface logic will auto- 
 matically generate an interrupt return in the case of a "no reply condi- 
 tion. In this case it will set the proper interrupt indicators and 
 retain the unit address which caused the "no reply". In the case where 
 the unit malfunction or parity error lines are turned on during the 
 access, the Interface logic will set an appropriate temporary storage 
 flip-flop and turn on the access fail signal, ACFAIL. The control 
 sequence will have to test this line and set the appropriate interrupt 
 indicators, if necessary. Tne unit address will still be in the unit 
 address storage register in the EN-TP Interface Logic, however. 
 
 ll/U/70 Section 3.1-5 - 3/3 
 

 
3.2 The Core Storage Units 
 
 There are three types of Core Storage Units used in the 
 Illiac III system. 
 
 1) FC = Fast Core. This type of core storage has a 
 capacity of 16,381+ memory words and a cycle time 
 of TOO nsec. 
 
 2) SC = Slow Core. This type of core storage has a 
 capacity of 65,536 memory words and a cycle time 
 of 3ysec. 
 
 3) DC = Dictionary Core (read only). This type of core 
 storage has a capacity of 262, lUU memory words and a 
 cycle time of 8ysec. (No regeneration is required.) 
 
 All three forms of storage use the same type of accessing procedure; they 
 are distinguished within the computer only by the unit address which is 
 originally given to the Exchange Net. 
 
 In the Illiac III system there are a maximum of four units of 
 each type of storage. Each unit is self-contained assembly consisting of 
 all registers, timing circuits, power supplies, amplifiers, and interface 
 circuitry necessary for operation of the system and compatibility with 
 the Illiac III environment. 
 
 The standard memory word is 80 bits, consisting of 6h data bits, 
 8 flag bits, and 8 parity bits. This corresponds to an Illiac III double- 
 word cell, augmented by parity bits. Each memory word is divided into 
 eight byte zones which may be read and/or written (if not read-only storage) 
 independently of one another. One parity bit is associated with each byte 
 of the word. Correct parity is odd — the sum of 10 bits in each byte, 
 module 2, is 1 if the byte is error-free. 
 
 1. A core memory word = two data fields. A data field = bytes 1,2,3 and 
 k (bits 10-^9) of one INBUS or 0UTBUS word. One core memory word = 8 
 bytes (0-T) = 80 bits (0-79). 
 
 6/24/69 
 
 Section 3.2 - 1/2 
 
The data input to each storage unit consists of 36 information 
 lines plus U parity lines. The input lines may be time-shared and may 
 send the following information: 
 
 1) 18 address hits and 8 read/write control hits 
 
 2) UO Left Word hits 
 
 3) HO Right Word hits 
 
 In addition to the data input lines there are 10 lines for input control 
 information. This control byte (control field) of an INBUS word, is never 
 stored in any Core Storage Unit. The control bytes are used for accessing, 
 controlling data transmission and transmitting Unit status. The Core Storage 
 Units do not require a Unit command. 
 
 The data output to each storage unit also consists of 36 data lines 
 plus k parity bits . The output lines may be time-shared and may send the 
 following information: 
 
 1) kO Left Word bits 
 
 2) HO Right Word bits 
 
 In addition to the data output lines there are 10 lines for output control 
 information. 
 
 All input signals (control and data) are supplied to the memory 
 on the INBUS of the Exchange Net and all output signals are transmitted to 
 the OUTBUS. The requirements for Processors and Memory Units and the 
 detailed bit- to-bit relations of INBUS and OUTBUS lines are given in the 
 following sections along with a detailed explanation of each signal. Then 
 the Processor-Core Signal Sequencing will be described. The last section 
 deals with the various differences between the three types of core units. 
 
 5/15/69 SeCti ° n 3 ' 2 " 2/2 
 
3.2.1 Requirements for Processors and the Core Storage Unit:.; 
 
 When communicating with the Core Storage Units each Processor 
 must be capable of: 
 
 1) Generating a Til sequence TIIO, Till and TII2 on the Til line 
 of the INBUS control byte. 
 
 2) Transmitting in the INBUS data field during TIIO time: 8 Byte 
 Read /Write bits (BRW 0-7) and an address (ik bits for FC, 16 
 bits for SC, and 18 bits for DC). INBUS data byte 1 (bits 10- 
 17) is used to transmit BRW bits 0-7 respectively. BRW bits 
 0-7 are associated respectively with bytes 0-7 of a memory 
 word. INBUS data bytes 2 (bits 23-27), 3 (bits 30-37) and 
 Mbits U0-1+4) are used to transmit all core addresses. Bit kk 
 of an INBUS word is the least significant bit of all core 
 addresses . 
 
 The transfer of information from an INBUS data byte position 
 during Till or TII2 time, into a data byte position of a core 
 memory word, is conditional on the associated BRW bit being a 
 logical 1. If a particular BRW bit is a logical 0, the con- 
 tents of the associated byte of a core memory word is unchanged, 
 
 3) Transmitting information in the INBUS data field, during Till 
 and TII2 time. 
 
 k) Using a sequence of TI0 signals, TI0O and TI01, in the 0UTBUS 
 control byte, to transfer information from the 0UTBUS data 
 field into its buffer registers. 
 
 When communicating with the Processors each Core Memory Unit must 
 be capable of: 
 
 1) Generating a TI0 sequence TI0O and TI01 on the TI0 line of 
 the 0UTBUS control byte. 
 
 2) Transmitting information in the 0UTBUS data field during TI0O 
 and TI01 time. 
 
 3) Using a sequence of Til signals, TIIO, Till, and TII2, in the 
 INBUS control byte, to transfer information from the INBUS 
 data field into its buffer registers. 
 
 1. DC will not require BRW (zone) bits. 
 
 5/15/69 , Section 3.2.1 - l/l 
 
3-2.2 Input to the S torage Units 
 
 Figure 3.2.2/1 shows the positions of the eight read/write bits 
 and the 18 address bits during the time they are on the input lines. 
 Figure 3.2.2/2 shows the positions of the various control signals in the 
 input control lines to the memory units. The purpose of this section is 
 to explain in detail what these inputs mean. 
 
 The Byte Read/Write information comprises eight (8) bits, 
 BRW. , i = 0, 1,..., 7- 
 
 If BRW. = "1", the ith byte of the selected (addressed) 
 memory word is to be treated in the Clear/Write mode. 
 
 If BRW. = "0", the i th byte of the selected memory word is 
 to be treated in the Read/Restore mode. 
 
 The address information comprises 18 bits, a , a , , ..., a , 
 which is interpreted as the integer double-word address. 
 
 !7 i 
 A = Z 2 a. 
 
 i=0 
 
 Note that, as can be seen in Figure 3.2.2/1, the lower most 3 data bits 
 of the 3 byte address, which in the Illiac III system denote the byte 
 address within a double word, are not even used by the memory. However, 
 they are transmitted by the Taxicrinic Processor anyway. 
 
 The first Transfer Information In signal TIIO, going to a "l" , 
 causes the start of the memory operation cycle. It is only accepted if 
 another memory cycle is not already in progress. The TIIO signal must 
 be on for at least 50 nsec. in order to be definitely accepted by the 
 memory unit . 
 
 U/18/69 Section 3.2.2 - 1/U 
 
BYTE READ/WRITE 
 
 ADDRESS BITS 
 
 r 
 
 r 
 
 BYTE I 
 
 BYTE 2 
 
 BYTE 3 
 
 BYTE 4 
 
 10 
 
 5 °> 
 
 o 
 
 o 
 
 CL 
 
 BYTE NUMBER TO WHICH 
 THIS BRW SIGNAL APPLIES 
 
 10 
 
 o 
 
 o 
 
 Q. 
 
 8 
 
 10 
 
 o 
 
 ?», 
 
 5 O 
 
 Q. 
 
 '10 
 
 '13 °I2 
 
 '14 
 
 '15 
 
 16 
 
 '17 
 
 Figure 3.2.2/1 - Input to the Storage Units: 
 At Time TIIO 
 
 o 
 
 ' 
 
 Section 3.2.2 - 2/k 
 
TP-EN 
 Interface 
 
 PREN 
 (none) 
 
 Til 
 
 (not used) 
 
 (none) 
 
 Exchange Net 
 INBUS Bit No, 
 
 
 
 2 
 3 
 1+ 
 
 5 
 6 
 7 
 8 
 *9* 
 
 Description 
 
 Processor Request to Exchange Net 
 Exchange Net ' s Reply to Unit 
 Transfer Information In 
 
 •Indicates that this line does not go through the Exchange Net 
 
 Figure 3.2.2/2 - Memory Unit INBUS Control Byte 
 
 7/1/69 
 
 Section 3.2.2 - 3A 
 
The BRW and address signals are accepted by the memory if they 
 occur (i.e., reach mid-swing) not later than the time of occurrence of 
 the TIIO signal and remain stable for at least 60 nsec. after the TIIO is 
 accepted. 
 
 There will be three Transfer Information In (Til) signals in 
 each memory cycle. They are used to actively gate information to be 
 written from the INBUS into the memory address and data buffer registers. 
 In order of time of occurrence in the cycle, the three signals are desig- 
 nated TIIO, Till and TII2. These signals are always delivered to the 
 Til line. TIIO starts the memory cycle (as stated previously). 
 
 The widths of the Till and TII2 signals which are acceptable 
 to the memory are between kO and 80 nsec. The expected temporal positions 
 of the leading edges of Till and TII2 (when they occur) relative to the 
 leading edge of the TIIO is 120 and 2^0 nsec, respectively. 
 
 The memory contains internal circuitry for generating the Till 
 and TII2 signals. The occurrence of these signals relative to the occurence 
 of the TIIO can be adjusted to any time between the TIIO and the beginning 
 of the restore/write position of the memory cycle in steps of 25 nsec. 
 Till and TII2 gate information into the memory's data buffer 
 register. Till gates data into the left word of core and TII2 gates data 
 into the right word. In either case, the write information presented to the 
 memory on the U0 data input lines must be physically aligned with the memory 
 digit positions in which the input information is to be stored. This means 
 that it is the responsibility of the calling processor to permute the data 
 boundaries so that it coincides with the double word boundaries of the 
 accessed word in memory. 
 
 5/15/69 Section 3 - 2 - 2 " h/k 
 
3.2.3 Output from the Storage Units 
 
 Figure 3-2.3/1 shows the positions of the various control 
 signals in the output control lines from the storage units. The 
 purpose of this section is to explain in detail what these outputs mean. 
 
 The Transfer Information Out line is used to gate the left and 
 right data words of core into user (processor) data buffers. 
 
 The Unit Request's Exchange Net signal is used in the core to 
 retain the 0UTBUS after Unit Busy = 0, i.e. between cycles. 
 
 The Unit Busy signal is generated by the memory and remains in 
 the "l" state from the time of reception of a TIIO signal until TI01 
 goes to "0". 
 
 The Unit Malfunction signal becomes "l" when any measured 
 temperature or DC voltage substantially exceeds expected tolerances. 
 The signal is intended to indicate that a hardware condition clearly 
 prejudicial to continued operation of the memory has arisen. 
 
 The Unit Parity Error signal becomes "l" if the parity of one 
 or more bytes of the Word in the memory data buffer register has erroneous 
 parity at the beginning of the write/restore portion of the cycle. The 
 signal is generated and transmitted no later than 150 ns. after the write/ 
 restore begins. The signal is reset to "0" by the memory unit at the end 
 of each memory cycle, i.e. when Busy goes to "0". 
 
 Two pulses are used, TI0O and TI01. TI0O = 1 means that the 
 left word of a core address is on the 0UTBUS; TI01 = 1 means that the 
 right word of a core address is on the 0UTBUS, TI0O and TI01 are each 125 
 nsec. wide; they are separated by 100 nsec. in time. 
 
 6/2U/69 Section 3.2.3 - 1/3 
 
Memory- EN 
 Interface 
 
 UREN 
 
 ENRP 
 
 TI0 
 UB 
 
 UM 
 
 UPE 
 
 (not used) 
 
 (none) 
 
 Exchange Net 
 OUTBUS Bit No, 
 
 
 
 2 
 3 
 k 
 5 
 6 
 T 
 8 
 *9* 
 
 Description 
 
 Unit reauests Exchange Net 
 
 Trans, information out 
 Unit busy 
 Unit malfunction 
 Unit parity error 
 
 indicates that this line does not go through the Exchange Net 
 
 Figure 3.2.3/1 - Memory Unit OUTBUS Control Byte 
 
 7/1/69 
 
 Section 3-2.3 - 2/3 
 
At information ready time (data register is reliable for 
 
 reading) the core requests (Unit-Requests-Exchange-Net on line of 
 the OUTBUS) the Exchange Net. After the Exchange Net sends a reply 
 
 back to core, (Exchange Net-Reply-to-Unit on line 1 of the INBUS) 
 the core responds. Two TI0 signals, TI0O and TI01 , are sequenced on 
 the TI0 line (2) of the OUTBUS. When TI0O = 1 the left data word is on 
 the OUTBUS. TI0O and TI01 are equal to 1 for 125 nsec. each; they are 
 separated by 100 nsec. 
 
 When TI01 -> 0, Unit Busy -> and the core is ready to be 
 cycled again. Once the response logic of the core secures the OUTBUS, 
 it will not release it until (Unit Busy = 0). (Processor Requests 
 Exchange Net = , on line of the INBUS ). This technique allows a user 
 (Processor) to transfer (read or write) in a burst mode if desired, i.e. 
 the Exchange Net is accessed only once and the INBUS and OUTBUS are not 
 released until all data transfers are complete. 
 
 h/lQ/69 Section 3.2.3 - 3/3 
 

3.2. k Processor-Core Memory Unit Signal Sequencing 
 
 A core cycle is started when TIIO initially goes to a logical 
 1. During the time TIIO = 1 the core address and BRW 0-7 are gated, 
 from the INBUS data field, into their respective buffer registers, within 
 a Core Memory Unit. 
 
 During the time Till = 1, the contents of bytes 1 (bits 10-19), 
 2 (bits 20-29), 3(bits 30-39), and U(bits U0-U9), of the INBUS data field 
 are gated into bytes 0(bits 0-9), l(bits 10-19 ), 2 (bits 20-29), and 
 3(bits 30-39) > respectively, of a Core Memory's data buffer. 
 
 During the time TII2 = 1, the contents of bytes l(bits 10-19), 
 
 2(bits 20-29), 3(bits 30-39), and U(bits U0-U9), of the INBUS data field 
 
 p 
 are gated into bytes U(bits U0-U9), 5(bits 50-59), 6(bits 6O-69), and 
 
 7(bits 70-79), respectively, of a Core Memory's data buffer. 
 
 Till and TII2 will not be required for the Dictionary Core (DC). 
 
 After TII2 time a core is ready to transfer information back 
 to the requesting Processor. A core transfers information back to a 
 requesting Processorby generating a sequence of TI0 signals TI0O and TI01. 
 
 During the time TI0O = 1, the contents of bytes 0(bits 0-9), 
 l(bits 10-19), 2(bits 20-29), and 3(bits 30-39), of a Core Memory's data 
 buffer are contained in bytes l(bits 10-19), 2 (bits 20-29), 3 (bits 30-39), 
 and Mbits U0-U9), respectively, of the 0UTBUS data field. 
 
 During the time TI01 = 1, the contents of bytes U(bits U0-U9), 
 5(bits 50-59), 6(bits 6O-69), and 7(bits 70-79) of a Core Memory's data 
 buffer, are contained in bytes l(bits 10-19), 2(bits 20-29), 3(bits 30-39) 
 and Mbits I+O-U9), respectively, of the 0UTBUS data field. 
 
 1. Conditional on BRW bits 0-3. 
 
 2. Conditional on BRW bits U-7 
 
 U/I8/69 Section 3.2.U - 1/1 
 

 
3.2.6 Exchange Net-TP Interface for the Memory Units 
 
 The purpose of this part of the Exchange Net-TP Interface 
 Logic is to provide the needed control signals so that the memory 
 sequences can easily communicate through the Exchange Net to the core 
 memory units . The memory units are harder to control than the other 
 units for two reasons: 
 
 1) There are more of them. This means more logic is 
 needed simply to generate all of the unit addresses 
 which might be used. 
 
 2) Their timing is much more critical. Since they are 
 essentially synchronous devices the commands and data 
 being sent to them must appear at fairly accurately 
 specified times in relation to one another. 
 
 The first memory-related Exchange Net control signal is the 
 Exchange Net Memory Control Byte Enable signal, ENMCB/E. This signal 
 enables the logic which decodes the high order bits of the core address 
 and determines the unit address which must be placed on the INBUS control 
 byte (see Figure 3.1.6 for the listing of unit addresses). It also turns 
 on the Processor Request to the Exchange Net, once the unit address is 
 valid. At this time it also turns on the TIIO signal so that the memory 
 cycle will begin as soon as the path through the Exchange Net has been 
 cleared. This can be done in the case of the core memories since there 
 are no unit commands which must be sent and the other data needed by the 
 memory (i.e. address and read/write byte) is already valid at the time 
 the path is completed. 
 
 Finally the ENMCB/E signal activates the timing logic which keeps 
 track of the length of time the request has been active. This logic 
 basically consists of a pair of control points which turn the input count 
 signal of an 8-bit IC counter on and off. The desired length of time can 
 
 6/23/69 Section 3.2.6 - 1/3 
 
In 
 
 be measured by waiting for a pre-determined state of the counter 
 order to minimize the logic needed only a few high order hits of the 8 
 bit counter need be used. If the counter reaches this state before the 
 Exchange Net replies, the interface logic automatically cancels the 
 request, turns on the appropriate interrupt indicator, activates the 
 interrupt return signal, and turns on the Exchange Net No Reply signal, 
 XNNRP, which is used to turn off the activated control point. 
 
 Under normal circumstances the Exchange Net will send a reply 
 to the TP indicating that the path to the unit has been completed. When 
 this happens the interface logic will generate the XNRET signal which may 
 be used by the memory sequence to initiate any operations which might have 
 to take place before data from the sequence is returned, or in the case of 
 a write sequence, to initiate transmission of the data to be written. The 
 interface logic also insures that the TIIu signal is automatically turned 
 off an appropriate amount of time after the memory cycle has started. 
 
 Finally the interface logic resets the timing logic and begins 
 timing tne length of time for the unit to respond. If this does not occur 
 within the prescribed length of time, an interrupt is generated in a man- 
 ner analogous to the Exchange Net timing interrupt and tne Memory Unit No 
 Reply Signal, mUNRP, is turned on. In a read access, this signal is used 
 to turn off the control point which is currently waiting to store the 
 returning data into a register. In a write access the signal is sent Dack 
 to a null control point occurring immediately after sending tne second 
 data word to be written. This control point waits for either a data 
 ready signal from the memory unit (signifying that the unit is operating 
 and has reached the write portion of the memory cycle) or the MUNRP signal. 
 
 If more data is to be sent to the memory, as in the case of a 
 write command, it is the responsibility of the control sequence to see 
 that it is placed on the INBUS at the proper time. The Exchange Net Logic 
 can be used to transmit the information once it is on tne cable drivers to 
 
 ; ,, Section 3-2.6 - 2/3 
 
 7/1/69 
 
 k 
 
the Exchange Net by activating the TII/E signal which will turn on the 
 Til signal. The interface logic produces a delayed signal, TIID, which 
 can be used by the control point which generated Til/E to turn itself off 
 after Til has been on for the proper length of time. 
 
 When the last piece of data has been sent to the memory unit, 
 the control sequence must turn on the Exchange Net Release Signal, 
 XNREL wnich will cause the processor request to the Exchange Net to 
 turn off. 
 
 If and when the memory sends data to the TP, it will activate 
 the TIO control line on the OUTBUS control byte. The Exchange Net-TP 
 Interface uses this signal to produce several control signals for the TP 
 memory control sequence. 
 
 Since the read sequence must know which data word is being sent 
 back, i.e. the first or second, the interface logic uses two flip-flops, 
 MDAT1 and MDAT2, which are turned on when the first and second data words, 
 respectively, arrive. These flip-flops are reset the next time an access 
 is made to the Exchange Wet. It is important to note that there is a 
 built-in delay between the time there is valid data on the lines coming 
 from the memory and the time the MDAT1 or MDAT2 signals are sent to the 
 memory control sequence logic. This allows time for the data to be 
 gated into the desired register. The detailed operation is explained 
 in Section 4.1.3.6, the Read Access Control Logic. 
 
 If at any time after the Exchange Net has established the path, 
 the memory unit signals that a memory malfunction or parity error has 
 occurred, the interface logic will set a temporary storage flip-flop and 
 turn on the access failure line, ACFAIL. This signal must be tested by 
 the memory control sequence after it has completed an access. If it is 
 on, the control sequence must set the proper interrupt indicator, using 
 the two temporary storage flip-flops and then transfer control to the 
 Memory Interrupt Sequence. 
 
 7/1/69 Section 3.2.6 - 3/3 
 
3.3 The Arithmetic Units 
 
 The two identical Arithmetic Units (AU's) perform most of the 
 arithmetic operations in the Illiac III system. The exceptions are integer 
 addition and subtraction as well as several unary operations which are 
 executed by the Taxicrinic Processors. 
 
 The prime responsibility of the Arithmetic Units is the high- 
 speed execution of floating point arithmetic operations. The units also 
 provide facilities for integer multiplication and division and conversion 
 from one number-type to another, e.g. floating to long fixed. 
 
 As in the case with the other units in the system, communication 
 with the processors is via the Exchange Net. The AU's interact pri- 
 marily with the TP's although paths are also available between the AU's 
 and the I/O Processor. The Exchange Net assigns an AU to a requesting 
 processor and also makes certain that the results of an arithmetic opera- 
 tion are returned to the processor which initiated the operation. The 
 position of the AU's in the overall system is shown in Section 1.1 in 
 Figure 1.1. 
 
 The execution of an arithmetic instruction begins in a Taxicrinic 
 Processor. If the TP determines that the AU is required to execute the 
 operation, it sends a request to the Exchange Net which locates and assigns 
 an AU which is not in use. The TP then sends the AU a control byte and h 
 data bytes. The control byte contains the instruction variant ( add, subtract , 
 etc.) and the number type (fixed, floating, or decimal). Since in general 
 the operands will occupy more than h bytes , several data transmissions will 
 need to take place. The AU, based on a rapid decoding of the control byte, 
 will load the data as it is received into the proper AU registers. 
 
 5/8/69 Section 3.3 - 1/2 
 
When all of the operands have been sent, the Processor breaks 
 its link with the Exchange Net and the AU executes the instruction. When 
 the execution is finished,the AU notifies the Exchange Net which in turn 
 accesses the TP which made the original request. The result is then returned 
 one word at a time to the TP. If an error condition such as overflow has 
 occurred, a bit is set in the control byte accompanying the result and a 
 flag designating the nature of error is set in the data. 
 
 A more detailed description of the input and output operations in 
 the AU will be given in the following sections. 
 
 The expected execution time for floating point (56 bit mantissa) 
 addition, subtraction and multiplication in 3-6 ysec. For floating point 
 division, the expected execution time will be 8-9 ysec. These operations 
 are not interrupt able. However, POLY, the multi-cycle polynomial evalua- 
 tion instruction can require tens of microseconds and therefore is 
 interruptable by the Exchange Net. 
 
 d 
 
 5/8/69 
 
 Section 3-3 - 2/2 
 
3.3.1 Input to the Arithmetic Units 
 
 The structure of the control byte which is sent to an Arithmetic 
 Unit when its services are needed is shown in the table in Figure 3.3.1/1. 
 A brief description of each signal name is given in the table in Figure 
 3.3.1/2. The nomenclature is consistent with that defined in File No. 790, 
 "A Discussion of Illiac III Processor-Unit Communication via the Exchange 
 Net". 
 
 Assuming that the reader is now familiar with the signal names , 
 the next section describes the signal sequencing for a TP to AU transmission. 
 
 Having recognized the need for an AU, a TP sets PREN = "l" with 
 the Unit Address bits 5-8 of TP-EN Inbus Interface) set to 1111 = 15,q. The 
 unit address must be valid before, and 100 nsec. after, PREN = 1. One hundred 
 nsec. after PREN = 1 but before any Til signals are generated, the unit 
 address lines are changed to contain instruction variant and number type 
 information. 
 
 Within the Exchange Net, the TP is assigned to an AU and the TP 
 identification number is copied into the assigned AU Identification Register 
 (contained within the EN). The contents of this register are used by the AU 
 in returning results to the TP which requested it. 
 
 When the INBUS path to an AU has been secured, the Exchange Net 
 sends a reply, ENRP = 1, back to the requesting TP. Once ENRP = 1 the TP 
 may transfer information to the AU at any time it is available. The TP 
 transfers operands by generating a sequence of Til signals TIIO, Till, TII2 , 
 TII3, on the Til line. Associated with each Til signal is a full word of 
 data and one control byte on the INBUS which must be valid during the time 
 each TII signal is valid. The initial design values for the timing rela- 
 tionship between valid data and the TII signals are given in Figure 3.1.1/3- 
 
 5/12/69 Section 3.3.1 - 1/6 
 
TP - EN 
 
 Exchange 
 
 Net 
 
 AU - EN 
 
 Interface 
 
 INBUS Bit 
 
 
 * 1 * 
 
 No. 
 
 Interface 
 
 
 PREN 
 
 PREN 
 
 (none) 
 
 ENRU 
 
 Til (Transfer Information In) 
 
 2 
 
 
 Til 
 
 IVO = UCO 
 
 3 
 
 
 IVO 
 
 IV1 = UC1 
 
 h 
 
 
 IV1 
 
 IV2 = UC2 
 
 5 
 
 
 IV2 
 
 IV3 = UC3 
 
 6 
 
 
 IV3 
 
 NTO = UCU 
 
 7 
 
 
 NTO 
 
 NTl = UC5 
 
 8 
 * 9 * 
 
 
 NTl 
 
 (none) 
 
 IAUO 
 
 ^Indicates that this line does not go through the Exchange Net 
 
 Figure 3.3.1/1 - INBUS Control Bit Assignment 
 
 5/13/69 
 
 Section 3-3.1 - 2/6 
 
Name 
 
 Description 
 
 Equivalent Name in 
 AU Documentation 
 if Different 
 
 PREN * 
 ENRU * 
 Til * 
 IV 
 
 n 
 
 NT 
 
 UC * 
 n 
 
 IAUO 
 
 Processor Requests Exchange Net 
 
 Exchange Net Reply to Unit 
 
 Transfer Information In 
 
 Instruction Variant, Bit n 
 
 Number Type , Bit n 
 
 Unit Command, Bit n 
 
 (These bits are assigned to 
 
 instruction variant and number 
 
 type bits as shown in Figure 3-3.1/^ 
 
 during TP to AU transmission. ) 
 
 Interrupt AU 
 
 AU Request 
 
 In Info Ready 
 
 Interrupt 
 
 *Standard Signals used in control bytes for all Processors and Units 
 See DCS File No. 790. 
 
 Figure 3.3-1/2 - Description of INBUS Control Signals 
 
 5/13/69 
 
 Section 3-3.1 - 3/6 
 
Data Valid at 
 EN - AU 
 Interface 
 
 TIIO 
 
 FIRST DATA WORD: 
 300 ns 
 
 2U0 ns 
 
 -1 
 
 60 ns_ 
 
 Data Valid at 
 
 EN - AU 
 Interface 
 
 Til n 
 for n > 
 
 SUCCEEDING DATA WORDS: 
 220 ns 
 
 160 ns >h^° nS 
 
 Figure 3.3.1/3 - Relative Timing Between Valid Data 
 on INBUS and Til 
 
 5/19/69 
 
 Section 3.3-1 - U/6 
 
data must be valid longer for the first transmission since the 
 instruction variant and number type must be decoded prior to the loading 
 of the data (the IV and NT codes are given in Figure 3.1-lA). This 
 case is illustrated at the top of Figure 3- 1.1/3- The timing for all 
 successive transmissions is shown at the bottom. In both cases, the 
 data must remain valid at least 60 ns . after the Til is turned off. The 
 minimum interval required between successive Til pulses is only about 20 
 nsec, however in practice the TP cannot supply operands this rapidly. 
 There are no bounds on the maximum duration of this interval. It is 
 anticipated that emperical fine-turning will reduce these duration require- 
 ments by 50$. 
 
 With the exception of POLY, the AU knows how many transmissions 
 to expect based upon a decoding of the order (IV and NT). When the correct 
 number has been received the AU begins execution. In the case of POLY, 
 the TP must maintain the count of the number of coefficients sent. The 
 last coefficient is sent to the AU with the IV field all l's. When the 
 last Til signal goes to 0, the TP releases the INBUS by setting PREN = 0. 
 The Exchange Net in turn sets the TP's ENRP = 0. 
 
 The remaining signal in Table 3.1.1/1 to be discussed is IAU0. 
 This interrupt line is used in the case in which both AU's are performing 
 POLY orders in conjunction with two TP's and a third TP requires the use 
 of an AU. In this case, the Exchange Net will set IAU0 = 1 to interrupt 
 AU number 0. This unit will then return a partial result to the calling 
 TP and next accept the pending order. The TP holding the uncompleted 
 POLY will initiate a request to the EN for an AU to complete the work and 
 the request will be granted when either AU is free. 
 
 6/2U/69 Section 3-3.1 - 5/6 
 
IV Bit No. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 ORDER 
 
 Not used 
 CYL 
 CVF 
 CVD 
 
 NEG 
 ABS 
 MNS 
 TA 
 
 ADD 
 
 Not used 
 
 SUB 
 
 CPRA 
 
 MPY 
 
 POLY Note : End of POI 
 indicated by 111] 
 
 Not used (Except as 
 indication of end of P( 
 
 NTO NT1 
 
 
 1 
 
 1 
 1 1 
 
 Number Type 
 S. Fixed 
 L. Fixed 
 Floating 
 Decimal 
 
 Figure 3.3.1 A - Instruction Variant Code for Arithmetic Operations 
 
 5/1U/69 
 
 Section 3-3.1 - 6/6 
 
3.3.2 Output from the Ar it timet ic Units 
 
 The structure of the control byte which is returned to a TP 
 from an AU is shown in the table in Figure 3-3.2/1. A brief description 
 of each signal name is given in the table in Figure 3.3.2/2. The nomen- 
 clature is consistent with that described in Department of Computer Science 
 File No. 790. 
 
 When the AU has results to return to the calling TP, the signal 
 UREN is set to 1 and the EN makes a path to the TP specified into the AU 
 Processor Identification Register. This register contains the identifica- 
 tion number of the TP that last accessed the AU. When the return path is 
 made, ENRU (in the INBUS, Figure 3.1.1/1) is set to 1. The AU may then 
 transfer information by placing valid data on the 0UTBUS and generating 
 the appropriate sequence of TI0 signals. An AU returns either 1 or 2 words 
 When the last TI0 signal goes to 0, the AU may release the 0UTBUS by 
 setting UREN = 0. The Exchange Net will then set the AU's ENRU = 0. 
 
 When AU #0 is interrupted during a POLY order, the partial 
 result will be returned to the TP as described above except that MCI = 1, 
 indicating that the order has not been completed. The fact that AU#0 was 
 executing a POLY order is transmitted to the Exchange Net by UMC = 1. 
 
 If a Unit Malfunction such as low-voltage is detected in the 
 course of executing an AU order, UM will be set to 1. An error in the 
 result caused by improper format of operands or results out of bounds will 
 set the BR (Bogus Result) bit. A more specific indication of the nature 
 the error condition is given by the flags of result as shown in Figure 
 3.3.2/3. 
 
 The signal UB is set to 1 by the AU as soon as the pending AU 
 order is decoded. Being a 1 , it prevents the Exchange Net from assigning 
 it to another AU prior to completion of the present order. 
 
 5/13/69 Section 3.3-2 - 1/5 
 
TP - EN 
 Interface 
 
 UREN 
 
 
 ENRP 
 
 
 TI0 
 
 
 UB = 
 
 USO 
 
 UM = 
 
 US1 
 
 UPE 
 
 = US2 
 
 UMC 
 
 = US3 
 
 MCI 
 
 = usU 
 
 BR = US5 
 (none) 
 
 Exchange Net 
 
 AU - EN 
 
 0UTBUS Bit No. 
 
 Interface 
 
 
 
 UREN 
 
 * 2. * 
 
 (none) 
 
 2 
 
 TI0 
 
 3 
 
 UB 
 
 h 
 
 UM 
 
 5 
 
 UPE 
 
 6 
 
 US3 = UMC 
 
 T 
 
 USU = MCI 
 
 8 
 
 US5 = BR 
 
 * 9 * 
 
 (none) 
 
 indicates that this line does not go through the Exchange Net. 
 
 Figure 3.3.2/1 - 0UTBUS Control Bit Assignment 
 
 
 5/13/69 
 
 Section 3-3.2 - 2/5 
 
Name 
 
 UREN * 
 ENRP * 
 TI0 * 
 
 UB 
 
 UM 
 
 UPE 
 
 UMC 
 
 MCI 
 
 BR 
 
 US * 
 n 
 
 Description 
 
 Unit Requests Exchange Net 
 Exchange Net Reply to Processor 
 Transfer Information Out 
 Unit Busy- 
 Unit Malfunction 
 Unit Parity Error 
 Unit Multi-Cycle 
 
 Multi-Cycle Interrupt (to notify 
 TP that the AU it has been using 
 has been interrupted). 
 
 Bogus Result 
 
 (Indicates to the TP that 
 
 the result is incorrect . The 
 
 TP determines the nature of the 
 
 error from the flags of incorrect 
 
 result) . 
 
 Unit Status, Bit n 
 (These standard signals are 
 assigned to specific status 
 signals as shown in JFigure 3.3.2/1 
 
 Equivalent Name in 
 AU Documentation 
 if Different 
 
 Exchange Request 
 
 Out Info Ready 
 
 Parity Error 
 Multi-Cycle in progress 
 
 *Standard signals used in the control bytes of all Processors and Units 
 See DCS File No. 790. 
 
 Figure 3-3.2/2 - Description of 0UTBUS Control Signals 
 
 5/13/69 
 
 Section 3-3.2 - 3/5 
 
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 CD 
 
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 5/1U/69 
 
 Section 3-3.2 - U/5 
 
When improper parity occurs in any bytes of the operands , a 
 flip-flop is set but loading of the operands continues. On completion 
 of the loading, the AU does not, however, begin executing the order. It 
 rather jumps to the 0UTBUS sequence and returns a one word pseudo result 
 (all O's) to the calling TP with the UPE bit set to 1. The AU will then 
 reset as if the order had been successfully completed. The TP can 
 initiate appropriate recovery action which may include reattempting 
 execution of the order. 
 
 6/2k/69 Section 3-3.2 - 5/5 
 
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