UNIVERSITY OF 
 ILLINOIS LIBRARY 
 
 At urbanA'Champaign 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/blocksumregister890maja 
 
Hip 
 
 /, Report No. UIUCDCS-R-77-890 
 
 ^iati 
 
 i 
 
 UILU-ENG 77 17^6 
 
 BLOCK SUM REGISTER AND BURST ARITHMETIC 
 BY 
 James Hsioh-Cheng Ma 
 
 August, 1977 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, ILLINOIS 
 
 The Library of the 
 
 NOV 2 1977 
 
 University of Illinois 
 at lirhana-Chamr 
 
UIUCDCS-R-77-890 
 
 BLOCK SUM REGISTER AND BURST ARITHMETIC 
 BY 
 JAMES HSIOH-CHENG MA 
 
 August, 1977 
 
 Submitted in partial fulfillment of the requirements 
 for the degree of Master of Science in Electrical Engineering 
 in the Graduate College of the 
 University of Illinois at Urbana-Champaign, 1977 
 
Ill 
 
 ACKNOWLEDGMENT 
 
 The author wishes to thank his advisor, Professor W. J. Poppelbaum, 
 for his advice and guidance on the project. He also wishes to thank the 
 members of the Information Engineering Laboratory for their advice and 
 friendship. Special thanks are due to Ehud Bracha for his invaluable aid 
 in the final phase of this project. Finally, the encouragement and support 
 of the author's family has been indispensable and is deeply appreciated. 
 
IV 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1 . INTRODUCTION 1 
 
 2. THE BLOCK SUM REGISTER 3 
 
 2.1 Current Summing Register 3 
 
 2.2 Charge Summing Register 3 
 
 2.3 Load Current Register 6 
 
 3. A BURST ARITHMETIC UNIT 9 
 
 3.1 Burst Addition 9 
 
 3.2 Burst Subtraction H 
 
 3.3 Burst Multiplication H 
 
 3.4 Reciprocal 14 
 
 3.5 Burst Division 14 
 
 4. PHYSICAL LAYOUT AND OPERATION OF THE AU 17 
 
 5. CONCLUSIONS 18 
 
 LIST OF REFERENCES 19 
 
 APPENDIX 
 
 Signetics 8273 Specifications 20 
 
 Photograph of the AU 24 
 
1 . INTRODUCTION 
 
 The purpose of this thesis is to develop a simple Block Sum Register and 
 to construct an arithmetic unit capable of addition, subtraction, multipli- 
 cation, reciprocal, and division using the Block Sum Register. 
 
 Burst processing is a method of information representation and process- 
 ing developed by Dr. W. J. Poppelbaum (1). Burst processing has been shown to 
 be useful fo^ video and audio signal processing. The main idea of burst pro- 
 cessing is to represent information by blocks or bursts of unweighed binary 
 digits and to perform simple, low precision processing on these blocks. 
 Figure 1 shows the representation of numbers by a block of length ten. Note 
 that only the number of ones in the block determine the value represented, 
 not the position within the block. Higher precision can be obtained, as 
 shown in Figure 1, if the average of the successive blocks are taken. There- 
 fore, to represent a number to 1% precision, ten bursts of length 10 each 
 will suffice and .1% precision will then require one hundred bursts of length 
 10 each. 
 
 Bursts of length 10 are convenient for decimal arithmetic and will be 
 assumed for the rest of the paper. It is obvious that a single burst can 
 represent eleven numbers from to 1.0 in increments of .1 and thus is 
 capable of approximating a value between and 1.0 to 10% precision. This 
 inherent coarseness of the burst representation results in greatly simplied 
 arithmetic circuitry. The trade off for this simplicity is that burst 
 encoding has lower information capacity than weighed binary: a single burst 
 can represent 11 values, whereas 10 bits of weighed binary can represent 2 
 values. 
 

 
 
 
 
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2. THE BLOCK SUM REGISTER 
 
 2.1 Current Summing Register 
 
 The Block Sum Register or BSR is a device defined to yield a quantized 
 analog output proportional to the number of ones in a block of length N. 
 Figure 2 shows the BSR and an implementation for a BSR of length 10 using a 
 10 bit shift register driving 10 current sources. This implementation is 
 essentially a current summing digital to analog converter with equally 
 weighted resistors instead of binary multiple resistors. Large output step 
 sizes are possible with this design since the base voltage of each current 
 source is a minimum of 3.5 volts. The burst can also be held in the shift 
 register with the clock stopped without affecting the BSR output. In 
 practice the current sources require close matching of the transistors, 
 which suggest monolithic transistors, and/or variable resistors in order to 
 assure uniform step sizes. 
 
 2.2 Charge Summing Register 
 
 A different approach to implementing a BSR results in some reduction in 
 complexity and weighted binary output rather than analog output. This would 
 be desirable in interfacing burst and binary processing. Since the number 
 of ones in the shift register can be determined by summing the number of 
 ones entering the shift register and then subtracting the number of ones 
 leaving the shift register, only the first and last bit of the shift 
 register need be examined. Figure 3 shows an implementation based on 
 considering each one to be a unit of charge and using a capacitor to store 
 
/*■ 
 
 - X 
 
 N 
 
 x x x • • • • • x n _ 2 x n _. 
 
 X n 
 
 10 BIT SHIFT REGISTER 
 
 REF 
 
 ♦ * 
 
 R £R £R £R <"R ^R 
 
 SHIFT 
 OUTPUT 
 
 X V 
 
 X = # OF l's IN 
 
 SHIFT REGISTER 
 
 RF 
 
 Figure 2. Block Sum Register 
 
SHIFT REGISTER 
 
 JT 
 
 • • • » • 
 
 10 K 
 
 EXAR 
 B101 
 
 V REF =10 VOLTS 
 
 1 -V 
 
 EXAR 
 B101 
 
 OUT 
 
 =±= .0\5 fiF 
 
 + 5V 
 
 SHIFT 
 
 
 
 V 
 
 cc 
 
 
 
 INPUT 
 
 
 GND 
 
 
 
 
 
 
 
 
 
 
 
 
 i 
 
 10 
 
 SHIFT 
 OUTPUT 
 
 r OUT 
 
 Figure 3. Block Sum Register 
 
these charges. A one entering the shift register would turn on the 
 charging transistor and increment the charge in the capacitor by a unit. A 
 one leaving the shift register would turn on the discharge transistor and 
 remove a unit of charge from the capacitor. Outputs of .25 volts per step 
 with 10 steps for a maximum of 2.5 volts have been obtained. Linearity of 
 5% is possible, with the restriction that the capacitor is charging in the 
 linear portion of the capacitor characteristic. The disadvantage of this 
 design is that the output is dependent on the shift register clock 
 frequency. This is due to the quantity of charge corresponding to one is 
 proportional to the duration of each pulse. Also as the frequency is 
 lowered, either the collector voltage of the charging transistor or the 
 capacitance must be increased in order to maintain linearity. Replacement 
 of the capacitor with an up-down counter controlled by the first and last 
 bit yields parallel binary output. 
 
 2.3 Load Current Register 
 
 The most satisfactory BSR in terms of simplicity and linearity of out- 
 put steps takes advantage of the electrical characteristics of the shift 
 register. As shown in Figure 3, if a 10 ohm current sensing resistor is 
 placed in the ground path of the shift register, the variation in current 
 drawn by the shift register as a function of the number of ones or zeroes 
 can be detected. This variation is exactly a quantized analog output 
 suitable for BSR's. The utmost in simplicity is achieved with the BSR 
 composed of a shift register and a resistor. The step size is highly 
 dependent on the particular shift register used. While all of the 11 shift 
 registers examined showed current variations, only the Signetics 8273 10-bit 
 shift register exhibited sufficient variation in current to be of use. 
 
cc 
 
 OUTPUTS 
 
 A 
 
 BURST 
 
 ^ INPUT RESET 
 
 16 15 14 13 12 11 10 
 
 SIGNETICS 8273 
 
 OUTPUTS 
 
 ^ CLOCK CLOCK 
 1 2 
 
 8 
 
 10/ 
 
 -^V 
 
 OUT 
 
 SIGNETICS 8273 - 10 BIT SERIAL IN PARALLEL OUT SHIFT REGISTER 
 
 MINIMUM FREQUENCY - 25 MHz 
 
 NUMBER OF 
 ONES 
 
 10 
 
 9 
 
 8 
 
 7 
 
 6 
 
 5 
 
 4 
 
 3 
 
 2 
 
 1 
 
 
 
 SAMPLE OUTPUT VOLTAGES 
 (±.0002 VOLTS) 
 
 144 
 
 .150 
 
 153 
 
 .159 
 
 162 
 
 .168 
 
 171 
 
 .177 
 
 180 
 
 .186 
 
 189 
 
 .195 
 
 198 
 
 .204 
 
 207 
 
 .213 
 
 216 
 
 .222 
 
 225 
 
 .231 
 
 234 
 
 .240 
 
 Figure 4. Signetics 8273 Shift Register BSR 
 
8 
 
 Figure 4 shows the Signetics 8273 used as a BSR and its characteristics. 
 Two sample outputs are shown. The linearity of all Signetics 8273 examined 
 were within 3% per step. The step size varies from .0085 volts to .010 
 volts for different chips. The difference in step size and minimum voltage 
 level are acceptable since low cost op amps provide the necessary gain and 
 level shifting while also providing the required buffering. 
 
3. A BURST ARITHMETIC UNIT 
 
 The use of Block Sum Registers allow on-line arithmetic operations to 
 be performed on burst encoded information in a simple manner with results 
 immediately available in analog or burst format. Since burst representation 
 on a single block basis approximate the information encoded to 10% precision 
 (with higher precision obtained through averaging), the arithmetic circuits 
 can also be of 10% precision. There is difficulty achieving higher 
 precision in multiplication and division, since the average of products 
 and quotients is not the same as products and quotients of the averages. 
 Addition and subtraction does not suffer from this problem. This problem 
 has been considered by Bracha (2) and the results show that with some 
 restrictions on the rate of change of the input sequences of burst operands, 
 the error can be kept to a minimum. The operands in this arithmetic unit 
 are assumed to be positive numbers. 
 
 The output of the BSR is either a current or a voltage, so analog 
 arithmetic methods can be applied to burst encoded operands. Analog 
 arithmetic has the advantages of virtually no delay and fairly simple 
 circuits. Up to Vk precision can be obtained. Due to constraints in the 
 multiplier, the analog voltages corresponding to the values of the burst 
 are defined to be negative 1 volt to negative 6 volts, in negative .5 volt 
 decrements, mapped onto burst values of to 1.0 in increments of .1. 
 
 3.1 Burst Addition 
 
 Addition is performed by summing the voltages of the BSRs containing 
 the burst operands. Figure 5 shows the circuit. The result is scaled to 
 
+ 5 V 
 
 — 15V 
 
 10 
 
 INPUT +5V 
 
 100 K 
 
 100 K 
 
 + 5V 
 
 INPUT +5V 
 
 -I5V 
 
 10 9 
 
 8273 
 
 6 7 8 
 
 + 5V CLOCK 
 
 5, UK 
 
 100 
 
 f 
 
 5. iik 
 
 + 5V CLOCK 
 
 806 
 
 IK 
 
 ■ — VW- 
 
 t ^^ 
 
 806 
 
 t 
 
 'IK 
 
 100K 
 
 5.11 K 
 
 100K 
 
 1 + A-l 
 
 Figure 5. Adder and Subtracter 
 
 
11 
 
 (A+B)/2 to facilitate encoding into burst format. The main sources of 
 error come from the difference in step sizes, nonlinearity, and difference 
 in DC bias of the BSR outputs. Nonlinearity is less than 3% and adjusting 
 the summing resistors of the amplifier matches the step size and DC bias. 
 
 3.2 Burst Subtraction 
 
 Subtraction in the form of 1 + A - B can be easily accomplished by 
 complementing the B-burst to obtain 1 - B and then performing addition. 
 Figure 5 shows the circuit. The B-burst is complemented by a transistor 
 connected in the common emitter configuration. Scaling the results to 
 (l+A-B)/2 is done to allow for encoding into bursts. By leaving the result 
 as 1 + A - B, the problem of negative number representation is avoided. 
 However, the constant factor can be easily removed by adding a positive 6 
 volts to the summing inputs of the amplifier. The analog circuits used can 
 yield bipolar voltages, so negative numbers could be allowed. It is 
 interesting to note that any number of operands can be added or subtracted 
 simulanteously. 
 
 3.3 Burst Multiplication 
 
 Multiplication is based on the transconductance method (3). This 
 method is the simplest method for multiplication and is based on the 
 transistor's linear relationship between the collector current and the 
 transconductance. The multiplication property can be understood by 
 differentiation, a simplified Ebers and Moll equation for the transistor. 
 
12 
 
 where I is the collector current 
 a is approximately .99 
 
 I ^ is the emitter saturation current 
 es 
 
 V. is the base-emitter voltage in volts 
 
 kt/q = 25.69 mV 25°C 
 
 
 dI c 
 
 For small variations 
 AI c 
 
 = 3- i 
 AV be kt L c 
 
 or 
 
 AI c ■ fe Vbe 
 
 Therefore by letting the base voltage be one operand and the collector 
 reference voltage be the other operand, the collector current will be 
 proportional to the product of the two operands. Figure 6 shows the trans- 
 conductance idea implemented with a simple differential amplifier circuit. 
 The emitter voltage is varied rather than the collector voltage. The output 
 is the difference in the two collector currents. 
 
 a V R 3 
 t _ t = y E_ in °u 
 
 x cl x c2 kt 5.07kft lu V A 
 
 Vn is limited to be .6 volts less than V« in order to maintain forward bias 
 on the base-to-emitter junction. This restricts Vn to be negative, with a 
 maximum of negative .6 volts if the V» is positive. The major source of 
 
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14 
 
 error comes from the exponential relationship between the base voltage and 
 the collector current. However, by dividing V. by the 10K - 10 ohm divider 
 network, the actual base voltage is reduced to 6mV for the maximum V. of 
 6 volts. This is much less than the junction constant kt/q = 25.69 mV at 
 25°c. Experimental results show the precision is better than 5%. 
 
 3.4 Reciprocal 
 
 The reciprocal function is performed by multiplying the operand by an 
 internally generated burst and comparing the product to the analog level 
 corresponding to a burst of .1. This scaling is used to prevent overflow 
 and allow for encoding into burst format. Figure 7 shows the eleven burst 
 values and their reciprocal. The reciprocal of a burst of zero is defined 
 to be a burst of 1.0 since 1.0 is the maximum value possible. Figure 7 also 
 shows the reciprocal representable in a single burst. The method used 
 automatically generates the sequence of bursts with the exact average analog 
 level corresponding to the reciprocal. In practice the precision is limited 
 by the comparator and the multiplier. The comparator used has a precision 
 of 1.2% and the multiplier contributes 5%. Experimental results show 
 actual precision of 5%. 
 
 3.5 Burst Division 
 
 Given the reciprocal and a multiplier, the division function can be 
 realized. Figure 8 shows the addition of a multiplier to the reciprocal 
 generator. The numerator is not multiplied by the analog level of the 
 single burst, which corresponds to the 10% approximation of the reciprocal, 
 but is multiplied by the exact sequence of bursts which is the reciprocal 
 of the denominator. Maintaining the multiplier and the at 5% precision 
 allows quotients to be of 10% precision. 
 
 
15 
 
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17 
 
 4. PHYSICAL LAYOUT AND OPERATION OF THE AU 
 
 The arithmetic unit contains six banana plugs for +5 volts, +15 volts, 
 ground and clock, two sets of ten switches and a banana plug for the output. 
 The arithmetic circuitry has been described and will not be considered here. 
 
 Since the load current variation of the Signetics 8273 shift register 
 depends not only on the number of ones in the shift register, but also on 
 whether the clock is high or low, the duty cycle should be 5% or less to 
 minimize the variations in the outputs of the arithmetic circuitry. 
 
 The two sets of input switches provide constant bursts to the arithmetic 
 unit. Each switch corresponds to a time slot in the bursts. The switches 
 are inputs to a Signetics 8274 ten bit parallel input shift register. On 
 e^ery tenth clock pulse, the logic levels corresponding to the switch 
 positions are loaded into the Signetics 8274 shift register and shifted out 
 serially during the next ten clock pulses. 
 
 The internal outputs of the arithmetic circuits are in analog form. 
 These outputs are encoded into burst format and are available at the output 
 banana plug. The encoding is performed by comparing the analog output with 
 the voltage level corresponding to each burst value. The output of the ten 
 comparators are loaded into a Signetics 8274 shift register on every tenth 
 clock pulse and shifted out during the next ten clock pulses. 
 
 The photograph at the end of the Appendix shows the arithmetic unit. 
 
18 
 
 5. CONCLUSIONS 
 
 A Block Sum Register composed of one shift register and one resistor 
 has been developed. The BSR developed offers good linearity and ease of use. 
 Depending on the application some form of buffering may be necessary. The 
 buffering amplifier would also provide any needed level shifting or 
 amplification. The BSR is rated at 25 MHz minimum. 
 
 A low precision arithmetic unit has also been constructed using the 
 Signetics 8273 shift register as the BSR. The clock frequency of the shift 
 register is 600 KHz, due to the limitation of the 741 op-amp used. The 
 arithmetic unit uses 4 shift registers, 4 transistors, and 7 op-amps. 
 Negative numbers could be allowed since the analog circuitry can yield 
 bipolar voltages. Higher speeds can be obtained by using a faster op-amp 
 or by using a fixed gain discrete amplifier. 
 
 Burst representation lends itself to applications where precision is 
 not critical or when it can be obtained through averaging. The simplifi- 
 cations result in low cost precessing elements operating on line. The 
 BSR is a semianalog device performing processing in analog and storage and 
 transmission in digital format. 
 
 
19 
 
 LIST OF REFERENCES 
 
 1. Poppelbaum, W. J., "Statistical Processors," "Advances in Computers," 
 Vol. 14, pp. 182-230, 1976. 
 
 2. Bracha, E., "Burstcalc, A Burst Calculator," Department of Computer 
 Science, University of Illinois, Urbana, Illinois, UIUCDCS-R-75-769, 
 October 1975. 
 
 3. Sheingold, D., ed., " Nonlinear Circuits Handbook" , Analog Devices, 
 Norwood, Massachusetts, 1974. 
 
PIN CONFIGURATION 
 
 20 
 
 GND 8 
 
 B,F,W Package 
 
 %l 
 
 1 
 
 Q 7 
 
 2 
 
 *8 
 
 3 
 
 % 
 
 4 
 
 <W 
 
 5 
 
 CLOCKj 
 
 6 
 
 CLOCf^ |_7 
 
 16J V 
 
 cc 
 
 15J Q 5 
 
 1U Q 4 
 
 ]3J Q 3 
 
 J2J Q 2 
 
 ID Q } 
 
 ToH "D" INPUT 
 
 91 RESET 
 
 DESCRIPTION 
 
 The 8273, 10-Bit Shift Register is an array of binary elements interconnected 
 to perform the serial -in, parallel -out shift function. This device utilizes 
 a common buffered reset and operates from either a positive or negative edge 
 clock pulse. Clock 1 is triggered by a negative going clock pulse and Clock 
 2 is triggered by a positive going clock pulse. The unused clock input 
 performs the inhibit function. The circuit configuration is arranged as a 
 single serial input register with ten true parallel outputs. 
 
21 
 
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24 
 
 Photograph of the AU. 
 
ECURITY CLASSIFICATION OF THIS PAGE (Whon Dmtm Bnlormd) 
 
 REPORT DOCUMENTATION PAGE 
 
 I. REPORT NUMBER 
 
 I UIUCDCS-R-77-890 | 
 I TITLE (mnd Subtitle) 
 BLOCK SUM REGISTER AND BURST ARITHMETIC 
 
 2. GOVT ACCESSION NO 
 
 7. AUTHORr*; 
 
 James Hsioh-Cheng Ma 
 
 9. PERFORMING ORGANIZATION NAME AND ADDRESS 
 
 Department of Computer Science 
 
 University of Illinois at Urbana-Champaign 
 
 Urbana, IL 61801 
 
 READ INSTRUCTIONS 
 BEFORE COMPLETING FORM 
 
 3. RECIPIENT'S CATALOG NUMBER 
 
 S. TYPE OF REPORT ft PERIOD COVERED 
 
 M.S. Thesis /August, 1977 
 
 S. PERFORMING ORO. REPORT NUMBER 
 
 UIUCDCS-R-7 7-871 
 
 • . CONTRACT OR GRANT NUMBERfaJ 
 
 N00014-75-C-0982 
 
 10. PROGRAM ELEMENT. PROJECT, TASK 
 AREA ft WORK UNIT NUMBERS 
 
 II. CONTROLLING OFFICE NAME AND ADDRESS 
 
 Office of Naval Research 
 
 Code 437 
 
 Arlington, Virginia 22217 
 
 12. REPORT DATE 
 
 August, 1977 
 
 IS. NUMBER OF PAGES 
 
 U MONITORING AGENCY NAME ft ADDRESSf*/ dlttormnt /ram Controlling Of lie*) 
 
 IS. SECURITY CLASS, (of thlt Opoti) 
 
 Release Unlimited 
 
 ISa. DECLASSIFICATION/ DOWNGRADING 
 SCHEDULE 
 
 16- DISTRIBUTION STATEMENT (ot thlt Roport) 
 
 Distribution unlimited 
 
 17. DISTRIBUTION STATEMENT (ol tho •btlrmcl entered In Block 30, It different from Report) 
 
 IB. SUPPLEMENTARY NOTES 
 
 19. KEY WORDS (Contlnum on revere* aide II neeeeeory arid Identity by block number) 
 
 Burst Processing 
 Block Sum Register 
 
 20. ABSTRACT (Continue on rmvoreo tide II neceeemry "><* Identity by block number) 
 
 The Block Sum Register (BSR) is a basic building block used in Burst Processin 
 The main difficulty with it has been the large number of discrete components 
 required for the current sources. 
 
 The paper introduces various BSR designs with considerably smaller numbers 
 
 of discrete components using the electrical characteristics of the BSR's shift 
 
 register. The best design is then used in an arithmetic unit which performs 
 
 DD I JAN 73 1^73 EDITION OF 1 NOV 6S IS OBSOLETE 
 
 S/N 0102-014-6601 | 
 
 SECURITY CLASSIFICATION OF THIS PAOE (When Dmlm Knterod) 
 
LLUWTY CLASSIFICATION OF THIS PAGEr*h.n D.t. B n f~d) 
 
 20. the basic arithmetic operations, i.e., addition subtraction, multiplicatic 
 and division. 
 
 SECURITY CLASSIFICATION OF THIS PAGEf***. Dmf Snt.r~« 
 
3GRAPHIC DATA 
 
 r 
 
 1. Report No. 
 
 UIUCDCS-R-77-89Q 
 
 3. Recipient's Accession No. 
 
 -3tio 
 
 e and Subtitle 
 
 SLOCK SUM REGISTER AND BURST ARITHMETIC 
 
 5. Report Date 
 
 August, 1977 
 
 6. 
 
 fior(s) 
 
 James Hsioh-Cheng Ma 
 
 8* Performing Organization Rept. 
 
 No. UIUCDCS-R-77- 890 
 
 forming Organization Name and Address 
 
 Department of Computer Science 
 
 University of Illinois at Urbana-Champaign 
 
 Urbana, IL 61801 
 
 10. Project/Task/Work Unit No. 
 
 11. Contract /Grant No. 
 
 N00014-75-C-0982 
 
 onsoring Organization Name and Address 
 
 Office of Naval Research 
 
 Code 437 
 
 Arlington, Virginia 22217 
 
 13. Type of Report & Period 
 Covered 
 
 Master's Thesis 
 
 14. 
 
 pplementary Notes 
 
 The Block Sum Register (BSR) is a basic building block used in Burst 
 Processing. The main difficulty with it has been the large number of discrete 
 components required for the current sources. 
 
 The paper introduces various BSR designs with considerably smaller numbers 
 of discrete components using the electrical characteristics of the BSR's shift 
 register. The best design is then used in an arithmetic unit which performs 
 the basic arithmetic operations, i.e., addition, subtraction, multiplication 
 and division. 
 
 ey Words and Document Analysis. 17o. Descriptors 
 
 Burst Processing 
 Block Sum Register 
 
 I Identifiers /Open-Ended Terms 
 
 COSATI Field/Group 
 
 vailability Statement 
 
 Release Unlimited 
 
 19. Security Class (This 
 Report) 
 
 UNCLASSIFIED 
 
 20. Security Class (This 
 
 Page 
 UNCLASSIFIED 
 
 21. No. of Pages 
 
 22. Price 
 
 ■l NTIS-35 ( 10-70) 
 
 USCOMM-DC 40329-P71 
 
»"*• 
 

OCT 2'NM 
 
 V>u> 
 
UNIVERSITY OF ILLINOIS-URBANA 
 
 510 84 IL6R no COO? no 886 893(1977 
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