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L162 Digitized by the Internet Archive in 2013 http://archive.org/details/graphicsonetermi814artw UIUCOCS-R-76-814 S/o- ?f yvo. itf / C00-2383-0033 U GRAPHICS ONE TERMINAL DESIGN AND USER'S MANUAL by BRUCE A. ARTWICK and ALFRED D. WHALEY July 1976 UIUCDCS-R-76-814 C00-2383-0033 GRAPHICS ONE TERMINAL DESIGN AND USER'S MANUAL by BRUCE A. ARTWICK and ALFRED D. WHALEY July 1976 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS 61801 This work was supported in part by the United States Energy Research and Development Administration under contract US ERDA E(ll-l) 2383. Ill FOREWORD The research and development described in this report occured durinn the period from January 1975 to April 1976 with many delays due to parts availability problems. The graphics system described is believed to be one of the first in a new generation of computer graphic terminals incorporation larqe bit maps stored in high density random access memories, and using internal high speed micro-computers for character and vector generation. Credit for participation in the early development stages and for the design of portions of the processor data paths and control structure noes to Lawrence Lopez. This research was supported in part by the United States Energy Research and Development Administration under contract US ERDA E(ll-l) 2383, IV TARI.E OF CONTENT?; Page INTRODUCTION 1 SCREEN DISPLAY OPERATION 3 Matrix Generator 3 Memory System and Cards 5 Memory Address and Timing Control Card ......... 7 Address Structure and Registers 8 Writing and Reading Screen Memory 10 PROCESSOR STRUCTURE 11 Data Units 12 Arithmetic and logic unit 12 Accumulator 12 Memory mask multiplexer. 12 Data Units 12 Program counter , 12 Address register 13 PC/address register multiplexer 13 Control System 14 Operation register 14 Seguencer 15 Hardware implementation of seguencer 15 Seguencer initialization 15 Seguencer pause now sianal 18 PC/address multiplexer control 19 Branch decoder 19 Clock 19 IK RAM/ROM Memory System 21 Peripheral Bus Structure 21 Hesiqn Schematics 21 System Performance 23 SYSTEM PROGRAMMING 24 Backqround 24 Addressing Modes 25 Instruction Set 27 I/O Device Reqister Locations 29 INTERFACING GUIDE 31 Usino the Peripheral Bus 31 Slow Devices and Memory 32 Peri bus Lines 32 Data Routinn System 32 Back Panel Wiring 33 APPENDIX A 34 APPENDIX B . . . . 49 APPENDIX C 59 1 INTRODUCTION The system described in this report was developed out of the need for a low cost computer terminal with extensive graphic capabili- ties. Preliminary design criteria included simple hardware construction using a micro-computer for flexability, expandability, character genera- tion, vector qeneration and other graphics tasks. Bilevel screen display data is stored in a large random access memory which is read out sequentially to a video display, one bit at a time. Through cycle steal inn, memory and thus picture modification is accomplished. The generated dot matrix is of arbitrary dimensions which are not necessarily powers of two therefore advanced counting schemes are used to keep track of line and bit counts. Due to the system's low cost constraint, a standard television receiver is used as a video monitor by cutting into the video circuitry after the RF tuner. Standard 525 line resolution is used. Small matrix displays (up to 200 dots square) use double line resolution while larger displays use the interlace facilities to increase resolution. Alternate frames must therefore be displayed on the two interlaced fields adding to the complexity of the counting system. In the development of the terminal the need for a high speed micro-computer for fast character and vector generation became apparent. Although MOS and bipolar processors were currently available, a TTL design was chosen. This design offers the advantages of being inexpen- sive, more specialized for graphics work and much faster than MOS pro- cessors. After development was completed a fairly powerful computer resulted with about the same number of integrated circuits required to 2 interface to popular microprocessors at about one third the cost. This report is presented 1n two sections. The screen display qenerator will first be presented followed by the microcomputer section, SCREEN DISPLAY OPERATION The screen display unit consists of three parts. 1. The matrix generator 2. The memory control and addressinq unit 3. The random access memory system MATRIX GENERATOR A vertical line counter and a horizontal bit counter along with corresponding count recoqnizers keep track of the matrix size and posi- tion. V.'hen a preset horizontal bit count is recognized the bit clock and the video display are gated off. Through the adjustment of the bits per line recognizer and the bit clock rate, display width and density can be respectively adjusted. The left margin of the matrix is deter- mined by delaying the clock and video restart from the horizontal sync pulse. The vertical counter has two recognizers. The start display recognizer determines which line from the top of the display will be used to start the matrix and also triggers a memory initialization sys- tem which prepares display data one line before the display begins. The stop display recognizer turns the video enabling system off when the desired number of lines has been displayed. Although the video is blanked at the bottom of the screen, memory readinq continues in order to keep the dynamic memories refreshed. A new memory restart address is issued to the memory counter upon frame initialization one line before the display starts. The horizontal bit count recoqnizer watches the horizontal coun- ter and determines when ten, twenty or forty bits have been displayed. 4 The memory control circuitry can use the resultinn siqnal to prepare new information by loadinq new data from the random access memory into a larqe shift reqister (see memory section). This is the read request load shift reqister siqnal. The matrix qenerator requires that valid data always be availa- ble to be shifted onto the video monitor. It is up to the memory con- trol system to see that this requirement is met and that the memory out- put looks like the output of a larqe shift reqister. The matrix qeneration just described is performed by the matrix qenerator card. Two important subsystems of the matrix qeneration sys- tem are the frame initialization system and the sync siqnal and video output qenerator. A National Semiconductor MM5320 color television video sync qen- erator IC is used to qenerate all required sync siqnals and proper input clock waveforms are controlled by a dual one-shot clock. Good waveforms are vital for proper field index qeneration which is used for the inter- lacinq. A one transistor video mixer has been desiqned to meet EIA RS 330 standards for video monitor output. The dot matrix is bilevel with no intermediate qray shades employed. Within the matrix qeneration sequence there exists a frame ini- tialization step. Before a frame can properly beqin, valid data for that frame must be available in the shift reqister. A frame starts on line 0. Initialization procedures are perfor- med on line -1 and consist of loadinq the restart address, readinq the memory at that location, loadinq the memory contents into the latches, and incrementinq the memory address reqister. The memory card desion 5 shows these units and at what times each of these events take place. Since alternating frames require different frame starting ad- dresses when the interlace facility is being used, a toggle flip flop and two gates have been provided to keep track of alternate fields. Ini- tial syncronization of this flip flop is performed by the field index signal. Figure 1 shows the matrix generator card. MEMORY SYSTEM AND CARDS Due to the large amount of memory needed to store a dot matrix (160k bits for a 400 square matrix), a 4k dynamic RAM (Intel 2107) was used. The only refresh requirement is that sixty-four rows be read once every millisecond (this memory is ornanized as 64 rows by 64 columns). This refresh specification is met through the continous reading of the memory for display purposes. Calculations showed that fifty nanoseconds per bit access time would be needed to display 400 bits on one forty microsecond line al- lowing half of the time for memory cycle stealing for external memory access. A memory parallelling scheme was employed to reduce this re- quirement to 1.5 to 2.0 microseconds depending on the number of RAMs used. For various sized matricies ten, twenty or forty are parallelled leaving 50, 100 and 200 percent safety timing margins respectively. Latches are used as a hinh speed buffer memory for RAM data and a card to card chainable shift reqister is loaded from the latches at the proper time. Parallel dumping of memory into the latches is performed by simultaniously enablinq all the RAMs and strobing in data at the proper time. The RAMs all have a common address. Individual bit access is T3 i- a l. o re t- X •r- t- 4-> ro 3 a u c o >ir- Line Counter 7 performed by supplying the proper common address and enabling the desired chip which is selected by the chip address decoder. Individual bit reading is accomplished by examining the access data output as only an enabled and thus the selected chip can provide a logic one level. Individual bit writing can be performed by providing all the RAMs with a write signal. Hnly the enabled chip will respond, writing the data bit into that RAM. MEMORY ADDRESS AND TIMING CONTROL CARD The memory control system must: 1. keep track of memory display addresses 2. generate memory timing pulses for read and write cycles 3. interleave display and memory access cycles Address information supplied to the RAMs has two sources, the memory address counter for sequential display dumping, and the screen data address, for individual bit access by the processor for image modi- faction. The screen data address is buffered for asynchronous loading, allowing the processor to load the buffer at any time yet permitting the display unit to synchronously load the address when needed. The address counter is controlled by the matrix generator. The memory timing sequence determines at which times either address is needed and operates the memory address multiplexer accordingly. The chip and card address selector operates in the same way, however additional decoding of the address is provided to drive the memory card decoders. This circuitry is on the matrix generator board due to spacing problems. Upon receiving a read request siqnal from the matrix generator the memory timinq system generates pulses to produce a read / read 8 modify write sequence. The display address is read and data is loaded into the memory cards' latches. After the read is completed, the ad- dress from the screen data address register is multiplexed to the memory and a read modify write cycle is performed. A write flip flop can be externally set by the controlling processor and the next read modify write cycle will write the contents of the input data into the addressed location. A read will also be performed at this address whether re- quested or not and the data is available for processor use. Proper delays and pulse durations as specified by Intel have been met. Figure 2 shows the memory control and timinn card. ADDRESS STRUCTURE AND REGISTERS The display unit is designed to be driven by a sixteen bit data bus and therefore appears to be three registers. The two address re- gisters can be loaded by strobinn the load bottom 4 or load top 14 lines. The set write flag line is also available to the processor to perform accesses. Address register TOP 14 2 bit card I i | 12 bit common address | address | 15 o Address register BOTTOM 4 i |4 bit chip addressi 's o Screen Data one bit I data | | is The memory system design results in the following means of Hard-wired 2nd Frame Start Address Memory Address Counter Peripheral bus input port Memory Address Multiplexer i Screen Data Address Buffer Screen Data Address Register 12 Bit Screen Memory Address 1 Memory Card Control Signals Read Cycle Length " All chips enable Read Modify Write Cycle n»l*y Read Modify Write Cycle Time Screen Read Flip Flop I nad Circuit Figure 2. Memory timing and control card. 10 addressing individual bits. 1 . A 2 bit card address (for up to 4 memory cards) 2. A 12 bit common address (for the 4K RAMs) 3. A 4 bit chip address (10 memory chips per card) WRITING AND READING SCREEN MEMORY Although the screen display unit can take data bits to be writ- ten at an average rate of one bit per three microseconds, there are periods of up to twenty or thirty microseconds where the display clock is stopped (right and left screen marm'ns) where no data can be written, The write flag can be used as a screen busy flag for the controlling processor so writinn during these periods can be avoided. 11 PROCESSOR STRUCTURE The two constraints the processor 1s based upon are simple, hinhly efficient design and high speed operation. Data paths and con- trol schemes were designed accordingly. A slnnle accumulator sixteen bit parallel processor design was used. Sixteen bits provide one in- direct bit, a five bit opcode and a ten bit address field. This allows for a Ik range of direct memory addressing and sixteen bit arithmetic which was thought to be enough for a graphics terminal. Through in- direct addressing a full 64K of memory or device registers can be ac- cessed. Arithmetic operations are based on the versatile functions of the 74181 arithmetic and logic unit. Through the use of an extended opcode field on nonmemory reference (generic) instructions where the address field is not used, a large instruction set is possible. The processor unit is built on two nine by five inch circuit boards which are screwed together to form an 88 pin two level plug-in module. The processor is contained on one card while the clock and IK of read only and random access memory are on the other. Twenty connec- tions are made between the cards with plug-in flexible cables. The processor module can be divided into 4 basic units. 1. Data units 2. Address units 3. Control system 4. Memory system These will now be explained. 12 DATA UNITS Three units form the basis for data flow: ARITHMETIC AND LOGIC UNIT. Four 74181 ALU integrated circuits are used to perform arithmetic, logic and multiplexing operations between memory data and accumulator data with the result going to the accumulator ACCUMULATOR. Two 74198 eight bit bidirectional shift registers comprise the accumulator. All shifts and rotates are done in the accumulator. The output from the ALU can be read into the accumulator and the output can be strobed into memory or used by the ALU as an operand. MEMORY MASK MULTIPLEXER. On immediate mode instructions, the lower ten bits from the address field are used as data. The six bit memory mask multiplexer provides either a 1 or to all six top ALU memory inputs on these operations. Bit nine determines if the top six bits will be or 1, thereby acting as a sign propigation bit. The established data paths form four classes of data manipula- ting instructions. 1. No load-no store: operates only on accumulator (e.g. com- plement) 2. load-no store: loads data from memory and may operate on it (e.g. add) 3. no load-store: stores data to memory which may have been operated on (e.g. complement and store) 4. load-store: memory and accumulator contents are operated on and stored (e.a. add and store) ADDRESS UNITS PROGRAM COUNTER. Four 74161 high speed look ahead counters are used to 13 keep track of the program location. Every instruction performed sup- plies a clock pulse to these synchronous counters. Normally, the count is incremented but if a branch operation is 1n effect this clock pulse causes the PC to be loaded with the effective address if the proper con- ditions (+,-,zero or hardware flag) are met. ADDRESS REGISTER . Two 74174 and one 74175 six and four bit D latches form this register. An instruction fetch causes the instruction to be loaded and the top six bits cleared. case 1. If this is a memory reference instruction the address can be multiplexed to the memory and the memory contents used as data. case 2. If this is a branch instruction the contents can be loaded into the PC for the branch address. On indirect instructions, normal referencing is used (case 1 above) but all sixteen bits of the memory contents are loaded into the address register. On the operational phase of the indirect instruction, case 1 or 2 again apply but this time a full sixteen bits are available to address locations outside of the lower IK of memory. PC/ADDRESS REGISTER MULTIPLEXER . Four 74157 two to one four channel multiplexers determine which address the memory will use; the PC or the address register. The control unit section tells when each is appropri- ate. 14 CONTROL SYSTEM The operation reqister, sequencer, branch detector, and clock comprise the control unit. OPERATION REGISTER. This is an 8 bit D latch (one 74174 and one 7474) which is loaded durinq the instruction fetch. Seven bits are used to store the opcode of the instruction and one bit stores the value of an external input to the processor (the external flaq). The external flag can be tested by an instruction and is useful for branching on certain external conditions which is further covered in the branch detector sec- tion. Further decoding of the opcode is needed for instruction execu- tion. Two 8223 programable read only memories derive the necessary 13 bit ALU and sequencer gatinn control codes. ROM 1 - ALU Function Selector Bit Sional Function 1 Set 2 indicator Activates opcode extensions 2 S3 3 S2 ALU function control 4 SI 5 SO 6 Cn 7 Mode 8 Immediate mode indicator ROM 2- Sequence Control ROM 1 Branch 2 No Read 3 Read 4 Write 5 Branch On External Flag An indirect instruction temporarily disables ROM 2 to hold off execution of that instruction until the indirect address has been ac- cessed. After the address has been accessed, the indirect bit latch (part of the operation register) is cleared preventing further indirec- ting of the instruction. Fiqure 4 shows the operation register and ROM 15 decoding. SEQUENCER. Synchronous control points are used to provide control sequences for the processor. Clocked flip flops, each representinq a state, are chained toqether to form control chains. The opcode of the instruction to be performed determines the control sequence to be used. The state chain structure is shown in fiqure 3. HARDWARE IMPL I MENTATION OF SEQUENCER. A strinq of D flip flops is used to impliment the flow chart. Throuqh proper initialization, one bit can be routed throuqh the timinq chains with derived pulses beinq used for timinq. Efficient desiqn was used in makinq full use of flip flop features. Instead of qates beinq used to channel bits from input to out- put, the overridinq clear inputs are held low or high to accomplish the same thinq. This has the added benefit of clearinq out any erronious bits which may have been introduced in the timinq chain. Fiqure 5 shows how the D latch clear feature is effectively used. The opcode, via the control ROM and extension bit decoder, determines which flip flops will be held clear and where the bit will flow. The timinq diaqram with the desiqn schematics shows which pulses are used to load the data units and memory at what times. NR means no read, NW means no write, R means read and NRNW represents no read, no write. The NRNMx2 is a useful sequence which loads the accumulator twice. This allows for double shifts and rotates which are code and time savinci. SEQUENCER INITIALIZATION. Initialization is performed by settinq the initialization SR flip flop. The SO state flip flop is preset and the 16 1 ' Instruction fetch t _j Pranch ! MRNW x2 i r MR Read Indirect v Conditional decision Load Accumulator Read pause Read pause 1 no 1 1 '" /es r i IF inc. PC load PC V } ! Load Accumulator Memory Address req. 1 i f T Reset indirect bit Write decision *y< >s no write l } f inc. PC Fiqure 3. Flow chart of state chain functions. 17 External flan Indirect bit To branch decoder ROM 2 Sequence select 5 Bit OP code Exten- tlon bit ROM 1 ALU Function Address register output Extension OP field decoder sequencer qatinq to sequencer gatinq ALU select lines sequencer Accumulator gating function control Figure 4. Operation decoding and sequence control. data D >- > T enable clock a) sequencer qatinq circuit, data clock* D i| T f enable b) more efficient equivalent. Fiqure 5. Effecient use of flip flops. 18 SI flip flop is cleared. The running clock propagates 'O's from SI throughout the timing chains. The PC is cleared and the valid data at memory location settles. k'hen the initialization flip flop is reset, execution at becins on the first leading edge of the clock. The ini- tialization flip flop is provided for debouncing and a standard SPDT switch can be used to triaoer it. If a fast device is used to initial- ize the system, 600 ns must be allowed for memory settling time in an initialization pulse. SEQUENCE PAUSE NOW SIGNAL. This processor is desioned to run extremely fast so when slow memory (access time of more than 35 ns) is used, the processor must halt operations until the memory data becomes valid. Since fast device registers and PROMS as well as slow MOS RAMs are used, responsibility to stop operation of the processor has been delegated to the memory being addressed. K'hen the processor knows a memory read pause will be reguired if slow memory is used, it sends out a pulse cal- led the Pause Mow signal. Tf the slow memory being addressed sees this, it can pull down (hold at logic 0) the clock enable line. This stops the processor clock for as long as is needed to access the memory. A one-shot in the memory unit is ideal for this application. When data becomes valid, releasinn the clock enable line resumes processing. It should be noted that no pause now signal is given on the write signal. It's up to the memory being used to pause if it needs extra write time. Forty ns after the clock enable line is released, the memory address changes (only on the write cycle) in preparation for the next instruc- tion fetch. Care should be taken in memory design to insure that ad- dress hold reguirements are met. 19 PC/ADDRESS MULTIPLEXER CONTROL. Durinq the fetch cycle, the PC is multi- plexed to the memory address to fetch the instruction at that address. After the operation reqister and address reqister are loaded the address register takes over the memory address. On immediate mode instructions, however, the PC controls the memory address throughout the operation so the data can be used (immediate mode instructions contain an opcode and data field). BRANCH DECODER . Every instruction performed causes a clock pulse to go to the PC clock input. The branch instruction is no exception, as the PC can not only be incremented but loaded as well. If the proper condi- tions are met, the data is loaded from the address register and would be the branch address specified by the instruction. The lowest four bits of the opcode specify the branch conditions and the accumulator high bit (for accumulator zero) and the external flag provide the comparison. An and-or gate decodes the result of the comparison and activates the PC load function which will synchronously be performed instead of an increment. Figure 6 shows branch decoder operation. CLOCK . A frequency dividing flip flop is used to buffer the clock and to let the clock be stopped at either a high or low level. At high clock frequencies the clock stopping system may not have time to stop the clock before a new clock pulse comes out of the master clock. Since the sequencer states are activated only on leading edges this small pulse will have no effect because it will cause a trailing edge in the final output. This acts as a safety factor. 20 OPCODE | I | fcranch +J ten bit branch address w Accumulator (neoative bit) ALU output, (ace = 0) IK RAM ^- i i > Fxternal devices 1 < * i > i control data 16 bit data in data in signals out address O.C. tristate Figure 7. Peripheral bus structure. 16 TOCPU lines ~~ I | 16 Accumulator out I I 16 Address lines I (tristate) lines (processor driven) stop the clock clock _n_TL 1 1 4 5 volts initialize ~LT nround 1TL write external flaq _TL til- pause now Fiqure 3. Peripheral bus lines. 23 not have many nates or flip flops relative to the many functions perfor- med. Uhat it does have, however, may be hard to understand without a close study in some cases because some nates perform many funct1ons(in particular the set 2 decoder, the indirect ROM 2 enable system and the riRNW 2 level qatinn system). The rest is straight forward. The timing flow diagram and the symbolism on the design drawings show which edges and levels do what. SYSTEM PERFORMANCE The micro computer has incorporated many schottky and high speed parts to obtain high speed operation. Standard clock speed is 20 MHZ which is immediately divided by the clock flip flop to provide a micro cycle time of 80 MS. The processor has been tested to a higher speed. SPECIFICATIONS 39 total (65 with variations) 740-1660 MS including memory cycles Immediate, deferred, data, direct 5 volts, 2.0 amps 25 MHZ 80 MS 36 TTL MSI and SSI ICs 74181 ALUs Instruction Set Instruction Time Addressing Modes Power Requirements Clock Frequency Microcycle Time Loqic Arithmetic Unit 24 SYSTEM PROGRAMMING A guide to programmminq the processor with relation to the terminal system will now be presented. BACKGROUND The processor is a dynamic machine; not in the sense of needing refreshing hut in that it has no stop instruction and once initialized, is always runninq. Initialization clears the PC and starts execution at address zero. In the graphics version of the processor, thirty-two words of read only memory act as a bootstrap program to load the main program from another source (the controlling computer). Once loaded, execution is diverted to the main pronram stored in the one K of random access memory which was loaded by the bootstrap. There is no way to switch a program into the processor with this arrangement. A larger computer or some sort of buffer memory must be used. Much thought has gone into the instruction set to make instructions as powerful and useful as possible. One instruction programmers will miss is the subroutine call. This would have taken more hardware to implement and was felt to be not worth the extra cost. Only simulated subroutines are possible. 25 ADDRESSING MODES The processor has a sixteen bit operational field. The bottom one K of memory can be addressed directly while deferred addressing is available for high memory addressing (up to sixty-four K). DIRECT AND INDIRECT MEMORY ACCESS MODE. I Op Op Op Op Op A A A A A A A A A A Indirect 5 bit opcode 10 bit address This is used for every memory access instruction. The indirect bit signifies indirect addressing and the contents of memory will be used as the operand. EXTENDED INSTRUCTION MODE . The shifts and rotates all have the same five bit op codes. Four extension bits determine the type of shift or rotate Op 1 1 Ex Ex Ex Ex N N N N N N Opcode Opcode extension Not used The indirect bit can be set but since this is a generic instruction, direct or indirect addressing has no meaning. An indirect shift however takes 2 clock pulses longer than a direct shift due to the extra memory fetch. IMMEDIATE MODE INSTRUCTIONS . The indirect add, subtract, load and logical and, all use the ten bit address field for data. The top seven bits of the instruction assume the value of the propigation bit. The add instruction can be used to add small negative or positive constants to the accumulator. By making the propigation bit zero an add results 26 and a propiqated one causes an add of a negative or a subtract. The SU5M subtracts the accumulator from a small constant. This is quite useful when a negate is desired (0-ACO-ACC). Indirect immediate mode instructions use the value of the contents of the opcode plus the constant. This is probably a useless mode for this instruction. BRANCH INSTRUCTIONS . The direct addressing mode is used for branch instructions. Indirect branches to high addresses are possible also and execution will continue in high memory unless indirect mode is aqain used. More hardware would have been necessary for paqing. All 7 combinations of plus minus and zero are available as branch conditions, flote that a branch on plus, minus or zero is an unconditional branch. READ AMD WRITE INSTRUCTIONS . These use the same address for read and write operations. This is useful for modifying memory but it should be remembered that the accumulator also assumes the memory value and is modified, thus loosing its old contents. The memory increment or decrement (IMCS and DECS instruction) should be useful for pointers since it is loaded, incremented and stored in one operation. GENERIC INSTRUCTIONS . Instructions such as COM (compliment accumulator) which only modify the accumulator use the same format as the direct or indirect memory access instructions but the ten bit address has no meaning. DATA MODE . The whole sixteen bit field can be used to store data as long as it is never executed. The indirect bit has no significance thus only one level of indirect addressinq is possible. This was chosen over multilevel indirecting due to the need for sixteen bit arithmetic. 27 INSTRUCTION SET. The fol lowing instruction list gives opcodes in both octal and binary. The opcode and the address share an octal digit to include the tenth address bit. Operation Opcode Address Instruction Store 1774 054 1774 056774 The cross assemblers for this processor assemble opcodes automatically and this makes things much easier. 28 PROCESSOR INSTRUCTION SET INSTRUCTION HNU CYCLES TIME OPCODE OCTAL MEMORY ACCESS INSTRUCTIONS ACC->MEM ST 4 1160 ns 110110 address 154 MEM -> ACC L 4 1160 101000 120 MEMaACC-»ACC AND 4 1160 101001 122 V OR 4 1160 101010 124 9 XOR 4 1160 101011 126 + ADD 4 1160 101100 130 — SUB 4 1160 101 101 132 -1-»ACC-*MEM NOS 4 1160 noon 146 0-*ACC->MEM CLRS 4 1160 110100 150 £CT-*ACC*MEM CAMS 4 1160 110010 144 MTFT-*ACC*MEM COMS 5 1660 101110 134 A ANDS 5 1660 111001 162 V ORS 5 1660 111010 164 © XORS 5 1660 nion 166 +■ ADDS 5 1660 n iooi 170 — SUBS 5 1660 n n oi 172 MFM+HMEM-*ACC INCS 5 1660 IllllO 174 MEM-1*MEM*ACC DECS 5 1660 111000 160 to->acc COM 4 740 001111 arbitrary 036 IMMEDIATE MODE ACC+CONSTW\CC ADDM 4 740 OlllllP constant 076 ACCaOONST-»ACC ANDM 4 740 010000P 040 CONST-+ACC 1 .OADM 4 740 010101P 052 CONST-ACC+ACC SURM 4 740 010111P 056 SHIFTS AND ROTATES SHIFT RIGHT RS 4 740 0100011100 arb. 6 0434 SHIFT LEFT LS 4 740 0100011000 0430 ROTATE RIGHT ROR 4 740 0100011110 0436 ROTATE LEFT R L 4 740 0100011010 0432 SHIFT RIGHT x'< 2 RS2 5 320 0100011101 0435 SHIFT LEFT x2 LS2 5 820 01 00011 001 0431 POT. RIGHT x2 R0R2 5 320 0100011111 0437 ROT. LEFT x2 ROL2 5 320 0100011011 0433 BRANCH INSTRUCTIONS RR. ON FLAG BF 4 740 1 00000 address 100 BR. + ACC BP 4 740 1 00001 102 BR. - ACC BM 4 740 1 00010 no PR. + or - BPM 4 740 I 00011 112 BR. ZERO ACC BZ 4 740 1001 00 104 BR. + or ZERO BPZ 4 740 1 00101 106 BR. - or ZERO BMZ 4 740 I 00110 114 BRANCH B 4 740 iooin 116 NOTE: I=Indirect Bit P=Propanation Pit 29 I/O DEVICE REGISTER LOCATIONS LOCATION 177440 / MART RFCEIVE REGISTER D7 06 D5 D4 D3 D2 PI DO 1 EE UART rec. done Trans reg empty UART receive req. data note: Writing in this register clears the receive done flag. 177500 / KEYBOARD Kp D7 D6 D5 D4 D3 D2 Dl "bT| Key pressed 177540 / SCREEN DATA Keyboard data EL J Display screen data at preloaded screen address. 177404 / SCREEN DISPLAY ADDRESS TOP 14 BITS 11 10 9 8 7 6 5 4 3 2 1 1C1 COJ - Card address 12 bit common address 177405 / TOP 14 Same as 177404 but sets screen address and writes a '0' on screen. 177425 / TOP 14 Same as 177404 but sets screen address and writes a '1' on screen. 177410 / SCREEN DISPLAY ADDRESS BOTTOM 4 BITS Sets screen address (bottom 4 bits) C3 C2 CI COl Chip address 177411 Bottom 4 BITS Same as 177410 but sets screen address and writes '0' on screen. 30 177431 / BOTTOM 4 Same as 177410 but sets screen address and writes 'T on screen. 177402 / UART TRANSMIT REGISTER 1 1 D7 D6 D5 D4 D3 D2 Dl DO Data to be sent. 000000-00037 BOOTSTRAP LOADING ROUTINE 177775-177777 RESERVED FOR LOADER 31 INTERFACING GUIDE USING THE PERIPHERAL BUS. Sixty- four K of memory and device registers are accessable through indirect addressing and devices on the periperal bus should be designed to recognize and respond to an address within this field. The graphics version of the processor has a 4k slow peri- perals and memory address field with built in 500 ns delays. Device registers are conventionally located in the upper one K of memory. This allows for memory expansion without renister relocation in software. 64K 63K 4K IK 40 I II 2 I 3 I 4 I 5 I 1) fast device registers 2) expansion memory 3) slow memory and devices 4) main memory 5) ROM bootstrap Figure 9. Basic memory map. A typical device on the peripheral bus consists of an address recognizer, a renister and a tristate gate network if the device can write on the bus. Since common write and Pause Now lines are used for all peripherals, design must be such that devices perform these operations only when addressed. Extereme caution is exercised to make sure two sets of tristate gates are not driving the bus at the same time as oate failure could result. 32 SLOW DEVICES AND MEMORY . If a slow device is to be located in the upper 60K addresses, the Pause Now and Stop the Clock features must be used. Upon receivinq a write or Pause Mow signal, the device must pull down the Stop the Clock line as quickly as possible and for the duration of the data settling time keep it down. The clock must, therefore, be stopped within forty ns after the Pause flow or a new leadinn edqe will result causina next state execution. 74121 one-shots have an 30 ns propagation delay making them unsuitable for this application, '-'hen properly used, a 74122 can give a low value of 23 ns and is more useful. PERI3US LINES. Address and accumulator output lines dre TTL level driven by 7419(3 and 74157 intearated circuits within the processor. I.oadinn rules for these ICs must be observed. Data to the processor (Tocpu) is on a tristate bus. The proper transmitters and receivers (8t34) are used. Stop the Clock line is open collector driven and has a 360 ohm pull-up resistor. The nate used to sink the current is properly rated. The write line indicates that the processor is trying to write into a memory location. Data is valid throughout its duration. Initialize is low when initializinn. The external flag input can be used for whatever condition is desired as a branch on flag point. The branch is performed on a loqic one at this input. DATA ROUTING SYSTEM. In applications where many device renisters are used, instead of havino address recognizers and timinn circuitry for each renister it is more efficient to have a recoqnizer which recoo- nizes a block of renisters (the device renisters) usinn the top por- tion of the address, and recognize a reqister within that block usinn 33 the low part of the address (using one of 8 bits for a 'switch'). A data routing card, therefore, can consist of an address recognizer, delays and gating. Another advantage of the data routino card is that a decoder can be used to select devices to drive the tristate bus. Rus conflicts are avoided as the decoder never selects two drivers at once. BACK PANEL WIRING. To make the processor operational it is essential that a few of the back plane pins for the two card plug-in module be connected, as more than the twenty interconnecting wires are needed to electically join the two cards. The essential list is given below. In the terminal wiring list, complete interconnections between data router cards and other devices are shown. Sinnal CPU Card Memory card Pause now e e Wri te f 5 A8 P P A 9 n n A10 m m All 1 1 A12 k k A13 J J A14 h h +5v abc2 abc Gnd rvwxyz 12467 34 APPENDIX A DESIGN SCHEMATICS * t- 01 •*-> to t- J- •i— u 0) 0) D QJ ■M +J a; s- 4-> (A c J- QJ (/> •r- 3 X •^ D o to OJ c QJ u 10 r— OJ o. 0} i_ • E J- T- C re ■D +-> , to o k- ■C r— to *^- D O E j- re S- "D i- . tx qj a o * * n T u — 1 1 3 » 1 . t bus ector y mas iplex re ■M 3 D- 3 r- J- -M C > a. — ! QJ E 2: ) 11 * Zj 1 1 er Xi ■M 3 Cl 3 O re Q. 4-> L. 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O ° z - uj C E£B 3- 49 APPENDIX B BACK-PANEL WIRING AND INTERCONNECTIONS 50 PROCESSOR INTERCARD DIP CONNECTORS Al - Address Bl - Accumout 6 CI - Processor Input 4 A2 - 1 B2 - 7 C2 - 5 A3 - 2 B3 - 8 C3 - 6 A4 - 3 B4 - 9 C4 - 7 A5 - 4 B5 - 10 C5 - 3 A6 - 5 B6 - 11 C6 - 9 A7 - 6 B7 - 12 C7 - 10 A8 - 7 B3 - 13 C8 - 11 A9 - Accumout B9 - 14 C9 - 12 A10- 1 BIO- 15 CIO- 13 All- 2 Bll- Processor Input Cll- 14 A12- 3 B12- 1 C12- 15 A13- 4 B13- 2 C13- Not used A14- 5 B14- 3 C14- Fast Clock flote: Although no microconsole has been built, the OIP connectors would be an excellent point to obtain signals for such a device. TERMINAL CINCH PLUG This plug is wired to accomodate a keyboard, communications line, and an initialize/run switch. Pin 1 - Ground 2 - Keyboard bit 1 3 - 2 4 - 3 5 - 4 6 - 5 7 - 6 8 - 7 9 - 8 10- 9 11- +5 Volts 12- Initialize Pin 13 - Run 14 - Ground 15 - Oata into terminal 16 - Oata from terminal 17 - Not used 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 51 on r- 2 z: O UJ c 2: -0 •0 -0 -a -0 -a 2: OJ C1J c c c c c c V) 4-> 3 . 3 3 3 3 3 »— 1 3 -r- fO S-f— .— r— r— 1— CTlOO fc-r— i- U J- J- s_ I/O + + + S- D. 2 ffJ O^' D"> O) Ol O) 3 > 2 X >> N a. (_> a: o oo 1/0 UJ o o C£ c. u-> «rj- co c\j 1— o 1 — r-r-i-r-p-OlCOMOl/l^-rOOOr-O OOOOOOOOOOOOOOOO 1— c\joo«a-Lni£>r^cocri Oi— c\jco«d-u->*£)r>.cccy>Or— c\j -«— r— 1— r— r— r— (— 1— C\J C\J C\J CO CO C\J r— o 3 3 3 3 aaaa -o OOOO |-^V£)Lf)^l- tn re -a 0-0 cu 4- je t-> -*: r— E c O- $- 4-> 3 > 5 x >> N on ear re c 1/0 r>» «r> tn ^j- 1— r— 3 3 3 3 3 3 0.0.0.0.0.0. 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The basic terminal system consists of the following. 1. UART communication card 2. Processor card 3. IK processor memory 4. Data routing card 5. Screen display matrix generator 6. Screen display memory timing 7 to 9. 1 to 4 cards of screen memory 10. Power supply driver card The wiring list on the following pages follows the numbering conventions above. Extra cards may be included between cards 9 and 10 if more peripherals or memory are desired. 56 22 pin socket siqnal 1 2 3 4 5 acO r 22 1.9 acl s 21 2,8 ac2 t 20 7 ac3 u 19 6 ac4 V 18 ac5 w 17 ac6 X 16 ac7 y 15 ac8 14 ac9 13 aclO 12 acll 11 acl2 10 acl3 9 acl4 8 acl 5 7 kp h kbO 12 kbl 11 kb2 10 kb3 9 kb4 m kb5 1 kb6 k kb7 i clock check 18 +5 a,b a,b a,b b,t b,w +5 c,2 c 20 +12 -5 -12 20 m s 1 r d pause now e e write 19 f 5 9 stop clock 3 s load top 14 2 1 load bot. 4 3 n write data 6 write set 7 aO y 8 al X 12 a2 w 1 a3 V 4 a4 u 5 a5 t P or card: 5 6 ,9 ,8 7 1 6 2 3 4 5 6 7 8 9 10 11 u 10 v,b 13,21 13,21 13,21 13,21 b b b b d d d d c c c c 57 signal 123456789 10 a6 s n a7 r m a8 p p a a9 n n k alO m m ,i all 1 1 h al2 k k f al3 j j e al4 h h d al5 c tocpuO f 22 tocpul e 21 tocpu2 d 20 tocpu3 c 19 tocpu4 4 18 tocpu5 3 19 tocpu6 2 16 tocpu7 1 15 tocpu8 14 tocpu9 13 tocpul 12 tocpull 11 tocpul2 10 tocpul 3 9 tocpul 4 6 8 tocpul5 5 7 10 around 21,22 r,v 1,2 14,22 22, p w,z l,t l,t 1 ,t l,t qround z w,x 4,6 z z z z z z qround y,z z option bit 8 init 13 3 receive drive bus 15 s keyboard drive bus 16 . r load uart n 1 uart data in p data output 11 h sinqle chip enable 5 n a 10 f f f f b 11 h h h h bit clock 12 p p p p 58 siqnal 123456739 10 13 video output request read and load sr mem count clr nem count load inc count display data clr sr card 1 c card 1 d card 2 c card 2 d card 3 c card 3 d card 4 c card 4 d addressO address! address2 address3 address4 address5 address6 address7 addre$s8 address9 addresslO addressll access data 1 access data 2 access data 3 access data 4 all chips enabled load latch write enable data chain in 1 data chain in 2 data chain in 3 sync load 14 k n n n n 15 r 16 P 17 f 18 y 19 m m m m J J k k f J h k d J e k a .1 c k 13 3 3 3 3 14 5 5 5 5 15 6 6 6 6 16 3 8 8 3 17 9 9 9 9 18 11 11 11 11 19 12 12 12 12 20 14 14 14 14 21 15 15 15 15 22 17 17 17 17 y 18 18 18 18 X 20 20 20 20 a X c X d X e X 1 e e e e m s s s s s 22 r 22 y r 22 y r 22 y 12 59 APPENDIX C CONSTRUCTION TECHNIQUES AND ADDENDUM SHEETS 60 CONSTRUCTION TECHNIQUES. Prototype development has shown that the fol- lowing methods produce the most reliable processor. 1) All sockets should be firmly soldered, screwed or glued to the circu- it cards. 2) Adequate decouplinq should be provided by using one or more .2 uf capacitors per each three inteqrated circuits. 3) *\ 200 uf filter capacitor should be provided on the processor board for line regulation. 4) IK. pull-up resistors are needed on the decoding ROM. Vertical, dual inline mountino was found to be the best method of mountinn these resis- tors. 5) The ROM codes are shown in the desiqn schmatics. Proper POM pronram- minq techniques should be used. 6) Many ground and positive voltage pins are allocated on the processor and memory cards to assure uniform power distribution. 7) DIP plugs and sockets provide reliable intercard connections. 8) All leads qoinq to MOS inputs must be properly loaded with 470 ohm resistors to prevent ringing. 9) AH unused inputs should be clamped to positive or around to prevent oscillations. 61 RECOMMENDED DEBUGGING TECHNIQUES The most efficient way to pet the processor operational is to build one completely and step instructions throuqh their cycles with a manual clock. Instructions can be fed into the processor throqh the intercard dip connectors and the accumulator may be watched. The ini- tiaization flip flop and everythina it should initialize should be checked first. It was found that monitorinn the whole accumulator with LEDs was helDful. For sequencer checkout, wire wrapinq wires to the state out- puts and drivinq labled LEDs is most efficient. The whole PC and ad- dress reqister may be watched with LEDs but it was found that the lower four address bits of the address multiplexer were nood enouqh, especial- ly in later debuqqina staqes. If careful wirino practices are observed, debugqing should not take lona. If the whole system seems dead, check for: 1) Power and polarity wirino at the ICs 2) All enable, presets and clears at proper levels 3) "11 ICs in proper direction, location and all pins in sockets. rase 2 is the usual problem. If addressinq seems to do stranqe thinqs, the lookahead connections on the counters should be checked. 62 LOADING PROGRAMS UNDER BOOTSTRAP VERSIONS OriF AND TWO Pronrams are loaded into the processor memory from an external source such as the control linn computer. A bootstrap pronram is stored in the lower 32 words of memory to perform this initial pronram loadino. |lr )on processor initialization, the pronram counter of the pro- cessor is set to location zero and the bootstrap pronram performs the initial nronram load. Versions one and two first send a character (a ! character) to the control linn processor which sinnal a request to be loaded. The control linn computer then sends the pronram to be loaded as a strinn of characters. The only difference between bootstrap version one and two is in the way words are composed from the einht bit charac- ters in the input strinn. Version one assumes all 8 bits are valid and packs two characters per word while version 2 packs three characters per word so a £ bit loading format can be used. The first two words received (4 or 6 characters) specify the oroaram's lennth and address to be loaded at. The remaininn words are loaded into processor memory until the nronram lennth is reached. The last pronram instruction is then executed. The last instruction, there- fore, acts as a "jump to pronram start point" instruction. Pronram loadinn must not write in the ROM area (address to 31 ) and the lennth word (word number one in the loadinn process) is the total of all words loaded, includinn the address and lennth word. The address word (word two of the load) is the load start point minus one. The followinn pronram is bootstrap version two. 63 nxtwrd nxtbyt wait fill fil2 fil3 fil4 fil5 adr arcvr atrans temp ctr ptr bytct end i orn 000000 cheap 1 bootstrap loader loadm 0005 atrans adr ptr 1775 bytct temp st 1 st loadm st 1 ls2 ls2 ls2 st 1 i bpz st i an dm or s incs bm 1 st i decs bmz i incs b 000000 000000 000000 001776 177440 177402 000000 000000 000000 000000 temp arcvr wait arcvr 0077 temp bytct nxtbyt temp ptr ctr ptr ptr nxtwrd Finure C-l . Bootstrap version 2, 64 POWER AMD GROUNDING To insure a reliable system it is most important that nood power bussinn and decouplinq techniques be followed. Multiple nround and power pins on circuit cards, many small decouplinq capacitors, heavy power backplane wiring and heavy oround planes on the cards are all important. The 40K RAM cards were found to be extremely sensitive to poor oroundinn conditions. 'loisy nround levels and uneven power supply levels produce stranoe, data sensitive, intermittent problems which are extremely dif- ficult to narrow down to their real cause. For a hioh speed device such as this terminal, excellent qroundinn is a must. Form AEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT f Sm Instruction* on /fevers* Sid* I 1. AEC REPORT NO. C00-2383-0033 2. TITLE GRAPHICS ONE TERMINAL DESIGN AND USER'S MANUAL 3. TYPE OF DOCUMENT (Check one): d a- Scientific and technical raport (~| b. Confaranoa papar not to ba publishad in a journal: Tltla of conference Data of conference Exact location of confaranoa. Sponsoring organization □ c. Othar (Spacify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): K"l a. AEC's normal announcement and distribution procedure* may ba followed. I | b. Make available only within AEC and to AEC contractor* and othar U.S. Government agencies and thalr contractors. ~2 c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) C. W. Gear Professor and Principal Investigator Organization Department of Computer Science University of Illinois at Urbana-Champaign Urbana, IL 1*1801 Signature u-- Date July 1976 FOR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: 8. PATENT CLEARANCE: [~~1 a. AEC patent clearance has been granted by responsible AEC patent group. Q b. Report has been sent to responsible AEC patent group for clearance. I | c. Patent clearance not required. BIBLIOGRAPHIC DATA SHEET 1. Report No. UIUCDCS-R-76-814 4. Title and Subtitle GRAPHICS ONE TERMINAL DESIGN AND USER'S MANUAL 3. Recipient's Accession No. 5. Report Date July 1976 6. 7. Author(s) BRUCE A. ARTWICK AND ALFRED D. WHALEY 8- Performing Organization Rept. No -UIUCDCS-R-76-814 9. Performing Organization Name and Address Department of Computer Science University of Illinois at Urbana-Champaign Urbana, IL 61801 10. Project/Task/Work Unit No. C00-2383-0033 11. Contract /Grant No. US ERDA E(ll-l) 2383 12. Sponsoring Organization Name and Address United States Energy Research and Development Administration 9800 South Cass Avenue Argonne, IL 60439 13. Type of Report & Period Covered 14. 15. Supplementary Notes 16. Abstracts Described is a graphics terminal using raster scan on an ordinary TV monitor. The scan is done out of a bank of 4K dynamic rams which are set or reset asynchronously by an independent microprocessor. Special features are the microprocessor built out of ordinary 7400 series parts which does all graphics, text and communications and the method for storing the raster image in rams. 17. Key Words and Document Analysis. 17a. Descriptors Graphics terminal microprogramming raster scan programmable terminal microprocessor computer graphics programmable terminal 17b. Identifiers/Open-Ended Terms 17e. COSATI Field/Group 18. Availability Statement Unlimited FORM NTIS-35 ( 10-70) 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 71 22. Price USCOMM-DC 40329-P71 OEC \5 1976 UNIVERSITY OF ILLINOI3-URBANA 3 0112 039572828 in fflffB H EftfiAtV ■Hfl mtf is S3! TCHX MHV M