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[MoV* uiucDcs-R-72-508 
 
 coo-114 69-0202 
 
 HARDWARE /SOFTWARE INTERFACE FOR 
 THE STEREOMATRIX DISPLAY 
 
 by 
 Ian MacDonald Cunningham 
 
 June 1972 
 
UIUCDCS-R-72-508 
 
 HARDWARE /SOFTWARE INTERFACE FOR 
 THE STEREOMATRIX DISPLAY* 
 
 by 
 Ian MacDonald Cunningham 
 
 June 1972 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS 
 URBANA, ILLINOIS 6l801 
 
 Supported in part "by the Department of Computer Science and the Atomic 
 Energy Commission under contract US AEC AT(ll-l)lU69» and submitted in 
 partial fulfillment of the requirements of the Graduate College for the 
 degree of Master of Science in Computer Science. 
 
iii 
 
 ACKNOWLEDGMENT 
 
 I would like to thank my advisor, Professor C. W. Gear, 
 for his support, Miss Barbara Hurdle for her typing, and 
 Mr. Harold Lopeman for his excellent work in constructing the 
 interface. I would also like to thank Professor W. J. Poppelbaum, 
 the principal investigator for the Stereomatrix; and 
 Professor W. J. Kubitz, Mr. Shiv Verma, Mr. Steve Whiteside, and 
 Mr. Chuck Pirnat for their assistance. IVy wife deserves many 
 thanks for both her assistance and understanding. 
 
iv 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. SYSTEM OVERVIEW 2 
 
 3. HARDWARE INTERFACE 5 
 
 3.1 Design Philosophy 5 
 
 3.2 Programming the Interface 6 
 
 3.3 Overview of Hardware Logic 11 
 
 3.U Line Generator Algorithm lk 
 
 k. SOFTWARE SUPPORT IT 
 
 k.l Introduction IT 
 
 k,2 Graphics Data Structure IT 
 
 U.3 Stereomatrix Software 21 
 
 k.h Software Implementation 25 
 
 5. CONCLUSIONS 2T 
 
 LIST OF REFERENCES 32 
 
 APPENDIX A 33 
 
 APPENDIX B 35 
 
V 
 
 LIST OF FIGURES 
 
 Figure I'-u^.- 
 
 1. Stereomatrix Display System 3 
 
 2. Display Command Formats 8 
 
 3. Interrupt and Address Extension Registers 11 
 
 k. Block Diagram of PDP-8/I Stereomatrix Interface 13 
 
 5. Line Generator Algorithm 16 
 
 6. Graphics Data Structure 19 
 
 7. Position for Modified Sensor Outputs 31 
 
1 . INTRODUCTION 
 
 A random access, three-dimensional laser display called 
 Stereomatrix has been built by a group in the Department of Computer 
 Science at the University of Illinois [l]. Three-dimensional wire 
 figures are displayed by generating separate images for the left and 
 right eyes. The light from the laser is split into two beams, and 
 then the polarization of the left beam is rotated 90 degrees. Both 
 beams are deflected along the x and y axis, resulting in a double 
 image. The observer wears glasses with oppositely polarized lenses 
 which give the visual effect of a third dimension. The observer's 
 position is sensed by an infrared light source contained on the 
 glasses. Movements of the observer are detected and automatic re- 
 displaying of the figure as it would appear to the observer from the 
 new position occurs. The observer also may scale, rotate, and 
 translate the picture under complete hardware control. A three- 
 dimensional cursor is also displayed by the hardware which permits 
 initializing of points in space and identifying lines that already 
 appear on the screen. 
 
 Wire figures for the display are supplied by either 
 PAGAN [2], a hardware generator of geometric figures, or by a PDP-8/I 
 computer. The design of the latter' s interface and programming system 
 is described in the report. 
 
2. SYSTEM OVERVIEW 
 
 A block diagram of the Stereomatrix-PDP-8/l graphics system 
 is shown in Figure 1. The Stereomatrix display can be divided into 
 four subsections: laser and deflecting optics, position sensor, 
 coefficient generator, and transformer. 
 
 The light source is a 2 watt argon laser. Acoustical 
 deflectors and lenses are used to position and focus the beam on the 
 rear of the screen. Beam positioning is random access, requiring a 
 constant 6.8 microseconds to move to any point on the screen 
 (1.5 x 10 points/second). 
 
 The position sensors continually monitor the infrared light 
 source on the observer's glasses. The two angles supplied by these 
 sensors plus the distance between them are sufficient for calculating 
 the observer's location. 
 
 The coefficient generator controls rotation, translation, 
 and scaling of the figure. The generator is controlled directly by 
 several switches which allow selection of one of the above operations 
 plus axis and direction and a reset button to return the figure to 
 its initial position. 
 
 The transformer receives the figure from the computer in 
 digital form and converts it to analog. The output of the coefficient 
 generator, which is. a matrix, is used by the transformer to modify the 
 figure as requested by the user. The figure is then modified again 
 using the data from the position sensors., creating the final two 
 perspective drawings. All operations are performed digitally by the 
 coefficient generator, but the calculation rate of the transformer 
 requires that the calculation be performed on analog values. 
 
USER CONTROL BOX 
 
 POSITION 
 CONTROL 
 
 OBSERVER WITH SPECIAL 
 GLASSES AND LIGHT 
 
 DISPLAY CONTROL BOX 
 
 SCREEN 
 
 Y \ 5 ? 
 
 ^POSITION SENSOR 
 
 jr 
 
 TRANSFORMER 
 
 COEFFICIENT k_ 
 GENERATOR 
 
 INVERSE 
 TRANSFORMER 
 
 DISPLAY 
 
 INTERFACE 
 
 *£- 
 
 ^1 IV 
 
 Je^. 
 
 MEMORY 
 
 AND 
 D.M.A. 
 
 I/O BUS 
 
 PDP-8/I 
 C.P.U. 
 
 Figure 1. Stereomatrix Display System 
 
A hardware cursor is also incorporated in the display. An 
 inverse transformer converts the cursors co-ordinates from the 
 observer's space to computer space before transmitting them back to 
 the interface. 
 
 The transfer of data between the display and the interface 
 utilizes both digital and analog signals. The PDP-8/I generates 
 display files for the interface which then transmits a sequence 
 of three-dimensional co-ordinates. The display interface and 
 computer transfer control information using the PDP-8/I I/O bus, 
 and the interface accesses the display files using the Direct Memory 
 Access (DMA). 
 
 The display and the computer are approximately 200 feet 
 apart. The interface and communication controls operate asynchronously 
 with a maximum data rate of approximately 2.5 x 10 co-ordinates 
 per second. 
 
3. HARDWARE INTERFACE 
 
 3.1 Design Philosophy 
 
 The project was motivated by a need to test the Stereomatrix 
 display and to study user requirements in a three-dimensional graphic 
 environment, and not the development of a new or novel computer/display 
 interface. In order to design and implement a total graphics system 
 within a reasonable time limit , some hardware compromises have to be 
 made. For example, a hardware line generator, while common in most 
 sophisticated displays, was not included. Direct program manipulation 
 of the three co-ordinate registers would reduce the usable computing 
 power of the machine and would not exceed the minimum transmission 
 rate. As a result, a line generator of limited directional powers 
 was implemented. A line of up to 63 points is generated in one of 
 twenty-seven directions. This is done by controlling the increment 
 for each axis to -1, 0, or +1. These directions plus two control 
 modes are encoded into five bits of a display command. Another bit 
 is reserved for the intensity ( ON/OFF) and the remaining six bits are 
 either display status or length information. Direct branches and 
 subroutine calls, often embedded in the display file, were implemented 
 in the graphics syntactic data structure, resulting in considerable 
 simplification in the control. 
 
 All data is transmitted as digital signals (except cursor 
 co-ordinates) which exist at the display as analog values. Asynchronous 
 circuits control both the interface and the transmission of co-ordinates 
 to the display. As a result, any increase in the plotting rate of the 
 display (presently limited by laser optics) will automatically increase 
 the speed of the interface . 
 
Four flags generate interrupts. One is set by the interface 
 upon completion of a display file while the other three are set at the 
 display by 
 
 1. the user control "box switches, 
 
 2. the cursor position interrupt switch, or 
 
 3. "by the incidence of a displayed line with 
 the cursor. 
 
 3.2 Programming the Interface 
 
 The computer must transmit a sequence of points that will 
 represent the desired graphic image when it is displayed. Because the 
 display does not have its own memory and the image is not stored on 
 the screen, this process must occur continually. The display interface 
 uses the PDP-8/I I/O "bus to initialize registers, start hardware 
 sequences, and notify the software of interrupt conditions. The direct 
 memory access facility, DMA, fetches information sequentially from the 
 computer's main memory. This data is used to generate the sequences 
 of co-ordinates. Conceptually, the interface can be broken into three 
 sections: picture generation, cursor co-ordinates, and interrupts and 
 miscellaneous controls. The following discussion defines and explains 
 the usage of all interface instructions. Appendix A lists all 
 instructions, their mnemonics, and their octal value. 
 
 Picture Generation 
 
 The X , Y , and Z co-ordinate registers which position the 
 laser beam are initialized by direct transfers, from the accumulator. 
 The 10-bit values are left justified and expressed in sign and 
 magnitude notation. The left most bit is a "l" for negative values. 
 
The load instructions LDX (LoaD X), LDY, and LDZ transfer the contents 
 of the accumulator to the X, Y, and Z co-ordinate registers, respectively, 
 The contents of the accumulator (AC) remain unchanged and the two low- 
 order bits are ignored. 
 
 With this initialization completed, the memory address of the 
 display file for the DMA is transferred to the interface and the display 
 started. The program code is 
 
 CLA / CLEAR AC 
 
 TAD ADRES / ADDRESS OF DISPLAY FILE 
 
 DSPRGO / START DISPLAY 
 The instruction DSPRGO (DiSPlay Reset and Go) is the OR of the two 
 display instructions STPDSP (SToP DiSPlay) and DRAW. STPDSP forces the 
 interface logic into the halt state if it has not already been entered 
 and the display completed flag is cleared. 
 
 Next, DRAW transfers the contents of the AC to the DMA 
 address register in the interface and starts the display. Note that 
 the contents of the address register are unchanged by the STPDSP 
 instruction. 
 
 The display file referenced by DSPRGO must contain one or 
 more single word display commands. The format for the three types of 
 commands is in Figure 2. A typical display file contains a load 
 status command followed by a number of line commands and completed with 
 a halt. The halt command sets the display completed flag which results 
 in a program interrupt. SKDF (SKip on Display File done) tests this 
 flag. Another display file may be initiated without re-initializing the 
 co-ordinate or display status registers since they are not affected by 
 the halt command. Lines which exceed the limit of the screen are 
 
Load Status Command 
 
 A, B, and C fields are loaded into display status register. 
 Bit 1 56 7 8 9 10 11 
 
 CXI '^ I a Fb 
 
 A: Scale 00 Every point 
 
 01 Every 2nd point 
 
 10 Every 3rd point 
 
 11 Every Uth point 
 
 B: Free "bits for future use 
 
 C: Brightness proportional to 
 value, i.e. 11 is brightest 
 
 Line Command 
 
 Plots a line in 1 of 27 directions and up to 63 scaled 
 points in length. 
 
 Bit 1 5 6 11 
 
 I DIRECTION LENGTH 
 
 I: Line is intensified if bit is "l" 
 
 DIRECTION: Value is ( (Z*3) + Y) * 3 + X where 
 
 X, Y, Z = if no axial component 
 = 1 for positive increment 
 = 2 for negative increment 
 
 LENGTH: Length of line before modified by scale 
 
 Halt Command 
 
 Picture generation is stopped and display flag is set. 
 Bit 1 5 6 11 
 
 Figure 2. Display Command Formats 
 
wrapped around by the interface and no interrupt is generated. A 
 co-ordinate register value of +511 when incremented becomes -511. 
 
 Cursor Co-ordinates 
 
 The current position of the cursor is always held in a 
 buffer in the interface and is accessed by the instructions RDX 
 (ReaD X cursor co-ordinates), RDY, and RDZ. The accumulator is 
 automatically cleared before the co-ordinate value is transferred 
 to the AC. The value is expressed in 10 bits, left justified 2's 
 complement notation. 
 
 Display Interrupts and Miscellaneous Controls 
 
 Three additional registers are of interest to the programmer: 
 the memory address extension register, the switch register, and the 
 interrupt register. The first contains the extended address bits 
 required by the DMA. It is loaded along with the interrupt register 
 which is discussed below. 
 
 The switch register holds the output from the five switches 
 on the user control box. This register is OR'ed into the AC and then 
 cleared by the REDBX (REaD BoX) instruction. Depressing switch i 
 (l <_ i <_ 5) will result in AC bit 12 - i being a "l" upon completion 
 of this instruction. The sixth switch on the user box (marked "I") 
 sets a bit in the interrupt register. 
 
 The interrupt register holds the cursor, incidence, and 
 switch register flags. If the OR of these flags is "l", a program 
 interrupt occurs. SKBF (SKip on Buffered Flags) tests for this 
 condition. In order to determine which flags are set, this register 
 
10 
 
 is OR'ed into the AC by the RDFLG (ReaD FLaGs) instruction. The 
 specific bit meanings are shown in Figure 3a. The CLRFLG (CLeaR 
 FLaGs) instruction both resets flags in the interrupt register and 
 loads the memory address extension register. The format of the AC 
 bits is shown in Figure 3b. A flag is cleared only if the 
 corresponding bit was a "l". When servicing an interrupt, it is 
 advisable to clear only the one flag as the others may have been 
 subsequently set and a loss of the interrupt will occur. Both the 
 cursor and switch register flags, unlike incidence, notify the 
 program that action is required, but do not stop picture generation. 
 
 The incidence flag is set only after the incidence mode 
 has been enabled in the display and the cursor is "near" to a line 
 drawn by the computer. When this flag is set, the RUN flip-flop 
 in the interface is cleared, causing picture generation to cease. 
 The RDCMA (ReaD Complement of Memory Address) instruction OR's the 
 logical complement of the memory address used by the DMA into the AC. 
 This address is normally one more than the address of the display 
 command plotting the point, but it may be two more due to look-ahead 
 in both the display and interface controls . Upon completion of any 
 processing, the display may be continued without loss of information 
 by the RESUM (RESUMe) instruction. The AC is not used. 
 
11 
 
 Bit 1 2 
 | FO | Fl | F2 [ 
 
 Figure 3a. Accumulator bits for RDFLG instruction 
 
 Bit 1 2 9 11 
 
 Figure 3"b. Accumulator bits for CLRFLG instruction 
 
 FO : Cursor Position Interrupt 
 Fl : Cursor Incidence Interrupt 
 F2 : User Control Box Interrupt 
 MEA: Memory Address Extension for DMA 
 Figure 3. Interrupt and Address Extension Registers 
 
 3.3 Overview of Hardware Logic 
 
 A block diagram of the Stereomatrix interface in Figure k 
 includes both the major cards with their functions and major control 
 signals contained in the interface. Each of the rectangles represents 
 one card (except Accumulator In). In order to simplify both 
 construction and maintenance of the interface, identical cards were 
 designed where possible. Consequently, 13 cards of the interface 
 represent only four designs. 
 
 The Sequencer which is the heart of the picture generating 
 process requests data by sending BRK1 to the DMA control card. It 
 handles the transfer of display commands from the computer's memory 
 and the incrementing of the memory address register. The Sequencer 
 proceeds upon receipt of the NODAT signal. The Direction Decoder 
 deciphers the command field. The halt command stops the Sequencer 
 and interrupts the processor while the status command gates the length 
 
12 
 
 register into the display status register and B'RKl is set again for 
 more data. If neither of these commands occur, the Sequencer waits 
 for a data request from the display (LKEQ) and then responds with 
 LDATGO level. The co-ordinate registers are up/down sign and 
 magnitude binary counters. The COUNT pulse from the Sequencer updates 
 these registers based upon inputs from the Direction Decoder which 
 specifies +1, 0, or -1 increments. From one to four COUNT pulses, 
 depending upon the scale in the display status register, are generated 
 by the Sequencer. The length of the line which is stored in the DMA 
 Control card is monitored by the Sequencer and decremented after each 
 new co-ordinate is accepted by the display. When the length becomes 
 zero, the Sequencer requests another display command from memory. If 
 the intensity bit in the line commands is OFF, the Sequencer operates 
 at its maximum rate of approximately U00 ns. per register increment. 
 The Sequencer and DMA control run asynchronously except for one state 
 responsible for clocking the co-ordinate registers. The algorithm 
 is discussed in more detail in the next section and the logic drawing 
 is in Appendix B. 
 
 Five cables each transmit 10 digital signals between the 
 interface and the display. This high speed data transmission system 
 utilizes balanced, terminated, twisted pair lines. This method has 
 high common-mode noise rejection. 
 
 The three A/D converters, one for each cursor co-ordinate, 
 are controlled by a signal (not shown) from the display. Upon 
 completion of a conversion, the results are stored in the A/D Data 
 Buffer. Consequently, cursor co-ordinate values are available to the 
 program while another A/D conversion is being performed. 
 
13 
 
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 The three Accumulator In cards, each controlling four bits, 
 select one of six possible inputs and gate that one onto the PDP-8/I 
 I/O Data Bus. 
 
 The interrupt register is contained in the DMA Control card, 
 while the display file completed flag constitutes part of the Sequencer. 
 
 The interface is easily modified for similar future 
 applications. For example, only the co-ordinate registers need be 
 modified to change from the sign and magnitude notation presently 
 used. If the new device is in close proximity to the interface, the 
 line drivers and receivers may be removed and replaced with ribbon 
 or similar type cables. 
 
 3.^ Line Generator Algorithm 
 
 The line generator algorithm is the Sequencer card and is 
 flowcharted in Figure 5 with an accompanying definition of terms in 
 Table 1. 
 
 Data transfers and point generation rates of the Sequencer 
 are controlled by two external signals: LKEQ and LDATGO. To initiate 
 a transfer the display raises LKEQ (see Figure k) . With new co-ordinate 
 values, the interface responds with LDATGO which the display uses to 
 gate the data into its registers. It then drops LKEQ which automatically 
 clears LDATGO at the interface and the transfer is completed. The 
 Sequencer uses two internal signals to determine the present state of 
 
 the transfer operation. One signal, LFREE = LKEQ + LREQ. LDATGO, is 
 high whenever the display is not in the process of strobing co-ordinate 
 
 values into its registers. The second signal, LRDY = LKEQ. LDATGO is 
 high only when the display is requesting more data and the interface 
 
15 
 
 has not responded. These signals ensure correct sequential operation 
 for all transmission rates. 
 
 NODAT is set to "l" if another display command is 
 
 required from memory. It is cleared after the 
 data is available. 
 
 BRK1 is set to initiate DMA transfer. 
 
 HALT is "1" if the display command is HALT. 
 
 LFLAG the interrupt flag for the display file done. 
 
 STATUS is "1" if the display command is LOAD STATUS. 
 
 LFREE is set whenever updating the co-ordinate registers 
 
 will not cause transmission of erroneous data. 
 
 INT has value "l" if the current contents of the 
 
 co-ordinate registers have been plotted. The 
 algorithm prevents double intensification of 
 identical sequential points, e.g. last point 
 of a line and first of next one are identical. 
 
 I is the intensity ON/OFF bit of a display command. 
 
 A value of "l" implies ON. 
 
 LRDY set when display is requesting more data. 
 
 LDATGO a transition to high signals the display to 
 
 gate in new co-ordinate values. 
 
 CNTO is "0" when LLENGTH contains zero; otherwise, 
 
 SCALER a 2-bit register compared with SCALE to control 
 
 number of register increments per transfer. 
 
 LLENGTH 6-bit register containing length of line left 
 to plot. 
 
 SCALE the scale value ( 2-bit s) held in display status 
 
 register. 
 
 Table 1. Signal Definitions for Figure 5 
 
16 
 
 (SCALER * *N 
 SCALEB +1 J 
 
 Figure 5. Line Generator Algorithm 
 
17 
 
 k. SOFTWARE SUPPORT 
 
 U.l Introduction 
 
 The Stereomatrix display system was developed to investigate 
 the projection of three-dimensional, computer drawn images. No 
 specific application was being considered while implementing this 
 system. Rather, a study of user/computer communications was needed 
 to evaluate possible types of user/computer controls required in this 
 environment. Consequently, in designing the software support, no 
 effort was made to incorporate any semantics into the graphic structure. 
 The graphics system supports only a syntactical structure and any 
 implied semantics to the user is only in the form, "What you see is 
 what you get." 
 
 The display hardware includes controls for manipulating only 
 the entire picture. The software extends this power by facilitating 
 adjustments of both subpictures and elements (defined in next section). 
 In addition, point identification is extended upward to include element 
 and subpicture selection. The cursor controls and user control box 
 switches are sufficient for implementing drawing routines, since no 
 semantic information is required by the graphics package. 
 
 The following sections discuss the graphics data structure, 
 a sketch routine and system software implementation. 
 
 U.2 Graphics Data Structure 
 
 A diagram of the data structure is shown in Figure 6. It 
 contains all the information required to initialize the co-ordinate 
 registers, load status, and plot lines. This structure is separated 
 
18 
 
 into five levels: picture heads, subpicture initiators, subpicture 
 heads, element initiators, and elements. 
 
 Picture Heads : Up to six pictures are held in storage and are named 
 PICTNO through PICTN5. Only PICTNO is displayed; the others store 
 images which are displayed by copying to PICTNO. Each picture has 
 one 1-word head which points to a list of subpicture initiators. 
 The picture heads are stored in fixed memory locations and may contain 
 a null pointer (binary zero). If PICTNO is null, nothing is displayed. 
 
 Subpicture Initiators : A unique , singly linked list of subpicture 
 initiators exists for each picture head containing a non-zero pointer. 
 The initiator provides new co-ordinate register values for positioning 
 the subpicture. In addition, it provides a pointer to the subpicture 
 head, a pointer to the next initiator and an identification field 
 (I.D.). The I.D. fields are not currently used and were incorporated 
 to allow future expansion of the structure. 
 
 Subpicture Heads : The subpicture incorporates one or more picture lines 
 (elements) into a graphical unit. The subpictures are position- 
 independent since the co-ordinate registers are never reloaded. 
 Repositioning of the beam from the end of one line to the start of the 
 next is performed by plotting lines with the intensity OFF. The first 
 three fields of the subpicture head are the avial components of a vector from 
 the initial point to the final co-ordinate of the subpicture. A pointer to a 
 list of element initiators, a COUNT field, and ah I.D. field completes the 
 subpicture head. The COUNT field contains the number of subpicture initiator; 
 
19 
 
 PICTURE HEADS 
 
 SUBPICTURE 
 INITIATORS 
 
 SUBPICTURE 
 HEADS 
 
 ELEMENT 
 INITIATORS 
 
 ELEMENTS 
 
 * All numbers in octal 
 
 Figure 6. Graphics Data Structure 
 
20 
 
 pointing to this subpicture. As references to a subpicture are 
 removed, the COUNT is decremented (a subpicture may appear more than 
 once in a picture and in one or more pictures). When this value 
 becomes zero, the subpicture is deleted. 
 
 Element Initiators : Every subpicture head points to a list of one or 
 more element initiators. The first field of the initiator contains 
 the address of an element and the second field point to the next 
 initiator. This list is unique to each subpicture head and is deleted 
 with it. 
 
 Elements : The elements are variable lengthed files containing several 
 control fields and a sequential list of display commands. The first 
 two fields, SIZE and NEXT, are used by the storage allocation routines. 
 The AX, AY, and AZ fields contain the components of a vector from the 
 beginning to the final co-ordinate of the element. The COUNT field 
 again determines when the element is no longer required. An element 
 may also appear more than once in a subpicture and in more than one 
 subpicture. 
 
 The low level software (further explained in a subsequent 
 section) contains routines for insertion, deletion, and modification 
 of nodes and display files. The plotting rate of the graphics system 
 is not degraded by the complexity of the data structure since list 
 transversal operates in parallel with line generation. A subpicture 
 is repositioned by modifying the co-ordinate values in the subpicture 
 initiator. Modification to a subpicture causes all displayed instances 
 
21 
 
 to be modified. The unintensified lines which permit subpictures to be 
 position independent are "plotted" at HOO ns . per point and do not 
 significantly decrease the amount of displayable information. The 
 alternative of reloading the co-ordinate registers would decrease the 
 simplicity of subpicture control and would require more processor time. 
 In addition, many subpictures will be localized images containing short, 
 unintensified lines. 
 
 The graphics structure simplifies many operations and utilizes 
 storage efficiently. The vector in the subpicture head facilitates 
 the concatenation of another element to the subpicture. Duplication of 
 a subpicture only requires the addition of another subpicture initiator, 
 adjustments to several pointers , and an increment to the COUNT in the 
 subpicture head. 
 
 U.3 Stereomatrix Software 
 
 A drawing package was developed to evaluate the interactive 
 controls available and to permit experimentation with possible future 
 graphical applications. An understanding of the data structure is 
 essential since the picture building procedures use this as a basis. 
 Only PICTNO is modifiable since it is the only image displayed. 
 
 The Stereomatrix user communicates with the system via the 
 switches on the user control box, the cursor joy stick, and its 
 associated switches. The user control switches, numbered 1 to 5 
 (left to right), set bits in a buffer register. The sixth switch 
 generates a computer interrupt causing the program to read this buffer 
 and initiate a response. In the following discussion, "BTj" denotes 
 
22 
 
 pressing switch "j" and then the interrupt switch. If a combination 
 of switches is required, all must be depressed "before requesting 
 the interrupt. IONLY signifies an interrupt with no other switches 
 previously set. 
 
 There are three switches associated with the operation of the 
 cursor. Pressing the switch marked "M" will cause a cursor interrupt 
 which alerts the program of the current cursor position. When the 
 M C" switch is pushed, an incident interrupt will occur whenever the 
 cursor is in close proximity to a line on the screen. This feature 
 is disabled when "D" is pushed. In the explanation below, the 
 letters "M", "C", and "D" denote pressing the switches marked by these 
 symbols. The controls for rotation translation and scaling are also 
 adjacent to the cursor and their operation is self-explanatory. 
 
 Nine modes of operation are controlled by the user switches 
 with external inputs being interpreted uniquely for each mode. The 
 IONLY input from the user switches will terminate any mode and force 
 entry to mode zero from which all other modes may be entered. The 
 remaining eight modes function as follows : 
 
 Mode 1: Straight Element Drawing 
 
 BT1 enters this mode. M locates one end on the straight line 
 at current cursor position. The other end follows the cursor. M 
 again completes the line at its last position. Another line is started 
 by M and IONLY will exit back to mode zero. In addition to the element, 
 a subpicture initiator, subpicture head, and element initiator are 
 added to the data structure of PICTNO. 
 
23 
 
 Mode 2: Cursor Element Tracing 
 
 BT2 enters mode. M initiates trace at current cursor position 
 and it follows the path of the cursor. M completes this trace and 
 M again will initiate another. IONLY exits back to mode zero. The 
 same data structure as in mode 1 is added to PICTNO. 
 
 Mode 3: Element Identification and Deletion 
 
 BT3 enters mode. C enables detection hardware. The element 
 identified by the cursor is constantly flashed on and off until 
 either another element is identified or other actions are taken. 
 BT3 will delete an identified element. If the element deleted is the 
 only one in the subpicture, then the mode is forced into subpicture 
 deletion (mode k) . IONLY exits from this mode and returns any 
 identified element to its normal state. 
 
 Mode h: Subpicture Identification and Deletion 
 
 BTU enters mode. C enables detection hardware. Subpictures 
 are identified in a similar manner to elements. BTi+ will delete an 
 identified subpicture. The subpicture initiator will be deleted 
 from the list of initiators for PICTNO and if COUNT field has value 
 "one" in the subpicture head, then it also will be deleted. IONLY 
 exits from mode and returns any identified subpictures to their 
 normal state. 
 
2k 
 
 Mode 5: Subpicture Assimilation 
 
 BT5 enters mode. C again enables detection hardware. A host 
 subpicture must be identified with the cursor and BT5. Other sub- 
 pictures will be spatially concatenated to this one. The host 
 subpicture will constantly flash on and off as will the next identified 
 subpicture. BT5 will merge the newly identified subpicture with the 
 host, creating a new host subpicture. The subpicture initiator for 
 the second identified subpicture will be deleted. Another identified 
 subpicture may now be concatenated. IONLY exits from this mode. All 
 instances of the host subpicture will be modified, but any other 
 instances of the merged subpictures will not be changed. 
 
 Mode 6: Translation 
 
 BT1 and BT2 and one other switch enter this mode . If this 
 other switch is BT3, the entire picture is moved by the cursor, or a 
 subpicture with BTU or a copy of a subpicture with BT5. The incident 
 control must be enabled by C. The first point detected will serve 
 as the reference and will follow the cursor. 
 
 Mode 7» Storing Pictures 
 
 BT1, BT2, BT3, and BTU enter this mode. Only PICTNO is 
 displayable and modifiable, and hence, it. must be savable and 
 retrievable. BTj generates a copy of PICTNO pointed to by PICTN j . 
 The previous PICTNj is deleted and only new subpicture initiators are 
 created for the copy. The mode automatically returns to zero after 
 PICTNO has been copied. IONLY aborts this mode with no copy saved. 
 
25 
 
 Mode 6: Retrieving Pictures 
 
 All switches set enter this mode. BTj concatenates PICTNJ 
 to PICTNO. If PICTNO is null, then only PICTNj will be displayed. 
 The previous PICTNj is not destroyed. 
 
 k.h Software Implementation 
 
 The software is organized into two levels to facilitate the 
 programming and expansion of the system. The lower level is highly 
 dependent upon the data structure, display control features, and other 
 I/O conditions. Routines in this section perform storage allocation, 
 line generation, list manipulation, and interrupt handling for the 
 display and interval clock. These procedures and the display data 
 structure occupy the bottom 1+K of memory. The second level (or high 
 level) is the application software for the display. The logical 
 operation of these routines is clearer and more concise since lower 
 level procedures are invoked which handle device and data structure 
 subtleties. All program coding is in assembly language. 
 
 Two storage allocation routines are incorporated in the 
 lower level control — one for fixed length nodes and one for variable 
 length elements . The two and six word nodes are allocated sequentially 
 from opposite ends of a continuous block of storage. A singly linked 
 list is maintained for each size of free nodes. When this list is 
 empty, another node is taken from the storage not yet claimed. Over- 
 flow results when the list of free nodes is empty and all storage has 
 been claimed. Element memory allocation uses a singly linked list of 
 free storage with each continuous block containing its size and a 
 pointer to the next one. A specific core requirement is made and the 
 first block of sufficient size is utilized. 
 
26 
 
 Software for handling the l6 ms . interval timer is 
 incorporated into the lower level. A maximum of six variable 
 lengthed intervals can be controlled by this routine. Every half 
 second an error recovery routine checks for pathological conditions 
 in the system. If PICTNO is not null and has not been displayed in 
 the interval, the recovery procedure forcibly starts the interface. 
 This feature proves very valuable in a system where initially 
 neither the software nor hardware is fully error free. 
 
27 
 
 5. CONCLUSIONS 
 
 In present 2-D graphical systems, the display is a functional 
 tool which serves as a communications link between the computer and 
 user. The 3-D graphical system potentially offers more to the user. . 
 The display is not as much a tool used in order to communicate with 
 the computer, but in effect, it becomes the actual object of communi- 
 cation. The user is more fully able to communicate directly with the 
 displayed figure — the computer now becomes the functional tool, acting 
 only as the "brain" for the display. I will suggest a modification to 
 a proposed change to Stereomatrix that would improve the quality of the 
 displayed images and methods to attain the level of user/display 
 rapport alluded to above . 
 
 A proposed modification to the display for automatic 
 generation of lines would greatly increase the amount of flicker-free 
 material that can be displayed. Due to acoustical delays in the laser 
 deflecting components, approximately seven microseconds is required 
 between point intensifications. The distance between two successive 
 points is not important. If the delay between intensifications is 
 decreased, a smear results as portions of the right move to the new 
 position. By decreasing the delay for continuous lines, the rate of 
 plotting will increase and the resulting smear will enhance the quality 
 of picture. The interface will require redesigning to accommodate a 
 display controlled line mode; however, the plotting rate of curved lines 
 will not increase. By utilizing one of the free bits in the display 
 status register to select a display rate, the program could plot any 
 continuous line at the higher rate. The interface would not be changed 
 and only minor modification would be required to the display. 
 
28 
 
 For a computer-driven display to react dramatically in a 
 real-time environment, it requires the assistance of additional logic. 
 Automatic rotation of graphic images is one of the most desired 
 functions for a display system. More computing power is required for 
 performing these calculations in real-time than is availahle from a 
 minicomputer. The Stereomatrix does have rotational type powers, but 
 the computer neither knows nor controls what functions are performed. 
 It can only send a string of co-ordinates to be intensified and the 
 coefficient generator modifies this input. 
 
 Control of the coefficient generator which initiates 
 rotation, etc., can be given to the computer by permitting it to 
 store and forward inputs from the display control box. The computer 
 can then keep track of the total manipulations performed. The 
 coefficient generator fixes angular frequency for rotation and other 
 variables at a "suitable" constant. Under computer control, the 
 rate of rotation and translation may be varied. In addition, these 
 features may be invoked automatically by the computer in response to 
 other inputs to the system. Since the controlling signals are dc levels 
 very little additional interface control logic would be required to 
 implement this feature. 
 
 The display hardware can, at present, rotate a picture only 
 about one of the major axes. With the power available, the computer 
 can affect rotation about any axis. An initial sequence of translations 
 and rotations move the picture so that the desired axis of rotation is 
 on one of the major axes. Then, the desired rotation is performed. 
 The picture is then returned to its initial position by reversing the 
 order and direction of the initial operations. If none of the 
 
29 
 
 intermediate results are displayed, then the picture will appear to 
 rotate around the desired axis. 
 
 The 3-D environment of the Stereomatrix display lends itself 
 to more sophisticated dialogues than does the 2-D system. If the 
 display is envisaged as a "window" through which the displayed figure 
 and the user communicate with one another, then both should "see" the 
 other in their respective three-dimensional space. The Stereomatrix 
 display is one-sided in this respect. While the observer has complete 
 freedom of movement to look through the window, the displayed figure 
 has no idea where or what the observer is doing. Consequently, it 
 cannot respond dynamically to his actions. Vision requires the use 
 of a camera, sophisticated software and a large controlling computer. 
 However, if the computer is able to determine the observer's position, 
 then the displayed figure "sees" shadows or fuzzy shapes. Allowing 
 the computer access to the position sensors makes this possible, and in 
 addition, it can calculate direction and rate of movement of the user. 
 
 As an example, consider the situation where one displayed 
 figure A always positions itself between the user and a displayed 
 object. As the observer moves, the computer rotates and translates the 
 entire picture, maintaining displayed figure A, the object and the user 
 directly in line with one another. The observer will sense that 
 displayed figure A can "see" him as it reacts to his movements. Delayed 
 computer responses will give the displayed figures more "human-like" 
 movements . 
 
 There are applications where it is desirable to rotate only 
 portions of a picture. The coefficient generator is not designed to 
 operate separately on several sections of a picture concurrently and 
 
30 
 
 could not be easily modified to do so. While translation of subpictures 
 is supported by the graphics software, rotation is not. A modification 
 completely inhibiting perspective-related rotations of specified parts 
 of a picture would present an interesting feature and is illustrated by 
 the following example. 
 
 A displayed human figure, Igor, and the observer are staring 
 directly at each other. The observer moves to his left. Normally, he 
 would see the right side of Igor's head and body. By modifying the 
 outputs from the position sensor, only Igor's head will turn to follow 
 the movements of the observer. Now, the observer sees the right side 
 of Igor's body, but Igor's head is still staring "head on" at the 
 observer. In other words, Igor's head would appear to rotate on his 
 shoulders. A similar effect has been observed in certain oil portraits 
 done in such a perspective that the subject's eyes appear to stare at 
 the observer from any position of observation. The usual sensor 
 outputs are utilized while displaying the body and with the head, the 
 position sensor values are modified to position the user on the center 
 axis coming from the display and at the same distance from the display 
 as the body (see Figure 7). If Igor is not displayed at the center 
 of the screen, more complex changes must be made to the modified position 
 sensor outputs . 
 
 The Stereomatrix display represents a new direction in computer 
 display systems. It gives the user both three-dimensional vision and 
 personal freedom of movement. Although Stereomatrix has 3-D projectional 
 powers, it has 2-D interactive controls. Its potential as a true user/ 
 display communications system presents a unique challenge for further 
 
31 
 
 development. The suggested modifications will increase its interactive 
 capabilities and help produce a truly dynamic system, thus, lending 
 itself to an improved quality of user/display rapport. 
 
 Observer's 
 Position 
 
 Assumed Observer's Position 
 for Drawing Head 
 
 Screen 
 
 Position 
 Sensors 
 
 Figure 7. Position for Modified Sensor Outputs 
 
32 
 
 LIST OF REFERENCES 
 
 [l] Kubitz, W. J. and Poppelbaum, W. J. "The Stereomatrix Display," 
 
 presented at the Society for Information Display International 
 Symposium and Exhibition in Philadelphia, May U-6, 1971. 
 
 [2] Partridge, R. L. "PAGAN, A Three Dimensional Pattern Generator," 
 Department of Computer Science Report No. k6k t University of 
 Illinois, Urbana, Illinois 6l801, August 1971. 
 
 [3] SMALL COMPUTER HANDBOOK, Digital Equipment Corporation, Maynard, 
 Massachusetts, 1967-1968. 
 
33 
 
 APPENDIX A 
 
DISPLAY INSTRUCTIONS 
 
 34 
 
 CLRFLG 
 
 DRAW 
 
 DSPRGO 
 
 LDX 
 
 LDY 
 
 LDZ 
 
 RDCMA 
 
 RDFLG 
 
 RDX 
 
 RDY 
 
 RDZ 
 
 REDBX 
 
 RESUM 
 
 SKBF 
 
 SKDF 
 
 STPDSP 
 
 655U 
 65kk 
 65U6 
 6511 
 6521 
 6531 
 6562 
 6552 
 6516 
 6526 
 6536 
 6561 
 6564 
 6551 
 65U1 
 65U2 
 
 CLeaR FLaGs 
 
 DRAW 
 
 DtSPlay Reset and Go 
 
 LoaD X 
 
 LoaD Y 
 
 LoaD Z 
 
 ReaD Complement of Memory Ad 
 
 ReaD FLaGs 
 
 ReaD X cursor co-ordinate 
 
 ReaD Y cursor co-ordinate 
 
 ReaD Z cursor co-ordinate 
 
 REaD BoX 
 
 RESUMe 
 
 SKip on Buffered Flags 
 
 SKip on Display File done 
 
 SToP DiSPlay 
 
35 
 
 APPENDIX B 
 
36 
 
 The PDP-8/I generates IOP pulses for controlling I/O 
 devices. The six device numbers used by the interface are also 
 referenced by letters as follows: X - 51, Y - 52, Z - 53, A - 5k, 
 B - 55, C - 56. The machine instruction DSPRGO (65U6) generates 
 pulse I0PA2 followed by IOPAU. 
 
 The following comments refer to particular cards . 
 A/D Data Buffer 
 
 The two flip-flops controlling the one -shot prevent gating 
 of new A/D outputs into the buffer during the RDX, RDY, and RDZ instructions. 
 
 Sequencer 
 
 The Sequencer has seven states called SEQO through SEQ6. 
 The transition between states is controlled by a U-input HAND gate 
 whose output clears the flip-flop of the previous state and sets the 
 one of the next simultaneously. For a state transition to occur, the 
 RUN flip-flop and the required Boolean condition must be "l". In 
 addition, to maintain correct sequential operation, the flip-flop of 
 the state being left must be set and the signal that sets it must 
 have returned to its normally high level. The Sequencer rate is 
 determined by the controlling Boolean condition up to the maximum 
 rate determined by circuit delays. 
 
 A/D Converter 
 
 The STROBE input (positive pulse) initiates a conversion. 
 The BUSY output rises with STROBE and drops when the conversion is 
 completed. Maximum conversion time is 50 microseconds with an input 
 range of +5 volts. Calibration is as follows: 
 
37 
 
 1. With cables to Stereoraatrix removed, connect a pulse 
 generator to the STROBE pin. The generator should 
 produce a 3V pulse of 1 microsecond duration and a 
 period of approximately 100 microseconds. 
 
 2. Load the following program to observe A/D output in 
 AC register on PDP-8/I console. 
 
 CLA 
 
 TAD (-UOO 
 
 DCA TIMER 
 
 RDX / or M or RDZ 
 
 ISZ TIMER 
 
 JMP .-1 
 
 JMP .-6 
 
 3. Ground MA INPUT and adjust the OFFSET pot (200kn) 
 until the output code reads 0111111111XX. Then, apply 
 -5.00V to the input and adjust the 2kft pot for 0000000001XX. 
 
38 
 
 CABLE la 
 IE-1 
 
 CABLE lb 
 IE-2 
 
 CABLE 2 
 IF-1 
 
 DA00 
 0AO1 
 0A02 
 DA03 
 DA04 
 DA05 
 DA06 
 DA07 
 DA08 
 
 DA09 
 0A10 
 DA11 
 BRK REQ 
 DATA OUT 
 B- MPX 
 ADR ACC 
 
 CYCLE SEL. 
 
 DAEX-1 
 DAEX - 2 
 DAEX -3 
 
 DMA CABLES 
 
 D 
 
 1 
 
 2 
 
 3 
 
 4 
 
 5 
 
 6 
 
 7 
 
 8 
 
 9 
 
 10 
 
 11 
 
 »? 
 
 13 
 
 14 
 
 1? 
 
 tf 
 
 DMA 
 
 L 
 E 
 
 L 
 E 
 
 L 
 E 
 
 L 
 E 
 
 a/d 
 
 DMA 
 
 
 
 
 
 
 
 
 
 
 C 
 
 V 
 
 V 
 
 V 
 
 V 
 
 D 
 
 C 
 
 D 
 
 S 
 
 X 
 
 Y 
 
 Z 
 
 L 
 
 L 
 
 L 
 
 L 
 
 A 
 
 E 
 
 E 
 
 E 
 
 E 
 
 A 
 
 
 
 1 
 
 E 
 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 B 
 
 L 
 
 L 
 
 L 
 
 L 
 
 T 
 
 N 
 
 R 
 
 
 
 R 
 
 R 
 
 R 
 
 N 
 
 N 
 
 N 
 
 N 
 
 L 
 
 
 
 
 
 A 
 
 T 
 
 E 
 
 u 
 
 E 
 
 E 
 
 E 
 
 E 
 
 E 
 
 E 
 
 E 
 
 E 
 
 S 
 
 S 
 
 S 
 
 S 
 
 
 R 
 
 C 
 
 E 
 
 G 
 
 G 
 
 G 
 
 
 
 
 
 
 H 
 
 H 
 
 H 
 
 H 
 
 B 
 
 
 
 T 
 
 N 
 
 1 
 
 1 
 
 1 
 
 D 
 
 D 
 
 D 
 
 D 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 U 
 
 L 
 
 1 
 
 c 
 
 S 
 
 S 
 
 S 
 
 R 
 
 R 
 
 R 
 
 R 
 
 
 F 
 
 F 
 
 F 
 
 F 
 
 F 
 
 
 
 
 E 
 
 T 
 
 T 
 
 T 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 T 
 
 T 
 
 T 
 
 T 
 
 F 
 
 
 N 
 
 R 
 
 E 
 
 E 
 
 E 
 
 V 
 
 V 
 
 V 
 
 V 
 
 
 E 
 R 
 
 E 
 R 
 
 E 
 R 
 
 E 
 R 
 
 E 
 R 
 
 N 
 
 T 
 E 
 
 D 
 
 E 
 
 R 
 
 R 
 
 R 
 
 E 
 R 
 
 *0 
 
 E 
 R 
 
 *1 
 
 *2 
 
 1 
 #3 
 
 DMA 
 
 V 
 
 Vo 
 
 Vo 
 
 \ I 
 
 
 
 
 
 \ / 
 
 
 R 
 R 
 U 
 
 P 
 T 
 
 C 
 
 D 
 
 E 
 R 
 
 
 
 
 
 AC in 
 
 AC in 
 
 AC in 
 
 L 
 
 C 
 A 
 B 
 
 B 
 U 
 S 
 
 B 
 U 
 S 
 
 B 
 
 Y 
 
 
 
 
 
 
 Bits 
 
 
 Bits 
 
 4 
 
 Bits 
 8 
 
 1 
 
 N 
 E 
 
 R 
 E 
 
 c 
 
 L 
 
 E 
 
 1 
 
 2 
 
 3 
 
 A 
 
 
 F 
 
 
 
 
 
 
 1 
 2 
 
 5 
 6 
 
 9 
 10 
 
 2 
 
 
 
 
 A 
 
 
 L 
 A 
 G 
 S 
 
 
 
 
 
 
 3 
 
 7 
 
 11 
 
 1 
 E 
 
 E* 
 
 CARD LAYOUT 
 
39 
 
 
 
 
 I/O BUS 1 
 
 
 
 
 I0PX1 
 
 - 
 
 F2D1 
 
 
 IOPB1 
 
 - 
 
 F2D2 
 
 I0PX2 
 
 - 
 
 F2E1 
 
 
 I0PB2 
 
 - 
 
 F2E2 
 
 IOPXU 
 
 - 
 
 F2F1 
 
 
 IOPBU 
 
 - 
 
 F2F2 
 
 GMD 
 
 - 
 
 F2H1 
 
 
 GMD 
 
 - 
 
 F2H2 
 
 IOPY1 
 
 - 
 
 F2J1 
 
 
 I OP CI 
 
 - 
 
 F2J2 
 
 I0PY2 
 
 - 
 
 F2K1 
 
 
 I0PC2 
 
 - 
 
 F2K2 
 
 IOPYU 
 
 - 
 
 F2L1 
 
 
 IOPCU 
 
 - 
 
 F2L2 
 
 GRND 
 
 - 
 
 F2M1 
 
 
 GMD 
 
 - 
 
 F2M2 
 
 IOPZ1 
 
 - 
 
 F2N1 
 
 
 BTS3 
 
 - 
 
 F2N2 
 
 IOPZU 
 
 — 
 
 F2P1 
 F2R1 
 
 
 GMD 
 
 — 
 
 F2P2 
 
 IOPZU 
 
 SKIP 
 
 F2R2 
 
 GMD 
 
 - 
 
 F2S1 
 F2T1 
 F2U1 
 
 
 GMD 
 
 ~ 
 
 F2S2 
 
 IOPA1 
 
 CLRAC 
 
 F2T2 
 
 I0PA2 
 
 INTERRUPT - F2U2 
 
 IOPAU 
 
 _ 
 
 F2V1 
 
 
 INIT 
 
 
 
 F2V2 
 
I/O BUS 2 
 
 ko 
 
 BMB(O) 
 
 - F3D1 
 
 BMB(l) 
 
 - F3E1 
 
 BMB(2) 
 
 - F3F1 
 
 GRND 
 
 - F3H1 
 
 BMBC3) 
 
 - F3J1 
 
 BMB(U) 
 
 - F3K1 
 
 BMB(5) 
 
 - F3L1 
 
 GRND 
 
 - F3M1 
 
 BMB(6) 
 
 - F3N1 
 
 BMB(T) 
 
 - F3P1 
 
 BMB(8) 
 
 - F3R1 
 
 GRND 
 
 - F3S1 
 
 BMB(9) 
 
 - F3T1 
 
 BMB(IO) 
 
 - F3U1 
 
 BMB(ll) 
 
 - F3V1 
 
 BAC(O) 
 
 - F3D2 
 
 BAC(l) 
 
 - F3E2 
 
 BAC(2) 
 
 - F3F2 
 
 GRND 
 
 - F3H2 
 
 BAC(3) 
 
 - F3J2 
 
 BAC(U) 
 
 - F3K2 
 
 BAC(5) 
 
 - F3L2 
 
 GRND 
 
 - F3M2 
 
 BAC(6) 
 
 - F3N2 
 
 BAC(T) 
 
 - F3P2 
 
 BAC(8) 
 
 - F3R2 
 
 GRND 
 
 - F3S2 
 
 BAC(9) 
 
 - F3T2 
 
 BAC(IO) 
 
 - F3U2 
 
 BAC(ll) 
 
 - F3V2 
 
1*1 
 
 I/O BUS 3 
 
 ACIN(O) - Fl*Dl 
 
 ACIN(l) - FUEl 
 
 ACIN(2) - Fl*Fl 
 
 GRND - Fl*Hl 
 
 ACTN(3) - FUJI 
 
 ACINO) - Fl+Kl 
 
 ACINC5) - FULl 
 
 GRND - FUML 
 
 ACIN(6) - Finn. 
 
 ACIN(7) - FUP1 
 
 ACIN(8) - Fl*Rl 
 
 GRND - FUSl 
 
 ACIN(.9) - FUTl 
 
 acinCio) - FUUl 
 
 ACIN(ll) - FUVl 
 
k2 
 
 UMUM1MD 
 
 »/0 K CURIO* 
 
 OUTPUT 
 
 IlIBlt) ilT(t) 
 
 111911) IITdl 
 
 (11014) IIT(T) 
 
 OtBll) IIT(I) 
 
 (ItDlt) IITIS) 
 
 (1IBI7I BIT(4) 
 
 (ItBlt) IIT(S) 
 
 (ItDlt) UTIII 
 
 (ItOtO) ■ITII) 
 
 (U0J1) IIT(O) 
 
 umumttD 
 4/0 r cutto* 
 
 OUTPUT 
 (100 It) IIT(t) 
 
 (11011) IIT(t) 
 (11014) ilT(T) 
 (1101*1 ilT(t) 
 (11011) IIT(I) 
 
 (itoin iiT(4) 
 
 (IBOtl) IITISI 
 (IS Bit) IIT(t) 
 (IBBtO) tlT(l) 
 (180(1) IIT(0) 
 
 UNtUfUPCB 
 
 */o z euttot 
 
 OUTPUT 
 (MBit) t)T(t) 
 
 I1ID1I) 
 (M014I 
 
 dtoia) 
 
 (It Bit) 
 (ItfilT) 
 (ItBlt) 
 (llOlt) 
 lltBW) 
 (UDtl) 
 
 t)T(t) 
 tlT(T) 
 tlT(t) 
 tlT(S) 
 IITI4) 
 IITIS) 
 IITItl 
 IIT(l) 
 tlT(O) 
 
 (Ci»«i,rt'i) 10PM 
 (Pl»ft,»tL))10PT4 
 
 (PlSP),Pt*l)10PZ4 
 
 (PtTt) 5C*H 
 ItlBtl) 410 OONt 
 
 EHl 
 
 »ii 
 
 «IL 
 
 ;» 
 
 fa. 
 
 M 
 
 t tr~~Ttj jiT~T* »P™ll 
 
 CT 
 
 sj itT~~Tt 
 
 rM F £l I' *»« 
 
 i m| u c« 
 
 t t 
 
 > 
 
 t t 
 
 0* 
 
 ■J litj - "" Tol aj 
 
 0B« [7 C4 
 
 I It 
 
 II 
 
 t 1 
 
 3 
 
 i) a, 
 
 \si Ai 
 
 s 
 
 02 
 
 11 ,1*. 
 ii 
 
 OS 
 
 *J A- 
 
 C2 
 
 •I jlS 
 
 21 A- 
 
 SJ >£. 
 
 21 .2. 
 
 
 Nt 
 
 » cutto* coopbi 
 
 tITItl (PStPl) 
 
 liT(t) Citai) 
 
 tlT(T)(P14MI) 
 *IT(I)(»1«N1) 
 t)T(t)(P14H) 
 IIT(4)(P14IH) 
 IITIS) (PI SMI) 
 ■IT(4)(P|INI> 
 IITIlllttSPl) 
 
 HTIOKPIWl) 
 
 y cumm* coons 
 
 tlT(t) (PISPt) 
 
 »)T(ti irimi 
 
 tlT(T)(P14Ht) 
 tlT(t)(P14Mai 
 IIT(t)(P14Pl) 
 
 IIT(4I(P14PI) 
 IITIS) (PIMt) 
 tlT(t) (PlINt) 
 UTIIMPlSPt) 
 
 tlT(O) (Pit PS) 
 
 z cupsop coomi 
 
 WT (») (P1SU1) 
 BIT (t) (F1SV1) 
 IIT (T) (P14SI) 
 IIT(t)(F14Tl) 
 IITIS) (P14U1) 
 •IT(4)(P14VD 
 WT IS) IPlStl) 
 SIT(Z)IFISTI) 
 •IT(limiUl) 
 
 IIT (0) IPISVI) 
 
 A/D pATA BUFFER 
 
 7474 
 
 7474 
 
 
 
 T474 
 
 7474 
 
 
 
 7474 
 
 7474 
 
 
 
 7474 
 
 7474 
 
 
 
 c e A 
 
 7474 
 
 7474 
 
 
 
 7474 
 
 7474 
 
 74111 
 
 
 7474 
 
 7474 
 
 7410 
 
 
 7474 
 
 74107 
 
 7404 
 
 
U3 
 
 I'SVII •1CIIII 
 I'Jof l itCIIOI 
 
 • •>'.-■ LO' •'■ < 
 
 l»>M.tlOJII MCI'I 
 ■"..' t V. t*CI«l 
 IF3LI.E10L1I MCI91 
 
 IFMI.CI0M1I (MCI* 
 
 irjja.eioNii mciji 
 irjrj.EiOPII B»CI2) 
 
 irJtJ.tWKl! «».-.:' 
 
 i"02,eiosii eacioi 
 
 (rjPJ! 10PB4 
 ICIKtl NOD1T1 
 
 (EtE2,»2VI> 10PM 
 IE902.EIEU 8-mpx 
 
 (E»02l Biifi 
 
 ICIH2.F2V2I INIT 
 (CSF2) ID* ICC 
 
 .... ' — •'> 
 
 •-iz^. 
 
 r«m 
 
 7474 
 
 7474 
 
 
 74 III 
 
 7404 
 
 7474 
 
 74 10 
 
 T4T4 
 
 7404 
 
 7400 
 
 
 74T4 
 
 7410 
 
 7404 
 
 
 D C B A 
 
 T4T4 
 
 7400 
 
 
 
 74UJ 
 
 7410 
 
 
 
 T41t3 
 
 7404 
 
 7474 
 
 
 74»M 
 
 7404 
 
 7474 
 
 
 trivutaaii.) 
 1'iuniwsno) 
 
 (»JTl)3Miltl 
 IF}*.) §(*(•) 
 
 l.'J'lilMlin 
 (F3».U IMI(I1 
 
 (EtM2) LOtTAT 
 
 <E9L2) L FLAG I 
 
 IE9K2.F2U1) 10PA2 
 (F2T1) I0PA1 
 
 (FHHi) CUMCOM 
 
 (FMK1) CRSIOT 
 
 (FltLl) FCN«Q 
 
 (F2D2I lOFil 
 
 NTfNUTV (0) 
 IE13HI) 
 
 DMA Control - Interrupt Flogs 
 
kk 
 
 (FSL1) BMB(S) 
 
 (F5K1) 8MB (4) 
 
 (FSJ1) BMBI3) 
 
 (F3F1) BMB(2) 
 
 (FSE1) BMB(l) 
 
 (F3D1) BMB(C) 
 
 (F7B2) BUFFL 
 
 (E9K1) I 
 
 £U_ 
 
 EN1 
 
 EP1 
 
 ESI 
 
 3V 
 
 Dl 
 
 CI 
 
 CI 
 
 Bl 
 
 10 
 
 Bl 
 
 7420 
 
 7420 
 
 7420 
 
 7410 
 
 7404| 1 
 
 2 
 3 
 4 
 
 7420 
 
 7420 
 
 7430 
 
 7420 
 
 7430 
 
 7420 
 
 5£*y— m>- 
 
 
 . s 
 
 C - 
 - D 
 
 fc>L 
 
 MEy-i. 
 
 
 gE^ry-^- 
 
 r B2jB^ 
 
 i©^ 
 
 DIRECTION DECODER 
 
 EN2 
 
 ER2 
 
 ET2 
 
 EV2 
 
 XP1.US (F1001I 
 
 10M2 (F2E1) 
 10PY2 (F2K1) 
 10PZ2 (F2P1) 
 
 CLRAC (F2T2) 
 XNEO (F10E1) 
 
 ZPLUS (F12D1) 
 
 ZNEG (F12E1) 
 
 YPLUS (F11D1) 
 
 YNEG (FUE1) 
 
 HALT (E9H1) s-\ 
 f E8 
 
 STATUS (E9Fl{ rt ] 
 
U5 
 
 ■ MP« '•!." it K1I-' 
 
 (E«V2> STATUS 
 IEBT2I H«LT 
 
 [F7K2I SC* 
 (FTJ2) SCI 
 
 BZsTC"*^ 
 
 TMEoT oT^l 
 
 i»> 
 
 X 
 
 ST5* 
 
 T02ERO. ' 
 
 S ^ ^ Ba rsy. 1 --"- 
 
 LFREE 1 ' TOZEK* »8 f" ' ! 
 
 CTCLEF- 
 RUN- 
 
 SEQ6- 
 
 ^ y 
 
 fcO^B 
 
 '^y ^^^ 
 
 ' B4 I 3 84 
 
 ' i , Jvl 
 
 ' Sri V 
 
 5*57(F7V2.E10T1I 
 I0F44IE7VI.EIMI1I 
 
 I0PC4 (F212I 
 
 IMIT (£781) 
 
 INCIOENT <F7F>2.FIJ«I) 
 
 IOFM :F7Nl) 
 
 LFL4GI (F7M1) 
 
 LDSTAT IFTU) 
 
 L04TCO IEISLII 
 
 L«EO (F16F1I 
 
 DIRECTION (E4J2I 
 
 CYCLE -SEL (E4L2I 
 
 NO04TI (ETUI) 
 
 COUNT (F10B1) 
 
 f^Kfi^ 
 
 sTW 
 
 
 7404 
 
 74 74 
 
 
 
 7400 
 
 7404 
 
 
 7400 
 
 7420 
 
 74121 
 
 74121 
 
 7400 
 
 74107 
 
 74107 
 
 
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 7404 
 
 7420 
 
 T420 
 
 7474 
 
 7400 
 
 7410 
 
 7420 
 
 7474 
 
 7404 
 
 7410 
 
 74 20 
 
 7474 
 
 
 7420 
 
 7420 
 
 7474 
 
 SEQUENCER 
 
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 EM0.EFU,fF|2 
 
 XNCO.VNEG.ZNEG 
 
 (ttf» ,Et»2,E«Lj) 
 
 <E»T2> COUNT 
 
 iopxi,io»vi,iofzi 
 
 XPLUS.VPLUS.ZPLUS 
 
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 X,Y,2 CO-ORDINATE REGISTER 
 
 
 
 
 
 7404 
 
 74121 
 
 
 
 7400 
 
 7410 
 
 
 
 7410 
 
 7400 
 
 
 
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 7400 
 
 74S0 
 
 74107 
 
 
 7410 
 
 7410 
 
 7404 
 
 
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 7404 
 
 74SO 
 
 74O0 
 
 74113 
 
 7404 
 
 74JO 
 
 
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 INTENSITYU) 
 X,Y,Z.DGT9 
 
 INTENSITY(O) 
 X.Y.Z.DGT8 
 
 FREE(l) 
 X,Y,Z,0GT7 
 
 FREE (0) 
 X,Y,Z.DGT6 
 
 LDATGO 
 X.Y.Z.DGT5 
 
 FRAME 
 X,Y,Z,DGT4 
 
 FCNCLR 
 X.Y.Z.DGT3 
 
 X.Y.Z.DGT2 
 
 X.Y.Z.DGTl 
 
 X,Y,Z,DGTO 
 
 EF1 
 
 EHl 
 
 EJ1 
 
 EK1 
 
 ELI 
 
 EMI 
 
 EN1 
 
 EP1 
 
 ER1 
 
 ESI 
 
 EB2 
 
 3V 
 
 3V 
 
 3V 
 
 •-5V 
 
 iD 
 
 3V H»° 
 
 5 
 
 iQ 
 
 3V -fio 
 
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 12 
 
 13 
 
 12 
 
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 9 
 
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 06 
 
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 13 
 
 12 
 
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 13 
 
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 12 
 
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 E13 
 
 E14,E15,E16 
 
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 75109 
 
 75109 
 
 
 
 75109 
 
 
 
 
 75109 
 
 
 
 
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 11 
 
 12 
 
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 11 
 
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 3V 
 
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 75107 
 
 75107 
 
 
 
 75107 
 
 
 
 
 75107 
 
 
 
 
 75107 
 
 
 
 
 Line Receivers 
 
 -3V 
 
 FB2 
 
 FF1 LKO (MP2) 
 
 FH1 CURCOR (F7R1) 
 
 FJ1 STROBE ClBD-9) 
 
 FK1 CRSIOT (F7S1) 
 
 FL1 FCNREO (F7T1) 
 
 FM1 BB0X(5)(14FH1)FCNT(9) 
 
 FN1 BB0X(4)(15FLl)FCNT(e) 
 
 FP1 BB0X(3> (15FK1) FCNT(B) 
 
 FR1 BB0X(2) (15FJ1) FCNT(IO) 
 
 FS1 BBOXU) (15FH1) FCNTU1) 
 
l4 9 
 
 CU«»0» Z(3,r),0*N 
 
 ■).». (J.T.UI 
 
 CINISO* »(3,7>,0«N 
 
 cu»«o« r |3,ti,c*n 
 
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 74 S3 
 
 7460 
 
 
 
 7433 
 
 
 
 
 7433 
 
 74S0 
 
 
 
 7433 
 
 
 
 
 •CIN ilTt (3,7,111 
 
 »CIN BITS (2,t,10) 
 
 *CIH UTS (1,5,91 
 
 4CIN IITJ (0,4,1) 
 
50 
 
 STEREOMATRIX 
 
 COAXIAL CABLE 
 
 INTERFACE 
 
 Dl! 
 
 X CURSOR 
 Y CURSOR 
 Z CURSOR 
 
 3PL 
 
 AY 
 
 (ANALOG) 
 ±5V 
 
 021 
 5 
 
 
 
 
 ±5V 
 
 10 
 
 
 
 
 ±5V 
 
 15 
 
 
 
 
 
 
 
 
 
 (D12-10) X BUSY 
 (015-10) Y BUSY 
 (D18-10) Z BUSY 
 
 CONNECTOR 
 
 012 X CO-ORDINATE 
 
 Y CO-ORDINATE 
 
 Z CO-ORDINATE 
 
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 © 
 
 13 
 
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 12 
 
 D25 
 
 21 
 
 D12-3 
 D15-3 
 D18-3 
 
 
 6 
 
 
 
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 15V 
 
 
 
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 7 
 
 
 
 -15 V 
 
 2- 9 
 
 
 2 
 
 
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 5 
 
 
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 4 
 
 
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 2-4 
 
 
 3 
 
 
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 2- 3 
 
 
 9 
 
 
 
 
 2- 2 
 
 
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 2- 1 
 
 
 
 
 
 
 
 
 
 
 +15V- 
 
 1 Offset 
 — -\AA, 15V 
 
 20 Kn 
 
 10 
 12 
 13 
 14 
 15 
 16 
 17 
 18 
 19 
 20 
 21 
 
 A/D DONE 
 (F6 B2) 
 
 CURSOR CONTROLS 
 
51 
 
 BOX 1 
 
 BOX 2 
 
 R-1.6K 
 
 
 
 
 7404 
 
 
 
 
 7474 
 
 
 
 
 7474 
 
 
 
 7430 
 
 7474 
 
 
 
 7400 
 
 74121 
 
 
 
 
 
 B B0X1 
 
 B BOX 2 
 
 B BOX 3 
 
 B BOX 4 
 
 B BOX 5 
 
 FCNREQ 
 
 Transformer 
 Rack 4 
 Cord 6 
 
 BUTTON CONTROL AND REGISTERS 
 
, C-427 
 
 la) 
 
 C3201 
 
 U.S. ATOMIC ENERGY COMMISSION 
 
 UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR 
 
 DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT 
 
 ( Ss* Instruction* on R* 
 
 Sldm) 
 
 ,l REPORT NO. 
 
 C0O-1U69-O202 
 
 2. TITLE 
 
 HARDWARB/SQFWARE INTERFACE FOR 
 THE STBREOMATRIX DISPLAY 
 
 >E OF DOCUMENT (Check on*): 
 
 ] ■. Scientific and technical report 
 
 ] b. Conference paper not to be published in a journal: 
 
 Title of conference 
 
 Date of conference 
 
 Exact location of conference. 
 
 Sponsoring organization 
 
 ] c. Other (Specify) Thpgi s 
 
 COMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): 
 
 .] a. AEC's normal announcement and distribution procedures may be followed. 
 
 ] b. Make available only within AEC and to AEC contractors and other VS. Government agencies and their contractors. 
 
 ] c. Make no announcement or distribution. 
 
 USON FOR RECOMMENDED RESTRICTIONS: 
 
 EMITTED BY: NAME AND POSITION (Please print or type) 
 
 C. William Gear, Professor 
 and Principal Investigator 
 
 snization 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 nature 
 
 ^K&kfe^- 
 
 Date 
 
 April 13, 1972 
 
 FOR AEC USE ONLY 
 
 t CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION 
 COMMENDATION: 
 
 ENT CLEARANCE: 
 
 J a. AEC patent clearance has been granted by responsible AEC patent group. 
 ] b. Report has been sent to responsible AEC patent group for clearance. 
 J c. Patent clearance not required. 
 
BIOGRAPHIC DATA 
 SET 
 
 1. Report No. 
 
 UIUCDCS-R-72-508 
 
 3. Recipient's Accession No. 
 
 5- Report Date 
 
 June 1972 
 
 Itle *nd Subtitle 
 
 HARDWARE /SOFTWARE INTERFACE FOR 
 THE STEREOMATRIX DISPLAY 
 
 ,uthor(s) 
 
 Ian MacDonald Cunningham 
 
 8- Performing Organization Rept. 
 No. 
 
 'erforming Organization Name and Address 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 10. Project/Task/Work Unit No. 
 
 US AEC AT(ll-l)lU69 
 
 11. Contract /Grant No. 
 
 US AEC AT(ll-l)lU69 
 
 Sponsoring Organization Name and Address 
 
 US AEC Chicago Operations Office 
 9800 South Cass Avenue 
 Argonne, Illinois 60U39 
 
 13. Type of Report 8t Period 
 Covered 
 
 Thesis research 
 
 14. 
 
 Supplementary Notes 
 
 Abstracts 
 
 A random-access, three-dimensional laser display called Stereomatrix has "been 
 built by a group in the Department of Computer Science at the University of 
 Illinois. Three-dimensional wire figures are displayed by generating separate 
 images for the left and right eyes . The light from the iaster is split into 
 two beams, and then the polarization of the left beam is rotated 90 degrees. 
 Both beams are deflected along the x and y axis, resulting in a double image. 
 The observer wears glasses with oppositely polarized lenses which give the 
 visual effect of a third dimension. The observer's position is sensed by an 
 infrared light source contained on the glasses. Movements of the observer are 
 detected and automatic redisplaying of the figure as it would appear to the 
 observer from the new position occurs. The observer also may scale, rotate, and 
 translate the picture under complete hardware . control. A three-dimensional 
 cursor is also displayed by the hardware. 
 
 Key Words and Document Analysis. 17o. Descriptors 
 
 random-access 
 three-dimensional 
 laser display 
 stereomatrix 
 polarization 
 
 Identifiers/Open-Ended Terms 
 
 COSATI Field/Group 
 
 Availability Statement 
 
 unlimited distribution 
 
 19.. Security Class (This 
 Report) 
 
 ■ ■ . UNCLASSIFIED 
 
 20. Security Class (This 
 Page 
 
 UNCLASSIFIED 
 
 21. No. of Pages 
 
 2L 
 
 22. Price 
 
 M NT1S-35 (10-70) 
 
 USCOMM-DC 40329-P71 
 
7 m