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DCS Report No. 4ll 
 
 ^X^lM 
 
 DIAGNOSIS OF PRINTED CIRCUIT CARDS 
 ON A PROGRAMMABLE TEST EQUIPMENT 
 
 by 
 Masayuki Inagaki 
 
 July 30, 1970 
 
 ILLIAC IV Document No. 228 
 
Report No. 4 11 
 
 DIAGNOSIS OF PRINTED CIRCUIT CARDS 
 ON A PROGRAMMABLE TEST EQUIPMENT 
 
 by 
 
 Masayuki Inagaki 
 
 July 30, 1970 
 
 Department of Computer Science 
 University of Illinois at Urbana- Champaign 
 Urbana, Illinois 6l801 
 
 This work was supported in part by the Advanced Research Projects 
 Agency as administered by the Rome Air Development Center under Contract 
 No. USAF 30(602)-klkk and submitted in partial fulfillment of the 
 requirements for the degree of Master of Science in Computer Science, 
 June 1970. 
 
ABSTRACT 
 This paper discusses methods of editing test dictionaries 
 using the results of printed circuit card fault simulation, identifying 
 failures in a printed circuit card. To identify a failure in a card under 
 test, a generalized automatic test equipment is introduced and three 
 identification methods are presented and evaluated. A program for generating 
 test dictionaries was written in Extended ALGOL for the Burroughs B5500 
 computer and used for test dictionary generation for the ILLIAC IV PE and 
 CU cards and is also described in this paper. 
 
I V 
 
 TABLE OF CONTENTS 
 
 [ age 
 
 1. INTRODUCTION 1 
 
 2. THEORETICAL DESCRIPTION OF DIAGNOSTIC TEST GENERATION 3 
 
 2.1 Definitions 3 
 
 2.2 Mathematical Description k 
 
 3- THEORETICAL APPROACH FOR TEST DICTIONARY GENERATION 2k 
 
 3-1 Method of Test Dictionary Generation 2k 
 
 3-2 Procedure for Failed Function Identification 27 
 
 3.2.1 Abstract Test Equipment (ATE) for Identifying 
 
 Failed Functions 27 
 
 3-2.1.1 The Function of ATE 27 
 
 3.2.1.2 The Function of Logic Devices 30 
 
 3.2.1.2.1 Input-Output Pattern Table ... 31 
 
 3.2.1.2.2 Test Dictionary Table 31 
 
 3.2.1.2.3 Input Pattern Store Register . . 31 
 3.2.1.2.** Output Pattern Store Register . 31 
 3.2.1.2.5 Expected Response Store Register 31 
 3-2.1.2.6 Comparator 31 
 
 3.2.1.2.7 Auxiliary Memory 32 
 
 3.2.1.2.8 Control Unit 32 
 
 3.2.1.2.9 Arithmetic Unit 32 
 
 3' 2. 2 First Failed Function Identification Method 
 
 Using ATE 32 
 
 3.2.3 Second Failed Function Identification Method 
 
 Using ATE 39 
 
 3«2.U Third Failed Function Identification Method 
 
 Using ATE k2 
 
 3.3 The Comparison Between First, Second and Third Methods . . k'J 
 
V 
 
 Page 
 
 k. TEST DICTIONARY EDITING PROGRAM k-9 
 
 k.l Performance of Test Dictionary Editing Program ^9 
 
 k.2 Brief Description of Test Dictionary Editing Program .... 51 
 
 1+.2.1 Control Program 51 
 
 U.2.2 Pre-processing Program 51 
 
 U.2.3 Test Dictionary Generator Program 57 
 
 h.2.h Error Table Sorting Program 59 
 
 U.2.5 Indistinguishable Failure Selecting Program 59 
 
 5. CONCLUSION 61 
 
 REFERENCES 62 
 
 APPENDIX 63 
 
vi 
 
 LIST OF FIGURES 
 
 Figure Page 
 
 2.1 Example of Network for Error Table in Table 2.2 5 
 
 2.2 Test Generation Procedure 10 
 
 2.3 Example of Network for Following Analysis (A Part of 
 
 PE Control Logic) 12 
 
 2.k An Illustration Model for Test Generation 16 
 
 3-1 The Chart of ATE 33 
 
 3-2 Flow Chart of the First Method kO 
 
 3-3 Flow Chart of the Second Method ^3 
 
 3-k Flow Chart of the Third Method k6 
 
 k.l Test Generator System 50 
 
 k.2 Test Dictionary Editing Program 52 
 
 k.3 <board name>/ETAJBLE File 55 
 
 h.k The Contents of the Completed Error Table Array 56 
 
 4.5 <board name>/EWDS0RT File 58 
 
VI 1 
 
 LIST OF TABLES 
 
 Table Page 
 
 2.1 Table of the Failed Function vs. Failure of the Network 
 
 Shown in Figure 2.1 6 
 
 2.2 Error Table of the Network Shown in Figure 2.1 7 
 
 2.3 Table of the Failed Function vs. Failure of the Network 
 
 Shown in Figure 2.3 13 
 
 2.k Partial Error Table lk 
 
 2.5 Completed Error Table 17 
 
 2.6 
 
 a) Pin Level Error Table of Failed Function f , 21 
 
 b) Pin Level Error Table of Failed Function f oir 21 
 
 3.1 Example of Test Dictionaries 28 
 
 3-2 Example of the Definition 29 
 
1. INTRODUCTION 
 
 The methods to diagnose a logic circuit can be classified into 
 two categories. One is the "combinational testing approach" [1] and 
 another is the "sequential testing approach" [2]. In the combinational 
 testing approach, a fixed set of tests is applied to a logic circuit and 
 the set of outputs of the machine is examined and analyzed to detect or 
 identify a failure. A test dictionary, which is a listing of the test 
 results of the known failures organized to make it easy to look up 
 is utilized in the identification process of the method. In the sequen- 
 tial testing approach, a set of tests to be applied to a machine is not 
 predetermined, but a test to be applied next is determined by the previous 
 test results. Each failure or a group of failures giving an identical 
 diagnostic result is then identified by a certain test sequence and no 
 additional data analysis or dictionary look-up is necessary. 
 
 The combinational testing technique was selected for the 
 ILLIAC IV logic card diagnosis because the preprocessing for test organ- 
 ization is not required. But a well organized list of the test input 
 patterns and the corresponding outputs is necessary for failure isolation 
 purpose. The necessary information can be obtained from logic simula- 
 tion [3]« The description of a logic circuit is compiled into a simu- 
 lator program which can simulate the behavior of the object circuit. A 
 particular failure of the circuit can then be easily simulated by simply 
 changing the description of the logic. Simulating all the possible fail- 
 ures, we can obtain a set of input patterns and corresponding output 
 patterns for test dictionary information with which we can analyze the 
 test results. 
 
The diagnosis of the ILLIAC IV quadrant, especially Control 
 Unit and Processing Elements will he performed by following procedure. 
 A failure will be isolated within an easily replaceable unit such as CU 
 cards or PE by the on-line diagnosis built in the operating system. This 
 replaceable unit is changed with the error-free unit. The defective unit 
 is diagnosed by the off-line test equipment. With the assistance of a 
 test dictionary, the defective component in this unit is found by this 
 machine. We will discuss the test dictionary generation for the off-line 
 diagnosis in this paper. 
 
2. THEORETICAL DESCRIPTION OF DIAGNOSTIC TEST GENERATION 
 
 2.1 Definitions 
 
 Let p be the number of inputs of the circuit and 
 
 A = { A. | j = 1, 2, 3, >•-, 2 P and A /A if r / s ) 
 
 J r s 
 
 where A. = ( az , a~., az, -- a. --, a ) and 
 J 1 2' 3 i P 
 
 a? e { 0, 1 } for i = 1, 2, — , p. 
 Then, A. is a particular input pattern of the circuit and A is a set of 
 
 J 
 
 all the possible input patterns of the circuit. Similarly, let q. be the 
 number of outputs of the circuit and 
 
 B = { B. | J = 1, 2, 3, — , 2 q andB /B ifr/s }, 
 
 where B. = ( bj[, b^, b^, — , bj, — , b^ ) and 
 
 bj G { 0, 1 } for i = 1, 2, 3, — , q- 
 
 Then, B. is a particular output pattern of the circuit and B is a set of 
 J 
 
 all the possible output patterns of the circuit. 
 
 Let F = { f_, f.,, f_ , f. } be a set of functions 
 
 12 k J 
 
 where f is the function of the logic circuit without failures 
 
 
 and f , f , , f (f. / f . if i / j) are the functions of the logic 
 
 with failures. 
 
 Error Table is a table which can be derived from the Fault Table 
 by the following procedure. An Error Table has F - {f } and A as its row 
 headings and column headings, respectively, and the (i - j) element 
 e. . is defined by 
 
e. . = U (B rt . Q B. .) 
 ij Co ij 
 
 = (b° J ©D^) U (b° d ©** d ) U ... U (b^©b^). 
 
 From the definition above, it is easy to see the validity of 
 the following proposition. 
 
 Proposition 1. 
 
 A failure corresponding to the function f . can be detected at 
 the output of the circuit by input pattern A. if and only if e. . = 1. 
 
 J -'-J 
 
 The example of Error Table is shown in Table 2.2 and the example 
 of network is shown in Figure 2.1. 
 
 For each A. eA, f. eF assigns a value B„. eB, i.e., B„. = f„ (A.) 
 
 B . is the output pattern of the circuit without failures for the input 
 
 pattern A. . 
 J 
 
 A table, whose row headings are the elements of F, column 
 headings are the elements of A and (i, j) - element is B. ., is called a 
 Fault Table or Fault Matrix [1]. 
 
 2.2 Mathematical Description 
 
 Card Test Generator System has been developed for ILLIAC IV logic 
 card diagnostic test generation. The purpose of the Card Test Generator 
 System is to generate the input test patterns for failure detection or 
 location with exhaustive pseudo-random patterns. The reasons why the 
 exhaustive pseudo-random patterns are used for input test patterns are as 
 follows. Recently, the complexity of printed circuit card has increased 
 with the improvement of hardware technology. Therefore the number of 
 connector pins may be very large (say 100). For example, a typical CU 
 (Control Unit) card of the ILLIAC IV computer has approximately 150 input 
 
Figure 2.1 Example of Network for Error Table in Table 2.2. 
 
Table 2.1 
 
 Table of the Failed Function vs. Failure 
 of the Network Shown in Figure 2.1 
 
 
 
 Failed function 
 
 Failure 
 
 f i 
 
 PKG 2-L-05 
 
 f 2 
 
 PKG 2-L-ll 
 
 f 3 
 
 PKG 3-H-U2 
 
 h 
 
 PKG 3-L-08 
 
 f 5 
 
 PKG 3-L-ll 
 
 f 6 
 
 PKG 1-L-ll 
 
 f 7 
 
 PKG 2-L-08 
 
 f 8 
 
 PKG 2-L-09 
 
 f 9 
 
 PKG 1-H-Ul 
 
 f 10 
 
 PKG 2-H-05 
 
 f ll 
 
 PKG 2-H-UO 
 
 f 12 
 
 PKG l-L-08 
 
 f 13 
 
 PKG 2-H-Ul 
 
 f lU 
 
 PKG 3-H-I4O 
 
 f 15 
 
 PKG 2-L-20 
 
 f l6 
 
 PKG l-L-09 
 
 f 17 
 
 PKG 1-H-UO 
 
Table 2.2 
 
 Error Table of the Network Shown 
 in Figure 2.1. 
 
 Failed 
 Function 
 
 
 
 Input 
 
 Pattern 
 
 
 
 
 -x T 
 
 A T 
 A 2 
 
 A T 
 A 3 
 
 T T 
 A, A/ 
 h 5 
 
 T 
 
 A 6 
 
 \ T 
 
 T 
 A 8 
 
 f i 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 f 2 
 
 1 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 f 3 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 f U 
 
 1 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 f 5 
 
 1 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 f 6 
 
 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 
 
 f T 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 f 8 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 f 9 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 f 10 
 
 
 
 
 
 
 
 1 1 
 
 
 
 
 
 
 
 f ll 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 f 12 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 f 13 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 f lU 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 f 15 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 f l6 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 f 17 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
pins. If we generate all possible combinations of input patterns to try 
 
 150 
 to detect the failures, the number of patterns is 2 .It is impractical 
 
 to generate all possible input patterns. 
 
 To solve this problem, the inputs of the card are partitioned 
 
 into groups, where for practical reasons we decided that each group would 
 
 at most have 16 input pins. This is possible because most of the cards 
 
 are designed in such a way that each of them contains several functional 
 
 blocks or several slices of functional blocks. By partitioning, the 
 
 number of input patterns to each group is made much smaller than the total 
 
 number of possible input patterns for test generation. If partitioned 
 
 input pin groups are functionally independent of each other, the input 
 
 patterns of each partitioned group can be generated independently. To 
 
 exhaust possible input patterns for each group input, a pseudo-random 
 
 pattern generation method is used, wherein consecutive patterns are 
 
 reasonably different and all 2 combinations are generated in exactly 2 
 
 steps (n < 16). The Card Test Generator System has two simulation parts, 
 
 one is Good Logic Simulation which simulates the failure free logic and 
 
 another is the Failed Logic Simulation which simulates the logic with the 
 
 inserted failures. The input pattern A.'s generated by the pseudo random 
 
 pattern generator are applied to these two Simulators. The output of Good 
 
 Logic Simulation represented by B n . associated with an input pattern A. 
 
 is compared with the output of Failed Logic Simulation of f „ represented 
 
 by B„.. If B„ . is different from B^ . , then the failed function f„ can be 
 
 detected by A.. The input patterns A. (je {1, 2, ..., 2 }) are applied 
 
 J J 
 
 to a logic card until all failed functions are detected. The set of input 
 patterns which can detect all failed functions is essential even though 
 
this is not minimum set for failure detection, and this set will be con- 
 
 T T T T 
 sidered as the set of the input test pattern A = {A, , A p , . .., A } in 
 
 the following discussion of failure analysis. Since the difference be- 
 tween the correct output B . and the incorrect output B . associated with 
 
 T 
 input pattern A. is significant for failure detection, the indication of 
 
 J 
 
 the difference between B . and B . is generated in the step of the card 
 test generation as an entry of the error table (Table 2.2). Therefore, 
 we have a special table called an Error table instead of the fault table. 
 
 In Card Test Generator System, input test patterns are first 
 generated for failure detection. This test generation procedure is de- 
 scribed as follows: 
 
 (1) Using a pseudo random test pattern A. and all failed function 
 
 J 
 
 are examined to determine if they are detectable by A.. 
 
 J 
 
 T 
 
 (2) Let the set of failed functions detectable by input pattern A 
 
 be F , (where F e F) . 
 
 (3) Next the f» in the subset (F-F ) are further tested by other 
 
 T 
 test patterns, and the subset F~ is found by test pattern A p . 
 
 (h) Step 3 is repeated until (F - U. F.) = 0, (where is the empty 
 
 J J 
 
 set). This process is shown schematically in Figure 2.2. 
 
 By this procedure, an error table is constructed as in Table 2.3- 
 
 T 
 We call this Error Table as Partial Error Table. A is the last input 
 
 r 
 
 pattern detecting the last subset of F. Once a failed function has been 
 
 detected, it is not tested again by later test patterns. Therefore, the 
 
 outputs of these failed functions with respect to the later input patterns 
 
 are not considered, but rather the detected failed functions are put into the 
 
 Partial Error Table and only the undetected failed functions are tested again. 
 
10 
 
 (STEP 1) 
 
 This is the set of all detectable failures. 
 
 (STEP 2) 
 
 The input patternA can detect the failure 
 
 subset F • Then F is removed 
 from the original failure set 
 for next step. 
 
 (STEP 3) 
 
 The input pattern A can detect the failure subset 
 F . Then F is removed from the 
 
 original failure set for next step. 
 
 Figure 2.2 Test Generation Procedure 
 Part I 
 
11 
 
 (STEP n) 
 
 With pattern A , all other failures are considered 
 n' 
 
 as detectable. 
 
 Figure 2.2 Test Generation Procedure 
 Part II 
 
12 
 
 Figure 2.3 Example of Network for Following Analysis 
 (A Part of PE Control Logic) 
 

 Table 2.3 
 
 Table of the Failed Function vs. Failure 
 of the Network Shown in Figure 2.3 
 
 Failed function 
 
 Failure 
 
 Failed function 
 
 Failure 
 
 "10 
 
 11 
 
 "12 
 
 "13 
 
 "15 
 r i6 
 
 '17 
 r i8 
 
 "19 
 
 20 
 
 "21 
 
 hlf-H-02 
 H4-H-05 
 HU-L-01 
 Kl-H-05 
 Kl-H-Ul 
 K1-L-01+ 
 Kl-L-13 
 Kl-L-16 
 K2-L-02 
 K3-H-0U 
 K3-H-05 
 K3-L-09 
 K3-L-12 
 K3-L-16 
 H^-H-01 
 H^-L-02 
 HU-L-1^ 
 K1-H-0U 
 Kl-H-43 
 K3-L-08 
 
 H1+-L-13 
 
 22 
 
 "23 
 ■2k 
 
 : 25 
 r 26 
 
 r 27 
 ^28 
 
 F 29 
 F 30 
 
 31 
 
 '32 
 
 33 
 
 : 35 
 '36 
 
 37 
 38 
 
 r 39 
 
 : ko 
 
 Ki-L-05 
 Ki-L-08 
 Ki-L-11 
 
 K3-H-1+1 
 HU-L-12 
 K3-H-U2 
 H^-L-05 
 
 hU-l-16 
 
 K3-H-M+ 
 K2-L-16 
 K2-L-11 
 Kl-H-ljO 
 K1-H-U2 
 K2-H-02 
 K2-L-13 
 K3-L-20 
 K3-H-40 
 K2-L-12 
 K2-L-1U 
 K2-L-09 
 
Table 2.k 
 Partial Error Table 
 
 14 
 
 INPUT PATTERN NUMBER 
 
 FA1LEP 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 FUNCTION 
 
 1 
 
 2 
 
 3 
 
 a 
 
 5 
 
 6 
 
 7 
 
 e 
 
 9 
 
 10 
 
 11 
 
 12 
 
 13 
 
 14 
 
 15 
 
 F 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 2 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 3 
 
 
 
 
 
 
 c 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 4 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 5 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 6 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 7 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 8 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 9 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F10 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Fll 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F12 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F13 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F H 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F15 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F16 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F17 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Fie 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F19 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F20 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F21 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F22 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F23 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F24 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F25 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F26 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F27 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F28 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F29 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F30 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F31 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F32 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F33 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F3* 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F35 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F36 
 
 
 
 
 
 
 
 c 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 F37 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F36 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 F39 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 F40 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 FA1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
15 
 
 Since the Partial Error Table is made for failure detection, it 
 
 doesn't have sufficient information to locate the failures. We define 
 
 1 T 
 
 e.. = ( ] if and only if f . is detected "by A.. For example, if f ., f . 
 
 T 
 are the failed functions detected by input pattern A., 
 
 (i) e n = e, i+1)i = for A^ (i 6 (1, 2, ..., j-1)) 
 
 (11) e lo = e (i + l)j = 1 f ° r A ] 
 
 T 
 (iii) e„. and e, „ , \. are undefined for A. (i e fj+1, j+2, ... k}). 
 
 Let E. be the error pattern fector of f », E„ cannot be compared with E» , 
 
 because of the restriction of (iii). Therefore, this error table is insuf- 
 ficient for the purpose of distinguishing failed functions. To complete 
 the undefined element e«., e, >. . in (iii), another procedure is required. 
 
 T T T 
 We will try to use the input test pattern set {A., A , ..., A } 
 
 for locating failed functions. In Figure 2.2, when the subset of failed 
 
 m 
 
 functions F. is found by A., the failures in the subset U F. (i e (1,2, ..., 
 J G i x 
 
 m 
 
 (j-l)}) are neglected for the input pattern A.. Therefore, we might be 
 
 u 
 
 able to find some of the failures which belong to U F. (i e {1, 2, ..., 
 
 i ■ L 
 
 m 
 
 (j-l)}) using input pattern A., as shown in Figure 2.2. To completely fill 
 
 J 
 
 the undefined entries of the Partial Error Table, the set of input test 
 
 T T T 
 patterns {A , A , ..., A } is returned to the input of Card Test Generator 
 
 System (Figure 2.k) . 
 
 After completing the Partial Error Table, we call it the Com- 
 pleted Error Table (Table 2.5). With this Completed Error Table, failure 
 location capability might be improved. Let E, be an error vector of the 
 failed function f , this is a row vector of the error table and E„ is 
 
 denoted as 
 
 E £ " (e £L' e £2> '"> e £r ) ' 
 
16 
 
 (STEP 1) 
 
 (STEP 2) 
 
 The set of all detectable 
 failed functions. 
 
 A_ can detect the subset TP . 
 The subset F, is not removed 
 
 from F. 
 
 A Q can detect the subset F Q 
 
 F is not removed from F. 
 
 (STEP 3) 
 
 A„ can detect the subset F . 
 
 F is not removed from F. 
 
 (STEP r) 
 
 A can detect the last subset F . 
 r r 
 
 The set F is completely detected. 
 
 Figure 2.k An Illustration Model for Test Generation 
 
Table 2.5 
 Completed Error Table 
 
 37 
 
 INPUT PATTERN NUMBER 
 
 FAILED 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 FUNCTION 
 
 1 
 
 2 
 
 3 
 
 4 
 
 5 
 
 6 
 
 7 
 
 6 
 
 9 
 
 10 
 
 11 
 
 12 
 
 13 
 
 14 
 
 15 
 
 F 1 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 F 2 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 F 3 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 F 4 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 F 5 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F 6 
 
 
 u 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 F 7 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 F 8 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 F 9 
 
 
 
 1 
 
 1 
 
 1 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 F10 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 Fll 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F12 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F13 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F14 
 
 1 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 F 15 
 
 
 
 
 
 
 
 
 1 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 F16 
 
 
 
 
 
 
 
 
 1 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 F17 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 Fie 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 F19 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 F20 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F21 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F22 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 F23 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 F24 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 F25 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F26 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F27 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F26 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 F29 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 F30 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 F31 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F32 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F33 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F34 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F35 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 F36 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 F37 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 F38 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 F39 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 F40 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 F41 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 G 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
18 
 
 Proposition 2. 
 r 
 If U_ n (e . © e .) =1 for arbitrary u,v, u / v then all failed 
 
 functions are distinguishable. 
 
 Proof: 
 
 To distinguish the difference between two error vectors 
 
 E and E , it is sufficient that at least one of the elements 
 u v 
 
 in E is different from the corresponding element in E . If 
 u v 
 
 r 
 
 U , (e . v © e .) = 1 for u d v, (e , © e _) U (e _ Q e _) 
 j=l uj ^ w vj r ul w vl u2 v2 
 
 U ... U (e ©e )=1. At least one term of above boolean 
 ur w vr 
 
 equation is non-zero. Let jth term be non-zero, then 
 
 e . © e . = 1. To satisfy e . © e . = 1, e . = and 
 
 uj ^ vo uj v vj uj 
 
 e . = 1 or e . K 1 and e . = 0. Since e . is not equal to e ., 
 vj uj vj uj * vj' 
 
 E is different from E for u ^ v. Therefore, E is distin- 
 u v ' ' u 
 
 guishable from E by the jth element in error vector. For 
 
 arbitrary u, v (where u / v, and u, v € {1, 2, . .., k}), if 
 r 
 
 U t (e . © e .) = 1, then all failed functions are distin- 
 
 j=l uj w vj y 
 
 guishable to each other. 
 
 In the Completed Error Table, a few failed functions may remain 
 indistinguishable. We define these failed functions as pseudo- indistin- 
 guishable failed functions. Let G be the set of the pseudo-indistin- 
 
 St 
 
 guishable failed functions (where a e {1, 2, ..., w} and w is the number 
 of these sets). Let G be the union of the sets G (a € {1, 2, ..., w}), 
 
 St 
 
19 
 
 then G is denoted with G as 
 
 a 
 
 G = G n U G- U ... U G . 
 12 w 
 
 The distinguishable failed functions belong to the subset (F - G) . 
 
 These pseudo -indistinguishable failed functions may become 
 
 distinguishable when their output pattern vectors are examined. Let g. 
 
 be the transfer function between the input test pattern and the value of the 
 mth bit of output pattern. That is, b = g. (A.) (where j e {1,2, ...,r}) 
 
 Let an output pin signal pattern vector b„ be defined as 
 
 Vn = 'W^' g |m (A 2>> •••' g im (A r )} 
 
 = (b*\ b i2 , ..., b fr ) 
 
 m m m 
 
 b is the value of the mth bit of output pattern without failures and 
 m 
 
 b if the output pin signal pattern vector without failures. 
 
 We introduce a Pin Level Error Table containing pin and input 
 pattern information for each failed function. Basically a Pin Level Error 
 Table is made for each failed functions. Therefore, we have k (where k 
 is the number of failed functions) Pin Level Error Tables. The Pin Level 
 Error Table for failed function f g is constructed as follows: 
 
 The incorrect output pattern for failed function f „ is compared 
 
 with the correct output pattern by applying exclusive-or operation to 
 
 T 
 them for all A. . 
 
 J 
 
 In the Pin Level Error Table, the row designator is the pin p 
 
 T 
 and the column designator is the input test pattern A.. Each entry of 
 
 J 
 this table indicates the difference between the correct operating value 
 
 and the failed operating value. 
 
20 
 
 Let P„ (me {1, 2, . .., q}) be the mth pin patter vector; i.e., 
 the mth row of the Pin Level Error Table for a particular failed function 
 f .. That is, P„ is expressed as 
 
 V = b 0m© b |m 
 
 " (g 0m <4> © g |m <4>> Som < A 2> © ^ (**), 
 
 ■■■' ^U^&s^Ul))- 
 - =(b 01 @b fl , b°W 2 , ...,b 0r ©b to )- 
 
 m^m mm 7 m ^ m 
 
 Proposition k. 
 
 If U . (b°^ © b^) = 1, then failed function f. is detectable 
 j=l m ^ m ' ' £ 
 
 at pin p . 
 m 
 
 Proof: 
 
 It is sufficient that at least one element of b, is 
 different from the element of same position of b~ . 
 
 If U , (b°^ © b^) = 1, at least one term of U (b°^ © b^) 
 j=l v m w m ' ' j=l m w m 
 
 is non-zero. Let that be the jth term, the b © b = 1. 
 
 ' m v m 
 
 Therefore b J is different from b J and f „ is detectable at pin 
 
 m m Jo 
 
 T 
 p with input pattern A. • 
 
 An example of the Pin Level Error Table is shown in Table 2.6 a) 
 
 P. = (001000010000000) (where I = 21, m = l) is dectable at pin p m 
 
 T T 
 with input pattern A and An • 
 
21 
 
 Table 2.6 a) 
 Pin Level Error Table of Failed Function : 
 
 21' 
 
 INPUT PATTERN NUMBER 
 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 1ft lb 
 
 PI 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 P2 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 P3 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 P4 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 P5 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F6 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 F7 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Table 2.6 b) 
 Pin Level Error Table of Failed Function f ol _. 
 
 INPUT PATTERN NUMBER 
 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lb 
 
 PI 000000000000000 
 
 P2 ooooooooooooooo 
 
 P3 ooooooooooooooo 
 
 p4 ooooooooooooooo 
 
 P5 ooooooooooooooo 
 
 p6 ooooooooooooooo 
 
 P7 001000010000000 
 
m 
 
 22 
 
 By Proposition h, we can find the set of pins at which the 
 failed function is detectable. Let P be the set of all output pins p 
 and be denoted as P = {p , p , . .., p }. 
 
 Let V „ be the set of output pins at which failed function f g is 
 
 detectable (P. c P) . Now, assume that failed functions, f . , f. are pseudo- 
 l i 3 
 
 indistinguishable from each other. We can find P. and P. for each f . , f. 
 
 by the Pin Level Error Table of each failed function. We can also 
 
 distinguish f. from f ., if P. is different from P. . 
 i J i J 
 
 Proposition 5. 
 
 Let f. and f . be failed functions which are pseudo- indistinguish- 
 able from each other. If P. / P., then f. is distinguishable from f . by 
 pin number. 
 
 There is an important relation between the Pin Level Error Table 
 and the Error Table. Proposition 6 shows this relation. 
 
 Proposition 6. 
 
 ! 
 
 Let p ' (m e (m. nu, .... m,} where d is the number of element 
 
 m 12 ' d J 
 
 t 
 
 of P.) be the element of P. and P ' be the m th pin pattern vector of 
 iu So m jo 
 
 m d 
 
 failed function f ., then f U p ' = E„ . 
 
 m =m 
 
 Proof: 
 
 m. 
 
 ,u" p • : ,u ((b ^- e ^), (^°? ©b^),..., 
 
 ' £m ' m ' w m ' m ' w m ' " 
 m =hl m =m 
 
 m' w m' 
 
23 
 
 Since the pin pattern vectors of elements in (P - P.) are 
 
 m d q 
 
 all zero vector, ,U p • ' = U p 
 
 m =itl m=l 
 
 (where q is the number of output pins) . 
 
 \ p, = S ((b 01 © b fl ), (b 02 © J 2 ), ..., ( b 0r © „*» 
 
 m=l #m m=l vv m w m y ? v m w m y ' ' v m ^ m 
 
 = ( 3, (t 01 © b fl >, S n ( b 02 © b^ 2 ), ..., 3 ( b 0r © b te » 
 
 v m=l v m w m " m=l m w m y ' ' m=l m w m 
 = (e £L' e ^2' "•' e ir ) 
 
 = E i 
 
 The procedure of analyzing the failed functions is summarized 
 
 in the next Proposition. 
 
 Proposition 7- 
 
 When E. = E. (for E. . I i 4 j). if P. / P., then f. is dis- 
 
 tinguishable from f ., if P. = P., then f. is still indistinguishable from 
 
 J i J i 
 
 f. . 
 
2k 
 
 3. THEORETICAL APPROACH FOR TEST DICTIONARY GENERATION 
 
 3.1 Method of Test Dictionary Generation 
 
 To diagnose a failed printed circuit card, we have to examine 
 
 T 
 carefully the relationship between input pattern A. and test output results 
 
 J 
 
 B,. . It is desirable to have a test dictionary to show relations between 
 
 T 
 input pattern A., output result B g . and a failed function f . for efficient 
 
 failure analysis. With the assistance of a test dictionary test results 
 
 will be analyzed either automatically or manually, and a field maintenance 
 
 personnel will have the necessary information to identify the failed 
 
 circuit components or packages. 
 
 The necessary information for a test dictionary for analyzing 
 
 T 
 the failed functions, that is, the input pattern A. (je{l, 2, ..., r}), 
 
 J 
 
 the output pin name p (me{l, 2, ..., q}) associated with a failure, and 
 the failed function f . (&e{l, 2, ..., k}) is given in the Pin Level Error 
 Table prepared by the Card Test Generator System discussed in the previous 
 
 m 
 
 section. An entry in the Pin Level Error Table represents g (A. ) ^) 
 
 T 
 g„ (A.), where m is the index number of pin p , I is the index number of 
 °zm 3 m 
 
 T 
 failed function f, and j is the index number of input pattern A.« If 
 
 T T 
 
 g~ (A.)©g„ (A.) = 1, this tells us that the failed function f„ is 
 
 T 
 detectable at the pin p by the input pattern A. . 
 
 T 
 We define the relationship between A., P and f„ as a triplet 
 
 * j m I 
 
 T 
 (A., p , f .). This will be represented simply as an index triplet 
 
 (j, m, I), since there exist one to one correspondences between Input 
 
 pattern A., output pin name p and failed function f «, and j, m and I 
 
 respectively. 
 

 A complete set of index triplets (j, m, $,) is basic information 
 for the test dictionary, and usually these index triplets are sorted so 
 that a field engineer or some automatic test equipment can easily find 
 desired triplets. If we take into account the ordering with respect to 
 these elements of an index triplet (j, m, $,) , we define the hierarchy of 
 elements of an index triplet as a dictionary index term or keyword, such 
 that the left element has the highest hierarchy and the right has the 
 lowest hierarchy. And we introduce the lowest hierarchy designator d 
 given by 
 
 d {$, m, I) = fg . 
 
 By changing the hierarchy of elements in an index triplet, that 
 is, by permutating the key words, six different type dictionaries can be 
 generated, each dictionary consisting of a complete set of index triplets. 
 It should be noted that there are no differences in those six dictionaries 
 with regard to dictionary information. Let representative triplets of 
 these dictionaries be defined as follows: 
 
 1- [3, m, i] 
 
 2. [d, i, m] 
 
 3- [i, m, j] 
 
 ^ [&, 3, m] 
 
 5- [m, j, ft 
 
 6. [m, I, j]. 
 When we consider the hierarchy of elements of those six triplets, the 
 
 lowest hierarchy elements are determined by the higher hierarchy two 
 
 T 
 elements, for example, d (j, m, £) is determined by the input pattern A. 
 
 and the output pin name p . We can choose any type dictionary for a 
 
26 
 
 failed function identification procedure as will be shown later. In this 
 paper, we will discuss three dictionaries, which are denoted by the repre- 
 sentative triplets [j, m, 8,1, [i, m, j], and U, j, m] . The [j, m, i5] 
 
 T 
 dictionary gives the suspected failed functions if input pattern A. and 
 
 J 
 
 output pin p associated with an unmatched output value are known, and 
 m 
 
 the other two dictionaries are useful to determine the failed function or 
 to isolate within a set of indistinguishable failed functions . 
 
 The following terminologies will be used in the explanation of 
 how to handle dictionaries in failed function identification procedures: 
 
 i) Definition of classifying designator D. 
 
 a) D/ s denotes the set of all index triplets. 
 
 VQ-j P) 7) 
 
 b) D/ s<x denotes the subset of the index triplets 
 
 v<x, is, y) 
 
 which have the same element a in them. 
 
 c) D/ n (a, 3) denotes the subset of the index 
 
 vcc, p, y) 
 
 triplets which have the same element a and 3 in 
 them, 
 
 where a, 3, y e (,], m, I } and a ^ 3> 3 £ 7> a ^ y . 
 
 ii) Definition of index set designator A^ a ' &' J >. 
 
 (<x B y) 
 A^ ' ' ' denotes the index set of next lower hierarchy 
 
 element of 6, where 5 e {j, m, £} and 5 is not 
 the lowest hierarchy element. 
 
 iii) Definition of the lowest hierarchy set designator d. 
 d denotes the set of the lowest hierarchy elements . 
 It is noted that if there is a set S which has only one element 
 (a, 3, y) , then d (a, 3, y) = dS. 
 
27 
 
 For example, three dictionaries are shown in Tables 3*1 and 
 3-2 along with examples of the above terminology. 
 
 3.2 Procedure for Failed Function Identification 
 
 In this section, we will discuss the procedure for identifying 
 failed functions. We introduce the Abstract Test Equipment (ATE) by the 
 following reasons. Generally, a general purpose computer can be used for 
 failure identification procedures, but an interface between the computer 
 and the card under test may be necessary. If we wish to find an efficient 
 method to identify the failure for high speed test execution and analysis, 
 it is preferable to design a special purpose computer for much more effi- 
 cient failure identification procedures. For example, PDP-9 and TI-561 
 computers are used for diagnosis of the CU and PE cards of ILLIAC IV 
 computer, but these diagnosis computers are not fast enough for test ex- 
 ecution and failure analysis in higher clock rates operation. Therefore, 
 we consider the ATE as a special purpose test equipment. The function of 
 ATE will be briefly discussed in 3*2.1, and three methods of identifica- 
 tion procedures by use of ATE will be described precisely and evaluated. 
 
 3.2.1 Abstract Test Equipment (ATE) for Identifying Failed Functions 
 
 3-2.1.1 The Function of ATE 
 
 ATE is an off-line diagnosis test equipment, and is used for 
 identifying failed functions in a card using the input test patterns, 
 output patterns and test dictionary records generated by the Card Test 
 Generator. The block diagram of ATE is shown in Figure 3»1« ATE is 
 
Table 3-1 Example of Test Dictionaries 
 
 28 
 
 
 [j,m,^] dictionary 
 
 [i,m,j] dictionary 
 
 [.0,j>m] dictionary 
 
 
 {(j 'l , V i l ) 
 
 (U^ny^) 
 
 C(i 1 ,j 1 ,m 1 ) 
 
 
 (j i'VV 
 
 U^m^jg) 
 
 (i 1 ,j 1 ,m 2 ) 
 
 
 (3 i'VV 
 
 (^ 1 ,m 2 ,j 1 ) 
 
 (i 1 ,d 2 ,m 1 ) 
 
 
 (j^^^j) 
 
 (^m 2 ,0g) 
 
 (^dg^g) 
 
 
 (3^2* & J 
 
 (ig,!!^,^) 
 
 ^2^"l' m l ) 
 
 
 (j^VV 
 
 (ig^^jg) 
 
 (& 2 ,3 lf m ) 
 
 %,3,y) 
 
 (j^nyig) 
 
 (V m 3' d l } 
 
 Ugjjg^) 
 
 
 (<V m 3 'V 
 
 (^ 2 ,m 3 ,dg) 
 
 (^ 2 *dg,m 3 ) 
 
 
 (Jg,!^,^) 
 
 ( VvV 
 
 U^,^) 
 
 
 (jg^m^ig) 
 
 Ug^,^) 
 
 U^j^nig) 
 
 
 (Jg^g,^) 
 
 (4 ,m 2 ,jg) 
 
 U^j-^nO 
 
 
 (jg,m 2 ,i 3 ) 
 
 ( V m 3^1 } 
 
 (iydg^g) 
 
 
 (jg,mg,^) 
 
 U^nyjg) 
 
 (i 3 ,j 2 ,m 3 ) 
 
 
 (j 2 ,m 2 ^ 5 ) 
 
 (VVV 
 
 (^j^mg) 
 
 
 (jg^ 3 ,ig) 
 
 (i v m 2 ,j 2 ) 
 
 U v V m 2 } 
 
 
 (dg,m 3 ,i 3 )} 
 
 ■ — -. ■■■■ ■ — 
 
 (^ 5 ,d 2 ,m 2 )) 
 
Table 3.2 Example of the Definition 
 
 
 
 fj,m,^} dictionary 
 
 $,m, j] dictionary 
 
 [J5,j,m] dictionary 
 
 
 If a = j, j 
 
 
 If a = I , 
 
 
 If a = ^ , 
 
 
 {(j^,^), 
 
 
 ((i^n^,^), 
 
 
 ((i^J^n^), 
 
 D (a) 
 (a, 3, y) 
 
 (j 1 ,m 1 ,i 2 ), 
 
 
 U-^nyjg), 
 
 
 (i^d^mg), 
 U-^dg*^), 
 
 
 (d^Eg^); 
 
 
 ^Vfe'V' 
 
 
 ( W n 2 )} 
 
 
 (d-^*^,^), 
 
 
 (i^^dg)) 
 
 
 
 
 (j^nig,^), 
 
 
 
 
 
 
 (d^^u*-^)* 
 
 
 
 
 
 
 (o-^ny^)) 
 
 
 
 
 
 
 If a = J 1 ,P = 
 
 m-L* 
 
 If a = i ] _, p 
 
 = v 
 
 If a = i 1 , P = d^ 
 
 
 {(d-^^,^), 
 
 
 {(^ 1 ^m l ,j 1 ), 
 
 
 {Ci 1 ^J 1 ,m 1 ), 
 
 D (a,P, 7 ) 
 
 (j 1 ,ra 1 ,i 3 )} 
 
 
 (i^^dg)} 
 
 
 U^d^nig)} 
 
 a(«,P,7) 
 
 If & = 3 V 
 
 
 If 5 = hl^ 
 
 
 if 6 = d x , 
 
 
 
 {m^m^m } 
 
 
 fd^Jg} 
 
 
 { V m 2 } 
 
 d(D (a,3,7) ' 
 
 If a = j,, 
 
 If a = i , 
 Cd-^dg} 
 
 If a = I , 
 1 
 
 (^Mg) 
 
 (a, 3,7) 
 
 
 = n^, 
 
 If a = i x , 3 
 
 (d^dg) 
 
 = v 
 
 If a = l v 3 = j^ 
 
 ^V m 2^ 
 
30 
 
 assumed to be composed of subunits such as memory, registers, comparator, 
 arithmetic unit and control unit. 
 
 Each subunit of ATE works as follows : 
 
 First, the card under test is initialized if necessary. The 
 
 T 
 set of input pattern A. and the set of the corresponding correct output 
 
 J 
 
 pattern B are stored into the Input- Output Pattern Table in the ATE. One 
 
 T 
 of these input patterns A. is loaded into the Input Pattern Store Register 
 
 J 
 
 and the corresponding output pattern B . is loaded into the Expected 
 
 Response Register. The contents of the Input Pattern Store Register is 
 
 transferred to the card and the output pattern of the cards are fetched 
 
 into Output Pattern Store Register. The output pattern B . is compared 
 
 with expected response B by the Comparator. If the Comparator indicates 
 
 B = B . , then the function of the card is not any failed function which 
 uj xj 
 
 T 
 can be detected by the input pattern A . . If the Comparator indicates 
 
 J 
 
 B^ . / B ., then the function of the card is failed function and information 
 Oj xj' 
 
 T 
 about pin p and input pattern A. will be used for failed function identi- 
 fication. The failure information associate with p is given by the Com- 
 parator. This results of the Comparator are transferred to the Auxiliary 
 Memory and stored. 
 
 Output results of the Comparator are processed by the stored 
 program for failure analysis . 
 
 3.2.1.2 The Function of Logic Devices 
 
 An abstract test equipment to identify the failed function in 
 a card under test is assumed to have following logic devices : 
 
31 
 
 3.2.1.2.1 Input-Output Pattern Table 
 
 This is the memory area for input patterns and corresponding 
 output patterns for test. 
 
 3.2.1.2.2 Test Dictionary Table 
 
 This is the memory area for test dictionary records . 
 
 3.2.1.2.3 Input Pattern Store Register 
 
 This register is used for storing one of the input patterns from 
 the Input- Output Pattern Table. 
 
 3.2.1.2.4 Output Pattern Store Register 
 
 This register is used for storing the output result of the card 
 under test. 
 
 3.2.1.2.5 Expected Response Store Register 
 
 This register is used for storing the correct expected output 
 pattern associated with the input pattern. 
 
 3.2.1.2.6 Comparator 
 
 The content in Output pattern Store Register is compared by this 
 Comparator with the expected response value in the Expected Response 
 Register. The Comparator has the same number of outputs as the Output 
 Pattern store Register. When there exists a difference between the output 
 value of pin p of the Expected Response Store Register and the output 
 value of pin p of the Output Pattern Store Register, the output of pin p 
 
 of Comparator is a 1, otherwise a 0. The set of pins p such that the 
 
32 
 
 output value of pin p of Comparator is 1 is checked by the Control Unit 
 described in 3-2.1.2.8 and stored into Auxiliary Unit described in 3.2.1.2.7. 
 
 3.2.1.2.7 Auxiliary Memory 
 
 This Memory is used for storing the results of the Comparator. 
 
 The results of the Comparator are checked by Control Unit. Input pattern 
 
 T 1 
 
 A. and the set of pins {p output of Comparator is a 1 at p } are stored 
 
 in this memory as a set of information. 
 
 3.2.1.2.8 Control Unit 
 
 This unit consists of the control function of ATE and also 
 handles the stored program for ATE. 
 
 3.2.1.2.9 Arithmetic Unit 
 
 The functions are the search of Test Dictionary Table, the 
 comparison between the information in Test Dictionary Table and the 
 contents of Auxiliary Memory, and logical operation between triplets in 
 Test Dictionary Table. 
 
 3.2.2 First Failed Function Identification Method Using ATE 
 
 The purpose of this method is to find out the possible failed 
 
 function with the aid of the [j, m, £] ([pattern, pin, failure]) diction- 
 
 T 
 ary by using input pattern A. and the set of p at which the Comparator 
 

 <tf 
 
 *H 
 
 -p 
 
 u 
 
 0) 
 
 w 
 
 a 
 
 Id 
 
 
 
 o 
 
 
 H 
 
 «3 
 o 
 
 •H 
 tlO 
 O 
 
 1-3 
 
 -P 
 
 ?£ 
 
 ^ 
 
 0) 
 
 a 
 
 •H 
 
 l-H 
 
 03 
 
 
 w 
 
 > 
 
 oJ 
 
 £ 
 
 O 
 
 P> 
 
 O 
 
 ■d 
 
 a5 
 
 £1 
 
 w 
 
 O 
 
 w 
 
 3 
 
 •H 
 02 
 
 H 
 O 
 
 •P 
 
 a 
 o 
 o 
 
 0) 
 
 •H 
 
 l-H 
 
 i 
 i 
 i 
 
 A 
 
 Expected Response 
 
 ~1 — 
 
 s 
 
 ^ 
 
 Output Pattern 
 Store Register 
 
 Comparator 
 
 U 
 
 •p 
 
 I. 
 
 p> 
 p" 
 
 Ph 
 
 s 
 
 a 
 
 <1> 
 
 u 
 
 H 
 
 <D 
 
 & 
 
 -P 
 
 ctf 
 
 -P 
 
 R 
 
 crt 
 
 
 Ph 
 
 
 
 £ 
 
 
 
 
 ri 
 
 
 
 -P 
 
 « 
 
 0) 
 
 
 03 
 
 o 
 
 H 
 
 
 O 
 
 •H 
 
 ,Q 
 
 
 EH 
 
 ■P 
 
 <ti 
 
 
 
 O 
 
 E-i 
 
 
 
 •H 
 
 
 
 
 o 
 
 
 
 Figure 3.1 The Chart of ATE 
 
3^ 
 
 indicates a difference between actual response and expected response. The 
 [£, j, m] ([failure, pattern, pin]) dictionary is used to check all possible 
 failed functions and to identify the particular failed function. 
 
 Let us assume that we have detected an unknown failed function 
 
 T 
 f associated with a certain input pattern A., , and let the set of index 
 x J 
 
 numbers of the pins at which the Comparator shows a 1 be [m., m , . .., m ] 
 
 T 
 which is represented by C. Since we are using input pattern A., and have 
 
 J 
 
 observed a disagreement at pin p , (m'eC), | triplets (j, m, x), 
 
 (j, mp, x), . .., (j, m p , x), where x is the index of the unknown failed 
 
 function, must be selected by means of table look up on [j, m, l\ diction- 
 
 T 
 ary to find all possible failed functions detected by A. . In other words, 
 
 J 
 
 the sets D/ . s (j T , m), (m e A.?' m ' ') on the [j, m, £] dictionary 
 
 Vj, m, jo) j 
 
 are looked up at first. In the set D/ . m „\ (j f )> sets V, . s (j; m'), 
 
 V j, m, Xj ) \j , m, jo j . 
 
 for all (m'ec, CC &\y m ' ^)have necessary information to find out an 
 
 J 
 
 unknown failed function f from possible failed functions f ., 
 
 X Xj , 
 
 U'e(i ,, i , ..., i }). The unknown failed function f is expected to 
 
 1 d T] x 
 
 be found from the triplets in the sets ~D f . »x (jj m'), for all 
 (m'ec). 
 
 The contents of D/ . g s (jj m' ) will be examined more 
 
 precisely in the following manner. These possible failed functions can be 
 
 t t 
 
 ( A m ) 
 
 identified by applying intersection operations to the sets b(D f . s ' 
 
 for all m'ec. If J) £C (d(D, . ^ (jj m'))) is the null set, then f x 
 

 cannot be properly identified, and unpredicated failures such as inter- 
 mittent failure and/ or multiple failures may have occurred. If Q 
 
 (o"(D/ . n\ (dl m' ) ) ) contains only one element, then the element is 
 \ 3 y m > » ) 
 
 identified, because only this element can satisfy the relation between 
 
 T 
 input pattern A., and the set of pins p ,, for all m'eC. If 
 
 _ (S(D/ . n \ (j! m' ))) contains more than one element, then these 
 elements still remain as possible failed functions f ,,, . If we cannot 
 isolate to a single failed function in the previous step, the [£, 3, m] 
 dictionary is used for exact determination of the unknown failed function. 
 When we use the [$,, m, j] ([failure, pin, pattern]) dictionary, a f » t 
 
 is looked up and input patterns A.„, for all j n € A ,,' ' ^' and for all 
 
 m"e A,,'' ' are applied to the card and the output results of p , t 
 
 are examined, therefore the number of tests is equal to the number of 
 
 triplets in D/ » . \ (P ) . On the other hand, if we use the [i, 3, m] 
 \xj } m, 3 ) 
 
 ([failure, pattern, pin]) dictionary, a f « t is looked up and input 
 
 T (£ i m) 
 
 patterns A.„ for all j e A^,' J ' ; are applied to the card and the output 
 3 *> 
 
 results of p „ for all m"e A.„' ^' ' are examined, therefore the number of 
 
 m , ( ' vr\\ 
 
 tests is equal to the number of elements of (A.„ j"e A ' ^' }. 
 
 3 & 
 
 By looking up the triplet table on the [&, j, m] dictionary, the collection 
 
 of the sets {D/- . > (P ) for all Pe A ( ?' m ' l) , where cM' m ' £) is 
 U, j, m) ', m' m' 
 
 the set of index number of failed functions in Q _ (d(D/ . ^ (jj m')))} 
 are selected. D, . \ (P ) shows the relationship between the input 
 patterns and the corresponding set of pin numbers for the failed functions 
 fg* . When input patterns A T „ (j"e A^j' m ' ^ in D,^ . s (P)) are 
 
36 
 applied to the card for failure analysis purposes, and if a 1 appears at 
 all output pins p u (m"e A.,,' °' ) of the Comparator, the elements A.,. 
 
 and p n of triplets in D /fl . >. {V) satisfy the condition of the output 
 
 m * U, j, m) 
 
 results caused "by the failed functions associated with the input pattern 
 
 T 
 A. ir . Let these selected failed functions be the candidates of the function 
 J 
 
 f , "because there exists the possibility that more than one failed function 
 f« t could be selected by test dictionary lookup, if these failed functions 
 f.,, f.„, ...f.s are indistinguishable from each other or the output results 
 of one f «, includes the output results of the other f *„ in the test dic- 
 tionary table. In the following discussion, we restrict the failed func- 
 tions as {f r , for all t p e ^^ (d(D ( ^ (jj m')))}. 
 Lemma 1. 
 
 U, j, m) U, m, j) 
 where f r e m g ec (d(D (jf M) (jM*))). 
 
 Proof : 
 
 Vj,») <''>-< D «, j,») u; r>. *» <u j"« 4H"°) 
 
 By definition, the triplet {l\ j',' m" ) is assumed to be same as 
 the triplet {V, m" j"). Therefore 
 
 D (i , m , -j) U') E CUj < j")| j"6 A<f> ^ m) m"e £$*> *> m) ] 
 = iUl jym»)| j"*^' J ' m> m" 6 A^' J '' m) } 
 
 By the same procedure, (D, n . s {V ) => D/« ,\ (i' ) holds, 
 
 \lo, j, m; — \,#, m, j; 
 
37 
 
 then we have 
 
 V (0 ■ x U*) = D/fl n U') 
 
 Theorem 1. 
 
 If 
 
 m € A^ f j g A m „ 
 
 © g „ (d u; m y j")))) = 1, 
 
 forf,, . ^ 0( D( 3> n> |} («»•))), 
 
 then f «, is chosen as the one of the candidate failed functions 
 by use of the \.l 3 m > j] dictionary. 
 
 Proof: 
 
 Since n ( fl (g (d (i», m", j» ) ) © 
 
 i;' m 
 
 m "V J V 
 
 T 
 g „ (A.,,)) = 1, every triplet which 
 
 belongs to D, „ . N (i') satisfies the relation between the 
 
 T 
 output results of p „ associated with the input pattern A.„ 
 
 caused by a failed function f . Therefore f „, is chosen as 
 
 one of the failed function candidates with the aid of the 
 
 [&, m, j] test dictionary. 
 
 Corollary 1. 
 
 f -, is chosen as one of the possible failed functions f by the 
 
 Ju X 
 
 [£, J, m] dictionary, if the condition described in the theorem 1 is 
 satisfied. 
 
38 
 
 Proof: 
 
 SlnCe D U d, m) (r) = °U, m, j) (r) by the Previous 
 Lemma 1, all triplets which belong to D/» . \ (£') also 
 
 satisfy the output condition caused by f 
 
 With the [j, m, i] dictionary, possible failed functions can be 
 selected, but there might exist indistinguishable failed functions or an 
 inclusion relation between a failed function and another failed function 
 in the possible failed functions. Therefore, these possible failed function 
 are examined by [£, j, m] dictionary. 
 
 We assume that failed functions f „, and f .„ are found by this 
 method. By the foregoing theorem, 
 
 n ( n (g n .- (a U; < r))0g w , (d U; m; j»)))) = i 
 
 m"eA j"eAm" 0m ^ 
 
 and n ( n ( g (d u; m ; r))© g- (d U; *;■ r)))) = 1 '- 
 
 m"eAi" j"€Am" Um ^ 
 
 To distinguish f ., and f .„ , the set D/ , . \ (£') should be compared 
 
 £ £ \J6> m, j ) 
 
 with the set D (i> M> 3) (i"). If D (ij m> a) (!•) ^ D (i> ^ ., (I"), then 
 f Qx is distinguishable from f .„ and f should be identified as one of them. 
 
 Xj Xj X 
 
 If D/, .n (i f ) = D/ . .x {£"), then f., is indistinguishable from 
 
 \lo } m, j J (_#, m, j J # 
 
 f „„ , and f can not be uniquely identified. 
 
 Ju X 
 
 These relations are generalized into the next Proposition. 
 Proposition 8. 
 
 Let f n , f 09 , ..., f „ satisfy the theorem, where £ , £ , ..., 
 £s e {1, 2, ..., k}. 
 
 If D i, m, J) (r) * D (i,m, J) U"), where r M" -d i; |» 
 e{l, 2, ..., k}, then these failed functions are distinguishable from 
 

 each other, and f is identified as one of them. If D/„ . \ (&-.) = 
 ' x \Hj, m, jj 1 
 
 D/ „ . N (I J) = ... = D/ « . n (i ), then these failed functions are 
 U, m, j) 2' U, m, j) b" 
 
 indistinguishable from each other and f is not uniquely identified. 
 
 The procedures of this method are summarized in the flow chart 
 of Figure 3.2. 
 
 3.2.3 Second Failed Function Identification Method Using ATE 
 
 In the first failure analysis procedure, input patterns are 
 inserted into the card until an unmatched response is detected. To 
 identify failures, possible failed functions are picked up from the 
 [j> m > -#] dictionary and the results associated with the input pattern 
 sequence for each possible failed function are examined by use of the 
 [H, j, m] dictionary. The failed function which satisfies all input 
 patterns could then be determined. 
 
 If there exist many possible failed functions in the [j, m, £~] 
 dictionary, many input pattern sequences are required to find the failed 
 function in the [£, j, m] dictionary and testing might be time consuming. 
 This is the disadvantage of the first method. 
 
 In this section, we propose another failure analysis method to 
 
 identify failed functions after applying all of the input patterns. All 
 
 T 
 A.'s are inserted into the card under test without any failure analysis 
 
 and the outputs of Comparator are stored into the Auxiliary Memory for 
 
 m mm 
 
 error analysis: that is, if g„ (A.,) + g (A.,) =1, A., and p , are 
 
 Om j xm «j j m' 
 
 T 
 recorded into the Auxiliary Memory for all A. of the card under test. The 
 
 J 
 
 T 
 Comparator output pattern file of pairs (A.,, p ,) is recorded completely. 
 
 The unknown failed function f can be identified by analyzing the recorded 
 
 (A.,, p ,) and the [i, j, m] dictionary as follows: Let this record be 
 
ho 
 
 Initialize Card and set A J, B Q . to Register 
 
 Xi> m > i) 
 
 m' 
 
 the set of index number of failed functions 
 
 in iAc wa (J , m, i) (*;»'») 
 
 r 
 
 the set of index number of the set 
 
 KD 
 
 Figure 3.2 Flow Chart of the First Method. 
 
 Part I 
 

 Initialize Card and set A.n> ^ • „, 
 
 .„ AS, f\, m) 
 where j "eAJ, , ' J ' ' 
 
 
 m) 
 
 <- next 
 
 
 index s 
 
 et 
 
 
 m) 
 
 ln D (i, 
 
 J. 
 
 m) ' 
 
 j") 
 
 Memorize f\ , in Auxiliary Memory 
 
 i f -next element in AV ^ m ^ 
 
 m' 
 
 Flow chart in the dashed line shows 
 END \ ^■' ie P roc edure controlled by stored 
 program. 
 
 Figure 3.2 Flow Chart of the First Method. 
 
 Part II 
 
1+2 
 
 represented as an index triplet i.x, j,' m'), where f is the unknown 
 failed function. The unknown failed function f can be identified as f „. 
 
 if D (i, J, m) ^ is equal to B (jl -j m) ^') by searchin S the U> J> m l 
 dictionary. 
 
 If D/. v (x) Id,. , {V) for all l\ then f cannot be 
 
 identified by the test dictionary, and intermittent or multiple failures 
 
 may be expected. 
 
 If D, . . \ (x) = D/ - . v U, ) = = D/ . . v {Us), 
 
 U> 3, m) U, o, m) l y U, J, m) 
 
 then f belongs to the indistinguishable failed function f»_, . .., f. 
 
 The procedure of this method is summarized as in the following 
 flow chart in Figure 3«3« 
 
 3.2.U Third Failed Function Identification Method Using ATE 
 
 When the outputs of some pins of the Comparator show a 1, we can 
 pick up the set C, where the set C is defined as the set of index numbers 
 of the pins p , which show a mismatch at the Comparator between output and 
 expected response, as described in the first method. 
 
 Possible failed functions can be found from the [j, m, £] 
 
 T 
 dictionary with respect to input pattern A. , and pin p , . Since 
 
 d(D/ . g s (j 1 , m 1 )) (where m'eC) contains possible failed functions, the 
 
 possible failed functions are selected by ANDing together 
 
 d(D/ . \ (y, m')) with respect to the index numbers of the pins p , , 
 
 Q _ (d(D, . \ (y, m'))). If all the sets { Q _(d(D, . n (j ' >m')))) 
 m'eC wv (j, m, £) K0 ' ''' l nr»eC v (j, m, i) 
 
 T 
 for all input patterns A., for which the Comparator showed a mismatch are 
 
 J 
 now ANDed together, then failed functions could be identified. Let A be 
 
«+3 
 
 J + i 
 
 + 
 
 Initialize ATE 
 
 Initialize Card and set A., 
 B n ^ to Register 
 
 YES 
 
 Memorize A. , p ,, where m'eC, and construct 
 j ' m' 
 
 D/ „ . s (x) in the Auxiliary Memory 
 \Xj) J ^ mj 
 
 Figure 3.3 Flow Chart of the Second Method 
 
 Part I 
 
kh 
 
 Lookup D Uf . f m) U'), 
 
 T 
 
 pick up (A ,, p m .) which belongs to D^ * ^ 
 
 (r) 
 
 L. 
 
 Store f „, in the file F in Auxiliary Memory 
 
 If F = <p, no failures are identified. 
 
 If F has one element, f is identified. 
 
 7 x 
 
 If F has more than one element, these failures 
 are indistinguishable. 
 
 Flow chart in the dashed line shows 
 the procedure controlled by the 
 stored program. 
 
 Figure 3. 3 Flow Chart of the Second Method 
 
 Part II 
 
U5 
 
 the set of index numbers of the input patterns which have detected unknown 
 failed functions f x . If ^Q £A (^^ (d(D(^ & ) (j,' m'))) has only 
 
 one element, then a failed function is identified. This is given clearly 
 in the following reason. 
 
 Let's assume that n ( fl, , (d(D, -n (jj m'))) 
 
 J 
 
 = {f/,,), then we can get the set of triplets {(j,' m,' V) \ 
 
 m'e A^' m ' ^ j'eA} such that d(j,' m,' V) = ? , • Since the triplet 
 J> » . 
 
 (j; m, 1 J5') is assumed to be equal to the triplet (£} y, m 1 ), 
 ((j; m; r) | m'eA^' m ' i} , we have j'eA] = {U, 1 j,' m,') | 
 
 J 
 
 m , eA U, J. m)^ ...^ ^ For ^„^ ^,^ it ig clear that we have 
 
 D (i, d, m) (r) ^ [i > y > m,) I m ' eA ^' J ' ^^ J ' eA} * Therefore 
 
 D/ g . s (i') consists of the set of triplets strictly related to fg,, 
 
 and failed function is identified as f „,. 
 
 If n ( n (a( D (j; m')))) has more than one 
 j'€A meA^' ' ^ 3 > m > Z) 
 
 J 
 
 element, then these elements are indistinguishable with each other. 
 
 If " ( %, m, I) (S(D (j, », I) («»'»))-*, then 
 d ' €A meAj ' 
 
 we have failed to identify f and intermittent or multiple failures are 
 
 expected. 
 
 This procedure is summarized by the flow chart in Figure 3«^« 
 
1+6 
 
 Initialize ATE,j «- 1, X «- all l's, initialize the 
 test result vector X. 
 
 YES 
 
 
 NO 
 
 
 
 
 
 
 Initiali: 
 
 :e 
 
 Card 
 
 and 
 
 
 set 
 
 T 
 A . & 
 
 B 
 
 Oj 
 
 to 
 
 Regi 
 
 ster 
 
 X ~ XAMD Ac (3(D (j, m, t) {i! m,))) 
 
 ~f is identified 
 
 as {X}. 
 
 Flow chart in the dashed line shows 
 the procedure controlled by the 
 stored program. 
 
 Figure 3.k Flow Chart of the Third Method 
 
hi 
 
 3-3 The Comparison Between First, Second and Third Methods 
 
 The three methods described in previous sections are evaluated 
 with respect to the execution time which is required to complete the identi- 
 fication of a failure. The procedure of each method is represented by the 
 flow charts in Section 3-2, since these flow charts show the function of 
 ATE. We introduce the formula for execution time to be estimated. The 
 parameters for this formula are defined as follows: 
 
 a = Initialization time for the card under test 
 
 P = Initialization time for ATE 
 
 n = Number of clocks to fetch B 
 
 xo 
 
 T ... = Period time of clock 
 elk 
 
 T = Write time of Auxiliary Memory 
 r = Total number of input patterns 
 
 T = Execution time of program for first method 
 
 (Time elapsed for steps contained in dashed lines in Figure 3*2) 
 
 T „ = Execution time of program for second method. 
 
 (Time elapsed for steps in dashed lines in Figure 3-3) 
 
 T ' = Execution time of program for third method 
 
 (Time elapsed for steps contained in dashed lines in Figure 3«^) 
 
 N = Number of loops to find B n . + B . = 1 (l < N < r) 
 
 x * Cy xj v - x - ' 
 
 k = Total number of failed functions 
 N 
 
 £ 
 
 Number of failed functions in the set Q {d.(D/ • /n(j> m '))} 
 (1 < N < k) m ^ , m ' l) 
 
 (! < Kg < k ) 
 
 N. = Number of Input patterns to examine the failed function f, t . 
 
 This number is known from E in Error Table. 
 
 (1 < N. < r). l 
 
 - J - 
 
 (T) Execution time for first method. 
 
 T x = p + N x x (a + n x T^) + N^ x N . X T pl 
 
^) Execution time for second method. 
 
 T 2 = p+rx(a + nx T^) + N. x T m + N^ x T p2 
 
 3) Execution time for third method. 
 
 T 3 = P+rx(a + nx T^) + N.. x T p3 
 
 The execution time depends upon N„, N., T .. , T „, T „ from above formulas. 
 
 £ 3 pi p2' p3 
 
 Assume that T n ~ T _ ~ T „, it is clear that the method (T n ) is the most 
 pi p2 p3' V 
 
 inefficient. If N„ > N. (which is usually true), then the third method 
 
 ill J 
 
 (T~) is the most efficient. It should he noted that each execution time 
 
 depends upon T nJ) T _, T _, if T - £ T n , T / T _ and T _ / T _ . 
 pi' p2' p3 pi ' p2' p2 ' p3 P3 Pi 
 
 We should choose carefully a test identification method with the 
 
 Automatic Test Equipment to investigate the execution time of each program 
 
 step and the relations between total input patterns for testing, total 
 
 possible failures and total output pins on a logic card. 
 
h9 
 
 k. TEST DICTIONARY EDITING PROGRAM 
 
 The purpose of the Test Dictionary Editing Program is to analyze 
 information generated by the Card Test Generator System and to edit test 
 dictionaries for failure identification. 
 
 k.l Performance of Test Dictionary Editing Program 
 
 The total system with the Card Test Generator System and the Test 
 Dictionary Editing Program integrated is shown in Figure k.l. A Logic 
 Simulator has been developed so that the designer can check and debug his 
 logic design and can exercise test programs. 
 
 The main purpose of the Card Test Generator is to generate a set 
 of input patterns for detecting circuit failures on printed circuit boards. 
 
 In the Card Test Generator, pseudo-random patterns are used for 
 test generation to detect all possible distinguishable failures, as men- 
 tioned in the previous section. 
 
 Since a set of test patterns is generated by the Card Test 
 Generator only for failure detection, an Error Table to identify failures 
 is not completed in this step. To complete the Error Table, the fault 
 simulation as a part of the Card Test Generator is run again with respect 
 to the given test patterns previously. 
 
 The purpose of the Translator is to translate data from Card Test 
 Generator System formats into input data for test equipment. 
 
 The Test Dictionary Editing Program was developed to generate 
 test dictionaries for failure identification using the information generated 
 by the Card Test Generator System. This program also analyzes the indis- 
 tinguishability of failures. 
 
50 
 
 Logic 
 Simulator 
 
 Card 
 Test 
 Generator 
 
 Translator 
 
 Wiring 
 
 information 
 
 input 
 
 Test Dictionary 
 
 Editing 
 
 Program 
 
 Figure k.l Test Generator System 
 
51 
 
 k.2 Brief Description of Test Dictionary Editing Program 
 
 The Test Dictionary Editing Program consists of five major programs: 
 Control Program, Pre-processing Program, Error Table Sorting Program, Test 
 Dictionary Generator Program and Indistinguishable Failure Selecting Program. 
 The flow of this system is shown in Figure k.2. 
 
 U.2.1 Control Program 
 
 This program controls the other four programs. If the Test 
 Dictionary Editing Program is for any reason stopped in mid- run, we can not 
 recognize which programs of the four have already been completed. The 
 Control Program takes care of this condition and determines which program 
 should run again. Normally, the four programs run as shown in Figure k.2. 
 The Control Program checks if the four programs have already been completed. 
 If they have been, it terminates the computer run. Otherwise, it calls 
 the uncompleted program again. Usually, we can control the Test Dictionary 
 Editing Program by executing the Control Program. 
 
 U.2.2 Pre-processing Program 
 
 The Pre-processing Program reads the files generated by the Card 
 Test Generator System and changes the formats of these files for efficient 
 Error Table sorting and Test Dictionary Editing. The data flow of this 
 program is shown in Figure k.2. 
 
 This program handles the following nine input files: 
 (i) <board name>/ADILSxx 
 
 This is the table of DIL type vs. DIL name, 
 (ii) <board name>/AEQ,VFxx 
 
 This is the equivalent failure mode table. Equivalent 
 
52 
 
 Information 
 
 ^generated by the 
 
 iCard Test Generator 
 System 
 
 > 
 
 Pre-processing 
 Program 
 
 / 
 
 / 
 
 / 
 
 / 
 I 
 
 I 
 
 Control 
 Program 
 
 / 
 
 * 
 
 Error Table 
 Sorting Program 
 
 Test Dictionary 
 Generator Program 
 
 V 
 
 Test 
 Dictionaries 
 
 Indi stingui shable 
 Failure Selecting 
 Program 
 
 /Information 
 I for each 
 \ Failure 
 
 Figure k.2 Test Dictionary Editing Program 
 
53 
 
 failures, which are rejected in the Card Test Generator 
 System, are recorded in this table, 
 (iii) <board name>/ELSTFAY 
 
 This is a list of failures which have been detected through 
 use of the Card Test Generator System, 
 (iv) <board name>/lSSRTxx 
 
 This is the table of the actual pin name vs. subscript 
 number to be used in the Card Test Generator System, 
 (v) <board name>/EPARAMS 
 
 This is the list of parameters which are used in this 
 program, 
 (vi) <board name>/ETABLE 
 
 This is the Completed Error Table which was discussed in 
 Chapter 2. 
 (vii) <board name>/EXCLVOR 
 
 This is the Pin Level Error Table which was discussed in 
 Chapter 2. 
 (viii) HISTORY/ <board name> 
 
 This contains run number information for updating and 
 maintaining files, 
 (ix) CUCTTRS/PINASIN 
 
 This is the table of CU adapter pin vs. the actual pin name. 
 In above nine files, <board name>/ETABLE and <board name>/EXCLVOR 
 files are the essential files for test generation. These two files are 
 described in detail as follows: 
 
5k 
 
 (a) <board name>/ ETABLE. (Completed Error Table). 
 
 Record size of this file is determined by the maximum of three 
 quantities, the number of inputs, the number of outputs, and the number of 
 Flip-Flop's on a card. Usually the number of failures are greater than 
 these three numbers, therefore the first part of ETABLE could be divided 
 into many records depending upon the number of failures. 
 
 The ETABLE arrays are shown in Figure k.3> Assume that input 
 pattern No. 2 is inserted into card to simulate failure No. 3* If there 
 exists a difference between the output without any failure and the output 
 with failure No. 3> then the entry of the column 2 and the row 3 in the 
 ETABLE array is a 1, otherwise it is a 0. The second record is the Input 
 Pattern Table which contains the input test patterns. The third record 
 is the Output Pattern Table containing the correct output patterns asso- 
 ciated with the input test patterns. The fourth record contains informa- 
 tion about the state of each flip-flop on the card at the beginning of 
 each test. 
 
 (b) <board name>/EXCLV0R (Pin Level Error Table). 
 
 The EXCLVOR table contains the failure identification informa- 
 tion at the output pin level. By applying the exclusive-or operation 
 between the correct output pattern and the incorrect output pattern, any 
 incorrect output pin signal will appear as a 1 and a correct output pin 
 signal as a 0. To conserve file space, EXCLVOR tables are constructed 
 only for detected failures, i.e., only for non-zero rows of ETABLE in the 
 recorded file. 
 
 These two files, (ETABLE and EXCLVOR), are the main input file 
 for the dictionary generator Pre-processing Program. Files (i), (ii), 
 (iii), (iv), (v), (viii) and (ix) are read for preprocessing as follows: 
 
55 
 
 Number of tests in first step 
 
 The 
 group 
 
 of 
 First 
 
 Step 
 
 Second 
 Step 
 
 A Information 
 for Flip -Flop 
 in Card. 
 
 Figure k,3 <board name>/ETABLE File 
 
56 
 
 Failure 
 
 No 
 
 
 1 
 2 
 
 3 
 h 
 
 2_ 
 
 
 
 1 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 k5 k6 hi 
 
 o 
 
 l 
 
 
 
 1 
 
 
 
 r T n 
 
 
 
 © 
 
 
 
 1 
 
 1 L o ! l 
 
 Result of failure detection 
 corresponding to input 
 pattern No. 2. 
 
 Size 
 
 Equal 
 
 to 
 
 No. 
 
 of 
 
 Failures 
 
 Figure h.k The Contents of the Completed Error Table Array 
 
The <board name>/ETAlLE file is read using the parameters 
 recorded in the <board name>/EP ARAMS file. The <board name>/EXCLVOR file 
 contains the more detailed detection information. The <board name>/ETABLE 
 file is used only as an index to find the appropriate <board name>/EXCLVOR 
 record which contains the relationship between failures and pin level 
 error indications. To find indistinguishable failures at the completed 
 error table level, we compose the table for failures vs. input patterns 
 as shown in Figure k.5 by reformating the entries of ETABLE. This table 
 is written on disk as the <board name>/EWDSORT file and the file is read 
 by the Error Table Sorting Program described in the next section. 
 
 Next, <board name>/EXCLVOR file is analyzed for the test dic- 
 tionary. The <board name>/EXCLVOR file has tables for all failures; 
 each table gives the relationship between test input patterns in columns 
 and pin names in rows as discussed in Chapter 2. If entry (j f , m') of 
 the table of failed function f „, shows 1, the failed function f „ r can be 
 detected by input pattern A., at pin p ,. These three data become one 
 triplet (j ', m, j> V ) of test dictionary. These triplets are written on 
 disk as <board name>/OGLSORT file. This file will be used to edit test 
 dictionaries. After generating these triplets, the test dictionary 
 generator program is called and this program terminates. 
 
 U.2.3 Test Dictionary Generator Program 
 
 The Test Dictionary Generator Program generates the three 
 test dictionaries discussed in Chapter 3 by sorting the triplets gen- 
 erated by the Pre-processing Program. 
 
 The input information for this program is the triplets file 
 (<board name>/OGLSORT) . The output information is three dictionaries, 
 
58 
 
 n words 
 
 U7 bits 
 
 i+7 bits 
 
 hrj bits 
 
 Figure k.5 <board name>/EWDSORT File 
 
59 
 [j,m, i] dictionary, [<0,m,j] dictionary, and [i,j,m] dictionary, constructed 
 
 J 
 
 T 
 by sorting the triplets in the order A., p , and f „, the order f , p , and 
 
 T T 
 
 A. and the order f ., A., and p respectively. Examples of a [j,m, £] dic- 
 
 tionary and a [i,m,j] dictionary are shown in Appendix. 
 
 k.2.k Error Table Sorting Program 
 
 The purpose of the Error Table Sorting Program is to find pseudo- 
 indistinguishable failures in the <board name>/EWDSORT file by sorting the 
 entries of the file. If all error patterns are different from each other, 
 then all failures can be distinguished. However, if the same pattern 
 appears for more than one failure, these failures are indistinguishable 
 from each other. These pseudo indistinguishable failures will be classi- 
 fied more precisely in the indistinguishable failure selecting program. 
 The output from this program is the sorted error table (<board name>/ 
 SRTDEWD) . 
 
 4.2.5 Indistinguishable Failure Selecting Program 
 
 The purpose of the Indistinguishable Failure Selecting Program 
 is to further attempt to distinguish the pseudo indistinguishable failures 
 found by the Error Table Sorting Program. This distinction is performed by 
 checking the pin outputs in the <board name>/EXCLVOR file. 
 
 If the set of pins at which each of the failures in the pseudo 
 indistinguishable failure set are different, these pseudo indistinguishable 
 failures are distinguishable from each other. If the set of pins at which 
 some failures appear is not different from the set of pins for other 
 failures, these failures are indistinguishable from each other by the 
 
6o 
 
 <board name>/EXCLV0R file. Information about these indistinguishable 
 failures (<board name>/lNDFLTL) will be used as additional data in the 
 test dictionaries to report if the selected failure is indistinguishable 
 from other failures. 
 
61 
 
 5- CONCLUSION 
 
 A test dictionary generation method has been presented and 
 failure analysis and identification methods by use of test dictionaries have 
 been discussed. The files generated by the Card Test Generator System are 
 used as the fundamental data for failure analysis. Usually failures are 
 analyzed using the Error Table, but we also used the output pin information 
 on the Pin Level Error Table to improve the resolution of failure identifi- 
 cation. 
 
 We proposed three methods for failure identification procedures 
 by use of test dictionaries and evaluated these methods. One of these 
 methods may be selected according to the figure of merit such as the size 
 of possible failures in the card for testing and the size of input patterns 
 to be generated. 
 
62 
 
 REFERENCES 
 
 [1] Kauz, William H. , "Fault Testing and Diagnosis in Combinational 
 
 Digital Circuits", IEEE Transactions on Electronic Computers, 
 April 1965, PP. 352-366. 
 
 [2] Chang, Herbert Y., "An Algorithm for Selecting an Optimum Set of 
 Diagnostic Tests", IEEE Transactions on Electronic Computers, 
 October 1965, PP- 706-711. 
 
 [3] Tanaka, Chiyozi, "Parallel Simulation of Digital Systems", ILLIAC IV 
 Document No. 211, Department of Computer Science, University of 
 Illinois at Urbana-Champaign, Urbana, Illinois, April 1970* 
 
 [k] Chang, H. Y. and Thomis, W. , "Methods of Interpreting Diagnostic 
 
 Data for Locating Faults in Digital Machines", The Bell System 
 Technical Journal, February 1967* PP« 289- 317 • 
 
 [5] Tanaka, Chiyozi, Abel, Luther C, and Naemura, Kenji, "Parallel 
 
 Logic Simulator and Its Use for Test Generation", Workshop on 
 Reliability and Maintainability of Computer Systems at Lake of 
 the Ozarks (Diagnostic Group Memorandum (DM-03^-)), October 1969< 
 
63 
 
 APPENDIX 
 
6k 
 
 CARD fcAMElQTHESIS* TEST REVISION! # DIAGRAM*! 
 
 *** PACE .1 ** 
 
 » GENERATED ON 5/27/70 
 
 TEST DICTIONARY 
 CARD NAME! OTHESIS 
 
65 
 
 •♦♦ PAGE 2 •« 
 
 CARD NAHf |CTHISIS# TEST REVISIONi t DIAGRAM*! . » GEfctRATED ON 5/27/70 
 
 INPUT DATA TABLE NUMBER OF GlOCKSl 1. 
 
 TEST NO. 
 
 000000000000000 
 
 0000000 0111111 
 
 NO. CON PIN i 2 3 4 5 ,fc 7 8 9 1 2 3 4 5 
 
 1 PI All 1 1 1 1 1 1 1 1 1 1 
 
 01000 1100010000 
 010000111011001 
 
 0100001 10000001 
 010000000000000 
 001000010000000 
 001101110100111 
 001101110100111 
 001101110100111 
 001000010000000 
 000100100000000 
 00010C100000000 
 000010001100111 
 000010000100111 
 000001011011001 
 
 2 
 
 Bl 
 
 A15 
 
 3 
 
 PI 
 
 A17 
 
 4 
 
 61 
 
 A21 
 
 5 
 
 PI 
 
 A23 
 
 6 
 
 PI 
 
 A27 
 
 7 
 
 Pi 
 
 A33 
 
 8 . 
 
 PI 
 
 A35 
 
 9 
 
 PI 
 
 A03 
 
 10 
 
 ei 
 
 B18 
 
 11 
 
 pi 
 
 P20 
 
 12 
 
 61 
 
 B30 
 
 13 
 
 pi 
 
 R38 
 
 14 
 
 Fl 
 
 C39 
 
 15 
 
 PI 
 
 C03 
 
66 
 
 CARD KAHt toTHE S!S# TEST REVISION! » DIAGRAM*! 
 
 •** PAGE 3 ** 
 
 » gEmcRATEO ON 5/27/70 
 
 THE SORTED LIST NO.l 
 
67 
 
 *♦* PAGE 4 *« 
 
 CARD KAHEiOTH£SIS» TEST REVISIONI * DIAGRAM*! $ GENERATED ON 5/27/70 
 
 FAILURE MODE REMARKS 
 
 TEST 
 
 PATTERN* 
 
 OUTPUT 
 PIN I 
 
 GOOO 
 OUTPUT 
 
 1B06 
 1A29 
 1C05 
 1D32 
 
 H4 
 HA 
 HA 
 Kl 
 
 05 H 
 02 H 
 01 L 
 05 H 
 
 lbOfl 
 
 1626 
 
 1A29 
 103? 
 
 M 
 
 H4 05 H 
 
 Kl 41 H 
 
 Kl 41 H 
 
 H4 01 L 
 
 Kl 05 H 
 
 1B08 
 1626 
 1A29 
 
 M 
 
 1C05 
 1032 
 1C33 
 
 H4 
 Kl 
 
 H4 
 Kl 
 
 H4 
 
 Kl 
 
 Kl 
 
 01 L 
 04 L 
 
 02 H 
 04 L 
 
 01 L 
 13 L 
 
 04 I 
 
 lboe 
 
 1A29 
 1C05 
 
 H4 
 H4 
 H4 
 
 01 I 
 
 02 H 
 01 I 
 
 lfcOB 
 1B26 
 U29 
 
 H4 05 H 
 Kl 16 L 
 Kl 16 L 
 
 TEST NO. 
 
68 
 
 CARD NAKiOTHtSIS' TEST REVISION! » OlAGRAMIl 
 
 TEST 
 PATTERN* 
 
 OUTPUT 
 PlN f 
 
 6000 
 OUTPUT 
 
 FAILURE MODE 
 
 *** PAGE 5 •• 
 GENERATED ON 5/27/70 
 REMARKS 
 
 1C05 
 
 H4 
 
 01 L 
 
 6 1*00 
 
 6 1626 
 
 6 1A29 
 
 6 1C05 
 
 6 1032 
 
 HA 01 L 
 
 0. Kl 41 H 
 
 C Kl 41 H 
 
 H4 01 L 
 
 Kl 05 H 
 
 7 1000 
 7 1B26 
 7 1A29 
 
 H4 01 L 
 
 Kl 41 H 
 
 1 Kl 41 M 
 
 e lgoe 
 
 6 1B26 
 6 1*29 
 
 1032 
 1C33 
 
 
 
 H4 
 
 01 I 
 
 I 
 
 Kl 
 
 04 I 
 
 
 
 M4 
 
 02 H 
 
 H 
 
 Kl 
 
 04 L 
 
 
 
 Kl 
 
 13 L 
 
 
 
 Kl 
 
 04 L 
 
 lBoe 
 
 K2 02 L 
 
 10 
 
 ldoe 
 
 
 
 H4 
 
 01 L 
 
 10 
 
 1B26 
 
 
 
 Kl 
 
 16 L 
 
 10 
 
 1A29 
 
 
 
 Kl 
 
 10 L 
 
 10 
 
 1C05 
 
 
 
 H4 
 
 01 L 
 
 TrST NO. 11 
 
69 
 
 *** PAGE 6 *« 
 
 CARD NAHEiOTHESlS* TEST REVISION! » DIAGRAMS* $ GENERATED ON 5/27/70 
 
 FAILURE MODE REMARKS 
 
 TEST 
 
 PATTERN* 
 
 output 
 
 PlN I 
 
 GOOD 
 OUTPUT 
 
 11 
 11 
 11 
 11 
 
 1B08 
 1B26 
 1A29 
 1032 
 
 K2 02 L 
 Kl 41 H 
 Kl 41 H 
 
 Kl 
 K3 
 
 OS H 
 04 H 
 
 12 
 
 1A29 
 
 H4 
 
 02 K 
 
 13 
 13 
 13 
 13 
 
 1608 
 1B26 
 1A29 
 1C05 
 
 H4 01 L 
 
 Kl 16 L 
 
 Kl 16 L 
 
 H4 01 L 
 
 14 
 14 
 14 
 14 
 
 lyoe 
 1B26 
 U29 
 1C05 
 
 H4 01 L 
 
 Kl 16 L 
 
 Kl 16 L 
 
 H4 01 L 
 
 15 
 
 15 
 15 
 
 iboe 
 
 M 
 
 lb26 
 1A29 
 
 H4 
 K3 
 
 Kl 
 
 Kl 
 
 01 L 
 05 H 
 
 16 L 
 
 16 L 
 
 TEST NO. 15 
 
70 
 
 CARD NAMEIOTHLSIS* TEST REVISION! * OIAGRAMM 
 
 *** PAGE 7 * 
 $ GENERATED ON 5/27/7C 
 
 THE SORTEO LIST NO. 2 
 
71 
 
 *** PAGE e ** 
 
 CARD NAMElOTMESIS* TEST REV1SIONI i DIAGRAM*! , GENERATED ON 5/27/70 
 
 FAILURE POOE OUTPUT TEST GOOO REMARKS 
 
 PIN • PATTERN * OUTPUT 
 
 MA 02 M U29 1 
 
 W 3 M 
 
 « 4 w 
 
 m 5 m 
 
 • 12 » 
 
 Hfl 05 h lpoe 1 
 
 " 2 
 
 " 5 
 
 H4 01 L HOB 3 
 
 « 4 » 
 
 » 6 " 
 
 » y w 
 
 « 6 " 
 
 N 10 * 
 
 " 13 " 
 
 " 14 « 
 
 m J5 w 
 
 H4 01 L 1C05 1 
 
 " 3 " 
 
 " 4 • 
 
 " 5 
 
 " 6 
 
 " 10 
 
 " 13 
 
 » 1« 
 
 H4 01 I 1032 
 
 Kl 05 H 1D32 1 
 
 m 2 " 
 
 6 
 11 
 
 Kl «1 H 1826 2 
 
 " 6 " 
 
 • ■ H ft 
 
 FAILURE MODE NAME l Kl 41 H 
 
72 
 
 FAILURE. MOPE 
 Kl 41 H 
 
 
 
 
 ■** PAGE 9 •* 
 
 ONI > DIAGRAMII 
 
 i GENERATED ON 5/27/70 
 
 OUTPUT 
 PIN * 
 
 TEST 
 
 PATTERN $ 
 
 GOOD 
 OUTPUT 
 
 REMARKS 
 
 1*29 
 
 m 
 m 
 
 M 
 
 2 
 
 6 
 
 7 
 
 11 
 
 
 
 M 
 R 
 
 • 
 
 Kl 04 L 1P26 3 
 
 » 8 " 
 
 Kl 04 L U29 3 
 
 « 8 " 
 
 Kl 04 L 1C33 3 
 
 " 8 " 
 
 Kl 13 L 1D32 3 
 
 n 
 
 6 
 
 Kl 16 I 1P26 5 
 
 m 10 " 
 
 " 13 " 
 
 m 14 « 
 
 13 
 
 * 
 
 Kl 16 L 1*29 5 
 
 " 10 • 
 
 " 13 « 
 
 * 14 " 
 
 m j5 n 
 
 K2 02 L ie08 9 1 
 
 " 11 » 
 
 K3 04 h lp32 11 
 
 K3 05 H le08 15 
 
 FAILURE MOOT NAME I K3 05 H 
 
UNCLASSIFIED 
 
 Security Classification 
 
 DOCUMENT CONTROL DATA R&D 
 
 (SacuHty claamltlcatlon o( title, body ol aaetracl and Interning annotation aniat ba wittf^ whan the overall report le elm filled) 
 
 originating AC ti vi T v 'Corporate author) 
 
 Center for Advanced Computation 
 University of Illinois at Urbana-Champaign 
 Urbana, Illinois 6l801 
 
 la. KIPOKT IECUKITV CLAillFIC »TIOU 
 
 UNCLASSIFIED 
 
 26. CROUP 
 
 REPORT TITLt 
 
 Diagnosis of Printed Circuit Cards on a Programmable Test Equipment 
 
 I. DESCRIPTIVE NOTU (Type or raport and inclusive daft) 
 
 Research Tteport. 
 
 |. au T mo HIS 1 (Flrat naata, middle Initial, laal nama) 
 
 Masayuki Inagaki 
 
 REPORT DATE 
 
 July 30, 1970 
 
 7e\ TOTAL NO. OF PACES 
 
 80 
 
 76. NO. OF MEF1 
 
 la. CONTRACT OR GRANT NO. 
 
 USAF 30-(602)-4lM 
 
 6. PROJECT NO. 
 
 ARPA Order 788 
 
 •a. ORIGINATOR'S REPORT NUMBER!*) 
 
 ILLIAC IV Document No. 228 
 
 •6. OTHER REPORT NO(S> (Any othar number* char may ba aaalgned 
 thla report ) 
 
 DCS Report No. 411 
 
 10. DISTRIBUTION STATEMENT 
 
 Copies may be requested from the address given in (l) above. 
 
 II. SUPPLEMENTARY NOTES 
 
 None 
 
 12. SPONSORING MILITARY ACTIVITY 
 
 Rome Air Development Center 
 Griffiss Air Force Base 
 Rome, New York 13440 
 
 3. ABSTRACT 
 
 This paper discusses methods of editing test dictionaries using 
 the results of printed circuit card fault simulation, identifying failures 
 in a printed circuit card. To identify a failure in a card under test, 
 a generalized automatic test equipment is introduced and three identification 
 methods are presented and evaluated. A program for generating test 
 dictionaries was written in Extended ALGOL for the Burroughs B5500 computer 
 and used for test dectionary generation for the ILLIAC IV PE and CU cards 
 and is also described in this paper. 
 
 )D .'•'r..1473 
 
 UNCLASSIFIED 
 
 Security Classification 
 
UNCLASSIFIED 
 
 Security Classification 
 
 KEY WORDS 
 
 Hardware Diagnostics 
 Design Automation 
 
 HOLE I WT 
 
 ROUE WT 
 
 UNCLASSIFIED 
 
 Security Classification 
 
KPfc 
 
 i\^