H ■ ■ LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 I£6r riOcieO-170 cop.SL The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN NOV 15 1973 L161 — O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/memorysearchalgo165lyon no. 1^5 DIGITAL COMPUTER LABORATORY cop. 3 f UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT NO. I65 MEMORY SEARCH ALGORITHMS FOR AN ITERATIVE PROCESSOR by Stephen Mark Lyons July 17, 196^ (This work is being submitted in partial fulfillment of the requirements for the degree of Master of Science.) 7 iii Dp. J ACKNOWLEDGMENT The author wishes to thank Dr. Gemot Metze for his supervision of the preparation of this paper, and for his patience, He also gratefully acknowledges the invaluable assistance given by Dr. So R. Ray. TABLE OF CONTENTS iv Page SUMMARY ..•*•...••.•••...... v CHAPTER I. INTRODUCTION TO THE INVESTIGATION. ........... 1 CHAPTER II. DISCUSSION OF THE TRANSFER MEMORY AND THE ITERATIVE ARRAY 3 CHAPTER III. DERIVATION AND DISCUSSION OF THE SEARCH ALGORITHMS ... 8 CHAPTER IV. CONCLUSIONS. . ..... 28 BIBLIOGRAPHY . 30 APPENDIX 31 SUMMARY Three search algorithms are derived for the iterative processor of the Illinois Pattern Recognition Computer: a between limits search, a minimum search and an ordered retrieval. The processor is compared to another system in its ability to perform ordered retrieval. These algorithms represent an investigation into possible uses for the logic existing in the iterative processor not previously explored, CHAPTER I INTRODUCTION TO THE INVESTIGATION A memory search is an operation conducted on all or part of the contents of a memory in order to determine the information contained in the memory. To execute an effective memory search it is necessary to process the memory content with a parallel operation. This can he accomplished with an iterative processor, which is a highly repetitive group of identical modules designed to operate in parallel. This paper is concerned with the construction of three memory search algorithms for the iterative processor of the Illinois Pattern Recognition Computer [Illiac III]: a between limits search, a minimum search (and its dual, maximum search) and an ordered retrieval. The computer is designed specifically for visual pattern processing [1] but the extensive logic built into the iterative processor warrants this investigation into other possible uses for the processor. The iterative processor or "Iterative Array" is part of the Pattern Articulation Unit of the Illiac III computer (Fig. l) . Connected to the processor is a small matrix memroy called the Transfer Memory. This is the memory on which the searches will be conducted. The memory searches investigated are not chosen specifically to take advantage of certain proper- ties of the memory or the processor but on the basis of their recognized usefulness . A between limits search (a search for all memory words between prescribed upper and lower arithmetic bounds) has many applications, such as information retrieval and visual pattern processing. In information retrieval * Numbers in brackets refer to entries in the Bibliography this search is needed where the upper and lower arithmetic bounds on words in the memory correspond to coded information in a continuous, bounded range. For example, if all information in the memory concerned Transactions of the IEEE , all binary numbers between 10 and 100 might correspond to issues of the Transactions of the P.G.E.C. Thus, a search for all words with arithmetic value between the limits 10 and 100 would, perhaps, yield information con- cerning the location of the PGEC issues. In visual pattern processing the between limits search is helpful in data reduction [1]. The minimum search is a search for the arithmetic minimum of the words contained in memory. The search derived in this paper is applicable to words of any list length and is meant as an extension of the machine's ability to perform such a search. A minimum search already exists for three bit binary numbers [2]. However, the approach to the problem was neces- sarily quite different in the case of longer binary words. An extension of the minimum search yields a search by which all words are retrieved from memory in order corresponding to their arithmetic value--an ordered retrieval. Due to the current interest in ordered retrieval, caused by the application to business and information files [3], a study is made of the adaptation of the iterative processor to this search. The results of this investigation are then compared to a system designed specifically for ordered retrieval [3]« The iterative processor and associated memory are discussed in Chapter II. The three search algorithms are derived and explored in detail in Chapter III. In the last chapter, Chapter IV, concluding remarks are made and possible extensions of the investigation are discussed. CHAPTER II DISCUSSION OF THE TRANSFER MEMORY AND THE ITERATIVE ARRAY The Transfer Memory [Figs. 1,2] is a random access, linear select core memory of ^8 x 102^ bits arranged for read or write operations either by long, 102^ bit words (lying in the plane orthogonal to the Z axis) or short i+-8 bit (Z axis) words. [Fig. 1] Logically connected to the Transfer Memory is an iterative processor called the Iterative Array [Fig. 53* The Iterative Array is designed to process the long, 102^ bit, plane words parallel by word. That is, consider- ing the Z axis words, it is able to process, simultaneously, the same bit position of all 102^1- Z axis (short) words in parallel. This 102^ bit parallel processor is composed of nine horizontal registers labeled M and S, through So in Fig. 3 (shown for one module). These registers are interconnected to provide logical functions of vertically- related cells (i.e., bits of the same Z words). The output to and the input from the eight neighbor modules is provided for pattern recognition processes. Since the nearest neighbor logic is not germane to the development of this paper, it will not be discussed. Note also that all data passing between the Iterative Array and the Transfer Memory must be transferred via the M register [Fig. 2]. By controlling the gating of the 0UTBUS [Fig. 3] the following functions of nine variables or any subset of the variables can be formed on the 0UTBUS: f = M • S • S . . . Sg ' means logical AND f SB f 2 1 f = M v S, v S. . . . v Sn v means logical OR 3 12 o Either of two functions formed on the INBUS may "be gated into one or more of the registers : = M s, (y OUTBUS.) i=0 g 2 = g l There is one restriction on the input, however. A function cannot be gated into a register that is also an argument of the function. As an example: So v S could not be an input to either register S or So- Connected to the M register is an encoder [Fig. 2]. It consists of combinational circuitry which delivers either a ten-bit binary number equal to the minimum coordinate (bit number) of the M register which contains "0", or a one-bit signal ("SOME MARK") indicating the existence of at least one "0" in the M register. Zeros may be interpreted as interrogation responses as will be shown. After the encoder has addressed a position of the M register containing a zero, that zero may be reset to one by means of a MARK operation which then allows the encoder to proceed to the next zero. * The formation of any INBUS or OUTBUS function takes 0-5 microsecond. (See [2].) PATTERN ARTICULATION UNIT ARITHMETIC COMPUTER MAIN CONTROL TRANSFER MEMORY (SHORT OR Z WORDS) MAIN CORE MEMORIES 48 I BITS PAU CONTROL i i TTT 1024 BITS i i -Z WORD -PLANE" WORD (LONG OR PLANAR WORDS) M REGISTER S8 SI ITERATIVE ARRAY (2-d LOGICAL PROCESSOR) PHOTOGRAPHIC SCANNERS (I/O) I L J JAQ Jg S Y S T EM FIG. 1 m — m u — wv> I m =% _si?-~ jz: i£3 Isf \LL nil Ti r~i — r i S rr 11$* ' I u. o UJ < o m Id J- o < V) s en 5 tr on < UJ > »- < tr ui u. o UJ _J Q O 2 UJ 2 w 00 o UJ o w m =J tZODOOO o z CHAPTER III DERIVATION AND DISCUSSION OF THE SEARCH ALGORITHMS Between Limits Search An interrogation of the Transfer Memory by the Iterative Array may be performed to find all words in the memory between specified upper and lower arithmetic bounds. The words describing the upper and lower arithmetic bounds are contained in the arithmetic computer [Fig. 1] where they are processed to determine the search executed by the Iterative Array. A between limits search of the memory contents for all words K such that A > K > B, for any two words A and B, will be constructed in two parts. First an algorithm is formed to obtain all words K > B. This information will be stored and used as a mask for the second search--that of finding all words K < A. That is, the second search is executed only on those words passing the first search. An objective in the construction of such algorithms is that the Transfer Memory not be used to store intermediate information obtained in the search, because of the time factor involved in going from the Iterative 2 Array to the Transfer Memory. For this reason registers So and S are used to store information derived from the logical processing of information con- tained in the other registers. 3 The rows of the Transfer Memory will be transferred in groups of six to the Iterative Array, starting at the most significant end (the end of A word will always refer to one of the 102 4, short k8 bit ("Z axis") words in the Transfer Memory. However, any search may be conducted on only a specific part (or "Key") of the Z axis words. P _ A transfer of a word between the Iterative Array and the Transfer Memory is performed in 2usec--four times as long as a formation of a function in the Iterative Array. A row consists of 102^ bits, one bit from the same bit position of each of the Z axis words. A row is, therefore, one of the previously mentioned "lon,g" words. greatest arithmetic -value) of the words stored. Let the i th row be designated R.. The word B, B = b l b 2 b 5 -\ ■■■\- is made available to the arithmetic computer. The processing of the rows in memory "by the Iterative Array is determined by the bit value of B in the following manner: (1) If b. = 1 (S ? v R A ) Sg — «* M — * Sq (2) If b. =0 s ' l (R.) Sg s, S ? — > M — ^ S ? (3) Repeat steps (l) and (2) for all remaining rows incrementing i on each pass. (k) At the end of the operation So — > S Set S fi to 1. All words greater than or equal to B correspond to zeros in S . Now the word A, A = a. a a . . . a. . . . a , 12 3 1 n' is made available to the arithmetic computer so that a search can be conducted on all words corresponding to zeros in S to find those less than or equal to A. The search is accomplished with the following algorithm: (1) If a. = Sg(S v R j _) — > M — > S T (2) If a. = 1 (R.) Sg v S ? — -* M — * Sg 10 (3) Repeat steps (l) and (2) for all remaining rows incrementing i on each pass. (k) S, — * M The words indicated by zeros in M at step (k) are the words that lie between the limits A and B. The algorithms used in each part of the search are duals so an analysis of one will be sufficient. Consider the search for K > B. Register S 7 is designated to store ones corresponding only to words that have been found to be greater than B and register So to store zeros corresponding only to those words previously determined to be less than B. If b. is equal to one, then no information is obtained as to words greater than B but any word having a zero in this position, that has not previously been determined greater than B, has now failed. This information must be stored in Sq. To propagate ones in positions of words previously determined greater than B, the logical sum of the row being tested and S is taken. If the result derived from this OR operation and Sn are combined in a logical product, only zeros corresponding to failures are formed [step (l)]- When b. is equal to zero all ones in the ith row, corresponding to words that have not previously failed, are greater than B. To propagate failures, the logical AND of this row and So is taken. The result of this logical product and register S are combined in a logical sum to give ones in the positions, in S , corresponding to words greater than B--the desired result. To show that a word greater than B is always recorded correctly, assume that a zero is recorded in So corresponding to a word greater than B. This could only happen at Step (l) ' which implies that the word had not previously passed (or else a one would have been recorded in S , corresponding to its position) and that when b. = 1, there is a zero in the words i th position. Therefore, the word would be less than B--a contradiction. 11 A similar argument holds for all words less than B. Assume that S contains a one corresponding to a word less than B. This situation could only exist after the execution of step (2) and would, therefore, mean that the word had not previously failed (or else a zero would be recorded in the corresponding position in So) and that when b. = there is a one in the word'-s ith hit position. Hence, the word would be greater than B, the desired contradiction. The binary content of the words, A and B, determine the function formed by the Iterative Array. These two words are processed by an arithmetic computer [Fig. 1] which in turn gives the appropriate commands to the Iterative Array and the Transfer Memory. It is assumed that the time involved in this interrogation by the arithmetic computer is comparable to the time it takes for the execution of a command from the arithmetic computer by the Iterative Array or Transfer Memory. It is also assumed that interrogation and execution can be carried on simultaneously. Considering, then, only the time involved in the transfer of rows between the memory and the iterative processor and the time it takes to form a logic function, the calculation of the execution time for the between limits search is simple. Not including the retrieval of all words found in the search, the execution of the algorithm on k-Q bit words takes 289 p.sec. (See Appendix.) Maximum and Minimum Search The search for the minimum or maximum word stored in memory requires minor changes in the encoder. As mentioned on page k the encoder, in its present form, gives only a "SOME MARK" signal indicating the existence of at least one "0" in the M register* As a response to a minimum or maximum interrogation, it is desired to have three distinct signals with regard to (IV- 1 12 the number of "0" ! s in the M register: (l) a "NO MARK" signal (simply the logical negation of the presently existing "SOME MARK" signal), (2) a "ONE MARK" signal (given when there exists only one "0" in the M register) and (3) a "PLURALITY" signal (given when there are more than one "0" in the M register). The existing equipment can easily be altered to give these 1 responses. The words in the memory are divided into blocks of seven bits each, Starting at the most significant end of the words in memory, R is trans- ferred to S , R„ to S/- ; etc. Beginning with S , all registers are operated 2 upon in the following manner. To Determine the Minimum Word (1) Transfer to So "0" ! s corresponding to words being searched-- all other positions contain "l ni s„ (2) Set N = 7 (3) Sg v S n — > M (a) If only one mark read out as the minimum word. Stop. (b ) If no marks go to step (k) (c) If more than one mark; M — -> So go to step (k) (k) Decrease n by 1 (a) If n = transfer next section of the Transfer Memory to the Iterative Array and go to step (2). If there are no more sections: Sg— > M Read out all words corresponding to "0" in M. (b) If n/0 go to step (3). Approximately 6k AND circuits in addition to existing logic. p " All commands, etc., would be furnished by an arithmetic computer as in the case of the between limits search. 13 To De termine the Maximum Word (1) Transfer to So "l"'s corresponding to words being searched-- all other positions contain "0"'s (2) Set n = 7 (a) If only one mark read out as maximum word. Stop. (b) If no marks go to step (k) (c) If more than one mark: M — •> So go to step (k) (k) Decrease n by 1 (a) If n = transfer next section of the Transfer Memory to the Iterative Array and go to step (2) If there are no more sections: Sn > M Read out all words corresponding to "0" in M. (b) If n f go to step (3) Again the algorithms are duals --as would be expected after a similar development occurred in the previous section for the between limits search. Therefore, a discussion is given only for the minimum search. Initially register So contains "1" ' s corresponding to words in the memory on which the search will not be performed. Such words are "masked" by "l"*s in So. Whenever a word is determined not to be a minimum it will also be masked by a "l" in So. Hence S„ is said to contain the "mask" for the search. The logical sum of So and S [step (3)] propagates the "l"'s contained in So so that these positions will never cause a "ONE MARK* or a "PLURALITY" signal to appear. After the logical sum of So and S has been taken one of three situations will be determined by the Encoder: Ik (1) There is only one "0" in M. This means that only one word has a "0" in row S (of those words still being n ° checked) and is therefore, the minimum, [step (3 a )] (2) There is no "0" in M. This could only mean that all words being checked contain "l"'s in S and no information as to to n the minimum word can be determined. Therefore, the same mask (Sn) is used for the next row. [step (3b)] (3) There is more than one "O" in M. This implies that more than one word and perhaps all words being checked have "0"'s in S o A further check is necessary to determine the minimum n J word. But a new mask may be needed because some of the words being tested up to this point could have "l"'s in this row and, of course, only words with "0"'s in M need be tested further. Therefore, M becomes the new mask, [step (3c)] When the last row of the Transfer Memory has been checked an no minimum word has been found [step (hz)] then there is more than one minimum word and these words correspond to the "0"'s in So. When this occurs the contents of So is transferred to M so that these words may be read out. To show that this method correctly represents minimum words by "0"' s in So (or M) assume the following cases: (l) A word is the minimum word in the Transfer Memory and is being tested but in its corresponding position in So there is a "l". Since So is changed only at step (3c), this would mean the word has a "l" in S when other words have "0"'s. n Hence, it is not a minimum word. This is the desired contradiction. 15 (2) A word is not a minimum but is being searched and at the end of the search its corresponding position in So contains a "0". To be larger than the minimum word, a word must necessarily be "l" in at least one row where the minimum word is zero. At step (jc) a "l" would be transferred to So in the position of the word in question- -again the necessary contradiction. Since the mask in Sp propagates the information about words that have "failed" the search from one seven bit block to the next, there is no chance of a word being retrieved as a minimum word if it has been previously proven not a minimum., The time it takes to complete a maximum or minimum search is within the bounds determined by the "worst case" and the "best case" situations As a "worst case" situation the search would have to be conducted for all k-Q rows of the Transfer Memory while a "best case" situation means the search is completed with the logical operation on the first row. Assuming k-Q bit binary words, the "worst case" would take 170 usee and the "best case" 15 usee. (See Appendix.) Both the worst case and best case would take about 2000 usee to execute with a standard [non-iterative] processor. Ordered R e trieval With very few changes, the minimum or maximum search algorithm may be utilized as an ordered retrieval algorithm. That is, all words may be retrieved from the memory in order corresponding to their arithmetic value. Because of the emphasis given the minimum search in the last section, this algorithm is used to construct an ordered retrieval algorithm by which words 16 are retrieved from memory starting at the minimum word and proceeding in order to the maximum word,, As in the case of the other searches, storing intermediate informa- tion obtained "by this search in the Transfer Memory is to be avoided because of the time involved in transferring information between the memory and the processor. To accomplish this, register S is used as a mask for all words that are not to be tested or have already been retrieved. Thus, when a word is retrieved as a minimum, a "l" is transferred to the corresponding position in S causing the word to be masked for all later searches. So will also contain a mask but it will function as in the minimum search--concerned only with finding a minimum word and not with which words have been retrieved. Instead of dividing the words into blocks of seven bits, blocks of six bits are the maximum possible since S is used as a mask, All specifica- tions on the order of block transfers remain unchanged. Let it again be understood that all execution commands delivered to the Iterative Array and the Transfer Memory originate in the arithmetic computer. The following six steps constitute an ordered retrieval algorithm. (1) Transfer to S "C"'s corresponding to words being searched-- all other positions contain "l"'s. (2) S ? — » Sg (3) Set N = 6 (k) S Q v S n — > M (a) If only one mark go to step (6) (b) If no marks go to step (5) (c) If more than one mark: M — > So, go to step (5) 17 (5) Decrease n "by 1 (a) If n - transfer next block to Iterative Array,, If there are no more blocks go to step (6) (b) If n f go to step (1+) (6) M v S„ — » Sg Sg — > S ? Read out words corresponding to "0"'s in M. Start with first bit block and repeat steps starting at step (3)« Notice that there is only one basic difference between this algorithm and the one for minimum search. This is step (6) which causes a new mask to be formed in S„. All of the "0 ,;: s in M are stored as "l"'s in S^ (and S D ) 7 7 o because these zeros correspond to words to be retrieved. On the next search these positions will be effectively masked so no word will be retrieved more than once. With these positions masked, the search starts again at the most significant end of the words in the memory. This process continues until all words are retrieved (until S contains only "l" 8 s). With such a nondense set of words in the Transfer Memory it is difficult to set upper and lower bounds for the time it takes to complete an ordered retrieval. But as a pessimistic approximation of the "worst case 5 ' situation it is assumed that for each word retrieved the search must be per- formed on every row in the Transfer Memory. As a further approximation it is. assumed that each row entails the formation of a logic function at step v.4c) With these assumptions the time for an ordered retrieval is about 180000 usee. Taking into consideration the probability of two words in the Transfer Memory lift being equal (l in 2 ) the "best case" choice could reasonably be the It is again assumed that the arithmetic computer speed need not be taken into consideration. L8 situation when all words are distinct and determined by the first ten rows of the Transfer Memory. Under this condition the time for an ordered retrieval execution is about 20000 usee. (See Appendix.) Seeber and Lindquist have proposed an associative memory system capable of executing ordered retrieval [3]« I n this system, the processing logic and storage elements are intermingled as opposed to the separation of the Iterative Array and Transfer Memory. Instead of forming a logic function of the rows of the memory, this system uses an interrogation of each row, carried out by a device similar to a ternary counter. The three states of this counter are designated as "M", "0" and "1" . When the counter is in the "M" state no interrogation of the row on which the counter is operating is required. When the counter is in the "0" state the row is searched for binary 0's and when it is in the "l" state a search is made for binary l's. The cycle of the ternary counter is "M" to "1" to "0" and back to M M" . Connected to the memory is a Match Indicator (Ml) which performs essentially the same function as the encoder in that it monitors the responses from the interrogation of the rows by the ternary counter and gives a no match (0), one match (l) or plurality match (P) signal corresponding to the result of the interrogation. Except at the start of the search, when all stages of the ternary counter are set to M, the setting of the ternary counter is a function of the Match Indicator signal. Starting at the most significant end of the words in memory, the state of the first counter stage is changed from "M" to "0" . An interrogation An associative memory is a memory in which words are located on the basis of at least part of their information content. The proposed memory uses cryotrons as storage cells. For a complete description of a cryotron memory see, R. R. Seeber, "Cryogenic Associative Memory," Nat. Conf . of the ACM, August, i960 . 19 is then made (in parallel) of all words in memory using OMM ... M as the interrogation word. If the MI signal is "0" (indicating no matches to this interrogation) the state of the first counter stage is changed to "l" and another interrogation is tried. If the MI signal is "l", the word matching this interrogation word (OMM . . . M) is retrieved and the state of the first counter stage is changed to "1". If the MI signal is "P" the state of the first stage is not changed but the state of the counter stage connected to row 2 is changed from "M" to "0" . The interrogation is next conducted using 00M . .. M. In general, the procedure for changing counter stages mentioned above is carried on throughout all rows of the memory. In addition, when a stage is advanced from the "l" state to the "M" state, a carry is produced and directed to the counter stage connected to the row containing the next bit position greater (in arithmetic value) than the row connected to the advancing counter stage. This carry changes the state of the recipient stage. For example, if the counter settings were 010001MM. . .M and if the interrogation using these settings caused the Ml signal to be '"0", the sixth counter stage from the left would be advanced to "M" and the fifth stage to "l". The new ternary counter settings would then be 01001MMM. . .M. The example on page 20 is given to clarify the rules for this ordered retrieval operation. The search is conducted on seven words, each six bits in length. The chart shows when each word is retrieved, the MI signal after each interrogation and the ternary counter settings for each interrogation. Seeber and Lindquist consider a retrieval try as one interrogation of the memory. In the example given there are 17 retrieval tries. The ratio of number of retrieval tries to the number of successful retrievals is found by experimentation to be in the range from two to three for small random-sample 20 o 3 c- H V£> H LT\ H -d- H H CM H rH O rH ON CO rH rH rH rH 2 2 H O H r-\ rH O H O H O H 2 H O O 2 rH o s s: "I rl rH 2 2 2 < h o 2 2 2 < H 2 2 2 g 1 O H 2 2 2 \ O O H 2 2 md ^ o o o 2 2 LT\ rO, I OJ <-i O O 2 2 2 H O 2 2 2 2 H o 2 2 2 2 o 2 g 2 2 s 2 2 2 2 2 2 H c\| m 4- ir\ vo C r? O ■H Cfl +3 c ■H R '/] 0) O EH Hi CD ■P ,G •H P ffl Ch fH CD ■H (H P OJ K CO O is 0) p IT\ MD M CD •H ri P p 21 sorts o Letting one interrogation "by their system correspond to the formation of a new logic function in the ordered retrieval developed for the Iterative Array, the retrieval ratio for the Iterative Array search is k8 for the "worst case" condition and 5 for the "best case." The method by Seeber and Lindquist is more efficient than the one developed for the Iterative Array because their search does not start at the beginning of the memory for each retrieval. In the case of the ordered retrieval derived from the minimum search, it is necessary to start at the beginning of the memory for each retrieval because after a retrieval, a new logic function must be formed and this logic function will not necessarily contain all rows as variables. This is due to the fact that some rows will cause a no mark signal at step (k) of the algorithm (caused by all words searched at that time being equal to "l" in that row). However, the informa- tion about which rows are to be included and which are not has been determined at step (h) . This information can be stored in the arithmetic computer and used as a basis for determining execution commands for the Transfer Memory and Iterative Array. As an example of how the new logic function is created to continue the search after a retrieval, assume the logic function that creates a "one mark" situation in M is S„ v R n ^ R^ ^ R, v R,- v R,- v R/- ^ Rq s/ R^« This 7124-55do9 function, before row (9) is made part of the logical sum, creates a "plurality" signal or a "one mark" signal in M. This is the logic function that should be formed to continue the retrieval. Rows R and R must be inhibited from becoming part of the function by the arithmetic computer. This is valid because the logical function is an interrogation of the words in the Transfer Memory. 22 Rows with subscripts greater than the subscript of any row included in the logical sum being used in interrogation must not be inhibited from being tested as a possible addition to the logical sum. This is because each retrieval necessitates the formation of new masks in S and Sn, and rows that have been inhibited on previous retrieval tries may be made part of the logical sum because of the new masks. The following search algorithm is comparable to the one developed by Seeber and Lindquist in that the search does not start at the beginning of the memory after each retrieval. (1) Transfer to S and So "0"'s corresponding to words being searched—all other positions contain "l"'s. (2) Set n = 1 (3) Sq v R n ~t M (a) If only one mark go to step (5) (b) If no marks go to step (k) (c) If more than one mark M — > So, got to step (h) (k) Increase n by 1 (a) If n = kS, go to step (5) (b) If n / Ii9 go to step (3) (5) M^S T — * Sg Sq — > S ? Read out all words corresponding to "0"'s in M. S ? — ^M (a) If only one mark read out the word corresponding to this mark. Stop * Assuming k8 bit words 23 (b) If no marks Stop (c) If more than one mark go to step (6) (6) Decrease n by 1 (a) If n = go to step (2) (b) If n f go to step (7) n < 7) \/ R K - S 7 -* M (a) If only one mark go to step (5) (b) If no marks go to step (6) (c) If more than one mark; M — — > So; go to step (k) (d) If no function can be formed go to step (k) In step (7) the logical sum is taken over rows 1 through n of the Transfer Memory that are not inhibited by the arithmetic computer. If the first n rows are inhibited then the search continues at the (n+l) row as a consequence of (7b). Because of the necessity of forming the logic function at step (7) this algorithm is written using the rows of the Transfer Memory as variables of the logic functions instead of using the Iterative Array register in which the rows are processed. This is done to clarify the way the search function is derived. The algorithm does not indicate when it is necessary to inhibit a row of the Transfer Memory because this is a function performed by the arith- metic computer. The arithmetic computer determines which rows to inhibit from the encoder signal at step (3)« it Step (1+a) will never occur at this point because this would mean that all rows give no information. 2k Steps (l) through (5) constitute the ordered retrieval derived from the minimum search. Steps (6) and (7) continue the search at the first uninhibited row preceding the row that determined the retrieval at step (5). If this function gives no information [step (7c)] then the search starts at the second uninhibited row, etc. Comparison of the Two Systems The dependence of the number of steps necessary to execute an ordered retrieval upon the word composition of the memory complicates a com- parison of the search derived for execution by the iterative processor with the search proposed by Seeber and Lindquist. However, some conclusions can be drawn. Many of the Iterative Array operations are executed before and after an interrogation of a row and have no counterpart in the execution of ordered retrieval by the associative memory-ternary counter system. These operations can be considered preparatory operations since they (a) prepare the mask registers for the next interrogation [steps (3c), (5) an( i (l)]> (b) determine if the search is to be continued [step (5)] or (c) are concerned with memory accesses [steps (3) and (7)]» The changing of the mask may be avoided in many cases by discreet use of overlapping operations. The operations at step (5) and memory accesses cannot be avoided. The latter operation is a consequence of having only eight registers to process as many as kQ rows for a retrieval. For words of six bits or less the number of registers is sufficient but in the case of longer words, the number of registers may make it necessary to transfer a row from memory each time it is For instance, at step (3), Sn v R could be read into M and S,-. If the "-some mask" situation occurs the next logical sum is S, v R . This sum is on then read into S8 and M, etc. 25 made part of the logical sum. A transfer between the Iterative Array and the Transfer Memory is the most time consuming operation performed in the search. These preparatory operations are the limiting factors in the method of serial search executed by the Iterative Array as compared to the parallel search executed by the Seeber and Lindquist system. Since the memory access time is the most time consuming operation in the iterative processor search, the worst case comparison between the two systems will be discussed in terms of the number of rows which must be accessed for each retrieval. The situation causing the "worst case" occurs at step (7) > under the conditions that none of the n rows are inhibited (n being determined at step (6)) and that for all n, the logical sum formed at step (7) generates a "no mark" situation in M. Under these conditions the search must form at least n logical sums before any word will be retrieved. These n sums are generated at step (7) and, therefore, there are n ) K = - — -^ *■ rows transferred from the memory to the processor for these i=l operations. The associative memory -ternary counter system will interrogate a maximum of 2n times to determine the same information under the stated conditions. The comparison of 2n interrogations by the Seeber and Lindquist system to the - — -r memory accesses necessary in the case of the iterative processor is admittedly pessimistic. But it does indicate that for ordered retrieval using the Iterative Array, the number of bits per word must be limited for assurance of a reasonable number of memory accesses per retrieval. Example 2, page 26 shows the execution of the ordered retrieval search by the Iterative Array on the same words retrieved in Example 1, page 20, by the associative memory -ternary counter system. Interrogation (16) of Example 2 is not executed with an interrogation function but is a 26 rd (1) > A 0) o •H •H !h S P (D K a •H 0) SH Jh crs Q) Ti u> U TJ n fn is -d- N~\ [-- VO CM H rH H H O H O H rH H O O H H O O rH O rH H rH H H H H H H rH O H rH H O O O O O O H O O H O _* VO VO H LT\ rH LTN H H CM N"N -d" LTN VO tn a o ■H -P •rH to o CM DO -P Ti T* •H ^ ts a> Jh •rl 0) ^ P X) p w -p cu •H p^ bO ch 0) o K a (U g d •H T3 P aj CTl > bl) CO o •H U ^H U -P rQ a d H H , H rH H rH *N CM OJ OJ CVJ *\ •v 1 -H o o K K « K K K H W K W K OJ OJ K 43 s s cr; *\ *s »\ »s « K " a H rH rH rH »s •s H K K K K rH H h 0) H TJ CO o S) rH o CM Ph H H O O o Ph H P-i O H H H a -h H co bD C Ti •H CD P pq 3 o ro, K> N"A K>, KN t>- t— hr> N"N N"N N~\ C— fA n^ D— LTN ft CD cd x P H OJ H I CO CO CO S3 o H Eh 3 o o ■H p o G 00 co CO CO CO CO CO CO > > f~ CO -d" t- CO CO CO K > CO CO CO CO CO CO > CO CO CO > CO co > CO > rH K > H > CM > > K ^ > > > > n^ OJ OJ KA -d- K > ffi K ffi K LTN > > -d- LT\ > VO > > f~ co --J- CM > CM K OJ K --J- -d- -d- o H OJ rr\ JJT LTA VO C^ CO ON O H H H OJ rH KA rH H LT\ VO 27 consequence of step (5) of the algorithm. This example uses only six bit words, therefore, it is necessary to perform only six transfers from the memory to the Iterative Array. Seeber and Lindquist estimate an interrogation and response from the MI to take 7 u-sec with their system. This means the retrieval of the seven words in Example 1 takes 119 usee compared to approxi- mately 56 usee for the Iterative Array (See Appendix) . If a row had to be read into the Iterative Array each time the row is made part of a logical sum, the time to execute the ordered retrieval by the Iterative Array is 88 (isec. It must be noted that the time comparison is not the best method of comparing the two systems. The interrogation and response time quoted by Seeber and Lindquist is not the optimum for their system. Another approach to the problem of executing ordered retrieval using the Iterative Array is to program the ternary counter operation in the arithmetic computer. The arithmetic computer can then determine the inter- rogation function from the counter. For example, if the counter setting is 101001MM. . .M, the result of the logic operation R v R v R v R, s, R v Re- stored in register M will create a zero in M corresponding in position to a word equal to 101001 in its first six bit positions.' From this information in the M register the encoder will signal the next setting of the counter, as did the Match Indicator in the system proposed by Seeber and Lindquist. However, the effectiveness of this method of ordered retrieval is also limited by the number of transfers necessary from the memory to the iterative processor. * For a discussion of this method of search see [2] 28 CHAPTER IV CONCLUSIONS The three search algorithms derived for the iterative processor give an indication of the versatility of the processor. The between limits search and the minimum search are well adapted to the serial processing of the words in the Transfer Memory by the Iterative Array. This is true for the between limits search because the words determining the upper and lower bounds on the search are processed serially. The minimum search must be executed serially because the interrogation of the memory is done without previous knowledge of the memory content. The ordered retrieval search, when involving words of six bits or less, is also well executed by the processor, as is shown in Example 2. The memory accesses necessary in the execution of a search by the Iterative Array constitute the greatest time factor in every search (see Appendix) and, therefore, is a limiting factor in the processor-' s application. However, it must be understood that the Iterative Array is designed for the purpose of pattern processing and the number of registers it contains (which determines the number of row transfers necessary) is designated to fulfill this purpose. A comparison of the execution times of an ordered retrieval search on the same words (Examples 2 and 3) shows the search executed by the Iterative Array is faster than the search executed by the Seeber and Lindquist system. But the examples also show that the total number of operations necessary to execute the search with the associative memory-ternary counter system is less than the number necessary with the Iterative Array. In general this operation 29 difference will exist, which demonstrates the logical superiority of a system that processes information within the memory. The Iterative Array has an advantage over the Seeber and Lindquist system for executing ordered retrieval in that a row is never interrogated more than once for each retrieval. But this advantage is overshadowed by the necessity of executing so many memory accesses for a retrieval. To eliminate memory access time the number of registers in the Iterative Array (other than the M register) must equal the number of bits in the words being searched plus two for masking purposes. (if the mask changing procedure mentioned on page 2h is also used this entails three registers for masking purposes.) In effect, the additional registers eliminate the need for the Transfer Memory. An excellent extension of the present investigation would be to explore the practicality of a memory containing the Iterative Array logic. Neither the possible uses of the iterative processor nor the discussion of the logic system it possesses is exhausted by this paper. Memory search is only one of many uses for the existing logic. It has been shown [2] that the Iterative Array is capable of executing simple arithmetic operations. An extension of the present investigation would be to find the practical and theoretical limits of using the Iterative Array as an arithmetic unit. Another extension would be to find the usefulness of the Iterative Array for solving coding theory problems such as computation of Hamming distances . * It should be noted, however, that the cost per bit of the Iterative Array is one to two orders of magnitude greater than the cost per bit of the Transfer Memory. 30 BIBLIOGRAPHY [l] B. H. McCormick, "The Illinois Pattern Recognition Computer- -ILLIAC III," IEEEE Trans, on Elec . Computers , vol. EC-12, pp. 791-813; December 1963. [2] S. R. Ray and K. C. Smith, "Design of an Iterative Pattern Recognition Processor," Digital Computer Laboratory, University of Illinois, Report No. l6l; April, 1964. [3] R. R. Seeber and A. B. Lindquist, "Associative Memory with Ordered Retrieval," IBMJRD, 6, No. 1, pp. 126-136; January, 1962. 31 APPENDIX Operation Execution Time Information transfer between the Transfer Memory and the Iterative Array 2 usee Encoder operation [monitoring of M register] 0.5 usee Iterative Array logical operation 0.5 usee Word readout or address given 2 usee Assumption: The arithmetic computer operating time may be ignored. Calculation of operation times (not including readout time except in the case of ordered retrieval) Between Limits Search Number of information transfers between the Iterative Array and Transfer Memory 96 Number of encoder operations Number of Iterative Array logic operations 19^- Total Time = 2(96) usee + 0.5(l94)usec - 289 usee. Minimum and Maximum Search Case I "Worst Case" Number of information transfers between the Iterative Array and Transfer Memory hty Number of encoder operations ^8 Number of Iterative Array logic operations 96 Total Time = 2(1+9) usee + 0.5(96 + kQ) usee = 170 usee 32 Case II "Best Case" Number of information transfers between the Iterative Array and Transfer Memory 7 Number of encoder operations 1 Number of Iterative Array logic operations 1 Total Time = 2(7) |_isec + 0.5(l+l) usee _ 15 [isec Ordered Retrieval Case I "Worst Case" Number of information transfers between the Iterative Array and Transfer Memory (4-8)(l024-) ■= 4-9152 Number of encoder operations (4-8)(l024-) = 4-9152 Number of Iterative Array logic operations (96) (102*+) = 98304- Number of word readout or addresses 1024- Total Time = 2(1+9152 + 1024) usee + 0,5(98304 + ^9152) usee = 180000 u.sec Case II "Best Case" Number of information transfers between the Iterative Array and Transfer Memory (5) ( 1024) = 5120 Number of encoder operations (5)(l024-) = 5120 Number of Iterative Array Logic operations (lO)(l024-) = 1024-0 Number of word readout or addresses 1024- Total Time = 2(5120 + 1024) + 0. 5(5120 + 1024o)jisec = 20000 usee 35 Example II Number of information transfers between the Iterative Array and Transfer Memory 6 Number of encoder operations 23 Number of Iterative Array logic operations 37 Number of word readout or addresses 7 Total Time = 2(6 + 7) usee + 0,5(23 + 37) usee = 56 usee .> UN °*^ UNIVERSITY OF ILLINOIS-UHBANA 510 84 IL6R no C002 no 160-170(1964 Report / 3 0112 088398166