LIBRARY OF THE 
 
 UNIVERSITY OF ILLINOIS 
 
 AT URBANA-CHAMPAIGN 
 
 0.OO.2. 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/branchandboundal438naka 
 
April 1971 
 
 ~yK^4i 
 
 A BRANCH- AND- BOUND ALGORITHM 
 FOR OPTIMAL NOR NETWORKS* 
 (The Algorithm Description) 
 
 by 
 
 Tomoyasu Nakagawa 
 Hung- Chi Lai 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, ILLINOIS 
 
Report No. U38 
 
 A BRANCH-AND-BOUND ALGORITHM FOR OPTIMAL NOR NETWORKS* 
 (The Algorithm Description) 
 
 by 
 
 Tomoyasu Nakagawa. 
 Hung-Chi Lai 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 This work was supported in part by the National Science Foundation 
 under Grant No. NSF GJ-503 
 
CONTENTS 
 
 Introduction 
 
 1, Definition of the basic form of the algorithm 
 
 2. Heuristics for the set of SCUC and IPPC 
 
 3- Pruning non-optimal solutions by redundancy check 
 k. Description of the entire algorithm 
 
Introduction 
 
 The branch-and-bound algorithm is applied by E.S. Davidson to the 
 synthesis problem of optimal combinational networks for arbitrary switching 
 functions using NAND gates, by introducing the desirability order and other 
 speed improvement gimmicks [l]. (In our expository paper [2], we summarized 
 his algorithm, explaining the details of these gimmicks. ) We implemented his 
 algorithm for NOR gates by using simpler heuristics than Davidson's and also 
 by incorporating a new gimmick called 'redundancy check'. This. report presents 
 the description of our version of the branch -and -bound method. 
 
1. Definitions and the Basic Form of the Algorithm 
 
 We want to solve the synthesis problem of optimal combinational networks 
 with NOR gates for m Boolean functions of n variables. 
 
 The criterion of optimality is the minimization of the cost function C 
 defined by C = A X R + B X I, where R is the number of gates, I is the total 
 number of inputs to gates (i.e., the sum of connections of external variables 
 and interconnections among gates), and A, B are non-negative coefficients (i.e., 
 weights). Different combinations of the weights A and B imply different 
 optimization problems: A > and B = implies the minimization of the number 
 of gates, A » B > implies the minimization of the number of gate inputs 
 after first minimizing the number of gates, and so on. In this report, however, 
 we will be concerned with the case A » B > unless we mention otherwise. 
 
 In the algorithm, we will represent given m output functions of n external 
 variables in terms of a truth table. Let x., i= 1, ..., n, ben external 
 variables, and let f , h = 1, ..., m, be the given m output functions. The x^, 
 I = 1, . . • , n, and f , h = 1, . . . , m, are expressed in the following way: 
 
 X iT ( 4 "■' 4 _1) ' iml > "" 4 (!.!). 
 
 „2 n -l> 
 
 and f h = (f h , ..., f h ), h = 1, 
 
 m 
 
 For example, in the case of m = 1, if the output function f^ is x^ v x^x^ 
 
 then 
 
 x- -(00001111) 
 
 *> 
 
 x 2 =(00110011) 
 
 x =(01010101) ) (I- 2 ) 
 
 and 
 
 f = (01011000) 
 
We will exclude from our discussion the case where some of the output 
 functions among the m functions are identical to other functions or external 
 variables. Therefore, we always need at least m gates to realize m output 
 functions f. Let us assign one NOR gate labeled h to each f , h = 1, . . . , m. 
 We call this network (i.e., m isolated gates whose outputs are assigned 
 f , h = 1, . . . , m) the initial solution . Fig. 1.1 is the initial solution 
 to the problem of an output function f , f = x -i x o ^ x -i x p x o> f° r a special 
 case of m = 1. 
 
 atel ( ) (01011000) 
 
 Fig. 1.1 The initial solution to f^ = x ± x </ x x x . The output of 
 the NOR gate is assigned f , but the gate has no inputs yet. 
 
 The algorithm starts with the initial solution, and expands the initial 
 solution by connecting external variables, by introducing new gates, or by 
 making interconnections among gates, so that the resulting loop-free networks 
 realize the m given functions simultaneously. 
 
 In accordance with (l.l), the output of every gate to be introduced 
 
 n , 2 n -l N 
 
 into a network is represented in the form of 2 -tuple as (P , ..., P ), 
 
 where each P for j = 0, ..., 2 -1, may assume the values or 1. It should 
 
 be noted, however, that the algorithm will not assign a definite value or 1 
 
 at once to all components, P s, of a gate. Accordingly, we use the symbol 
 
 * to denote the value of P is unassigned. Let us find out a necessary 
 
 n 
 2-1 
 condition that the output (P , ..., P ) of any gate in a NOR network 
 
 2 n -l 2 n -l> 
 satisfies. Take two gates, i and k. Let (P., ..., P. ) and (P,, ..., P, 
 
 denote the outputs of gate i and gate k, respectively. If gate i is connected 
 
1 J 
 
 to gate k, then the components P. and P" must satisfy the following condition, 
 
 no matter whether or not gate i and gate k have other inputs, because the 
 
 gates perform NOR operation: 
 
 pj 3 = for all j such that P? = 1 
 k l 
 
 and P? = for all j such that P? - 1 
 
 l k 
 
 gate k (~) (0 1 l) 
 
 ' : O 
 
 gate i ( ) (l 1 0) 
 
 (1.3). 
 
 Fig. 1.2. If there are 1-components in a NOR gate, then corresponding 
 
 components in its immediately preceding/succeeding gates must be 0. 
 
 A similar condition must also hold between the output of gate k and an 
 external variable Xp, when Xp is connected to gate k, regardless of other 
 inputs to gate k: 
 
 k = for all j such that x» = 1, 
 and x 3 p = for all j such that pJ = 1 
 
 (i.*0. 
 
 If the assignment of binary values to the components r's of the output 
 
 2 n -l 
 (P , ..., P ) of a gate satisfies the above condition with respect to all 
 
 of jjomediately preceding/succeeding gates and all connected external variables, 
 
 2 n -l N 
 then we call this assignment of (P , ..., P ) a feasible assignment . 
 
7 
 
 (Notice that some of components 3r 's could be *. ) 
 
 Using the concept of feasible assignment, let us define an "intermediate 
 solution". 
 
 Definition (Intermediate solution) . 
 
 A network of R gates, R > m, with external variables x, is called an 
 intermediate solution if the network satisfies the following set of conditions: 
 (i) The entire network has no loops. R gates are numbered 1 through R, as 
 gate 1, . . . , gate R. 
 (ii)-a The first m gates (i.e., gate i, for i =1, ..., m) are assigned 
 
 m output functions. In other words, the output of gate i is (f., ..., 
 
 2 n -l 
 f ), for i = 1, . . . , m. These gates may or may not be connected to 
 
 other gates yet. 
 
 (ii)-b The outputs of the remaining gates (i.e., gate i, i m + 1, ..., R), 
 
 if any, are completely or incompletely specified. Each gate i for 
 
 i = m + 1, . . . , R, is connected to at least one of other gates in the 
 
 network. 
 
 (iii) The assignment of the output of each gate is feasible. 
 
 Notice that the initial solution defined previously is a special 
 case of an intermediate solution. 
 
 The network corresponding to an intermediate solution may or may 
 not realize the given set of functions f, , h = 1, . . . , m. An intermediate 
 solution whose network realizes the given set of functions is said to be a 
 feasible solution . A feasible solution whose cost is the least among all 
 feasible solutions is an optimal solution . 
 
 In order to construct feasible solutions, we introduce the concept 
 of "cover". 
 
Definition (Covered component and uncovered component ) 
 
 J o 
 A component P = of gate k is said to be covered , if gate k has 
 
 i£ ~ ■"— "™*"^ — 
 
 at least one input (i.e., the output of gate i or external variable xJ whose 
 
 j -th component (P. or x, ) is 1. P, = of gate k is said to be uncovered , 
 
 J 'o 
 if P is not yet covered. 
 
 K. 
 
 Fig. 1.3 is an example of intermediate solution, where some components 
 are already covered. (The covered components are shown with underlines.) 
 
 Clearly an intermediate solution is a feasible solution if all output 
 
 -j 
 components P = in all gates k are covered. 
 
 f ± = X.jX v x^x 
 
 (0 1011000 ) 
 
 (1010000 0) (g) XH (* * 1 * *) 
 
 (00001111) x 
 
 (* 1 0) W ^J (* 1 * * * * *) 
 
 x 2 x 3 
 (0 0110011) (0 101010 1) 
 
 Fig. 1.3 Example of an intermediate solution for f = x x v x x x , 
 
 where some components are covered and others are not. 
 (The covered components are underlined.) 
 
Let us introduce the concept of possible covers for an uncovered 
 component. As seen from the definition "below, possible covers are the only 
 
 available external variables and/or gates with which we can cover the un- 
 
 J o 
 covered component under consideration. Suppose P in gate k is an uncovered 
 
 component in a given intermediate solution. 
 
 Definition (Possible covers of an uncovered component P, = of gate k) 
 
 (i) An external variable x. which is not yet connected to gate k is a 
 possible cover of P = if x. satisfies the following condition: 
 
 r x. =1, and 
 
 L x J " =0 for all j such that P J = 1. 
 
 Xj K. 
 
 (II) A gate i which is already connected to gate k is a possible cover 
 of P =0 if gate i satisfies the following condition: 
 
 p d ° . .. 
 
 i 
 
 (ill) A gate i which is not yet connected to gate k is a possible cover of 
 P = if gate i satisfies the following condition: 
 
 a connection of gate i to gate k will not form any loops, 
 
 < P. = 1 or *, and 
 
 v. 
 
 P? =0or* for all j such that pj = 1. 
 
 1 J£ 
 
 (IV) A gate which is not yet incorporated in the intermediate solution is 
 a possible cover. This gate is called a new gate , and satisfies the 
 following condition: 
 
10 
 
 The output components are all ■*. 
 
 The gate number of this gate is assigned R + 1, when the 
 
 highest gate number in the current intermediate solution is R. 
 
 With each of the possible covers defined above, we can cover P n accord- 
 
 k 
 
 ing to the following procedure, called an implementation of a possible cover. 
 
 Procedure (implementation of a possible cover ) 
 
 Step 1; If the possible cover is not yet connected to gate k, then connect 
 
 it to gate k; otherwise do nothing. 
 Step 2: If the j -th component of the possible cover is not yet assigned, 
 
 then assign the value 1 to it; otherwise do nothing. 
 Step 3: Assign the value to unassigned components so that the assignment 
 
 of the output of every gate in the network be feasible. 
 
 The Fig. l.U illustrates the above procedure for the case where a possible 
 
 cover is gate i of definition (ill) above. 
 
 J 'o 
 Suppose we are going to cover P fc in gate k with gate i in the figure 
 
 (a). By step 1, we connect gate i to gate k. By step 2, we set P.° = 1. 
 
 And by step 3, we assign the value to the components indicated by a, 0, y, 
 
 and 5. The resulting network is the figure (b). 
 
11 
 
 ( ll 
 
 6 
 
 ) 
 
 gatlT^Q^ (£ 
 
 ) 
 
 ( o 
 
 8 
 
 (a) before covering of P =0 with gate i. 
 
 gate KS^ ^ 
 
 1 
 ) 
 
 V 
 
 ( 1 0— - 1 1 ) 
 
 ) 
 
 (b) after a covering of P =0 with gate i 
 
 Fig. l.k Illustration of the procedure of implementing a possible cover 
 
12 
 
 By applying the above procedure repeatedly to uncover components in 
 each of the intermediate solutions, we eventually obtain intermediate solu- 
 tions in which all output components Pr. = in all gate k are covered. 
 In order to enumerate all such intermediate solutions systematically, we 
 introduce the following set of rules. 
 
 Definition (SCUC & IPPC) 
 
 The selection criterion of uncovered components (SCUC ) is the criterion 
 under which an uncovered component Pr. = is selected from the given inter- 
 mediate solution. '. 'he implementation priority of possible covers (IPPC ) 
 is the priority under which the order of implementation among the possible 
 covers for the selected uncovered component is determined. 
 
 Using the concepts defined in this section, we present the basic form 
 of Davidson' s branch-and-bound algorithm based on which he made several 
 versions of programs. In the algorithm below, we use a parameter C which 
 we call the cost ceiling , or the incumbent cost ; the C is used to preclude 
 all intermediate solutions whose cost exceeds the cost of the current best 
 feasible solution. Initially (! is set to a sufficiently large number. 
 
 'he basic form of the algorithm (Davidson ) 
 
 Step (start ) : k = 1. 
 
 Let S denote the initial solution. 
 
 Set C to a sufficiently large number. 
 Step 1 : Calculate the cost C, of the current intermediate solution S . 
 
13 
 
 Compare C, with C. If C, is greater than C , then go to step 7-lj 
 otherwise go to step 2. 
 Step 2 : Search for an uncovered component in S, . If there is none, then 
 
 go to step 8; otherwise go to step 3« 
 Step 3 ^ Select one uncovered component from S , according to the selection 
 
 criterion of uncovered component (SCUC). Let P denote it. 
 Step 4 : Ma.ke a list of all possible covers of P. 
 Step 5 : Store P and the list of possible covers in a working space, and 
 
 label k to this portion of working space. Select one possible cover 
 from the list, according to the implementation priority of possible 
 covers (IPPC). 
 Step 6 : Increment k by 1. 
 
 Implement the possible cover selected at step 5j generating the 
 augmented intermediate solution, S . Go to step 1. 
 Step 7 (backtrack) 
 Step 7-1: Decrease k by 1. 
 
 If k becomes 0, then go to step 9j otherwise go to step 7-2. 
 Step 7-2: Retrieve P and the list of possible covers of the label k from 
 the working space. 
 
 Search for unimplemented possible covers in this list. 
 If there are no unimplemented possible covers, then go to 
 step 7-1; if there are some, then go to step 7 _ 3» 
 Step 7-3: Reconstruct S v . 
 
 Select one of the unimplemented possible covers from the list, 
 according to the IPPC. 
 
 If we replace this condition ' C > C by 'C > C, then the algorithm 
 obtains only one optimal network, instead of all optimal networks. 
 
11+ 
 
 Step 1-h: Increment k by 1. 
 
 Implement the possible cover taken at step 7-3> generating the 
 augmented intermediate solution, S . Go to step 1. 
 
 Step 8 (solution) ; Print S . 
 
 Replace the value of C with the cost G of S, . 
 
 k k 
 
 Go to step 7-1. 
 Step 9 : Stop. 
 
 In the next two sections we describe two kinds of gimmicks to obtain 
 our improved version of the algorithm: our modification of the set of 
 SCUC and IPPC, and a redundancy check of feasible solutions which prunes 
 non-optimal solutions. We modify Davidson's versions of the algorithm 
 with these gimmicks. The entire description of the algorithm is presented 
 in section k. 
 
2. Heuristics for the Set of SCUC and IPPC 
 
 The set of SCUC and IPPC is the most important part of the algorithm, 
 "because this determines the order of intermediate solutions which the 
 algorithm enumerates. The investigation on this part of the algorithm was 
 the subject with which Davidson was mostly concerned; he experimented eight 
 versions of his program with different combinations of SCUC's and IPPP's. 
 According to the experiment, he chose the best version among the eight. 
 However, the heuristics incorporated into the SCUC and IPPC of this version 
 (and also most of other versions) is fairly complicated. 
 
 We conceived a set of SCUC and IPPC which is simpler than the simplest 
 version of Davidson's program, and which yet works as comparably well as 
 his most elaborate version. 
 
 Before presenting our version of the SCUC and IPPC, we define some 
 
 -x- 
 concepts necessary for describing the SCUC and IPPC. 
 
 Type of covered component 
 
 J o 
 A component P =0 which is already covered is assigned the type COV. 
 
 (COV stands for a component which is already COVered. ) 
 
 J o 
 Types of possible covers of an uncovered component P, = of gate k . 
 
 1111111 iC 
 
 Possible covers are classified into the following seven types. 
 
 J "o 
 G : A gate i which is already connected to gate k, and has P. = *. 
 
 , * ^O V 
 
 (G stands for a Gate having P. = *J 
 
 -x- 
 
 t 
 
 See [2]. 
 
 The concept defined here is essentially the same as Davidson's. However, 
 
 we use different mnemonic names for the types in the concept. 
 
 For the definition of possible cover, see Section 1. 
 
16 
 
 #■ 
 
 VC : An external variable x ff which is not yet connected to gate k, and 
 
 which has x ° = 1, and x<J = for all j such that PjJ - 1. (VC 
 
 stands for a Variable whose Connection being * (unassigned) ) . 
 
 GC 0: A gate i which is not yet connected to gate k, and which has 
 
 P.° = 1, and P? = for all j such that P? = 1. (&C*0 stands for 
 i.i k 
 
 a Gate whose Connection being *, and Pr = for all j such that 
 
 GC : A gate l which is not yet connected to gate k, which has P. = 1, 
 
 P. = or * for all j such that P n = 1, and where there is at least 
 i ■ k ' 
 
 * * 
 
 i i * * 
 
 one P. = * among those P. s. (GC stands for a Gate whose 
 i l . 
 
 J o j 
 
 Connection is *, and which has P. = 1, and P. = or * for all 
 — ' l 7 i — — 
 
 j such that PJ 5 = 1.) 
 
 G C 0: A gate i which is not yet connected to gate k, and which has P. = * 
 
 and P"? = for all j such that P? = 1. (G C stands for a Gate 
 i k . 
 
 J o J 
 
 whose Connection is *, and which has P. = *, and P: = for all 
 
 k — ' i — 
 
 j such that PJ 5 = 1.) 
 
 * * ■* ^o 
 
 G C : A gate i which is not yet connected to gate k, which has P. = *, 
 
 P. = or * for all i such that P n = 1, and where there is at 
 
 i ° k ' 
 
 i i , * * * 
 
 least one P: = * among those P.'s. (G C stands for a Gate 
 
 J o X j 
 whose Connection being *, P = *, and Pt = or * for all j 
 
 such that PJ 3 " = 1.) 
 
 k 
 
 NWG: A new gate. (NWG stands for a NeW Gate.) 
 The desirability order of types is defined by 
 
 -* * •* ■* ■* * #■ ■#•**■ 
 
 COV-G -VC - GC - GC -GCO-GCO - NWG 
 
 where COV is the most desirable, and NGW is the least desirable. 
 
 The type of an uncovered component is defined by the most desirable 
 type among its possible covers. 
 
IT 
 
 The type of gate k is defined "by the least desirable type among 
 all components P^ = 0. 
 
 Based on these concepts, our version of the SCUC and the IPPC is 
 as follows. 
 
 If the current intermediate solution has type NWG components, then 
 we employ Davidson's special scheme, called 'Remove NF vectors , which 
 generates from the original intermediate solution having type NWG compo- 
 nents another intermediate solution in which no type NWG components 
 exists. This scheme is to choose certain type NWG components to be covered 
 in order to maximize the number of new gates which must be introduced into 
 the network. This results in the preclusion of some equivalent networks with 
 permuted gate labels. For details, refer to [2}. Therefore, we assume in 
 the following that the current intermediate solution does not have uncovered 
 components of type NWG. 
 
 The SCUC 
 
 If the current intermediate solution has uncovered components of types 
 
 -x- 
 VC or less desirable, then select an uncovered component among those types 
 
 such that it has the fewest possible covers . If there are two or more 
 
 uncovered components which has the same fewest number of possible covers, 
 
 then select one whose type is the least desirable. If the current inter- 
 
 mediate solution has only uncovered components of type G , then select an 
 
 uncovered component (of type G Jwhich has the fewest possible covers. 
 
 This is explained in [2], as 'Special treatment of type NWG components'. 
 
 Davidson chooses the least desirable type but did not choose the type 
 of the fewest possible covers. 
 
18 
 
 The IPPC 
 
 Implement the possible covers of the selected uncovered component 
 according to the following order 
 
 ■* •* * ■# ■* * * ■*-*■* t 
 G - VC - (GCO, GCO ; GCO, GCO) 1 - NWG. 
 
 The possible cover (s) of type G are assigned the highest priority and 
 the possible cover of type NWG is assigned the lowest priority. 
 
 Davidson did not use the types of possible covers as the primary 
 criterion in his IPPC. 
 
 The motivation of establishing this set of the SCUC and IPPC is as 
 follows. 
 
 An uncovered component which has less number of possible covers 
 is "hard to cover" in a sense, since if we postpone covering of this un- 
 covered component until later, this uncovered component will more likely 
 lose any possible covers except a new gate. Accordingly we might miss good 
 networks. Therefore it seems a good rule to cover first an uncovered compo- 
 nent which has the fewest possible covers in a given intermediate solution. 
 However, if we take simply "the fewest possible covers" as the main criterion 
 of selecting uncovered components without distinguishing type G components 
 from uncovered components of other types, then type G components could be 
 selected too frequently at an early stage of the branching steps. Concentra- 
 tion on covering type G components may more likely result in the following 
 situation: one gate which is introduced as a new gate to cover a certain 
 component of another gate realizes the negation of the latter gate. With 
 repetition of this process, we may have indefinitely cascaded inverters with- 
 out completing a feasible network. In order to avoid such a hazard, we select 
 
19 
 
 one with the fewest possible covers among those whose types are VC or less 
 desirable. When the given intermediate solution has only uncovered components 
 of type G , we select one with the fewest possible covers among them. 
 
 Once an uncovered component is selected, we cover this uncovered component 
 with each of its possible cover, generating the corresponding augmented inter- 
 mediate solution. We have to order these possible covers such that we 
 generate a 'good' augmented intermediate solution first, i.e., one which is 
 as close to a feasible solution as possible. The desirability order seems 
 one of good rules for this purpose. 
 
 The difference of our heuristics from Davidson's may be illustrated in 
 the following way. The entire searching process of the branch -and -bound 
 algorithm is represented by a tree (called a search tree) in which the root 
 node corresponds to the initial solution of the problem, and non-terminal nodes 
 and terminal nodes correspond to intermediate solutions and feasible solutions, 
 respectively. Davidson's SCUC is based on minimizing the length of paths 
 from the root node to terminal nodes. Therefore, the search tree correspond- 
 ing to his SCUC is shallow in depth, but it may become broad in width. On 
 the other hand, our SCUC is based on minimizing the number of branches 
 originating from each node. Therefore the entire search tree corresponding 
 to our heuristics is generally thin in width. 
 
20 
 
 3. Pruning Non-Optimal Solutions "by Redundancy Check 
 
 Because of the nature of the branch-and-bound method, the first feasible 
 solution obtained by the algorithm may not be optimal. After finding the 
 first feasible solution, the algorithm searches for better feasible solutions 
 with the use of backtracking. Given the cost ceiling C, the algorithm dis- 
 cards all intermediate solutions whose cost exceed the cost ceiling, which 
 results in pruning of many non-optimal solutions implicitly. The lower 
 the cost ceiling, the more the algorithm prunes non-optimal solutions. The 
 redundancy check stated in [k] is a new gimmick which applies transformations 
 to the current feasible solution in order to get a better solution. Thus, 
 the cost ceiling can be lowered and some feasible solutions would be pruned. 
 The following is the summary of this gimmick. 
 
 (i) Elimination of gates 
 
 I-(i) We search for external variables and/or outputs of gates whose 
 
 disjunction turns to be identical to the output of gate i under consider- 
 ation. 
 
 If we find such external variables and/or output of gates, then we 
 replace each of the output connections of gate i by the new connections 
 of those external variables and/or gates (Fig. 3«l)« 
 
 I-(ii) We search for external variables and/ or outputs of gates whose new 
 
 connections in some portion of the entire network make gate i having only 
 one output connection redundant. 
 
 Since finding such external variables and/or outputs of gates in general 
 case is extremely difficult, we investigate several special cases. The 
 following is one among those we investigated. 
 
21 
 
 
 (a) 
 
 (b) 
 
 Fig. 3-1 Example of Transformation I-a: If the output of gate i is iden- 
 tical to the disjunction of the outputs of gates p and q in (a), 
 then we have a network having one less gate as shown in (t>). 
 
 Assume that the only output g of gate i is connected to gate k. Let gate 
 t denote the output gate of the entire network, and let F be its output. 
 
 Define h , = F ®Fj, and e = F, ©F", where F, is the output of gate t 
 when g is disconnected from gate k, and F" is the output of gate t when 
 the constant input 1 is connected to gate i. If we find some external 
 
 variables and/or gates whose disjunction e satisfies h c e C e , then 
 eleiminate gate i and its input connections and output connection, after 
 connecting these external variables and/or gates to gate k (Fig. 3*2). 
 
 Other transformations similar to the above one are explained in [hi. 
 
 we 
 
 (II) Elimination of Connections 
 
 II- (i) We search for connections (of external variables or gate outputs) 
 whose disconnections do not change the output of the entire network. 
 If we find such connections, then we eliminate them. 
 
22 
 
 disjunction = e 
 
 j£>; 
 
 (a) 
 
 (b) 
 
 Fig. 3.2 If e satisfies h, , c e c e i n ( a ), then we have a better network 
 
 as shown in (b) 
 
 Il-(ii) We search for an external variable or the output of a gate whose 
 
 new connection to another gate makes some existing connections redundant. 
 The transformation is based on the following property of a NOR network 
 configuration as shown in Fig. 3-3 (a). 
 
 Fig. 3.3(a) A NOR network configuration which consists of a subnetwork 
 o and gate t, where all output connections of a go to only- 
 gate k, but not to other gates. 
 
23 
 
 disconnected 
 
 Fig. 3.3(b) A network configuration equivalent to Fig. 3- 3(a) 
 
 Property 
 
 If an external variable g (or the output g of a gate outside of the 
 a) satisfies F > g, along with g > g., for i = 1, ..., v, where g. are some 
 
 Tj 1 1 
 
 of inputs to the a, then Fig. 3»3(b) is an equivalent network configuration 
 with respect to the output of gate t. Fig. 3- 3(h) has (v-l) less inputs 
 than Fig. 3- 3(a). 
 
 By combining the above transformations, we have the computational 
 procedure for checking redundances as shown in Fig. 3«^+- 
 
KDY-step 
 
 2k 
 
 Let S denote the given feasible network. 
 
 KDY-step 1 
 
 JsL 
 
 J 
 
 <r 
 
 Apply I - (i ) to S. 
 
 If we suceed in eliminating gates, 
 
 then rename the resulting network as S 
 
 KDY-step 2 
 
 ^_ 
 
 Apply I - (ii ) to S. 
 
 If we succeed in eliminating a gate which has only 
 one output connection, then rename the resulting 
 network as S, and go to KDY-step 1 
 
 KDY-step 3 
 
 _^ 
 
 Apply II - (i ) to S. 
 If we succeed in eliminating a connection, then 
 rename the resulting network as S, and go to 
 KDY-step 1. 
 
 KDY-step k 
 
 N^_ 
 
 Apply II - (ii ) to S. 
 
 If we succeed in eliminating one or more existing 
 connections, then rename the resulting network 
 as S, and go to KDY-step 1. 
 
 KDY-step 5 
 
 ±. 
 
 Terminate. 
 
 The S at KDY-step h is the best feasible net- 
 work we generated. 
 
 Fig. 3*^- The flow chart of the redundancy check procedure. 
 
25 
 
 h. Description of the Entire Algorithm 
 
 Incorporating the heuristics of the SCUC and IPPC and the redundancy- 
 check into the basic form of the branch-and-bound algorithm, we complete 
 our version of the algorithm as follows. 
 
 Step (start ) : Set K = 1, and BTK = 0. (BTK counts the number of 
 backtracks. ) 
 
 Set the cost ceiling C to a sufficiently large number. 
 Set up the initial solution S . 
 
 Step 1 (loop ) : Calculate the cost C of S ; the cost is defined by 
 
 A X E + B X I, where R is the number of gates, I is the number 
 
 of inputs to gates, and A and B are the given non-negative weights. 
 
 Step 2 : Search for uncovered components. 
 
 If the current intermediate solution S has no uncovered components, 
 then go to step 8 (solution); if S has no type NWG components, 
 then go to step 3; if S has type NWG components, apply to S the 
 scheme of 'Special treatment of type 1WG components'; the result- 
 ing intermediate solution has no type NWG components. Rename this 
 intermediate solution as S . Go to step 3» 
 
 Step 3 : Select one uncovered component from S , with the use of the 
 selection criterion of uncovered components (SCUC). 
 Let P denote the selected uncovered component . 
 
 Step 4 : List all possible covers of P. 
 
 Calculate the cost C for each possible cover; the cost C is defined 
 
 by C n + AC n + c, where C, is the cost of S. , AC. = B x {the number of 
 k k k k k 
 
 A. 
 
 gates which are other than the gate containing the P, and whose 
 
26 
 
 -X- 
 types are different from COV and G } , and 
 
 0, if the type of the possible cover is G 
 
 . = B, if the type of the possible cover is one of VC , GC 0, 
 
 \ * -* * •* -*•*■* 
 GC , GCO, and G C , 
 
 = A + 2 X B, if the type of the possible coves is NWG. 
 
 Accept only the possible covers for which C < C holds, then sort 
 those remaining according to the implementation priority of possible 
 covers (IPPC), and go to step 5; in the case where there is no 
 acceptable possible cover, go to step 7 (backtrack). 
 
 Step 5 ; Make a double-entry list (i.e., entries: a possible cover and 
 
 the corresponding C for each item) of the accepted possible covers 
 
 such that the first item is the possible cover of the highest prio- 
 
 ity and its corresponding C, the second item is the possible cover of 
 
 the second highest priority and its corresponding G . .., and the last 
 
 item is the possible cover of the lowest priority and its corresponding C. 
 
 Store the P and the double-entry list into a working space. 
 
 Label K to this portion of working space. We call this working 
 
 space the possible cover list (PC-list ) , and we refer to the P 
 
 and the double -entry list as the K-th P and the K-th block of the 
 
 PC-list, respectively. Select the first possible cover from the 
 
 K-th block of the PC-list. Go to step 6. 
 
 Step 6 : Increment K by 1. 
 
 Implement the first possible cover selected at step 5, generating 
 the augmented intermediate solution, S . 
 Go to step 1. 
 
27 
 
 Step 7 (backtrack) : BTK = BTK + 1. 
 
 Step 7-1: Decrease K by 1. 
 
 If K becomes 0, then go to step 9j otherwise go to step 7-2. 
 
 Step 7-2: Retrieve the K-th P and the K-th block of the PC-list. 
 
 If there are no unimplemented possible covers at all, or the cost 
 C of every unimplemented possible cover exceeds the cost ceiling 
 C, then go to step 7-1 j otherwise go to step 7-3- 
 
 Step 7-3: Reconstruct S . 
 
 Select from the K-th block of the PC-list the possible cover 
 
 which was implemented last time. If the type of this possible 
 
 -x- 
 cover is G , then set the j -th component of gate i to 0, i.e., 
 
 P. =0, where j is the component position of the P and i is 
 
 the gate number under consideration. (Notice the possible cover 
 
 -x- 
 is a gate, since the type of the possible cover is G . ) Go to 
 
 -x- -x- 
 step 7-^5 if the type of this possible cover is one of VC , GC 0, 
 
 -x- -x- 
 or GC , then impose a condition that this possible cover (an 
 
 external variable or a gate) be prohibited from connecting to 
 
 the gate that contains the K-th P, in any succeeding intermediate 
 
 solutions. Go to step 7-^+- If "the type of the possible covers 
 
 "X" -X- -X- -)f -X- 
 
 is different from G , VC , GC 0, or GC , then do nothing. 
 Go to step 7-k. 
 Step J-k: Take from the K-th block of the PC-list the possible cover next 
 
 to the possible cover taken at step 7-3- (This possible cover 
 has the highest priority among unimplemented ones. ) 
 Increment K by 1. 
 
 Implement this possible cover, generating the augmented inter- 
 mediate solution, S^. Go to step 1. 
 
 K 
 
28 
 
 Step 8 (solution ) 
 
 Step 8-1: Print S . Go to step 8-2. 
 
 Step 8-2 (redundancy check): 
 
 S^. is the current best network. 
 
 Apply to S the redundancy check procedure consisting of 
 
 K , . . 
 
 RDY-step through RDY-step 5, as explained in section 1. 
 
 A new network at KDY-step 5, if any, is the current best network. 
 
 Let C denote the cost of this network. 
 
 ■* 
 If C = C, then go to step 7-1; otherwise replace the value of 
 
 C with C , and print the current best network. 
 
 Go to step 7-1- 
 Step 9 (stop) 
 
 Terminate the computation. 
 
 All the printed feasible solutions of the lowest cost are 
 
 the optimal solutions. 
 
29 
 
 REFERENCES 
 
 1. E.S. Davidson, "An algorithm for NAND decomposition of combinational 
 switching functions," Ph.D. dissertation, Department of Electrical 
 Engineering and Coordinated Science Laboratory, University of Illinois, 
 1968. 
 
 2. T. Nakagawa and S. Muroga, "Exposition of Davidson's thesis 'An algorithm 
 
 for NAND decomposition of combinational switching systems,'" To be published^ 
 
 Department of Computer Science, University of Illinois. .. 
 
 3. T. Nakagawa and H.C. Lai, "Reference manual of FORTRAN program ILLOD- 
 (NOR-B) for optimal NOR networks," To be published as a report, Department 
 of Computer Science, University of Illinois. 
 
 k. T. Nakagawa, H.C. Lai and S. Muroga, "Pruning and branching methods for 
 
 designing optimal networks by the b ranch- and-bound method," To be published 
 as a report, Department of Computer Science, University of Illinois. 
 
 5. C.R. Baugh, T. Ibaraki, T.K. Liu and S. Muroga, "Optimum network design 
 using NOR and NOR-AND gates by integer programming," Report No. 293> 
 Department of Computer Science, University of Illinois, January 1969. 
 
 6. S. Muroga and T. Ibaraki, "Logical design of an optimum network by 
 integer linear programming - Part I," Report No. 26k, Department of 
 Computer Science, University of Illinois, 1968. 
 
 7. S. Muroga and T. Ibaraki, "Logical design of an optimum network by 
 integer linear programming - Part II," Report No. 289, Department of 
 Computer Science, University of Illinois, December 1968. 
 
 8. S. Muroga, "Logical design of optimal digital networks by integer 
 programming," in book Advances in Information Systems Science, Vol. 3 
 edited by J.T. Tou, Plenum Press, 1970, pp. 283-3^8. 
 
 9. T. Nakagawa and S. Muroga, "Comparison of the implicit enumeration 
 method and the branch- and-bound method for logical design," To be 
 published as a report, Department of Computer Science, University of 
 Illinois . 
 

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