'_=r=_j^ SSL**-- L I B HAHY OF THE UN IVLRSITY Of ILLINOIS S\o. & E " ,,l >*> fi : ::ii s „„„„...«.»»»»";;;;:::;:";;».i "•».„.„ llnHa |l||!|.«llllliml l >IUHI n> "" | * || ...iHll»HI >a ;i||HIIIIUIIIIHIII»ll":*fiH aMl11 „,,..tllfl . 1I ..» ,,i ,.,""". „ fi ..-IH».H..i»»»««"- , " ,,,,H " III' IIII II* HIIIIIIIillII*"*S3SI" i **'"" 11 &t) T- S L f t , _ . > — _ _ 7 r t l jr J -.** a. K O -1 z o UJ £ I* —i i i hi »- 5 p (0 I 1 i - 1 1 1 < 1 * eo UJ O UJ o t- is O — M « 2 5 oB < z (£ CO H„ to £ So z ** M PZ 17 Intuitively the idea "behind digital image thinning is to "shrink" an original digitized image to a line drawing --while preserving all connectivity of the original „ The utility of the thinning process is readily apparent . Thinning extends to the local neighborhood of a point certain global aspects of the picture. For example, imagine a process by which all black track-like elements are thinned to "unit" thickness,, massive black areas are reduced to mere peripheries, while intersection junctions of the original are preserved. For a rectangular (or rhombic) raster we can then classify all black cells of this "thinned" image into four categories—merely by counting the number of black points in the eight (six) cells immediately surrounding the cell in question: Number of Black Points Class of Point in Immediate Surround isolated point end point 1 interior point (of a line segment) 2 junction point 3 or more This mode of classification, applicable only for thinned images, is an immense simplification of the equivalent procedure for unthinned images. Positions noted by eye as end, interior, or junction point on the original (unthinned) digitized image are selected, in general, on the basis of elaborate decision criteria—often involving a knowledge of neighboring points over an extensive area. Simulation studies to date show that line width normalization (thinning) can be efficiently realized by simple AND, OR, NOT boolean functions of the out- put of nearest-neighbor stalactites. 3.1.2 Bubble Logic Certain noise-cleaning operations, in particular gap filling, implicitly involved an estimation of size- -a counting operation. The neighboring bits in question are transferred to eight bits of the internal storage register of the stalactite „ These cells of the stalactite are made "self-ordering"— a fixed number of identical operations will order the contents of the register so that all "zeros" rise to the top, all "ones" 18 precipitate to the bottom of the vertically-aligned stalactite (Figo 8), Once in this canonical form, threshold logic is achieved by sampling (in parallel) contents of all internal flipflops of given depth. For a physical description of the bubbling process consider a vertically-oriented register containing mixed "l's" and "O'so" Examine all adjacent pairs of digits and everywhere replace each (_) pair by a ( ) pair. All other digits remain unchanged. Clearly this operation neither creates nor destroys "l's" but, if iterated, "l's" ultimately move to the bottom-most cells. For an r-bit register a maximum of r - 1 iteratives of the bubble operation are required to order completely the contents of the register. Figure 8 shows an example of bubbling in which four operations completely order the register. Subsequent operations do not change the contents of the register so it is not necessary to sense the completion of ordering. The register is shown oriented vertically to strengthen the analogy that "O's" are bubbles moving to the top, hence the term ''bubbling." To describe the logical function involved let A, B, C be any three consecutive positions of the register (counting downward). The basic bubbling operation (BID) is then given by Bubble l's Downward (BID) ^ v where B is any register position, A and C are adjacent positions (A above, C below) and B' is the new contents of the register B. In addition bit stacking (and unstacking) facilities are built into the stalactite logic. These prove to be special cases of the bubble logic. 3°1°3 Structure of the Stalactite The iterative array of stalactites can be connected in either rectangular or rhombic symmetry at programmer's option (Fig. 7)- Each stalactite can be visualized as having a sole transmitting channel (the signal output line). In turn the stalactite can receive information from any (or all) r top B' = BC all interior B' = AB v BC , bottom B' = A v B 19 r BITS 'm STALACTITE TOP J^ > _^ AFTER BUBBLING >» r-p 0'$ r p 1$ .WHERE p IS THE NUMBER OF VARIABLES X,,X 2t --,X m TAKING VALUE 1. CANONICAL FORM FOR SYMMETRIC BOOLEAN FUNCTIONS OF m VARIABLES(m^r) FIGURE 8A INITIAL STATE ITERATION I ITERATION 2 ITERATION 3 ITERATION 4-7 1 X X 1 1 1 X X 1 1 X X 1 1 1 X 1 1 1 1 1 FINAL STATE SUCCESSIVE STEPS IN THE BUBBLING PROCESS FIGURE 8B 20 of its immediate neighbors: eight for a rectangular array, six for a rhombic array (see Fig. 7)< In addition the stalactite can sense its own output (input channel in Fig. 7)= The internal symmetry of each stalactite module reflects all trans- lational, rotational,, and reflectional symmetries of an (infinite) planar array, and employs a minimum number of active elements consistent with efficient realization of processing macro-instructions . The generic stalactite contains ten one-bit registers of internal storage (Fig. 9)° These flipflops j labeled M, 0, . .., 8 serve as (l) the buffer register of the transfer memory (M); (2) an auxiliary nonbubbling register (0); and (3) eight consecutive bubbling flipflops (l, 2, ..,, 8). If we ignore intra-stalactite processing (bubbling, etc.), the simple structure of the stalactite for communicating with its neighbors can be under- stood from the following constraints : 1) the new value of every internal flipflop is a function of only the normal nine inputs (eight neighbor, one self) and of control lines common to every stalactite of the array, 2) the new input signal is a function only of the present contents of the internal flipflops and of control lines common to every stalactite of the array. In addition to avoid race conditions, we will insist 3) in any one instruction an internal flipflop is not both read from and written into,, (Of course in any one instruction flipflops may be inert and ignorable : neither read from nor written into. ) Constructions of the above type can be called unconditional transfer orders -- unconditional, because the execution of the instruction does not depend on the internal state of the stalactite. Let us partition the generic stalactite into three blocks labeled TRANSMIT, RECEIVE and STORE as shown in Fig. 9. Blocks TRANSMIT and RECEIVE, as implied by the constraints (l) and (3) above, are pure combinatorial nets (i.e., without internal storage). 21 22 A given internal flip flop can in any one machine instruc tior. be written into,, or read from, but not botho That is, the RD control signals and the LD control signals must be partitioned into two disjoint setSo Alternatively one could partition the set of internal flipflops, marking some for "intermediate storage" as in the traditional double-ranked shift register. We will find it faster (one machine cycle rather than two) to have the control assign (in common for the whole array) internal flipflop numbers to intermediate results., and permute these assignments from one instruction to the next. The ten registers of internal storage , the block STORE, are not differentiated, and therefore fed from a common bus „ The TRANSMIT combinatorial net must be a symmetrical boolean function of the output of the ten internal registers, if these are to be undifferentiated. The AND function of outgated flipflops, with or without subsequent complementation has been chosen for the TRANSMIT net. That the net RECEIVE must be a symmetric net of its nine inputs is less obvious. We have proved a theorni that asserts "a generic stalactite, capable of being embedded in an (ideally infinite) array of either rectangular or (at programmer's option) rhombic array, and exhibiting all translational, rotational, and reflectional symmetries of the embedding space, must be a symmetric function of its eight input terminals (from nearest neighbors)." The or self-input terminal is shown to be distinguished by this proof, and could be treated separately. Notice that inputs from diagonally-connected neighbors are in no way distinguished, even though for the rectangular array alone there exists no rotation or reflection interchanging diagonal and horizontal/vertical axis inputs. This symmetry is in force only because the stalactite array can be viewed (at the option of the programmer) with either rectangular or hexagonal packing. The OR function of all ingated signal lines, with or without subsequent complementation, has been selected for the RECEIVE net. 3.2 The Transfer Memory The central core of the pattern articulation unit (PAU) has been introduced above as an iterative array of processing modules with word size 32 x 32. These modules require individual access to memory. This memory can be partitioned into a part intrinsic to the stalactite, i.e., those flipflops implicit in the realization of threshold logic, etc.; and. into a remaining part 23 extrinsic to the iterative array proper. Collectively this latter memory will "be referred to as the transfer memory (TM) and is logically inert. 3.2.1 Use of Auxiliary Memory Demands for intermediate storage are seen to arise naturally — either (l) from the nature of the input visual image,, or (2) from the necessity to retain intermediate partial results. Examples of the former situation arise when successive input images are continuous in (i) time sequence (neighboring motion picture frames, television scans, etc.), (ii) tone (successive slices of gray scale), or (iii) color (the digitization implicity in four-color printing). Here congruent storage is essential if the processing routine is to exploit similarities of image shape from frame to frame. The necessity to store intermediate results of the iterative array stems directly from the means of executing honogeneous logical transformations in the processor. The complexity of the iterative array can obviously he greatly simplified if various digital filtering operations can be performed not in parallel, but serially, and intermediate results (32 x 32 = 102^4- bit words) stored. For example; local track setment orientation can be designated as being predominantly horizontal, vertical, left-diagonal or right-diagonal in four serial tests, whereas simultaneous identification requires approximately four times as much hardware. * To this end the transfer memory supplies ^8 planes of 102^ bits each of random access memory. In this mode of operation one bit from each of the 102 4 processing modules (stalactites) is transmitted in parallel to (from) the TM in any one memory cycle . -* The intrinsic speed advantage of contemporary digital circuitry over neutral response rates strongly suggests that a different schema- -time -multiplexed use of one processing array with facilities (TM) for storage of intermediate results--be used in the man-made recognition machines, in contrast to the extreme filtering parallelism found, for example in the frog's eye. [H. R. Maturana, J. Y. Lettvin, W. S. McCulloch, and W„ H. Pitts, "Anatomy and Physiology of Vision in the Frog," Jour. General Physiology, ^3, 129, (I960)] ~ 2k 3.2.2 Extraction of Information at a Labeled Point Normally a processing routine can be case into a form where relatively few stalactites are labeled,, i,e, ; singled out for detailed examination. All tracking operations culminate in this form- -labeling of terminal nodes , points of intersection, etc. The essential point is that ancillary information- -most naturally associated with each labeled node--can be extremely useful. For example in bubble -chamber data processing local orientation can help distinguish track segments of an electron spiral from segments of an intersecting beam track. Such information, perhaps aimed at improved tracking by assisting selection of the next point of readout, is extracted from the transfer memory by a second mode of reference. Rather than a global view of one bit from each of the 102 4 stalactites, parallel output of the contents of one stalactite is sampled. In this latter node the transfer memory is viewed as a random access memory of 1024 words, one word (48 bits) associated with each cell of the processing array. 3. 3 List Compilation 3.3-1 List and Mark Instructions The problem of extracting an abstract graph description of a line drawing embedded in a plane of the stalactite array has been introduced in Section 2.2. Once each node of the line drawing has been labeled in parallel by local boolean processing, the list compilation facilities required to read out (and thus generate the abstract graph) can be reduced to two principal operations : 1) List Instruction . All points (i.e., black cells of a sparsely populated plane) are sequentially identified by ten-bit coordinates Z = (X,Y) with five bits X, five bits Y. Sequential readout implies a linear ordering of all 1024 cells of the array, and that an algorithm for finding the first black point is known. 2) Mark Z Instructions . A single cell specified by address Z is marked (i.e., set = "l"). Marking, as will be shown below, can also be used for erasing points of the sparsely 25 populated plane as found. Iteration of the search algorithm to find the "first" black point,, alternated with subsequent erasure of each point as found, eventually lists all points of the plane. 3.3.2 Use of the M Register From engineering considerations* it is convenient to specialize the mark and list instructions to the M plane of the stalactite array. The two coordinate instructions then take the form: MARK (Z): sets to "l" the M flipflop of the stalactite at coordinate Z = (X^Y). LIST: serially compiles a list of all coordinates Z of stalactites having "0" in the M flipflop.** Coordinate Z of the next point found is transferred to the LIST register automatically upon storage of the previous contents of the register. In use, a sparsely populated plane is complemented, loaded into the stalactite M register, and a first black point identified by the LIST instruc- tion. Each coordinate of this list, once compiled, is used to MARK its associated M flipflop (and thus erase the point). Black points connected to this point (found by flash- through) are in turn listed. This technique (for isolated track segments each LIST instruction brings down only one entry) builds a paired list of nodes, i.e., the branches of the associated abstract graph (Fig. 10), * \ Coaxial cable connects the transfer memory (TM) and the M plane. It is convenient to make the MARK and LIST instructions adjuncts of the TM gating arrangement and to capitalize upon the close jaxtaposition of M-plane signal lines at the TM. As we normally complement a plane before transferring it to the M register and initiating the LIST instruction, we will refer to a "0" in this M plane as a "black point . " 26 END POINT- (COORDINATE READ OUT BY LIST INSTRUCTION) INERT POINTSss (NO ENTRANCE UNLESS SPECIFIED BY MARK INSTRUCTION) NOTE DUAL PATHS PERMISSIBLE PATH CAN BE TERMINATED HERE BY REMOVAL OF THE JUNCTION POINT BEGIN (INITIATED BY MARK INSTRUCTION) 4 3 2 i lo 1 1 5 = 1 LJmI ■ACCEPTANCE FIELD OF CENTER POINT '(FIELD SPECIFIED BY GATES CONDITIONALLY OPENED- IN THIS CASE ONLY G(5)j G(8)«V PATH BUILDING WITH MULTI-SELECTION SWITCH ARRANGEMENT FIGURE 10 27 3.3°3 Search Algorithm Ordering The list instructions as mentioned above imply a linear ordering of all 1024 cells of the two-dimensional array. A point in this array is specified by coordinate (X,Y) with five bits of X^ five bits of Y. Rather than the customary integer representation it is convenient to visualize (X + iY) as a point within the unit square: < X < 1, < Y < 1 with X^Y proper binary fractions . All "M" cells with an output signal of "0" are lexicographical ordered first on Y, then X. The cell of lowest order is then LISTed first (Fig. 10 ). 3 . 3 o 4 An Associate Memory Coordinate readout, in conjunction with the logical processing facilities of the stalactite array., combined to transform the transfer memory into a versatile associative memory ,. Consider the transfer memory initially filled with < 1024 words_, each of 48 bits Let any specified subset of bit positions (0^ 1, = .., 47.) be designated a c ode field . The associative property in simplest form asserts that the addresses of all words (if any) having as contents of their code field an (arbitrary) requested bit pattern are directly identified. In the PAU design parallel associative search is done by trans- ferring the bit plane of the code field in turn to the stalactite array with appropriate complementation such that the ideal pattern, so manipulated,, is identically zero. After stacking (or bubbling )^ the M bit of all blank stalactites is marked and the corresponding addresses compiled. The logical flexibility of the stalactite array permits obvious generalizations of this technique: in particular _, the addresses of those words whose code field bits satisfies some simple boolean function can be selected by appropriate intra- stalactite programming. 3.4 PAU Order Code For purposes of control the instruction set of the PAU can be partitioned into seven basic types of instructions: 1) stalactite transfer orders (conditional/ unconditional^ with/without simultaneous border transfer) 2) stalactite bubble orders 3 ) transfer memory orders 28 h) flash- through 5) pyramidal readout (i.e., list, mark instructions) 6 ) border input/output 7) special instructions In the interest of brevity we will treat in detail here only the stalactite transfer and bubble orders „ Instructions requiring communication between the stalactite array and the transfer memory will be momentarily ignored in this section. We emphasize that the instructions described below are machine micro- instructions o Programming macro - instructions, on the other hand, are dis- cussed in references 3 and 6„ Sample code is illustrated in Fig* 11. For pedagogical reasons it is convenient to introduce two redundant bits and subdivide the resulting 40-bit stalactite u- instruction into four control groups of ten bits each. The first of these is called the flow control as the first five bits of the group specify the information flow through the stalactite as a whole. Flow group (first five bits): ■ 5 bits-S> |c G C F B A M pi O U B -p ! 0) -p 10 4d H pi a; a w ,a ■p •H CTJ J3 01 H PS |o O O Pq pq Here C and C specify whether the outgoing or incoming signal respectively, or both, are to be complemented (see Fig. 9)» Bit G, when "l" and only then, indicates that the gate input control group must be examined as at least one input gate is opened (gate control / 0). Bit F, whe "l, " indicates the flash- through bypass is to be called into play. The fifth, or B bit, when "l, " evokes a bubble logical operation, the selection of which is given by the second five bits of the flow group. 29 FORNANGO, J. P. 31022 • • INITIAL PRE • SETMCD -PROCESSING ROUTINE FOR BU 72 LETTER ( X) , BCGLOP START READ Ml PRINT Ml, ,72,72 CCCMMT (-ORIGINAL PICTURE! INOEX SET, 1,0 FILL BCOFUN M2,, MO,, Ml,, (37$) BCOLOP Ml,,0R,Ml,,M2 TPARK 0LSUR,,M2,,M0.tMl,,GEt7 BCOLOP Ml,,0R,M2,,Ml BCOFUN M2,,Ml,,M|,,(2/3/6/7t) BCOFUN M2,,M0,,M2,,(5«7$) BCOFUN M3,,Ml,,Ml,,(4/7/S/m BCOFUN M3,,M0,,M3,,(7*U> BCOFUN M4,,Ml,,Ml,,(6/l/2/3$> BCOFUN M4,,M0,,M*,,(1*3*) BCOFUN M5,,Ml,,Ml,,(B/3/4/St) BCOFUN M5, ,N0,,M5,,(3*5») BCOLOP Ml,, OR, Ml,, MS BCOLOP Ml,, OR, Ml,, MA BCOLOP Mi,,0R,Ml,,H3 BCOLOP Ml,,0R,Ml,,H2 INOEX 1NCR,1,1 JUMP LESS, FILL, 1,2 BCOFUN M2,, Ml,, Ml, ,(5/1$) BCOFUN M3,,Ml,,Ml,,(l/56) BCOLOP M2,,QR,M2,,H3 BCOFUN M2,,M0,,M2,,(I5t) BCOLOP Ml,,0R»Nl,,M2 INOEX SET, 1,0 BOOLOP M7,, EQUAL, Ml THIN TMARK DLSUR,,M2,,Ml,,Ml,,LEt3 BCOFUN M3,,MI,,M1,,(37$) BCOFUN M4,,MI,,M1,,(IS$) BCOFUN MS,, Ml,, Ml, ,(3/7*7/3$) BCOFUN M6,,Ml,,Ml,,(I/5*S/f$) BCOFUN M3,,M3,,M3,,(i+5$) BCOFUN M4,,M4,,M4,,(3«»7$) BCOFUN MS,,M5,,M3,,(3*7$) BCOFUN M6,,M6,,M4,, (!♦$$) BCOLOP M3# »0R,M5,,M6 BCOLOP M4,,AND,M1,,M3,,BAR TPARK 0LSUR,,M5,,M2,,M3,,EQt2 < BCOLOP M6,,AN0fM2, , MS,, BAR BCOLOP M2 f ,0R,M6,,M4 BCOFUN Ml,,M7,,M2,,(26*4B$> 1 BCOLOP Mi, ,0R,Ml,,M2 INOEX INCR,l,l JUMP LESS,THIN,1,3 COMPLETELY FILLED CONTEXT PLANE FILL SINGLE HOLES IN N. OIR. FILL HOLES WITH 7 OR • NEIGHBORS CORNER FILL EAST PILL SAVE POINTS MITH 3 OR LESS NEIGH REMOVE P IF IT IS A BOUNDARY PT NEXT TO 2 INTERNAL PIS* PUT BACK SAVEO PTS WHICH 010 NOT HAVE 2 NEIGHBORS REMOVED. PUT BACK REMOVEO PTS WHICH WOULD BE 01 AG. INTERNAL IP KEPI. Figure 11, Sample PAU Simulator Program" (Using Macro- Instruction Set) 13 30 \\ Flow group (second five bits) u D N 2 H i H 03 o o ■H ^H -P 3 -p Bits U and D (positions 6 and 7) define the type of bubble logic. Here the number of iterations to be applied (0, 1, 2, . .., 7) is given by the binary number N Q N,N_. When B = 1, the three bits of iteration number N are transferred to a control counter to control iterations of bubbling. Having set up the flow it is appropriate to interrogate which flipflop outputs are to be sent as a confluence ( AND/ AND) out over the output channel. The appropriate flipflops are specified by the FF Read Control group: FF Read Control group: 1* 10 bits >| ^ 1 M 1 (2_ 3 h 5 6 7 18 Having thus established the output signal of every stalactite we sum (OR) together the requisite input signals to the stalactite, as specified by the Input Gate Control group : Input Gate Control group : \ 1 " 1 C 1 2 3^5 6 7 8 Here the significance of the C bit needs re-emphasis: C (= "l") signifies that conditional input gating is to be used, i.e., each gate 0, 1, ,.., 8 marked with a 1 in the input gate control group is, in fact, open only if the corres- pondingly numbered stalactite flipflop contains a "l" at the beginning of this instruction. It will be remembered that the iterative array can operate in two connectivities: rectangular or rhombic. For the rectangular case all ten bits of the input gate control group are used; for the rhombic array, the last two 31 bits are ignored and the input gates, as associated internal flipflops, renumbered to conform to the conventions. Finally, the output signal of the input combinatorial net (called the incident bit ) is, after possible complementation, ready to be stored, or interrogated as the conditional control bit for a bubble-logic operation (if specified by B = "l"). If the former situation obtains, then and only then, is the fourth and final control group examined--the FF Load Control Group: FF Load Control group: k 10 bits >l \ K * 1 M 1 2 3 h 5 6 7 8 Here each of the ten bits corresponds respectively with the ten internal flip- flops of the generic stalactite . In summary the intra- stalactite micro-instructions are specified by four control groups of ten bits each, placed in the ^4-0-bit stalactite instruction register (SIR): Stalactite Instruction Register: I II III IV 10 20 30 kO Ti Tl cd cd CD •p o > « 3 CD h-l o ft -P -H 1^ a& ta fe The interpretation of the individual control groups has been described above 3=5 Fabrication of the Pattern Articulation Unit (PAU) 3.5 .1 Layout From a packaging point of view the PAU consists of six subdivisions listed below: 1 ) iterative array 2) PAU control 3) transfer memory and pyramidal readout encoder h) SCR power supplies 32 5 ) final voltage regulators 6) air-conditioning unit All units are housed in the computer main frame with the exception of the SCR power supplies (basement), relay wall boxes (wall-mounted in computer room), and air-conditioning unit (roof -mounted directly above main frame). The distribution of the remaining units as housed in the main frame is shown in Fig. 12. Each of these units is discussed momentarily below. 3-5.2 The Iterative Array There are six basic circuit boards of the iterative array. Each circuit board is packaged on a 3 "98^- "-wide x ^-.750"-long photoceram board. A total of I36O boards are required. Of these 102 4- are used to house the stalactites of the iterative array, one per board. The distribution of circuit boards of the iterative array is housed in the four front transistor bays of the computer main frame is shown in Fig. 13 . Control drivers are placed largely with middle of the transistor bays to keep wiring length to a minimum. Drivers to even and odd rows of the array are separated, consistent with the potentiality of using either rectangular or rhombic connectivity. Every stalactite board has two coaxial connections (respectively to/from the TM, and hence PRE). This integrates to a massive arterial network of miniature coaxial cable which is fanned into the TM (front central rack). Coaxial connections to (from) the border of the ^0 x ^0 array, though extensive, are nominal in comparison. 3.5=3 The Stalactite Because the stalactite plays a role of central importance in the array, its design configuration is shown in Fig. 1^-.* This circuit design of Professor K. C. Smith will be separately reported in more detail by him at a later date (see reference 18). 33 CM 9) L. 3 3^ o a « 5 I 8 I 0> o d; ^ i s > S 5- * P o t ° o ae < ■ < < < < a. o 3 o >- < V) o o CD ol, aal n Drs as — • 36 Certain features of the design warrant emphasis. First it should be observed that virtually no decoding of control signals is done within the stalactite. That is, each control line is directly identified with a bit in the general micro- instruct ion. Secondly, almost half the circuitry of a module is expended on control, or routing of the signal, reflecting the wide range of admissible orders that a module can execute. That portion of the stalactite of high symmetry, i.e., the ten internal flipflops with associated gates and bubble logic, are realized in ten thin-film microcircuits, each 0.42 x 2 inches (Fig. 15).* Conventional silicon transistors and microdiodes are used. Parts of low symmetry, i.e., the control portions of the stalactite, are packaged on printed-circuit chips using conventional discrete components . 3.5.4 Transfer Memory and Pyramidal Readout Encoder The transfer memory and the pyramidal readout encoder function together as an associative memory. For this reason they are packaged together in the entire front center rack and share the 1024 coaxial cables entering from and the 1024 coaxial cables exiting to the 1024-bit M register of the stalactite array. Packaging the circuitry of the transfer memory in close superposition with the core matrix stack requires considerable ingenuity. A drawer arrange- ment holding the transfer memory circuitry, pyramidal readout encoder circuitry, the matrix stack, as well as the interconnecting coaxial cable, is planned. Dr. Hans Bilger materially assisted in these layouts 37 i * r I .... ,$ . . ■■ ■■ , o ro - o < ' L^ -£3 [ -□i ■a, -j-QL s ■■=? L_ [ID » — HZHr - & -n. ded- l! < CL k . SUMMARY This report has described the system design of an all-digital computer for visual recognition „ One processor, the Pattern Articulation Unit (PAU), has been singled out for detailed discussion. Other units, in particular the Arithmetic Unit and the Taxicrinic Unit, are treated in reports listed in the attached bibliography. The PAU has been shown to be a processor of fundamentally new design- - its logical organization has no analogue in the central processing unit of existing computers. The PAU is the first modular parallel processor (l) which because of its digital organization is capable of more reliable visual identifi- cation than part analogue/part digital preprocessors of much less generality and potential virtuosity; (2) which is faster than any presently suggested alternative realizable today at comparable cost; (3) and which can serve as a prototype to a new generation of parallel computers that will capitalize upon thin film and integrated semiconductor circuitry of the immediate future. •38- p D D a □ a D SELECTIVE BIBLIOGRAPHY OF PAPERS ON THE ILLINOIS PATTERN RECOGNITION COMPUTER ( ILLIAC III) Summary Articles 1. Bo Ho McCormick and R„ Narasimhan, Design of a Pattern Recognition Digital Computer with Application to the Automatic Scanning of Bubble- Chamber Negatives, Nuclear Instruments and Methods 20 , (1963), 401-^06. 2. Bo H. McCormick,, The Illinois Pattern Recognition Computer ( ILLIAC III), Digital Computer Laboratory Report Ho. 1^-8, August 20, 19^3 Programming (PAU Simulator) 3. James H, Stein, User's Manual for PAX, an IBM 7090 Program to Simulate the Pattern Articulation Unit of ILLIAC III, Digital Computer Laboratory Report No. 1^7, July 29, 1963 k. James H. Stein, Program Description of PAX, an IBM 7090 Program to Simulate the Pattern Articulation Unit of ILLIAC III, Digital Computer Laboratory File No,, in preparation Programming (Syntactic Model) 5. Ro Narasimhan, A Linguistic Approach to Pattern Recognition, Digital Computer Laboratory Report No. 121, July 10, 1962 60 R. Narasimhan, A Programming Lanaguage for the Parallel Processing of Pictures, Digital Computer Laboratory Report No. 132, January 9> 19^3 7» Ro Narasimhan, Syntactic Descriptions of Pictures and Gestalt Phenomena of Visual Perception, Digital Computer Laboratory Report No. 1^2, July 25, 1963 Programming (Bubble Chamber Automatic Scanning) 80 Ro Narasimhan, A Programming System for Scanning Digitized Bubble- Chamber Negatives, Digital Computer Laboratory Report No. 139* June 2k } 19^3 9. Ro Kevin Rice, A Preliminary Study of PAU Mcirolists in Bubble -Chamber Photographs, Digital Computer Laboratory File No. 506, February 1, 1963 10. R. Narasimhan and Brian Ho Mayoh, The Structure of a Program for Scanning Bubble -Chamber Negatives, Digital Computer Laboratory File No. 507, February 7, 19^3 -39- D 4o 11. Brian H. Mayoh, Bubble- Chamber Scanning Program: Syntax Table for the Compilation Phase of the Main Program, Digital Computer Laboratory File No. 538, May 28, 1963 12. R. Kevin Rice and R, Narasimhan, Bubble -Chamber Scanning Program: J ' 1. LABEL, 2. SEARCH, Stage 1, Digital Computer Laboratory File No. 5^2, June 10, 1963 13. R. Narasimhan and J. P, Fornango, A Preprocessing Routine for Digitized Bubble- Chamber Pictures, Digital Computer Laboratory File No. 558, July 22, 1963 Oscilloscopic Scanner Design lh. Cyril P. Bates and B. H, McCormick, Scanner Digital Control, Digital ' Computer Laboratory File No., in preparation Pattern Articulation Unit (PAU) Engineering J 15. Sylvian R. Ray, The Transfer Memory, Digital Computer Laboratory Report No. 1^5, August l6, 1963 16. B. H. McCormick, Specifications for Thin Film, Passive Element Microcircuit Modules, Digital Computer Laboratory File No. 563, July 31, 1963 17. K. C. Smith and Dennis Hall, Observations of the Operation of a 3 - Bit Bubbling Register, Digital Computer Laboratory File No, 482, August 31, 1962 □ D D 18. K. C. Smith, The Pattern Articulation Unit: Circuit Design of the Iterative Array, Digital Computer Laboratory Report No., in preparation Taxicrinic Unit (TU) 19. K. Ibuki, The Taxicrinic Unit of ILLIAC III: A Tentative Design, Digital Computer Laboratory Report No., in preparation Arithmetic Unit (AU) 20. S. Matsushita and B. H. McCormick, Logical Design of the Main Arithmetic Unit of ILLIAC III, Digital Computer Laboratory File No., in preparation D hi Semiconductor Evaluation and Fast Circuit Design 21. S, Yamada, Cable Driver and Terminator Design, Digital Computer Laboratory Report No. 1^6, August 21, 19^3 22. So Yamada, Performance Characteristics of Fast Logic for TL LIAC III: Basic NAND and NOR Circuits, Digital Computer Laboratory Report No., in preparation 23. S. Yamada, Design of the Program- Controlled Semiconductor and Printed Circuit Board Test Console, Digital Computer Laboratory Report No s , in preparation To receive copies of any of the above listed reports, check those you would like and mail your request to: Digital Computer Laboratory University of Illinois Urbana, Illinois Those reports which are now in preparation will be sent to you as soon as they become available. NAME POSITION (Please Print) COMPLETE ADDRESS DATE