LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 5lO. 84 lifer no. 619- &2 AE R REG T REG GWM > AJdresc ACCESS LOGIC Extension Address > Data Transmit Data <\ HLT/ ' ^RUN Receive Z=> REG j>o REG FILE L Bus V ! ! I II I REG ONES - OVFL CRY CH ALU X Bus c REG C CONTROL IjOGIC TABLE C Figure 1.1 SUE Data Flow Diagram Control Signals M REG Arithmetic and Logic Unit The arithmetic and logic "unit processes sixteen "bits of data in parallel. It has two sixteen bit input data paths designated the XBUS and the YBUS and one sixteen bit output data path designated the LBUS. The XBUS data may come from one of twelve general purpose registers in the register file. The YBUS data is selected using a multiplexor. It may be the contents of the A, R, or T register, or a literal supplied from the literal field of the control word. The ALU can perform one of thirty two functions, sixteen of the functions being logical with the other sixteen being arithmetic. The output may be used to set the carry and overflow flip flops if specified by the two bit C field in the microinstruction. The output of the ALU may be transferred to the same file register specified as the XBUS input and also to either the E, T or A registers. A one bit register called the ones flip flop may also be set when the output of the ALU is all ones. The Register File The register file consists of a set of twelve sixteen bit registers which may be used as input to the ALU XBUS and may be loaded from the ALU LBUS. These registers may be used as general purpose temporary storage with the exception of register eight. This register is special in that it may only be used for a status register. Whenever it is loaded the top four bits are transferred to the bus controller and are used to mask interrupts from I/O devices. Infibus Interface The Infibus interface contains three sixteen bit registers as well as all necessary control logic and drivers to interface to the Infibus. The registers are the A, R and T registers. The A register is the address register. It contains the address of either a memory location or a device register which is to be accessed via the Infibus. The R or receive register receives all data being read via the Infibus. The R register may not be loaded by the microprogram, but only from the Infibus. The T register is the transmit register. It is used as its name implies to transmit data onto the Infibus. The T register also has another special function. It is a shift register which under microprogram control may perform one of eight different types of shifts. Also included within the Infibus interface is a two bit address extension register. This register is an extension to the A register, and contains address bits sixteen and seventeen. It can be loaded from the two low order bits of the LBUS using a special command microstep. Initiation of output to and input from Infibus is performed using special commands and completed by doing a wait for bus access completion microstep. The Infibus interface also contains special logic to allow other master modules on the Infibus to access the register file while the CPU is halted. It also allows other master modules to access the CPU's halt and run flip flops so that they may halt and restart the CPU. Microprogram Control The microprogram control section of the SUE consists of the control store, a table containing rows of sixteen eight bit words used as branch addresses or literal data, three registers and associated logic. The registers are the sixteen hit E register, the twelve hit S register and the thirty-six hit M register. The control store consists of up to 102^ thirty-six hit words divided into pages of 256 words. The 102 k word limit is a physical one and hy moving the control memory to a separate hoard it could be expanded to ^096 words. The table is normally 256 words of eight bits each. However, a slight hardware modification will allow larger table sizes. The table is organized in rows of sixteen words. The entry selected from within a row is determined by the contents of one of four bit fields selected from the E register. The table is used extensively for instruction decoding. The E register is used for encoding the next microinstruction. One of two four bit fields may be ANDed to the X field of the next microinstruc- tion, and one of four four bit fields may be used to select a table row entry. The least significant four bits of the E register also have a special purpose. These four bits may be used as a loop counter which is incremented each time the T register is shifted by a special command. The S or sequence register is the microprogram instruction counter. It contains the address of the next microinstruction to be executed. It may be modified only by performing branch or jump microinstructions. There are no provisions to save and restore the S register for the purpose of returning from microprogram subroutines. The M register contains the encoded microinstruction presently being executed. 8 B. Microcode Description A SUE microinstruction is divided into thirteen fields. The format of the microinstructions is given in Figure 1.2. A brief description of each field is given in this chapter, and a detailed description is given in Appendix B. S Field The S field is the microinstruction sequence control. It may specify that the microinstruction is to he sequential, sequential with a special command, a wait for an Infihus access to complete, an unconditional branch or a conditional jump. T Field The T field specifies the type of ALU function which is to be performed, that is, whether the function is logical or arithmetic. A Field The A field designates one of sixteen logical operations or one of sixteen arithmetic functions to be performed depending on the value of the T field. C Field The C field controls setting of the carry and overflow flip flops and the enabling of the carry bit to the carry input to the ALU. The actual meaning of the C field varies depending on whether the ALU operation is an arithmetic or logical one as determined by the T field. If it is logical the C field allows the carry and overflow flip flops to be cleared and the carry se^. If it is arithmetic the C field designates whether the o cvi k\ -^ LT\ VD t- CO ON 3 LT\ OJ CM ITS Kl OJ 1-^ >H Ph X O EH O H OJ 0) •H H H 15 not used. A description of each of the fields as used by the emulator is given below. Current Mode - Two bit field specifying the current value of address bits l6 and 17 • Previous Mode - Two bit field specifying the previous value of address bits l6 and 17 . Priority - Three bit field containing the processor priority level. A device may not interrupt the processor unless its priority is greater than that given in the priority field of the program status word. Trace - One bit field which when set will cause a software interrupt through location l^o of kernal mode memory after the completion of the current instruction. Condition Codes - Four bit field containing the condition codes. They may be set automatically by instruction execution or set directly by accessing the processor status or by executing a condition code instruction. C. Interrupts Interrupts may be initiated by external hardware devices, by software through the execution of one of several special interrupt instructions, or internally by detection of the trace bit being set, an access to a nonexistent memory location, or by an attempt to execute an illegal instruction. When an interrupt occurs the processor status is pushed onto the system stack followed by the current program counter. The program counter and status word are then loaded from two consecutive memory locations in l£ kemal address space as specified by the interrupting device or internally by the processor. When leaving the interrupt service routine a return from interrupt instruction may be executed which will restore the old program counter and processor status so that program execution may continue where it was interrupted. D. Addressing Modes Many of the PDP-11 instructions contain one or two six bit fields for specifying an operand. The operand field consists of two three bit fields with the right three bits specifying a general register and the left three bits specifying one of eight addressing modes. (See Figure 2.2.) Figure 2.2 PDP-11 Operand Field The addressing modes are: - Register Mode The operand is taken as the contents of the specified register. 1 - Register Deferred The contents of the register are used as the address of the operand. 2 - Autoincrement The contents of the register are used as the address of the operand. The register is then incremented by two 17 if the instruction is a word instruction or by one if it is a byte instruction. A special case is for byte instructions -which specify R6 or R7. In these cases the register is always incremented by two. 3 - Autoincrement Deferred The contents of the register are used to specify a location whose contents are used as the address of the operand. The register is then incremented by two. k- - Autodecrement The register is decremented by two for word instructions and by one for byte instructions unless the register specified was R6 or R7. In these cases it is always decremented by two. The result is then used as the address of the operand. 5 - Autodecrement Deferred The register is decremented by two and the result is used as the address of a location whose contents is the address of the operand. 6 - Indexed The contents of the program counter R7 are used to address a location whose contents when added to the contents of the specified register form the address of the operand. The program counter is then incremented by two. 7 - Index Deferred The contents of the program counter R7 are used to address a location whose contents when added to the contents of 18 the specified register form an address whose contents are the address of the operand. The program counter is then incremented by two. E. Instruction Format To achieve its powerful instruction set the PDP-11 uses a variable format instruction. Seven major instruction formats are used with several others being modified versions of them. These formats are described below, and detailed descriptions of individual instructions are given in Appendix C. The double operand format of Figure 2.3 consists of a four bit operation code, a six bit source field, and a six bit destination field. The top bit of the opcode specifies whether the instruction is to operate on an eight bit byte or on a sixteen bit word. The source and destination fields each contain a three bit register number and a three bit addressing mode as discussed previously. The single operand instruction format shown in Figure 2.h contains a ten bit opcode and a six bit destination field. Again the most significant bit of the opcode specifies whether the instruction is to operate on byte or word data. The destination field is the same as that for the double operand format. The register operand instruction format given in Figure 2.5 is a modified version of the double operand format. The main difference is that one of the operands may only be register mode. A second difference is that there are no byte instructions using this format. Branch instructions use the format shown in Figure 2.6 with a similar format being used by the TPA.P and EMT instructions. The left eight bits contain the opcode and the right eight bits contain a signed offset for oranch instructions and a function field for EMT and TRAP instructions. 19 OP Code 1 i i Source 1 1 1 i 1 Destination i i i i i 15 12 11 6 5 Figure 2.3 Double Operand Instruction Format OP Code Destination -J I ! L 15 6 5 Figure 2.k Single Operand Instruction Format OP Code J L Register Source/Destination 15 9 8 65 Figure 2.5 Register Operand Instruction Format OP Code 1 . 1 1 1 1 1 Offset 1 1 1 1 1 1 1 15 8 7 Figure 2.6 Branch Instruction Format 20 This function field is used by software routines and has no effect on instruction execution. In the case of the branch instructions the offset is multiplied by two and added to the program counter. This allows a forward branch of 127 words or a backward branch of 128 words. The condition code instruction format is used only by the two condition code instructions which allow setting and clearing of condition code bits in the processor status word. As seen in Figure 2.7 the least significant four bits of the instruction specify which bits are to be set or cleared in the processor status word. The subroutine return instruction format uses the format given in Figure 2.8, the least significant three bits specifying the register to be used for the return. The remaining instructions use only an opcode as shown in Figure 2.9. F. New Instructions Although the PDP-11 instruction set is very flexible it was felt that several new instructions were desirable. These instructions require three operands requiring the addition of another instruction format. The format is shown in Figure 2.10 and the new instructions are described in detail in Appendix C. 21 OP Code N Z V C 1 1 1 1 1 1 1 1 1 1 1 15 h 3 Figure 2.7 Condition Code Instruction Format 15 OP Code 1 i Register _J L_ 3 2 Figure 2.8 Subroutine Return Instruction Format OP Code J I i L J L j J Figure 2.9 Miscellaneous Instruction Format ■ 1 OP Code [ 1 1 I I 1 REG 1 REG 2 1 1 1 1 1 ■i REG 3 1 1 Figure 2.10 Triple Operand Register Format 22 CHAPTER III THE EMULATOR This chapter describes the PDP-11 emulator written for the SUE. The emulator includes all of the PDP-ll/UO instructions and four additional instructions as well as all of the necessary firmware to support a memory mapping unit should one he built for the SUE in the future. The full emulator requires 512 words of table space and 1021+ words of control store. A smaller version can also be used which excludes the MTPI, MFPI, MUL, LTV, ASH, ASHC, STM, LDM, BTS and BTM instructions. This version requires only 768 words of control store. The emulator executes instructions at approximately the same speed as the PDP- 11/20. Instructions using register mode are slightly slower than those of the 11/20 while many instructions using other modes are faster. A complete listing of instruction execution times are given in Appendix A. A. Register Allocation The SUE register file contains twelve general purpose registers. The first eight of these registers are used to store the PDP-11 registers. Register six is the stack pointer and register seven the program counter. Register eight is used to store the processor status word. This register is unique in that the four most significant bits are used to mask off I/O interrupts. Register nine is the instruction register. It contains the instruction currently being executed. The remaining two registers 23 are used by the emulator for temporary storage and their contents depend on the instruction being executed and the state of the execution. B. Processor Status Word A description of the PDP-11 processor status word format was given in Chapter II. Because of hardware differences between the SUE and the PDP-11 it was necessary to store the processor status word internally in a format that is different from the PDP-11. The internal format is shown in Figure 3.1. The four most significant bits contain an interrupt mask. This mask is transferred to the bus controller each time register eight is loaded. This is a hardware function and as a result these bits cannot be used for any other function. As used by the emulator the mask corresponds to the priority field as given in Table 3.1. Priority Interrupt Mask Bits 65k 15 Ik 13 22 1 10 Oil 10 10 1 110 111 Table 3.1 Priority Interrupt Mask Encoding Since the processor status word can be accessed directly as an address and also saved in memory during interrupts the processor status word must be reformatted each time it is accessed. The fact that an instruction can 1 1 1 1 1 1 1 1 1 1 OJ 2k o N^ -=J- VD J >> ■P •H to O •H *H ft N o\ O OJ ir\ -P ?h ra ■H 25 access the processor status as an address creates a problem for the SUE because no hardware is provided to detect when the processor status word is being accessed, and the overhead required to check each address in the firmware would be prohibitive. Instead the firmware attempts to access the processor status word as Infibus address 177776o. Since this address in nonexistant a timeout will occur on the bus after two microseconds. At this point a check is made in the firmware to determine if the program was trying to access the processor status. If it was, the status is fetched from register eight, converted from internal format to PDP-11 format and used as the data. This makes access to the status word very slow. However, the status word is seldom accessed as an address. A similar process is used when an attempt is made to write into the status word. C. Memory Mapping and Protection Features The memory mapping features make use of the two additional address lines provided by the SUE. These address lines are normally set to the current mode as specified in the processor status. These lines can be used by a memory mapping device to select a set of registers which would be used for mapping a virtual address given by address lines through l6 into a physical address on the bus. Such a unit would be placed on the bus between the SUE processor and its memory and peripherals. To prevent a normal user from simply changing bits to get into another mode the mode bits are always ORed into the status word whenever it is loaded via an RTI or RTT instruction. This allows each successively lower mode to have control over all modes higher than it. Mode zero is kernal mode, and it has control over all other modes. It is the only mode in which a program can address the status word directly and also the only 26 mode in which the HALT and SPL instructions can be executed. In other modes the HALT instruction will cause an illegal instruction interrupt to occur, and the SPL instruction will be executed as a no-op. Interrupts must be handled differently than on the PDP-ll/UO because the emulator has only one stack register. The PDP-ll/UO pushes the old program counter and status word on the new modes stack. The emulator is forced to push them on the old modes stack since each mode does not have its own stack register. The software must then change the stack pointer and retrieve the old program counter and status word and move it onto its own stack. D. Addressing Modes The emulator contains seven sets of addressing modes. They are required because no microsubroutine linkage is provided in the SUE hardware. There is a set of mode routines for each of the following: single operand word instructions single operand byte instructions double operand word instructions - source mode double operand byte instructions - source mode double operand word instructions - destination mode double operand byte instructions - destination mode single and register operand special instructions The register operand and single operand special instructions include the JSR, JMP, SXT, MTPI, MFPI, MUL, and DIV. The mode routines for these instructions differ from the others in that only the address of the operand is calculated. In all other cases the operand is actually fetched. 27 E. Instruction Decoding Instruction decoding is performed using the microlevel table. A particular row of the table is selected, and a four bit field of the instruction is used to index into that row. The element obtained from the table is then used to either select another row to be used to access the table again in the next microinstruction, or it can be used as a jump address to which the next microinstruction jumps. Because most fields in the PDP-11 instruction set are only three bits wide and are not aligned on a four bit boundary the instruction must often be shifted to align the fields for decoding. Also as a result of the three bit fields many entries within a row in the table are repeated. Decoding begins with the four most significant bits of the instruction. These bits are used to access one of sixteen elements in row seven of the table. The element selected specifies the next row to be used for decoding bits eight through eleven. Decoding of bits twelve through fifteen results in the instructions being dividied into six groups as shown in Figure 3.2. The floating point group is unimplemented and results in the selection of a row in which all of the entries are addresses of the illegal instruction routine. The other groups contain the following instructions: Group CLR, DEC, INC, NEG, TST, COM, ASL, ASR, ADC, SBC, SXT, ROL, ROR, SWAB, BR, BEQ, BNE, BLT, BGE, BLE, BGT, JSR, MARK, RTS, SPL, JMP, BPT, IOT, BTS, RTT, RTI, HALT, WAIT, RESET, MTPI, MFPI, and the condition code instructions. 28 1 I L_ Group (Fig. 3.3) 1-6, E i I l_ Double Operand Word Group (Fig. 3.9) 8 i i i Group 8 (Fig. 3.15) 9-D Double Operand Byte Group (Fig. 3.18) Register Group (Fig. 3.12) Floating Point Group (Unimplement ed ) Figure 3.2 Instruction Decoding of Bits 12-15 29 Double operand word group MOV, CMP, BIT, BIC, BIS, ADD, and SUB Group 8 CLPB, DECB, INCB, NEGB, TSTB, COMB, ASLB, ASEB, ADCB, SBCB, ROLB, RORB, BMI, BPL, BCS, BCC, BVS, BVC, BHT, BLOS, BID, BHIS, EMT, and TRAP Double operand byte group MOVB, CMPB, BITB, BICB, and BISB Group decoding Decoding of bits eight through eleven of group separates the individual branch instructions within the group as well as the JSR and BTS instructions. This is diagrammed in Figure 3.3. The remaining instructions are divided into three groups containing the following instructions : Group 0.0 HALT, WAIT, RTI, BPT, IOT, RESET, RTT, RTS, SPL, SWAB, JMP, and the condition code instructions. Single operand word group CLR, DEC, INC, NEG, TST, COM, ASL, ASR, ADC, SBC, ROR, and ROL Single operand special group MARK, MFPI, MTPI, and SXT The branch instructions need no further decoding so control passes directly to the execution routines. The BTS instruction likewise can be executed without further decoding. The JSR and single operand word group instructions require decoding of their addressing mode. The single operand special instructions also require address mode decoding as well as other decoding. I 1 I Group 0.0 (Fig. 3.h) 1 BR Instruction Execution X BNE Instructi Execution J L BEQ Instructi Execution k _L BGE Instructi Execution 30 BLT Instruction Execution BGT Instruction Execution 7 LE Instruction Execution 8-9 _l L JSR (Fig. 3.13) A-C Single Operand Word Group (Fig. 3.6) ingle Operand Special Group (Fig. 3.8) E-F BTS Instruction Execution Figure 3.3 Group Decoding, Bits 8-11 31 Group 0.0 decoding Bits four through seven are used to further decode the instructions in this group as illustrated in Figure 3.^-. Individual instructions separated are JMP, RTS, SPL, SWAB, and the condition code instructions. The RTS, SPL, and the condition code instructions are executed without further decoding. The JMP and SWAB must have the addressing mode decoded. The SWAB instruction is a normal single operand instruction and is treated as such in any further decoding. However, before control is passed to one of the single operand mode routines the SWAB instruction's opcode is modified by setting bit eight in the instruction. This allows easier decoding into individual instructions after exiting the mode routines. The JMP instruction uses the single operand special mode routines, and like the SWAB instruction the opcode for JMP is also modified. In this case it is modified by setting bit twelve. The remaining instructions in group 0.0 are either illegal opcodes or are part of group 0.0.0. Decoding of this group is shown in Figure 3.5- The group includes the HALT, WAIT, RTI, BPT, I0T, RESET, and RTT instructions as well as nine illegal opcodes. Single operand word group decoding Further decoding of the single operand word instructions is given in Figures 3.6 and 3.7. Only five of the addressing mode routines can be entered directly. The other three modes differ only in that they are indirect modes and require only an additional memory fetch. Decoding into individual instructions is performed using bits six through nine as shown in Figure 3.7- The decoding of the SWAB instruction is the result of the modification to the opcoce as discussed previously. 32 15 12 11 8 7 k i i i 1 1 1 i i i Group 0.0.0 (Jig. 3.5) 1-3 _L Illegal Opcodes k-7 J L JMP (Fig. 3.13) J L SPL Instruction A _1_ _L Clear Condition Code Instruction Execution B Set Condition Code Instruction Execution C-F RTS Instruction Execution SWAB (Fig. 3.6) Figure 3.^ Group 0.0 Decoding, Bits k - 7 33 o HALT Instruction Execution WAIT Instruction Execution J L RTI Instruction Execution IOT Instruction Execution RESET Instruction Execution 6 J 1_ RTT Instruction Execution 7-F _1 BPT Instruction Execution Illegal Opcodes Figure 3.5 Group 0.0.0 Decoding, Bits 0-3 3h o-i _J I u_ Mode (Fig. 3.7) 2-3 _J I L_ Mode 1 (Fig. 3.7) h-7 I I 1 Modes 2, 3 (Fig. 3.7) 8-B I 1 L_ Modes k, 5 (Fig. 3.7) C-F I I I Modes 6, 7 (Fig. 3.7) Figure 3.6 Single Operand Word Instruction Mode Decode 35 1 1 1 R DR Instructic Execution jn 1 i i i R DL Instructic Execution :>n 2 i 1 I A SR Instructs Execution Dn 3 ! 1 1 Ai 3L Instructic Execution >n h-6 i i i Illegal Opcodes 7 i i i St tfAB Instructs Execution .on 8 ! 1 1 c LR Instructic Execution Dn TST Instruction Execution Figure 3.7 Single Operand Word Instruction Decoding 36 Single operand special group decoding Figure 3.8 shows the decoding of the single operand special group. Bits six through nine are used to select the table element, however, since bits eight and nine are fixed the decoding is actually only on bits six and seven. The MAEK is executed with no further decoding while the other three instructions require decoding of the addressing mode. Again opcodes are modified to allow easier decoding into individual instructions later. The SXT instruction is modified by setting bit fourteen, MFPI by setting bits fourteen and fifteen, and the MTPI by setting bits thirteen and fourteen. Decoding of the addressing mode is shown in Figure 3.13. Further decoding of these instructions will be discussed later. Double operand word group decoding The double operand word group decoding is given in Figures 3.9 through 3.H. Double operand instructions require the decoding of two sets of addressing modes. Like the single operand word instructions, the mode routines for modes 3> 5> and 7 are combined with modes 2, k, and 6 respectively. Decoding into individual instructions for execution is given in Figure 3.H. Both word and byte instructions use the same row in the table for this decoding. Register group decoding The register group of instructions is decoded as shown in Figure 3.12. The ASH, ASCH, STM, LDM, and SOB instructions are fully decoded and are executed. The XOR instruction is treated identically to a double operand instruction with a source addressing mode of 0. Thus upon detection of an XOR instruction control is passed directly to the double operand word 37 15 12 11 8 7 6 1 1 1 D l l I MARK Instruction Execution 1 MTPI (Fig. 3.13) MFPI (Fig. 3.13) I i i I SXT (Fig. 3.13) Figure 3.8 Single Operand Special Instruction Decoding 38 o-i I i I Mode (Fig. 3.10) 2-3 I Mode 1 (Fig. 3.10) 3-7 J 1 L Modes 2, 3 (Fig. 3.10) 8-B I I L_ Modes k, 5 (Fig. 3.10) C-F _l Modes 6, 7 (Fig. 3.10) Figure 3.9 Double Operand Word Instruction Source Mode Decoding 39 o-i i i i Mode (Fig. 3.11) 2-3 Mode 1 (Fig. 3.11) k-7 I L Modes 2, 3 (Fig. 3.H) 5-B Modes k, 5 (Fig. 3.H) C-F Modes 6, 7 (Fig. 3.H) Figure 3.10 Double Operand Word Instruction Destination Mode Decoding 0,8,1 J I L Unused 1 J L MOV Instruction Execution 4 L ± CMP Instruction Execution 3 BIT Instruction Execution 1+ J L BIC Instruction Execution BIS Instruction Execution ADD Instruction Execution 1+0 7 J L XOR Instruction MOVB Instruction Execution J L I CMPB Instruction Execution B BITB Instruction Execution BICB Instruction Execution D _L BISB Instruction Execution E SUB Instruction Execution Figure 3.11 Double Operand Instruction Decoding la 0-1 J I MUL (Fig. 3.13) 2-3 DIV (Fig. 3.13) h-5 __l L ASH Instruction Execution 6-7 ASHC Instruction Execution 8-9 XOR (Fig. 3.10) A-B SIM Instruction Execution C-D i i L EDM Instruction Execution E-F _J L SOB Instruction Execution Figure 3.12 Register Group Decoding k2 0-1 J I L Mode (Fig. 3. 1*0 2-3 Mode 1 (Fig. 3.1*0 k-7 Modes 2, 3 (Fig. 3. 1*0 8-B _j Modes k, 5 (Fig. 3. 1*0 C-F Modes 6, 7 (Fig. 3.1*0 Figure 3.13 Single Operand Special Instructions Mode Decoding U3 source mode routine, and any further decoding of the XOR instruction is performed as though it were a double operand instruction. The MUL and DIV instructions require decoding of their addressing modes. This is done as shown in Figure 3.13. Before control passes to one of the mode routines the opcode of the MUL instruction is modified by clearing bit thirteen of the instruction. Special single operand and register group instruction decoding Seven instructions use the single and register operand special mode routines. These include the JSR, JMP, SXT, MUL, DIV, MTPI, and MFPI instructions. Each of these instruction's opcode was modified if necessary so that the four most significant bits are unique. This results in decoding into individual instructions as shown in Figure 3.1^-. Group 8 decoding Group 8 decoding is given in Figure 3.15. After decoding of bits eight through eleven the remaining branch instructions as well as the EMT, TRAP, and BTM instructions are fully decoded. The single operand byte instructions are the only ones requiring further decoding. The modes are decoded as shown in Figure 3.l6. Unlike the mode routines for the word instructions only modes six and seven can be combined. This is because the autoincrements and autodecrements vary depending on whether the mode is direct or indirect. An indirect mode always results in an autoincrement or autodecrement by two while the direct mode may result in an autoincrement or decrement by either one or two depending on which register is being used. Decoding into individual instructions is illustrated in Figure 3.17. hk o i i i_ JSR Instruction Execution 1 J I L JMP Instruction Execution 2-3,8-B,D-F Illegal Opcodes _L SXT Instruction Execution _1 I L_J MUL Instruction Execution J I L MTPI Instruction Execution 7 DIV Instruction Execution MFPI Instruction Execution Figure 3.lU Special Single Operand and Register Group Instruction Decoding J L _L BPL Instruction Execution 1 BMI Instruction Execution 2 BHE Instruction Execution 3 J L BLOS Instruction Execution k J L_ BVC Instruction Execution BVS Instruction Execution Illegal Opcode ^5 BCC Instruction Execution 7 BCS Instruction Execution _L EMT Instruction Execution 9 j_ TEAP Instruction Execution A-C Single Operand Byte Group (Fig. 3.16) E-F _L BTM Instruction Execution Figure 3.15 Group 8 Decoding, Bits 8 - 11 1+6 o-i __l L Mode (Fig. 3.17) 2-3 Mode 1 (Fig. 3.17) k-5 Mode 2 (Fig. 3.17) 6-7 Mode 3 (Fig. 3.17) 8-9 Mode h (Fig. 3.17) A-B J L_ Mode 5 (Fig. 3.17) C-F Modes 6, 7 (Fig. 3.17) Figure 3.l6 Single Operand Byte Instruction Mode Decoding ^7 15 12 8 i 1 i 2-3 i i i i RORB Instruction Execution 1 J L ROLB Instruction Execution 2 ASRB Instruction Execution 3 _L ASEB Instruction Execution h-7 Illegal Opcodes _L CLRB Instruction Execution COMB Instruction Execution Figure 3.17 Single Operand Byte Instruction Decoding A _1 L INCB Instruction Execution B X DECB Instruction Execution J_ _L NEGB Instruction Execution J_ ADCB Instruction Execution E _L SBCB Instruction Execution F TSTB Instruction Execution Double operand byte group decoding Decoding of the double operand byte instructions continues with the decoding of the source mode as shown in Figure 3.18 and the destination mode in Figure 3.19. For the same reason as the single operand byte modes, the double operand byte modes require a separate routine for each mode with the exception of modes six and seven which can be combined. Separation into individual instructions for execution is given in Figure 3.H. F. Instruction Execution Execution of those instructions which do not modify the condition codes is straightforward. Those that do change the condition codes however, require considerable manipulation and testing to determine and set them properly. This is a result of the SUE setting condition codes differently than the PDP-11. Byte instructions are the worst because the SUE does all arithmetic and logic using a full sixteen bits and sets the condition codes accordingly. Execution also presents a problem with storing of the result. It is a problem because it must be determined not only whether the result is to be stored into a memory location or a register, but whether it is to be stored at all. The storing is performed by two routines, one for byte and one for word instructions. Those instructions such as CMP which do not restore the result bypass these routines. To prevent the need for re-evaluating the destination mode the data address is always saved in a register, and to make it easier to determine if the mode was mode all mode routines other than mode routines set bit three in the instruction register. This destroys the actual mode, but it is no longer needed once it has been decoded. Thus after the execution h9 o-i __l I L_ Mode (Fig. 3.19) 2-3 Mode 1 (Fig. 3.19) fc-5 i Mode 2 (Fig. 3.19) 6-7 Mode 3 (Fig. 3.19) 8-9 i i i Mode h (Fig. 3.19) A-B Mode 5 (Fig. 3.19) C-F _J L Modes 6, 7 (Fig. 3.19) Figure 3.18 Double Operand Byte Instruction Source Mode Decoding 50 0-1 J L Mode (Pig. 3.11) 2-3 Mode 1 (Fig. 3.H) l»-5 I L Mode 2 (Fig. 3.11) 6-7 Mode 3 (Fig. 3.H) 8-9 i i i Mode k (Fig. 3.H) A-B I Mode 5 (Fig. 3.H) C-F J I L Modes 6, 7 (Fig. 3.H) Figure 3.19 Double Operand Byte Instruction Destination Mode Decoding 51 determining if the destination mode was is simply a one bit test. If the destination mode is a check must be made to determine if the register specified was the program counter. If it was special action which is described in the next section must be taken. G. Instruction Fetch To increase the speed of the emulator the next instruction is fetched while the current instruction is being executed whenever feasible. This is not done on any instruction which will result or possibly result in the program counter being changed such as in branch instructions and software interrupt instructions. Exceptions to this rule are instructions with a destination mode of which specify register 7> the program counter. In these cases the next instruction is reread in case a change was made to the program counter. H. Interrupts There are two types of interrupts which occur on the PDP-11. These are software generated interrupts and I/O interrupts. An interrupt causes the old processor status and program counter to be stored on the stack and new ones to be loaded from a two word vector in memory. The address of the vector depends on the interrupt which occurs. Software interrupts occur whenever an EMT, TKAP, IOT, or BPT instruction is executed. They also occur after each instruction is executed whenever the trace bit in the processor status word is set, or when an attempt is made to access an illegal address or execute an illegal instruction. The vector address for each software interrupt is predefined in the firmware to those specified for the PDP-11. 52 I/O interrupts occur whenever the bus controller determines that an I/O device is requesting an interrupt on a level which is not masked off by the emulator. When the interrupt bit is detected by the emulator it responds by enabling the interrupt resulting in the I/O device placing its device address on the bus so the CPU can read it. Unlike the PDP-11 the device address is given and not a vector address. Since the emulator requires a vector address it must be calculated from the device address. This is done by extracting bits h, 5, 6, 7, 9> 10 and 11 and shifting them to result in the sequence Bll BIO B9 B7 B6 B5 Bk This does not allow the vector address to be independent of the I/O device address as it is on a normal PDP-11, but this is the only way it can be done without making a hardware change. Each time an interrupt occurs the old PS must be converted into the PDP-11 format and the new PS into the internal format. This conversion must also be done when returning from interrupts or accessing the processor status word directly. To enable the emulator to use the same set of conversion routines for all three cases the routines were implemented as subroutines. Since the SUE does not support subroutines, returns are performed using the table. An offset into the table is loaded into a register before the routine is called and is used to select the return address from the table. This is slow but necessary to avoid the large amount of control store which would be required if multiple routines were used. 53 CHAPTER TV HARDWARE MODIFICATIONS TO IMPROVE PERFORMANCE Although the SUE microprogram format is quite flexible and not highly dependent on the SUE's instruction set, the fact remains that it was not designed to allow easy emulation of the PDP-11 instruction set. As a result there are many minor changes which could he made to the hardware which would result in considerably improved performance with a smaller amount of microstore being required. Most of these changes can be logically implemented very easily while physically it is very difficult because the SUE processor uses a multilayered board. Some of these changes are discussed below. A. Program Status Word As described in Chapter III the internal format of the processor status word used by the emulator differs considerably from the format used by the PDP-11. This difference is the result of the hardware being designed for the status word as used by the SUE instruction set. The SUE uses a four bit mask for the processor priority. This mask occupies the top four bits of the status word. The PDP-11 uses a three bit encoded priority. It would be quite easy to implement a decoding circuit which would set the mask properly. Another problem with the program status results from the fact that the position and order of the N, Z, C and V bits differ between the 5h SUE and the PDP-11. The hardware also requires that the N and Z bits be put into the status word at a different time from the C and V bits. This could easily be changed to allow setting of all four bits at the same time and in the same position as the PDP-11. B. Condition Codes Another difference between the SUE and the PDP-11 is that the condition codes are set differently in some operations. This is especially true with shift operations. The PDP-11 sets the overflow on all types of shifts while the SUE only sets the overflow on the arithmetic shift left. Thus to set the condition codes properly several tests may have to be performed. C. Byte Instructions Closely related to the condition code problem is that of byte instructions. ALU operations on the SUE are always a full sixteen bits. To set the condition codes properly on byte instructions requires considerable testing. Another problem with byte instructions is that the SUE accesses bytes in the opposite order of the PDP-11. The PDP-11 accesses the low byte of a word as an even address while the SUE accesses the low byte as an odd address. This requires the emulator to complement the low address bit every time a byte is fetched from memory. D. Subroutine Capabilities Many routines in the emulator are repeated two or more times. This is especially true with address mode routines. If the SUE had a microprogram subroutine capability it would be possible to use the same set of routines for both single operand and double operand instructions. This would save a considerable amount of control store. 55 E. Exceptional Conditions There are three conditions which must be tested for each instruction executed. These are: (l) test for pending interrupts, (^) test if the halt flip flop has been set, and (3) test if the trace bit is set. Each of these must be tested separately. It would be much faster if a test for any of these conditions could be performed with one microinstruction, and if one of them is set to test further to determine which one is set. F. Registers One of the biggest problems with the SUE is the lack of available registers. Four more registers should be added to the register file to increase the number from twelve to sixteen. It would also be desirable to be able to load the R register with the ALU output. This would allow register data and data from memory to be handled in the same way. G. Octal Oriented Fields Probably the hardest modification to make would be to make the fields oriented toward octal numbers rather than hexadecimal numbers. This would allow easier decoding with less table space. 56 LIST OF REFERENCES [1] SUE Computer Handbook, Lockheed Electronics Company, Los Angeles, California, 1972. [2] Microprogramming Guidelines for the SUE 1110 Micro-Processor, SUE Application Memo Number 101 , Lockheed Electronics Company, Los Angeles, California, 1972. [3] Snyder, F. G., The NPL 110 Processor, Interdepartmental Communication AS-31, Lockheed Electronics Company, Los Angeles, California, October 22, 1971. [k] SUE 1110 Processor Logic Drawings, Lockheed Electronics Company, Los Angeles, California, 1972. [5] PDP- Li/20 Processor Handbook, Digital Equipment Corporation, Maynard, Massachusetts, 197L [6] PDP-ll/Uo Processor Handbook, Digital Equipment Corporation, Maynard, Massachusetts, 1972. [7] PDP- H/l+5 Processor Handbook, Digital Equipment Corporation, Maynard, Massachusetts, 197L 57 APPENDIX A INSTRUCTION TIMING Branch Instruction Timing Mnemonic No Branch Forward Backward BR 1.77 us 1.80 us BEQ 1.65 us 2.03 us 2.06 us BNE 1.65 us 2.03 us 2.06 us EMI I.65 us 2.03 us 2.06 us BPL 1.65 us 2.03 us 2.06 us BCS I.65 us 2.03 us 2.06 us BCC I.65 us 2.03 us 2.06 us BVS I.65 us 2.03 us 2.06 us BVC I.65 us 2.03 us 2.06 us BIT 1.90 us 2.1+2 us 2.1+5 us BGrE 2.00 us 2.29 us 2.32 us BLE 2.16 us 2.68 us 2.71 US BGT 2.13 us 2.55 us 2.58 us Double Operand Instruction Timing Instruction Time = Execution Time + Source Time + Destination Time Double Operand Execution Times Mnemonic Time Mnemonic Time BIT 1.91 us BITB 2.78 us BIC 2.1+3 us BICB 3.30 us BIS 2.1+3 us BISB 3.30 us MOV 2.30 us MOVB 2.69 us CMP 2.30 us CMPB 2.95 us ADD 2.72 us SUB 2.72 us XOR 2.1+3 us (sc >urce mode is alway s 0) 58 Double Operand Source and Destination Times Source Mode 1 2 3 h 5 6 7 Word Byte 0.39 us 0.39 us 0.91 us 0.91 us 0.91 us 1.01+ us 1.59 us 1.U6 us O.78 us 1.30 us 1.59 us 1.H6 us 1.59 us l.k6 us 2.^7 us 2.31 us Destination Word 0.39 us 1.13 us 1.13 us I.98 us 1.13 us I.98 us I.98 us 2.83 us Byte 0.52 us 1.00 us I.56 us I.85 us I.56 us I.85 us I.85 us 2.70 us Single Operand Instruction Timing Instruction Time = Execution Time + Destination Time Mnemonic Time CLR 2.82 us COM 3.11 us TST 2.17 us INC 3 . 11 us DEC 3.11 us WEG 3.11 us ADC 3.27 us SBC 3.50 us R0L 3.60 us R0R 3.79 us ASL 3.21 us ASR 3.66 us SWAB 3.99 us Mnemonic Time CLRB 2.97 us COMB 3.21 us TSTB 2.17 us INCB 3.37 us DECB 3.50 us NEGB 3.89 us ADCB 3.89 us SBCB U.02 us ROLB 3.63 us RORB 3.92 us AS LB 3.92 us ASRB 4.05 us Single Operand Destination Modes Mode 1 2 3 5 6 7 Word 0.39 us 1.00 us 1.20 us 1.81 us 1.^6 us 2.0U us 1.81 us 2.70 us Byte 0.52 us 1.00 us l.k6 us I.85 us 1.59 us I.85 us 1.95 us 2.70 us 59 JSR, JMP, and SXT Instruction Times Instruction Time = Execution Time + Source Time Execution Times Mnemonic Time JSR