LIBRARY OF THE 
 
 UNIVERSITY OF ILLINOIS 
 
 AT URBANA-CHAMPAIGN 
 
 510.84 
 
 Ijt'6r 
 
 no. 715-721 
 cop. Z 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/networktransduct719hohu 
 
Kb, 7/^ 
 
 uiucDcs-R-75-719 
 
 'yjt&sCjf 
 
 1 
 
 NETWORK TRANSDUCTION PROGRAMS BASED ON 
 
 CONNECTABLE AND DISCONNECTABLE CONDITIONS 
 
 WITH FAN-IN AND PAN-OUT RESTRICTIONS 
 
 (A description of NETTRA-G1-FIFO and 
 
 NETTRA-G2-FIF0) 
 
 KEITH R. HOHUIIN 
 
 April, 1975 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, ILLINOIS 
 
 IHE LIBRARY OF THE 
 
 JUN 3 1975 
 
 UNIVERSITY OF ILLINOIS 
 
UIUCDCS-R-T5-719 
 
 NETWORK TRANSDUCTION PROGRAMS BASED ON 
 
 CONNECTABLE AND DISCONNECTABLE CONDITIONS 
 
 WITH FAN-IN AND FAN-OUT RESTRICTIONS 
 
 (A description of NETTRA-G1-FIFO and 
 
 NETTRA-G2-FIF0) 
 
 KEITH R. HOHULIN 
 
 April, 1975 
 
 Department of Computer Science 
 University of Illinois at Urban a -Champaign 
 Urbana, Illinois 
 
 This work was supported in part by the National Science Foundation under 
 Grant No. NSF-GJ-40221. 
 
11 
 
 ACKNOWLEDGEMENT 
 
 The author would like to express his gratitude to Professor 
 Saburo Muroga for his guidance during the preparation of this paper as 
 well as his careful reading and constructive criticism which helped to 
 improve the original manuscript. The author also expresses his gratitude 
 to J. Culliney, Y. Kambayashi, J. Legge and H.C. Lai who developed the 
 basic algorithms and programs used in the study described in this paper. 
 
Ill 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. THE PROGRAMS 3 
 
 2.1 NETTRA-G1-FIFO 3 
 
 2. 2 NETTRA-G2-FIF0 9 
 
 3. EXPERIMENTAL RESULTS 12 
 
 3.1 An Outline of Subroutine MAIN for 
 
 NETTRA-G1-FIF0 and NETTRA-G2-FIF0 12 
 
 3.2 The Input Data Cards 15 
 
 3. 3 Results of Computer Experiments 21 
 
 REFERENCES 36 
 
 APPENDIX: AN EXAMPLE WITH INCOMPLETELY SPECIFIED 
 
 OUTPUT FUNCTIONS 38 
 
CHAPTER 1 
 INTRODUCTION 
 
 Recently, network "transduction" procedures for the synthesis 
 of networks with many NOR (NAND) gates have been studied extensively 
 [l]~[lO]. One such procedure uses the concept of compatible sets of 
 permissible functions as a basis for the development of conditions for 
 the connectability and disconnectability of the connections in a network. 
 (The connections in a network include both the connections from the 
 external variables to the gates and the interconnections among the gates.) 
 The theoretical development of this procedure (which is known as PROCIl) 
 is given in [k] and two computer programs based on PROCIl (known as 
 NETTRA-G1 and NETTRA-G2) are presented in [5]. 
 
 One application of the network transduction approach to logical 
 design is the synthesis of networks whose gates have fan-in and/or fan- 
 out restrictions. Several procedures which, when given a network, solve 
 its fan-in and fan-out problems have been developed and programmed by 
 J. Legge at the University of Illinois [13]. The program which implements 
 
 these procedures will be referred to in this paper by the name "FIFO". 
 The existance of FIFO allows the following approach to be used to imple- 
 ment fan-in and fan-out restrictions into NETTRA-G1 and NETTRA-G2: 
 obtain an initial network, use FIFO to solve the fan-in and/ or fan-out 
 
 t Refer to [l] [h] for the definitions of terminology. 
 
 tt The program called FIFO in this paper consists of subroutine JEFF and 
 all subroutines controlled by JEFF in [13]. 
 
problems of the initial network, and, finally, apply a modified version 
 of PROCII (known as PRIIFF) which maintains the fan-in and fan-out 
 restrictions during the computation. Networks synthesized using a com- 
 bination of FIFO and PRIIFF generally contain fewer gates than networks 
 synthesized by FIFO alone. The results of experiments run on the com- 
 puter using PRIIFF and FIFO in NETTRA-G1 and NETTRA-G2 are given in 
 Chapter 3. The versions of NETTRA-G1 and NETTRA-G2 which include PRIIFF 
 and FIFO (i.e., fan-in and/or fan-out restrictions) will be referred 
 to by the names NETTRA-G1-FIF0 and NETTRA-G2-FIF0, respectively. 
 
 Chapter 2 documents the changes which were made to PROCII so 
 that the fan-in fan-out restrictions of the networks being transduced 
 are not exceeded (i.e., the changes needed to obtain PRIIFF from PROCII). 
 The changes made to a subroutine of NETTRA-^ called PROCIV are also 
 discussed in chapter 2. 
 
 Another application of the network transduction approach is the 
 synthesis of networks whose output functions have "don't care" conditions 
 (i.e., networks with incompletely specified output functions). The results 
 of using NETTRA-G1-FIF0 and NETTRA-G2-FIF0 for an example with incom- 
 pletely specified output functions are given in the Appendix. 
 
CHAPTER 2 
 THE PROGRAMS 
 
 Both NETTRA-G1 and NETTRA-G2 use subroutine PROCII as a basis for 
 implementing their respective transduction procedures. The primary dif- 
 ference between NETTRA-G1 and NETTRA-G2 is that NETTRA-G2 through its 
 subroutine PROCIV concentrates on removing specific gates from the network 
 under consideration while NETTRA-G1 does not attempt to remove specific 
 gates. The incorporation of FIFO and PRITFF into NETTRA-G1 and NETTRA-G2 
 allows networks with fan-in and fan-out restrictions to be synthesized 
 using the network transduction approach. The discussion in this chapter 
 assumes that the reader has a general knowledge of the information con- 
 tained in [1] [k] [5]. Sections 2.1 and 2.2 discuss NETTRA-G1-FIF0 and 
 NETTRA-G2-FIF0, respectively. 
 
 2.1 NETTRA-G1-FIF0 
 
 The program NETTRA-G1-FIF0 consists of the following subroutines: 
 MAIN, CONCCO, ELANDO, MINI2, RNONES, SUBNET, OUTPUT, PROCII, FIFO and 
 PRIIFF. The general organization of NETTRA-G1-FIF0 is shown in Fig. 2. 1.1. 
 An arrow from block i to block j indicates that the subroutine represented 
 by block i calls the subroutine represented by block j . The functions 
 of subroutines MAIN, CONCCO, ELANDO, MINI2, RNONES, SUBNET, OUTPUT and 
 PROCII are discussed in [5]. FIFO is presented in [13]. 
 
 The definitions given below will facilitate the discussion of 
 the flowchart of PRIIFF which appears in Figs. 2.1.2 and 2.1.3. 
 

 
 ■* 
 
 
 
 
 
 
 
 >fc 
 
 
 
 FIFu 
 
 >* 
 
 MAIim 
 
 f 
 
 
 
 OUTPUT 
 
 
 w 
 
 
 PROCII 
 
 SUBNET 
 
 
 PRIIFF 
 
 «S» 
 
 K. 
 
 
 c 
 
 
 
 ) 
 
 i 
 
 
 
 
 MOH2 
 
 
 
 "n 
 
 
 C t 
 
 v 
 
 ^ 
 
 
 
 
 
 
 CONCCO 
 
 
 
 J 
 
 >h. 
 
 
 
 ^ 
 
 
 
 
 
 
 RNONES 
 
 
 
 
 
 
 
 / 
 
 \ 
 
 
 
 
 
 
 
 
 
 ■^ 
 
 EIAKT 
 
 DU 
 
 k. 
 
 
 
 
 
 Fig. 2.1.1 General Organization of the Program NETTRA-G1-FIF0. 
 
1. FI is the maximum fan-in for each gate in the network. 
 
 2. FO is the maximum fan-out for each gate which is not 
 an output gate. 
 
 3. F00 is the maximum fan -out for each output gate. 
 
 k. FOX is the maximum fan -out for each external variable. 
 
 5. GCO is the gate in the network which is currently 
 being considered by PRIIFF. 
 
 6. LIST L is a list of the essential inputs to gate GCO, 
 where an input to GCO is defined to be essential if 
 the output function of GCO is not in the compatible 
 set of permissible functions for GCO when that input 
 is disconnected from GCO (see [h], [5] for details). 
 The elements of the list are ordered by the decreasing 
 number of essential l's they contain. 
 
 7. LIST C is a list of gates and external variables 
 which are connectable to gate GCO. The elements of 
 LIST C are ordered by the decreasing number of O's 
 of GCO they cover. 
 
 8. The array LI PREP contains the number of immediate 
 predecessors both gates and external variables of 
 each gate and external variable in the network 
 (of course external variables do not have any 
 immediate predecessors). Thus, LIPRED(l)=J if gate 
 or external variable I has J inputs (LIPRED(l)=0 
 for all external variables ) . Array LIPRED has 
 entries for the external variables to make it uniform 
 with LISUCC (defined below). 
 
 9. The array LISUCC contains the number of immediate 
 successors of each gate and external variable in the 
 network. Thus, LISUCC ( I )=J if gate or external 
 
variable I is connected to J gates. Arrays 
 LI.PRED and LISUCC are updated each time the 
 network configuration changes. 
 
 Blocks numbered 1 through 10 and 12 through 23 in Figs. 2.1.2 
 and 2.1.3 are identical to the blocks numbered 1 through 10 and 12 
 through 23 in Figs. 2.1.1.1 and 2.1.1.2 of [5]. That is, it was not 
 necessary to make any changes to these blocks in order to convert 
 PROCII to PRIIFF. Since a complete discussion of blocks numbered 1 
 through 23 is given in [5], only block 2k and the changes made to block 
 11 will be discussed below. 
 
 In block 11 a search is made for all gates and external variables, 
 which are effectively connectable to gate GCO. A list of all such gates 
 and external variables is stored in LIST C as described in the discussion 
 of block 11 given in [5 ] . In addition to the conditions of effective 
 connectability given in [k] , the following conditions must also be 
 imposed: if the value of LISUCC for any output gate, non-output gate or 
 external variable is equal to F00, F0 or FOX, respectively, then that 
 gate or external variable is not effectively connectable to GCO and can- 
 not be listed in LIST C. This condition prevents any element P of LIST C 
 which is connected to GCO in block 15 from exceeding its fan-out limit. 
 Also, EFFCON is chosen from LEST C in block 19 so that no fan-out problems 
 occur when EFFCON is connected to GCO in block 21. 
 
 Block 19 searches LIST C for a gate or external variable called 
 EFFCON to connect to GCO. To prevent gate GCO from exceeding its fan-in 
 limit, the value of LIPRED(GCO) is checked in block 2k. If GCO already 
 has FI inputs, the program goes to block 23 rather than block 19« It 
 should also be noted that no fan-in probelms occur for GCO in block 15 
 since input TH is disconnected before input P is connected. 
 
( START V 
 
 FORM 
 GORDER 
 
 TRY TO 
 
 REMOVE 
 
 REDUNDANT 
 
 CONNECTIONS 
 
 UPDATE 
 ARRAYS 
 
 C 
 
 GCO = 
 
 GORDER 
 
 (GCOUNT) 
 
 INITIALIZE 
 
 COUNTER: 
 CGOUNT= 
 
 RETURN 
 
 ; 
 
 FUNCTIONS, REMOVE 
 
 ANY UNNECESSARY 
 INPUTS, AND UPDATE 
 
 GSMALL OF ALL 
 GATES FEEDING GCO 
 
 Fig. 2.1.2 Generalized Flowchart of PRIIFF. 
 
10 
 
 f START V 
 
 -► 
 
 ELIMINATE NON-ESSENTIAL 
 INPUTS, ORDER OTHERS 
 (IN A "LIST L") BY 
 DECREASING NUMBERS 
 OF ESSENTIAL l's 
 
 11 
 
 LIST ALL CONNECTABLE 
 FUNCTIONS (IN A "LIST C") BY 
 DECREASING NUMBERS OF O's 
 ' (IN GCO) COVERED. 
 ELIMINATE ANY SMALLER 
 THAN OTHERS . DO NOT PUT I 
 IN LIST C IF FAN-OUT 
 FOR I EQUALS LISUCC (i). 
 
 TRY TO REPLACE AN 
 ELEMENT, TH, FROM 
 LIST L WITH AN 
 ELEMENT, P, FROM 
 
 LIST C 
 
 DISCONNECT TH 
 FROM GCO 
 CONNECT P 
 
 RE-EVALUATE 
 
 LIST L AND 
 
 REMOVE EFFCON 
 
 FROM LIST C 
 
 I 
 
 CONNECT EFFCON 
 TO GCO 
 
 SEARCH LIST C FOR AN 
 APPROPRIATE EFFECTIVE- 
 LY CONNECTABLE GATE OR 
 EXTERNAL VARIABLE, 
 EFFCON 
 
 23 
 
 — m 
 
 UPDATE GSMALL FOR 
 THOSE GATES STILL 
 FEEDING GCO 
 
 <G0 TO ^ 
 BLOCK 3 J 
 
 Fig. 2.1.3 Details of Block 9 of PRIIFF Flowchart in Fig. 2.1.2. 
 
2.2 NETTRA-G2-FIF0 
 
 The program known as NETTRA-G2 -FIFO consists of the following 
 subroutines: MAIN, CONCCO, EIANDO, MINK, RNONES, SUBNET, OUTPUT, PROCII, 
 FIFO, PRIIFF and PROCIV. The general organization of NETTRA-G2-FIF0 is 
 shown in Fig. 2.2.1. As before an arrow from block i to block j indicates 
 that the subroutine represented by block i calls the subroutine repre- 
 sented by block j. Subroutines MAIN, CONCCO, EIANDO, MINI 2 , RNONES, 
 SUBNET, OUTPUT, PROCII, FIFO and PRIIFF of NETTRA-G2-FIF0 are identical 
 to the subroutines with the same names in NETTRA-G1-FIF0 . 
 
 PROCIV is a simple subroutine which controls the application 
 of PROCII and PRIIFF to the network. A flowchart for PROCIV is given in 
 Fig. 2.2.2 o Blocks numbered 1 through 7 are identical to blocks numbered 
 1 through 7 of Fig. 2.2.1.1 of [5] and, thus, will not be discussed here. 
 
 In block 8 the value of a variable called FFFLAG is checked to 
 determine whether PROCIV calls PROCII or PRIIFF. If FFFLAG=1, then the 
 program is to maintain the fan-in and fan-out restrictions on the network 
 and PRIIFF is called. Otherwise, there are no fan-in fan-out restrictions 
 to be maintained so PROCII is called. 
 
 In block 9 PRIIFF is called to attempt to remove gate PORDER(l) 
 from the network. The action taken by PRIIFF is identical to the action 
 taken by PROCII in block 7 (described in [5]) except that PRIIFF main- 
 tains the fan-in fan -out requirements of the gates in the network (as 
 described in the discussion of NETTRA-G1-FIF0 in section 2.1). 
 
10 
 
 FIFO 
 
 MAIN 
 
 OUTPUT 
 
 PROCIV 
 
 PRIIFF 
 
 MINI2 
 
 PROCII 
 
 SUBNET 
 
 CONCCO 
 
 RNONES 
 
 — T" 
 
 ELANDO 
 
 t \ 
 
 Fig. 2.2.1 Generalized Flowchart of the Program NETTRA-G2-FIF0, 
 
11 
 
 c 
 
 START 
 
 CALL MENI2 TO COMPUTE 
 PERMISSIBLE FUNCTION 
 VECTOR FOR EACH GATE 
 
 COUNT THE NUMBER 
 OF l's IN THE 
 PERMISSIBLE FN. 
 FOR EACH GATE 
 
 ORDER GATES IN AN ARRAY 
 "PORLER" BY INCREASING 
 NUMBERS OF l's IN 
 PERMISSIBLE FUNCTION 
 VECTORS 
 
 CALL PROCII 
 FOCUSING ON 
 REMOVAL OF 
 GATE PORDER(l) 
 
 CALL PRIIFF 
 
 FOCUSING ON 
 REMOVAL OF 
 GATE PORDER(l) 
 
 Fig. 2.2.2 The Flowchart for PROCIV. 
 
12 
 
 CHAPTER 3 
 EXPERIMENTAL RESULTS 
 
 The IBM 360/75J at the University of Illinois was used to run 
 experiments on NETTRA-G1-FIF0 and NETTRA-G2-FIF0. All subroutines in 
 the programs were compiled in FORTRAN H level 21.7 (0PT=2) with the 
 University of Illinois system providing timing subroutines with entry 
 names STIMEZ and KTIMEZ. The results of these experiments are given in 
 section 3.3. Section 3.1 provides additional details about NETTRA-G1-FIF0 
 and NETTRA-G2-FIF0, and section 3.2 discusses the input data cards 
 needed to use the programs. 
 
 3.1 An outline of Subroutine MAIN for NETTRA-G1-FIF0 and NETTRA-G2-FIF0 
 
 Generalized flowcharts for NETTRA-G1-FIF0 and NETTRA-G2-FIF0 
 were given in Fig. 2.1.1 and Fig. 2.2.1, respectively. Those diagrams 
 show which subroutines can call which subroutines but they provide little 
 indication of the actual flow of the program. Figures 3.1.1(a) and 
 3.1.1(b) outline the order in which subroutine MAIN of Fig. 2.1.1 and 
 Fig. 2.2.1 calls suboutines PROCII, FIFO and PRIIFF of Fig. 2.1.1 and 
 subroutines PROCIV and FIFO of Fig. 2.2.1, respectively. The notation 
 PROCIV (PROCII) means that MAIN calls PROCIV and PROCIV calls PROCII. 
 
 NORNET is the name of a subroutine which is used to provide the 
 initial network in both NETTRA-G1-FIF0 and NETTRA-G2-FIF0. NORNET 
 synthesizes the Universal network which realizes a given set of one or 
 more output functions (which are specified as described in section 3.2). 
 
13 
 
 #■* 
 
 *-* 
 
 (a) 
 
 (b) 
 
 Fig. 3.1.1 (a) The order of the subroutines called by MAIN in NETTRA-G1-FIF0, 
 (b) The order of the subroutines called by MAIN in NETTRA-G2-FIF0. 
 
 These loops are followed until the respective subroutine can not further 
 reduce the cost of the network. 
 
 ** These loops are followed at least ITER-1 times. 
 
Ik 
 
 It should be noted that there are many other networks which can be used 
 as an initial network. One example is a three level network with the 
 minimum number of gates which can be found using a program called TANT 
 [ll] [l2], NORNET was used in these experiments because it has a simple 
 structure and requires a short computation time. 
 
 PROCTI is called by NETTRA-G1-FIF0 and PROCIV (PROCTl) is called 
 by NETTRA-G2-FIF0 before FIFO is called in Fig. 3.1.1 to reduce the 
 number of gates in the network which must be considered by FIFO. 
 
 The loops in Fig. 3.1.1 marked by a single asterisk (*) are 
 followed until there is no further reduction in the cost of the network. 
 The cost of a network is defined as A xR + B xC where A is the cost coeffi- 
 cient for gates, R is the number of gates in the network, B is the cost 
 coefficient for connections, and C is the number of connections. The 
 values of A and B are provided on the input data cards (see section 3.2). 
 Thus, for example, PROCII is called repeatedly by MAIN of NETTRA-G1-FIF0 
 until it cannot further reduce the cost of the network. 
 
 The two loops in Fig. 3.1.1 marked with two asterisks (**) are 
 followed a minimum of ITER-1 times where ITER is specified by the user 
 on the input data cards (see section 3.2). These loops will be followed 
 more than ITER-1 times as long as the cost of the network derived by 
 PRIIFF or PROCIV (PRIIFF) continues to decrease. Thus the action of 
 MAIN of NETTRA-G1-FIF0 can be summarized as follows: NORNET is called 
 to provide the initial solution, PROCII is called repeatedly until there 
 is no further improvement, FIFO is called to solve any fan-in fan-out 
 problems in the network, PRIIFF is called repeatedly to reduce the cost 
 of the network while maintaining the fan-in fan-out restrictions, PROCII 
 is called again, etc. NETTRA-G1-FIF0 stops when the loop marked with 
 
15 
 
 two asterisks (*-*) has been followed ITER-1 times or when the cost of 
 the network derived by PRIIFF stops decreasing. 
 
 3.2 The Input Data Cards 
 
 Chapter 5 of [5 ] gives a general discussion of the input data 
 cards for NETTRA-G1 and NETTRA-G2. However, some of the features described 
 in that chapter have not been implemented in the current versions of the 
 programs, and some changes in the input data were necessary in order to 
 implement fan-in fan-out restrictions. Thus a complete discussion of 
 the input data cards necessary to use NETTRA-G1-FIF0 and NETTRA-G2-FIF0 
 (with NOKNET providing the initial solution) is given in this section. 
 
 The order of the input data cards for one problem is shown in 
 Fig. 3.2.1 where a problem is defined as the synthesis by NETTRA-G1-FIF0 
 or NETTRA-G2-FIF0 of networks which realize a given set of one or more 
 switching (output) functions. The data cards for each problem consist 
 of a title card, a parameter card, and functions cards. The user can 
 run several problems at a time by concatenating the input data cards. 
 
 3.2.1 The Title Card 
 
 Each problem must have exactly one title card which may contain 
 any suitable title for the problem. The contents of the title card will 
 be printed as a heading for the output. NETTRA-G1-FIF0 and NETTRA-G2-FIF0 
 do not attempt to obtain any information about the problem for the title 
 card. 
 
 3.2.2 The Parameter Card 
 
 This card contains ten problem parameters each of which occupies 
 a field of four columns. All numbers on the parameter card are read 
 
16 
 
 FUNCTION CARD(S) 
 
 LAST OUTPUT FUNCTION 
 
 FUNCTION CARD(S) 
 
 FIRST OUTPUT FUNCTION 
 
 PARAMETER CARD 
 
 TITLE CARD 
 
 Fig. 3.2.1 The Input Deck for One Problem. 
 
17 
 
 using a FORTRAN I format which requires that they be right justified in 
 their assigned fields to be read correctly. 
 
 (a) N 
 
 N, punched in columns 1 through U, is the number 
 of external variables of the given switching (output) f unc- 
 tion (s). Theoretically the programs can handle functions 
 with any number of external variables , but the current ver- 
 sions of NETTRA-G1-FIF0 and NETTRA-G2-FIF0 are designed 
 for a maximum of N=5. The dimensions of certain arrays in 
 the programs could be increased to accommodate functions 
 with values of N greater than five. 
 
 (b) M 
 
 M is the number of output functions in the net- 
 work and is punched in columns 5 through 8. Both NETTRA- 
 G1-FIF0 and NETTRA-G2-FIF0 are designed to handle multiple 
 output networks. It should be noted that arrays in the 
 current versions of the programs are dimensioned so that 
 the maximum allowable value for the sum of the number of 
 gates and the number of external variables in the network 
 is sixty. 
 
 (c) A and B 
 
 A is a non -negative cost coefficient for the 
 gates in the network and is punched in columns 9 through 
 12. B, punched in columns 13 through 16, is a non- 
 negative cost coefficient for the connections in the net- 
 work. Thus the cost of a network is calculated as 
 
18 
 
 
 Network Reduction Problem 
 
 Values of A and B 
 
 1. 
 
 Reduce the number of gates only. 
 
 A= 1 and B= 
 
 2. 
 
 Reduce the number of gates 
 primarily, then reduce the 
 number of connections . ' 
 
 A = 1000 and B = 1 
 
 3. 
 
 Reduce the number of connections 
 only. 
 
 ,A= and B= 1 
 
 k. 
 
 Reduce the number of connections 
 primarily, then reduce the 
 number of gates secondarily. 
 
 A = 1 and B = 1000 
 
 5. 
 
 Reduce the sum of the number of 
 gates and the number of 
 connections . 
 
 A=B=1 
 
 Table 3.2.1 Typical Combinations of Values for A and B for Different 
 Network Reduction Problems . 
 
 t NETTRA-G1-FIF0 and NETTRA-G2-FIF0 are oriented toward this reduction 
 problem, so the user will probably find this combination of A and B 
 the most useful. 
 
19 
 
 COST = AxR + BxC where R is the number of gates in the 
 network and C is the number of connections in the network. 
 Typical combinations of values for A and B are given in 
 Table 3.2.1. 
 
 (d) UC 
 
 UC, punched in columns 17 through 20, indicates 
 whether or not the complements of the external variables 
 are available. If the networks are to have uncomplemented 
 external variables only, then columns 17 through 20 must 
 be blank . If anything is punched in columns 17 through 
 20, the programs will include both the complemented and 
 uncomplemented variables in the networks. A convenient 
 notation is to punch the letter "C" in column 20 if the 
 complemented variables are to be available. 
 
 (e) PI, F0, F00 and FOX 
 
 FI, F0, F00 and FOX (punched in columns 21 
 through 2k, 25 through 28, 29 through 32 and 33 through 
 36, respectively) specify the maximum allowable values for 
 the fan-in of gates, the fan-out of non-output gates, the 
 fan-out of output gates and the fan-out of external vari- 
 ables, respectively. If no fan-in or fan-out restrictions 
 are required then the appropriate fields can either be 
 left blank or filled with a large integer. If one or more 
 of these four fields are blank, the programs will set the 
 appropriate variables to 100. Since a blank field is read 
 as an integer zero (0) in FORTRAN I format, integer zero 
 
20 
 
 cannot be used to specify a fan-in or fan-out value of 
 zero. Thus, it is necessary to punch a negative integer 
 in the appropriate field in order to specify a fan-in or 
 fan-out of zero. Upon reading a negative value, the pro- 
 grams will set the appropriate value to zero. 
 
 (f) ITER 
 
 If ITER is specified as an integer, i, then 
 loops in Fig. 3.1.1 which are marked with a double 
 asterisk (■**) will be followed a minimum of i-1 times as. 
 discussed in section 3*1. ITER is punched in columns 37 
 through kO. 
 
 3.2.3 The Function Cards 
 
 Subroutine NORNET reads the function card(s) which contain the 
 truth table(s) for the output function (s). The truth table for each 
 output function must be punched (one column for each value ) beginning 
 in the first column of each card. The number of cards needed for each 
 function depends upon the number of variables (in general the truth 
 table for an n variable function has 2 values). For example, four cards 
 are needed for an eight variable function (the current version of NORNET 
 
 o 
 
 can handle functions with up to eight variables) since 2 =256, while 
 
 5 
 only one card is needed for a five variable function since 2 =32. 
 
 The truth table values must be punched in the following order (in this 
 
 case for a three variable function): f(0,0,0), f(0,0.l), .„., f(l,l,0), 
 
 f(l,l,l). 
 
 t Since NETTRA-G1-FIF0 and NETTRA-G2-FIF0 can handle networks with incom- 
 pletely specified output function, the truth tables can have three values: 
 zero (0), one (l), or don't care (*). 
 
21 
 
 3.3 Results of Computer Experiments 
 
 NETTRA-G1-FIF0 and NETTRA-G2-FIF0 were used to obtain networks 
 for thirty h- variable functions and thirty 5-variable functions using 
 several different combinations of fan-in and fan-out values. All sub- 
 routines were compiled using the FORTRAN H compiler level 21.7 (OPT =2) 
 with the University of Illinois system providing timing subroutines with 
 entry names STIMEZ and KTIMEZ. NETTRA-G1-FIF0 requires about 230K bytes 
 of core storage with about 115K bytes used by the actual program instruc- 
 tions and about 115K bytes used for stored data. NETTRA-G2-FIF0 requires 
 about 232K bytes of core' storage with about 117K bytes used by the actual 
 program instruction and about 115K bytes used for stored data. 
 
 Tables 3.3.1 through 3.3.^ summarize the results of the experi- 
 ments described above. Each table contains several columns. The column 
 entitled FUNCTION (HEXADECIMAL) gives the hexadecimal representation of 
 the truth table for each function (kkFl = 0100101011110001 ) . The cost 
 of the Universal network derived by N0RNET for each function is given 
 in the column labeled ORIGINAL NETWORK (N0RNET) . In all of these tables 
 the cost is defined as 1000 x R + C (A = 1000 and B=l) where R is the 
 number of gates and C is the number of connections. Thus a network with 
 ten gates and fifty connections has a cost of 10050. 
 
 The columns labeled NETTRA-G1-FIF0 and NETTRA-G2-FIF0 each 
 consist of two subcolumns. Subcolumn FIFO lists for each function the 
 lowest cost network derived by FIFO when it is called by MAIN as part 
 of NETTRA-G1-FIF0 or NETTRA-G2-FIF0 (as shown in Fig. 3.1.1(a) and (b) 
 respectively). Similarly, subcolun PRIIFF lists for each function the 
 lowest cost network derived by PRIIFF when it is called by MAIN of 
 
22 
 
 
 Ph 
 
 o- 
 
 Er- 
 
 CO 
 
 ON 
 
 VO 
 
 t- 
 
 t- 
 
 O- 
 
 t- 
 
 -3- 
 
 NO 
 
 J- 
 
 ■ 
 
 H 
 
 o> 
 
 LTN 
 
 
 Ph 
 
 H 
 
 in 
 
 H 
 
 OJ 
 
 OJ 
 
 H 
 
 H 
 
 OJ 
 
 OJ 
 
 OJ 
 
 OJ 
 
 OJ 
 
 OO 
 
 OJ 
 
 H 
 
 o 
 
 H 
 
 O 
 
 o 
 
 O 
 
 o 
 
 o 
 
 O 
 
 O 
 
 o 
 
 o 
 
 o 
 
 o 
 
 O 
 
 O 
 
 o 
 
 O 
 
 ft 
 
 H 
 
 3 
 
 H 
 
 o 
 
 t- 
 
 [>- 
 
 PI 
 
 H 
 
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30 
 
 NETTRA-G1-FIF0 or NETTRA-G2-FIF0. The costs in the column labeled FIFO 
 (alone) are the lowest costs found by Legge [13]. A flowchart of subrou- 
 tine MAIN for FIFO (alone) is given in Fig. 3.3.1. The single asterisk 
 (•*) and the double asterisk (**) have the same meaning in Fig. 3.3.1 as 
 they did in Fig. 3.1.1. 
 
 Three general observations can be made from the results in 
 Tables 3.3.1 through 3.3.^. First, the networks derived by PRIIFF 
 generally contain considerably fewer gates than the networks derived by 
 FIFO (alone). Second the networks derived by FIFO generally contain 
 fewer gates than the networks derived by FIFO (alone). This phenomenon 
 can be completely attributed to the effectiveness of PRIIFF in removing 
 gates from the networks derived by FIFO. The final observation is that 
 PRIIFF can usually derive a network with lower cost than the network 
 derived by FIFO. These three observations lend strong support to the 
 statement that PRIIFF as used in NETTRA.-G1-FIF0 and NETTRA-G2-FIF0 pro- 
 vides an effective means for reducing the cost of a network while main- 
 taining the required fan-in fan-out restrictions. 
 
 It should be noted, however, that ITER =5 was used in NETTRA- 
 G1-FIF0 and NETTRA-G2-FIF0 while ITER =2 was used in FIFO (alone). If 
 ITER =5 had been used in FIFO (alone), the network cost for some functions 
 may have been further reduced. Table 3.3.5 shows an example of a function 
 for which ITER =5 is necessary to obtain the lowest cost network by PRIIFF 
 in NETTRA-G1-FIF0. However, for the 2^0 problems solved using NETTRA-G1- 
 FIFO and NETTRA-G2-FIF0, ITER = 1 would have been sufficient to obtain 
 the lowest cost network in 210 problems, ITER =3 would have been suffi- 
 cient in 13 problems, and ITER=^ would have been sufficient in 12 
 problems. ITER =5' was necessary in only 5 problems in order to obtain 
 
31 
 
 NORNET 
 
 I 
 
 PROCII 
 
 I 
 
 FIFO 
 
 ** 
 
 I STOP J 
 
 Fig. 3.3.1 The order in which subroutines are called by subroutine MAIN 
 of FIFO (alone). 
 
 * Thus loop is followed until PROCII can not further reduce the cost of 
 the network. 
 
 ** This loop is followed at least once (ITER =2) or until FIFO can not further 
 reduce the cost of the network. 
 
32 
 
 
 COST BY 
 
 COST BY 
 
 COST BY 
 
 ITERATION 1 " 
 
 PROCII 
 
 FIFO 
 
 PRIIFF 
 
 1. 
 
 9025 
 
 21+037 
 
 15025 
 
 2. 
 
 10020 
 
 17027 
 
 1502U 
 
 3. 
 
 12022 
 
 17027 
 
 15025 
 
 k. 
 
 9019 
 
 18028 
 
 16025 
 
 5. 
 
 9019 
 
 15023 
 
 1^023 
 
 6. 
 
 10021 
 
 18028 
 
 18028 
 
 Table 3.3.5 An example by NETTRA-G1-FIF0 (U-variable function #8 in 
 
 Table 3.3.1 with FI = F0= F00= FOX= 2) shewing the necessity 
 of ITER= 5. 
 
 t An iteration is defined to be each call to FIFO, 
 
33 
 
 the lowest cost network. Because of this it does not matter whether 
 ITER =5 or 2 is used although a value such as 2 would have given similar 
 results and would have resulted in a reduction in the computation time. 
 Thus we compare the results by NETTRA-G1-FIF0 and NETTRA-G2-FIF0 (with 
 ITER=5)with the results by FIFO (alone) (with ITER=2). 
 
 One final comparison that can be made from the results in Table 
 3.3.1 through 3.3.^ is between the effectiveness of NETTRA-G1-FIF0 and 
 NETTRA-G2 -FIFO . One measure of effectiveness is the percentage of times 
 each program derives the lowest cost network. Such figures for NETTRA- 
 G1-FIF0 and NETTRA-G2-FIF0 are given in Table 3.3.6. These figures 
 demonstrate that NETTRA-G2-FIF0 is more powerful on the average than 
 NETTRA-G1-FIF0 in terms of ability to remove redundant gates. 
 
 Table 3.3.7 shows the average computation time per function 
 in seconds for NETTRA-G1-FIF0 and NETTRA-G2-FIF0. All time values printed 
 by the programs are provided using system timing routines. These figures 
 show that NETTRA-G2-FIF0 requires slightly more than twice the amount 
 of computation time per function than NETTRA-G1-FIF0. It is also inter- 
 esting to note that in NETTRA-G1-FIF0 PROCII requires more time than 
 PRIIFF while in NETTRA-G2-FIF0 exactly the opposite is true. FIFO uses 
 about the same amount of time per function in both programs. 
 
 The results given in this chapter indicate that NETTRA-G1-FIF0 
 and NETTRA-G2-FIF0 are effective programs for synthesizing fan-in fan-out 
 restricted networks within a reasonably short computation time. NETTRA- 
 G2-FIF0 appears to be somewhat more effective than NETTRA-G1-FIF0 in 
 synthesizing networks with a smaller number of gates but at the expense 
 of an increase in computation time. 
 
3"+ 
 
 PROBLEM 
 
 PERCENTAGE* 1 " OF TIMES 
 
 PERCENTAGE 1 " OF TIMES 
 
 SPECIFICATIONS 
 
 NETTRA-G1-FIFO DERIVES 
 LOWEST COST ++ NETWORK 
 
 NETTRA-G2-FIF0 DERIVES 
 LOWEST COST 1 "" 1 " NETWORK 
 
 1. 4-VAR. FUNCTIONS 
 
 
 
 FI = FO = FOO = FOX = 2 
 
 56.7 % 
 
 76.6 i 
 
 2. k-VAR. FUNCTIONS 
 
 
 
 FI = FO = FOO = FOX = 3 
 
 83.3 i 
 
 86.7 1o 
 
 3. 5-VAR. FUNCTIONS 
 
 
 
 FI = FO = FOO = FOX = 3 
 
 50.0 % 
 
 73.3 % | 
 
 k. 5-VAR. FUNCTIONS 
 
 
 
 FI = FO = FOO = FOX = k 
 
 56.7 % 
 
 76.6 % 
 
 Table 3.3.6 A measure of the effectiveness of NETTRA-G1-FIF0 and 
 NETTRA-G2-FIF0. 
 
 t The sum of the percentages in each row is greater than 100$ since 
 
 both NETTRA-G1-FIF0 and NETTRA-G2-FIF0 derive the lowest cost network 
 for some functions. 
 
 tt For purposes of this table, the cost of a network is defined as the 
 number of gates (i.e., A=l and B=0). 
 
35 
 
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36 
 
 REFERENCES 
 
 [l] Y. Kambayashi and S. Muroga, "Network transduction by permissible 
 functions (General principles of NOR network transduction NETTRA 
 programs)," to appear as Report. Department of Computer Science, Univ. 
 of Illinois, Urbana, 111. 
 
 [2] J.N. Culliney, H.C. Lai, and Y. Kambayashi, "Pruning procedures for 
 NOR networks using permissible functions (Principles of NOR network 
 transduction programs NETTRA- PG1, NETTRA- PI, and NETTRA-P2).. Report 
 UIUCDCS-R-7i4--690, Department of Computer Science, Univ. of Illinois, 
 Urbana, 111., Nov. 197^. 
 
 [3] H.C. Lai and J.N. Culliney, "Program manual: NOR network pruning 
 
 procedures using permissible functions (Reference manual of NOR network 
 transduction programs NETTRA-PG1, NETTRA- PI, and NETTRA-P2). Report 
 UIUCDCS-R-7^-686, Department of Computer Science, Univ. of Illinois, 
 Urbana, 111., Nov. 197^. 
 
 [k] Y. Kambayashi and J.N. Culliney, "NOR network transduction procedures 
 based on connectable and disconnectable conditions (Principles of NOR 
 network transduction programs NETTRA-G1 and NETTRA-G2)," to appear as 
 Report. Department of Computer Science, Univ. of Illinois, Urbana, 111. 
 
 [5] J.N. Culliney, "Program manual: NOR network transduction based on 
 connectable and disconnectable conditions (Reference manual of NOR 
 network transduction programs NETTRA-G1 and NETTRA-G2)," Report UIUCDCS- 
 R-75-698, Department of Computer Science, Univ. of Illinois, Urbana, 
 111., Feb. 1975. 
 
 [6] H.C. Lai and Y. Kambayashi, "Generalized gate merging and substitution 
 for NOR network transduction (Principles of NOR network transduction 
 programs NETTRA-G3 and NETTRA-GU)," to appear as Report, Department of 
 Computer Science, Univ. of Illinois, Urbana, 111. 
 
 [7] H.C. Lai, "Program manual: NOR network transduction by generalized gate 
 merging and substitution (Reference manual of NOR network transduction 
 programs NETTRA-G3 and NETTRA-G4)," Report UIUCDCS-R-75-71 1 ^ Department 
 of Computer Science, Univ. of Illinois, Urbana, 111., April 1975. 
 
 [8] Y. Kambayashi, H.C. Lai, J.N. Culliney, and S. Muroga, "NOR network 
 
 transduction based on error- compensation (Principles of NOR network trans 
 duction programs NETTRA- El, NETTRA-E2, and NETTRA- E3)," to appear as 
 Report. Department of Computer Science, Univ. of Illinois, Urbana, 111. 
 
37 
 
 [9] H. C. Lai and J.N. Culliney, "Program manual: NOR network transduction 
 
 based on error compensation (Reference manual of NOR network transduction 
 programs NETTRA-E1, NETTRA-E2, and NETTRA-E3)," to appear as Report. 
 Department of Computer Science, Univ. of Illinois, Urbana, 111. 
 
 [lO] B. Plangsiri, "NOR network transduction procedures: "Merging of gates" 
 and "Substitution of gates" for fan- in and fan-out restriceted networks 
 (NETTRA-G3-FLF0 and NETTRA-PGl-FIFO)," Report UTUCDCS-R-7^-688, Department 
 of Computer Science, Univ. of Illinois, Urbana, 111., Dec. 197^» 
 
 [ll] James F. Gimpel, "The Minimization of TANT Networks," IEEE Transactions 
 on Electronic Computers , Vol. EC-16, No. 1, pp. 18-38, Feb. 1967. 
 
 [12] K. R. Hohulin and S. Muroga, "Alternative methods for solving the cc-table 
 in Gimpel' s algorithm for synthesizing optimal three level NAND networks," 
 to appear as Report, Department of Computer Science, Univ. of Illinois, 
 Urbana, 111. 
 
 [13] J.G. Legge, "The design of NOR networks under fan-in and fan-out 
 
 constraints (A programming manual for FLFOTRAN-Gl)," Master's thesis, 
 Electrical Engineering Dept., Report UIUCDCS-R- 7^-661, Department of 
 Computer Science, Univ. of Illinois, Urbana, 111., June 197^« 
 
 [lk] S.Y.H. Su and C.W. Nam, "Computer-Aided Synthesis of Multiple -Output 
 Multilevel NAND Networks with Fan- In and Fan-Out Constraints," IEEE 
 Transactions on Computers , Vol. C-20, No. 12, pp. lM+5-1^55, Dec. 1971. 
 
38 
 
 APPENDIX 
 
 AN EXAMPLE WITH INCOMPLETELY 
 SPECIFIED OUTPUT FUNCTIONS 
 
 In the December 1971 issue of IEEE Transactions on Computers , 
 Su and Nam presented an algorithm for synthesizing multiple -output 
 networks using NAND gates with fan-in and fan-out restrictions which 
 realize incompletely specified switching functions llkl. One set of 
 ^--variable output functions used as an example by Su and Nam is given 
 in Table Al. These same functions were used to further test NETTRA-3- 
 FIFO and NETTRA-U-FIFO. However, NETTRA-G1-FIF0 and NETTRA-G2-FIF0 
 synthesize NOR networks, and thus it was necessary to use the duals of 
 the functions in Table Al as the input functions to NETTRA-G1-FIF0 and 
 NETTPA-G2-FIF0. These dual functions are listed in Table A2. That is, 
 NETTPA-Gl-FIFO and NETTRA-G2-FIF0 were used to synthezise NAND networks 
 realizing the functions in Table Al by specifying the functions in 
 Table A2 on the function cards and then interpreting the networks printed 
 by the programs as NAND networks rather than NOR networks. 
 
 The results of using the functions in Table A2 as inputs to 
 NETTPA-Gl-FIFO and NETTRA-G2-FIF0 with ITER =5 are shown in Table 3. 
 Since the network synthesized by Su and Nam's algorithm (shown in Fig. Al) 
 has a cost of 250^+2 (twenty five gates and forty two connections), the 
 results in Table A3 further establish the effectiveness of NETTRA-G1-FIF0 
 and NETTRA-G2-FIF0. It is interesting to note that the computation 
 times for the multiple-output case are considerably longer than for the 
 single output case (see section 3.3). 
 
39 
 
 OUTPUT FUNCTIONS 
 
 NAND TRUTH TABLES 
 
 Z2 
 Z 3 
 
 00000*0100*0*111 
 1111001100*0*001 
 111**01111*0*011 
 0000000101*0*011 . 
 
 Table Al. Su and Nam's ^-variable incompletely specified output functions, 
 
 OUTPUT FUNCTIONS 
 
 NOR TRUTH TABLES 
 
 Zl 
 
 z 2 
 
 Z 3 
 
 000*1*1101*11111 
 011*1*1100110000 
 001*1*00001**000 
 001*1*0101111111 
 
 Table A2. The duals of the functions in Table Al. 
 
4o 
 
 PROGRAM 
 
 (FI, FO, FOO, FOX) 
 
 PRIIFF 
 
 NETWORK 
 
 COST 
 
 TOTAL 
 COMPUTATION 
 TIME (SEC.) 
 
 NETTRA-G1- 
 FIFO 
 
 (2. 2. 0. 2) 
 
 17030 
 
 47.42 
 
 (2, 2, 1, 2) 
 
 18032 
 
 35.50 
 
 (2, 2, 2, 2) 
 
 17031 
 
 35.27 
 
 NETTRA-G2- 
 FIFO 
 
 (2, 2, 0, 2) 
 
 20036 
 
 64.83 
 
 (2, 2, 1, 2) 
 
 17031 
 
 61.24 
 
 (2, 2, 2, 2) 
 
 17031 
 
 54.94 
 
 Table A3. Results by NETTRA-G1-FIF0 and NETTRA-G2-FIF0 for the functions in 
 Table 4.1. • 
 
 1 — 
 
 ITERATION 
 
 NAND OUTPUTS BY PRIIFF 
 (HEXADECIMAL REPRESENTATION) 
 
 PRIIFF 
 
 NETWORK 
 
 COST 
 
 Z l 
 
 z 2 
 
 V 
 
 z 4 
 
 1 
 2 
 
 3 
 
 4 
 
 5 
 6 
 
 05 OF 
 050F 
 0527 
 
 0507 
 010F 
 050F 
 
 F301 
 F301 
 F301 
 F301 
 F301 
 
 F301 
 
 E3E3 
 FBEB 
 FBEB 
 FBEB 
 FBEB 
 FBEB 
 
 0143 
 oi4b 
 0163 
 0143 
 0143 
 0143 
 
 21038 
 20034 
 19033 
 19034 
 17030 
 21036 
 
 Table A4. Output functions and network cost by PRIIFF at each iteration 
 of NETTRA-G1-FIF0 with FI = F0=F0X=2 and FOO = (in Table A3). 
 
kl 
 
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 derived by PRIIFF at each iteration of NETTRA-G1-FIF0 with PI = FO = FOX = 2 
 and F00=0 (in Table A3). It is interesting to observe that the PRIIFF 
 network realizes a different set of output functions at each iteration. 
 The network of cost 17030 in Tables A3 and A4 is shown in Fig. A2. This 
 network has eight fewer gates than Su and Nam's network but requires 
 only one more level. 
 
 NETTRA-G1-FIF0 and NETTRA-G2-FIF0 may be able to obtain better 
 results for some completions (i.e., assignments of O's and l's to the 
 "don't cares" ("*'s)) of imcompletely specified functions since the pro- 
 grams do not treat all possible completions of incompletely specified 
 functions. Thus NETTRA-G1-FIF0 and NETTRA-G2-FIF0 were used to obtain 
 networks for nine different completions of the functions in Table Al. 
 The truth tables for these completions are shown in Table A5. As before 
 the NOR truth tables are used as inputs so that the networks by NETTRA- 
 G1-FIF0 and NETTRA-G2-FIF0 can be used as NAND networks realizing the 
 NAND truth tables. The results of these nine completions are shown in 
 Table A6. All of the network costs are less than the 250^2 of Su and 
 Nam's network. The times are comparable with those in Table A3. The 
 network of cost 16029 in Table A6 is shown in Fig. A3. This network 
 has nine levels, i.e., one more level than Fig. Al. 
 
 The results in this appendix as well as those in chapter 3 
 firmly establish the effectiveness of NETTRA-G1-FIF0 and NETTRA-G2-FIF0 
 for synthesizing networks with fan-in and fan-out restrictions and/or 
 incompletely specified output functions. Using a reasonably short 
 computation time, these programs can generally derive networks with a 
 lower cost than the networks derived by other procedures. 
 
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BIBLIOGRAPHIC DATA 
 SHEET 
 
 1. Report No. 
 
 UIUCDCS-R-75-719 
 
 3. Recipient's Accession No. 
 
 4. Title and Subtitle 
 
 NETWORK TRANSDUCTION PROGRAMS BASED ON CONNECTABLE AND 
 DISCONNECTABLE CONDITIONS WITH FAN- IN AND FAN-OUT RESTRI 
 (A description of NETTRA-G1-FIF0 and NETTRA-G2-FIF0) 
 
 5. Report Date 
 
 April 1975 
 
 7. Author(s) 
 
 Keith R. Hohulin 
 
 8- Performing Organization Rept. 
 
 No - UTUCDCS-R- 75-719 
 
 9. Performing Organization Name and Address 
 
 University of Illinois at Urbana- Champaign 
 Department of Computer Science 
 Urbana, Illinois 6l801 
 
 10. Project/Task/Work Unit No. 
 
 11. Contract/Grant No. 
 
 NSF-GJ-^0221 
 
 12. Sponsoring Organization Name and Address 
 
 National Science Foundation 
 188 G Street, N.W. 
 Washington, D.C. 20550 
 
 13. Type of Report & Period 
 Covered 
 
 Technical 
 
 14. 
 
 15. Supplementary Notes 
 
 16. Abstracts 
 
 Two computer programs (NETTRA-Gl-FIFO and NETTRA-G2-FIF0) which implement network 
 transduction procedures based on connectable and disconnectable conditions with 
 fan-in and fan-out restrictions are presented in this paper. These programs can 
 synthesize NOR (NAND) networks with either completely or incompletely specified 
 output functions. The results of computer experiments on NETTRA-Gl-FIFO and 
 NETTRA-G2-FIF0 for both completely and incompletely specified functions are also 
 presented. 
 
 17. Key Words and Document Analysis. 17a. Descriptors 
 
 Logical design, network transduction procedures, NOR gate networks, fan- in 
 restrictions, fan-out restrictions, incompletely specified functions. 
 
 17b. Identifiers/Open-Ended Terms 
 
 '7c. ( OSA I I Field/Group 
 '8. Availability Statement 
 
 RELEASE UNLIMITED 
 
 19. Security (lass (This 
 Report) 
 
 UNCLASSIFIED 
 
 20. Security (lass (This 
 Page 
 
 UNCLASSIFIED 
 
 21. No. of Pages 
 
 50 
 
 22. Price 
 
 FORM NTIS-1B ( 10-70) 
 
 USCOMM-DC 40329-P7I 
 
*» 
 
>*■ 
 
 * 
 
V