LI B RARY OF THE ■^' UNIVLR.SITY Of ILLINOIS 510. 94 Ii6r , ho.524-33d ccp. ,2 * », ?-. . The person charging this material is re- sponsible for its return on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. University of Illinois Library OCT 2 \ 1978 NOV 1 4 1970 NOV 1 - ^ Ut - 7 1870 m ^ 157! OEC 1 9 ^^ iFEB -I m APR 2 ^' ma U 1972 ^ 4 (5" Ay 9 9 ^^p' NOV 1 2 V87^ . - l^^^i^ - - SEP 3 1977 ,r: 14 2004 JUL a 19: '5 :.;iJ(IL10ii|ni *«6 25BfCD MAR 8 1978 MAR 8 RECD JAW 2 ^ PW* 1^ 5 *^7r MAR ^® ^^■'^ V!:-i!: iar7 I L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/testmodeapproach326rett 5tC> \j ^ \j it*^ • ^i. A TEST MODE APPROACH TO FAULT DETECTION IN SEQUENTIAL CIRCUITS by J. Rettiff May 1969 JUN ] ( DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN • URBANA, ILLINOIS ijrijveijitv of llllitois Report No. 326 A TEST MODE APPROACH TO FAULT DETECTION IN SEQUENTIAL CIRCUITS* by J. Rettig May 1969 Department of Computer Science University of Illinois Urbana, Illinois 618OI * This report was supported in part by U. S. AEC Grant AT(11-1)iU69 and was submitted in partial fiafillment of the requirements for the degree of Master of Science in Computer Science, June I969. Ill ACKNOWLEDGEMENT The author is indebted to Dr. C. W. Gear whose suggestions, comments, and criticisms helped greatly during the research work and the writing of this thesis. The author is also grateful to Prof. G. Metze for his suggestions and criticisms. iv TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. TEST MODES 2 3. COMBINATIONAL CIRCUITS 7 3.1. Detecting Single Faults 7 3.2. Detecting Fault Pairs 10 3.3. Fault Identification 13 3.^. Example 15 k. SYNCHRONOUS SEQUENTIAL CIRCUITS 21 k.l. Detecting Single Favilts 21 U.2. Detecting Faiolt Pairs 23 k,3. Fault Identification 2k k.h. Example 25 5. ASYNCHRONOUS SEQUENTIAL CIRCUITS 32 5.1. Detecting Single Favilts 33 5.2. An Asynchronous Circuit 3l+ 5.3. Example 35 6. CONCLUSIONS k3 LIST OF REFERENCES kk LIST OF FIGURES Figure Page 2-1 3- Input NAND— Single Faults . k 2-2 Indistinguishable Fault Classes h 2-3 Exclusive OR With Good Machine 5 2-k Single Fault Cover: Test Modes 5 2-5 2-Input NMD With Failiire 6 2-6 Hardware Configuration — 2-Input NMD 6 3-1 Forward Trace-Sensitizing A Path Prom A Test Mode. l6 3-2 Backward Trace-Setting Up Required Inputs 17 3-3 Fault Table Generation l8 3-U Test Pattern Generation Combinational Circuits . . 19 1+-1 Synchronous Seq.uential Circuit Model 26 U-2 Test Pattern Generation Synchronous Seq_uential Circuits 27 4-3 Test Patterns 28 k-k Permanent Fa\ilt Table 30 5-1 Asynchronous Seq.uential Circuit Model 37 5-2 An Asynchronous Sequential Circuit 38 5-3 Test Patterns 39 5_li Transient Fa\ilt Table kO 5-5 Fa\ilt Dictionary k2 1 . INTRODUCTION This paper is concerned with the computer-aided generation of test patterns which will detect the presence of single faults (stuck-at-zero or stuck-at-one ) or faiolt pairs (internal shorts) in sequential circuits. The circuit which is "being tested may be an LSI module, a printed circuit board, or any functional section of logic circuitry. It is assumed that the circuit is accessible from a limited number of terminals which are designated primary inputs and primary outputs. A test pattern is the set of primary inputs which is to be applied to the circuit and primary outputs which will result if the faults which this test detects are not present in the circuit. A nearly minimal set of test patterns which will detect the presence of single favilts and fault pairs will be produced. If the fault must be identified, a set of additional tests will normally be needed to separate the faults into indistinguishable classes . A test procedure for generating test patterns to cover single faults and fault pairs in combinational circuits is given. Then this test procedure is extended so that the same set of faults can be detected in synchronous sequential circuits. Finally, the test procedure is applied to some asynchronous circuits and some of the problems which will occur are mentioned. 2. TEST MODES A test mode for a device is a device input vector which will locate a set of failures inside the device or along the connections. The complete set of test modes for a device is a subset of the set of all possible input vectors. This reduction in the number of tests req_uired will resiolt in a considerable saving for multi-input devices, eg., an 8-input NMD has 9 test modes out of 256 input combinations. Figure 2-1 shows all the possible machines which may result when a stuck-at-zero or stuck-at-one fault is inserted into the inputs or into the output of a 3-input NAI>JD. Figure 2-2 gives the indistinguishable fault classes which result. In Figixre 2-3 the exclusive OR of the output of the good machine with each of the faulty machines is given. The test modes, which are shown in Figure 2-i|, are the minimum number of input combinations needed so that all faulty machines give a different response than the good machine for at least one input combination. Since this approach does not check all possible input combinations, a failure could occur which woxild cause the device to fail only on an input combination which is not tested. However, this sort of a failure cannot be simulated by any simple alteration of the device. So it seems safe to ignore this possible failure mode. Figure 2-5 is a truth table for a 2-input NAND which has a failure in an input combination which is not tested by any test mode (i.e. x.^ = 0, x_ = 0, z = O). Figure 2-6 shows a hardware configuration for a 2-input NAND. There are no simple faults which can be injected into the circuit which can transform it into the circuit represented by the preceding truth table. However, there may be an intermittent fault, eg., an intermittent emitter collector short. 3 which could cause the device to fail when one input combination is applied but not when another one is applied. If the test sequence is cycled several times before concluding that a circxiit is good, the intermittent faults will probably be located. xt- MACHINE FAULT BOOLEAN OUTPUT EXPRESSION "o Good Machi ne x^x^x^ ^1 ^1 s - a - 1 x^x^ ^2 ^1 s - a - 1 M3 Xo s - a - 1 XiX^ % Xg s - a - 1 ^ X3 s - a - 1 ^1^2 \ x^ s - a - 1 M^ z s - a - 1 1 ^8 z 3 - a - Figure 2-1 3-Input NAND —Single Favilts MACHIUE OUTPUT EXPRESSION % x^x^x^ \ x^x^ M3 v^ \ x^x^ '^2' ^. "6' M 1 Mp, Figure 2-2 Indistinguishable Fault Classes x,x^x^ M.0M„ M„0M^ M^0M^ M^0M^ Mo0M 1 Figure 2-3 Exclusive OR With Good Machine 1 10 oil 1 10 10 1 110 111 l^^^O i'l^UmQ i^gOmQ 1 1 1 1 1 1 1 1 1 TEST MODE NO. x x x 1 111 2 Oil 3 10 1 k 110 Figure 2-4 Single Faiilt Cover: Test Modes X, Xz ?L o O o I 1 1 O 1 \ 1 o Figure 2-5 2-Input NMD With Failure X. ^ -VNAr Xz ■Kh * — W W- Figiire 2-6 Hardware Configuration — 2-Input NMD 3. COMBINATIONAL CIRCUITS A set of test patterns must be generated which will detect single faults (s tuck-at-zero or stuck-at-one ) or fault pairs (internal shorts) in combinational circ\xits. A set of test patterns will be generated to cover single fatilts. Then an additional set of test patterns will be generated to cover those faiilt pairs which are not covered by the previous tests. S.l. Detecting Single Faults Tebt patterns to detect single faults can be generated by applying a test mode to a device and sensitizing a path to a primary output. VJhen each Ler>t mode on every device is seen at a primary cutput, tlie set of single faults is covered. Indicators are generated for each device output within the circijit to indicate the length of the shortest path to a primary input a,rKl to a primary output. The input (output) level number indicates the number of gates which the signal must go through to reach the primary input (output). Tae input level number (ILN) is useful in selecting a path to a primary input when a device input is being specified. The output level number (OLN) is useful in selecting a path from a device output to a primaiy output if fanout occurs from that output. The procedure of setting up the inputs to the devices along the path to a primary output so that the device output can be seen at a primary output is called sensitizing a path. For NAND circuits this consists of making all of the device inputs ones except for the one being sensitized, 'Oien the device output is the complement of the sensitized 8 input. The path which is chosen at every Junction where fanout occurs is determined by the output level number. The path which has the lowest output level number and has not previously been atten^ted in propagating this test mode will be selected. Thus the shortest path to the output will be selected initially. If this path fails, the longer paths will be tried until every path has been attempted. If a test mode cannot be propagated to a primary output, and if no other test modes have previously been set up within this test pattern, then this test mode cannot be seen at any primary output and the faiilts which this test mode detects will not affect any primary output \anless mxoltiple faults occur. (Figure 3-1 gives a block diagram of this path sensitization procedure.) Once the test mode has been propagated to a primary output, those device inputs which are necessary to set up the test mode and to transfer it to a primary output have been stored in a stack according to their input level number with those inputs with the highest input level number on top of the stack. The process of propagating these inputs back to the primary inputs is known as backward trace. The input at the top of the stack is generated by setting up the inputs to the preceding device so that the desired output results. If a contradiction results when trying to set up an input, the entire test is erased and another atten^t is made at propagating the test mode. If an input can be specified, those inputs to the preceding device which are not primary inputs are added to the stack. (See Figure 3-2 for a block diagram of this procedure.) When the stack is empty, a fault table must be generated which will indicate which device test modes and primary inputs are seen at each primary output. This fault table can be produced by starting at a primary output and proceeding backwards adding test modes or primary inputs to 9 the list if they affect that primary output. For NMD circuits, if an output is a zero and can be seen at a primary output, all of the preceding inputs (all ones) can also be seen at a primary output. If the output is a one, only the device input which is a zero can be seen at a primary output. (Figure 3-3 is a block diagram of this procedure.) The selection of a test mode and a procedure for propagating it will affect the number of test patterns which are generated to cover all single faults. Two of the methods which can be selected are the following: 1. Start setting up test modes on those devices connected to the primary outputs and additional test modes will be covered when the required device inputs are propagated to the primary inputs. When every device in a level has been tested in every test mode, then begin generating test modes on those devices in the preceding level which have not been completely tested. 2. Start setting up test modes on those devices connected to a primary input and propagate the test along every path to the primary outputs. When every device in a level has been tested, apply test modes to those devices in the following level which have not been completely tested. The first method seems to generate fewer test patterns because most of the devices in the circuit will be tested by the time all of the test modes on those devices connected to the primary outputs have been generated. A major factor in determining the running time and the number of tests which a program will generate is the niimber of test modes which 10 are set up ajid propagated to the output within the same test pattern. After a test mode has been propagated to a primary output a strategy- must be devised for deciding whether to attempt to propagate another test mode within the same test pattern and which test mode should be propagated. If a circuit has a considerable amoxont of fanout, there will be few independent blocks of circiiitry in it. As a result, several test modes cannot be set up within the test pattern since a contradiction will result because of an output which was specified by a previous test mode. When a contradiction results, all of those inputs and outputs which have been specified by this test mode will be erased and another attempt will be made to propagate the test mode. The computer time which was used generating and erasing this test has been wasted. One strategy which can be used is to generate another test pattern as soon as a test mode has been found which cannot be propagated along any path to a primary output. 3.2. Detecting Fa\ilt Pairs After a set of test patterns have been generated to cover all single faults, these test patterns must be examined to .determine whether all fault pairs (internal shorts) which are distinguishable at a primary output are detected by these test patterns. Additional test patterns must be generated to detect those fault pairs not previously detected. The response of a circuit to an internal short will depend on the implementation of the circuit. If outputs of two (7^ series) NAND's which are initially at different levels are shorted together, the output which was a one is loaded down to a zero. A procedure for 11 detecting this faiilt would be to make the two outputs different and to insure that the output which shoiild he a one is seen at a primary- output. Another restriction which is necessary for the detection of this fault pair is that the one output must not be farther from a primary output than the zero output. This insures that the zero output is not caused by the one output which would result in an intermediate value if they were shorted. If two inputs to the same device are shorted together, it will not affect the operation of the circuit unless the line to one of the inputs should fanout to another input. If neither line does fanout, the fault pair is indistinguishable. If fanout exists, the fault pair can be detected by propagating the fault along the fanout path. The test patterns which were generated to cover single fa\ilts must be examined to determine which fault pairs these test patterns will cover. The primary inputs which are imspecified represent don't care conditions. If zeros are applied to these lines the probability of detecting faiilt pairs will be improved. The following is a procedure for covering fault pairs: 1. Pick a pair of lines (primary inputs or device outputs) in the circuit which have not been tested. If every pair has been tested, go to step 8. 2. Determine whether tfee fault pair is distingiiishable . If it is not, return to step 1. 3. Are different levels applied to these two lines by any of the test patterns? If not, go to step 6 and create a test pattern to cover the fault pair. 12 k. Is the output level number of the one output less than or equal to the output level number of the zero output? If not, go to step 3 and try another test pattern. 5. Is the one output in the fault table? (is the one output seen at a primary output?) If it is not, go to step 3 and find another test pattern. If it is, the fault pair is covered. Go to step 1 and find another fault pair. 6. Make the output closer to the primary output a one, and the other output a zero. 7. Propagate the one to a primary output. If a con- tradiction occurs, the fault pair is indistingioishable. If a test pattern is generated, create a fault table for this test pattern. Go to step 1 and try another fault pair. 8. All distinguishable fault pairs are covered. This proced\are can be in^jroved by trying to cover several fa\ilt pairs with the same test pattern. In most circuits, the additional test patterns which are added to cover fault pairs should be fewer than the set of test patterns needed to cover single f axilts . The additional time required to cover the fault pairs should be less than that needed to cover single faults . Another method which could be used to detect fault pairs would be to apply different levels to each pair of lines during the test pattern and to monitor the source current to detect a failure. 13 If outputs of two T^ series NMD's, which are at different levels , are shorted together the so\irce current supplied to these devices will increase by about 20ma. The source current normally is 3ma when the output is a one, and Ima when it is a zero. For small circuits the percent change in source current caused by the fa\ilt pair is large, and can be easily distinguished. If NAND's are used to drive the primary inputs and are driven by the same supply as the circuit being tested, all fault pairs will be detected in small circuits. Since the source current depends on the device output, if many device outputs change from one test pattern to another this change could hide the occurrence of the fault pair. A solution to this problem would be to calculate the nominal source current for each test pattern and to change the allowable soxirce current monitored by the tester from one test pattern to another. The implementation of this could be expensive. Another approach would be to calculate the maximiom nominal source current and to use this as the allowable source current. In large circuits some fault pairs would not be distinguished by this approach. For combinational circuits sensitizing the path from the one output seems to be a better method than monitoring the source current. 3.3. Fault Identification If faults m\:st be identified, the preceding test patterns m\ist be analyzed to determine if they group the single faults into indistinguishable fault classes. If they do not, an additional set of tests must be generated to partition the fault classes. However, fault pairs will not be identified because this class of faults is so large that the number of additional tests would be prohibitive in most circuits. Ik In order to identify a single fault, a faiilt dictionary should be produced. This fault dictionary is produced by taking the exclusive OB of the response of the good machine with the response of each one of the faulty machines. Everywhere a one appears in the fault dictionary it indicates an output of the faulty machine that is different from that of the good machine during a test pattern. Each column of the fault dictionary is called a fault signattire. A fault dictionary can be obtained directly from the fault table. A one will be placed in the fault dictionary whenever a test mode is seen at a primary output. Otherwise a zero will be placed in the fault dictionary. Indistinguishable faults should be grouped together into a faiilt class before creating the faiilt dictionary. One situation when indistinguishable faults woiald occur would be when there is no fanout between devices. In this case, faults on the test modes of the two devices are indistinguishable. After the indistinguishable faults have been combined into fault classes, the exclusive OR of each col\imn of the fault dictionary with every other column is taken. If a one appears anywhere in the resulting column, these two faults can be distinguished. If all zeros appear in any column, these two faults have not been distinguished and another test pattern must be generated to distinguish these faults . The additional test patterns necessary to partition two fault classes can be generated by sensitizing the path from the output of one of the fault classes and desensitizing the path from the other one. In other words, set up the primary inputs so that the output of one device can be seen at a primary output and the output of the other one cannot. If this cannot be done, the faults are indistinguishable. 15 When every coliomn which is the exclusive OR of two fault classes has a one in it, every fault class will have a unique fault signature. If a fault occurs whose response does not correspond to the response of any of the faiolty machines, a multiple fault or a fault pair which are not identified in the fault dictionary might have occurred. 3.'+. Example Figure 3-^ shows a combinational circuit and the test patterns which resiilt if the previously described procedures are applied. Test patterns 1-5 will detect aJ.1 single faults except a failure on device H in test mode 2. The fact that this test mode is indistinguishable indicates that the connection from the output F to the input of the device whose output is labeled H is unnecessary. These test patterns will also detect all faialt pairs except CI, GI, and CF. Test pattern 6 is generated to detect CI and GI. Test pattern 7 is generated to detect CF. After collapsing the device test modes and primary input levels into fault classes, the fault dictionary is created. Each column in the fault dictionary is compared with every other column to determine if the fault classes have been distinguished by the test patterns. Faiilt classes BO, F3, and DO, and G2 have not been distingtiished by the first seven test patterns. The eighth test pattern is created by sensitizing the path from the BO, F3 fault class and desensitizing the path from the DO, G2 test mode. Fault classes 12 and Bl, Al, and Fl are not distinguished by the first seven test modes. Any attempt to sensitize a path from one faiilt class while desensitizing a path from the other will fail. Therefore, these faTilt classes are indistinguishable. l6 TEST MODE. TO F>R.OP*.<»Arre FtlHD A. PATH » L-OVSietT OU^i TRy AKlOTHeR TE«rr PKT-reRM NO DESTAo^' CO««e»4T PA,TH AMD STA.RT PROPA.feA>-T£ »UTOUT PI-AC PATH TAXEKl IMOI?T|V4(90ISHA8U TE«,T hA0OE N\A>KE OTMER DEWCe. IMPOTS ves ?TORE lNPOTe> IKl A •bTACVC. WO Figure 3-1 Forward Trace-Sensitizing A Path From A Test Mode IT ^ »TH W « C»HS.aT KtO yc& «>EUC.CX % Mooe > vaPOT« To ocviice I's 6.TACK. Figure 3-2 Backw«u:d Trace-Setting Up Required Inputs 18 ( »TlkRT j FICK, A PHIMARV OUTPUT POT PRCCEDWIO OCN/lCE. OUTPUT IN r^ovrr TAKUC TAH-e. NEXT OUTPUT PROM *T/KC< FIND A oevice tNPOT >«£& PUT PRecceoiNb OOTPOT Iki FVPO %Tft,tK^ Find a OftVICe. OOTPOT PUT PReCE.D)»4te OUTPUT \>4 FIFO 5tTA,CI<:. A.DO OUTPUT TO F H OO H ^ H H o W Pr, C5 pq Q LTN IPv US U-N LfN LTN "^ o CM H H H CM o OJ H OO H w o Q Pm O M Q M < ptl f^ O w H H CM CM CM OJ OO OO 00 OO OO -:f *^ O CM H H rH CM o OJ H OO CM H H o O Q Pt, O M Q M < Piq pt. o ^ ci) Q H H CM CM OJ OJ 00 OO OO OO OO ^ -* J- OJ O H OJ H H CM tr! H H M CM P=^ CVJ O CM Q CM 00 <^ O CM H H H CM o CM H OO O H Q H Pm CM CM M CM CM M OO ^ ^ OO o OO K CM O H OJ O Q H CM H CM H H O O H H M CM Pt. CM CVl Q CM M OJ O O CJ Q 30 3^+5678910 11 12 1G2 1G2 1G2 1G2 5E1 6G3 8H1 8G2 9G1 9G1 IDO IDO IDO IDO 5F3 6f1 9J1 8D0 9F2 9F2 2H1 211 2F2 2F2 5G1 6E3 9H1 9D1 9D1 3J1 2F2 2G1 2G1 5A1 6B0 lOJl 8G2 8G2 2G1 211 211 5B1 THl 8D0 8D0 2D1 2D1 2D1 5D1 8J1 911 911 3H2 312 312 6H2 10H2 1012 10 J2 10E3 lOBO 10G3 llHl UJ2 3A0 3A0 6J2 3E2 3E2 3F1 3F1 3G3 3G3 i+Hl iiF2 5J1 i+Gl 1+Dl 5H2 6J2 Figure h~k Permanent Faiilt Table ( i^ontinued 31 F3 Bl Al AO BO II Dl DO Jl J2 El E2 E3 Fl F2 Gl G2 G3 HI H2 12 1 2 3 1 1 k 1 1 1 1 5 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 7 1 1 1 8 1 1 1 1 9 1 10 1 1 11 1 1 1 1 12 1 1 1 1 1 1 1 Fault Dictionary 32 5. ASYNCHRONOUS SEQUENTIAL CIRCUITS Another type of circuit for which a test procedure should generate test patterns is an asynchronous sequential circ\iit. An asynchronous sequential circuit does not have the clock input applied to the feedback path as a synchronoiis sequential circviit does. Therefore there is no isolation between the inputs and outputs of the devices in the feedback path to insure that they change only at specified times. If more than one primary input is changed from one test pattern to another, the feedback outputs (secondary inputs) could respond in several ways depending on the order in which the primary inputs are changed. For example, if the primary inputs are to he changed from 00 to 11, they will go through an intermediate state of either 01 or 10. If a device in the feedback path responds to this intermediate state, the secondary inputs will be in an unexpected state. Therefore, if any asynchronous circuit is to be tested, the test procedure is restricted to single changes on the inputs to that asynchronovis circuit. (Figure 5-1 is a block diagram of an asynchronous circiiit.) An asynchronous sequential circuit can be implemented \ising D-type flip flops and NAND gates if the preset and clear inputs to the D-type flip flop are used. Those primary inputs which feed the preset or the clear input to any D-type flip flop (directly or indirectly) are called asynchronous inputs . By changing only one asynchronous input from one test pattern to another, the state of the storage devices can be determined and the asynchronous portion of the circuitry can he tested. Changing a single input is a slow, safe way to create the next test pattern. Multiple input changes can be made if no static hazards occur which alter the state 33 of the secondary inputs. Once the asynchronoiis portion of the circuitry has been tested, these asynchronous inputs should be held constant (if possible) and the synchronovis circuitry can be tested as was previoxosly described. If an asynchronous input is also an input to the synchronoiis circuitry, the other asynchronous inputs should be set up so that this input does not affect any of the preset or clear inputs while the synchronous circuitry is being tested. The input or the output level numbers are increased by one if a signal travels through a preset or a clear input of a D-type flip flop along a path to a primary input or a primary output. As a result, several lines in the circuit (eg. the outputs of a D-type flip flop) could have different input and/or output level numbers for asynchronous and synchronous operation. Thus, the level numbers of some of the lines in the circuit depend upon whether the asynchronous or the synchronous circuitry is being tested. Another type of asynchronoxis sequential circuit can be implemented using NAND's if there exists a feedback path aroiond a loop consisting solely of NAND's (eg. a NAWD flip flop). A procedure can be developed which will recognize these NAND feedback circuits. Then the primary inputs which eiffect this circuit are labeled asynchronous inputs, and one asynchrono\is input is changed between test patterns until all test modes in the asynchronous circ\iit have been tested. 5.1. Detecting Single Favilts An asynchronous circuit is tested for single faxilts by generating test patterns which will detect a failure in any device test mode. An initial test pattern is generated which sets as many as possible 3U of the flip flops in some initia.L state. Another test pattern is generated which will test some device test mode. Then intermediate test patterns are created which each differ from the preceding test pattern in only one input . It might be advantageous to generate test patterns for several device test modes and to rearrange these test patterns so that the n\amber of intermediate test patterns can be minimized. This area requires further investigation to determine the best procedure for selecting and rearranging test patterns. After the asynchronous circxiitry has been tested, the asynchronous inputs are checked to determine whether any of them are common to the synchronous circiiitry. The asynchronous inputs which are not common to the synchronoxis circuits cannot be seen at the preset or clear inputs of any D-type flip flop. Once this has been done, the asynchronous inputs which do not affect the synchronous operation will remain the same while the synchronous circuitry is being tested. The synchronous circuitry is tested in the manner described in the preceding section. The initialization procedure will not be needed for those memory elements which have been initialized by the test patterns for the asynchronous circuitry. 5.2. Detecting Fault Pairs and Fault Identification The test patterns which were generated to test the asynchronous circuitry shoiild detect most of the fault pairs in that circuitry and identify most of the single faults in it. The fault pairs which might occur between the lines in the asynchronous and the synchronous circuitry can be covered by specifying the don't cares on the synchronous inputs. If all fault pairs which contain an asynchronous line have not been covered. 35 a test pattern should be generated by the methods previoiisly described and intermediate test patterns should be created to reach this test pattern with single input changes . The fault pair detection and fault identification of single faults in the synchronous circTiitry proceeds in the manner described in the preceeding section. 5.3. Example Two gates are added to the example of a synchronous sequential circuit (Figure i|-2). These gates drive the preset and clear inputs to the D-type flip flop (Figure 5-2). The asynchronous inputs to the circuit are K, L, M, and N, The synchronous inputs are A, B, C, and D. The asynchronous circuitry is tested by the first seven test patterns; so the synchrono\as circiiitry does not affect the output. (The test patterns are given in Figure 5-3.) Synchronous inputs A, B, and D are don't cares during the first seven test patterns; while C, which is the clock input, is a zero to insure that the synchronoiis circuitry is inhibited. The eighth test pattern sets up the final test mode in the asynchronous circuitry and also sets up the first synchronous tests on G. Test patterns 8-li+ will detect all single favilts in the synchronous circuitry. Some of the don't care inputs to the synchronous circuitiy which occur in test patterns 1-7 are specified in order to detect those fault pairs which could occur between the synchronous and the asynchronous lines . Test patterns 15 and l6 are created to detect fault pairs BD, BF, BH, DJ, EJ, DH, and GJ. The transient and the permanent fault tables are shown in Figure 5-^. The first seven test patterns do not appear in the transient faiilt table because none of the faults which woiild appear in the transient 36 fault table for these test patterns are propagated to a primary output. The fault dictionary shown in Figure 5-5 is created from the permanent fault table. Test patterns IT, l8, and 19 are created to distinguish between the fault classes Dl, Gl, and Bl, Al, El, F3 and between 12, Fl, G3, and AO, E2. Since every column in the fault dictionary is \miq_ue, every fault class can be identified. 37 PRIMARY ■*- ' ^ PRIMARY INPUTS ^OUTPUTS COMBINATIONAL LOGIC SECONDARY INPUTS f* FEEDBACK ELEMENTS [clock Figure 5-1 Asynchronous Sequential Circ\iit Model 38 K(0.\) o 4>(M) pfo.aO Bro.23) I > ^^^^ /(2,2I) ' ^ P Q TC \ CILN.OLKI) D Q HTCQ (2.0) Figure 5-2 An Asynchronous Circuit 39 1 2 3 U 5 6 T 8 9 10 11 12 13 lit 15 l6 IT 18 19 AOXOXlXlllO BOXOXlXllll C0000000333 DOXOXlXlOll EIXIXOXOOOI FlXOXlXlllO GIXIXOXOIOI HllOOllOOlO lOOllOOllOl JllOOllOOOl KlOOOllllll LlllllOOOOO MOOlllllOOO NlllOOOllll 00111011111 PllOlllOlll X = DON'T CARE 3 = CLOCK INPUT Figure 5-3 Test Patterns 1 1 1 X 1 X X 1 1 X 1 X X 3 3 3 3 3 3 3 3 3 1 1 1 1 1 X X 1 1 1 X 1 X X 1 1 1 1 1 X X 1 1 1 1 X X 1 1 1 1 1 X 1 1 1 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ko 8 9 10 G H G H G H 11 G H 12 G H 13 Ih G H G H 15 G H 16 G H IT G H ,8G2 8(J3 9G1 8G2 10G3 9G1 11F2 10G3 8D0 8L0 9F3 8D0 lOFl 9F3 llDl lOFl 9D1 9H1 10E2 9D1 llGl 10E3 9E1 lOAO 9E1 nil lOAO 9A1 1012 9A1 10G3 1012 9B1 9G1 9B1 lOFl 9G1 9F3 10H2 10E2 9F3 9D1 lOAO 9D1 9E1 1012 9E1 9A1 9G1 9A1 9F3 9B1 9D1 llHl 9E1 9A1 9B1 12E3 11F2 13G1 12E3 1UG2 iUH2 15G2 15H1 i6g1 16H1 17G3 17H1 12B0 llDl 13D1 12B0 iUDO 13G1 15D0 li+G2 i6d1 15G2 17F1 16g1 12ifl 11F2 13F2 12ri 13D1 12G3 llDl 1311 12G3 13F2 1212 llGl 12E3 1212 1311 10G3 nil 12B0 10G3 12E3 lOFl 10G3 12F1 lOFl 12B0 10E2 lOFl 12G3 10E2 12F1 lOAO 10E2 1212 lOAO 12G3 1012 lOAO 10G3 1012 1212 9G1 1012 lOFl 9G1 11F2 9F3 9G1 10E2 9F3 llDl 9D1 9F3 lOAO 9D1 llGl 9E1 9D1 1012 9E1 1111 9A1 9E1 9G1 9A1 lOFl 9B1 9A1 9F3 9B1 10E2 11F2 9B1 9D1 11F2 lOAO llDl 12H2 9E1 llDl 1012 llGl 9A1 llGl 9G1 1111 9B1 nil 9F3 11F2 13H1 9D1 llDl 9E1 llGl 9A1 nil 9B1 Figure 5-'+ Transient Fault Table Continued iUdo 15D0 1712 i6d1 16g1 i6di kl 1 2 3 i» 5 6 7 8 9 10 11 12 13 li+ 15 16 17 18 19 U3 2P2 3P1 k02 5J3 6P3 7J'+ 803 803 8G2 11J2 12J1 13J2 lUjl 15J2 l6Jl 17J1 l8j2 19J1 101 2M0 1J1» UKO 501 6N0 7P1 8L0 BLO 8D0 10H2 llHl 12H2 13H1 ll+H2 15H1 16H1 17H2 18H1 ILl IMl 5KL 7M1 9H1 9G1 10G3 11F2 12E3 13G1 1UG2 15G2 16g1 17G3 IKl lUl 5K1 7N1 lOJl 9F3 lOFl llDl 12B0 13D1 l^tDO 15D0 16d1 17F1 9D1 10E2 llGl 12F1 1311 1712 9E1 lOAO nil 12G3 12E3 16g1 9A1 1012 10G3 1212 12B0 16d1 9B1 9G1 lOFl 11F2 12F1 9F3 10E2 llDl 12G3 9D1 10 AO llGl 1212 9E1 1012 nil 11F2 9A1 9G1 10G3 llDl 931 9F3 lOFl llGl 9D1 10E2 nil 9E1 lOAO lOFl 9A1 1012 10E2 9B1 9G1 lOAO 9F3 1012 9D1 9G1 9E1 9F3 9A1 9D1 9B1 9E1 9A1 9B1 Permanent Favilt Table U2 Bl J3 JU 12 Al LI Nl Dl DO Fl II El AO BO Kl KO LO Ml MO NO HI H2 Gl G2 G3 F2 F3 E2 E3 01 02 03 PI P2 P3 Jl J2 1 1 2 1 3 1 h 1 5 1 6 1 7 1 8 1 9 1 10 1 1 11 1 1 1 12 1 . 1 1 1 1 13 1 1 1 1 1 1 lU 1 1 1 1 1 1 1 15 1 1 1 1 1 1 1 16 ■ 1 1 IT 1 1 18 1 1 19 1 1 1 Figure 5-5 Fa\ilt Dictionary U3 7. CONCLUSIONS A computer program has been written which uses the test procedure described to generate test patterns to detect single faults in combinational circuits. The test patterns which are generated are nearly the minimal set of test patterns necessary to test single faults. This computer program will be extended so that it will generate test patterns to detect single faults in synchronous and asynchronous seq_uential circxiits . The amount of computer time and the number of test patterns req_uired to detect all single faults in sequential circtiits will determine the worth of this test procedure. If a test procedure is desired which will detect all favilts, then in addition to detecting single faiilts, fault pairs should also be detected. Often some random tests can be applied to the circuit or the source current can be monitored to increase the probability that a fault pair wo\ald be detected to an acceptable figure. The fault table and fault dictionary can easily be created and are useful in fault identification. However, it is questionable whether it is worth the additional test patterns and computer time necessary to distinguish fault classes. hk LIST OF REFERENCES Armstrong, D. B. On Finding a Nearly Minimal Set of Faiolt Detection Tests for Combinational Logic Nets, IEEE Transactions on Electronic Computers, February 1966, pp. 66-73. Howarter, D. R. The Selection of Failure Location Tests by Path Sensitization Techniques, University of Illinois Coordinated Science Laboratory, Report R-3l6, August I966. Jones, E. R. and Mays, C. H. Automatic Test Generation Methods for Large Scale Integrated Logic, IEEE Journal of Solid State Scale Integrated Logic, IEEE Journal of Solid State Circuits, Vol. SC-2, #i|, December I96T, pp. 221-225. Kautz, W. H. Fault Testing and Diagnosis in Combinational Digital Circuits, IEEE Transactions on Electronic Computers, February 1966, pp. 66-73. Lewis, R. S. An Approach to Test Pattern Generation for Synchronous Sequential Circuits, Ph.D. Thesis, Southern Methodist University. Roth, J. P. Diagnosis of Automata Failures: A Calculus and a Method, IBM Journal of Research and Development, Vol. 10, July 1966, pp. 278-291. 7. Roth, J. P., Bouricus, W. G. and Schneider, P. R. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits, IEEE Transactions on Electronic Computers, October 1967, pp. 567-579. 8. Powell, T. J. A Procedure for Ranking Diagnostic Test Inputs, University of Illinois, Coordinated Science Laboratory, Report R-35^, May I967. 9. Seshu, S. and Freeman, D. N. The Diagnosis of Asynchronous Sequential Switching Systems, IEEE Transactions on Electronic Computers, Vol. 10, J\ily 1966, pp. 278-291. )rmAEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) AEC REPORT NO. COO-IU69-OIIT 2. TITLE A Test Mode Approach to Fault Detection in Sequential Circuits TYPE OF DOCUMENT (Check one): Ij^ a. Scientific and technical report n b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): tx l a. AEC's normal announcement and distribution procedures may be followed. r~| b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. [~| c. Make no announcenrwnt or distrubution. REASON FOR RECOMMENDED RESTRICTIONS: SUBMITTED BY: NAME AND POSITION (Please print or type) C. W. Gear, Professor of Computer Science and Applied Mathematics Organization Department of Computer Science University of Illinois Urbana, Illinois 618OI i^"""" ,jZ&to^ ^ Date May lU, 1969 FOR AEC USE ONLY 7 AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: 8.j PATENT CLEARANCE: U a. AEC patent clearance has been granted by responsible AEC patent group. U b. Report has been sent to responsible AEC patent group for clearance. I LJ c. Patent clearance not required.