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2 UIUCDCS-R-72-515 
 
 Jy^tCt/^- 
 
 coo 2J469-0209 
 
 RASER: RANDOM TO SERIAL CONVERTER 
 
 by 
 
 TAKEHIKO KATOH 
 
 June, 1972 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/raserrandomtoser515kato 
 
UIUCDCS-R-72-515 
 
 RASER: RANDOM TO SERIAL CONVERTER 
 by 
 
 TAKEHIKO KATOH 
 
 June, 1972 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 This work was supported in part by Contract No. AEC AT(ll-l)lU69 
 and was submitted in partial fulfillment of the requirements for the 
 degree of Doctor of Philosophy in Electrical Engineering, June, 1972. 
 
Ill 
 
 ACKNOWLEDGEMENT 
 
 The author wishes to express his gratitude to his thesis advisor, 
 Professor W. J. Poppelbaum, for suggesting this problem and for his interest 
 and help during its solution. Deep thanks also go to Professor W. J. Kubitz 
 for his counsel and suggestions. 
 
 The author wishes to thank Mr. Frank Serio and his technical staff 
 in the fabrication group and machine shop for the work they contributed toward 
 the building of RASER. 
 
 Thanks also go to Mrs. Barbara Bunting for typing the thesis and 
 the staff in the drafting group for drafting the figures and staff in the 
 printing shop for duplicating the thesis. 
 
 Finally, the author thanks his wife, Linda, for her support and 
 encouragement through this project. 
 
iv 
 TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. OPERATIONS PERFORMED BY RASER 6 
 
 2.1 Random to Serial Conversion 6 
 
 2.2 Rotation and Reflection Around the Axes 7 
 
 2.3 Shrinking a Picture 11 
 
 2.1+ Picture Expansion 16 
 
 3. LOGICAL DESIGN OF RASER 23 
 
 3.1 Random to Serial Conversion 23 
 
 3.2 Rotation and Reflection Operations 28 
 
 3.3 Shrinking Operation 30 
 
 3.1+ Expansion Operation 33 
 
 3.^.1 First Step of Expansion Operation 33 
 
 3.^.2 Second Step of Expansion Operation (Format 
 
 Conversion) 35 
 
 k. CONCLUSION 1+0 
 
 LIST OF REFERENCES 1+1 
 
 APPENDIX 1+2 
 
 VITA 51 
 
V 
 
 LIST OF FIGURES 
 
 Figure Page 
 
 1. Fundamental Diagram of RASER 2 
 
 2. Word and Bit Location in the Binary Video Memory for (x, y) 
 Pair k 
 
 i i 
 
 3. Relation Between (x, y) and (x , y ) for Rotation 8 
 
 k. Relation Between (x, y) and (x , y ) for Reflection Around 
 
 the Axes 10 
 
 5. Examples of 1/2 x 1/2 Shrinking in 2 Typical Cases .... 13 
 
 6. Location of M(x , y ) in the Binary Video Memory 17 
 
 7. Address, A (x , y ) , in the Binary Video Memory 21 
 
 8. Block Diagram of RASER 2k 
 
 9. Timing Chart of Display Clock and Master Counter 25 
 
 10. Timing Control Circuit 27 
 
 11. Logic to Video Converter Circuit 29 
 
 12. Circuits for Picture Rotation, Reflection and Shrinking 
 Operation 31 
 
 13. Sample Rate Control Circuit 32 
 
 Ik. Difference Computation (for Expansion) Circuit 3^- 
 
 15. Matrix Pattern Generator Circuit .- 36 
 
 16. Format Conversion Circuit 38 
 
 17. Timing Chart of Format Conversion 39 
 
1. INTRODUCTION 
 
 In the computer graphic display field the raster format display 
 (of which standard television is a particular type) has certain advantages 
 over a random format type display in some applications. These advantages are 
 
 1) The efficiency of this format is greater than for a random for- 
 mat display when the amount of information to be displayed is large but the 
 scanning mechanism does not have a high frequency response, such as for 
 large screen displays using lasers or large screen CRT's. 
 
 2) There is no overflow problem when the amount of information 
 to be displayed is large and the duration of the display time is limited 
 (typically 1/30 of a second). 
 
 3) Costs are generally lower for the display, because of the 
 high volume of production of raster T.V. equipment. 
 
 The system described herein is named RASER (RAndom to SERial 
 Converter) since the raster format is SERIAL while the data from the computer 
 is RANDOM. This kind of conversion may also be called D/V conversion 
 (Digital- to- Video Conversion) or simply scan conversion. The purpose of 
 RASER is to bridge the gap between the random output of a computer and the 
 serial requirements of a raster display. 
 
 The fundamental idea of RASER is shown in Figure 1. Coordinate 
 pairs (x, y) corresponding to random locations in an xy-plane come into the 
 converter at a fixed rate (e.g. a pair every 3 M>s). In RASER a kK by lo bit 
 core memory with a full cycle time of 1 u-s, and a split cycle time of 1.1 \xs 
 plus time, is used as a binary video memory. Because of the size of the 
 binary video memory, the (x, y) pairs are 8 bits accuracy each. 
 
o 
 
 Q 
 
 ■p 
 
 64 
 
 •H 
 
 &4 
 
Let (x, y), the input to RASER, be defined as 
 
 7 i 7 i 
 
 x = Z x. -2 and y = Z y. -2 
 i = X 1= X 
 
 where x and y are sign digits and negative numbers are expressed as 2's 
 
 complements. Let (x 1 , y') be input to the binary video memory. The 
 
 x ' = x * 2^ + Z x . • 2 1 
 ' i = X 
 
 7 6 - i 
 and y' = y -2 ( + Z y -2 . 
 
 ' i = 
 
 Then "1" will be stored in the binary video memory at the bit b of the worl 
 at address A, where 
 
 i 11 6 - ±+h - 3 6 i-k 
 
 b= L x.-2 and A = y "2 + Z y. '2 + x^'2 + Z x.*2 
 i = x 7 i = o - 7 i „ U i 
 
 See Figure 2. "1" corresponds ultimately to an unblanked electron beam and 
 "0" to a blanked electron beam on the CRT screen. 
 
 For the display, the binary video memory is read out serially from 
 A = to A = ^095. The first point in the ith raster line is b = and 
 A = 16' i. The second point in the ith raster line is b = 1 and A = l6'i. The 
 (16 'j + i)th point in the ith raster line is b = I and A = l6"i + j. 
 
 With simple operations on the incoming (x, y) pairs, RASER car. dis- 
 play the picture rotated through 90 , 1^0 or 27O (clockwise) or reflected 
 about the x = y, x = -y, x = or y = axis. By shifting x and y by one 
 or two bits RASER can display a shrunken picture. 
 
 Let (x', y') be the input to the binary video memory, 
 
 7 6 ^ i 1 
 then x* = x''-2' + x -2 + Z x.'2 
 
 ' ' ± = 1 X 
 
-> x 1 
 
 Y' 
 
 V A=0 
 
 t 
 
 t 
 
 "5 5 C 
 
 A = 16 
 
 A=l 
 
 t 
 
 V A= 17 
 
 rz 
 
 A=15 
 
 RASTER LINE 
 
 $ 
 
 RASTER LINE i + 1 
 
 b=0 
 
 b=Zxi-2' 
 
 i=0 
 
 a 
 
 b = i 
 
 b = 15 
 
 BINARY VIDEO MEMORY 
 4K by 16 bits 
 
 I 
 
 A=4095 
 
 Figure 2. Word and Bit Location in the Binary Video Memory for (x, y) Pair 
 
7 6 ^ — i 1 
 
 and y' = y"-2' + y "2 + Z y. *2 for a 1/2 x 1/2 picture, 
 
 7 ' i = 1 X 
 
 z- j- 6 . 
 
 or x' = x"-2 7 + x"-2 + x^-2- 5 + Z x*2 
 
 7 6 7 i = 2 i 
 
 7 6 5 IP 
 
 and y* = y"-2' + y>'-2 + y «2 3 + Z y. «2 " for a 1/U x 1/1+ picture, 
 
 7 o r ± = 2 i 
 
 where x", x^. y" and y!-' are specified to RASER by the operator, and the 
 7 o 7 o 
 
 incoming coordinates are: 
 
 7 7 
 
 i i 
 
 x = Z x. *2 and y = Z y. '2 . 
 
 " " i 
 i = i - 
 
 RASER can also display an expanded picture of 2 x 2 or 1+ x h with 
 straight-line-interpolation requiring no additional computation time. How- 
 ever, for this operation the (x, y) pairs are required to be random with 
 respect to the raster scan but the distance, d, of successive incoming (x, y) 
 
 pairs, (x . , y.) and (x . , . y. n ), must be less than 2, where d is defined as 
 J J j+1' J+l 
 
 d=maxl|x. -x. +1 |, |y. -y J+1 |). 
 
2. OPERATIONS PERFORMED BY RASER 
 
 There are four main operations performed by RASER. 
 
 The first and main operation is random to serial conversion. The 
 second is rotation and reflection of a display, the third is the shrinking 
 and placing of the display in the proper portion on the CRT screen. The last 
 and most interesting operation is expanding a part of the picture with 
 straight line interpolation. 
 2.1 Random to Serial Conversion 
 
 In RASER the random to serial conversion is accomplished simply by 
 storing l's at the correct bit locations of the binary video memory and read- 
 ing out these bits at the proper moment. 
 
 Since the raster timing must provide overall control of the conver- 
 sion as well as display process, all digital and display functions must be 
 timed to the raster synchronization pulses. 
 
 Every raster line contains 256 points (16 words) and has about 
 6k usee duration. In order to make the display square, both the left and the 
 right ends of the raster must be blanked. Therefore, each point displayed 
 on the CRT screen is about 200 nsec in duration and is generated by an 
 unblanked or blanked electron beam on the CRT screen. This means a word 
 (16 bits) must be read out every 3.2 usee from the binary video memory. A 
 R/R cycle (Read Restore cycle) requires 1 usee, and there are, thus, only 2.2 
 usee remaining between cycles. In order to store l's for points in the 
 binary video memory without erasing the l's already there, the R/M/W (Read 
 Modify Write) cycle must be used. It takes 1.1 usee plus wait time. There- 
 fore one R/R cycle and one R/M/W cycle can be completed in 3.2 usee. 
 
7 
 
 The binary video memory contains 256 raster lines but there are 
 only 2^1 visible raster lines in one television field (1/60 of a second or 
 1/2 of a frame). RASER displays the whole content of the binary video memory 
 for each field. Thus, 8 lines of the top and 8 lines of the bottom of the 
 binary video memory will not be displayed. 
 2.2 Rotation and Reflection Around the Axes 
 
 Let the (x, y) pair be the input to RASER and (x*, y') be input 
 to the binary video memory as defined previously. Then x' and y' for the 
 various rotations are given as follows : 
 
 Case i) No rotation 
 
 x* = x -2 7 + Z x. '2 1 . 
 7 i =0 x 
 
 7 6 - i 
 
 y' = y 7 -2 ( + Z y -2 . 
 
 ' i = 
 
 See Figure 3(a). 
 Case ii) 90° clockwise rotation 
 
 - 7 6 i 
 
 x' = y -2' + Z y. -2 . 
 
 y i = 1 
 
 - 7 6 i 
 y* = x-2' + Z x. '2 . 
 
 7 i = X 
 
 See Figure 3(b). 
 Case iii) 180 clockwise rotation 
 
 7 6 - i 
 
 x'=x'2'+ Z x.-2. 
 
 7 i = X 
 
 - 7 6 i 
 y» = y -2' + Z y -2 . 
 
 ' i = 
 See Figure 3(c). 
 
8 
 
 -^x 
 
 >> x 
 
 ) 
 
 
 
 ^ ( x ,y) 
 
 
 
 
 
 «^ A 
 
 y 
 
 (a) No rotation 
 
 (c) 180° rotation 
 
 FT 
 
 ->X" 
 
 \ 
 \ 
 \ 
 \ 
 \ 
 \ 
 \ 
 
 \ 
 
 
 
 ^90° 
 
 
 \m 
 
 \ 
 
 f(x,y) 
 
 ST - ■■■■ 
 
 (x,yK 
 
 ^ 
 
 pi 
 
 y 
 
 
 ~270° 
 
 (b) 90° clockwise rotation 
 
 (d) 270° clockwise rotation 
 
 Figure 3. Relation Between (x, y) and (x , y ) for Rotati 
 
 on 
 
Case iv) 270 clockwise rotation 
 
 x ' = y • 2 7 + Z y . • 2 1 . 
 ' i = 
 
 7 6 - i 
 y' = x # 2' + S x.-2 . 
 
 ' i = X 
 See Figure 3(d). 
 Case v) Reflection around the axis, x = 0. 
 
 7 6 - i 
 
 x* = x *2' + Z x.-2 . 
 7 i ^O 1 
 
 7 6 - i 
 y* = y 7 '2 f + Z y -2 . 
 
 ' i = 
 See Figure 4(a). 
 Case vi) Reflection around the axis, y = 0. 
 
 x' = 3L*2' + Z x. -2 1 . 
 
 7 i ^o 1 
 
 - 7 6 i 
 y* - y -2 ( + z y "2 . 
 
 ' 1 = 
 
 See Figure 4(b) . 
 Case vii) Reflection around the axis, x = y. 
 
 x' = y -2 7 + Z y -2 1 
 ' i = 
 
 y' = x -2 7 + Z x -2 1 . 
 ' i = 
 
 See Figure 4(c). 
 
10 
 
 \ 
 
 i 
 
 \ 1 
 
 \ 
 
 \(x',y) 
 
 $ » 
 
 
 / 
 
 
 s 
 
 Y ^* ^ 
 
 s 
 
 
 
 
 i 
 y 
 
 (a) Reflection around the 
 axis, x = 0. 
 
 (c) Reflection around the 
 axis, x = y 
 
 ^ x 
 
 x = -y 
 
 (b) Reflection around the 
 axis , y = 
 
 (d) Reflection around the 
 axis, x = -y 
 
 Figure h. Relation Between (x, y) and (x , y ) for Reflection Around the Axe* 
 
11 
 
 Case viii) Reflection around the axis, x = -y. 
 
 7 6 - i 
 
 x' = y -2' + Z y. '2 . 
 
 ' i = 
 
 - 7 6 i 
 y* = x_-2' + Z x *2 . 
 
 ' i = 
 
 See Figure ^(d). 
 
 2.3 Shrinking a Picture 
 
 RASER can shrink a picture to 1 x 1/2, 1 x l/k, 1/2 x 1, 1/2 x 1/2, 
 
 1/2 x l/k, l/k x 1, 1/k x 1/2, 1 or 1/1+ x 1/k x 1/k. Again let the pair (x, y) 
 
 be the input to RASER and (x 1 , y') be the input to the binary video memory, 
 
 where 
 
 7 7 
 
 i i 
 
 x = Z x. "2 and y = Z y. "2 , 
 
 i « i = 
 
 and x and y are sign digits. 
 
 7-6 ^ i-1 
 If x' = x""2 + x '2 + Z x.«2 , the picture is shrunk by one 
 
 half in the x direction. If x" = 0, the picture is placed in the left half 
 of the screen. If x" = 1, picture is placed in the right half of the screen. 
 
 Similarly, if y' = y"-2' + y '2 + Z y •2 1 ~ , the picture is 
 
 ' ' i = l 1 
 
 shrunk by one half in the y direction. If y" = 0, it is placed in the upper 
 
 half of the screen, and if y' T = 1, it is placed in the lower half of the 
 
 screen. 
 
 6 
 
 If x' = x"-2 7 + x"-2 + x -2 5 + Z x.-2 1-2 , the picture is 
 7 6 7 is2 i 
 
 shrunk by 1/k in the x direction and if 
 
y . B y ». 2 7 + y"-2 6 + y'2 5 + I y *2 
 I • i „ o x 
 
 12 
 
 1-2 
 1.2 
 
 the picture is shrunk by 1/U in the y direction. 
 
 For x", x'J, y" and y'J there are 16 possible combinations and thus 
 
 16 different possible locations for the shrunken picture for l/k x 1/4 case. 
 Therefore the (x , y ) pair can be any pair of 
 
 f> 6 
 
 x' = x -2 7 + Z X.-2 1 , x"-2 7 + x -2 + Z X.-2 1 " 1 , or 
 7 i = X 7 7 i = 1 x 
 
 7 6 R^iP 7 ^ i 
 
 x ... 2 r + x .,. 2 o + - 2 P + 2 x . . 2 ±_ ^ and y' = y. -2' + Z y.-2, 
 
 7 6 7 i =2 1 x i = a 
 
 6 6 
 
 y"'2 7 + y-2 6 + Z y'2 1 " 1 or y'"2 7 + y;-2 6 + y„-2 5 + Z y '2 1 ' 2 . 
 ' ' i = 1 ' ' i = 2 
 
 However, difficulties arise for certain cases. Let the four succes- 
 sive (x, y) pairs be (x., y.) for j = 1, 2, 3 and h. Let 
 
 J J 
 
 7 7 
 
 x. = Z x. .-2 1 and y. - Z y . . '2 1 for j = 1, 2, 3 and 4. Let (x'., y 1 .) 
 
 j i = j,i j i = j.i u J' "y 
 
 for j = 1, 2, 3 and 4 be the input to the binary video memory. Also let 
 
 _ >» 6 . , ^ 6 . , 
 
 x: = x"-2 ( + x~-2 b + Z x -2 1 " 1 and y« = y"-2 7 + y *2 b + Z yTT' 21 " 
 J i J j I j_-iJ5- 1 - J i Jsl i — 1 ' 
 
 for j = 1, 2, 3 and k for a case of 1/2 x 1/2. 
 
 Suppose |x.-x. ,-| =1 and ly.-j. , I = 1 for j = 1, 2 and 3« Then 
 1 J J+H |0 J J j+l! 
 
 (x . , y.)' s are located diagonally in the original picture. (See an example 
 J J 
 
 in Figure 5(a).) Suppose d'(j, j + 1) = 1 for j = 1, 2 and 3 where 
 
 d'(j, j + 1)= max (|x' - x' . I, ly! + y • . I) for j = 1, 2 and 3- 
 
 Then after being shrunk to 1/2 x 1/2, four distinct points are still on the 
 screen. (See Figure 5(b).) For this case the shrunken line is two points thick. 
 
13 
 
 - 1 
 
 m 
 
 - * 
 
 x 
 
 I 
 
 X 
 
 ^ 
 
 rO 
 
 - ro 
 
 ro 
 
 GO 
 CJ 
 
 I— I 
 II 
 
 • — "I 
 
 o 
 
 " ro 
 
 - ro 
 
 X 
 
 o 
 
 II 
 
 ro 
 
 CVJ 
 
 2 
 
 or 
 
 i 
 
 /Tk 
 
 ro 
 
 
 CVJ 
 
 CVJ 
 X 
 
 
 ro 
 
 
 * 
 
 
 X 
 
 
 X 
 
 
 \ 
 
 
 7 
 
 
 
 \- 
 
 y 
 
 
 
 ■-I 
 
 
 
 1-1 
 
 
 
 
 l-H 
 
 
 
 
 >— - 
 
 
 
 
 
 
 
 
 >s 
 
 
 
 
 
 
 
 
 p4 
 
 
 
 
 X 
 
 
 
 T3 
 
 C 
 
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 CVJ 
 
 2 
 
 or 
 
 x 
 
 CO 
 
 s<N 
 
 /v 
 
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 >» 
 
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 T 
 
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 r-t 
 
 CM " 
 
 X 
 
 
 
 
 
 •—> 
 
 
 
 
 ,_^ 
 
 
 
 
 l—t 
 
 
 
 to 
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 C\J 
 
 H 
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 I 
 
 05 
 
 to 
 <u 
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 ctf 
 
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 cu 
 
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 b0 
 
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 d 
 
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14 
 
 The simplest solution to this problem is to write only every other 
 incoming (x, y) pair into the binary video memory as long as it is not an 
 isolated point. 
 
 Let d(j, j + 1) be defined as follows: 
 
 d(j, j + 1) = max [\x^ - X. + J , |y - y J+1 l) where (*y Yj ) and 
 (x. , , y. , ) are successive incoming pairs. Let I be a set of successive 
 positive integers, j, such that for all jel d(j, j + 1) = 1. If d(j, j + 1) = 
 then the current point is ignored and the next (x, y) pair for which 
 d(j, j + 1) - 1 will be named (x. +1 , y, +1 )- If d(j, j + 1) > 1 then j + 1 
 will start a new set. If I contains only one number then this point is 
 called an isolated point. 
 
 Let I 1 = {k + 2n(k + 2nel for n = 0, 1, 2, ..., and k is the smallest 
 number in 1} . 
 
 Let a 1 be written in the binary video memory at (x ! . , y'. ) for jel' 
 
 J J 
 
 instead of jel. Then the line is not two points thick for jel and there is 
 no discontinuity along the line for jel. Consider the following possibilities: 
 Case i) I contains only one number. Then I = I' by definition 
 
 of I'. 
 Case ii) j and j + lei and d'(j, j + 1) = then 
 
 (x!, y') = ( x j +1 > y^ +1 ) and also d€j' or j + lei' 
 whichever it may be it does not break the line. See 
 an example in Figure 5(c) and (d), j -2. 
 Case iii) j and j + lei and d'(j, j +1) =1 
 a) j £ I' 
 
 Then there is j - lei' by definition of I'. 
 
15 
 
 1) d*(j - 1, J) - 1 
 
 Since d is a distance function 
 
 d(j - 1, J + 1)£ d(j - 1, j) + d(j, j + l) = 2. 
 
 d'(j - 1, j + 1) 
 
 = maxt l x 'j-i - *W' ly'j-i- y'l+iH 
 ^maxtd^-ix.^-x.^i, (V«-|y d .i-y J+ il) 
 
 - (l/2).max{|x._ 1 - x . + J , [y.^ - y. +1 |} 
 
 * (l/2)'d(j - 1, j + 1) 
 Since the picture is shrunk to l/2 x l/2 the 
 distance between two points is shrunk by 1/2, 
 too. Therefore d'(j - 1, j +1) 
 
 = (l/2)'d(j - 1, j + 1).<: (1/2) '2 = 1 
 and the line is still continuous . 
 
 2) d'(j - 1, j) = 
 This is case ii. 
 
 b) j + 1 { I 1 . 
 
 If j + 2 i I then the end point-point is lost but it 
 does not effect continuity. If j + 2el then j + 2€l' 
 and this is case iiia. 
 In any case the continuity of a line is not effected by changing 
 I to I'. Clearly, the thickness of a line is reduced since I' contains half 
 as many elements as I and I ' is large enough not to break the continuity of a 
 line. 
 
 Shrinking a picture to l/U x l/k is the same as shrinking to 1/2 x 1/2 
 twice. 
 
16 
 
 2.U Picture Expansion 
 
 Let the pairs (x, y) be the input to RASER and let them be in the 
 part of the original picture which is to be expanded. 
 
 Let (x', y 1 ) be the input to the binary video memory and d, d' and 
 I be defined as in the previous section. 
 
 Then for h x k expansion 
 
 d*(j, j + 1) ^maxtlxj - xj +1 |, \y' - jr' |) 
 
 =max(V|x. - x. +1 |, *|y. +y J+1 |) 
 
 = U-max{|x. -x. + J, |y. + y. +1 |} 
 
 = U-d(j, j + 1) for j, j + l€l. 
 
 Since d(j , j + 1) = 1 for j , j + lei, 
 
 d'(j, 3 + 1) - Vl - ^ for j, j + lei. 
 
 Therefore the points between (xl , y'. ) and (x . , , , y . , , ) must be 
 
 J J J+l 0+1 
 
 interpolated. Because of the hardware realization implementation a first 
 order polynominal interpolation is employed here. However, for an isolated 
 point there is no way to interpolate and, unfortunately, an isolated point 
 will vanish, for the expansion operation. 
 
 Since R/R cycle takes at least 1 [isec and one point in the raster 
 scan takes 200 nsec, expansion must be a two-step operation. 
 
 However, for simplicity suppose expansion is a one-step operation. 
 Since a word in the binary video memory is 16 bits long, let the word be a 
 h x h matrix, rather than a 16 bit string, or a 1 x 16 matrix along the raster 
 scan. Then (x', y') pairs and matrices are in a one-to-one correspondence. 
 Let a matrix corresponding to (x', y') be M(x', y') and 
 
17 
 
 ■» X' 
 
 y 
 
 M(0,0) 
 
 M(1,0) 
 
 M(2,0) 
 
 • • • 
 
 M(63,0) 
 
 M(0,1) 
 
 M(l,l) 
 
 M(2,l) 
 
 • • • 
 
 M(63,I) 
 
 M(0,2) 
 
 M(l,2) 
 
 M(2,2) 
 
 • • • 
 
 M(63,2) 
 
 
 
 
 ^ 
 
 M(k,l)^*3 
 
 , uuu j( • • • RASTER SCAN 
 
 >». 
 
 
 
 
 
 X X X X 
 
 xxxx 
 
 
 T 
 
 v. 
 
 • 
 • 
 • 
 
 • 
 
 • I 
 1 
 
 • | 
 
 • 
 
 1 
 
 »j 
 
 • • • 
 
 1 * 
 
 
 • • • 
 
 M(0j63) 
 
 M(l,63) 
 
 M(2,63) 
 
 
 M(63,63) 
 
 I I 
 
 Figure 6. Location of M(x , y ) in the Binary Video Memory 
 
18 
 
 b b l b 2 b 3 
 
 \ b 5 b 6 b 7 
 
 b 8 b 9 b lO b ll 
 
 b 12 b 13 b lU b l 5 
 
 where b, is bit i of the word in the binary video memory, and the address 
 
 for M(x', y 1 ), A(x', y 1 ), is defined 
 
 A(x', y') = E (v-2 6 + x ) 2 1 . 
 i = 
 
 M(x', y') is defined as follows: 
 
 Case i) x*. - x' = -1 for j, j + l€l 
 
 If yj - n+i • - 1 ' 
 
 M(x!, y<) = 
 
 10 
 
 10 
 10 
 1 
 
 if r A - y- +1 . o. 
 
 M(x!, yj) = 
 
 J J 
 
 1111 
 
 
 
 
 
 if yj - y^ +1 - i, 
 
 
 
 
 
 
 
 r 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
19 
 
 Case ii) x\ - x' = for j, j + lei 
 
 if yj - yj +1 - -X, 
 
 M(x', yl) - 
 
 J J 
 
 10 
 
 10 
 
 10 
 
 10 
 
 If y j " y j + i * l > 
 
 M(x j> y j + i : 
 
 10 
 10 
 10 
 
 1. ° ° 2_ 
 
 Since d(j, j + 1) = 1 for j, j + lei, there is no such case that 
 
 x j - Si ■ ° «* yj - Si = °- 
 
 Case iii) x! - x' = 1 for j, j + lei 
 J J + i 
 
 if y: - y: +1 • -i 
 
 M(xj +1 , yp = 
 
 10 
 
 10 
 
 2 
 
 1111 
 
 
 
 
 
 j j+i 
 
 M(x j+1 , yj) . 
 
20 
 
 If y j " y j+l " l ' 
 
 M ( x j + 1' y j + l } 
 
 10 
 
 10 
 10 
 
 1L ° ° _L 
 
 The relation between M(x ' , y') and the binary video memory is 
 shown in Figure 6. The raster line consists of ith row of 6h matrices and 
 every h points a new word must be read out and the R/R cycle must be 
 800 nsec - this is too fast for RASER. 
 
 To solve this problem let the 1 x 16 matrix, M'(k, Z) , be defined as 
 • M'(k, Z) 
 
 M*(k + 1, Z) 
 M'(k + 2, Z) 
 M*(k + 3, &) 
 
 = [M(k, Z) ' M(k + 1, Z) ! M(k + 2, &) \ M(k + 3, A)] 
 
 k x 16 
 
 k x 16 
 
 where k and I are non-negative integers less than 6k and k is divisible by k, 
 then M"(k, Z) , M'(k + 1, Z) , M' (k + 2, Z) and M'(k + 3, &) are the matrices 
 stored in the binary video memory for display. 
 
 Conversion from M's to M"s is called format conversion. Let an 
 address of M(x', y') A'(x', y'), be redefined as 
 
 A'(x', y') = S y"2 + x -2 J + x -2 + Z x.2 . 
 X = U i = 2 X 
 
 (See Figure 7). 
 
 Read out the k words, at A*(k, Z) , A'(k + 1, ^), A'(k + 2, Z) and 
 
 A'(k + 3, Z) of the binary video memory. Then form a h x 16 matrix 
 
21 
 
 ■> X 
 
 
 
 4 
 
 8 , 
 
 1 
 
 5 
 
 9 , 
 
 2 
 
 6 
 
 10 
 
 3 
 
 7 
 
 11 
 
 64 
 
 68 
 
 72 
 
 65 
 
 69 
 
 73 | 
 
 66 
 
 70 
 
 74 
 
 67 
 
 71 
 
 75 , 
 
 ■ 128 
 
 132 
 
 136 
 
 4035 
 
 4039 
 
 4043 
 
 60 
 61 
 62 
 63 
 
 124 
 
 125 
 
 126 
 
 127 
 
 187 
 
 4095 
 
 I I 7 
 
 Figure 7. Address, A (x , y ), in the Binary Video Memory 
 
22 
 
 [M(k, I) \ M(k + 1, i) ! M(k + 2, I) M(k + 3, &)]. Then put these 
 matrices back into the binary video memory such that the first row of the 
 matrix is at A'(k, I) and the second row is at A'(k + 1, I) and the third 
 row is at A*(k + 2, 4)and the fourth row is at A'(k + 3, I). This is the 
 second operation of the two-step operation. 
 
 For a 2 x 2 expansion a matrix M(k, I) is divided into four 2x2 
 submatrices such that 
 
 M(k, £) 
 
 M i:L (k, Z) M 12 (k, i) 
 M 21 (k, |) M 22 (k, i) 
 
 Two l's are placed in each submatrix for each (x', y') pair and submatrices 
 and (x ' , y 1 ) pairs are in a one-to-one correspondence. 
 
23 
 3. LOGICAL DESIGN OF RASER 
 
 In this section the logic of the various operating modes of RASER is 
 described. A block diagram of RASER is shown in Figure 8. 
 3.1 Random to Serial Conversion 
 
 In this operation the random input, (x, y) pair goes through the samp- 
 ing rate control and the shrinker unchanged and is decoded at the bit decoder 
 before going into the data selector. 
 
 Since the TV monitor sync signals cannot be changed, all timing in 
 RASER is synchronized to these sync signals. The 5MHz display clock is gen- 
 erated by two cross-coupled monostable multivibrators. The shaped negative 
 edge of the delayed TV horizontal sync pulse (an approximately 500 nsec nega- 
 tive pulse) stops the display clock, and the shaped positive edge starts the 
 display clock again. The delay for the horizontal TV sync pulse is adjustable 
 and this determines the distance between the left edge of the picture and the 
 left edge of the CRT. 
 
 The display clock output is fed to a U-bit master counter, which is 
 cleared by the delayed TV horizontal sync pulse. When the master counter is 
 in the state 0011 a R/R (Read Restore) clock signal is produced (Refer to the 
 timing chart shown in Figure 9)« At count 1000 of the master counter the out- 
 put of the memory is transferred into a 16 bit (two 8-bit) parallel- in/serial- 
 out shift register and shifted by the display clock. The output of this shift 
 register is an unblanked binary video signal. At count 1011 of the master 
 counter a R/M/W (Read Modify Write) mode signal and a R/R clock signal are pro- 
 duced. The R/R address counter is also incremented by one at this time. At 
 count 1111 of the master counter the C/W (Clear Write) clock signal of the R/M/W 
 mode is produced. 
 
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26 
 The U least significant bits of the R/R address counter are cleared 
 by the delayed horizontal TV sync pulse. The rest of the R/R address counter 
 is cleared by a modified TV vertical drive signal, see Figure 10. 
 
 The binary video signal from the shift register is mixed with four 
 blanking signals: the mixed blanking of the TV sync generator, the blanking 
 for location indication, the blanking at the end of the raster lines and the 
 blanking generated during the clearing of the binary video memory. 
 
 The last three blanking signals above are associated with the R/R 
 address, and master-slave type flip-flops are used for the following reason. 
 Although the R/R address counter is incremented by one at count 1011, the bin- 
 ary video at this address is transferred into the 16-bit shift register and the 
 first bit of the binary video signal is available at count 1000 of the master 
 counter of the next cycle. The blanking must be synchronized with the binary 
 video output of the shift register rather than the address counter. For example, 
 in RASER the display clock is started by the delayed horizontal TV sync signal 
 and, simultaneously the master counter and the h least significant bits of the 
 R/R address are cleared. The l6-bit binary video signals of address l6*n are 
 read out from the binary video memory at count 0011 of the master counter, where 
 n = 0, 1, 2, ..., 255' However, the first bit of the binary video signal is 
 not available until the 1000 count of the master counter. Therefore, the video 
 signal must be blanked until the 1000 count of the master counter. Similarly, 
 at the end of the line of the display the R/R address becomes l6'(n + 1) but 
 the last bit of the binary video signal at address l6*n + 15 of the binary 
 video memory has not been displayed yet. The video signal is again blar-ked 
 just before the 16-bit binary video signals from address l6*(n + 1) are trans- 
 ferred into the 16-bit shift register. Therefore a master- slave typ^ flip- 
 flop utilizing the 0111 count of the master counter as its clock is used to gen- 
 erate the blanking signal. 
 
27 
 
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28 I 
 
 the video signals are blanked the display clock is kept running 
 to generate R/M^ mode signals. The display clock is stopped for about 500 nsec 
 by the negative edge of the delayed TV horizontal sync pulse and is started 
 again by the positive edge of the delayed TV horizontal sync pulse in order 
 to maintt! . Clearly, it is very important to adjust the clod 
 
 fre<; :h that the delayed TV horizontal sync pulse occur after the gen- 
 eration of the last C/W clock signal of the R/M/W mode but prior to generating 
 the next R/R clock signal. See Figure ^. 
 
 The logic to video converter circuit is shown in Figure 11. T, and 
 T represent the drivers of a dual peripheral positive-AND driver, the SN75^1P, 
 and T, is a Si low power switching transistor. D is a Ge switching diode 
 and D„ is a Si switching diode. 
 
 When 
 
 T, and T are off (i.e. the binary video signal is 1), the base 
 
 voltage of T , V , is equal to the forward voltage drop of D and D at about 
 
 36mA, and V, = 1.4V. The base-emitter voltage drop of T^ is .6V and V = .&V. 
 ' b 3 out 
 
 When T is on V, = .3V and V = --3V. When T is off but T n is on, 
 2 b out 2 1 
 
 V = .6V and V = OV. For binary video, the blanking and the video signal 
 
 zero level can be the same. 
 
 3.2 Rotation and Reflection Operations 
 
 The rotation and the reflection operations are done by using 1, 2 or 
 3 of the following 3 operations; 
 
 1. interchanging the 8 x bits with 8 y bits 
 
 2. complementing the 8 x bits 
 and 3- complementing the 8 y bits. 
 
29 
 
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 o 
 
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 ^ 
 
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 o 
 
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30 
 
 The logical circuits are very simple. 1 set of 16 D flip-flops with 
 a complement output, Q, and two sets of 16 2-wide 2-input and-or-inverter gates 
 are used. See Figure 12. 
 3.3 Shrinking Operation 
 
 Shrinking a picture in the x direction is done by shifting the 8 bits 
 of the x data 1 or 2 bits to the right (thus losing the low order bits) and 
 adding operator chosen location information to the high order bit or bits of 
 the shifted data. Shrinking a picture in the y direction is done similarly. 
 
 The circuits used are two sets (16 each) of 2-wide, 2-input and-or- 
 inverter gates. See Figure 12, right two lines. 
 
 To keep the line width thin, every other or every fourth pair (x, y) 
 must be sampled (or processed). 
 
 As defined in the previous chapter, let (x . , y.) and (x . , , y. +1 ) 
 
 be successive input pairs to RASER (j a positive integer), x. and x. are 
 
 J 0+1 
 
 stored in the 8 bit registers at the top of Figure 13 and y . and y are 
 
 J J ■*- 
 
 stored in the 8 bit registers at the bottom of Figure 13. 
 
 The sample rate is controlled by the top counter of the two k bit 
 counters in Figure 13 . If the mode is 1/4 x 1/4 then 0011 is loaded into the 
 counter. Suppose the input pair is (x . , y.) when 0011 is loaded into the 
 
 J J 
 
 7 i 7 i 
 
 counter and x = 2 x. . -2 and y. - Z y. .-2 . The inverse of the load 
 
 J i _ ,D ' J i = 3>1 
 
 signal of the counter is called the controlled sample clock signal and 
 
 > 1 
 
 (x., y.) is transformed to the next stage with the controlled sample clock 
 J J 
 
 I T 
 
 (i.e. (x , y ) is the output of the sampler), where 
 J J 
 
 ' - 7 6 i 7 6 - i 
 
 x = x -2 + Z x '2 and y = y -2 1 + Z y '2 1 . 
 
 J J ' ' i=0 J ' J J '' i=0 J ' 
 
31 
 
 fc 
 
 fe^ 
 
 S-53^ 
 
 ~* / 121 
 
 —\ y -J, 
 
 B^ 
 
 Q»y — - 
 
 O^ - 
 
 3^ 
 
 Q*y 
 
 B^ 
 
 0^ 
 
 B^ 
 
 B^- 
 
 IB^ 
 
 Figure 12. Circuits for Picture Rotation, Reflection and Shrinking Operation 
 
32 
 
 Figure 13. Sample Rate Control Circuit 
 
33 
 
 This counter then counts down by 1 if d(j, j+l) = 1 where 
 d(j, j+l) = maxllx^ - x J+1 |, |y - y J+1 |). 
 
 If d(j, j+l) = d(j+l, j+2) «= d(j+2, j+3) = 1 then the counter reaches 
 the 000 state. With the next clock signal 0011 is reloaded into the counter 
 if d(j+3, j+k) =1, (x • m y-jj,) i- s output from the sampler and the counter 
 starts counting down again. 
 
 d(j+k, j+k+1) / always (k a positive integer) since if two succes- 
 sive input pairs are the same then the clock signals of the counter are inhibited 
 and the second pair is ignored. 
 
 If d(j+k, j+k+1 ) > 1 then 0011 is reloaded into the counter, 
 
 (x . , ., , y . , , ) is output from the sampler and the counter starts counting 
 x j+k+1 j+k+1 
 
 down again. 
 
 For the 1/2 x 1/2, l/2 x 1/1+ or l/k x 1/2 mode 0001 is loaded into 
 
 the counter instead of 0011. Otherwise, 000 is loaded into the counter and 
 
 every (x . , y.) is output from the sampler. 
 J J 
 
 3.4 Expansion Operation 
 
 Suppose that (x . , y.) and (x . n , y. .. ) are the successive input 
 J J J+l J+l 
 
 I I I I 
 
 pairs to RASER with d(j, j+l) = 1 and that (x . , y.) and (x . , y. ) are the 
 
 ii it 
 
 successive outputs from the sampler. Suppose also (x., y.) and (x . n . y. ,) 
 
 J J J+l J+l 
 
 are the points in the portion of the picture for which expansion is desired. 
 3.4.1 First Step of Expansion Operation 
 
 The sequence of operations is as follows : 
 
 it it 
 First, the difference betwen (x . , y.) and (x . .. y. , ) is computed. 
 
 J J J+l J+l 
 
 The logical circuits for this are shown in Figure Ik. 
 
3U 
 
 pG> ! 
 
 X" 
 
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 A A A 
 
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 o 
 
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 53 
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 Cm 
 
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35 
 Next, these differences are fed into the hard wired matrix pattern 
 generator shown in Figure 15 . If the expansion is 2 x 2, then 2 ones are 
 output from the pattern generator for each incoming (x , y ) pair from the 
 
 sampler. The second least significant bits of x. and y. determine in which 
 
 J J 
 
 2x2 submatrix these 2 ones fall. If the expansion is h x U, k one's are 
 generated for each input pair. The appropriate pattern is stored in the 
 memory . 
 3.U.2 Second Step of Expansion Operation (Format Conversion) 
 
 The format conversion is done as follows: First the word M(k, Z) 
 stored at address A (k, Z) is read out and stored in two 8 bit shift registers. 
 Next bits 0, h, 8 and 12 are loaded into the serial inputs of k different 
 shift registers. Then bits 1, 5, 9 and 13 are loaded into these registers, 
 and so on. At the end of the first half of the format conversion cycle the 
 first shift register contains bits 0, 1, 2 and 3 of M(k, Z) , bits 0, 1, 2 and 
 3 of M(k+1, Z), bits 0, 1, 2 and 3 of M(k+2, Z) and bits 0, 1, 2 and 3 of 
 
 M(k+3, Z) in bit positions 0, 1, 2, ... 15, respectively. The contents of 
 
 1 
 
 the first shift register is M (k, Z) . Similary, the contents of the second 
 
 shift register, M (k+1, Z) , are bits 1, 5, 9 and 13 of M(k, Z) , bits 1, 5, 9 
 and 13 of M(k+1, Z) , bits 1, 5, 9 and 13 of M(k+2, Z) and bits 1, 5, 9 and 
 13 of M(k+3, Z) in bit positions 0, 1, + ..., 15 respectively. Similary, 
 M (k+2, Z) and M (k+3, Z) are in the third and fourth shift registers. 
 
 The second half of the format conversion cycle starts with the writing 
 of M. (k, Z) back into the binary video memory at A (k, Z) where M(k, Z) was 
 stored originally. At the same time M (k+1, Z) , M (k+2, Z) and M (k+3, Z) are 
 transferred into the first, second and third shift registers respectively. 
 
 Then at the next clock signal M (k+1, Z) is written back into the memory at 
 
 • 1 1 
 
 A (k+1, Z) and M (k+2, Z) and M (k+3, Z) are transferred to the first and 
 
36 
 
 
 a^> 
 
 
 ,- - 
 
 : s 
 
 MS 
 
 2 ■» « 2 
 
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 a a a = s 
 
 * • * * * 
 
 92 
 
 A 
 
 A 
 
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 £wi& 
 
 a a ■» 
 
 0000 Q0QQ QQQ(3 fcBSQ 
 
 * — v« 
 
 F 
 
 EZ^ 
 
 A A A A 
 
 p 
 
 •H 
 
 CJ 
 
 •H 
 O 
 
 M 
 
 o 
 p 
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 y 
 
 QJ 
 C 
 
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 d 
 
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 0) 
 
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37 
 
 second shift registers respectively. Similarly for M (k+2, £) and M (k+3, &) • 
 
 i i t 
 
 At the end of the format conversion cycle M (k, £) , M (k+1, l) , M (k+2, Si) and 
 
 M (k+3, &) are stored in the binary video memory at A (k, &) , A (k+1, i) 
 
 a' (k+2, £) and A '(k+3, i) respectively where M(k, I) , M(K+1, i) , M(k+2, i) 
 
 and M(k+3, £) were stored originally. 
 
 The format conversion mode requires Ik format conversion cycles. 
 After the format conversion is completed the normal R/R cycle can be used for 
 the picture display. 
 
 The logical circuits of the format conversion system are shown in 
 Figure 16. The timing chart of one complete format conversion cycle is shown 
 in Figure 17. 
 
 This completes the description of all important operations and their 
 logical circuits. The remaining logical circuits will be described in the 
 appendix . 
 
38 
 
 • h 
 
 {J*' 
 
 , . ..... 
 
 • 
 
 *£>-!&**->-. 
 
 Figure 16. Format Conversion Circuit 
 
39 
 
U. CONCLUSION 
 
 RASER has shown the feasibility of the binary digital hardware scan 
 converter. RASER has one outstanding advantage over digital software scan 
 conversion, namely speed. RASER performs on-line conversion from a random 
 scan to a raster scan except in the expansion operation. Even in the expan- 
 »n operation the conversion is almost in real time. 
 
 RASER illustrates that specialized operations may frequently be done 
 faster and/or cheaper by using job oriented, special purpose computer or ter- 
 minal rather than a general purpose computer. 
 
 In RASER the expansion mode requires a two-step operation, and it is 
 almost real-time operation. If 6h bits (instead of 16 bits) can be read out 
 from the binary video memory in one cycle then the second step of the expan- 
 sion operation (format operation) can be eliminated. However, it is not eco- 
 nomical to read out 6k bits from a core memory in one cycle but with MOSRAM's 
 or a plated wire memory it is relatively easy and in the near future they 
 may be cheaper than a core memory of the same capacity. 
 
 The limitation on the maximum word length of a core memory prohibits 
 the construction of a digital hardware scan converter having the speed of 
 RASER and with gray levels. This is so even if the bits capacity of the core 
 memory is large enough. Again, with MOSRAM's or a plated wire memory it 
 can be accomplished. 
 
 RASER has distinct advantage over analog storage tube scan converters 
 in having less wear and tear, better reliability, better noise immunity, 
 better registration for writing or erasing and speed of erasing. Disadvantages 
 are lower resolution and lack of gray levels. 
 
1+1 
 
 LIST OF REFERENCES 
 
 1. Chu, Y. Digital Computer Design Fundamentals . McGraw-Hill Book Co., 
 New York, 1962. 
 
 2. Luxenberg, H. R., and Kuehn, R. L. Eds. Display System Engineering . 
 McGraw-Hill Book Co., New York, 1968. 
 
 3. Metzger, R. A. "Computer Generated Graphic Segments in a Raster Display", 
 AFIPS Conference Proceedings , Vol. $k, 1969, pp. 161-172. 
 
 k. Noll, A. M. "Scanned-Display Computer Graphics", Communications of ACM , 
 Vol. lU, No. 3- March I97I, pp. 143-150. 
 
 5. Rosefeld, A., and Pfaltz, J. L. "Distance Functions on Digital Pictures", 
 Pattern Recognition , Pergamon Press, Vol. 1, 1968, pp. 33-61. 
 
 6. Sherr, S. "Applications of Digital Television Displays to Command Control, 
 Proceedings of the SID , Vol. 11, No. 2, Second Quarter 1970, pp. 6I-7O. 
 
 7. Thoman, R. E. "A Computer-Generated Television Display System", 
 Proceedings, 3rd. National Symposium. Society for Information Display , 
 San Diego, California, February 1964, pp. I46-I67. 
 
k2 
 
 APPENDIX 
 
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 20 > K>o-i-j6>o-l 
 
 E/FC 3 
 
 -^ V 
 
 E/FC 10 
 
 ■> W 
 
 E/FC 13 
 
 -> X 
 
 Logic to Video Converter and Delayed Horizontal Sync Pulse Circuits 
 
50 
 
 ALL TRIM POTS ARE 6W 
 ALL RESISTORS ARE V 4 W 
 ALL DIODES ARE IN41S1 
 FUSE IS lA 
 
 1 CD4001E COSMOS 
 
 ] SN7400 
 
 1 SN7404 
 
 1 SN7408 
 
 2 SN7490 DECADE COUNTER 
 
 1 SN7492 DIVIDE- BY- TWELVE COUNTER 
 
 1 SN7493 DIVIDE- BY- SIXTEEN COUNTER 
 
 4 SN74123 
 
 TOTAL 12 IC'S 
 
51 
 
 VITA 
 
 Takehiko Katoh was born in Osaka, Japan on May 11, 19^1. In 
 March 1964 he received his B.S. in Instrumentation and Measurement Engineering 
 from Keio University, Tokyo, Japan. Mr. Katoh continued his education in 
 Electrical Engineering at the University of Illinois in September 1964. In 
 February 1966 he joined the Circuit and Hardware Systems Research Group of 
 the Department of Computer Science under Professor W. J. Poppelbaum. He has 
 been employed by the Department of Computer Science as a Research Assistant 
 in that group since February 1966. He received his M.S. in Electrical Engineer- 
 ing in June 1967 and since then has continued to work under Professor W. J. 
 Poppelbaum toward a Ph.D. degree. 
 
FormAEC-427 U.S. ATOMIC ENERGY COMMISSION 
 
 (6/68) 
 AECM 3201 
 
 UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR 
 DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT 
 
 C S»» Instruction! on Rrvrm SM» I 
 
 1. AEC REPORT NO. 
 
 coo 1U69-0209 
 
 2. TITLE 
 
 RASER: RANDOM TO SERIAL CONVERTER 
 
 3. TYPE OF DOCUMENT (Check one): 
 
 £3 a. Scientific and technical report 
 
 O b. Conference paper not to be published in a journal: 
 
 Title of conference 
 
 Date of conference 
 
 Exact location of conference. 
 
 Sponsoring organization 
 
 □ c. Other (Specify) 
 
 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): 
 
 F1 a. AEC's normal announcement and distribution procedure* may be followed. 
 
 ~2 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. 
 ~2 c. Make no announcement or distribution. 
 
 5. REASON FOR RECOMMENDED RESTRICTIONS: 
 
 6. SUBMITTED BY: NAME AND POSITION (Please print or type) 
 
 Takehiko Katoh 
 Research Assistant 
 
 Organization 
 
 Department of Computer Science 
 
 University of Illinois 
 
 Urbana, I llinoi s 6lfi01 
 
 Signature f 
 
 Date 
 
 June, 1972 
 
 FOR AEC USE ONLY 
 
 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION 
 RECOMMENDATION: 
 
 8. PATENT CLEARANCE: 
 
 I I a. AEC patent clearance has been granted by responsible AEC patent group. 
 I I b. Report has been sent to responsible AEC patent group for clearance. 
 I I c. Patent clearance not required. 
 
i. Title and Subtitle 
 
 BIBLIOGRAPHIC DATA 
 SHEET 
 
 1. Report No. 
 
 UIUCDCS-R-72-515 
 
 RASER: RANDOM TO SERIAL CONVERTER 
 
 3. Recipient's Accession No. 
 5- Report Date 
 
 June, 1972 
 
 6. 
 
 J. Author(s) 
 
 Takehiko Katoh 
 
 8- Performing Organization Rept. 
 No. 
 
 |. Performing Organization Name and Address 
 
 Department of Computer Science 
 University of Illinois 
 .Urbana, Illinois 61801 
 
 10. Project/Task/Work Unit No. 
 
 US AEC AT (11-1) 1U69 
 
 11. Contract /Grant No. 
 
 US AEC AT (11-1) 1U69 
 
 12. Sponsoring Organization Name and Address 
 
 US AEC Chicago Operations Office 
 98OO South Cass Avenue 
 Argonne, Illinois 60^39 
 
 13. Type of Report & Period 
 Covered 
 
 14. 
 
 15. Supplementary Notes 
 
 It. Abstracts 
 
 RASER (RAndom to SERial Converter) is an on-line binary scan converter, 
 designed to convert pictorial information from the computer output form 
 (RAndom) to a raster format (SERial) suitable for a TV display. RASER 
 also performs picture rotation, shrinking or expansion along with the 
 scan conversion. 
 
 17. Key Words and Document Analysis. 17o. Descriptors 
 
 Scan converter 
 
 Raster format 
 
 Random to serial converter 
 
 17b. Identifiers/Open-Ended Terms 
 
 17c. COSATI Field/Group 
 
 II. Availability Statement 
 
 unlimited distribution 
 
 19. Security Class (This 
 Report) 
 
 UNCLASSIFIED 
 
 20. Security Class (This 
 Page 
 
 UNCLASSIFIED 
 
 21. No. of Pages 
 
 58 
 
 22. Price 
 
 c ORM NTIS-3S (10-70) 
 
 USCOMM-DC 40329-P71 
 
SEP 21 
 
 1972 
 

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