■HWftlltTtffnnf m Sffll Jl IHSBlf UH SHHS r IbHI mBM nageB BflflB rafflm HHHffll mMMBUMM MM Hoi in ri B H is Hfl I33S8KS H I BH n ralfflHHl mMirannfinii HiMT HQHJSwSw H H Hs 38881 MflflBjf Hi fflffl ■Hi H iff H H I win nana ■Hi H m HHBIfii ExRHRTKnflRf Bira Mi8llfimal»n4ufllfl mm jjtn&fijiftj Bat RfixlHul ■ HilHBl tHBWWlnalWHniimi HHB99j|||mBUM|U HHHmNnw Hrawsn hehhki ■■p LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 ho.5U-5l& cop- 2 cop -^ S /u-cL^C^I UIUCDCS-R-72-512 coo 1U69-0204 OUTLINING AND SHADING GENERATION FOR A COLOR TELEVISION DISPLAY by DONAID FARNESS HANSON June, 1972 JH£ yiR&HX Of THE JUL 5 1972 .UNIVERSITY OF il_LlNO:-3 AT tfr -".OH'VPA.'GN UIUCDCS-R-72-512 OUTLINING AND SHADING GENERATION FOR A COLOR TELEVISION DISPLAY by DONALD FARNESS HANSON June, 1972 Department of Computer Science University of Illinois Urbana, Illinois 61801 This work was supported in part by Contract No. AEC AT(ll-l) lk69 and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering, June, 1972. Digitized by the Internet Archive in 2013 http://archive.org/details/outliningshading512hans Ill ACKNOWLEDGMENT The author would like to express his appreciation to Prof. W. J. Poppelbaum for making him a member of his Hardware Research Group and for his continued patience and support, to Prof. W. J. Kubitz for suggesting the project and for his guidance and suggestions, and to members of the Hardware Research Group for their discussions and suggestions. Credit should be given to Prof. Kubitz for implementing the Auto Erase and Brightness functions reported here for the first time and to A. F. Irwin for light pen modifications and for the Sync Converter Delay Circuit design. A special word of thanks goes to the members of the Printed Circuit and Drafting Departments, headed by F. P. Serio and M. C. Goebel, and to B. E. Bunting for typing the thesis. G. E. Fiscus and S. J. McDowell designed and W. E. Marlatt etched all of the printed circuit boards used here. All of the drawings presented in this thesis were done by R. J. Kimbrell and L. E. Hanson. R. M. Rivera helped in making the mechanical parts of the project. A final thank you goes to D. L. Reed and R. E. Potter for doing the printing. IV TABLE OF CONTENTS Page I. INTRODUCTION 1 II. THE DESIGN PHILOSOPHY FOR THE ATC - MARK II 6 A. Fundamentals of the ATC Video and Synchronizing Signals . . 6 1. The Monitor 6 2. The Disc 6 3. The Camera 7 B. A Discussion of the Improvements Incorporated in the ATC - Mark II 7 1. The Bleeding Problem 7 . a. A Discussion of Possible Solutions 7 b. A Discussion of the Camera Problem 9 c. The Delay Line Scheme 12 d. The Implementation 13 e. Extension to More General Scenes 15 f. Double Line Correction 15 2. The Vertical Stripe Problem 19 3. Shades of Gray Capability 19 a. The Disc 19 b. The Implementation 21 III. THE CIRCUITRY FOR THE ATC - MARK II 22 A. Drawing Conventions "... 22 B. Mechanical Assembly and Block Diagrams 2h 1. The Sync Converter Delay Circuit 2k 2. The Control Panel and Display Console Junction Box . . 27 3. The Filter Card 32 h. The Range and Width Card 32 5. Cable Details 32 6. The Main Console Junction Box 32 7. The Card Racks (Video and Control) 37 C . The Outlining Circuitry .•...: 37 1. The Delay One-Shot and Switch Shifters kk 2. The Video Distribution Amplifier (VDA) (11+69-531) • . ^h 3. The Ultrasonic Delay Line k^ h. The + and - 12 Volt Power Supply 50 5. The Selection Switch Card (1^69-528) 50 6. The Synchronous Chopper 5^ 7. The LHP, LVD Distribution Buffer 5^ 8. The Logical Blanking Circuit (1469-555) 5^ 9. The Vertical Differentiator (1469-5^5) and Logic (ll+69-5 1 +6) . . 5^ Page 10. The Horizontal RC Filter Differentiator (1^69-^7^) . . 6l 11. The Horizontal Delay Line Differentiator (1469-536) and Logic (1469-537) 6l 12. The Video Gate (1469-554) with L/V Converter 66 13. The One Frame Gate 69 D. The Shading Circuitry 69 1. The Preview Color Area Circuit (1469-555) 71 2. The Modulator ( 1469- 5 %) • • • 71 3. The Modified Disc Read Amplifier 74 4. The Demodulator (1469-373) . . 74 5. The Video Adder (1469-180B) 78 IV. THE RESULTS 8l LIST OF REFERENCES 85 APPENDICES 87 A. The Delay Line Differentiation Scheme 87 1. The Delay Line [19], [21], [22], [23], [24] 87 2. The Model for Analysis 88 3. The Impulse Response [25], [26], [28], [29] 88 4. The Circuit . 89 5. Corrected Difference 91 6. The Region of Approximation 92 7. Noise Considerations [20], [29] 9k B. The One Frame Gate Design 96 C. Card Rack Lists 99 1. Card Rack A 99 2. Card Rack B 100 3. Card Rack C 101 D. Photographs of the Outlining Scheme 102 E. Power Supply Buss Bars 108 F. Photograph Displaying the Coloring Capability 109 VI LIST OF TABLES Table Page 1. The Switch Card Positions 1+2 2. Three-Position Switch Positions k3 Vll LIST OF FIGURES Figure Page 1. The Automatic Tricolor Cartograph - Mark II (ATC - Mark II) 2 2. Line Drawings k 3. Typical Video Waveforms 8 k. Special Case Video Waveforms 10 5. Sample Differentiations Ik 6. Automatic Outlining (Vertical Components Only) 16 7. Second Derivative Scheme 17 8. Result of Correction Network for Crossed Lines 18 9. Disc Response to a Ramp 20 10. Mechanical Assembly 25 11. System Block Diagram 26 12. Sync Converter Delay Circuit . 28 13. Mechanical Assembly of Control Switches 29 Ik. Control Panel Schematic 30 15. Display Console Junction Box 31 16. Switch Filter Card (1U69-I73) 33 17. Range and Width Card (1U69-551) 3^ 18. Cable Details 35 19. Main Console Junction Box 36 20. Video and Control Logic 38 21. Coloring Logic 39 22. Outlining Circuitry 1^0 Vlll Figure Page 23. Delay One-Shot and Switch Shifters k5 2k. Video Distribution Amplifier k6 25. Ultrasonic Delay Line ^8 26. Modified Ultrasonic Delay Line U9 27. + and - 12 Volt Power Supply 51 28. Positive Overvoltage Protector 52 29. Switch Card 53 30. Synchronous Chopper 55 31. LHD, LVD Distribution Buffer 56 32. Logical Blanking Circuit 57 33. Vertical Differentiator Circuit 58 3k. Sample Difference Signal 60 35 • Horizontal RC Filter Differentiator 62 36. Sample RC Filter Differentiator Input /Output Voltages . . 63 37 • Horizontal Delay Line Differentiator and Logic 6k 38. Sample Horizontal Delay Line Differentiator Input /Output Voltages 67 39- Video Gate with L/V Converter 68 kO. One Frame Gate 70 kl. Preview Color Area Circuit 72 k2. The Modulator (A, B, C) and L/V Converter (D) 73 ^3. Modified Disc Amplifier 75 kk. The Demodulator 76 U5. Demodulator Waveforms 79 k6. Video Adder 80 IX Figure . Page 1+7 . Disc Problems 82 48. Delay Line Circuit 90 -ia)2T 49. ioo Compared with 1-e " 93 50. One Frame Gate Design Diagrams 97 51. Performance for a Line Drawing 103 52. Performance for a Solid Area 10 4 53 • Double Line Correction 105 54. The ID for a Photograph 107 55. Photograph of Sample Artwork 109 ■ 7 I . INTRODUCTION The work described here is the second version of the Automatic Tricolor Cartograph (ATC). Phase one of the project was completed in 1968. At that time it was decided that certain improvements could and should be made on the machine. These improvements were (a) to alleviate a color bleeding problem, (b) to remove a moire pattern that plagued the display, and (c) to add shades of gray capability. The solution of these problems is the subject of this work. A brief description of the original system will be included here, but for a complete discussion of Phase I, the reader should read the thesis "A Tricolor Cartograph" [1]. The machine as described in [1] will be referred to as the ATC - Mark I. The additions and changes described here were made on the ATC - Mark I. The machine as described in this report will be referred to as the ATC - Mark II. A photograph of the ATC - Mark II is shown in Figure 1. In general terms, the ATC - Mark I performed the same functions as the ATC - Mark II now does. In general terms, then, the machine will be referred to simply as the ATC. The ATC is a color graphics display terminal capable of "drawing" and displaying color graphical information. The operator is able to draw an outline on the display screen and fill it in with color. The machine uses hard-wired algorithms for achieving this end; it is entirely self -enclosed and no digital computer hookups are needed. Figure 1. The Automatic Tricolor Cartograph - Mark II (ATC - Mark II ) The basic components of the ATC are (1) an analog disc, (2) a switch control panel, (3) a light pen, (k) a color television monitor, and (5) a hard-wired hybrid control. The analog disc is the memory for the whole system. It has five channels, four of which may be written upon or erased at will. Of these four channels, one is used to record outline information, and three are used to record color information. All four of these channels are continuously "played back" on the monitor. The sync information is permanently recorded upon the fifth track. The operator interacts with the system using the switch control panel and the light pen. Functional interaction is accomplished using the switch panel. Interaction with the monitor is achieved using the light pen. In using the ATC, the operator first sets the switch panel to the "DRAW OUTLINE" mode. Pointing the light pen at the monitor, a photodiode inside the pen picks up light from the tube face. When the scanned beam moves in front of the pen, the photodiode amplifier responds with a large voltage pulse which is sent to the outline track on the video disc and is recorded as a point. As the light pen is moved around on the face of the monitor a line drawing results. This line drawing L [see Figure 2(a)] can be arbitrary, and, in general, can be broken up into subsets C of open or closed regions whose boundaries may be shared but whose "areas" are not criss-crossed with any other lines. The boundary of each C is here called the "outline" . Next, the operator sets the pen to the "COLOR" mode and (a) Line Drawing L Broken into Regions C with Outline n n Pen Location ^ Colored Area (b) An Open Line Drawing that Will Be Colored for Pen Location as Shown Figure 2. Line Drawings 5 the color selector switches to the desired color, "RED", "GREEN", "BLUE", or any mixture of these. He then places the pen on the screen somewhere inside of the outline , and the coloring logic automatically generates a waveform that corresponds to the inside of the outline that he has indicated. This n waveform is then sent to the disc where it is chopped and written upon those video disc channels corresponding to the selected colors. This signal is then read and sent to the monitor. If the outline is closed, then the entire n ' area bounded by the outline may be filled in. If, however, the "outline" is open, the coloring logic decides if enough information is known to "fill it in" [see Figure 2(b)]. After coloring, new outlines may be drawn and colored in. In this way, color may be added to already present color. Selected automatic erasure and point by point writing and erasure are also possible in addition to the automatic coloring described above. For a detailed discussion of the ATC - Mark I, see [1]. 6 II. THE DESIGN PHILOSOPHY FOR THE ATC - MARK II Before presenting a discussion of the problems with the ATC - Mark I and the design philosophy for the ATC - Mark II, a discussion of the ATC television system will be given. A. Fundamentals of the ATC Video and Synchronizing Signals A very brief summary of the ATC video and synchronizing signals will be given here. References [2], [3] and [h] deal with standard television in much more detail. 1. The Monitor In the Tricolor Cartograph (ATC) as with most American television systems, a complete picture, called a frame, consists of 525 horizontally scanned lines. Each frame consists of two fields. An odd numbered line belongs to the odd field, and an even numbered line belongs to the even field. Each field scans the entire height of the monitor in such a manner that a scan line from the odd field is interlaced between two from the even. In this way, visible flicker due to phosphor decay rates is avoided. One line is scanned in about 63 • 5 usee, one field in about 16 2/3 msec, and one frame in about 33 1/3 msec. At these rates, 30 frames are scanned per second which is fast enough to give the illusion of smooth move' ment. It is worthwhile to note that adjacent lines appearing on the CRT face are 16 2/3 msec, apart in time, whereas every other line is just 63. 5 M-' : apart . 2. The Disc The various components of the ATC are synchronized using Horizonta Drive (HD) and Vertical Drive (VD) pulses that are derived from a sync signa 7 recorded on a channel of a video disc that turns once per frame. These pulses initiate scan lines in both the monitor and the camera so that a point on the vidicon image plane is scanned simultaneously with the corresponding point on the monitor. A HD pulse occurs once per line, and a VD pulse occurs once per field. The logical equivalent of HD is LHD and of VD is LVD. 3. The Camera The output of the camera, called the video signal, is a dynamically scanned representation of a two-dimensional space. Typical video signal voltage waveforms are shown in Figure 3« The blanked portion insures that the retrace cannot be seen during scanning. The sync signal is of very little importance here because the monitor and the camera are synchronized to the disc. B. A Discussion of the Improvements Incorporated in the ATC - Mark II At the end of Phase I of the project, the machine possessed three undesir- able qualities: (a) bleeding of color from one outline to another, (b) vertical stripes in the colored area, and (c) no shades of gray capability. 1. The Bleeding Problem When the operator is drawing an outline, he may move the pen by more than one line in a frame's time, thereby leaving gaps. In the case of nested outlines, should a point on an outer outline happen to fall on the same scan line as a gap in the inner outline, the color will "bleed" outside of the inner outline. This effect is discussed in detail in Reference [1]. a. A Discussion of Possible Solutions Several possibilities exist for solving the bleeding problem. Solutions to this problem that seem reasonable at first become unduly cumbersome 8 blanking — H sync-** fr- «5 ^sec one line « 63.5 ^s. blanking -H h- «1.3ms.|^ one frame « 33.3 msec. — H sync-Hh- h— one field— H « 0.6 msec. » 16. 6 msec. Figure 3. Typical Video Waveforms 9 after careful thought. One solution would be to develop some sort of gap- filling algorithm. The problem with this, however, is deciding how to define a gap, in view of the fact that adjacent points on the display are sometimes one field apart. Another solution would be to use a television camera to input outlines instead of the light pen. The camera's video, then, need only be con- verted to logic. For a suitable video to logic converter, gaps would not appear in the outline. This scheme is the one used here. Camera problems are discussed in the next section. b. A Discussion of the Camera Problem In vidicon television cameras, the video signal is curved by a large amount for low light levels (ordinary room light). This is due to a combination of aperture, deflection and focusing effects. At normal room light levels, the video exhibits a decrease in sensitivity from the center to the edge of the line of typically 20%. The camera's automatic gain control emphasizes the curvature by giving the output a higher gain for dark scenes than for well-lit scenes. References [5], [6], and [7] discuss this problem of curvature. Although this variation in curvature is not noticeable on the monitor, it is very noticeable on an oscilloscope display of the video wave- form as is shown in Figure h. The voltage waveform for one line of video is shown in the top photo and for one frame of video in the bottom photo in each (a) and (b). The waveforms in Figure h(a) result from a simple white outline drawn on a black background while those in Figure ^(b) are the result of a simple black outline drawn on a white background. In each case, the variation in voltage across a line is almost as large as the amplitude of the outline 10 Figure h. Special Case Video Waveforms (a) Waveforms of a White Outline on a Black Background 11 Figure k. Special Case Video Waveforms (b) Waveforms of a Black Outline on a White Background 12 pulses. As might be expected, we see the voltage over a field varies in a very similar manner to that over the line, making any sort of simple threshold detection impractical. We can see that for the black-on-white case, one has to extract usable information from negative- going pulses while for the white- on-black case, one has to extract information from positive -going pulses, c. The Delay Line Scheme A paper [8] was located in which an outlining scheme is devel- oped by using the superposition of two differentiations. Ordinary differentia tion of the video had been labeled as undesirable because of the fact that all horizontal lines are differentiated out. This paper, however, presents a way of getting around this problem. The scheme involves the superposition of a vertical differentiation by delay line and an ordinary differentiation. The delay line used in the paper is an ultrasonic delay line with a bandwidth of 1.5 MHz and a delay time of 63-5 usee (exactly one horizontal line). In order' to form the "vertical derivative", one must just subtract the delayed video from the real time video. The result of this so-called vertical differentia- tion is a horizontal line while the result of an ordinary or "horizontal" derivative is a vertical line appearing on the screen. The two, superimposed, form the "total" derivative or the all-direction outline. As discussed in Section II. A. 1, two adjacent (in the time sense horizontal line waveforms appear on the monitor's CRT face with another line from the other field in between them. A result of the delay being one hori- zontal line is that the differentiation is a field-by-field differentiation and not a frame -by- frame differentiation. Any horizontal information appearin in the television picture is actually vertically differentiated twice — once 13 for each field. The resultant horizontal component of the outline is twice as thick as it would be, had it been differentiated frame -by- frame. d. The Implementation It was not known whether the delay line scheme could be applied to the ATC, because of drift in the disc's speed. The time between HD timing pulses varies, causing the video's line period to change from line to line. A series of experiments were run and the necessary data collected to determine the average line length and standard deviation. The average line length was found to be 63-^918^ |-isec with a standard deviation of U.19 nanoseconds. Ultra- sonic delay lines available on the market typically specified the delay +10 nsec. and talks with suppliers indicated that the delay line scheme would work for the ATC - Mark II. The curvature of the video is no longer a problem due to the fact that this scheme depends only on the difference of two video waveforms with approximately the same shape of curve. Also, this technique avoids any sort of video flattening scheme while preserving the horizontal outline infor- mation. The delay line used was purchased from Corning Glass Company. The 3db bandwidth of the Corning delay line is 8 MHz down to k Hz. This is actually somewhat better than needed because the 3db bandwidth of the camera is only 7 MHz. Two different horizontal or ordinary differentiators were built. One, an RC filter differentiator was built experimentally so as to provide a good outline on the monitor when a line drawing is being scanned. The other was built using an 80 nsec delay line. In comparing the two, it is found that they provide essentially the same information. The system has been designed so that either one or the other may be selected. A sample horizontal delay line differentiation is shown in Figure 5(a). Here the top 11+ (a) Sample Horizontal Delay Line Differentiation (b) Sample Vertical Differentiation Figure 5. Sample Differentiations 15 waveform is video and the bottom is its delay line derivative. Figure 5(b) shows a sample vertical derivative. The top waveform is the delayed video, the middle waveform is the real-time video, and the bottom waveform is its "derivative". Photographs of the outlining scheme are discussed in Appendix D. e. Extension to More General Scenes The differentiation scheme allows for taking "outlines" of more complex scenes than just line drawings. This may be desirable in order to "color in" a solid object placed in front of the camera. When a general scene is viewed, the logical Derivative (LD) is extremely scene- content dependent. By this we mean that scenes composed of solid objects require a "double -sided" threshold placed on the derivative, while scenes composed of lines require a "single-sided" threshold. This is illustrated in Figure 6. A "single-sided" threshold detects either the plus or the minus side of the signal while a "double-sided" threshold detects both sides. If the scene viewed is composed exclusively of either solid areas or line drawings, then switches may be set to take the double- or single-sided thres- hold as desired. For scenes composed of both solid areas and line drawings, a scheme to remove double outlines from the line drawing parts, while not perturbing the solid area outlines, needed to be and was developed. f . Double Line Correction Several types of correction were tried. One idea was to OR the double-sided threshold of the first derivative with the double-sided thres- hold of the second derivative. This scheme is shown in Figure 7(a). Although this seems to be a sound technique theoretically, experiment showed that the double lines remained around the slanty part of the line while disappearing from the more vertical part, as shown in Figure 7(b). The next correction 16 1 CORRESPONDING VIDEO r DIFFERENTIATED VIDEO t T T "SINGLE -SIDED" THRESHOLD RESULT DOUBLE -SIDED THRESHOLD JIL_ RESULT Figure 6. Automatic Outlining (Vertical Components Only) © © 7l_j r \ 17 VIDEO ^ZZ* (VIDEO) © JL Jl "DOUBLE SIDED" THRESHOLD © * (VIDEO) © DOUBLE SIDED" THRESHOLD © n n n Jl (D or (D * D n n © (a) Sample Waveforms ONESHOTTED (§) (b) Result Figure 7. Second Derivative Scheme 18 technique tried involved the use of one-shots. A one-shot was triggered wit every input pulse that hit it while it wasn't high. The output pulse was used to overlap the gap between the two threshoMs. The resultant wide pulses were then one-shotted. This scheme is the one used here. It should be pointed out that the main advantage of this scheme is that it is adjust- able, whereas the second derivative scheme wasn't. The drawbacks of using the one-shot technique are several. The first is that, for crossed lines or cusps, outline information is omittet as illustrated in Figure 8. Resolution is also affected somewhat for scenes Figure 8. Result of Correction Network for Crossed Lines with close lines. In this case, if the line spacing varies in the vertical direction, lines that should appear as lines will appear dashed. This occurs if the one-shot cycle is completed between the two thresholds. The one-shot will trigger on the negative threshold instead of the positive, thereby giving the resultant output a zig-zag effect as well as a dashed effect [see Figure 53(b)]. Another drawback is that because the one-shot triggers with any length of input pulse, unnoticeable noise pulses are effe< tively "multiplied" to become very noticeable. Various possibilities exist for forming the vertical derivative correction. None were tried, however, because of monetary considerations. The vertical derivative is left uncor- rected here. Appendix D discusses a photograph of a corrected outline whicl illustrates these drawbacks. 19 2. The Vertical Stripe Problem In the ATC, the COLOR signal is chopped at 3 MHz in one phase dur- ing an odd field and 180 out of the odd- field phase during an even field. In the ATC - Mark I, the Disc Read Amplifiers were operated in the Class B mode so that the outputs took the form of half wave rectified sine waves. The superposition of the two fields then produced areas of color with vertical stripes in them corresponding to the nulls or peaks of virtual full wave rectified sine waves. It was decided to use a demodulator to detect when a sine wave is being read. The Disc Read Amplifiers were redesigned to operate in the Class A mode to provide the demodulators with a suitable signal. The disc speed variations mentioned before and phasing problems require that the reference or carrier frequency be derived from the signal itself. The demodulator used is amplitude sensitive so as to provide for shades of gray capability. 3- Shades of Gray Capability The work leading to Mark I of the ATC was concerned primarily with the development of a coloring algorithm, and so, shades of gray capability was not included. It was felt that shades of gray capability would sizably increase the scope of the machine and was, therefore, included as a goal in the ATC - Mark II. a. The Disc It was not known if the disc was shades of gray compatible. To prove that it was, a ramp generator was synchronized to the HD of the disc, and the ramp was then gated into the write input of a disc channel. The output of that channel's Disc Read Amplifier was then viewed on an oscilloscope and a photograph of this scope trace is shown in Figure 9. This experiment proved that the disc was shades of gray compatible. The range of input signals for outputs in the linear range is from about 0.7 volt to about 1.0 volt 20 Figure 9- Disc Response to a Ramp Sweep ~ 1 Horizontal Line 21 b. The Implementation The implementation is very straightforward. Control of shading is by means of three potentiometers located on the Control Panel. The opera- tor positions the potentiometers according to a "PREVIEW COLOR" area viewed on the CRT face. The amplitude of the COLOR signal is then clipped to a value corresponding to the potentiometer positions and channeled into the disc's write inputs. A chopper in the disc unit chops this signal before it is written on the disc's surface. 22 III. THE CIRCUITRY FOR THE ATC - MARK II With a few exceptions, the circuitry described here does not appea in Reference [1], "A Tricolor Cartograph". The schematic drawing of the col ing logic is included in order to give a better insight into the overall design of the machine. Any modified circuitry is included here, but cir- cuitry that hasn't been changed remains as described in [1]. A. Drawing Conventions Before embarking on the circuitry descriptions, it will be helpful to the reader to list the drawing conventions. First, the great majority of the circuitry described here is assembled on 22 pin printed circuit (PC) cards. Input /output pins on these cards are lettered on the component side of the board and numbered on the noncomponent side as follows : Component side ABCDEFHJKLMNPES TUVWXYZ [A through Z with G, I, and Q omitted] Noncomponent side 1 2 3 h 5 6 7 8 9 10 11 12 13 li+ 15 16 17 18 19 20 21 22 [1 through 22] In the card rack, there are three rows of cards, each row holding 28 cards. The top row is labelled A, the second B, and the third C. The Ultra- sonic Delay Line is mounted horizontally below card rack C and is labelled . card Dl. The block diagram of the card shown below means that the input is pin 5, the output is pin C, and the card is the tenth card in the bottom row. CIO c 23 A generalized NAM) is labelled in much the same way, as is shown below. Here the inputs are PC card pins 7 and 8, the output is pin 6, and the card is the twelfth card in the top row. In this case, it is important not to confuse the card pin numbers with the integrated circuit (IC) pin numbers. The detailed card drawings label card pins as shown in the drawing below. c> 3> 7> D CL Q *2 >D In this drawing, pins C, 3> and 7 represent PC card inputs, while 2 and D represent PC card outputs. The IC pin numbers are the numbers located just outside of the dotted square. All common points and power supply voltages are indicated by square boxes such as shown below. LVD ra 2k Original printed circuit layouts are labelled with the PC card number which always starts with ±U69, the contract number. A logical zero is -5 volts, and a logical 1 is ground. These are denoted as shown below. © © B. Mechanical Assembly and Block Diagrams The mechanical assembly of the ATC - Mark II is shown in Figure 10. The light pen, the shading potentiometers, and the control switches allow for operator interaction. A bundle of cables connects the Display Console to the Main Console. An F1.5, 22.5 to 90 n^ 1 zoom lens on the camera allows for chang ing the field of view without moving the camera. The block diagram of the system is shown in Figure 11. The block diagram of the Main Console is shown in the left part of the drawing and that of the Display Console in the right. Nine cables connect the two consoles. It is helpful to refer back and forth between Figures 10 and 11 in order to relate a block to the location of the corresponding circuitry. Each block in Figure 11 is represented by one or more drawings in either the Kubitz thesis | or in this one. In reading the rest of this thesis, the reader should keep this block diagram in mind. 1. The Sync Converter Delay Circuit The camera, located on top of the Display Console, requires sine wave synchrhonization. A commerically available sync converter was purchased to make the HD - sine wave conversion. For some reason, however, the camera and the monitor didn't want to start scanning at the same time, so that the camera's blanking appeared in the middle of the screen. The circuit shown in 25 J8) O 0) c o o JO a. v> b tt^S O (/> C S c i i ,oo o p- ^^ Od i UJ u. 8s- P s 1 - 1 !^ + 3 T>2 °® ■© °® "® Jt»y3^cy hi* © "NJH6 1IVN] ■3*- ® «- *® B" * n,1 "(g) r N N33yOi*« R< — i •® ->£ 4^ 4 t Jl *& 3 ->^ A IS wit (3) a ® m 3 Y _ * ■»» © a k © © ® © -»- ii 8 5 i -> < i ® £ O * * 26 >- H < pj _l O q_ to 5 ° ~U T UJ o CO o CJ a. M CM -> a. 1 1 i BE UJ 8 < UJ OB U i 3 * Q. I 3 s o ^ Figure 11. System Block Diagram 27 Figure 12 was built, using the sync converter power supply, to delay HD by a time determined by the setting of potentiometer PI. Typical waveforms are shown below the circuit. 2. The Control Panel and Display Console Junction Box The operator interacts with the system with the light pen and by setting the switches and potentiometers shown in Figure 10. The mechanical assembly of the Control Switches is shown in Figure 13. Mechanical interlocks are used in some cases to make the switches mutually exclusive. Figure lU shows the schematic of the Control Panel. The "AUTO ERASE", "AUTO COLOR", "PREVIEW COLOR", "PREVIEW OUTLINE", "CLEAR OUTLINE" and "STORE OUTLINE" switches are new. The "AUTO ERASE", "AUTO COLOR" and "PREVIEW COLOR" switches are mutually exclusive, and allow the operator to automatically erase or color the inside of an outline or to adjust the shading potentiometers for a desired color (preview the color). The "PREVIEW OUTLINE", "CLEAR OUTLINE" and "STORE OUTLINE" switches are mutually exclusive except that the "CLEAR OUTLINE" and "STORE OUTLINE" switches do not stay in when pushed. The "PREVIEW OUTLINE" switch allows the operator to adjust the camera while looking at the outline on the CRT. The "STORE OUTLINE" switch pops the "PREVIEW OUTLINE" switch out and records one frame of outline information on the disc. The "CLEAR OUTLINE" button pops out the "PREVIEW OUTLINE" button without recording anything. In each case, the switch signal comes from Switch A. Switch B is used to light the light bulbs inside of the button. The switch and shading potentiometer signals then go to the Display Console Junction Box, shown in Figure 15, where they are processed before routing to the Main Console. 28 2 = ■o c O *> o - S i 4i O w O I Q §C5 ilB o E _ z F ■£ m -tC^ b 2 AA/— p Tvs/j I Hi- i? > ? I- O Jdb csj <• <0 K) z CM IO m o O OD • z CM 00 O i-i * o O ^ /s I Q X *o O I CJ csJ ~ ° ? f o o o (VI O 0) o > rsi a, w w > Oi O w O X O Figure 12. Sync Converter Delay Circuit 29 ? .8 ! S > s - a- © 8 = i2 ■ it I \ c 3 O 1 4 F . i 2 o u u z It o IS -J 3 o Ul (J 3 O It o < £ o U 1° _j= f o ■ o o ■1 1 7o 13 u fc o s a o o u It o s Ul o S o (9 O a fc o < X Ul Ho £ fc o — O 3 g 7o o _ «J s l£° _~ 1 I f ■ — * s _i (J u K O _l *1 2 § J! o • o u g 4i ■ S* o o u fc o g •i o (9 O Ul o St o gi o z * o u a. o ft o u 3 o o u JC o o _l O -I >> JC JC u o •o o c C o *> e « F « c e o c M CD 2 M P o u w O O u O 'c n XL .C * C c £ o U e o ■^ (/) -C «l * c »_ * u 2 c o c .2 O i en c o 2 3 3 O -K * ^ O U o u JC o < < a < u _J o o i a >> w O c O w e o _J o c c c C c CI «* o a> E o E o 3 E o 5 £ o •» 2 2 a. 2 CO 2 « JZ < o u LU o < 9 o u o o < < in < < < «T u. u_ f<- K N r<- h- k Figure 13. Mechanical Assembly of Control Switches H Si 51 ? *^ -«i>« Ipt k 1 I- JHf T°- S a. j«f *-H *i ^ ? ■Hj J «B° -^r at «t «B° -jo i^ ^ -c«- itf II *B° -»"- -Vf «B° -»o- -tf IS- *B° -*4 I- *5° f 3~ 5 IJT* i-- -S-- --■S 'ii: |gy 30 j i ». Mm Jiolf — M 0i * IS § 18 Z 18 § K HI Figure lU. Control Panel Schematic 31 *.I. ijt.- i^f^ g W OQ CujOO 2 D ,QO J*;i J«j» ;«ij£ Figure 15. Display Console Junction Box 32 3. The Filter Card The switch signals go through a shaping network before going on the Main Console Junction Box. Figure 16 shows the schematic of the Filter Card. The diode is one of the diodes shown above the Filter Card in Figure 1 and is not on the PC card. If the input is grounded, the output sits at about ground; otherwise, it sits at about -5.6 volts. These shaped signals go to the Control Logic via the Main Console Junction Box. 1+. The Range and Width Card The wires from the shading potentiometers go to the Range and Widtl Card, shown in Figure 17 and located on top of the Display Console Junctioa Box. This card, together with the shading potentiometers, forms voltage divider circuits. The voltage at the potentiometer wipers are sent to the modulation circuits via the Main Console Junction Box. The light pen circuit has not been changed and so is not included here. 5. Cable Details Cable details for the machine are shown in Figure 18. Cables tha aren't shown here are wired pin for pin. Closing the enable switch shown the detail for cable U8 allows the operator to use the pen for drawing out! or coloring and brightens the display screen so that the pen can provide £ clean signal to the level detection circuit in Figure 15 (also see Figure U The power supply for the switch light bulbs is located in the Display Cons Junction Box, as shown in Figure 15- 6. The Main Console Junction Box Except for the pen pulse signal, signals from the Display Console Junction Box pass through the Main Console Junction Box, shown in Figure 33 «N> i 220 -AAAr- 1.5K .47 -10 ■> OUT r A^ L _AiB i c J .-^.-o.RJ -5 I I B > C > D > B * 1 ■> 2 * 3 V > W> » 17 19 -10 NOTES : ^ DIODE NOT PART OF SWITCH FILTER CARD. SHOWN TO ILLUSTRATE COMPLETE CIRCUIT. 2. A, 22 ARE GROUND Figure 16. Switch Filter Card (11+69-173) TO IK SHADING COEFFICIENT POT > > > 5> 7> 6> E> J > H> B> D> C> r 3h ♦ 10 cw 2K P2 30 K MAX. COLOR X T 30pfd MIN. COLOR CW r- 2.7 K 200 PI > I 1/2A ->10 RED B >11 GREEN 12 BLUE 1/2A 15>-°- r \^-°- .47 a: z 5 47 + 10 Pin 1 is ground NOTE OUTPUT VOLTAGE RANGE 770V to 1.010V Figure 17. Range and Width Card (1*4-69-551) 35 2- ° a m h (VI ro •* E c a> oU. UJ «> O a> AAA ■-1 t\J K) 19 + UJ I /K /K /K /N /K /N /K ii 0D O Id m c -> » a. A A 2 2 — *> CD fc - ° O ~ o z $ o A A A A A •D _l Q. E 3 in 2 t. z a> o uj a. a> Q -Q O C_> I o uj c a. CM ft I 2 < u> o i AAA/KAAAAA 10 cvi |? Jo o AAA a. iJ /f^/T\AAAAA / 1 s> A .0- ' a. oe in t- AAAAAAAAAAAAAAAAAAAAAAAA Figure 18. Cable Details 36 Q S •- ot « s § ? » » ? 5 1* 1" s> Si> is o Oj 2 O Kg O IB I 12 > 18 > z < s . I < CL (/) 8° I- 5~ IO> IOC >■ •f & m o a :I \J ■ jjJt| «"|" a _i Z z a. tr (o >- «j a .o i ? 2 7 T ♦ T > > 3< > n o o <* uj «"H Figure 19. Main Console Junction Box 37 before proceeding on to the card racks. DC power enters the Main Console Junc- tion Box where it is routed to the Display Console Junction Box and the card racks . 7. The Card Racks (Video and Control) The block in the System Block Diagram, Figure 11, labeled Video and Control (card racks) has in turn been broken into three other block diagrams. The division has been done primarily by function. The central drawing, shown in Figure 20, is the "ATC Video and Control Logic" drawing. Appended to it are two other functional block diagrams, the "ATC Coloring Logic," and the "ATC Outlining Circuitry". These drawings are shown in Figures 21 and 22, respec- tively. Wiring cross references between drawings are indicated with circled numbers. The signals to and from the disc are routed through the coaxial con- nectors, and the control signals and DC power from the Main Console Junction Box are shown entering through connector J31 in Figure 20. The Coloring Logic has not been changed in the ATC - Mark II. For a complete explanation of this drawing, see Reference [1], It is included here for easy reference. A more complete discussion of the "ATC Video and Control Logic" drawing will be given with the discussion of the shading circuitry. C. The Outlining Circuitry The Outlining Circuitry described below is a new feature in the ATC - Mark II. The block diagram for the Outlining Circuitry is given in Figure 22. Inputs are Logical Vertical Drive (LVD), Logical Horizontal Drive (LHD), the video, Preview Outline (P0) and Store Outline (SO). P0 and SO are derived from switch positions on the front panel, the video is from the camera, and LHD and LVD are timing pulses from the disc. Outputs are an inverted gated LOGICAL DERIVATIVE (LD) signal (ID)* (GO), a signal representing a Preview 38 <=> © e> © ® & ® ® © ® ® P ' :i1lM#B#i44iwif B v « itr „ i* 10 IS IS 3? is is is; i? Figure 20. Video and Control Logic 39 9NIMVM0 3'301 10W1MOO (M* QMlA 31V NO liMnfl* 0MIOM04t3«)M» 01 b)iJK Figure 21. Coloring Logic m ko 8 = 8 Jl. ■ « II fl ►. • »u - n ■ a » II II IIMI rH IL Ss« = :* BSli !I!M< tip 1 =2 2iS 8f! £ I J H B a far 1 1 [ (Si Ifff « _i 3 bi Soli a ci 2 °* !| Sgii Ss 11 ® © © © © ©, 9NI«»yQ DHCP 10M1N03 ON* 030IA 31* NO SbMnnN 0NI0NO<(S3MM03 Oi H3J3M Figure 22. Outlining Circuitry 41 Color Area, a signal to preview the LD (the outline information) and a gated video signal. To see where the inputs and outputs come from or go to, the reader should refer to the corresponding numbers in Figure 20. The video signal goes to a Video Distribution Amplifier (VDA) which has provision for ten outputs. LHD is used to clamp the video to a reference level. One output from the VDA goes to the Ultrasonic Delay Line, the output of which goes to the Vertical Differentiator along with another VDA output. Clamping pulses are also used in the Vertical Differentiator. Other VDA out- puts go to the horizontal differentiators and the Video Gate. The output of the Vertical Differentiator goes to the Vertical Differentiator Logic along with chopping signals keyed to LHD, blanking keyed to LHD and LVD (LB) and selection signals from the Switch Card. The outputs of the horizontal differentiators go to the Horizontal Differentiator Logic along with Logical Blanking (LB) and selection signals from the Switch Card. Level shifters are used to shift switch signals coming from the Horizontal Delay Line Differentiator to logic levels suitable for selecting the RC Filter Differentiator outputs. The output of the Vertical Differentiator Logic is a Vertical Logical Derivative (VLD) and of the Horizontal Differentia- tor Logic is the Horizontal Logical Derivative (HLD). VLD and HID are ORed together selectively using Switch Card signals to form the LD. Table 1 gives the action for Switch Card switch positions and Table 2 gives the action for 3-position switch positions. If both HLD and VLD are disabled from forming the LD, the video is gated onto the screen. Otherwise, the LD can be either previewed (by push- ing the P0 button) or gated onto the disc (by pushing the SO button). The SO signal goes to a cne-frame gate where the gate outline (GO) signal is k2 ten Position HID RC Filter Differentiator (One-Shotted Output) 1 Delay Line Differentiator (Not One-Shotted) 1 RC Filter Differentiator (Not One-Shotted J Leading Edge Only- 1 1 Delay Line Differentiator (One-Shotted) and Double Line Corrected Switch Position VLD Vertical Differentiator (Not Chopped) 1 Vertical Differentiator Even/Odd Field Chopped 1 Vertical Differentiator Odd/Even Field Chopped 1 1 Vertical Differentiator Chopped Switch Position LD /Video Gated Video (Camera) 1 HID 1 VLD 1 1 HLD v VLD Table 1. The Switch Card Positions Position Vertical Differentiator Switch on Cl6 ACTION Horizontal Differentiator Switch on C22 ^3 Up Trailing Edge (Single-Sided Threshold) Center Both Edges (Double-Sided Threshold) Down Leading Edge (Single-Sided Threshold) Position ACTION Up Trailing Edge (Single-Sided Threshold) Center Both Edges (Double-Sided Threshold) Down Leading Edge (Single-Sided Threshold) Table 2. Three-Position Switch Positions Uk formed from LVD. (LD)"(GO) is then ORed with any light pen signals before! proceeding to the disc. A block that is not part of the Outlining CircuitB is also included in this block diagram. This is the block labelled PrevieJ Color Area. The circuit details and appropriate comments, where needed, are given below. The number after the card name is the number assigned to thai printed circuit card. 1. The Delay One-Shot and Switch Shifters The circuit diagrams for the Delay One- Shot and Switch Shifters ar shown in Figure 23. The one-shot is used to generate a delay signal f rom I LHD. This is necessary because there is a slight delay between the LHD puk and the video's sync interval. A delayed HD pulse is formed from this delaj signal to clamp the video in the Video Distribution Amplifier (VDA). The Switch Shifters are used in connection with the horizontal dif ferentiation circuits to convert a zero volt to +5 volt switching signal to a zero volt to -5 volt switch signal. 2. The Video Distribution Amplifier (VDA) (1469-531) The VDA is used to: (1) clamp the video at a DC level, (2) clip the sync from the video, and (3) provide up to 10 isolated outputs. The circuit diagram of the VDA is shown in Figure 2k. A synchronous clamp [9], synchronized to shortened LHD pulses (OSLHD), clamps the video at a clamp/clip level set by P2. The one-shot provides clamp pulses that are slightly narrower than the camera's horizontal sync. More detailed discus- sions of the synchronous clamp circuit are found in [9] and [h] . ^5 Id X CO X o CO ffi Q 03 UJ Q cr < o _l < CO cr UJ > /\ z ro m in i to ■-4 Z • o O 3 Z CD z o oz «J- — • I- • • z oi!2n Z UJ .. .. < z-^, z o o o 2 CO 66 AA A/\ £ z> h- jo •—a > a6 AA AA 8 x * 2 3 O o N c 0. Hi' Figure 23. Delay One-Shot and Switch Shifters 46 Figure 2h. Video Distribution Amplifier 47 Capacitor C_ is made small so that the diode clamping gate can easily charge it. A high input- impedance amplifier is used so as not to appreciably affect the charging and discharging of C„, thereby avoiding low frequency distortion. This amplifier, composed of ^>2, Q3 and Qj+, is a direct- coupled voltage feedback amplifier and is discussed in references [2], [10], [11], [12], [13], [Ik] and [15] as well as most electronics texts. It should be mentioned here that the voltage gain A of such a circuit is approx- imately (R_ + JL,)/R_; the input impedance is high ~150kft and the output hi r ' hj impedance is low. Variations of this basic feedback triple are used in other parts of this project. In the case at hand, the gain (R + R )/R is made to be almost ill r ili two so that the voltage divider between 68ft and the 75ft cable at the emitter of each buffer transistor (Q5 through Q,9) will keep the output signal amplitudes approximately equal to the input signal amplitude. Potentiometer P2 is set such that the sync portion of the video at the outputs is clipped off when the outputs are terminated in 75ft. PI is adjusted so that OSLHD is slightly shorter than the camera's horizontal sync. 3. The Ultrasonic Delay Line The Ultrasonic Delay Line was purchased from Coming Glass Company. Figure 25 shows the delay line circuit topology as it was when it arrived. One feature of this circuit is that it has automatic gain con- trol (AGC). This feature hampered the balanced operation of the Vertical Differentiator circuit. For this reason, the delay line circuit was modified; the modified circuit, without AGC, is shown in Figure 26. The 2kft potentiometer should be set so that the voltage reading at TP3 is about +6 volts. This was the average voltage at TP3 before modification. ii rz — v L h i • ti< \y & ' rUUIIJiJijU [—•Hi' JJ- C£i, 3 Jlr E ^ a^ J^L iHh + A. r Hi' \^~r -Hi' I* %/- n Hi- > 9 Is -.Hi' I HDhHi' O (M IS 5 jo' |P2 ii 48 Figure 25. Ultrasonic Delay Line h9 IB* SfoS a: Figure 26. Modified Ultrasonic Delay Line V 50 U. The + and - 12 Volt Power Supply A + 12 volt power supply with overvoltage protection was built to furnish the Ultrasonic Delay Line with power. The circuit is shown in Figure 27. A Silicon General 2501 regulator is used [16]. This regulator provides balanced positive and negative voltages with a single adjustment. The supply has been derived from the +25 volt supplies. Diodes Dl and D2 lower dissipation in the power transistors and in the integrated circuit. An overvoltage protector has been included on each supply to protect the < line from the 25 volt supplies should a power reference diode or power transistor short. An equivalent circuit [17] for the positive overvoltage l_L_Sl protector is shown in Figure 28(a). When v. is less than g— I the voltage across R 2 is less than V R , the reference voltage of the reft, diode, and the ideal diode is cut off. The output voltage v Q is zero in case. If v. is greater than \_ V R then superposition may be used t shown in Figures 28(b) and 28(c). In this case, the output voltage v q € e + e as shown in the Figure. When v q reaches about .5 volt, the SCR trigger, causing the fuse to blow. PI and P3 are set to trigger SCR1 anc SCR2 at +13.5 volts and -13-5 volts, respectively. P2 is set so that ead output reads about 12 volts . Before going on to discuss the Vertical Differentiator and Log: Selection Switch, Synchronous Chopper, Distribution Buffer and Logical I circuits will be explained. 5. The Selection Switch Card (lU69~528) The Selection Switch C a rd is shown in Figure 29. Open colled inverters are used in a feedback configuration to provide a contact boui switch signal. This circuit [18] is used in the D.C.S. Logic Laboratory modules . 51 CD CO LO i en t HH 10 u n hi HI' t-< & ~tt J o o o <£ III 5 O 9 & * ? * r : « ■ JS -• 5 ' = ! i I * «• a t, • a ^ « > O o » s 5 * o s * s s ° s * 2 <3 i i . ^ Q ° v - n n - ^ «i' m o o o a o a q ~ i < <- H" -Vi^ ^A— rr ° 2 * — % ^rr-^ "< 4" '^>-t >- I I I . CM O I l-^ 1 *- ®" r r m Figure 27. + and - 12 Volt Power Supply H' cr > o cr cr 52 |— AA/V" -4-aaa> — o -Wv- OJ Ct o Hi. - cr tc > o: + N N cr cr cr WV-4-AAA/ * cr :_4 a: Hi' s — + N v/i C <" -o C ' o CLTO o E (A — < < Figure 28. Positive Overvoltage Protector 1469-528 Switch Card 53 2.2K 2.2K 2 19 A.Z >- 22 > 1/2A A A 47 Note : A ju mpers Allow Positive or Negative Operation. 2. All Units SN7405N Figure 29- Switch Card 5h 6. The Synchronous Cho The Synchronous Chopper, shown in Figure 30, is used to chop thel Vertical Logical Derivative into a form suitable for writing on the video disc. Two one-shots are used in a feedback arrangement to provide oscilld If LHD is low, the feedback path is disabled. When LHD goes high, it trigg the first one -shot and Ql goes low. After a delay set by PI, Ql goes high? again and it triggers the second one- shot which, after a delay set by P2, triggers the first one-shot again. This action continues until LHD goes low PI and P2 should be set so that the chopper frequency is about 2.8 MHz. 7. The LHD, LVD Distribution Buffer This circuit, shown in Figure 31, is used to provide the necesst fanout for LHD and LVD. 8. The Logical Blanking Circuit (1469-555) The Logical Blanking (LB) circuit, shown in Figure 32, blanks out useless signals at the beginning and end of each line or field that arise 1 to differentiation. LHD triggers one- shot #1 which after a delay set by PI triggers #h for a time set by Vh. LVD triggers #2 which in turn triggers #3. The flip-flop insures that the VLB signal spans an integral number < horizontal lines. The VLB and HLB shown are effectively ORed together to form LB. The circuit board is shared with the Preview Color Area circuit. 9. The Vertical Differentiator (l^69-5 1 +5) and Logic (±K69-5h6) The Vertical Differentiator, shown in Figure 33, is used to pre horizontal outline information. The delayed video from the Ultrasonic De. Line is clamped to re-establish the DC value it lost in passing through 1 Corning delay line. The real-time video is then subtracted from the delay video using an operational amplifier. The resulting difference signal is go 55 (D Q rl rl ■ne" c o o u. z _ w N £ ,? T> ° •= C Q o Z - < E a. z o. 3 ^. M H «l Ifl * CO Ui I- o GV Figure 30. Synchronous Chopper v^~ > 56 JL Pin 2 is ground NOTE : Built on 1469-553 Universal Card INVERTERS SN7404N Figure 31. LHD. LVD Distribution Buffer 57 ID LO lO I CD CD z *r o m z ; a a. < < < - (0 rt CO UJ »- O 2 Figure 32. Logical Blanking Circuit 58 Figure 33. Vertical Differentiator Circuit 59 then amplified with a feedback triple before passing on to a Fairchild uA7llC strobed dual comparator. A T filter is used to bypass high frequency compon- ents of the difference signal. The signal enters the plus terminal of one comparator and the minus terminal of the other. The voltage dividers at the other inputs set the comparison levels. The position of the three position switch sets the strobe voltages. From Table 2, we see that the switch selects either a positive or negative single-sided threshold (up and down) or a double-sided threshold (center position). The wire ORed output is then level-shifted to standard TTL levels. The top photo in Figure 3^, shows about 16 lines of video and the cor- responding difference signal. The scene viewed was a square white card on a black background. The bottom photo shows the real-time video, the delayed video, and the difference signal over a period of almost a field. The Vertical Differentiator Logic, also shown in Figure 33, is on a l i +69-5 i +6 card. The inverted level-shifted dual comparator signal is chopped if the center terminal of the two-position switch is grounded. The chopping signals come from the Synchronous Chopper (see Figure 30). The chopping is done using CHOP for one line and CHOP for the next (timewise) so that an outline stored on the disc won't have any holes in it. The signal at common point A is the unchopped original signal while that at D is either chopped or not depending upon the two-position switch position. The signals at com- mon points B and C are the same as at D except that either the odd or the even field is blanked out. Switch inputs from the Switch Card (see Figure 29) and the common points A, B, C and D go to a decoding circuit which selects one of the four common points A through D as the output. This signal is then blanked 60 Figure 3^4. Sample Difference Signal 61 during horizontal and vertical blanking with the output of the Logical Blanking (LB) circuit (see Figure 32) before passing through the final out- put. 10. The Horizontal RC Filter Differentiator (lk69-k r jk) Next, the two horizontal differentiators will be discussed. The RC Filter Differentiator, shown in Figure 35, was built experimentally. The design criteria were (1) to duplicate a line drawing drawn on a blackboard and (2) to form the outline of scenes composed of contrasty solid colors. In the drawing, the chain composed of 01, Q2 and Q3 forms a high frequency- response differentiator. The top trace in Figure 3o shows the video input and the bottom shows the output at the collector of Q3« 0,1 and Qj+ form a derivative of lower frequency picture components and need not be used except for solid objects. The comparator after 03 is set to detect positive signal deviations while that after Q,U detects negative deviations. 0,5 and Q6 level shift the comparator output to standard TTL logic levels for use by the one- shots. 11. The Horizontal Delay Line Differentiator (1^69-536) and Logic (1^69-537) For the sake of symmetry, it was of interest to build a delay line differentiator for the horizontal derivative as well. An analysis of the use of a shorted delay line as a differentiator is given in Appendix A. The Horizontal Delay Line Differentiator with Logic is shown in Figure 37* Th e video signal is amplified by about six using the feedback amplifier made up of stages 4I through Q|6. The characteristics of a similar 62 Figure 35. Horizontal RC Filter differentiator 63 Figure 36. Sample RC Filter Differentiator Input /Output Voltages 6k Hi SJIijii in I i{Ji si I 11 Figure 37. Horizontal Delay Line Differentiator and Logic 65 amplifier are calculated in Reference [30]. Potentiometer PI adjusts the output DC level. The input stage Ql is an emitter follower with its emitter tied to the feedback path. Q2 and 03 form a complementary case ode circuit with an effective adjustable Miller feedback capacitance C, . The bandwidth of the amplifier may be varied by adjusting C . Emitter follower QJ4 serves to lower the impedance seen by the output stage 0,5-0,6. An analysis of a similar output stage is given in Reference [31]. Basically, Q5 serves as a source of current for voltages above ground and Q6 a sink for those below. If the emitter of Qj+ is at least a diode drop above ground, then Q5 is pushing cur- rent into the load. As the input voltage goes up, the voltage drop across the 91ft collector resistor reduces the bias on Q6 through D3- As the input voltage falls below ground, Q5 is turned off and 06 is turned on through D3« Q6 then serves as a current sink. This amplifier provides a high quality 10 volt peak-to-peak video signal to the delay line. The one-way delay time of the delay line was chosen by experiment to be 80 nsec. Appendix A shows that the constraint for a delay line differentiation to be close to the deriva- tive is ooT < .17 radians. This gives f H = — mJd 5- ~ 3^0 kHz. 2* 2jt x 80 x 10 ^s For frequency components higher than f , the difference between the real-time and the delayed video components essentially subtracts out the low frequency hump, but retains the higher frequency pulses and their echoes. The result of a single- sided threshold appears much like the original line drawing. For double-sided thresholds, echoes from high frequency pulses are separated on the screen from the original by a distance corresponding to 2T. The lower frequency pulses are effectively differentiated, and the resultant output takes 66 on the appearance of an outline. Q7 and Q8 form a difference circuit used ; balancing the delay line output to account for the attenuation. This is d cussed in Appendix A. P2 determines the amount of input signal that i tracted from the unbalanced differentiated video. Capacitive coupling is t here to simplify circuit design. Emitter follower Q9 drives the comparator inputs. A sample of delay line differentiation is shown in Figure 38. Tfc top line is the input video and the bottom line is the voltage at the emit: of Q9. A T filter is used on each comparator input to bypass high f reque: . P3 and Ph set the threshold levels and the 3-position switch controls the s inputs for a single- or double-sided threshold (see Table 2). The compars; output is level shifted to TTL logic levels by D5, D6 and Q10. The logic card (l469 _ 537) performs the double line correction and the signal selecti:: The correction scheme was discussed in Chapter II (see Figure 6 and Sectic: II.B.l.f). The selector circuit is identical to that discussed in connect.: with the Vertical Differentiator. The output for a given switch position u given in Table 1 and is labelled the Horizontal Logical Derivative (HID). 12. The Video Gate (lk-69-^k) with L/V Converter The Video Gate circuit is shown in Figure 39 along with a L/V Converter that was etched on the same card for economy. A similar circuit .. discussed in Reference [30]. The inverters used here are open collector inverters with 30 volt minimum breakdown voltages. The video input is pi:, and the gate input is pin 11. If the gate signal goes high (ground), ther Q2 will be turned on and the video signal will pass on to the outputs, the gate signal goes low (-5), then Q2 will be turned off, Dl and D2 will' 1 turned off and D3 will be on, thus not allowing the video to pass to the puts. 67 Figure 38. Sample Horizontal Delay Line Differentiator Input/Output Voltages 1469-554 68 n> 3> 4> +10 i> 1.5K 1.5K 75 Ql -5 -W- Dl +10 Q2 -»" aD7 1/2A 21 > o-^\^-o- 1/2A 20 > o— / ~\j— o- 1/2A 22 > 0—0^-0- ;1K 4.3K -10 D2 3.9 K 'iiDZ -5 +10 03 27 + 10 .47 ^t-n.47 27 27 i:.47 -10 -5 ^7 ■>9 NOTES 1. Ql: 2N2905A Q2: 2N3905 Q3.Q4: 2N2219A Dl - 1N995 D2.D3-1N4151 D4.D5-1N4148 2. PINS 1,2,4,6,8,10,16 are ground 3. INVERTER : SN7406N Figure 39. Video Gate with L/V Converter 69 13. The One Frame Gate The One Frame Gate, shown in Figure kO, provides a gating signal for gating the outline information onto the disc. When the "STORE OUTLINE" switch on the front panel is depressed, the Gate Outline (GO) output goes high for the duration of two fields. The resistor-capacitor circuits at the switch panel and on the card provide a one-shotted pulse to the preset ter- minal of the flip-flop when the "STORE OUTLINE" button is pushed. The 220f2 resistor was chosen to keep the steady state voltage at pin Ik equal to about -k.65 volts (logical zero). The 4.7 pfd capacitor was chosen to provide an output pulse width of about 2.5 msec. The .k"J ufd capacitor is used to sup- press coupled transients that would otherwise trigger the gate. The details of the Moore circuit design are given in Appendix B. This completes descrip- tions of the outlining circuitry. D. The Shading Circuitry The shading circuitry described below has been added or modified for the ATC - Mark II. The reader should refer back to the System Block Diagram, Figure 11, and to the Video and Control Logic Block Diagram, Figure 20, to re-orientate himself. The control signals for the shading circuitry origin- ate from the shading potentiometers located at the Control Panel shown in Figure Ik. The potentiometer terminals are wired into the Display Console Junction Box, shown in Figure 15, where they go to the Range and Width Card, shown in Figure 17. The outputs of the Range and Width Card are voltages corresponding to the potentiometer settings. These voltages labelled RS, GS, and BS (for red, green and blue shading), are wired into the Video and Control Logic Block Diagram, as shown in Figure 20, where they are shown going to the Modulators . The Modulators are really just clippers, but are referred to throughout as Modulators . 70 A A 2 d J fr c o a * 'A O CO CM L J G>-^ =o m 0) o o isi ID IO o ^3 rO IO (VJ O - r L Ej°] TSO 1/2W 3! 09 11 010 JJ on 012 J OUTLINE OUT WRITE GATE > IN NOTES : 01, 05. OS. 06 • 2N2219A 02. 04 • 2N390S 01, 02, 04, OS. 06, 09, D10, Oil • 1N4148 03 • 1N41S1 07, 08, D12 • 1N995 ALL INVERTERS • SN7406N PIN Z IS GROUND 1/2A 1 5 : 7 : e : 10 : 12 : is : 13 TO VIDEO ADDER Figure k2. The Modulator (A, B, C) and L/V Converter (D) 7* gate signal is high (~ GND), then Q2, Dl, and Q3 are reverse biased and output is at about ground. Diodes Dk through D8 serve to protect the d: should anything go amiss. The modulator for the Preview Color function i| identical except that the shading voltage X is transformed into approp- video levels. The transformation is a linear transformation with the ou1 Y given by Y = AX + B. A Fairchild uA709C operational amplifier is used to perform this operat: Potentiometer PI determines B and P2 determines A. A small nonlinearity f larger shading voltages may be introduced with break point diode D3 and potentiometer P3. This was included to simulate saturation of the disc had it been necessary. 3- The Modified Disc Read Amplifier The disc's Write, Read and Erase Amplifiers are shown in Figure- The Read Amplifier is shown modified for Class A operation. The original Read Amplifier was operated in the Class B-C mode. The modification was made to provide a suitable waveform for the Demodulator. The disc's Write and Erase Amplifiers are also shown in the Figure. These have not been n fied. The signal from the Modulator is wired to the write input. The out- line channel's Write, Read and Erase Amplifiers have not been modified. **• The Demodulator (1U69-373) The Demodulator, shown in Figure hk, is completely DC coupled frx input to output. The four input diodes drop the DC level of the signal : Is 75 5>" i H" u. 8t "1 tUJ-Qp. ■*Hfr^H .J |2 A Figure 1+3. Modified Disc Amplifier !; s*L S sL s 76 BHgr-MH S^<«^ 11 C I I I si 1 1 II ti J! ill ro ro 1 <£> fgU— vw — w vw-d J Figure 4^. The Demodulator 77 2.03 volts to ground. The level may be made very close to ground by pro- perly adjusting P2. The carrier signal is derived from the signal itself in order to obtain a high quality demodulation for both color areas and color points, as well as to compensate for disc drifts. The color areas are modu- lated at about 3 MHz while the color points are chopped at a higher frequency. The disc is synchronized to the 60 Hz line and this causes drifts in the disc speed as the line frequency changes. With the disc's speed varying in time, it would be very hard to use an external source for the carrier signal. A Fairchild jjA710C comparator is used to provide the carrier signal to a Motorola MC1596G balanced demodulator integrated circuit. This integrated circuit effectively forms the product of the input signal, f(t)cosco t and the carrier signal, sign[cosoo t]. Disregarding the DC level, and for small delays, the output is proportional to f(t)cos(co t )sign[cosoo t]. If we break sign[cosco t] into its Fourier components, we have sign[coscu t] = — [cos t - — cos3 t + — cos5od t + ...] c jt c 3 c 5 c The expression for the product then becomes [29] f(t)cos(oo t)sign[cosoo t] = - f(t) , ^f^- cos(2cu t) - Mil C os(W t) + ... (1) jt 3jt x c ' 15jt v c ' K ' which depends only on f (t) and even multiples of the chopping frequency ao. . The output from the balanced demodulator is at a collector level DC voltage and the signal polarity is opposite to that desired. Transistor Q,l inverts the signal and shifts the DC level. Two LC parallel traps are used to sup- press harmonics of the modulation frequency. The expansion (l) above shows that if filters at 2cu , ^0 , ... are used then the final output will be 78 proportional to f(t). Theoretically, then, traps set at 2au and hat wou. give us the best result. Experimentally, it was found that a trap at was needed. This trap attenuates residual chopping frequency componc that slip through the Demodulator because of the carrier delay and feed- through. The trap set at 2a> (~6MHz) removes about 80% of the ripple .. the one set at co (~3MHz) removes only ~5$>. A photograph of a sample j^H signal and the corresponding output is shown in Figure k^>. Potentiorr, PU sets the output DC level, P5 sets the blanking level and P6 adjust, amplitude. The carrier null potentiometer P3 should be adjusted for i mum of 3 MHz feedthrough when the 3 MHz trap is detuned. 5. The Video Adder (11+69-180B) The 8-input Video Adder, shown in Figure k6, is the same basic cuit as the 3-input Video Adder used in the ATC - Mark I [1], except ■■ 8 inputs. Only 6 of these inputs are used in the ATC - Mark II. This < pletes the discussion of the circuitry added to the ATC - Mark I to f the ATC - Mark II. 79 Figure 1+5 . Demodulator Waveforms 80 ATC 8- INPUT VIDEO ADDER 1469-180B + 10 / 9 r \s—°- 20 100 M ' 20v x - r T T .47 25v IN 7 > 2 i ~i n cw 1.5K -*v\*- _i«pf_ , N e > f-^ r f so.. » ? PEN PULSE IN 1 >- OUTLINE IN 2 >- DEMODULATOR IN 3 >- PREVIEW COLOR I I N4 >i=-, 1K<« 1.5K CAMERA VIDEO IN 5 16 75 PREVIEW OUTLINE IN 6 > 18 SO^h 1.6K X T 68pf * 470fl 10 K 2N3905 X 2 N 3642 820A !27pf 1N482X -47 25v IK e 1N482 22 V 10Cv*f vX^ vLx Ay 47 . A.Z GND > ■ 20w _ _ 25v NOTES 1. ALL RESISTORS 1/4 W, 5% UNLESS SPECIFIED 2. EVERY OTHER PIN FROM 1 TO 21 AND A TO Y IS GROUND. (7)75*1 USED IN GREEN CHANNEL ONLY. Figure U6. Video Adder 81 IV. THE RESULTS The ATC - Mark II as described here has been assembled and is working. It incorporates all of the features of the ATC - Mark I. The quality of the display has been upgraded, eliminating the vertical color bars. In addi- tion, the machine is capable of coloring different shades which are selected by the operator using the shading potentiometers. The shade may be selected using a "preview color area" displayed on the CRT face, or the adventuresome operator may continuously vary the shade during the coloring process until he finds the one he wants. With the light pen in the "WRITE" mode, points appearing on the screen may be varied in intensity as they are written. One difficulty encountered during this investigation affects the quality of the result of the shading circuitry. The top photo in Figure ^7 shows storage scope waveforms for the input write signal and the resulting signal out of the Demodulator. The viewing time shown is about one frame. We see that somewhere between the input and the output, a distortion takes place. The bottom photo shows the input and output waveforms of the Demodulator. We see that the unusual modulation is coming from the disc surface. Although these variations are quite visible on the display, nothing has been done here to correct the result. It is believed that this modulation arises from a non-uniform magnetic coating on the disc. Newer video discs use FM modulation schemes to avoid this problem. Other than this problem, all of the goals for the shading circuitry have been attained. The ATC - Mark II has been designed so that if the machine is going to be used in a situation in which the camera input becomes unnecessary, the camera may be safely removed. If, however, the camera input is necessary, the operator may switch between the several options that are available to 82 Figure k^ . Disc Problems 83 him by using the Switch Card. The outline may be previewed by pushing the "PREVIEW OUTLINE" button. This allows the operator to set up the exact scene as he wants it. The outline may then be stored on the disc by pushing the "STORE OUTLINE" button. After storage, the outline may be colored in as desired. In actual practice, the outlining circuitry has proved to be only marginally useful for most operators. The reason for this is that most people prefer to draw their own outlines directly on the television screen. The use of this secondary source of input does not interest most people. Regardless of this, all of the basic goals for the outlining circuitry have been met. Comments on selected circuits: (1) The Horizontal Delay Line Differentiator circuit and Logic should be improved. The design is basically correct, but it suffers from noise problems. Something to try would be to put an active filter in before ampli- fying that would have a gain G(cjo) something like that in the graph below. £(MHz) 8U The use of such a band peaking amplifier would likely be to increase the effect of the high frequency components and the resolution. This might peak the useful signal that appears to be noise with the present arrangement The arrangement of the double-line correction one-shots should also be changed. Rather than trigger a one-shot on the negative portion of the signal, delaying the original, ORing the delayed and one-shotted signal and then one-shotting the result, a more efficient circuit would result by one- shotting on the leading edge of the signal, ORing the one-shotted signal and the real-time signal and then one-shotting the result. This would do the same thing far more economically. (2) Another problem remaining is that the Vertical Differentiator cuit requires a long warm-up time. It is believed that this is due to the AGC diodes in the Corning delay line. The problem would probably disappear if these diodes were replaced with an appropriate resistor. 85 LIST OF REFERENCES Kubitz, William J., A Tricolor Cartograph , DCS Report #282, University of Illinois, September 196b. Showalter, Leonard C, Closed Circuit TV for Engineers and Technicians , H. W. Sams and Co., 1969. Hansen, Gerald L., Introduction to Solid-State Television Systems , Prentice-Hall, 1969. Glasford, Glenn M. , Fundamentals of Television Engineering , McGraw- Hill, 1955. Neuhauser, R. G. and Miller, L. D., "Beam-Landing Errors and Signal Output Uniformity of Vidicons", Journal of the SMPTE , Volume 67, March 1958. Castlebury, J. and Vine, B. H., "An Improved Vidicon Focusing-Deflection Unit", Journal of the SMPTE , Volume 68, April 1959- Neuhauser, R. G. , "Vidicon for Film Pick-up", Journal of the SMPTE , Volume 62, February 195^-. Messerschmid, Ulrich, "Recent Developments of Electronics Special Effects in Television," Journal of the SMPTE , Volume 73, June 196^. Millman, J. and Taub, H. , Pulse and Digital Circuits , McGraw-Hill 1956, Page kkj. Thornton, R. , et. al. , Handbook of Basic Transistor Circuits and Measure - ments , SEEC Volume 7, Wiley 1966, Pages 38-39- Cowles, L. , Analysis and Design of Transistor Circuits , Van Nostrand 1966, Pages 103- 10U. Millman, J. and Halkias , C, Electronic Devices and Circuits , McGraw- Hill 1967, Page 1+93. Thornton, R., et. al. , Multistage Transistor Circuits , SEEC Volume 5, Wiley I965, Pages 182-lH^ Bray, D. and Hayden-Pigg, G. , "Video Circuits for Transistor Television Cameras", Journal of the SMPTE , Volume 72, November 1963. Kaufmann, P. and Klein, J., "Flow Graph Analysis of Transistor Feedback Networks", Semiconductor Products , October 1959- Mammano, R., "Using a Dual-Polarity, Tracking Voltage Regulator", Silicon General Applications Bulletin No. 1 , May 197 1. 86 [17 [is: [i9: [20. [2i; [22: [23: [2k] [25: [26; [27: [28: [29: [30: [31] Todd, C. D., Zener and Avalanche Diodes , Wiley-Interscience 1970* Faiman, M. : Private Communication. Millman, J. and Taub, H., Pulse, Digital and Switching Wav eforms, McGraw-Hill I96 . Chase, R., Nuclear Pulse Spectrometry , McGraw-Hill I96I. Johnson, W. , Transmission Lines and Networks , McGraw-Hill 1950. Brown, R., Sharpe, R. and Hughes, W. , Lines, Waves, and Antennas , Ronald Press I96I. Lewis, I, and Wells, F., M illimicrosecond Pulse Techniques , Pergamon 1959. , "Series 100 Delay Lines", EEC Bulletin NS-100. Cherry, C, Pulses and Transients in Communication Circuits , Chapman and Hall, 19IJ9T Balabanian, N. , Bickart, T. and Seshu, S., Electrical Network Theory , Wiley, 1969. Bracewell, R. , The Fourier Transform and Its Application , McGraw-Hill 1# Hayt, W. and Kimmerly, J., Engineering Circuit Analysis , McGraw-Hill 197- Lathi, B., Signals, Systems and Communication, Wiley I965. Hayden-Pigg, G. and Bray, D., "Semiconductor Circuits for Television Video-Switching and Distribution", IEE paper 4086E, June 1963. (Published in a book called Television Engineering). Burton, P. and Willis, J., "Unusual Transistor Circuits", Wireless World , March 1958. 8 7 APPENDIX A. THE DELAY LINE DIFFERENTIATION SCHEME t For a continuous function f(t), the derivative f (t) may be written as f'(t).u. '( t >: f < t -'> T - The following describes the use of a shorted delay line to approximate the derivative by forming the difference Af(t) = f(t) - f(t-2T). This differentiation scheme is discussed in References [19] and [20]. 1. The Delay Line [19], [21], [22], [23], [2k] The lumped constant delay line used here has a 125 MHz cutoff frequency, a 90ft impedance, and a maximum DC resistance of 4.5ft for its 100 ns length. If the Fourier spectrum of the delay line input signal is mainly composed of frequencies much less than the line's cutoff frequency, then the characteris- tic impedance Z n becomes a real constant and the phase factor p becomes strictly proportional to frequency. These approximations may be made when / ^ 2 f » 1 - — i ~ 1 where f is the cutoff frequency, and f is the frequency of opera- tion. The camera's video amplifier 3db bandwidth is 7 MHz so that the video's Fourier spectrum should be small for frequencies greater than about 10 MHz. / f \ 2 With f ^ 10 MHz,l- - I ;> 0-9936 and the approximations are applicable. For \ C / f < f , the attenuation is due to the DC resistance of the line. The attenu- ation in percent is Attenuation (%) = - — ^- — xlOOfo, Z + *DC 88 and the delay line output is multiplied by a factor attenuation (% " ~ 100 For a 160 nsec round trip delay, R-^, ~ 7 ohms and a ~ .93- 2. The Model for Analysis The ideal delay line model will be used here over the entire frequer range from minus infinity to infinity for purposes of analysis. This may be done because the actual delay line behaves much like an ideal delay line over the range of frequencies that the video signal's Fourier spectm takes on. For purposes of analysis, then, the model's transfer function becomes G(co) = e , -00 < < 00 - cnaraCsUc imP e d aa= e Z Q b ~ a Constant te an m . ' 3. The Impulse Response [25], [26], [28], [29] One way of determining the response r(t) of a network to a waveform w(t) is to find the response g(t) of the network to the impulse function S(t) and convolve it with w(t). In equation form r(t) = w(t)*g(t). The impulse response g(t) can be obtained in many cases through a Fourier trans- form analysis. The Fourier transform pair that will be used here is: 5T[f(t)] = F(a)) = / f(t)e~ iCUt dt ^ -00 and . r~ [F(co)] = f(t) = ^/f( c ,) e +ia)t dco If G(a>) is the transfer function of the network, then the impulse response g(t) is given by 89 g(t) =^' 1 [l-G(a>)] = & ,3 [G(a))] because the Fourier transform of 8[t) is 1. For the ideal delay line, we find g(t) = 5 (t-T) and the response of the network to an arbitrary waveform w(t) is just r(t) = w(t)*g(t) = w(t)*s(t-T) = w(t-T) as might be expected. k. The Circuit The top drawing in Figure kQ shows the delay line differentiator cir- cuit with an input f and output v . The resistor R provides an impedance match to Z~ at the driving end of the circuit to give a reflection coefficient close to zero. The computation of v for any f is complicated to do directly because the input impedance of the line is a complicated function of time. For a line operating without overlapping reflections, the input impedance of the line is the characteristic resistance of the line Z . If the line is initially uncharged, then the computation of v is considerably simplified by using the impulse response approach because interference effects need not be accounted for. The bottom drawing in Figure k-Q shows the delay line cir- cuit with an impulse voltage & input and the impulse response g at the out- put. The input voltage impulse 5 shown will suffer an attenuation due to the resistive divider R and Z giving an effective input impulse for computation of g(t) by Z ° 5(t) R l + Z 90 f(t) R, vottiy Figure 1+8. Delay Line Circuit Short g(t) V ^ • , I Short 91 This impulse then travels down the line for a time T before encountering a short circuit with a voltage reflection coefficient p of minus one. When the impulse reappears at the sending end of the delay line, it has suffered a sign reversal with a total round trip attenuation a and delay 2T. No further reflections take place if R = Z_. The delay line 's reflected Z 1 U response to - — o(t) = g-,(t) is then R l + Z 1 Z SoO-) = p + 7 pao(t-2T). 2 R x + Z Q The total impulse response g(t) is the superposition of g-,(t) with the reflected impulse g p (t) giving g(t) = g 1 (t) + g 2 (t) Z [6(t) + pa&(t-2T)] = R l + Z 2 [8(t) - as(t-2T)] S l + Z The output v (t) for a general input f (t) will then be given by v (t) = f(t)*g(t) = o R l + Z [f(t)*8(t) - af(t)*s(t-2T)] = Z = R + Z f f ( t ) - af(t-2T)], 1 which is just the result one might expect. 5 • Corrected Difference Although the preceding analysis was symbolic, it reaffirms our hypothesis that a shorted delay line accurately forms the difference of two signals. The only snag remaining is the attenuation a. If we subtract v (t) from 92 Z (l-a)f(t), the result v (t) is R l + Z v (t) = -a r ^- r [f (t) - f(t-2T)] . K l We see that this manipulation effectively removes the unbalancing effect^ the attenuation. 6 . ' ■ ■■: of Approximation Let us define Af = f (t) - f (t-2T) t The Fourier transform of Af is: AF = ^[Af] = (l-e" 1Cu2T )F(co) = D(go)f(o)) / \ -i<^2T where D(co) - 1-e ' . This function is plotted on the complex plane in Figure 49(a). Rewriting, we find D(o)J = e (e -e J = 2ie sinooT I (| - o)T) = 2sin(o)T)e The magnitude and phase of D(o>) are seen to be |D(co) | = 2sinooT and / , \ it /D(aQ = | - cdT . We need to compare these results with those for the Fourier transform of derivative f (t). The transform is: .^"[f'(t)] = io)F(cu) = r(co)F(cu) .it where r(fo) = ico = cue . This function is plotted on the complex plane lr Figure 49(b). The magnitude and phase of F(co) are seen to be Imaginary = i Increasing Frequency Range of close Approximation 93 21 0* -> Real 2ia/T ) (a) Plot of 1-e Imaginary = i A iai -ia)2T (b) Plot of iao ^ Real Figure h$. ioo Compared with 1-e •ico2T 9^ |r(o))| = u> and /r(co) ■ |. Comparing r(u>) with D(u>), we see that we have two independent constraints the value of T for Af to approximate the derivative. The first is that must be approximately proportional to o>. This is true when the product off is small. For less than 1% error, sin coT ~ Ca> when ^ |cjdT| < 0.2*+ radians where C is a constant. The second constraint is that (| - coT) be close to | radians. For small cd, we see this to be true. Assuming that 80 is close to 90 for our purpose, we have, 8 it , /it v it 5 2 < ^ " **> < 2" This gives the constraint on T to be such that <: UTI ^ fg ~ O- 1 ? radians. This is the most confining of the two constraints so that the shorted delay line is a fair approximation to the derivative for signals composed of fre- quencies below ovr where it ^H ~ i5t" 7. Noise Considerations [20], [29] If v (t) and v (t-2T) are the noise voltages at times t and t-2T resp n n tiveiy, the delay line differentiator output noise voltage v n (t) is giver o v (t) - v (t) - v (t-2T). n n x n o If we assume that v (t) and v (t-2T) are uncorrelated and that the noise i n x n x uniformly distributed in time, then the r.m.s. noise voltage E n at time t ii 95 the same as that at any other time. The resulting r.m.s. noise voltage at the output E is o E WE + E = V2E . n n n n o We see then, that the delay line differentiation scheme increases the r.m.s. noise voltage by a factor of \I2. Assuming that |odT[ is small, A.F can be writ- ten as -iciiPT AF = (1-e )F(co) ~ ia)2TF('JD). Fourier-transforming this result, we see that Af ~ 2Tf ' (t). As T is decreased, we see that A f will decrease. As T further decreases, a point will be reached where the r.m.s. value of the noise E is comparable o to the r.m.s. value of the signal, E . Thus, a further constraint on the o system is that T be large enough to make E » E = \f 2E . s n n o o For large video s/N ratios, it is feasible to use the delay line differentia- tion scheme. 96 APPENDIX B. THE ONE FRAME GATE DESIGN The circuit and notation for the one frame gate is shown in Figure Uo of the text. The Moore circuit design (pulse input - level ou1 technique will be used here. The design diagrams are shown in Figure 50 through (f). The timing diagram is given in (g). A LVD pulse occurs one per field so that two such pulses must be spanned to form a one frame gat- state transition diagram for a one frame gate is shown in (a). The corres- ponding state transition table is given in (b). If we assign states using adjacent Gray code, a suitable assignment is: a = 00 b = 01 c = 11 d = 10. For this assignment, the state transition table with state asc ment is as shown in (c). From this table we see that GO = q r The state transition table for q, is given in (d) and that for q g is given in (e). The SO signal is used to set the flip-flop output to one with the preset input, PR. We have ( q n when O n = ° PR = J n \ v - I d when q n - J- where d stands for the "don't care" action. The "don't care" is used because if the flip-flop output is already one, then presetting it won't have any effect. For D-type flip-flops, the next state is the present . of the D input. In equation form V+l The clock for the D inputs is Logical Vertical Drive (LVD). 97 LVD SO '■ Start Outline LVD ■ Logical Vertical Drive GO : Gate Outline (a) ►♦1 q r.l q t Q" so b LVO a GO W so LVO GO a 00 01 00 b b c 01 01 11 c c d 1 11 11 10 1 d d a 1 10 10 00 1 (b) (c ) 9 > Figure 51. Performance for a Line Drawing 104 9 o •H > Figure 52. Performance for a Solid Area 105 (a) LD without Correction (b) HID with Correction ■p-i rmvo ^"5 riraiKl^ T A ^ ^ n^-^-^.^^4- - 106 discontinuities shown in the stem of the four leaf clover occur where two vertical lines are very close, so that the delay one-shot wipes out the ^H of the two lines. The zig-zag effect in the stem occurs when the leading edge of the stem was overlapped by the one-shot but the trailing edge waa not. There are also discontinuities where there should be cusps. For scenes composed exclusively of solid areas or of line drawings, other sw: settings will result in a better job of outlining, as was shown in Figures i?l and 52. It is interesting to apply the outlining circuitry to photograph;. This is shown in Figure 5k. The outlining scheme may be applied to moving scenes without difficulty because all circuitry operates in "real time". 107 (a) Video (b) LD Figure 5^. The LD for a Photograph 108 APPENDIX E. POWER SUPPLY BUSS BARS _L -25 6 -10 o +10 o +25 o o ± -5 6 o 109 APPENDIX F. PHOTOGRAPH DISPLAYING THE COLORING CAPABILITY Figure 55 shows a sample of artwork that was generated with the ATC - Mark II. Color photographs of the ATC - Mark I were published in the November/December 1969 issue of Information Display magazine. Figure 55. Photograph of Sample Artwork (Original in Color) FormAEC-427 U.S. ATOMIC ENERGY COMMISSION (6/6 ?im UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR ae 201 DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) 1. AEC REPORT NO. coo 1U69-020U 2. TITLE OUTLINING AND SHADING GENERATION FOR A COLOR TELEVISION DISPLAY 3. TYPE OF DOCUMENT (Check one): Ec| a. Scientific and technical report _] b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): Bel a. AEC's normal announcement and distribution procedures may be followed. "2 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. ~2 c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) D. F. Hanson Research Assistant Organization Department of Computer Science University of Illinois Urbana, Illinois 61801 Signature //. ?4 Po7f>c£t««~* Date June, 1972 FOR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: LJ a. AEC patent clearance has been granted by responsible AEC patent group. LJ b. Report has been sent to responsible AEC patent group for clearance. LJ c. Patent clearance not required. BLIOGRAPHIC DATA EET 1. Report No. UIUCDCS-R-72-512 Title and Subcitle OUTLINING AND SHADING GENERATION FOR A COLOR TELEVISION DISPLAY 3. Recipient's Accession No. 5- Report Date June, 1972 'i Author(s) Donald Farness Hanson 8. Performing Organization Rept. No. 5 Performing Organization Name and Address Department of Computer Science Jniversity of Illinois Jrbana, Illinois 61801 10. Project/Task/Work Unit No. US AEC AT (11-1) 1*4-69 11. Contract /Grant No. US AEC AT (11-1) 1^69 Sponsoring Organization Name and Address JS AEC Chicago Operations Office : South Cass Avenue •rgonne, Illinois 60^+39 13. Type of Report & Period Covered Thesis Research 14. 1 Supplementary Notes 1 Abstracts This report describes improvements made on the Automatic Tricolor Cartograph - ark I. The Cartograph is a self-contained system for performing the automatic Dioring of operator-designated bounded areas on a color display. It has its own borage and refresh. In the original version, the storage of colored areas was such lat striations were somewhat noticeable on the display. In addition, the only means inputting outline information (to define the bounded regions) was by means of the tght pen. Only saturated colors were possible. The improvements described here were developed to eliminate the above 3 tcomings of the original system. A demodulation scheme was developed to elimin- the striations. An input system using a television camera was developed so that .ne drawings can be input directly without using the pen. Finally, a scheme for ear writing was developed so that the 3 primaries can be varied in saturation. !7Key Words and Document Analysis. 17a. Descriptors ideo Processing Systems television Graphics -splay Systems >elay Line Differentiation Nldentifiers/Open-Ended Terms OSATI Fie Id /Group '8. ,/ailability Statement -.mited distribution jB NTIS-35 (10-70) 19. Security Class (This Report) „. . UNCLASSIFIED. 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 120 22. Price USCOMM-DC 4032B-P71 JUL $t9f# W WW JH. nam !•••■ J ■ ■ ■ ■ I H HI H ■ ■ ^^m m Rl ■ ■ ■ ■ •tf.lfolf in tan 1 P WHi HuBn SB II H raBH